FEDK71050-03-01 Issue Date：Apr,10,2015 MK71050-03 ® Bluetooth Low Energy wireless module ■Overview MK71050-03 is a Bluetooth® Low Energy (here in after LE) wireless module which is integrating ML7105C-001 Bluetooth LE SoC, E2PROM, 26MHz crystal oscillator, 2.4GHz PCB pattern antenna and passive components. It has Bluetooth® LE compliant 2.4GHz band radio communication capability. MK71050-03 is suitable for applications such as Healthcare device, Remote Controller or PC peripherals. ■Features • Bluetooth® SIG Core Spec v4.0 compliant • Radio certification MIC JAPAN(certification no:006-000238） FCC（FCC ID:2ACIJ71050-3） CE（R&TTE） • Bluetooth® Qualification（End Product、QDID:66491） ® • Integrating ML7105C-001 Bluetooth LE single mode LSI • Integrating 26MHz xtal oscillator • Integrating 128kbit EEPROM • Single power supply 1.8V to 3.6V • Operating Temperature -20 deg.C to 70 deg.C • Current Consumptions Deep Sleep Mode 0.8uA（Typ.） (with external Low Power Clock) Idle Mode 3mA （Typ.） TX mode 9mA （Typ.） RX mode 9mA （Typ.） • Dimension 10.7mm(W) x 13.6mm (L) x 1.78mm (H) • Pb Free, RoHS compliant • Product Name MK71050-03 1/23 FEDK71050-03-01 MK71050-03 A0 (1) A1 (2) A2 (3) C4 D SDA (5) Q1 C15 SCL (6) G S (8) VCC (4) GND U2 EEPROM 128Kbit WP (7) C3 VDDBAT VDDBAT VDDCORE 10uF Outside module FETGATE ■Schematics R7 R6 C2 R4 C1 GND SCL R5 SDA C5 I2C_SDA I2C_SCL VDDBAT VDDIO ANT_GND REGOUT VDDVCO VDDCORE NC VDDRF L1 ANT1 R8 C6 OUT_ANT OUT_MOD C16 C7 N.M. SWRX C8 SWTX N.M. L2 UART_RXD UART_RXD UART_TXD UART_TXD SWOUT C9 U1 ML7105C-001 PLLLPF GND (Package GND) SPICLK SPICLK SPIXCS SPIXCS SPIDOUT GPIO0 GPIO1 GPIO2 GPIO3 RESETB LPCLKIN GPIO1 GPIO2 GPIO3 RESETB LPCLKIN A1 A1 GPIO0 A0 A0 REGC EFUSE TMODE SPIDIN 10uF LPCLKBUS REGC C13 EFUSE X1 26MHz TMODE C12 XOP C11 0Ω Outside module C10 XON Outside module R1 SPIDOUT LPCLKBUS SPIDIN 2/23 FEDK71050-03-01 MK71050-03 ■Pin assignment 39 ANT_GND 2 38 ANT_GND ANT_GND 3 37 ANT_GND ANT_GND 4 36 NC NC 5 35 ANT_GND OUT_ANT 6 34 NC OUT_MOD 7 33 A1 GND 8 32 A0 31 RESETB ANT_GND 1 NC 48 47 46 45 44 43 49 GND 42 41 40 50 GND VDDCORE 9 VDDBAT 10 30 TMODE LPCLKBUS 11 29 FETGATE LPCLKIN 12 28 GPIO3/PS_CONTROL REGC 13 27 GPIO2/IRQ EFUSE 14 26 GPIO1/WAKEUP SPIDIN 15 25 GPIO0/RF_ACTIVE 51 GND 16 17 18 52 GND 19 20 TOP 21 22 23 24 VIEW 3/23 FEDK71050-03-01 MK71050-03 ■Pin definitions No 1 2 3-4 5 6 Pin Name ANT_GND NC ANT_GND NC OUT_ANT I/O --------INOUT Ana/Dig --------ANA I/O type ----------- 7 OUT_MOD INOUT ANA --- 8 9 10 GND VDDCORE VDDBAT ------- GND PWR PWR GND VCC VCC 11 12 13 14 LPCLKBUS LPCLKIN REGC EFUSE INOUT INOUT OUT --- ANA ANA ANA DIG DIRIO DIRIO DIRIO DIRIO 15 SPIDIN IN DIG 16 SPIDOUT INOUT DIG 17 SPIXCS IN DIG 18 SPICLK IN DIG 19 20 GND UART_TXD --OUT GND DIG 21 UART_RXD IN DIG 22 23 GND SDA --INOUT GND DIG 24 SCL INOUT DIG 25 GPIO0/RF_ACTIVE INOUT DIG 26 GPIO1/WAKEUP INOUT DIG 27 GPIO2/IRQ INOUT DIG 28 INOUT DIG 29 GPIO3/PS_CONTR OL FETGATE IN DIG CMOS, IN CMOS, BiDIR CMOS, IN CMOS, IN GND CMOS, OUT CMOS, IN GND CMOS, BiDIR CMOS, BiDIR CMOS, BiDIR CMOS, BiDIR CMOS, BiDIR CMOS, BiDIR --- 30 TMODE IN DIG 31 RESETB IN DIG 32 33 34 35 A0 A1 NC ANT_GND IN IN ----- ANA ANA ----- CMOS, IN CMOS, IN DIRIO DIRIO ----- Function Antenna GND（※Refer to PIN descriptions.） No connection（※Refer to PIN descriptions.） Antenna GND（※Refer to PIN descriptions.） No connection（※Refer to PIN descriptions.） Output from Antenna (to be connected to OUT_MOD by user's PCB) Output from Module (to be connected to OUT_ANT by user's PCB) GND Internally generated power supply, Power supply 1.8 to 3.6V, require 10uF capacitor. Please use this pin open. Low Power clock input REGOUT, require 10uF capacitor. Control signal for EFUSE programming, fix to GND for normal usage Data input for SPI slave Data output for SPI slave Chip select for SPI slave Clock input for SPI slave GND Data TX port for UART Data RX port for UART GND SDA data port for I2C SCL clock port for I2C GPIO inout/RF_Active GPIO inout/WAKEUP GPIO inout/IRQ GPIO inout/external switch control (Q1) (To be connected to FETGATE by user's PCB.) Gate control Pin of internal FET (To be connected to PS_CONTROL by user's PCB.) Test mode control, fix to GND for normal usage Reset, low active Analog Test Pin0 Analog Test Pin1 No connection（※Refer to PIN descriptions.） Antenna GND（※Refer to PIN descriptions.） 4/23 FEDK71050-03-01 MK71050-03 36 37-48 49-52 NC ANT_GND GND ------- ----GND ----GND No connection（※Refer to PIN descriptions.） Antenna GND（※Refer to PIN descriptions.） GND ■PIN descriptions I/O symbol IRF I Ipd IAH ISH XSH O2 B2 B2PU ： ： ： ： ： ： ： ： ： RF input output pin Digital input pin Digital input with pull-down resistor Analog High voltage input pin Low power clock input pin Low power clock oscillator pin Digital output pin with 2mA load capability Digital bidirectional pin with 2mA load capability Digital bidirectional pin with 2mA load capability and pull-up resistor ●RF, Analog signals I/O Active Level OUT_ANT IRF --- 7 OUT_MOD IRF --- 32 A0 Hi-Z IAH --- Analog test pin0 33 A1 Hi-Z IAH, --- Analog test pin1 # Pin Name 6 Status/Value at reset Function Output from Antenna (to be connected to OUT_MOD by user's PCB) Output from Module (to be connected to OUT_ANT by user's PCB) ●XO、LPXO signals # Pin Name Status/Value at reset I/O Active Level 11 LPCLKBUS 0V XSH --- Please use this pin open. 12 LPCLKIN ISH XSH, ISH --- Low power clock input # Pin Name Status/Value at reset I/O Active Level 15 SPIDIN Input I --- 16 SPIDOUT Input B2 --- SPI SLAVE Data output 17 SPIXCS Input I Low SPI SLAVE Chip Select 18 SPICLK Input I --- Function ●SPI signals Function SPI SLAVE Data input SPI SLAVE Clock ●UART signals # Pin Name Status/Value at reset I/O Active Level 20 UART_TXD Output High O2 --- UART TXD output 21 UART_RXD Input Ipd --- UART RXD input Function 5/23 FEDK71050-03-01 MK71050-03 ●I2C signals Pin Name Status/Value at reset 24 SCL 23 SDA Pin Name # I/O Active Level Input B2PU --- I2C_SCL monitor pin.Please use this pin open. Input B2PU --- I2C_SDA monitor pin. Please use this pin open. Status/Value at reset I/O Active Level Output Low B2 --- GPIO inout/RF_ACTIVE output (default: RF_ACTIVE) Input B2 --- GPIO inout/WAKEUP input (default: WAKEUP) Output High B2 --- GPIO inout/IRQ output (default: IRQ) GPIO3 Output Low /PS_CONTROL B2 --- GPIO inout/Control signal for external Switch (default: PS_CONTROL) (To be connected to FETGATE by user's PCB.) Function Function ●GPIO signals # 25 26 27 28 GPIO0 /RF_ACTIVE GPIO1 /WAKEUP GPIO2 /IRQ Function ● Miscellaneous signals # Pin Name Status/Value at reset I/O Active Level 31 RESETB Input I Low Reset input (Low = Reset) 14 EFUSE --- --- --- E-Fuse writing voltage supply(Fixed to Low) 30 TMODE Input I --- TESTMODE input (Fixed to Low) 29 FETGATE Input I --- FET gate control input (To be connected to PS_CONTROL by user's PCB.) ●Regulator signal # Pin Name Status/Value at reset I/O Active Level 9 VDDCORE --- --- --- Internally generated power supply. (Note)Don’t short this pin. 13 REGC 1.2V 出力 --- --- Pin for de-coupling capacitor, require 10uF capacitor. I/O Active Level Function ●Power supply and Ground Status/Value at reset # Pin Name Function 10 VDDBAT --- --- --- Power supply 1.8 to 3.6V,require 10uF capacitor. 8 GND --- --- --- GND 19 GND --- --- --- GND 22 GND --- --- --- GND 49-52 GND --- --- --- GND 6/23 FEDK71050-03-01 MK71050-03 ●ANT_GND signals # 1,3-4 35 37-48 Pin Name Status/Value at reset ANT_GND I/O Active Level Function --- --- --- Antenna GND pins. ANT_GND pins has to be connected to board, but not to be connected any components on board. （Note）The pins are connected to GND in the module, but please use this pins open. ●NC signals # Pin Name Status/Value at reset I/O Active Level Function 2,5 34,36 NC --- --- --- NC pins has to be connected to board, but not to be connected any components on board. Please use this pins open. ●Unused pins Followings are recommendation for unused pins. # Pin Name Recommendation OPEN(NC pins has to be connected to board, but not to be connected any components on board.) Open(ANT_GND pins has to be connected to board, but not to be connected any components on board.) 2,5,34,36 NC 1,3-4,35 37-48 ANT_GND 11 LPCLKBUS Open 14 EFUSE Fix to 0V 15 SPIDIN Fix to High 16 SPIDOUT Fix to High 17 SPIXCS Fix to High 18 SPICLK Fix to High 20 UART_TXD Open 21 UART_RXD Fix to Low (See section for operating mode) 23 SDA Open （Pull-up resistor in the module） 24 SCL Open （Pull-up resistor in the module） 25 GPIO0/RF_ACTIVE Open 26 GPIO1/WAKEUP Fix to High or Low See section for operating mode 27 GPIO2/IRQ Open 28 GPIO3/PS_CONTROL To be connected to FETGATE by user's PCB. 29 FETGATE To be connected to PS_CONTROL by user's PCB. 32 A0 Open 33 A1 Open Remarks If input pins are left open with High Impedance status, significant current consumption might be observed. All input pins have to be fixed high or low level to avoid such current consumption. 7/23 FEDK71050-03-01 MK71050-03 ■Electrical Characteristics ●Absolute Maximum Rating Item Symbol Rating Unit Power supply (*1) VDDBAT Condition –0.3 to +4.6 V Digital input voltage (*2) VDIN –0.3 to VDD+0.3 V Digital output voltage (*3) VDO Ta = −20 to +70 deg.C –0.3 to VDD+0.3 V Analog HV IO voltage (*4) VAH GND=0V –0.3 to VDD+0.3 V Digital IO load current (*2)(*3) IDO –10 to +10 mA Analog IO current (*4) IA –2 to +2 mA Power Dissipation PD T.B.D. W Storage temperature Tstg -40 to +85 deg.C – (*1) VDDBATpin (*2) IO pins with I, IPD, B2 symbol in pin definition (*3) IO pins with O2,B2 symbol in pin definition (*4) IO pins with IAH, ISH, XSH, symbol in pin definition ●Recommended Operating Conditions Item Power Supply Symbol VDD Condition Min Typ Max Unit VDDBAT pin 1.8 3.3 3.6 V –20 +25 +70 °C Ambient Temperature Ta – Rising time digital input pins tIR1 Digital input/inout pins – – 20 Ns Falling time digital input pins Load capacitance digital tIF1 Digital input/inout pins – – 20 Ns CDL Digital output/inout pins – – 20 pF –250 ppm 32.768 +250 ppm kHz 30 50 70 % 2402 – 2480 MHz -70 – -10 dBm Low Power Clock (32.768 kHz) FLPCK1 LPCLKIN pin Low Power Clock Input Duty Ratio DLPCK1 External input from LPCLKIN, LPCLKBUS pin left OPEN RF Channel frequency (*1) RF input level (*1) Frequency range FRF OUT_MOD pin PRFIN – F = 2402 + 2 x k [MHz] here k=0, 1,2,…,39. 8/23 FEDK71050-03-01 MK71050-03 ●Current consumption (Ta = 25 deg.C) Item Symbol IDD2 Condition Deep Sleep state (External Low Power Clock) Idle state IDD3 RF RX state – 9 – mA RF TX state（-6dBm） – 9 – mA RF TX state（0dBm） – 10.9 – mA IDD1 Current Consumption Min Typ Max Unit – 0.8 – uA – 3 – mA IDD4 （note）Condition:Ta=25dec.C、VDDBAT=3.3V ●DC characteristics Item Symbol Condition Min Typ (Ta = −20 to +70 deg.C) Max Unit H level Voltage Input VIH1 (*1) (*2) (*5) VDD X0.7 – VDD V L level Voltage input VIL1 (*1) (*2) (*5) 0 – VDD X0.3 V LPCLKIN pin H level Voltage Input VIH2 (*3) 1 – VDD V LPCLKIN pin L level Voltage input VIL2 (*3) 0 – 0.3 V H level Voltage Output VOH IOH = −2mA VDD × 0.75 – VDD V L level Voltage Output VOL IOL = 2mA (*4) (*5) 0 – VDD × 0.25 V (*1) (*2) (*4) (*5) – 8 – pF Input pin capacitance CIN F=1MHz (*1) IO pins with I symbol in pin definition (*2) IO pins with IPD symbol in pin definition (*3) IO pins with ISH symbol in pin definition (*4) IO pins with O2 symbol in pin definition (*5) IO pins with B2 symbol in pin definition (*4) (*5) 9/23 FEDK71050-03-01 MK71050-03 ●RF Characteristics (Ta = −20 to +70 deg.C) Item Symbol Condition Min Typ Max Unit – 0 – dBm –40 – 40 ppm TX Maxium TX power POUT 0dBm setting Centre Frequency tolerance FCERR Master Clock tolerance < 40 ppm Modulation data rate DRATE – – 1 – Mbps Modulation index FIDX – 0.45 0.50 0.55 – Bandwidth-bit rate products BT BT GFSK – 0.5 – – RX Receiver Sensitivity PSENS PER =30.8% (*1) – -85 -70 dBm Maximum input level(*2) PRXMAX PER=30.8% (*1) – – -10 dBm – dBm -80 dBm RSSI detection range PRSSIMAX Upper -50 – PRSSIMIN Lower – – (*1) PER=30.8% is corresponding to BER=0.1% (*2) Condition: Ta = 25℃、VDDHV = 3.3V ●SPI interface (Ta = −20～+70°C) Min Typ Max Unit SPICLK Clock Frequency Item Symbol FSCLK 16.384 32.768 500 kHz SPIXCS input setup time TCESU 1/Fsclk − − ms SPIXCS input hold time TCEH 1/Fsclk − − ms SPICLK high pluse width TWCKH 250 − − ns SPICLK low pluse width TWCKL 250 − − ns SPIDIN input setup time TDISU 5 − − ns SPIDIN input hold time TDIH Condition Load capacitance CL=20pF 250 − − ns SPICLK output delay time TCKOD − − 250 ns SPIDOUT output hold time TDOH 5 − − ns 300 SPIXCS output enable delay time TCEEN 0 − SPIXCS output disable delay time TCEDIS 150 − ns ns Remarks: All timing specification is defined at VDDIO x 20% and VDDIO x 80% SPIXCS input setup/hold time have to be at least 1cycle of SPICLK clock frequency Measurement point 0.8VDDIO 0.2VDDIO Measurement point 0.8VDDIO 0.2VDDIO 10/23 FEDK71050-03-01 MK71050-03 SPIXCS TCEH FSCLK TWCKL SPICLK TCESU TWCKH TDISU SPIDIN TDIH MSB IN BITS6-1 LSB IN TCKOD TCKOD TCEEN SPIDOUT MSB OUT Hi-z TCEDIS TDOH BITS6-1 LSB OUT Hi-z (*) SPIDOUT becomes Hi-Z input when SPIXCS is High.So please insert the pull-up or pull-down resister . ●UART interface (Ta = −20 to +70 deg.C) Item Baud Rate Symbol Condition Min Typ Max Unit FBAUD Load capacitance CL=20pF − 57600 − bps(Hz) 11/23 FEDK71050-03-01 MK71050-03 ●Reset operation (Ta = −20 to +70 deg.C) Symbol Condition Min Typ Max Unit RESETB propagation delay time （Power on） Item TRDL Start supplying power (VDDBAT) 20 − − ms Reset pulse width TRPLS RESETB pin 1 − − us VDD VDDBAT GND TRPLS TRDL RESETB Power on reset function Reset function from RESETB pin It is possible to reset internal circuit by asserting RESETB after power supply is on. It is possible to reset internal circuit by same way even if it is not power sequence. Internal circuit will move to normal state after oscillation circuit become stable by clock stabilizing circuit after reset function. ●Power on Item Symbol Condition Min Typ (Ta = −20 to +70 deg.C) Max Unit VDD pin rising time TPWON While power on VDD pins (VDDBAT) 0.2 1 5 ms Power off Time TPWＯＦＦ VDD pins(VDDBAT) 10 − − ms VBOOT VDD pins(VDDBAT) − − 0.3 V Initial power level TPWON VDDBAT 90% 10% VBOOT VDD GND(0V) TPWOFF 12/23 FEDK71050-03-01 MK71050-03 ■Operating mode Following 3 operating modes are available to use BACI Mode: Application mode using SPI-SLAVE interface HCI Mode: HCI mode (Bluetooth LE standard compliant) using UART interface. RAM Mode: Function extention mode downloading user program to internal memory ■Operating mode configuration Configuration of operating mode will be done by pin status shown in table below. The symbol “X“ is don’t care, it has to be used as normal function. When configure operating mode, reset has to be issued. RAM mode and Debug mode is distinguished by configuration parameter. Operating mode Pin confitions UART_RXD BLI Mode Low HCI Mode(*1) High RAM Mode X (*1)Please fix wakeup pin to low level when using in HCI mode. Please refer to ML7105C-001 data sheet and associtated documentation for more detail. 13/23 FEDK71050-03-01 MK71050-03 ■Module dimension Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 14/23 FEDK71050-03-01 MK71050-03 ■Application example 2,5,34,36 1,3-4,35,37-48 NC MK71050-03 （BACI Mode） SPIDOUT SPICLK ANT_GND SPIXCS 0Ω 6 7 32 33 SPIDIN OUT_ANT OUT_MOD A0 A1 GPIO1/WAKEUP GPIO2/IRQ GPIO0/RF_ACTIVE 16 (*1) 18 SPI Interface 17 15 26 Control Signal 27 25 HOST-CPU 12 9 VDDCORE VDD LPCLKBUS 10 Power Supply 10uF 8,19,22 13 VDDBAT RESETB GND UART_TXD UART_RXD 11 20 21 REGC 10kΩ SCL SDA 30 EFUSE (*2) Reset signal 31 10uF 14 Low Power Clock (32.768kHz) LPCLKIN GPIO3/PS_CONTROL FETGATE TMODE 24 23 28 29 49-52 (*1) SPIDOUT becomes Hi-Z input when SPIXCS is High.So please insert the pull-up or pull-down resister . (*2) Please be careful to satisfy the RESETB propagation delay time(TRDL) . And if the state of reset signal is undefined after power on reset of HOST-CPU , please insert the pull-up or pull-down resistor. 15/23 FEDK71050-03-01 MK71050-03 ■Appendix ●PCB Land Pattern Unit:mm 16/23 FEDK71050-03-01 MK71050-03 7.775mm 8.05mm ●Metal Keep-Out Area / Reference layout of RF trace line 17/23 FEDK71050-03-01 MK71050-03 ●Radio certitication MIC JAPAN(certification no:006-000238） MK71050-03 complies with MIC JAPAN radio certification.(certification no:006-000238) FCC（FCC ID: 2ACIJ71050-3） This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1)this device may not cause harmful interference, and (2)this device must accept any interference received, including interference that may cause undesired operation. The regulatory label on the final system must include the statement: “Contains FCC ID: 2ACIJ71050-3" or using electronic labeling method as documented in KDB 784748. This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. The antenna used for this transmitter must not be collocated or operating in conjunction with any other antenna or transmitter within a host device, except in accordance with FCC multi-transmitter product procedures. The final system integrator must ensure there is no instruction provided in the user manual or customer documentation indicating how to install or remove the transmitter module except such device has implemented two-ways authentication between module and the host system. OEM Responsibilities to comply with FCC Regulations This module has been certified for integration into products only by OEM integrators under the following condition: - The transmitter module must not be colocated or operating in conjunction with any other antenna or transmitter. As long as the conditions above are met, further transmitter testing will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed (for example, digital device emissions, PC peripheral requirements, etc.). IMPORTANT NOTE: In the event that any of these conditions can not be met (for example the reference trace specified in this manual, or use of a different antenna), then the FCC authorization is no longer considered valid and the FCC ID can not be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate FCC authorization. CE（R&TTE） MK71050-03 complies with the radio test requirements (EN 300 328 V1.8.1) ,which is based on the R&TTE Directive (1999/5/EC). EMC and Safety test that is required for the CE marking should be done in the final end-product. ●Bluetooth SIG Qualification(End Product) MK71050-03 is listed on the Bluetooth SIG website as qualified End Products.（QDID:66491） External MCU Applications Profiles (*) BACI L-BLE-STACK (*) BAS,BLS,DIS,HRS, HTS,IAS,LLS,TPS MK71050-03 GAP End Product （QDID：66491) BACI SMP GATT/GAP L2CAP HCI LL PHY/RF Component Tested (QDID：47641) 18/23 FEDK71050-03-01 MK71050-03 ■Caution When implementing this product to double-sided printed board,please do not implement this product for the first time reflow side.( Opposite side reflow is prohibited due to module weight. ) ・Shield case may be discoloerd ,but there is no influence to the product performance and quality. 19/23 FEDK71050-03-01 MK71050-03 ■Revision History Document No. FEDK71050-03-01 Date Apr,10,2015 Page Previous Current Edition Edition – – Description Final edition 1 20/23 FEDK71050-03-01 MK71050-03 Precautions for the Specification 1) Contents of the Specification are the information at the time of their issuance. The information contained herein is subject to change without notice. 2) LAPIS Semiconductor has used reasonable care in preparing the information included in the Specification, but LAPIS Semiconductor does not warrant that such information is error free. LAPIS Semiconductor assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 3) The technical information specified herein is intended only to show the typical functions of the Products and examples of application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this document; therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such technical information. 4) The Specification contains information related to the LAPIS Semiconductor’s copyright and technical know-how. Any use of them other than pertaining to the usage of appropriate products is not permitted. Further, the Specification, in part or in whole, may not be reprinted or reproduced and disclosed to third parties without prior consent of LAPIS Semiconductor. Precautions for the Products ●Precautions for Safety 1) The Products are designed and produced for application in ordinary electronic equipment (AV equipment, OA equipment, telecommunication equipment, home appliances, amusement equipment, etc.). 2) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems. 3) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power control systems, and submarine repeaters. 4) The Products are designed for use in a standard environment and not in any special environments. Application of the Products in a special environment can deteriorate product performance. Accordingly, verification and confirmation of product performance, prior to use, is recommended if used under the following conditions: [a] Use in various types of liquid, including water, oils, chemicals, and organic solvents [b] Use outdoors where the Products are exposed to direct sunlight, or in dusty places [c] Use in places where the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [d] Use in places where the rPoducts are exposed to static electricity or electromagnetic waves [e] Use in environment subject to strong vibration and impact. [f] Use in proximity to heat-producing components, plastic cords, or other flammable items [g] Use involving sealing or coating the Products with resin or other coating materials [h] Use of the Products in places subject to dew condensation 5) The Products might receive the radio wave interference from electronic devices such as Wireless LAN devices, Bluetooth devices, digital cordless telephone, microwave oven and so on that radiate electromagnetic wave. 6) The Products are not radiation resistant. 7) Verification and confirmation of performance characteristics of Products, after on-board mounting, is advised. 8) Confirm that operation temperature is within the specified range described in the Specification. 21/23 FEDK71050-03-01 MK71050-03 9) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can break down and malfunction due to various factors. Therefore, if product malfunctions may result in serious damage, including that to human life, sufficient fail-safe measures must be taken, including the following: [a] Installation of protection circuits or other protective devices to improve system safety [b] Installation of redundant circuits in the case of single-circuit failure 10) Failure induced under deviant condition from what defined in the Specification can not be guaranteed. 11) This product is a specification to radiate the radio wave. It is necessary to acquire the attestation of decided Radio Law of each region used to use the equipment that radiates the radio wave. Please inquire about the attestation of Radio Law that this product acquires. 12) When product safety related problems arises, please immediately inform to LAPIS Semiconductor, and consider technical counter measure. ●Precautions for Reference Circuits 1) If change is made to the constant of an external circuit, allow a sufficient margin due to variations of the characteristics of the Products and external components, including transient characteristics, as well as static characteristics. 2) The reference circuit examples, their constants, and other types of information contained herein are applicable only when the Products are used in accordance with standard methods. Therefore, if mass production is intended, sufficient consideration to external conditions must be made. ● Precaution for Electrostatic This product is Electrostatic sensitive product, which may be damaged due to Electrostatic discharge. Please take proper caution during manufacturing and storing so that voltage exceeding Product maximum rating won't be applied to the Products. Please take special care under dry condition (Grounding of human body / equipment / solder iron, isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control etc.) ● Precautions for Storage / Transportation 1) Product performance and connector mating may deteriorate if the Products are stored in the following places: [a] Where the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2 and NO2 [b] Where the temperature or humidity exceeds those recommended by LAPIS Semiconductor Temperature: 5°C to 40°C, Humidity 40% to 60% [c] Storage in direct sunshine or condensation. [d] Storage in high Electrostatic. 2) Even under LAPIS Semiconductor recommended storage condition, connector mating, mountability, and heat resistance of products over 1 year old may be degraded. 3) Store / transport cartons in the correct direction, which is indicated on a carton as a symbol, otherwise bent leads may occur due to excessive stress applied when dropping of a carton. ● Precaution for Product Label QR code printed on LAPIS Semiconductor product label is only for internal use, and please do not use at customer site. It might contain internal products information that is inconsistent with product information. ● Precaution for Disposition When disposing Products, please dispose them properly with a industry waste company. ● Prohibition Regarding Intellectual Property LAPIS Semiconductor prohibits the purchaser of the Products to exercise or use the intellectual property rights, industrial property rights, or any other rights that either belong to or are controlled by LAPIS Semiconductor, other than the right to use, 22/23 FEDK71050-03-01 MK71050-03 sell, or dispose of the Products. ● The other precautions 1) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive. For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations. 2) When providing our Products and technologies contained in the Specification to other countries, you must abide by the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act. Copyright 2015 LAPIS Semiconductor Co., Ltd. 2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan http://www.lapis-semi.com/en/ 23/23