Renesas NP75N04YLG-E2-AY N-channel power mos fet Datasheet

Preliminary Data Sheet
NP75N04YLG
R07DS1247EJ0100
Rev.1.00
Mar 02, 2015
40 V – 75 A – N-channel Power MOS FET
Application: Automotive
Description
The NP75N04YLG is N-channel MOS Field Effect Transistors designed for high current switching applications.
Features
• Super low on-state resistance
RDS(on) = 4.8 mΩ MAX. (VGS = 10 V, ID = 38 A)
RDS(on) = 8.3 mΩ MAX. (VGS = 4.5 V, ID = 38 A)
• Logic level drive type
• Gate to Source ESD protection diode built in
• Designed for automotive application and AEC-Q101 qualified
Ordering Information
Part No.
NP75N04YLG-E1-AY *1
NP75N04YLG-E2-AY *1
Note:
Lead Plating
Pure Sn (Tin)
Tape 2500 p/reel
Packing
Taping (E1 type)
Taping (E2 type)
Package
8-pin HSON
*1 Pb-free (This product does not contain Pb in the external electrode)
Absolute Maximum Ratings (TA = 25°C)
Item
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) *1
Total Power Dissipation (TC = 25°C)
Total Power Dissipation (TA = 25°C) *2
Channel Temperature
Storage Temperature
Repetitive Avalanche Current *3
Repetitive Avalanche Energy *3
Symbol
VDSS
VGSS
ID(DC)
ID(pulse)
PT1
PT2
Tch
Tstg
IAR
EAR
Ratings
40
±20
±75
±225
138
1.0
175
–55 to +175
35
123
Unit
V
V
A
A
W
W
°C
°C
A
mJ
Notes: *1 TC = 25°C, PW ≤ 10 μs, Duty Cycle ≤ 1%
*2 Mounted on glass epoxy substrate of 40 mm × 40 mm × 1.6 mmt with 4% Copper area (35 μm)
*3 Tch(peak) ≤ 150°C, RG = 25 Ω
Thermal Resistance
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance
R07DS1247EJ0100 Rev.1.00
Mar 02, 2015
Rth(ch-C)
Rth(ch-A)
1.09
150
°C/W
°C/W
Page 1 of 6
NP75N04YLG
Preliminary
Electrical Characteristics (TA = 25°C)
Item
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Threshold Voltage
Forward Transfer Admittance *1
Drain to Source On-state Resistance *1
Symbol
IDSS
IGSS
VGS(th)
| yfs |
RDS(on)
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage *1
Reverse Recovery Time
Reverse Recovery Charge
Note:
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QG
QGS
QGD
VF(S-D)
trr
MIN.
—
—
1.5
40
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TYP.
—
—
2.0
46
3.8
4.5
4300
400
250
22
17
40
11
77
20
25
0.9
34
MAX.
1
±10
2.5
—
4.8
8.3
6450
600
450
44
41
140
27
116
—
—
1.5
—
Unit
μA
μA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
Qrr
—
34
—
nC
Test Conditions
VDS = 40 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
VDS = VGS, ID = 250 μA
VDS = 5 V, ID = 38 A
VGS = 10 V, ID = 38 A
VGS = 4.5 V, ID = 38 A
VDS = 25 V
VGS = 0 V
f = 1 MHz
VDD = 20 V, ID = 38 A
VGS = 10 V
RG = 0 Ω
VDD = 32 V
VGS = 10 V
ID = 75 A
IF = 75 A, VGS = 0 V
IF = 75 A, VGS = 0 V
di/dt = 100 A/μs
*1 Pulsed test
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
PG.
VGS = 20 → 0 V
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
50 Ω
RL
Wave Form
RG
PG.
VDD
VGS
VGS
VDD
0
VGS
10%
90%
VDS
90%
ID
IAS
90%
VDS
VGS
0
BVDSS
VDS
10%
0
10%
Wave Form
VDS
VDD
Starting Tch
τ
τ = 1 μs
Duty Cycle ≤ 1%
td(on)
tr
ton
td(off)
tf
toff
TEST CIRCUIT 3 GATE CHARGE
PG.
D.U.T.
IG = 2 mA
RL
50 Ω
VDD
R07DS1247EJ0100 Rev.1.00
Mar 02, 2015
Page 2 of 6
NP75N04YLG
Preliminary
Typical Characteristics (TA = 25°C)
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
120
160
PT - Total Power Disslpation - W
dT - Percentage of Rated Power - %
DERATING FACTOR OF FORWARD BIAS SAFE
OPERATING AREA
100
80
60
40
20
0
0
25
50
75
100
125
150
140
120
100
80
60
40
20
0
175
0
25
TC - Case Temperature - °C
50
75
100
125
150
175
TC - Case Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
100
ID(Pulse) = 225 A
RDS(ON) Limited
(VGS=10 V)
=1
00
μs
Power Dissipation Limited
=1
10
PW
PW
ms
PW
Secondary Breakdown Limited
s
1
0m
=1
ID - Drain Current - A
1000
TC = 25°C
Single Pulse
0.1
0.1
1
10
100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
Rth(t) - Transient Thermal Resistance - °C/W
1000
Rth(ch-A) = 150°C/W
100
10
Rth(ch-C) = 1.09°C/W
1
0.1
Single pulse
Mounted on glass epoxy substrate of 40 mm × 40 mm × 1.6 mmt
with 4% copper area (35 μm)
0.01
100 μ
1m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
R07DS1247EJ0100 Rev.1.00
Mar 02, 2015
Page 3 of 6
NP75N04YLG
Preliminary
100
200
10
ID - Drain Curent - A
250
150
100
50
0
0.2
0.4
0.6
0.8
1.0
TA = –55°C
–25°C
25°C
75°C
125°C
175°C
1
0.1
0.01
VGS = 10 V
Pulsed
0.001
1.2
VDS = 10 V
Pulsed
0
1
2
3
4
5
VDS - Drain to Source Voltage - V
VGS - Gate to Source Voltage - V
GATE TO SOURCE THRESHOLD VOLTAGE vs.
CHANNEL TEMPERATURE
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
3
|yfs| - Forward Transfer Admittance - S
VGS(th) - Gate to Source Threshold Voltage - V
0
RDS(on) - Drain to Source On-State Resistance - mΩ
FORWARD TRANSFER CHARACTERISTICS
2
1
VDS = VGS
ID = 250 μA
0
–100
–50
0
50
100
150
200
100
TA = –55°C
–25°C
25°C
75°C
125°C
175°C
10
VDS = 5 V
Pulsed
1
0.1
1
10
100
Tch - Channel Temperature - °C
ID - Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
10
9
8
7
VGS = 10V
4.5V
6
5
4
3
2
1
0
Pulsed
1
10
100
ID - Drain Current - A
R07DS1247EJ0100 Rev.1.00
Mar 02, 2015
1000
RDS(on) - Drain to Source On-State Resistance - mΩ
ID - Drain Current - A
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
10
9
ID = 15A
38A
75A
8
7
6
5
4
3
2
1
0
Pulsed
0
5
10
15
20
VGS - Gate to Source Voltage - V
Page 4 of 6
Preliminary
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE
10
8
VGS = 10V
4.5V
7
6
5
4
3
2
ID = 38 A
Pulsed
1
0
–100
–50
0
50
100
150
1000
Coss
Crss
VGS = 0 V
f = 1 MHz
100
0.01
200
0.1
1
10
100
Tch - Channel Temperature - °C
VDS - Drain to Source Voltage - V
SWITCHING CHARACTERISTICS
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
14
35
1000
100
td(off)
td(on)
tr
10
VDD = 20 V
VGS = 10 V
RG = 0 Ω
1
0.1
tf
1
10
12
30
VDD = 32 V
20 V
8V
25
10
20
8
15
6
10
4
VGS
VDS
5
0
100
ID = 75 A
0
10
20
30
40
50
60
70
ID - Drain Current - A
QG- Gate Charge - nC
SOURCE TO DRAIN DIODE FORWARD VOLTAGE
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
100
VGS = 0 V
10
1
Pulsed
0
0.2
0.4
0.6
0.8
1.0
VF(S-D) - Source to Drain Voltage - V
R07DS1247EJ0100 Rev.1.00
Mar 02, 2015
1.2
trr - Reverse Recovery Time - ns
VGS = 10 V
0.1
2
0
80
100
1000
IF - Diode Forward Current - A
Ciss
VGS - Gate to Source Voltage - V
Ciss, Coss, Crss - Capacitance -pF
10000
9
VDS - Drain to Source Voltage - V
td(on), tr, td(off), tf - Switching Time - ns
RDS(on) - Drain to Source On-State Resistance - mΩ
NP75N04YLG
10
di/dt = 100 A/μs
VGS = 0 V
1
0.1
1
10
100
IF - Drain Current - A
Page 5 of 6
NP75N04YLG
Preliminary
Package Drawing (Unit: mm)
8-pin HSON (Mass: 0.128 g TYP.)
Renesas Code: PLSN0008KA-A
1, 2, 3 : Source
4
: Gate
5, 6, 7, 8 : Drain
Equivalent Circuit
Drain
Body
Diode
Gate
Gate
Protection
Diode
Source
Remark: Strong electric field, when exposed to this device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred.
R07DS1247EJ0100 Rev.1.00
Mar 02, 2015
Page 6 of 6
Revision History
NP75N04YLG Data Sheet
Description
Rev.
1.00
Date
Mar 02, 2015
Page
—
Summary
First Edition Issued
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