LTC2328-18 18-Bit, 1Msps, ±10.24V True Bipolar, Pseudo-Differential Input ADC with 95dB SNR Features n n n n n n n n n n n n n n n n n Description 1Msps Throughput Rate ±5LSB INL (Max) Guaranteed 18-Bit No Missing Codes Pseudo-Differential Inputs True Bipolar Input Ranges ±6.25V, ±10.24V, ±12.5V 95dB SNR (Typ) at fIN = 2kHz –111dB THD (Typ) at fIN = 2kHz Guaranteed Operation to 125°C Single 5V Supply Low Drift (20ppm/°C Max) 2.048V Internal Reference Onboard Single-Shot Capable Reference Buffer No Pipeline Delay, No Cycle Latency 1.8V to 5V I/O Voltages SPI-Compatible Serial I/O with Daisy-Chain Mode Internal Conversion Clock Power Dissipation 50mW (Typ) 16-Lead MSOP Package Applications n n n n n Programmable Logic Controllers Industrial Process Control High Speed Data Acquisition Portable or Compact Instrumentation ATE The LTC®2328-18 is a low noise, high speed 18-bit successive approximation register (SAR) ADC with pseudodifferential inputs. Operating from a single 5V supply, the LTC2328-18 has a ±10.24V true bipolar input range, making it ideal for high voltage applications which require a wide dynamic range. The LTC2328-18 achieves ±5LSB INL maximum, no missing codes at 18 bits with 95dB SNR. The LTC2328-18 has an onboard single-shot capable reference buffer and low drift (20ppm/°C max) 2.048V temperature compensated reference. The LTC2328-18 also has a high speed SPI-compatible serial interface that supports 1.8V, 2.5V, 3.3V and 5V logic while also featuring a daisy-chain mode. The fast 1Msps throughput with no cycle latency makes the LTC2328-18 ideally suited for a wide variety of high speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The LTC2328-18 dissipates only 50mW and automatically naps between conversions, leading to reduced power dissipation that scales with the sampling rate. A sleep mode is also provided to reduce the power consumption of the LTC2328-18 to 300μW for further power savings during inactive periods. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 7705765, 7961132. Typical Application 5V 1.8V TO 5V 10µF –10.24V SNR = 95.3dB THD = –113dB SINAD = 95.2dB SFDR = –115dB –20 0.1µF –40 + LT®1468 2.2µF 0 VDDLBYP OVDD VDD IN+ – LTC2328-18 IN– REF REFBUF 47µF REFIN 100nF GND CHAIN RDL/SDI SDO SCK BUSY CNV SAMPLE CLOCK 232818 TA01 AMPLITUDE (dBFS) +10.24V 32k Point FFT fS = 1Msps, fIN = 2kHz –60 –80 –100 –120 –140 –160 –180 0 100 200 300 FREQUENCY (kHz) 400 500 232818 TA01b 232818fa For more information www.linear.com/LTC2328-18 1 LTC2328-18 Absolute Maximum Ratings Pin Configuration (Notes 1, 2) TOP VIEW Supply Voltage (VDD)...................................................6V Supply Voltage (OVDD).................................................6V Supply Bypass Voltage (VDDLBYP)............................3.2V Analog Input Voltage IN+, IN–...............................................–16.5V to 16.5V REFBUF....................................................................6V REFIN ...................................................................2.8V Digital Input Voltage (Note 3)............................ (GND –0.3V) to (OVDD + 0.3V) Digital Output Voltage (Note 3)............................ (GND –0.3V) to (OVDD + 0.3V) Power Dissipation............................................... 500mW Operating Temperature Range LTC2328C................................................. 0°C to 70°C LTC2328I..............................................–40°C to 85°C LTC2328H........................................... –40°C to 125°C Storage Temperature Range................... –65°C to 150°C VDDLBYP VDD GND IN+ IN– GND REFBUF REFIN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GND OVDD SDO SCK RDL/SDI BUSY CHAIN CNV MS PACKAGE 16-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 110°C/W Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2328CMS-18#PBF LTC2328CMS-18#TRPBF 232818 16-Lead Plastic MSOP 0°C to 70°C LTC2328IMS-18#PBF LTC2328IMS-18#TRPBF 232818 16-Lead Plastic MSOP –40°C to 85°C LTC2328HMS-18#PBF LTC2328HMS-18#TRPBF 232818 16-Lead Plastic MSOP –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2 232818fa For more information www.linear.com/LTC2328-18 LTC2328-18 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VIN+ Absolute Input Range (IN+) (Note 5) l –2.5 • VREFBUF – 0.5 2.5 • VREFBUF + 0.5 V – Absolute Input Range (IN–) (Note 5) l –0.5 0.5 V VIN+ – VIN– Input Differential Voltage Range VIN = VIN+ – VIN– l –2.5 • VREFBUF 2.5 • VREFBUF IIN Analog Input Current l –7.8 4.8 CIN Analog Input Capacitance 5 pF RIN Analog Input Resistance 2.083 kΩ CMRR Input Common Mode Rejection Ratio 66 dB VIN MIN TYP fIN = 500kHz MAX UNITS V mA Converter Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN Resolution l 18 No Missing Codes l 18 TYP Integral Linearity Error Bits DNL Differential Linearity Error BZE Bipolar Zero-Scale Error 1.6 (Note 6) l Bipolar Full-Scale Error LSBRMS –5 ±1 5 LSB l –1 ±0.1 1.25 LSB (Note 7) l –30 0 30 LSB VREFBUF = 4.096V (REFBUF Overdriven) (Notes 7, 9) l –125 REFIN = 2.048V (Note 7) l –150 Bipolar Zero-Scale Error Drift FSE UNITS Bits Transition Noise INL MAX 0.01 LSB/°C 125 LSB 150 Bipolar Full-Scale Error Drift ±0.5 LSB ppm/°C Dynamic Accuracy The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 4, 8) SYMBOL PARAMETER CONDITIONS MIN TYP SINAD Signal-to-(Noise + Distortion) Ratio ±6.25V Range, fIN = 2kHz, REFIN = 1.25V l 87.6 91 dB SNR THD SFDR Signal-to-Noise Ratio Total Harmonic Distortion Spurious Free Dynamic Range UNITS ±10.24V Range, fIN = 2kHz, REFIN = 2.048V l 91 95 dB ±12.5V Range, fIN = 2kHz, REFBUF = 5V l 92 96.5 dB ±6.25V Range, fIN = 2kHz, REFIN = 1.25V l 88 91.5 dB ±10.24V Range, fIN = 2kHz, REFIN = 2.048V l 92 95 dB ±12.5V Range, fIN = 2kHz, REFBUF = 5V l 94 97 dB ±6.25V Range, fIN = 2kHz, REFIN = 1.25V l –108 –98 dB ±10.24V Range, fIN = 2kHz, REFIN = 2.048V l –111 –98 dB ±12.5V Range, fIN = 2kHz, REFBUF = 5V l –106 –96 dB ±6.25V Range, fIN = 2kHz, REFIN = 1.25V l 98 110 dB ±10.24V Range, fIN = 2kHz, REFIN = 2.048V l 98 113 dB ±12.5V Range, fIN = 2kHz, REFBUF = 5V l 96 108 dB –3dB Input Linear Bandwidth 7 Aperture Delay 500 Aperture Jitter Transient Response MAX 4 Full-Scale Step 0.5 MHz ps psRMS µs 232818fa For more information www.linear.com/LTC2328-18 3 LTC2328-18 Internal Reference Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER VREFIN Internal Reference Output Voltage CONDITIONS VREFIN Temperature Coefficient (Note 14) MIN TYP MAX UNITS 2.043 2.048 2.053 V 2 20 l REFIN Output Impedance ppm/°C 15 VREFIN Line Regulation VDD = 4.75V to 5.25V REFIN Input Voltage Range (REFIN Overdriven) (Note 5) kΩ 0.08 mV/V 1.25 2.4 V Reference Buffer Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VREFBUF Reference Buffer Output Voltage VREFIN = 2.048V l 4.091 4.096 4.101 V REFBUF Input Voltage Range (REFBUF Overdriven) (Notes 5, 9) l 2.5 5 V REFBUF Output Impedance VREFIN = 0V REFBUF Load Current VREFBUF = 5V (REFBUF Overdriven) (Notes 9, 10) VREFBUF = 5V, Nap Mode (REFBUF Overdriven) (Note 9) IREFBUF 13 kΩ 0.89 0.39 l 1.2 mA mA Digital Inputs and Digital Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER VIH High Level Input Voltage l VIL Low Level Input Voltage l IIN Digital Input Current CIN Digital Input Capacitance CONDITIONS VIN = 0V to OVDD MIN TYP MAX UNITS 0.8 • OVDD V –10 l 0.2 • OVDD V 10 μA 5 pF VOH High Level Output Voltage IO = –500µA l VOL Low Level Output Voltage IO = 500µA l OVDD – 0.2 V IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l ISOURCE Output Source Current VOUT = 0V –10 mA ISINK Output Sink Current VOUT = OVDD 10 mA –10 0.2 V 10 µA Power Requirements The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER VDD Supply Voltage OVDD Supply Voltage IVDD Supply Current IOVDD INAP ISLEEP Supply Current Nap Mode Current Sleep Mode Current PD Power Dissipation Nap Mode Sleep Mode 4 CONDITIONS 1Msps Sample Rate (IN+ = –10.24V, IN– = 0V) 1Msps Sample Rate (IN+ = IN– = 0V) 1Msps Sample Rate (CL = 20pF) Conversion Done (IVDD + IOVDD, IN+ = –10.24V, IN– = 0V) Sleep Mode (IVDD + IOVDD) 1Msps Sample Rate (IN+ = –10.24V, IN– = 0V) 1Msps Sample Rate (IN+ = IN– = 0V) Conversion Done (IVDD + IOVDD, IN+ = –10.24V, IN– = 0V) Sleep Mode (IVDD + IOVDD) MIN TYP MAX UNITS l 4.75 5 5.25 V l 1.71 5.25 V l l l l l l 14.5 10 0.4 8.4 60 72.5 50 42 0.3 16 10 225 80 50 1.1 mA mA mA mA μA mW mW mW mW 232818fa For more information www.linear.com/LTC2328-18 LTC2328-18 ADC Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL fSMPL tCONV tACQ tCYC tCNVH tBUSYLH tCNVL tQUIET tSCK tSCKH tSCKL tSSDISCK tHSDISCK PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time Time Between Conversions CNV High Time CONDITIONS MIN CNV↑ to BUSY Delay Minimum Low Time for CNV CL = 20pF l (Note 12) (Note 11) l TYP l l tACQ = tCYC – tCONV – tBUSYLH (Note 11) l l l SCK Quiet Time from CNV↑ SCK Period SCK High Time SCK Low Time l (Notes 12, 13) l l l 460 460 1 20 MAX 1 527 13 UNITS Msps ns ns µs ns ns 20 20 ns ns 10 4 4 4 ns ns ns ns ns SDI Setup Time From SCK↑ (Note 12) l SDI Hold Time From SCK↑ SCK Period in Chain Mode (Note 12) l 1 l 13.5 tHSDO SDO Data Remains Valid Delay from SCK↑ tSCKCH = tSSDISCK + tDSDO (Note 12) CL = 20pF, OVDD = 5.25V CL = 20pF, OVDD = 2.5V CL = 20pF, OVDD = 1.71V CL = 20pF (Note 11) tDSDOBUSYL SDO Data Valid Delay from BUSY↓ CL = 20pF (Note 11) l 5 ns tEN Bus Enable Time After RDL↓ (Note 12) l 16 ns tDIS Bus Relinquish Time After RDL↑ REFBUF Wakeup Time (Note 12) l 13 tSCKCH tDSDO tWAKE SDO Data Valid Delay from SCK↑ l l l l CREFBUF = 47μF, CREFIN = 100nF Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground. Note 3: When these pin voltages are taken below ground or above VDD or OVDD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above VDD or OVDD without latch-up. Note 4: VDD = 5V, OVDD = 2.5V, ±10.24V Range, REFIN = 2.048V, fSMPL = 1MHz. Note 5: Recommended operating conditions. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB 7.5 8 9.5 ns ns ns ns ns 1 200 ns ms when the output code flickers between 00 0000 0000 0000 0000 and 11 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. Note 8: All specifications in dB are referred to a full-scale ±10.24V input with REFIN = 2.048V. Note 9: When REFBUF is overdriven, the internal reference buffer must be turned off by setting REFIN = 0V. Note 10: fSMPL = 1MHz, IREFBUF varies proportionally with sample rate. Note 11: Guaranteed by design, not subject to test. Note 12: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V and OVDD = 5.25V. Note 13: tSCK of 10ns maximum allows a shift clock frequency up to 100MHz for rising edge capture. Note 14: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. 0.8 • OVDD tWIDTH 0.2 • OVDD tDELAY tDELAY 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD 50% 50% 232818 F01 Figure 1. Voltage Levels for Timing Specifications 232818fa For more information www.linear.com/LTC2328-18 5 LTC2328-18 Typical Performance Characteristics fSMPL = 1Msps, unless otherwise noted. Differential Nonlinearity vs Output Code 3.0 0.5 2.5 0.4 2.0 0.5 0 –0.5 –1.0 –1.5 0.2 2000 0.1 COUNTS DNL ERROR (LSB) 0.0 –0.1 –0.3 –2.0 500 –0.4 –2.5 0 65536 131072 196608 OUTPUT CODE –0.5 262144 0 65536 131072 196608 OUTPUT CODE 232818 G01 –60 –80 –100 –120 –70 SNR –80 90 SINAD 80 70 –140 0 100 200 300 FREQUENCY (kHz) 400 500 232818 G04 6 –90 –100 –110 –120 THD 2ND 3RD –130 –160 –180 60 232818 G03 THD, Harmonics vs Input Frequency 100 SNR, SINAD (dBFS) AMPLITUDE (dBFS) –40 CODE SNR, SINAD vs Input Frequency SNR = 95.3dB THD = –113dB SINAD = 95.2dB SFDR = –115dB –20 0 262144 232818 G02 32k Point FFT fS = 1Msps, fIN = 2kHz 0 1500 1000 –0.2 THD, HARMONICS (dBFS) INL ERROR (LSB) 1.0 σ = 1.6 2500 0.3 1.5 –3.0 DC Histogram 3000 131090 131091 131092 131093 131094 131095 131096 131097 131098 131099 131100 131101 131102 131103 Integral Nonlinearity vs Output Code TA = 25°C, VDD = 5V, OVDD = 2.5V, REFIN = 2.048V, 0 25 50 75 100 125 150 175 200 FREQUENCY (kHz) –140 0 25 50 75 100 125 150 175 200 FREQUENCY (kHz) 232818 G06 232818 G05 232818fa For more information www.linear.com/LTC2328-18 LTC2328-18 Typical Performance Characteristics TA = 25°C, VDD = 5V, OVDD = 2.5V, REFIN = 2.048V, fSMPL = 1Msps, unless otherwise noted. 96.0 SNR, SINAD vs Input Level, fIN = 2kHz SNR, SINAD vs Temperature, fIN = 2kHz –105 98 THD, Harmonics vs Temperature, fIN = 2kHz 95.5 SNR SINAD 95.0 THD, HARMONICS (dBFS) SNR, SINAD (dBFS) MAGNITUDE (dBFS) 97 96 SNR 95 SINAD 94 –110 –115 THD 3RD 2ND –120 93 94.5 –40 –30 –10 –20 INPUT LEVEL (dB) 92 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 0 232818 G07 232818 G09 232818 G08 INL/DNL vs Temperature Full-Scale Error vs Temperature Offset Error vs Temperature 2.0 20 5 1.5 15 4 0.5 0 –0.5 –1.0 MAX INL MAX DNL MIN DNL MIN INL 3 10 OFFSET ERROR (LSB) 1.0 FULL-SCALE ERROR (LSB) INL, DNL ERROR (LSB) –125 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 5 0 –5 –10 2 1 0 –1 –2 –3 –1.5 –15 –4 –2.0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) –20 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) –5 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 232818 G10 232818 G11 232818 G12 232818fa For more information www.linear.com/LTC2328-18 7 LTC2328-18 Typical Performance Characteristics TA = 25°C, VDD = 5V, OVDD = 2.5V, REFIN = 2.048V, fSMPL = 1Msps, unless otherwise noted. Supply Current vs Temperature 120 VDD (IN+ = IN– = 0V) 8 80 CURRENT (µA) 100 CURRENT (mA) 10 6 4 2.0484 INTERNAL REFERENCE OUTPUT (V) 12 Internal Reference Output vs Temperature Sleep Current vs Temperature 60 40 20 2 OVDD 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 2.0481 2.0480 2.0479 2.0478 2.0477 2.0476 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 232818 G15 CMRR vs Input Frequency 80 30 75 25 Supply Current vs Sampling Rate 16 14 SUPPLY CURRENT (mA) 35 70 CMRR (dB) NUMBER OF PARTS Internal Reference Output Temperature Coefficient Distribution 20 15 65 60 10 5 55 0 50 6 8 10 232818 G16 8 2.0482 232818 G14 232818 G13 –10 –8 –6 –4 –2 0 2 4 DRIFT (ppm/°C) 2.0483 12 10 8 100 200 300 FREQUENCY (kHz) 400 500 232818 G17 VDD (IN+ = 0V) 6 4 2 0 VDD (IN+ = –10.24V) 0 VDD (IN+ = 10.24V) OVDD 0 100 200 300 400 500 600 700 800 900 1000 SAMPLING FREQUENCY (kHz) 232818 G18 232818fa For more information www.linear.com/LTC2328-18 LTC2328-18 Pin Functions VDDLBYP (Pin 1): 2.5V Supply Bypass Pin. The voltage on this pin is generated via an onboard regulator off of VDD. This pin must be bypassed with a 2.2μF ceramic capacitor to GND. VDD (Pin 2): 5V Power Supply. The range of VDD is 4.75V to 5.25V. Bypass VDD to GND with a 10µF ceramic capacitor. GND (Pins 3, 6 and 16): Ground. IN+ (Pin 4): Analog Input. IN+ operates differential with respect to IN– with an IN+-IN– range of –2.5 • VREFBUF to 2.5 • VREFBUF. IN– (Pin 5): Analog Ground Sense. IN– has an input range of ±500mV with respect to GND and must be tied to the ground plane or a remote sense. REFBUF (Pin 7): Reference Buffer Output. An onboard buffer nominally outputs 4.096V to this pin. This pin is referred to GND and should be decoupled closely to the pin with a 47μF ceramic capacitor. The internal buffer driving this pin may be disabled by grounding its input at REFIN. Once the buffer is disabled, an external reference may overdrive this pin in the range of 2.5V to 5V. A resistive load greater than 500kΩ can be placed on the reference buffer output. REFIN (Pin 8): Reference Output/Reference Buffer Input. An onboard bandgap reference nominally outputs 2.048V at this pin. Bypass this pin with a 100nF ceramic capacitor to GND to limit the reference output noise. If more accuracy is desired, this pin may be overdriven by an external reference in the range of 1.25V to 2.4V. CHAIN (Pin 10): Chain Mode Selector Pin. When low, the LTC2328-18 operates in normal mode and the RDL/SDI input pin functions to enable or disable SDO. When high, the LTC2328-18 operates in chain mode and the RDL/SDI pin functions as SDI, the daisy-chain serial data input. Logic levels are determined by OVDD. BUSY (Pin 11): BUSY Indicator. Goes high at the start of a new conversion and returns low when the conversion has finished. Logic levels are determined by OVDD. RDL/SDI (Pin 12): When CHAIN is low, the part is in normal mode and the pin is treated as a bus enabling input. When CHAIN is high, the part is in chain mode and the pin is treated as a serial data input pin where data from another ADC in the daisy chain is input. Logic levels are determined by OVDD. SCK (Pin 13): Serial Data Clock Input. When SDO is enabled, the conversion result or daisy-chain data from another ADC is shifted out on the rising edges of this clock MSB first. Logic levels are determined by OVDD. SDO (Pin 14): Serial Data Output. The conversion result or daisy-chain data is output on this pin on each rising edge of SCK MSB first. The output data is in 2’s complement format. Logic levels are determined by OVDD. OVDD (Pin 15): I/O Interface Digital Power. The range of OVDD is 1.71V to 5.25V. This supply is nominally set to the same supply as the host interface (1.8V, 2.5V, 3.3V, or 5V). Bypass OVDD to GND with a 0.1μF capacitor. CNV (Pin 9): Convert Input. A rising edge on this input powers up the part and initiates a new conversion. Logic levels are determined by OVDD. 232818fa For more information www.linear.com/LTC2328-18 9 LTC2328-18 Functional Block Diagram VDD = 5V VDDLBYP = 2.5V REFIN = 1.25V TO 2.4V REFBUF = 2.5V TO 5V OVDD = 1.8V TO 5V LDO 15k 2.048V REFERENCE 2× REFERENCE BUFFER IN+ IN– 4R R 0.63× BUFFER R 4R + 18-BIT SAMPLING ADC – SPI PORT CONTROL LOGIC CHAIN SDO RDL/SDI SCK CNV BUSY GND 232818 BD01 Timing Diagram Conversion Timing Using the Serial Interface CHAIN, RDL/SDI = 0 CNV BUSY CONVERT NAP AND ACQUIRE SCK SDO 10 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 232818 TD01 232818fa For more information www.linear.com/LTC2328-18 LTC2328-18 Applications Information Overview Transfer Function The LTC2328-18 is a low noise, high speed 18-bit successive approximation register (SAR) ADC with pseudodifferential inputs. Operating from a single 5V supply, the LTC2328-18 has a ±10.24V true bipolar input range, making it ideal for high voltage applications which require a wide dynamic range. The LTC2328-18 achieves ±5LSB INL maximum, no missing codes at 18-bits and 95dB SNR. The LTC2328-18 digitizes the full-scale voltage of ±2.5 • REFBUF into 218 levels, resulting in an LSB size of 78µV with REFBUF = 4.096V. The ideal transfer function is shown in Figure 2. The output data is in 2’s complement format. The analog inputs of the LTC2328-18 are pseudo-differential in order to reduce any unwanted signal that is common to both inputs. The analog inputs can be modeled by the equivalent circuit shown in Figure 3. The back-to-back diodes at the inputs form clamps that provide ESD protection. Each input drives a resistor divider network that has 011...111 OUTPUT CODE (TWO’S COMPLEMENT) The LTC2328-18 has an onboard single-shot capable reference buffer and low drift (20ppm/°C max) 2.048V temperature-compensated reference. The LTC2328-18 also has a high speed SPI-compatible serial interface that supports 1.8V, 2.5V, 3.3V and 5V logic while also featuring a daisy-chain mode. The fast 1Msps throughput with no cycle latency makes the LTC2328-18 ideally suited for a wide variety of high speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The LTC2328-18 dissipates only 50mW and automatically naps between conversions, leading to reduced power dissipation that scales with the sampling rate. A sleep mode is also provided to reduce the power consumption of the LTC2328-18 to 300μW for further power savings during inactive periods. Analog Input BIPOLAR ZERO 011...110 000...001 000...000 111...111 111...110 100...001 FSR = +FS – –FS 1LSB = FSR/262144 100...000 –FSR/2 Converter Operation The LTC2328-18 operates in two phases. During the acquisition phase, the charge redistribution capacitor D/A converter (CDAC) is connected to the outputs of the resistor divider networks that pins IN+ and IN– drive to sample an attenuated and level-shifted version of the pseudo-differential analog input voltage as shown in Figure 3. A rising edge on the CNV pin initiates a conversion. During the conversion phase, the 18-bit CDAC is sequenced through a successive approximation algorithm, effectively comparing the sampled input with binary-weighted fractions of the reference voltage (e.g. VREFBUF/2, VREFBUF/4 … VREFBUF/262144) using the differential comparator. At the end of conversion, the CDAC output approximates the sampled analog input. The ADC control logic then prepares the 18-bit digital output code for serial transfer. –1 0V 1 FSR/2 – 1LSB LSB LSB INPUT VOLTAGE (V) 232818 F02 Figure 2. LTC2328-18 Transfer Function 0.63 • VREFBUF IN+ 1.6k 400Ω RON 50Ω CIN 45pF 0.63 • VREFBUF IN– 1.6k 400Ω RON 50Ω CIN 45pF BIAS VOLTAGE 232818 F03 Figure 3. The Equivalent Circuit for the Differential Analog Input of the LTC2328-18 232818fa For more information www.linear.com/LTC2328-18 11 LTC2328-18 Applications Information a total impedance of 2kΩ. The resistor divider network attenuates and level shifts the ±2.5 • REFBUF true bipolar signal swing of each input to the 0-REFBUF input signal swing of the ADC core. In the acquisition phase, 45pF (CIN) from the sampling CDAC in series with approximately 50Ω (RON) from the on-resistance of the sampling switch is connected to the output of the resistor divider network. Any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the ADC core and resistor divider network. The IN+ input of the ADC core draws a current spike while charging the CIN capacitor during acquisition. Input Drive Circuits A low impedance source can directly drive the high impedance input of the LTC2328-18 without gain error. A high impedance source should be buffered to minimize settling time during acquisition and to optimize the distortion performance of the ADC. Minimizing settling time is important even for DC inputs, because the ADC input draws a current spike when entering acquisition. For best performance, a buffer amplifier should be used to drive the analog input of the LTC2328-18. The amplifier provides low output impedance to minimize gain error and allows for fast settling of the analog signal during the acquisition phase. It also provides isolation between the signal source and the ADC input which draws a small current spike during acquisition. Input Filtering The noise and distortion of the buffer amplifier and signal source must be considered since they add to the ADC noise and distortion. Noisy input signals should be filtered prior to the buffer amplifier input with a low bandwidth filter to minimize noise. The simple 1-pole RC lowpass filter shown in Figure 4 is sufficient for many applications. The input resistor divider network, sampling switch onresistance (RON) and the sample capacitor (CIN) form a second lowpass filter that limits the input bandwidth to the ADC core to 7MHz. A buffer amplifier with a low noise density must be selected to minimize the degradation of the SNR over this bandwidth. 12 50Ω ±10.24V + 66nF LT1468 BW = 48kHz IN+ – LTC2328-18 IN– 232818 F04 Figure 4. Input Signal Chain High quality capacitors and resistors should be used in the RC filters since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. Pseudo-Differential Bipolar Inputs For most applications, we recommend the low power LT1468 ADC driver to drive the LTC2328-18. With a low noise density of 5nV/√Hz and a low supply current of 3mA, the LT1468 is flexible and may be configured to convert signals of various amplitudes to the ±10.24V input range of the LTC2328-18. To achieve the full distortion performance of the LTC2328‑18, a low distortion single-ended signal source driven through the LT1468 configured as a unity-gain buffer as shown in Figure 4 can be used to get the full data sheet THD specification of –111dB. ADC Reference There are three ways of providing the ADC reference. The first is to use both the internal reference and reference buffer. The second is to externally overdrive the internal reference and use the internal reference buffer. The third is to disable the internal reference buffer and overdrive the REFBUF pin from an external source. The following tables give examples of these cases and the resulting bipolar input ranges. 232818fa For more information www.linear.com/LTC2328-18 LTC2328-18 Applications Information External Reference with Internal Buffer Table 1. Internal Reference with Internal Buffer REFIN REFBUF BIPOLAR INPUT RANGE 2.048V 4.096V ±10.24V Table 2. External Reference with Internal Buffer REFIN (OVERDRIVE) REFBUF BIPOLAR INPUT RANGE 1.25V (Min) 2.5V ±6.25V 2.048V 4.096V ±10.24V 2.4V (Max) 4.8V ±12V Table 3. External Reference Unbuffered REFIN REFBUF (OVERDRIVE) BIPOLAR INPUT RANGE 0V 2.5V (Min) ±6.25V 0V 5V (Max) ±12.5V Internal Reference with Internal Buffer The LTC2328-18 has an on-chip, low noise, low drift (20ppm/°C max), temperature compensated bandgap reference that is factory trimmed to 2.048V. It is internally connected to a reference buffer as shown in Figure 5a and is available at REFIN (Pin 8). REFIN should be bypassed to GND with a 100nF ceramic capacitor to minimize noise. The reference buffer gains the REFIN voltage by 2 to 4.096V at REFBUF (Pin 7). So the input range is ±10.24V, as shown in Table 1. Bypass REFBUF to GND with at least a 47μF ceramic capacitor (X7R, 10V, 1210 size) to compensate the reference buffer and minimize noise. 15k REFIN BANDGAP REFERENCE 100nF REFBUF REFERENCE BUFFER 6.5k 47µF 6.5k GND LTC2328-18 232818 F05a Figure 5a. LTC2328-18 Internal Reference Circuit If more accuracy and/or lower drift is desired, REFIN can be easily overdriven by an external reference since a 15k resistor is in series with the reference as shown in Figure 5b. REFIN can be overdriven in the range from 1.25V to 2.4V. The resulting voltage at REFBUF will be 2 • REFIN. So the input range is ±5 • REFIN, as shown in Table 2. Linear Technology offers a portfolio of high performance references designed to meet the needs of many applications. With its small size, low power, and high accuracy, the LTC6655-2.048 is well suited for use with the LTC2328-18 when overdriving the internal reference. The LTC6655-2.048 offers 0.025% (max) initial accuracy and 2ppm/°C (max) temperature coefficient for high precision applications. The LTC6655-2.048 is fully specified over the H-grade temperature range and complements the extended temperature range of the LTC2328-18 up to 125°C. Bypassing the LTC6655-2.048 with a 2.7μF to 100µF ceramic capacitor close to the REFIN pin is recommended. External Reference Unbuffered The internal reference buffer can also be overdriven from 2.5V to 5V with an external reference at REFBUF as shown in Figure 5c. So the input ranges are ±6.25V to ±12.5V, respectively, as shown in Table 3. To do so, REFIN must be grounded to disable the reference buffer. A 13k resistor loads the REFBUF pin when the reference buffer is disabled. To maximize the input signal swing and corresponding SNR, the LTC6655-5 is recommended when overdriving REFBUF. The LTC6655-5 offers the same small size, accuracy, drift and extended temperature range as the LTC6655-2.048. By using this 5V reference, an SNR of 97dB can be achieved. Bypassing the LTC6655-5 with a 47μF ceramic capacitor (X5R, 0805 size) close to the REFBUF pin is recommended. The REFBUF pin of the LTC2328-18 draws a charge (QCONV) from the external bypass capacitor during each conversion cycle. If the internal reference buffer is overdriven, the external reference must provide all of this charge with a DC current equivalent to IREFBUF = QCONV/tCYC. Thus, the DC current draw of REFBUF depends on the sampling 232818fa For more information www.linear.com/LTC2328-18 13 LTC2328-18 Applications Information 15k REFIN BANDGAP REFERENCE 2.7µF REFBUF REFERENCE BUFFER Internal Reference Buffer Transient Response 47µF LTC6655-2.048 6.5k 6.5k LTC2328-18 GND 232818 F05b Figure5b. Using the LTC6655-2.048 as an External Reference 15k REFIN REFBUF of the output code. If an external reference is used to overdrive REFBUF, the fast settling LTC6655-5 reference is recommended. BANDGAP REFERENCE REFERENCE BUFFER 6.5k For optimum transient performance, the internal reference buffer should be used. The internal reference buffer uses a proprietary design that results in an output voltage change at REFBUF of less than 1LSB when responding to a sudden burst of conversions. This makes the internal reference buffer of the LTC2328-18 truly single-shot capable since the first sample taken after idling will yield the same result as a sample taken after the transient response of the internal reference buffer has settled. Figure 7 shows the transient responses of the LTC2328-18 with the internal reference buffer and with the internal reference buffer overdriven by the LTC6655-5, both with a bypass capacitance of 47μF. 47µF LTC6655-5 6.5k 2 LTC2328-18 232818 F05c Figure 5c. Overdriving REFBUF Using the LTC6655-5 rate and output code. In applications where a burst of samples is taken after idling for long periods, as shown in Figure 6, IREFBUF quickly goes from approximately 390µA to a maximum of 1.2mA for REFBUF = 5V at 1Msps. This step in DC current draw triggers a transient response in the external reference that must be considered since any deviation in the voltage at REFBUF will affect the accuracy DEVIATION FROM FINAL VALUE (LSB) GND INTERNAL REFERENCE BUFFER 0 –2 EXTERNAL SOURCE ON REFBUF –4 –6 –8 0 100 200 300 400 500 600 700 800 900 1000 TIME (µs) 232818 F07 Figure 7. Transient Response of the LTC2328-18 CNV IDLE PERIOD IDLE PERIOD 232818 F06 Figure 6. CNV Waveform Showing Burst Sampling 14 232818fa For more information www.linear.com/LTC2328-18 LTC2328-18 Applications Information Dynamic Performance Total Harmonic Distortion (THD) Fast Fourier Transform (FFT) techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. The LTC2328-18 provides guaranteed tested limits for both AC distortion and noise measurements. Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency (fSMPL/2). THD is expressed as: Signal-to-Noise and Distortion Ratio (SINAD) where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. The signal-to-noise and distortion ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 8 shows that the LTC2328-18 achieves a typical SINAD of 95dB at a 1MHz sampling rate with a 2kHz input. Signal-to-Noise Ratio (SNR) The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Figure 8 shows that the LTC2328-18 achieves a typical SNR of 95dB at a 1MHz sampling rate with a 2kHz input. 0 SNR = 95.3dB THD = –113dB SINAD = 95.2dB SFDR = –115dB –20 AMPLITUDE (dBFS) –40 –60 –80 –100 –120 V22 + V32 + V42 +…+ VN THD= 20log V1 2 Power Considerations The LTC2328-18 provides two power supply pins: the 5V power supply (VDD), and the digital input/output interface power supply (OVDD). The flexible OVDD supply allows the LTC2328-18 to communicate with any digital logic operating between 1.8V and 5V, including 2.5V and 3.3V systems. Power Supply Sequencing The LTC2328-18 does not have any specific power supply sequencing requirements. Care should be taken to adhere to the maximum voltage relationships described in the Absolute Maximum Ratings section. The LTC2328‑18 has a power-on reset (POR) circuit that will reset the LTC2328-18 at initial power-up or whenever the power supply voltage drops below 2V. Once the supply voltage reenters the nominal supply voltage range, the POR will re-initialize the ADC. No conversions should be initiated until 200μs after a POR event to ensure the re-initialization period has ended. Any conversions initiated before this time will produce invalid results. –140 –160 –180 Timing and Control 0 100 200 300 FREQUENCY (kHz) 400 500 232818 F08 Figure 8. 32k Point FFT of the LTC2328-18 CNV Timing The LTC2328-18 conversion is controlled by CNV. A rising edge on CNV will start a conversion and power up the LTC2328-18. Once a conversion has been initiated, 232818fa For more information www.linear.com/LTC2328-18 15 LTC2328-18 Applications Information Internal Conversion Clock 14 VDD (IN+ = –10.24V) 12 10 VDD (IN+ = 0V) 8 6 4 VDD (IN+ = 10.24V) 2 0 OVDD 0 100 200 300 400 500 600 700 800 900 1000 SAMPLING FREQUENCY (kHz) 232818 G18 The LTC2328-18 has an internal clock that is trimmed to achieve a maximum conversion time of 527ns. With a minimum acquisition time of 460ns, throughput performance of 1Msps is guaranteed without any external adjustments. Auto Nap Mode The LTC2328-18 automatically enters nap mode after a conversion has been completed and completely powers up once a new conversion is initiated on the rising edge of CNV. During nap mode, only the ADC core powers down and all other circuits remain active. During nap, data from the last conversion can be clocked out. The auto nap mode feature will reduce the power dissipation of the LTC2328-18 as the sampling frequency is reduced. Since full power is consumed only during a conversion, the ADC core of the LTC2328-18 remains powered down for a larger fraction of the conversion cycle (tCYC) at lower sample rates, thereby reducing the average power dissipation which scales with the sampling rate as shown in Figure 9. Sleep Mode The auto nap mode feature provides limited power savings since only the ADC core powers down. To obtain greater power savings, the LTC2328-18 provides a sleep mode. During sleep mode, the entire part is powered down except for a small standby current resulting in a power dissipation of 300μW. To enter sleep mode, toggle CNV twice with no intervening rising edge on SCK. The part will enter sleep mode on the falling edge of BUSY from 16 16 SUPPLY CURRENT (mA) it cannot be restarted until the conversion is complete. For optimum performance, CNV should be driven by a clean low jitter signal. Converter status is indicated by the BUSY output which remains high while the conversion is in progress. To ensure that no errors occur in the digitized results, any additional transitions on CNV should occur within 40ns from the start of the conversion or after the conversion has been completed. Once the conversion has completed, the LTC2328-18 powers down and begins acquiring the input signal. Figure 9. Power Supply Current of the LTC2328-18 Versus Sampling Rate the last conversion initiated. Once in sleep mode, a rising edge on SCK will wake the part up. Upon emerging from sleep mode, wait tWAKE ms before initiating a conversion to allow the reference and reference buffer to wake up and charge the bypass capacitors at REFIN and REFBUF. (Refer to the Timing Diagrams section for more detailed timing information about sleep mode.) Digital Interface The LTC2328-18 has a serial digital interface. The flexible OVDD supply allows the LTC2328-18 to communicate with any digital logic operating between 1.8V and 5V, including 2.5V and 3.3V systems. The serial output data is clocked out on the SDO pin when an external clock is applied to the SCK pin if SDO is enabled. Clocking out the data after the conversion will yield the best performance. With a shift clock frequency of at least 40MHz, a 1Msps throughput is still achieved. The serial output data changes state on the rising edge of SCK and can be captured on the falling edge or next rising edge of SCK. D17 remains valid till the first rising edge of SCK. The serial interface on the LTC2328-18 is simple and straightforward to use. The following sections describe the operation of the LTC2328-18. Several modes are provided depending on whether a single or multiple ADCs share the SPI bus or are daisy-chained. 232818fa For more information www.linear.com/LTC2328-18 LTC2328-18 Timing Diagrams Normal Mode, Single Device shows a single LTC2328-18 operated in normal mode with CHAIN and RDL/SDI tied to ground. With RDL/SDI grounded, SDO is enabled and the MSB(D17) of the new conversion data is available at the falling edge of BUSY. This is the simplest way to operate the LTC2328-18. When CHAIN = 0, the LTC2328-18 operates in normal mode. In normal mode, RDL/SDI enables or disables the serial data output pin SDO. If RDL/SDI is high, SDO is in high impedance. If RDL/SDI is low, SDO is driven. Figure 10 CONVERT DIGITAL HOST CNV CHAIN LTC2328-18 RDL/SDI BUSY IRQ SDO DATA IN SCK CLK NAP AND ACQUIRE CONVERT NAP AND ACQUIRE CHAIN = 0 RDL/SDI = 0 CONVERT tCYC tCNVH tCNVL CNV tACQ = tCYC – tCONV – tBUSYLH tCONV BUSY tACQ tSCK tBUSYLH tSCKH 1 SCK 2 3 tHSDO tDSDOBUSYL SDO tQUIET 16 17 18 tSCKL tDSDO D17 D16 D15 D1 D0 232818 F10 Figure 10. Using a Single LTC2328-18 in Normal Mode 232818fa For more information www.linear.com/LTC2328-18 17 LTC2328-18 Timing Diagrams Normal Mode, Multiple Devices be used to allow only one LTC2328-18 to drive SDO at a time in order to avoid bus conflicts. As shown in Figure 11, the RDL/SDI inputs idle high and are individually brought low to read data out of each device between conversions. When RDL/SDI is brought low, the MSB of the selected device is output onto SDO. Figure 11 shows multiple LTC2328-18 devices operating in normal mode (CHAIN = 0) sharing CNV, SCK and SDO. By sharing CNV, SCK and SDO, the number of required signals to operate multiple ADCs in parallel is reduced. Since SDO is shared, the RDL/SDI input of each ADC must RDLB RDLA CONVERT CNV CHAIN CNV CHAIN LTC2328-18 SDO B BUSY LTC2328-18 IRQ DIGITAL HOST SDO A RDL/SDI RDL/SDI SCK SCK DATA IN CLK NAP AND ACQUIRE CONVERT CONVERT NAP AND ACQUIRE CHAIN = 0 tCNVL CNV tCONV BUSY tBUSYLH RDL/SDIA RDL/SDIB tSCK 1 SCK 2 tSCKH 3 16 17 18 tHSDO SDO Hi-Z D17A D16A D15A 19 20 21 34 35 36 tSCKL tDSDO tEN tQUIET tDIS D1A D0A Hi-Z D17B D16B D15B D1B D0B Hi-Z 232818 F11 Figure 11. Normal Mode with Multiple Devices Sharing CNV, SCK, and SDO 18 232818fa For more information www.linear.com/LTC2328-18 LTC2328-18 Timing Diagrams Chain Mode, Multiple Devices may limit the number of lines needed to interface to a large number of converters. Figure 12 shows an example with two daisy-chained devices. The MSB of converter A will appear at SDO of converter B after 18 SCK cycles. The MSB of converter A is clocked in at the SDI/RDL pin of converter B on the rising edge of the first SCK. When CHAIN = OVDD, the LTC2328-18 operates in chain mode. In chain mode, SDO is always enabled and RDL/SDI serves as the serial data input pin (SDI) where daisy-chain data output from another ADC can be input. This is useful for applications where hardware constraints CONVERT OVDD OVDD CNV CHAIN CNV CHAIN LTC2328-18 RDL/SDI RDL/SDI SDO A DIGITAL HOST LTC2328-18 IRQ BUSY B DATA IN SDO SCK SCK CLK NAP AND ACQUIRE CONVERT CONVERT NAP AND ACQUIRE CHAIN = OVDD RDL/SDIA = 0 tCYC tCNVL CNV BUSY tCONV tBUSYLH tSCKCH SCK 1 2 3 16 17 tSSDISCK 18 19 20 34 35 36 tSCKL tHSDO tHSDISCK SDOA = RDL/SDIB tQUIET tSCKH tDSDO D17A D16A D15A D1A D0A D17B D16B D15B D1B D0B tDSDOBUSYL SDOB D17A D16A D1A D0A 232818 F12 Figure 12. Chain Mode Timing Diagram 232818fa For more information www.linear.com/LTC2328-18 19 LTC2328-18 Timing Diagrams Sleep Mode To enter sleep mode, toggle CNV twice with no intervening rising edge on SCK as shown in Figure 13. The part will enter sleep mode on the falling edge of BUSY from CHAIN = DON’T CARE RDL/SDI = DON’T CARE NAP AND ACQUIRE CONVERT the last conversion initiated. Once in sleep mode, a rising edge on SCK will wake the part up. Upon emerging from sleep mode, wait tWAKE ms before initiating a conversion to allow the reference and reference buffer to wake up and charge the bypass capacitors at REFIN and REFBUF. CONVERT SLEEP NAP AND ACQUIRE CONVERT tWAKE tCNVH CNV tCONV BUSY tCONV tBUSYLH SCK CHAIN = DON’T CARE RDL/SDI = DON’T CARE CONVERT SLEEP NAP AND ACQUIRE CONVERT tWAKE tCNVH CNV tCONV BUSY tBUSYLH SCK 232818 F13 Figure 13. Sleep Mode Timing Diagram 20 232818fa For more information www.linear.com/LTC2328-18 LTC2328-18 Board Layout To obtain the best performance from the LTC2328-18 a printed circuit board (PCB) is recommended. Layout for the PCB should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the ADC. Recommended Layout The following is an example of a recommended PCB layout. A single solid ground plane is used. Bypass capacitors to the supplies are placed as close as possible to the supply pins. Low impedance common returns for these bypass capacitors are essential to the low noise operation of the ADC. The analog input traces are screened by ground. For more details and information refer to DC1908, the evaluation kit for the LTC2328-18. Partial Top Silkscreen Partial Layer 1 Component Side 232818fa For more information www.linear.com/LTC2328-18 21 LTC2328-18 Board Layout Partial Layer 2 Ground Plane Partial Layer 3 Power Plane Partial Layer 4 Bottom Layer 22 232818fa For more information www.linear.com/LTC2328-18 LTC2328-18 Board Layout Partial Schematic of Demo Board 232818fa For more information www.linear.com/LTC2328-18 23 LTC2328-18 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package 16-Lead Plastic MSOP (Reference LTC DWG # 05-08-1669 Rev A) 0.889 ±0.127 (.035 ±.005) 5.10 (.201) MIN 3.20 – 3.45 (.126 – .136) 4.039 ±0.102 (.159 ±.004) (NOTE 3) 0.50 (.0197) BSC 0.305 ±0.038 (.0120 ±.0015) TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) DETAIL “A” 3.00 ±0.102 (.118 ±.004) (NOTE 4) 4.90 ±0.152 (.193 ±.006) 0° – 6° TYP 0.280 ±0.076 (.011 ±.003) REF 16151413121110 9 GAUGE PLANE 0.53 ±0.152 (.021 ±.006) DETAIL “A” 0.18 (.007) SEATING PLANE 1.10 (.043) MAX 1234567 8 0.17 – 0.27 (.007 – .011) TYP 0.50 NOTE: (.0197) 1. DIMENSIONS IN MILLIMETER/(INCH) BSC 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 24 0.86 (.034) REF 0.1016 ±0.0508 (.004 ±.002) MSOP (MS16) 0213 REV A 232818fa For more information www.linear.com/LTC2328-18 LTC2328-18 Revision History REV DATE DESCRIPTION A 07/14 Updated minimum values for SINAD/SNR for ±6.25V range PAGE NUMBER 3 Updated Figure 9 16 232818fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of itsinformation circuits as described herein will not infringe on existing patent rights. For more www.linear.com/LTC2328-18 25 LTC2328-18 Typical Application LT1468 Configured to Buffer a ±10.24V Single-Ended Signal Into the LTC2328-18 15V 7 LT1468 5V +10.24V 3 + –10.24V IN+ 6 2 – VDD LTC2328-18 IN – REFBUF 4 REFIN 47µF –15V 100nF 232818 TA02 Related Parts PART NUMBER DESCRIPTION COMMENTS ADCs LTC2338-18/LTC2337-18/ 18-Bit, 1Msps/500ksps/250ksps Serial, LTC2336-18 Low Power ADC 5V Supply, ±10.24V True Bipolar, Differential Input, 100dB SNR, Pin-Compatible Family in MSOP-16 Package LTC2378-20/LTC2377-20/ 20-Bit, 1Msps/500ksps/250ksps Serial, LTC2376-20 Low Power ADC 2.5V Supply, Differential Input, 0.5ppm INL, ±5V Input Range, DGC, PinCompatible Family in MSOP-16 and 4mm × 3 mm DFN-16 Packages LTC2379-18/LTC2378-18/ 18-Bit, 1.6Msps/1Msps/500ksps/250ksps LTC2377-18/LTC2376-18 Serial, Low Power ADC 2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range, DGC, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages LTC2380-16/LTC2378-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps LTC2377-16/LTC2376-16 Serial, Low Power ADC 2.5V Supply, Differential Input, 96.2dB SNR, ±5V Input Range, DGC, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages LTC2369-18/LTC2368-18/ 18-Bit, 1.6Msps/1Msps/500ksps/250ksps LTC2367-18/LTC2364-18 Serial, Low Power ADC 2.5V Supply, Pseudo-Differential Unipolar Input, 96.5dB SNR, 0V to 5V Input Range, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages LTC2370-16/LTC2368-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps LTC2367-16/LTC2364-16 Serial, Low Power ADC 2.5V Supply, Pseudo-Differential Unipolar Input, 94dB SNR, 0V to 5V Input Range, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages LTC2389-18/LTC2389-16 18-Bit/16-Bit, 2.5Msps Parallel/Serial ADC 5V Supply, Pin-Configurable Input Range, 99.8dB/96dB SNR, Parallel or Serial I/O 7mm × 7mm LQFP-48 and QFN-48 Packages LTC1609 ±10V, Configurable Unipolar/Bipolar Input, Single 5V Supply, SSOP-28 and SO-20 Packages 16-Bit, 200ksps Serial ADC DACs LTC2756/LTC2757 18-Bit, Single Serial/Parallel IOUT SoftSpan™ ±1LSB INL/DNL, Software-Selectable Ranges, SSOP-28/7mm × 7mm LQFP-48 DAC Package LTC2641 16-Bit/14-Bit/12-Bit Single Serial VOUT DAC ±1LSB INL /DNL, MSOP-8 Package, 0V to 5V Output LTC2630 12-Bit/10-Bit/8-Bit Single VOUT DACs ±1LSB INL (12 Bits), Internal Reference, SC70 6-Pin Package LTC6655 Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.2V, 2ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package LTC6652 Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.2V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package References Amplifiers LT1468/LT1469 Single/Dual 90MHz, 22V/μs, 16-Bit Accurate Low Input Offset: 75μV/125µV Op Amp 26 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC2328-18 ● ● (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC2328-18 232818fa LT 0714 REV A• PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2014