Product Folder Order Now Support & Community Tools & Software Technical Documents ISO1211, ISO1212 SLLSEY7 – JUNE 2017 ISO121x Isolated 24-V Digital Input Receivers for Digital Input Modules 1 Features • • • • • • • • • • Compliant to IEC 61131-2; Type 1, 2, 3 Characteristics Accurate Current Limit: 2.2 mA to 2.47 mA Eliminates the Need for Secondary (Field-Side) Power Supply Input Tolerance With Reverse Polarity Protection: ±60 V Compatible With High-Side or Low-Side Switches High Data Rates: Up to 4 Mbps High Transient Immunity: ±70-kV/µs CMTI Wide Control-Side Supply Voltage (VCC1) Range: 2.25 V to 5.5 V Wide Ambient Temperature Range: –40°C to +125°C Available Channel Options – Single-Channel ISO1211, Narrow-Body SOIC-8 – Dual-Channel ISO1212, SSOP-16 Safety-Related Certifications: – VDE V 0884-10 Basic Insulation – UL 1577 Recognition, 2500-VRMS Insulation – CSA Component Acceptance Notice 5A and IEC 60950-1 Certification – CQC Certification per GB4943.1-2011 – TUV Certifications per EN 60950-1 and EN 601010-1 – All Certifications are Planned 3 Description The ISO1211 and ISO1212 are isolated 24-V digital input receivers, compliant to IEC 61131-2 Type 1, 2, and 3 characteristics, suitable for programmable logic controllers (PLCs) and motor-control digital input modules. Unlike traditional optocoupler solutions with discrete, imprecise current limiting circuitry, the ISO121x devices provide a simple, low-power solution with an accurate current limit to enable the design of compact and high-density I/O modules. These devices do not require field-side power supply and are compatible with high-side or low-side switches. The ISO121x devices operate over the supply range of 2.25 V to 5.5 V, supporting 2.5-V, 3.3-V, and 5-V controllers. A ±60-V input tolerance with reverse polarity protection helps ensure the input pins are protected in case of faults with negligible reverse current. These devices support up to 4-Mbps data rates passing a minimum pulse width of 150 ns for high-speed operation. The ISO1211 device is ideal for designs that require channel-to-channel isolation and the ISO1212 device is ideal for multichannel space-constrained designs. Device Information(1) PART NUMBER 2 Applications • Motor Drive I/O and Position Feedback CNC Control Data Acquisition Binary Input Modules PACKAGE BODY SIZE (NOM) ISO1211 SOIC (8) 4.90 mm × 3.91 mm ISO1212 SSOP (16) 4.90 mm × 3.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Programmable Logic Controller (PLC) Input Modules – Digital Input Modules – Mixed I/O Modules Application Diagram Field PLC Digital Input Module Sensor Switch PLC ISO1211 RTHR 24 V SENSE VCC1 IN OUT VCC RSENSE Power Supply 0V FGND GND1 Host Controller GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. ADVANCE INFORMATION • 1 • • • • ISO1211, ISO1212 SLLSEY7 – JUNE 2017 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... ADVANCE INFORMATION 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 7 7.2 Functional Block Diagram ....................................... 14 7.3 Feature Description................................................. 14 7.4 Device Functional Modes........................................ 15 1 1 1 2 3 5 8 Application and Implementation ........................ 16 8.1 Application Information............................................ 16 8.2 Typical Application .................................................. 16 9 Power Supply Recommendations...................... 21 10 Layout................................................................... 22 Absolute Maximum Ratings ...................................... 5 ESD Ratings ............................................................ 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 6 Power Ratings........................................................... 6 Insulation Specifications............................................ 7 Safety-Related Certifications..................................... 8 Safety Limiting Values .............................................. 9 Electrical Characteristics—DC Specification........... 10 Switching Characteristics—AC Specification ........ 11 Insulation Characteristics Curves ......................... 12 Typical Characteristics .......................................... 13 10.1 Layout Guidelines ................................................. 22 10.2 Layout Example .................................................... 22 11 Device and Documentation Support ................. 23 11.1 11.2 11.3 11.4 11.5 11.6 11.7 Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resource............................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 23 23 23 23 23 23 23 12 Mechanical, Packaging, and Orderable Information ........................................................... 23 Detailed Description ............................................ 14 7.1 Overview ................................................................. 14 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 2 DATE REVISION NOTES June 2017 * Initial release. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 ISO1211, ISO1212 www.ti.com SLLSEY7 – JUNE 2017 5 Pin Configuration and Functions 8 SENSE EN 2 7 IN OUT 3 6 FGND GND1 4 5 SUB ILIM 1 Basic Isolation VCC1 ADVANCE INFORMATION ISO1211 D Package 8-Pin SOIC Top View Pin Functions PIN NO. NAME I/O DESCRIPTION 1 VCC1 — Power supply, side 1 2 EN I Output enable. The output pin on side 1 is enabled when the EN pin is high or open. The output pin on side 1 is in the high-impedance state when the EN pin is low. In noisy applications, tie the EN pin to VCC1. 3 OUT O Channel output 4 GND1 — Ground connection for VCC1 5 SUB — Internal connection to input chip substrate. Leave this pin unconnected on the board. 6 FGND — Field-side ground 7 IN I Field-side current input 8 SENSE I Field-side voltage sense Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 3 ISO1211, ISO1212 SLLSEY7 – JUNE 2017 www.ti.com ISO1212 DBQ Package 16-Pin SSOP Top View 1 16 SENSE1 VCC1 2 15 IN1 EN 3 14 FGND1 OUT1 4 13 SUB1 Basic Isolation ILIM GND1 Functional Isolation 12 SUB2 5 NC 6 11 SENSE2 NC 7 10 IN2 GND1 8 9 FGND2 ILIM ADVANCE INFORMATION OUT2 Pin Functions PIN I/O Description NO. NAME 1 GND1 — Ground connection for VCC1 2 VCC1 — Power supply, side 1 3 EN I Output enable. The output pins on side 1 are enabled when the EN pin is high or open. The output pins on side 1 are in the high-impedance state when the EN pin is low. In noisy applications, tie the EN pin to VCC1 4 OUT1 O Channel 1 output 5 OUT2 O Channel 2 output NC — Not connected 8 GND1 — Ground connection for VCC1 9 FGND2 — Field-side ground, channel 2 10 IN2 I Field-side current input, channel 2 11 SENSE2 I Field-side voltage sense, channel 2 12 SUB2 — Internal connection to input chip 2 substrate. Leave this pin unconnected on the board. 13 SUB1 — Internal connection to input chip 1 substrate. Leave this pin unconnected on the board. 14 FGND1 — Field-side ground, channel 1 15 IN1 I Field-side current input, channel 1 16 SENSE1 I Field-side voltage sense, channel 1 6 7 4 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 ISO1211, ISO1212 www.ti.com SLLSEY7 – JUNE 2017 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VCC1 Supply voltage, control side –0.5 6 V VOUTx, VEN Voltage on OUTx pins and EN pin –0.5 VCC1 + 0.5 (2) V IO Output current on OUTx pins –15 15 mA VINx, VSENSEx Voltage on IN and SENSE pins –60 60 V V(ISO,FUNC) Functional isolation between channels in ISO1212 on the field side –60 60 V TJ Junction temperature –40 150 °C Tstg Storage temperature –65 150 °C (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Maximum voltage must not exceed 6 V. ADVANCE INFORMATION (1) 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) UNIT ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101 (2) V ±1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions MIN MAX UNIT VCC1 Supply voltage input side 2.25 5.5 V VINx, VSENSEx Voltage on INx and SENSEx pins –60 60 V IOH High-level output current from OUTx pin IOL Low-level output current into OUTx pin VCC1 = 5 V –4 VCC1 = 3.3 V –3 VCC1 = 2.5 V –2 mA VCC1 = 5 V 4 VCC1 = 3.3 V 3 VCC1 = 2.5 V 2 tUI Minimum pulse width at SENSEx pins 150 TA Ambient temperature –40 ns 125 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 mA °C 5 ISO1211, ISO1212 SLLSEY7 – JUNE 2017 www.ti.com 6.4 Thermal Information THERMAL METRIC (1) ISO1211 ISO1212 D (SOIC) DBQ (SSOP) 8 PINS 16 PINS UNIT RθJA Junction-to-ambient thermal resistance 146.1 116.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 63.1 56.5 °C/W RθJB Junction-to-board thermal resistance 80 64.7 °C/W ΨJT Junction-to-top characterization parameter 9.6 27.9 °C/W ΨJB Junction-to-board characterization parameter 79 64.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Power Ratings PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 450 mW 20 mW ISO1211 ADVANCE INFORMATION PD Maximum power dissipation (both sides) VSENSE = 60 V, VCC1 = 5.5 V, RSENSE = 200 Ω, RTHR = 0 Ω, TJ = 150°C PD1 Maximum power dissipation output side VCC1 = 5.5 V, CL = 15 pF, Input 2-MHz 50% dutycycle square wave at SENSE pin, TJ = 150°C PD2 Maximum power dissipation input side VSENSE = 60 V, VCC1 = 5.5 V, RSENSE = 200 Ω, RTHR = 0 Ω, TJ = 150°C 430 mW VSENSEx = 60 V, VCC1 = 5.5 V, RSENSE = 200 Ω, RTHR = 0 Ω, TJ = 150°C 900 mW 40 mW 860 mW ISO1212 PD Maximum power dissipation (both sides) PD1 Maximum power dissipation output side VCC1 = 5.5 V, CL = 15 pF, Input 2-MHz 50% dutycycle square wave at SENSEx pins, TJ = 150°C PD2 Maximum power dissipation input side VSENSEx = 60 V, VCC1 = 5.5 V, RSENSE = 200 Ω, RTHR = 0 Ω, TJ = 150°C 6 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 ISO1211, ISO1212 www.ti.com SLLSEY7 – JUNE 2017 6.6 Insulation Specifications PARAMETER SPECIFICATION TEST CONDITIONS D-8 DBQ-16 UNIT External clearance (1) Shortest terminal-to-terminal distance through air 4 3.7 mm CPG External Creepage (1) Shortest terminal-to-terminal distance across the package surface 4 3.7 µm DTI Distance through the insulation Minimum internal gap (internal clearance) 10.5 10.5 µm CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 > 600 V Material Group According to IEC 60664-1 Overvoltage category DIN V VDE 0884-10 (VDE V 0884-10): 2016-12 VIORM Maximum repetitive peak isolation voltage VIOWM Maximum isolation working voltage I I Rated mains voltage ≤ 150 VRMS I-IV I-IV Rated mains voltage ≤ 300 VRMS I-III I-III AC voltage (bipolar) 566 566 VPK AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test 400 400 VRMS DC voltage 566 566 VDC 3600 3600 VPK VPK (2) VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification), t= 1 s (100% production) VIOSM Maximum surge isolation voltage (3) Test method per IEC 60065, 1.2/50 µs waveform, VTEST = 1.3 × VIOTM = 5200 VPK (qualification) 4000 4000 Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 680 VPK, tm = 10 s <5 <5 Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM = 906 VPK, tm = 10 s <5 <5 Method b1: At routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s; Vpd(m) = 1.875 × VIORM = 1062 VPK, tm = 10 s <5 <5 Apparent charge (4) qpd Barrier capacitance, input to output (5) CIO Insulation resistance, input to output (5) RIO VIO = 0.4 × sin (2 πft), f = 1 MHz pC 440 560 VIO = 500 V, TA = 25°C > 1012 > 1012 VIO = 500 V, 100°C ≤ TA ≤ 125 °C > 1011 > 1011 9 9 VIO = 500 V at TS = 150 °C > 10 ADVANCE INFORMATION CLR fF Ω > 10 Pollution degree 2 2 Climatic category 40/125/21 40/125/21 2500 2500 UL 1577 VISO (1) (2) (3) (4) (5) Withstand isolation voltage VTEST = VISO = 2500 VRMS, t = 60 s (qualification); VTEST = 1.2 × VISO = 3000 VRMS, t = 1 s (100% production) VRMS Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. Apparent charge is electrical discharge caused by a partial discharge (pd). All pins on each side of the barrier tied together creating a two-terminal device Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 7 ISO1211, ISO1212 SLLSEY7 – JUNE 2017 www.ti.com 6.7 Safety-Related Certifications VDE Plan to certify according to DIN V VDE V 0884-10 (VDE V 0884-10):200612 and DIN EN 61010-1 (VDE 0411-1):2011-07 CSA UL Plan to certify under CSA Component Acceptance Notice 5A and IEC 60950-1 CQC TUV Plan to certify according to UL 1577 Component Recognition Program Plan to certify according to GB4943.1-2011 Plan to certify according to EN 61010-1:2010 (3rd Ed) and EN 609501:2006/A11:2009/A1:2010/ A12:2011/A2:2013 2500 VRMS Basic insulation per EN 61010-1:2010 (3rd Ed) up to working voltage Basic Insulation, Altitude of 300 VRMS, ≤ 5000 m, Tropical 2500 VRMS Basic insulation Climate, per EN 60950400 VRMS maximum 1:2006/A11:2009/A1:2010/ working voltage A12:2011/A2:2013 up to working voltage of 370 VRMS Basic Insulation, Maximum Transient Isolation Voltage, 3600 VPK, Maximum Repetitive Peak Isolation Voltage, 566 VPK, Maximum Surge Isolation Voltage, 4000 VPK 370 VRMS Basic Insulation working voltage per CSA 60950-1-07+A1 + A2 and IEC 60950-1 2nd Ed. + A1 + A2 Single protection, 2500 VRMS Certification planned Certification planned Certification planned Certification planned Certification planned ADVANCE INFORMATION 8 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 ISO1211, ISO1212 www.ti.com SLLSEY7 – JUNE 2017 6.8 Safety Limiting Values Safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ISO1211 IS Safety input current - field side PS Safety input, output, or total power TS Maximum safety temperature 310 RθJA = 146.1°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 1 237 RθJA = 146.1°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 1 155 RθJA = 146.1°C/W, VI = 24 V, TJ = 150°C, TA = 25°C, see Figure 1 35 RθJA = 146.1°C/W, VI = 36 V, TJ = 150°C, TA = 25°C, see Figure 1 23 RθJA = 146.1°C/W, VI = 60 V, TJ = 150°C, TA = 25°C, see Figure 1 14 RθJA = 146.1°C/W, TJ = 150°C, TA = 25°C, see Figure 2 855 mW 150 °C mA mA ISO1212 IS IS Safety input, output, or supply current - side 1 Safety input current - field side PS Safety input, output, or total power TS Maximum safety temperature (1) RθJA = 116.9°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 3 389 RθJA= 116.9°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 3 297 RθJA = 116.9°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 3 194 RθJA = 116.9°C/W, VI = 24 V, TJ = 150°C, TA = 25°C, see Figure 3 44 RθJA= 116.9°C/W, VI = 36 V, TJ = 150°C, TA = 25°C, see Figure 3 29 RθJA = 116.9°C/W, VI = 60 V, TJ = 150°C, TA = 25°C, see Figure 3 17 RθJA = 116.9°C/W, TJ = 150°C, TA = 25°C, see Figure 4 mA mA 1070 mW 150 °C The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 9 ADVANCE INFORMATION Safety input, output, or supply current - side 1 IS RθJA = 146.1°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 1 ISO1211, ISO1212 SLLSEY7 – JUNE 2017 www.ti.com 6.9 Electrical Characteristics—DC Specification (Over recommended operating conditions unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC1 VOLTAGE SUPPLY VIT+ (UVLO1) Positive-going UVLO threshold voltage (VCC1) VIT– (UVLO1) Negative-going UVLO threshold (VCC1) 2.25 1.7 VHYS (UVLO1) UVLO threshold hysteresis (VCC1) VCC1 supply quiescent current ICC1 V 0.2 ISO1211 EN = VCC1 ISO1212 V V 0.6 1 1.2 1.9 mA LOGIC I/O ADVANCE INFORMATION VIT+ (EN) Positive-going input logic threshold voltage for EN pin 0.7 × VCC1 VIT– (EN) Negative-going input logic threshold voltage for EN pin VHYS(EN) Input hysteresis voltage for EN pin IIH Low-level input leakage at EN pin EN = GND1 VOH High-level output voltage on OUTx VCC1 = 4.5 V; IOH = –4 mA VCC1 = 3 V; IOH = –3 mA VCC1= 2.25 V; IOH = –2 mA VOL Low-level output voltage on OUTx VCC1 = 4.5 V; IOH = 4 mA VCC1 = 3 V; IOH = 3 mA VCC1= 2.25 V ; IOH = 2 mA 0.3 × VCC1 V V 0.1 × VCC1 V –10 μA VCC1 – 0.4 V 0.4 V 2.47 mA CURRENT LIMIT I(INx+SENSEx), Typical sum of current drawn from IN and SENSE pins across temperature TYP RTHR = 0 Ω, RSENSE = 562 Ω, VSENSE = 24 V, –40°C < TA < 125°C 2.2 RTHR = 0 Ω, RSENSE = 562 Ω ± 1%; –60 V < VSENSE < 0 V I(INx+SENSEx) Sum of current drawn from IN and SENSE pins –0.1 RTHR = 0 Ω, RSENSE = 562 Ω ± 1%; 5 V < VSENSE < VIL 1.9 2.5 RTHR = 0 Ω, RSENSE = 562 Ω ± 1%; VIL < VSENSE < 30 V 2.05 2.75 RTHR = 0 Ω, RSENSE = 562 Ω ± 1%; 30 V < VSENSE < 36 V 2.1 2.83 RTHR = 0 Ω, RSENSE = 562 Ω ± 1%; 36 V < VSENSE < 60 V (1) 2.1 3.1 mA RTHR = 0 Ω, RSENSE = 200 Ω ± 1%; –60 V < VSENSE < 0 V (1) (2) 10 µA –0.1 µA RTHR = 0 Ω, RSENSE = 200 Ω ± 1%; 5 V < VSENSE < VIL 5.3 6.8 RTHR = 0 Ω, RSENSE = 200 Ω ± 1%; VIL < VSENSE < 36 V (2) 5.5 7 RTHR = 0 Ω, RSENSE = 200 Ω ± 1%; 36 V < VSENSE < 60 V (2) 5.5 7.3 mA Thermal considerations constrain operation with RSENSE = 562 Ω. For ISO1211, operation all the way to VSENSE = 60 V, and TA = 125°C is possible. For ISO1212, operation up to TA = 125°C and VSENSE = 36 V is possible. For operation beyond VSENSE = 36 V, TA must be derated at 0.8°C/V below 125°C. Thermal considerations constrain operation with RSENSE = 200 Ω. For ISO1211, operation up to to VSENSE = 30 V, and TA = 118°C is possible. For operation beyond VSENSE = 30 V, TA must be derated at 1.1°C/V below 118°C. For ISO1212, operation up to TA = 100°C and VSENSE = 30 V is possible. For operation beyond VSENSE = 30 V, TA must be derated at 1.8°C/V below 100°C. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 ISO1211, ISO1212 www.ti.com SLLSEY7 – JUNE 2017 Electrical Characteristics—DC Specification (continued) (Over recommended operating conditions unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOLTAGE TRANSITION THRESHOLD ON FIELD SIDE VIL VIH VHYS Low level threshold voltage at module input (including RTHR) for output high High level threshold voltage at module input (including RTHR) for output low Threshold voltage hysteresis at module input RSENSE = 562 Ω, RTHR = 0 Ω 6.5 RSENSE = 562 Ω, RTHR = 1 kΩ 8.7 RSENSE = 562 Ω, RTHR = 4 kΩ 15.2 V RSENSE = 562 Ω, RTHR = 0 Ω 8.55 RSENSE = 562 Ω, RTHR = 1 kΩ 10.95 RSENSE = 562 Ω, RTHR = 4 kΩ 18.25 RSENSE = 562 Ω, RTHR = 0 Ω 1 RSENSE = 562 Ω, RTHR = 1 kΩ 1 RSENSE = 562 Ω, RTHR = 4 kΩ 1 V V 6.10 Switching Characteristics—AC Specification PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tr, tf Output signal rise and fall time, OUTx pins tPLH Propagation delay time for low to high transition 140 ns tPHL Propagation delay time for high to low transition 15 ns tsk(p) Pulse skew |tPHL - tPLH| 130 ns CLOAD = 15 pF 18-VP-P clock signal on IN pin with 125-ns rise and fall time, RTHR = 0 Ω 3 ns tUI Minimum pulse width 150 tPHZ Disable propagation delay, highto-high impedance output 17 40 ns tPLZ Disable propagation delay, lowto-high impedance output 17 40 ns tPZH Enable propagation delay, high impedance-to-high output 3 8.5 µs tPZL Enable propagation delay, high impedance-to-low output 17 40 ns CMTI Common mode transient immunity 25 ns 70 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 kV/µ s 11 ADVANCE INFORMATION (Over recommended operating conditions unless otherwise noted). ISO1211, ISO1212 SLLSEY7 – JUNE 2017 www.ti.com 6.11 Insulation Characteristics Curves 900 350 VCC1 = 2.75 V VCC1 = 3.6 V VCC1 = 5.5 V VINx = 24 V VINx = 36 V VINx = 60 V 250 800 Safety Limiting Power (mW) Safety Limiting Current (mA) 300 200 150 100 50 600 500 400 300 200 100 0 0 0 50 100 150 Ambient Temperature (qC) 0 200 50 D001 100 150 Ambient Temperature (qC) 200 D002 Figure 2. Thermal Derating Curve for Safety Limiting Power per VDE for D-8 Package ADVANCE INFORMATION Figure 1. Thermal Derating Curve for Safety Limiting Current per VDE for D-8 Package 450 1200 350 300 Safety Limiting Power (mW) VCC1 = 2.75 V VCC1 = 3.6 V VCC1 = 5.5 V VINx = 24 V VINx = 36 V VINx = 60 V 400 Safety Limiting Current (mA) 700 250 200 150 100 1000 800 600 400 200 50 0 0 0 50 100 150 Ambient Temperature (qC) 200 Figure 3. Thermal Derating Curve for Safety Limiting Current per VDE for DBQ-16 Package 12 0 D003 50 100 150 Ambient Temperature (qC) 200 D004 Figure 4. Thermal Derating Curve for Safety Limiting Power per VDE for DBQ-16 Package Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 ISO1211, ISO1212 www.ti.com SLLSEY7 – JUNE 2017 6.12 Typical Characteristics 3 2.75 40qC 25qC 2.5 85qC 105qC 115qC 125qC 2.25 2.75 Input Current (mA) 1.75 1.5 1.25 1 40qC 25qC 85qC 105qC 115qC 125qC 0.75 0.5 0.25 2.5 2.25 0 0 5 10 RSENSE = 562 Ω 15 20 Input Voltage (V) 25 2 30 30 -30 -10 RTHR = 2 k: RTHR = 3 k: 10 45 50 Input Voltage (V) RTHR = 4 k: 30 50 70 Temperature (qC) 90 55 60 D006 RTHR = 0 Ω Figure 6. Input Current vs Input Voltage Low-Level Threshold Voltage (V) High-Level Threshold Voltage (V) RTHR = 0 k: RTHR = 1 k: 40 RSENSE = 562 Ω RTHR = 0 Ω Figure 5. Input Current vs Input Voltage 20 19 18 17 16 15 14 13 12 11 10 9 8 7 -50 35 D005 110 130 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 -50 RTHR = 0 k: RTHR = 1 k: -30 -10 10 D007 RSENSE = 562 Ω RTHR = 2 k: RTHR = 3 k: 30 50 70 Temperature (qC) ADVANCE INFORMATION Input Current (mA) 2 RTHR = 4 k: 90 110 130 D008 RSENSE = 562 Ω Figure 7. High-Level Voltage Transition Threshold vs Ambient Temperature Figure 8. Low-Level Voltage Transition Threshold vs Ambient Temperature 7 Input Current (mA) 6 5 4 3 40qC 25qC 85qC 105qC 115qC 125qC 2 1 0 0 10 20 RSENSE = 200 Ω 30 40 Input Voltage (V) 50 60 70 D009 RTHR = 0 Ω Figure 9. Input Current vs Input Voltage Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 13 ISO1211, ISO1212 SLLSEY7 – JUNE 2017 www.ti.com 7 Detailed Description 7.1 Overview The ISO1211 and ISO1212 devices are fully-integrated, isolated digital-input receivers with IEC 61131-2 Type 1, 2, and 3 characteristics. The devices receive 24-V digital-input signals and provide isolated digital outputs. No field-side power supply is required. An external resistor, RSENSE, on the input-signal path precisely sets the limit for the current drawn from the field input. The voltage transition thresholds are compliant with Type 1, 2, and 3 and can be increased further using an external resistor, RTHR. The ISO121x devices use an ON-OFF keying (OOK) modulation scheme to transmit the digital data across a silicon-dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. The conceptual block diagram of the ISO121x device is shown in the Functional Block Diagram section. 7.2 Functional Block Diagram INPUT IN Capacitive Isolation RSENSE ILIM ADVANCE INFORMATION RTHR SENSE OUT FGND Copyright © 2017, Texas Instruments Incorporated 7.3 Feature Description The ISO121x devices receive 24-V digital input signals and provide isolated digital outputs. An external resistor, RSENSE, connected between the INx and SENSEx pins, sets the limit for the current drawn from the field input. Internal voltage comparators connected to the SENSEx pins determine the input-voltage transition thresholds. The output buffers on the control side are capable of providing enough current to drive status LEDs. The EN pin is used to enable the output buffers. A low state on the EN pin puts the output buffers in a high-impedance state. The ISO121x devices are capable of operating up to 4 Mbps. Both devices support an isolation withstand voltage of 2500 VRMS between side 1 and side 2. Table 1 provides an overview of the device features. Table 1. Device Features 14 PART NUMBER CHANNELS MAXIMUM DATA RATE PACKAGE RATED ISOLATION ISO1211 1 4 Mbps 8-pin SOIC (D) 2500 VRMS, 3600 VPK ISO1212 2 4 Mbps 16-pin SSOP (DBQ) 2500 VRMS, 3600 VPK Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 ISO1211, ISO1212 www.ti.com SLLSEY7 – JUNE 2017 7.4 Device Functional Modes Table 2 lists the functional modes for the ISO121x devices. Table 2. Function Table (1) PU PD (1) (2) INPUT (INx, SENSEx) OUTPUT ENABLE (EN) OUTPUT (OUTx) H H or Open H L H or Open L Open H or Open L When INx and SENSEx are open, the output of the corresponding channel goes to Low. X L Z A low value of output enable causes the outputs to be high impedance. X X Undetermined COMMENTS Channel output assumes the logic state of channel input. When VCC1 is unpowered, a channel output is undetermined (2). When VCC1 transitions from unpowered to powered up; a channel output assumes the logic state of the input. VCC1 = Side 1 power supply; PU = Powered up (VCC1 ≥ 2.25 V); PD = Powered down (VCC1 ≤ 1.7 V); X = Irrelevant; H = High level; L = Low level; Z = High impedance The outputs are in an undetermined state when 1.7 V < VCC1 < 2.25 V. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 15 ADVANCE INFORMATION INPUT SUPPLY VCC1 ISO1211, ISO1212 SLLSEY7 – JUNE 2017 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information ADVANCE INFORMATION The ISO1211 and ISO1212 devices are fully-integrated, isolated digital-input receivers with IEC 61131-2 Type 1, 2, and 3 characteristics. These devices are suitable for high-channel density, digital-input modules for programmable logic controllers and motor control digital input modules. The devices receive 24-V digital-input signals and provide isolated digital outputs. No field side power supply is required. An external resistor, RSENSE, on the input signal path precisely sets the limit for the current drawn from the field input. This current limit helps minimize power dissipated in the system. The current limit can be set for Type 1, 2, or 3 operation. The voltage transition thresholds are compliant with Type 1, 2, and 3 and can be increased further using an external resistor, RTHR. The ISO1211 and ISO1212 devices are capable of high speed operation and can pass through a minimum pulse width of 150 ns. The ISO1211 device has a single receive channel. The ISO1212 device has two receive channels that are independent on the field side. 8.2 Typical Application Figure 10 shows the design for a typical multichannel, isolated digital-input module. Push-button switches, proximity sensors, and other field inputs connect to the host controller through an isolated interface. The design is easily scalable from a few channels, such as 4 or 8, to many channels, such as 256 or more. The RSENSE resistor limits the current drawn from the input pins. The RTHR resistor is used to adjust the voltage thresholds and limit the peak current during surge events. The CIN capacitor is used to filter noise on the input pins. For more information on selecting RSENSE, RTHR, and CIN, see the Detailed Design Procedure section. The ISO121x devices derive field-side power from the input pins which eliminates the requirement for a fieldside, 24-V input power supply to the module. Similarly, an isolated dc-dc converter creating a field-side power supply from the controller side back plane supply is also eliminated which improves flexibility of system design and reduces system cost. For systems requiring channel-to-channel isolation on the field side, use the ISO1211 device as shown in Figure 11. 16 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 ISO1211, ISO1212 www.ti.com SLLSEY7 – JUNE 2017 Typical Application (continued) 5 V or 3.3 V or 2.5 V Backplane supply ISO1212 RTHR SENSE1 CIN RSENSE VCC1 VCC OUT1 IN1 FGND1 RTHR SENSE2 CIN 24 V RSENSE OUT2 IN2 Power Supply FGND2 GND1 Host Controller 0V ISO1212 SENSE1 CIN ADVANCE INFORMATION RTHR VCC1 RSENSE IN1 OUT1 FGND1 RTHR SENSE2 CIN RSENSE IN2 OUT2 FGND2 GND1 GND 2 nF/2 kV PE Copyright © 2017, Texas Instruments Incorporated Figure 10. Typical Application Schematic Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 17 ISO1211, ISO1212 SLLSEY7 – JUNE 2017 www.ti.com Typical Application (continued) 5 V or 3.3 V or 2.5 V Backplane Supply ISO1211 RTHR 24 V CIN + SENSE VCC1 IN OUT VCC RSENSE ± FGND GND1 Host Controller ISO1211 RTHR ADVANCE INFORMATION 24 V + CIN SENSE VCC1 IN OUT RSENSE ± FGND GND1 GND Copyright © 2017, Texas Instruments Incorporated Figure 11. Single-Channel or Channel-to-Channel Isolated Designs With ISO1211 8.2.1 Design Requirements The ISO121x devices require two resistors, RTHR and RSENSE, and a capacitor, CIN, on the field side. Fore more information on selecting RSENSE, RTHR, and CIN, see the Detailed Design Procedure section. A 100-nF decoupling capacitor is required on VCC1. 8.2.2 Detailed Design Procedure 8.2.2.1 Setting Current Limit and Voltage Thresholds The RSENSE resistor limits the current through the input. A value of 562 Ω for RSENSE is recommended for Type 1 and Type 3 operation, and results in a current limit of 2.25 mA (typical). A value of 200 Ω for RSENSE is recommended for Type 2 operation, and results in a current limit of 6 mA (typical). For more information, see the Electrical Characteristics—DC Specification table and Typical Characteristics section. A 1% tolerance is recommended on RSENSE but 5% resistors can also be used if higher variation in the current limit value is acceptable. The RTHR resistor sets the voltage thresholds as well as limits the surge current. A value of 1 kΩ is recommended for RTHR in Type 3 systems (maximum threshold voltage required is 11 V). A value of 3 kΩ is recommended for RTHR in Type 1 systems (maximum threshold voltage required is 15 V) and a value of 330 Ω is recommended for RTHR in Type 2 systems. The Electrical Characteristics—DC Specification lists table the voltage thresholds with different values of RTHR. For other values of RTHR, derive the values through linear interpolation. A value of 0 Ω for RTHR also meets Type 1, Type 2 and Type 3 voltage-threshold requirements. The value of RTHR should be maximized for best EMC performance while meeting the desired input voltage thresholds. Because RTHR is used to limit surge current, 1/W MELF resistors must be used. 18 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 ISO1211, ISO1212 www.ti.com SLLSEY7 – JUNE 2017 Typical Application (continued) 8.2.2.2 Surge, ESD and EFT Tests Digital input modules are subject to surge (IEC 61000-4-5), electrostatic discharge or ESD (IEC 61000-4-2) and electrical fast transient or EFT (IEC 61000-4-4) tests. The surge impulse waveform has the highest energy and the widest pulse width, and is therefore the most stringent test of the three. Figure 10 shows the application diagram for Type 1 and 3 systems. For a 1-kVPP surge test between the input terminals and protection earth (PE), a value of 1 kΩ for RTHR and 10 nF for CIN is recommended. Table 3 lists a summary of recommended component values to meet different levels of EMC requirements for Type 1 and 3 systems. A 2-nF capacitor between FGND and PE is assumed. IEC 61131-2 TYPE RSENSE RTH CIN Type 1 562 3 kΩ Type 3 562 1 kΩ SURGE IEC ESD IEC EFT ±1 kV ±6 kV ±4 kV ±1 kV ±500 kV ±6 kV ±4 kV ±1 kV ±1 kV ±6 kV ±4 kV LINE TO PE LINE TO LINE LINE TO FGND 10 nF ±1 kV ±1 kV 10 nF ±1 kV 330 nF ±1 kV For higher voltage levels of surge tests or for faster systems that cannot use a large value for CIN, TVS diodes or varistors can be used to meet EMC requirements. Type 2 systems that use a smaller value for RTHR may also require TVS diodes or varistors for surge protection. Figure 12 shows an example usage of TVS diodes for surge protection. The recommended components for surge protection are CGA0603MLA-31900E (Varistor, Bourns), SMF36A (TVS, Littelfuse) and GSOT36C (TVS, Vishay). Varistors are less-expensive alternatives to TVS diodes. 5 V or 3.3 V or 2.5 V Backplane Supply ISO1211 RTHR 24 V SENSE VCC1 IN OUT VCC RSENSE TVS 0V FGND GND1 Host Controller GND Copyright © 2017, Texas Instruments Incorporated Figure 12. TVS Diodes Used Instead of a Filtering Capacitor for Surge Protection in Faster Systems 8.2.2.3 Multiplexing the Interface to the Host Controller The ISO121x devices provide an output-enable pin on the controller side (EN). Setting the EN pin to 0 causes the output buffers to be in the high-impedance state. This feature can be used to multiplex the outputs of multiple ISO121x devices on the same host-controller input, reducing the number of pins on the host controller. In the example shown in Figure 13, two sets of 8-channel inputs are multiplexed, reducing the number of input pins required on the controller from 16 to 10. Similarly, if four sets of 8-channel inputs are multiplexed, the number of pins on the controller is reduced from 32 to 12. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 19 ADVANCE INFORMATION Table 3. Surge, IEC ESD and EFT, Test ISO1211, ISO1212 SLLSEY7 – JUNE 2017 www.ti.com ISO1212 ISO1212 RTHR IN1 RTHR SENSE1 SENSE1 RSENSE OUT1 OUT1 IN1 RTHR IN2 IN1 SENSE2 SENSE2 RSENSE IN2 OUT2 RTHR EN ISO1212 ISO1212 RTHR RTHR RSENSE RSENSE SENSE1 SENSE1 IN1 RTHR IN8 IN15 RSENSE OUT1 OUT1 IN1 RTHR SENSE2 SENSE2 IN2 IN10 RSENSE IN2 OUT2 EN IN7 IN9 RSENSE IN16 RSENSE OUT2 OUT2 IN2 EN EN2 DIN8 DIN7 DIN2 DIN1 ADVANCE INFORMATION EN1 EN Host Controller Copyright © 2017, Texas Instruments Incorporated Figure 13. Using the Output Enable Option to Multiplex the Interface to the Host Controller 8.2.2.4 Status LEDs The outputs of the ISO121x devices can be used to drive status LEDs on the controller side as shown in Figure 14. The output buffers of the ISO121x can provide 4-mA, 3-mA, and 2-mA currents while working at VCC1 values of 5 V, 3.3 V, and 2.5 V respectively. 5 V or 3.3 V or 2.5 V Backplane Supply ISO1211 RTHR 24 V CIN Power Supply 0V SENSE VCC1 IN OUT VCC RSENSE FGND Host Controller GND GND1 Status LED Copyright © 2017, Texas Instruments Incorporated Figure 14. Using ISO121x Outputs to Drive Status LEDs 20 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 ISO1211, ISO1212 www.ti.com SLLSEY7 – JUNE 2017 8.2.3 Application Curve 2.75 2.5 Input Current (mA) 2.25 2 1.75 1.5 1.25 1 40qC 25qC 85qC 105qC 115qC 125qC 0.75 0.5 0.25 0 0 5 10 15 20 Input Voltage (V) 25 30 D005 9 Power Supply Recommendations To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended on the side 1 supply pin (VCC1). The capacitor should be placed as close to the supply pins as possible. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 21 ADVANCE INFORMATION RSENSE = 562 Ω RTHR = 0 Ω Figure 15. Input Current vs Input Voltage ISO1211, ISO1212 SLLSEY7 – JUNE 2017 www.ti.com 10 Layout 10.1 Layout Guidelines The board layout for ISO1211 and ISO1212 can be completed in two layers. On the field side, place RSENSE, CIN, and RTHR on the top layer. Use the bottom layer as the field ground (FGND) plane. TI recommends using RSENSE and CIN in 0603 footprint for a compact layout, although larger sizes (0805) can also be used. The CIN capacitor is a 50-V capacitor and is available in the 0603 footprint. Keep CIN as close to the ISO121x device as possible. The SUB pin on the ISO1211 device and the SUB1 and SUB2 pins on the ISO1212 device should be left unconnected. For group isolated design, use vias to connect the FGND pins of the ISO121x device to the bottom FGND plane. The placement of the RTHR resistor is flexible, although the resistor pin connected to external high voltage should not be placed within 4 mm of the ISO121x device pins or the CIN and RSENSE pins to avoid flashover during EMC tests. Only a decoupling capacitor is required on side 1. Place this capacitor on the top-layer, with the bottom layer for GND1. If a board with more than two layers is used, placing two ISO121x devices on the top-and bottom layers (back-toback) is possible to achieve a more compact board. The inner layers can be used for FGND. Figure 16 and Figure 17 show the example layouts. 2 mm maximum from VCC VCC RTHR 0.1 F C VCC1 Isolation Capacitor OUT GND1 GND1 Plane R IN C CIN EN MCU R SENSE RSENSE High Voltage Input FGND SUB FGND Plane Figure 16. Layout Example With ISO1211 2 mm Maximum from VCC VCC R VCC1 EN OUT1 MCU OUT2 NC C RTHR FGND FGND SUB1 R SENSE1 FGND High Voltage Input RTHR SUB2 IN1 INP1 R C INP2 CIN GND1 R IN1 RSENSE NC GND1 Plane SENSE1 GND1 CIN C RSENSE 0.1 F Isolation Capacitor ADVANCE INFORMATION 10.2 Layout Example FGND Plane Figure 17. Layout Example With ISO1212 22 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 ISO1211, ISO1212 www.ti.com SLLSEY7 – JUNE 2017 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: • Isolation Glossary • ISO1211 Isolated Digital-Input Receiver Evaluation Module • ISO1212 Isolated Digital-Input Receiver Evaluation Module 11.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to order now. PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ISO1211 Click here Click here Click here Click here Click here ISO1212 Click here Click here Click here Click here Click here 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.4 Community Resource The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.5 Trademarks E2E is a trademark of Texas Instruments. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1211 ISO1212 23 ADVANCE INFORMATION Table 4. Related Links PACKAGE OPTION ADDENDUM www.ti.com 7-Jul-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ISO1211D PREVIEW SOIC D 8 75 TBD Call TI Call TI -55 to 125 ISO1211DR PREVIEW SOIC D 8 2500 TBD Call TI Call TI -55 to 125 ISO1212DBQ PREVIEW SSOP DBQ 16 75 TBD Call TI Call TI -55 to 125 ISO1212DBQR PREVIEW SSOP DBQ 16 2500 TBD Call TI Call TI -55 to 125 XISO1211D ACTIVE SOIC D 8 75 TBD Call TI Call TI -55 to 125 XISO1212DBQ ACTIVE SSOP DBQ 16 75 TBD Call TI Call TI -55 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 7-Jul-2017 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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