Product Folder Sample & Buy Technical Documents Support & Community Tools & Software Reference Design LMV611, LMV612, LMV614 SNOSC69C – APRIL 2012 – REVISED JULY 2016 LMV61x Single, Dual, and Quad, 1.4-MHz, Low-Power, General-Purpose 1.8-V Operational Amplifiers 1 Features 3 Description • • • The LMV61x devices are single, dual, and quad lowvoltage, low-power operational amplifiers (op amps). They are designed specifically for low-voltage, general-purpose applications. Other important product characteristics are, rail-to-rail input or output, low supply voltage of 1.8 V and wide temperature range. The LMV61x input common mode extends 200 mV beyond the supplies and the output can swing rail-to-rail unloaded and within 30 mV with 2-kΩ load at 1.8-V supply. The LMV61x achieves a gain bandwidth of 1.4 MHz while drawing 100-µA (typical) quiescent current. 1 • • • • • Supply Values: 1.8 V (Typical) Ensured 1.8-V, 2.7-V, and 5-V Specifications Output Swing: – 80 mV From Rail With 600-Ω Load – 30 mV From Rail With 2-kΩ Load VCM = 200 mV Beyond Rails 100-µA Supply Current (Per Channel) 1.4-MHz Gain Bandwidth Product Maximum VOS = 4 mV Temperature Range: −40°C to 125°C 2 Applications The industrial-plus temperature range of −40°C to 125°C allows the LMV61x to accommodate a broad range of extended environment applications. • • • • • • • The LMV611 is offered in the tiny 5-pin SC70 package, the LMV612 in space-saving 8-pin VSSOP and SOIC packages, and the LMV614 in 14-pin TSSOP and SOIC packages. These small package amplifiers offer an ideal solution for applications requiring minimum PCB footprint. Applications with area constrained PCB requirements include portable and battery-operated electronics. Consumer Communication Consumer Computing PDAs Audio Pre-Amplifiers Portable or Battery-Powered Electronic Equipment Supply Current Monitoring Battery Monitoring Device Information(1) Typical Application V PART NUMBER + + R1 ± 2 kŸ RSENSE LMV612 ± 0.2 LMV611 Q1 2N3906 R2 LMV614 + 2 kŸ VOUT Load R3 PACKAGE BODY SIZE (NOM) SOT-23 (5) 2.92 mm × 1.60 mm SC70 (5) 2.00 mm × 1.25 mm VSSOP (8) 3.00 mm × 3.00 mm SOIC (8) 4.90 mm × 3.91 mm TSSOP (14) 5.00 mm × 4.40 mm SOIC (14) 8.64 mm × 3.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 10 kŸ ICHARGE VOUT RSENSE x R3 x ICh arg e 1 : x ICh arg e R1 Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMV611, LMV612, LMV614 SNOSC69C – APRIL 2012 – REVISED JULY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 7 1 1 1 2 3 5 Absolute Maximum Ratings ...................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 5 Electrical Characteristics – 1.8 V (DC) ..................... 6 Electrical Characteristics – 1.8 V (AC)...................... 7 Electrical Characteristics – 2.7 V (DC) ..................... 7 Electrical Characteristics – 2.7 V (AC)...................... 8 Electrical Characteristics – 5 V (DC) ........................ 9 Electrical Characteristics – 5 V (AC)..................... 10 Typical Characteristics .......................................... 11 Detailed Description ............................................ 16 7.1 Overview ................................................................ 16 7.2 Functional Block Diagram ....................................... 16 7.3 Feature Description................................................. 16 7.4 Device Functional Modes ....................................... 17 8 Application and Implementation ........................ 18 8.1 Application Information............................................ 18 8.2 Typical Applications ................................................ 20 9 Power Supply Recommendations...................... 21 10 Layout................................................................... 21 10.1 Layout Guidelines ................................................. 21 10.2 Layout Example ................................................... 22 11 Device and Documentation Support ................. 23 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 Device Support .................................................... Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 23 23 23 23 23 24 24 24 12 Mechanical, Packaging, and Orderable Information ........................................................... 24 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (March 2013) to Revision C Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 • Changed values in the Thermal Information table to align with JEDEC standards................................................................ 5 Changes from Revision A (March 2012) to Revision B • 2 Page Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 LMV611, LMV612, LMV614 www.ti.com SNOSC69C – APRIL 2012 – REVISED JULY 2016 5 Pin Configuration and Functions DCK and DBV Packages 5-Pin SC70 and SOT-23 Top View 1 5 +IN V± ±IN V+ + 2 ± 4 3 OUTPUT Pin Functions – LMV611 PIN NO. NAME 1 +IN – TYPE (1) DESCRIPTION I Noninverting input 2 V P Negative supply input 3 –IN I Inverting input 4 OUTPUT O Output P Positive supply input + 5 (1) V I = Input, O = Output, and P = Power DGK and D Packages 8-Pin VSSOP and SOIC Top View 1 8 + V OUT A A - 2 + 7 -IN A OUT B 3 6 +IN A + - -IN B B - 4 5 V +IN B Pin Functions – LMV612 PIN TYPE (1) DESCRIPTION NO. NAME 1 OUT A O Output A 2 –IN A I Inverting input A (1) I = Input, O = Output, and P = Power Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 Submit Documentation Feedback 3 LMV611, LMV612, LMV614 SNOSC69C – APRIL 2012 – REVISED JULY 2016 www.ti.com Pin Functions – LMV612 (continued) PIN TYPE (1) DESCRIPTION NO. NAME 3 +IN A I Noninverting input A 4 V– P Negative supply input 5 +IN B I Noninverting input B 6 –IN B I Inverting input B 7 OUT B O Output B 8 V+ P Positive supply input PW and D Packages 14-Pin TSSOP and SOIC Top View 1 OUT A IN A± IN A+ V+ IN B+ ± IN B 2 A ± D + + 14 OUT D 13 IN D± ± 3 12 4 11 5 10 IN D+ V± IN C+ 6 + ± B 9 ± + C 7 IN C± 8 OUT B OUT C Pin Functions – LMV614 PIN TYPE (1) DESCRIPTION NO. NAME 1 OUT A O Output A 2 IN A– I Inverting input A 3 IN A+ I Noninverting input A 4 V+ P Positive supply input 5 + IN B I Noninverting input B 6 IN B– I Inverting input B 7 OUT B O Output B 8 OUT C O Output C 9 IN C– I Inverting input C 10 IN C+ I Noninverting input C – 11 V P Negative supply input 12 IN D+ I Noninverting input D 13 IN D– I Inverting input D 14 OUT D O Output D (1) 4 I = Input, O = Output, and P = Power Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 LMV611, LMV612, LMV614 www.ti.com SNOSC69C – APRIL 2012 – REVISED JULY 2016 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN Differential input voltage MAX Supply voltage (V+–V −) 6 V– – 0.3 Voltage at input or output pin Storage temperature, Tstg (2) (3) (4) V V++ 0.3 V 150 °C 150 °C Junction temperature, TJMAX (4) (1) UNIT ±Supply voltage –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. Soldering specifications for all packages available at www.ti.com and Absolute Maximum Ratings for Soldering. The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Machine model (MM) (2) ±200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Machine model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22C101-C (ESD FICDM std. of JEDEC). 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX Supply voltage 1.8 5.5 UNIT V Temperature –40 125 °C 6.4 Thermal Information LMV611 THERMAL METRIC (1) LMV612 LMV614 DBV (SOT-23) DCK (SC70) D (SOIC) DGK (VSSOP) D (SOIC) PW (TSSOP) UNIT 5 PINS 5 PINS 8 PINS 8 PINS 14 PINS 14 PINS RθJA Junction-to-ambient thermal resistance 197.2 285.9 125.9 184.5 94.4 124.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 156.7 115.9 70.2 74.3 52.5 51.4 °C/W RθJB Junction-to-board thermal resistance 55.6 63.7 66.5 105.1 48.9 67.2 °C/W ψJT Junction-to-top characterization parameter 41.4 4.5 19.8 13.1 14.3 6.6 °C/W ψJB Junction-to-board characterization parameter 55 62.9 65.9 103.6 48.6 66.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — — — — — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 Submit Documentation Feedback 5 LMV611, LMV612, LMV614 SNOSC69C – APRIL 2012 – REVISED JULY 2016 www.ti.com 6.5 Electrical Characteristics – 1.8 V (DC) All limits ensured for TJ = 25°C, V+ = 1.8 V, V − = 0 V, VCM = V+/ 2, VO = V+/ 2, and RL > 1 MΩ (unless otherwise noted). (1) PARAMETER TYP (3) MAX (2) LMV611 (single) 1 4 LMV612 (dual) and LMV614 (quad) 1 5.5 TEST CONDITIONS MIN (2) UNIT VOS Input offset voltage TCVOS Input offset voltage average drift 5.5 µV/°C IB Input bias current 15 nA IOS Input offset current 13 IS Supply current (per channel) CMRR PSRR Common-mode rejection ratio Power supply rejection ratio 103 LMV611, 0 V ≤ VCM ≤ 0.6 V, 1.4 V ≤ VCM ≤ 1.8 V (4) 60 78 LMV612 and LMV614, 0 V ≤ VCM ≤ 0.6 V, 1.4 V ≤ VCM ≤ 1.8 V (4) 55 76 −0.2 V ≤ VCM ≤ 0 V, 1.8 V ≤ VCM ≤ 2 V 50 72 1.8 V ≤ V+ ≤ 5 V V , TA = 25°C CMVR Input common-mode voltage For CMRR range ≥ 50 dB AV Large signal voltage gain LMV612 (dual) and LMV614 (quad) V – 0.2 2.1 TA = −40°C to 85°C IO (1) (2) (3) (4) (5) 6 Output short-circuit current V+ + 0.2 V– + 0.2 V+ – 0.2 101 RL = 2 kΩ to 0.9 V, VO = 0.2 V to 1.6 V, VCM = 0.5 V 80 105 RL = 600 Ω to 0.9 V, VO = 0.2 V to 1.6 V, VCM = 0.5 V 75 90 RL = 2 kΩ to 0.9 V, VO = 0.2 V to 1.6 V, VCM = 0.5 V 78 100 1.65 1.72 V dB 0.077 1.75 VIN = ±100 mV (5) dB V+ 77 RL = 2 kΩ to 0.9 V dB V– VIN = ±100 mV Output swing µA –0.2 RL = 600 Ω to 0.9 V, VO = 0.2 V to 1.6 V, VCM = 0.5 V RL = 600 Ω to 0.9 V VO – V+, TA = 25°C TA = 125°C Large signal voltage gain LMV611 (single) nA 185 100 – mV 0.105 1.77 0.024 Sourcing, VO = 0 V, VIN = 100 mV 8 Sinking, VO = 1.8 V, VIN = –100 mV 9 V 0.035 mA Electrical characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No assurance of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. See Application and Implementation for information of temperature derating of the device. Absolute Maximum Ratings indicated junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depends on the application and configuration. The typical values are not tested and are not ensured on shipped production material. For specified temperature ranges, see Input common mode voltage specifications. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of 45 mA over long term may adversely affect reliability. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 LMV611, LMV612, LMV614 www.ti.com SNOSC69C – APRIL 2012 – REVISED JULY 2016 6.6 Electrical Characteristics – 1.8 V (AC) All limits ensured for TJ = 25°C, V+ = 1.8 V, V − = 0 V, VCM = V+/ 2, VO = V+/ 2, and RL > 1 MΩ (unless otherwise noted). (1) PARAMETER TEST CONDITIONS MIN (2) (4) TYP (3) MAX (2) UNIT SR Slew rate 0.35 V/µs GBW Gain-bandwidth product 1.4 MHz Φm Phase margin 67 ° Gm Gain margin 7 dB en Input-referred voltage noise f = 10 kHz, VCM = 0.5 V 60 nV/√Hz in Input-referred current noise f = 10 kHz 0.08 pA/√Hz Total harmonic distortion f = 1 kHz, AV = +1, RL = 600 Ω, VIN = 1 VPP THD 0.023% Amp-to-amp isolation (5) (1) (2) (3) (4) (5) 123 dB Electrical characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No assurance of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. See Application and Implementation for information of temperature derating of the device. Absolute Maximum Ratings indicated junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depends on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Connected as voltage follower with input step from V− to V+. Number specified is the slower of the positive and negative slew rates. Input-referred, RL = 100 kΩ connected to V+ / 2. Each amp excited in turn with 1 kHz to produce VO = 3 VPP (for supply voltages < 3 V, VO = V+). 6.7 Electrical Characteristics – 2.7 V (DC) All limits ensured for TJ = 25°C, V+ = 2.7 V, V − = 0 V, VCM = V+/ 2, VO = V+/ 2, and RL > 1 MΩ (unless otherwise noted). (1) TYP (3) MAX (2) LMV611 (single) 1 4 LMV612 (dual) and LMV614 (quad) 1 5.5 PARAMETER TEST CONDITIONS MIN (2) UNIT VOS Input offset voltage TCVOS Input offset voltage average drift 5.5 µV/°C IB Input bias current 15 nA IOS Input offset current IS Supply current (per channel) CMRR PSRR (1) (2) (3) (4) Common-mode rejection ratio Power supply rejection ratio mV 8 105 LMV611, 0 V ≤ VCM ≤ 1.5 V, 2.3 V ≤ VCM ≤ 2.7 V (4) 60 81 LMV612 and LMV614, 0 V ≤ VCM ≤ 1.5 V, 2.3 V ≤ VCM ≤ 2.7 V (4) 55 80 −0.2 V ≤ VCM ≤ 0 V, 2.7 V ≤ VCM ≤ 2.9 V 50 74 1.8 V ≤ V+ ≤ 5 V, VCM = 0.5 V nA 190 100 µA dB dB Electrical characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No assurance of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. See Application and Implementation for information of temperature derating of the device. Absolute Maximum Ratings indicated junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depends on the application and configuration. The typical values are not tested and are not ensured on shipped production material. For specified temperature ranges, see input common mode voltage specifications. Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 Submit Documentation Feedback 7 LMV611, LMV612, LMV614 SNOSC69C – APRIL 2012 – REVISED JULY 2016 www.ti.com Electrical Characteristics – 2.7 V (DC) (continued) All limits ensured for TJ = 25°C, V+ = 2.7 V, V − = 0 V, VCM = V+/ 2, VO = V+/ 2, and RL > 1 MΩ (unless otherwise noted).(1) PARAMETER TEST CONDITIONS – V ,TA = 25°C VCM Input common-mode voltage For CMRR range ≥ 50 dB AV Large signal voltage gain LMV612 (dual) and LMV614 (quad) TA = –40°C to 85°C V+ V– + 0.2 V+ – 0.2 104 RL = 2 kΩ to 1.35 V, VO = 0.2 V to 2.5 V 92 110 RL = 600 Ω to 1.35 V, VO = 0.2 V to 2.5 V 78 90 RL = 2 kΩ to 1.35 V, VO = 0.2 V to 2.5 V 81 100 2.55 2.62 Output short-circuit current (5) (5) V dB 0.083 2.65 VIN = ±100 mV IO UNIT V+ + 0.2 V– 87 RL = 2 kΩ to 1.35 V MAX (2) –0.2 3 VIN = ±100 mV Output swing TYP (3) RL = 600 Ω to 1.35 V, VO = 0.2 V to 2.5 V RL = 600 Ω to 1.35 V VO V – 0.2 V+,TA = 25°C TA = 125°C Large signal voltage gain LMV611 (single) MIN (2) – 0.11 2.675 0.025 Sourcing, VO = 0 V, VIN = 100 mV 30 Sinking, VO = 0 V, VIN = –100 mV 25 V 0.04 mA Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of 45 mA over long term may adversely affect reliability. 6.8 Electrical Characteristics – 2.7 V (AC) All limits ensured for TJ = 25°C, V+ = 2.7 V, V − = 0 V, VCM = 1 V, VO = 1.35 V, and RL > 1 MΩ (unless otherwise noted). (1) PARAMETER SR Slew rate GBW TEST CONDITIONS MIN (2) (4) TYP (3) MAX (2) UNIT 0.4 V/µs Gain-bandwidth product 1.4 MHz Φm Phase margin 70 ° Gm Gain margin en Input-referred voltage noise f = 10 kHz, VCM = 0.5 V in Input-referred current noise f = 10 kHz THD Total harmonic distortion f = 1 kHz, AV = +1, RL = 600 Ω, VIN = 1 VPP Amp-to-amp isolation (1) (2) (3) (4) (5) 8 7.5 dB 57 nV/√Hz 0.08 pA/√Hz 0.022% (5) 123 dB Electrical characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No assurance of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. See Application and Implementation for information of temperature derating of the device. Absolute Maximum Ratings indicated junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depends on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Connected as voltage follower with input step from V− to V+. Number specified is the slower of the positive and negative slew rates. Input-referred, RL = 100 kΩ connected to V+ / 2. Each amp excited in turn with 1 kHz to produce VO = 3 VPP (for supply voltages < 3 V, VO = V+). Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 LMV611, LMV612, LMV614 www.ti.com SNOSC69C – APRIL 2012 – REVISED JULY 2016 6.9 Electrical Characteristics – 5 V (DC) All limits ensured for TJ = 25°C, V+ = 5 V, V − = 0 V, VCM = V+/ 2, VO = V+/ 2, and RL > 1 MΩ (unless otherwise noted). (1) TYP (3) MAX (2) LMV611 (single) 1 4 LMV612 (dual) and LMV614 (quad) 1 5.5 PARAMETER TEST CONDITIONS MIN (2) VOS Input offset voltage TCVOS Input offset voltage average drift 5.5 IB Input bias current 14 IOS Input offset current IS Supply current (per channel) CMRR Common-mode rejection ratio PSRR Power supply rejection ratio 116 0 V ≤ VCM ≤ 3.8 V, 4.6 V ≤ VCM ≤ 5 V (4) 60 86 –0.2 V ≤ VCM ≤ 0 V 5 V ≤ VCM ≤ 5.2 V 50 78 1.8 V ≤ V+ ≤ 5 V, VCM = 0.5 V For CMRR range ≥ 50 dB V – 0.2 V , TA = 25°C Large signal voltage gain LMV612 (dual) and LMV614 (quad) VO Output swing (1) (2) (3) (4) (5) Output short-circuit current (5) 210 µA nA V+ + 0.2 V+ V– + 0.3 V+ – 0.3 RL = 600 Ω to 2.5 V, VO = 0.2 V to 4.8 V 88 102 RL = 2 kΩ to 2.5 V, VO = 0.2 V to 4.8 V 94 113 RL = 600 Ω to 2.5 V, VO = 0.2 V to 4.8 V 81 90 RL = 2 kΩ to 2.5 V, VO = 0.2 V to 4.8 V 85 100 RL = 600 Ω to 2.5 V 4.855 4.89 4.945 4.967 V dB VIN = ±100 mV RL = 2 kΩ to 2.5 V dB V– 0.12 VIN = ±100 mV IO nA –0.2 5.3 TA = –40°C to 85°C TA = 125°C AV 35 100 – + Large signal voltage gain LMV611 (single) µV/°C dB V , TA = 25°C Input common-mode voltage mV 9 – CMVR UNIT LMV611, Sourcing, VO = 0 V, VIN = 100 mV Sinking, VO = 5 V, VIN = –100 mV 0.037 0.16 V 0.065 100 mA 65 Electrical characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No assurance of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. See Application and Implementation for information of temperature derating of the device. Absolute Maximum Ratings indicated junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depends on the application and configuration. The typical values are not tested and are not ensured on shipped production material. For specified temperature ranges, see Input common mode voltage specifications. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of 45 mA over long term may adversely affect reliability. Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 Submit Documentation Feedback 9 LMV611, LMV612, LMV614 SNOSC69C – APRIL 2012 – REVISED JULY 2016 www.ti.com 6.10 Electrical Characteristics – 5 V (AC) All limits ensured for TJ = 25°C, V+ = 5 V, V − = 0 V, VCM = V+/ 2, VO = 2.5 V, and R L > 1 MΩ (unless otherwise noted). (1) PARAMETER TEST CONDITIONS MIN (2) (4) TYP (3) MAX (2) UNIT SR Slew rate 0.42 V/µs GBW Gain-bandwidth product 1.5 MHz Φm Phase margin 71 ° Gm Gain margin 8 dB en Input-referred voltage noise f = 10 kHz, VCM = 1 V 50 nV/√Hz in Input-referred current noise f = 10 kHz 0.08 pA/√Hz Total harmonic distortion f = 1 kHz, AV = +1, RL = 600 Ω, VO = 1 V PP THD 0.022% Amp-to-amp isolation (5) (1) (2) (3) (4) (5) 10 123 dB Electrical characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No assurance of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. See Application and Implementation for information of temperature derating of the device. Absolute Maximum Ratings indicated junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depends on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Connected as voltage follower with input step from V− to V+. Number specified is the slower of the positive and negative slew rates. Input-referred, RL = 100 kΩ connected to V+ / 2. Each amp excited in turn with 1 kHz to produce VO = 3 VPP (for supply voltages < 3 V, VO = V+). Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 LMV611, LMV612, LMV614 www.ti.com SNOSC69C – APRIL 2012 – REVISED JULY 2016 6.11 Typical Characteristics VS = 5 V, single supply, TA = 25°C (unless otherwise noted) 160 100 140 SUPPLY CURRENT (éA) VS = 5V 125°C 85°C 120 ISOURCE (mA) 10 100 25°C 80 -40°C 60 VS = 2.7V 1 VS = 1.8V 40 0.1 20 0 0 1 2 3 4 5 6 0.01 0.001 SUPPLY VOLTAGE (V) 100 VS = 5V ISINK (mA) 10 VS = 2.7V 1 VS = 1.8V 0.01 0.001 0.01 0.1 10 1 1 10 140 RL = 600: 130 NEGATIVE SWING 120 110 100 90 80 POSITIVE SWING 70 60 0 OUTPUT VOLTAGE REF TO GND (V) Figure 3. Sinking Current vs Output Voltage OUTPUT VOLTAGE PROXIMITY TO SUPPLY VOLTAGE (mV ABSOLUTE VALUE) 0.1 Figure 2. Sourcing Current vs Output Voltage OUTPUT VOLTAGE PROXIMITY TO SUPPLY VOLTAGE (mV ABSOLUTE VALUE) Figure 1. Supply Current vs Supply Voltage (LMV611) 0.1 0.01 OUTPUT VOLTAGE REFERENCED TO V+ (V) 1 4 2 3 SUPPLY VOLTAGE (V) 5 6 Figure 4. Output Voltage Swing vs Supply Voltage 45 RL = 2k: 40 NEGATIVE SWING 35 30 25 POSITIVE SWING 20 0 1 2 3 4 5 6 SUPPLY VOLTAGE (V) Figure 5. Output Voltage Swing vs Supply Voltage Figure 6. Gain and Phase vs Frequency Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 Submit Documentation Feedback 11 LMV611, LMV612, LMV614 SNOSC69C – APRIL 2012 – REVISED JULY 2016 www.ti.com Typical Characteristics (continued) VS = 5 V, single supply, TA = 25°C (unless otherwise noted) Figure 7. Gain and Phase vs Frequency Figure 8. Gain and Phase vs Frequency 90 VS = 5V 85 CMRR (dB) 80 VS = 2.7V 75 VS = 1.8V 70 65 60 1k 100 FREQUENCY (Hz) 10 Figure 9. Gain and Phase vs Frequency Figure 10. CMRR vs Frequency 1000 VS = 5V +PSRR 90 PSRR (dB) 80 70 -PSRR 60 50 40 100 1k FREQUENCY (Hz) Figure 11. PSRR vs Frequency 12 Submit Documentation Feedback 10k INPUT VOLTAGE NOISE (nV/ Hz) 100 30 10 10k 100 10 10 100 1k 10k 100k FREQUENCY (Hz) Figure 12. Input Voltage Noise vs Frequency Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 LMV611, LMV612, LMV614 www.ti.com SNOSC69C – APRIL 2012 – REVISED JULY 2016 Typical Characteristics (continued) VS = 5 V, single supply, TA = 25°C (unless otherwise noted) 1 10 INPUT CURRENT NOISE (pA/ Hz) RL = 600: AV = +1 THD (%) 1 0.1 1.8V 0.1 2.7V 5V 0.01 10 100 1k 10k 0.01 10 100k 10k 1k 100 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 14. THD vs Frequency Figure 13. Input Current Noise vs Frequency 10 0.5 RL = 600: AV = +10 SLEW RATE (V/Ps) 0.45 THD (%) 1 5V 0.1 FALLING EDGE 0.4 RISING EDGE 0.35 RL = 2k: 0.3 1.8V AV = +1 2.7V 0.01 10 VIN = 1VPP 0.25 100 1k 10k 0 100k 1 2 5 6 VS = 2.7V RL = 2 k: (50 mV/DIV) INPUT SIGNAL OUTPUT SIGNAL INPUT SIGNAL OUTPUT SIGNAL (50 mV/DIV) RL = 2 k: 4 Figure 16. Slew Rate vs Supply Voltage Figure 15. THD vs Frequency VS = 1.8V 3 SUPPLY VOLTAGE (V) FREQUENCY (Hz) TIME (2.5 Ps/DIV) TIME (2.5 Ps/DIV) Figure 17. Small Signal Noninverting Response Figure 18. Small Signal Noninverting Response Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 Submit Documentation Feedback 13 LMV611, LMV612, LMV614 SNOSC69C – APRIL 2012 – REVISED JULY 2016 www.ti.com Typical Characteristics (continued) VS = 5 V, single supply, TA = 25°C (unless otherwise noted) VIN INPUT SIGNAL VS = 5V OUTPUT SIGNAL (50 mV/DIV) (900 mV/div) RL = 2 k: VOUT VS = 1.8V RL = 2k: AV = +1 TIME (2.5 Ps/DIV) TIME (10 Ps/div) Figure 19. Small Signal Noninverting Response Figure 20. Large Signal Noninverting Response VIN (2.5 V/div) (1.35V/DIV) VIN VOUT VOUT VS = 5.0V VS = 2.7V RL = 2 k: RL = 2k: AV = +1 AV = +1 TIME (10 Ps/div) TIME (10 Ps/DIV) Figure 21. Large Signal Noninverting Response Figure 22. Large Signal Noninverting Response 90 90 SHORT CIRCUIT C URRENT (mA) SHORT CIRCUIT CURRENT (mA) 5V 80 5V 70 60 50 40 2.7V 30 20 1.8V 10 0 -40 10 60 TEMPERATURE (°C) 110 Figure 23. Short-Circuit Current vs Temperature (Sinking) 14 Submit Documentation Feedback 80 70 60 50 40 2.7V 30 20 1.8V 10 0 -40 10 60 110 TEMPERATURE (°C) Figure 24. Short-Circuit Current vs Temperature (Sourcing) Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 LMV611, LMV612, LMV614 www.ti.com SNOSC69C – APRIL 2012 – REVISED JULY 2016 Typical Characteristics (continued) VS = 5 V, single supply, TA = 25°C (unless otherwise noted) 3 3 VS = 2.7V VS = 1.8V 2.5 2.5 2 2 25°C -40°C 1.5 VOS (mV) VOS (mV) 25°C 1 0.5 85°C 1 0.5 85°C 125°C 125°C 0 0 -0.5 -0.5 -1 -0.4 0 0.4 0.8 -40°C 1.5 1.2 2 1.6 -1 -0.4 2.4 0.1 0.6 1.1 1.6 2.1 2.6 3.1 VCM (V) VCM (V) Figure 25. Offset Voltage vs Common-Mode Range Figure 26. Offset Voltage vs Common-Mode Range 3 VS = 5V 2.5 2 VOS (mV) -40°C 1.5 1 0.5 125°C 25°C 85°C 0 -0.5 -1 -0.4 0.6 1.6 2.6 3.6 4.6 5.6 VCM (V) Figure 27. Offset Voltage vs Common-Mode Range Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 Submit Documentation Feedback 15 LMV611, LMV612, LMV614 SNOSC69C – APRIL 2012 – REVISED JULY 2016 www.ti.com 7 Detailed Description 7.1 Overview The LMV61x devices achieve a gain bandwidth of 1.4 MHz while drawing 100-µA (typical) quiescent current. They also provide a rail-to-rail input with a maximum input offset voltage of 4 mV. Lastly, the LMV61x input common mode extends 200 mV beyond the supplies and the output can swing rail-to-rail unloaded and within 30 mV with 2-kΩ load at 1.8-V supply. 7.2 Functional Block Diagram IP Q16 nIN Q18 VBIAS1 Q19 Q17 IN I14 I15 M14 M15 VCC M62 M100 Out Class AB Control pIN VBIAS2 M12 M13 I12 I13 M60 M101 VEE Copyright © 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Input and Output Stage The rail-to-rail input stage of this family provides more flexibility for the designer. The LMV61x use a complimentary PNP and NPN input stage in which the PNP stage senses common-mode voltage near V− and the NPN stage senses common-mode voltage near V+. The transition from the PNP stage to NPN stage occurs 1 V below V+. Because both input stages have their own offset voltage, the offset of the amplifier becomes a function of the input common-mode voltage and has a crossover point at 1 V below V+. This VOS crossover point can create problems for both DC- and AC-coupled signals if proper care is not taken. Large input signals that include the VOS crossover point causes distortion in the output signal. One way to avoid such distortion is to keep the signal away from the crossover. For example, in a unity-gain buffer configuration and with VS = 5 V, a 5-V peak-to-peak signal contains input-crossover distortion while a 3-V peak-to-peak signal centered at 1.5 V does not contain input-crossover distortion as it avoids the crossover point. Another way to avoid large signal distortion is to use a gain of −1 circuit which avoids any voltage excursions at the input terminals of the amplifier. In that circuit, the common-mode DC voltage can be set at a level away from the VOS crossover point. For small signals, this transition in VOS shows up as a VCM dependent spurious signal in series with the input signal and can effectively degrade small signal parameters such as gain and common-mode rejection ratio. To resolve this problem, the small signal must be placed such that it avoids the VOS crossover point. In addition to the rail-to-rail performance, the output stage can provide enough output current to drive 600-Ω loads. Because of the high current capability, take care to not exceed the 150°C maximum junction temperature specification. 16 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 LMV611, LMV612, LMV614 www.ti.com SNOSC69C – APRIL 2012 – REVISED JULY 2016 7.4 Device Functional Modes 7.4.1 Input Bias Current Consideration The LMV61x family has a complementary bipolar input stage. The typical input bias current (IB) is 15 nA. The input bias current can develop a significant offset voltage. This offset is primarily due to IB flowing through the negative feedback resistor, RF. For example, if IB is 50 nA and RF is 100 kΩ, then an offset voltage of 5 mV develops (VOS = IB × RF). Using a compensation resistor (RC), as shown in Figure 28, cancels this effect. But the input offset current (IOS) still contributes to an offset voltage in the same manner. RF Ri Vi ± Vo (a) Vo (b) Vo (c) + Rc = Ri RF RF Ri ± Vi + Rc = Ri RF RF ± Vi + RC = RF Figure 28. Canceling Offset Voltage Due to Input Bias Current Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 Submit Documentation Feedback 17 LMV611, LMV612, LMV614 SNOSC69C – APRIL 2012 – REVISED JULY 2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LMV61x devices bring performance, economy, and ease-of-use to low-voltage, low-power systems. They provide rail-to-rail input and rail-to-rail output swings into heavy loads. 8.1.1 Half-Wave Rectifier With Rail-to-Ground Output Swing Because the LMV61x input common-mode range includes both positive and negative supply rails and the output can also swing to either supply, achieving half-wave rectifier functions in either direction is an easy task. All that is needed are two external resistors; there is no need for diodes or matched resistors. The half wave rectifier can have either positive or negative going outputs, depending on the way the circuit is arranged. In Figure 29 the circuit is referenced to ground, while in Figure 30 the circuit is biased to the positive supply. These configurations implement the half-wave rectifier because the LMV61x can not respond to one-half of the incoming waveform. It can not respond to one-half of the incoming because the amplifier can not swing the output beyond either rail. Therefore, the output disengages during this half cycle. During the other half cycle, however, the amplifier achieves a half wave that can have a peak equal to the total supply voltage. RI must be large enough not to load the LMV61x. RI VIN VIN RI + VOUT 0 t ± VOUT VCC t Figure 29. Half-Wave Rectifier With Rail-to-Ground Output Swing Referenced to Ground 18 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 LMV611, LMV612, LMV614 www.ti.com SNOSC69C – APRIL 2012 – REVISED JULY 2016 Application Information (continued) VCC VIN + VOUT VCC t VIN ± RI RI VOUT VCC t Figure 30. Half-Wave Rectifier With Negative-Going Output Referenced to VCC 8.1.2 Instrumentation Amplifier With Rail-to-Rail Input and Output Some manufactures make rail-to-rail op amps out of op amps that are otherwise non-rail-to-rail by using a resistive divider on the inputs. The resistors divide the input voltage to get a rail-to-rail input range. The problem with this method is that it also divides the signal, so to get the obtained gain, the amplifier must have a higher closed-loop gain. This raises the noise and drift by the internal gain factor and lowers the input impedance. Any mismatch in these precision resistors reduces the CMRR, as well. The LMV61x is rail-to-rail and therefore doesn’t have these disadvantages. Using three of the LMV61x amplifiers, an instrumentation amplifier with rail-to-rail inputs and outputs can be made as shown in Figure 31. In this example, amplifiers on the left side act as buffers to the differential stage. These buffers assure that the input impedance is very high and require no precision matched resistors in the input stage. They also assure that the difference amp is driven from a voltage source. This is necessary to maintain the CMRR set by the matching R1-R2 with R3-R4. The gain is set by the ratio of R2/R1 and R3 must equal R1 and R4 equal R2. With both rail-torail input and output ranges, the input and output are only limited by the supply voltages. Remember that even with rail-to-rail outputs, the output can not swing past the supplies so the combined common-mode voltages plus the signal must not be greater that the supplies or limiting occurs. Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 Submit Documentation Feedback 19 LMV611, LMV612, LMV614 SNOSC69C – APRIL 2012 – REVISED JULY 2016 www.ti.com Application Information (continued) R2 R1 + + ± ± ± + + R3 ± R4 Figure 31. Rail-to-Rail Instrumentation Amplifier 8.2 Typical Applications 8.2.1 High-Side Current Sensing V + + R1 ± 2 kŸ RSENSE ± 0.2 Q1 2N3906 R2 + 2 kŸ VOUT Load R3 10 kŸ ICHARGE VOUT RSENSE x R3 x ICh arg e 1 : x ICh arg e R1 Copyright © 2016, Texas Instruments Incorporated Figure 32. High-Side, Current-Sensing Schematic 8.2.1.1 Design Requirements The high-side, current-sensing circuit (Figure 32) is commonly used in a battery charger to monitor charging current to prevent overcharging. A sense resistor RSENSE is connected to the battery directly. This system requires an op amp with rail-to-rail input. The LMV61x are ideal for this application because its common-mode input range goes up to the rail. 8.2.1.2 Detailed Design Procedure As seen in (Figure 32), the ICHARGE current flowing through sense resistor RSENSE develops a voltage drop equal to VSENSE. The voltage at the negative sense point is now less than the positive sense point by an amount proportional to the VSENSE voltage. 20 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 LMV611, LMV612, LMV614 www.ti.com SNOSC69C – APRIL 2012 – REVISED JULY 2016 Typical Applications (continued) The low-bias currents of the LMV61x cause little voltage drop through R2, so the negative input of the LMV61x amplifier is at essentially the same potential as the negative sense input. The LMV61x detects this voltage error between its inputs and servo the transistor base to conduct more current through Q1, increasing the voltage drop across R1 until the LMV61x inverting input matches the noninverting input. At this point, the voltage drop across R1 now matches VSENSE. IG, a current proportional to ICHARGE, flows according to Equation 1. IG = VRSENSE / R1 = ( RSENSE × ICHARGE ) / R1 (1) IG also flows through the gain resistor R3 developing a voltage drop equal to Equation 2. V3 = IG × R3 = ( VRSENSE / R1 ) × R3 = ( ( RSENSE × ICHARGE ) / R2 ) × R3 VOUT = (RSENSE × ICHARGE ) × G (2) where • G = R3 / R1 (3) The other channel of the LMV61x may be used to buffer the voltage across R3 to drive the following stages. 8.2.1.2.1 Application Curve 5 VOUT (V) VOUT (V) 4 3 2 1 1 2 3 4 ILOAD (A) 5 C003 Figure 33. High-Side, Current-Sensing Results 9 Power Supply Recommendations For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, TI recommends that 10-nF capacitors be placed as close as possible to the op amp power supply pins. For singlesupply, place a capacitor between V+ and V– supply leads. For dual supplies, place one capacitor between V+ and ground, and one capacitor between V– and ground. 10 Layout 10.1 Layout Guidelines To properly bypass the power supply, several locations on a printed-circuit board must be considered. A 6.8-µF or greater tantalum capacitor must be placed at the point where the power supply for the amplifier is introduced onto the board. Another 0.1-µF ceramic capacitor must be placed as close as possible to the power supply pin of the amplifier. If the amplifier is operated in a single power supply, only the V+ pin must be bypassed with a 0.1-µF capacitor. If the amplifier is operated in a dual power supply, both V+ and V– pins must be bypassed. It is good practice to use a ground plane on a printed-circuit board to provide all components with a low inductive ground connection. Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 Submit Documentation Feedback 21 LMV611, LMV612, LMV614 SNOSC69C – APRIL 2012 – REVISED JULY 2016 www.ti.com Layout Guidelines (continued) TI recommends surface-mount components in 0805 size or smaller in the LMV611-N application circuits. Designers can take advantage of the VSSOP miniature sizes to condense board layout to save space and reduce stray capacitance. 10.2 Layout Example Figure 34. SOT-23 Layout Example 22 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 LMV611, LMV612, LMV614 www.ti.com SNOSC69C – APRIL 2012 – REVISED JULY 2016 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support For development support see the following: • LMV611 SPICE Model • LMV612 SPICE Model • LMV614 SPICE Model • SPICE-based analog simulation program, TINA-TI • DIP adapter evaluation module, DIP Adapter EVM • TI universal operational amplifier evaluation module, Op Amp EVM • TI software, FilterPro 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: • Absolute Maximum Ratings for Soldering (SNOA549) • AN-29 IC Op Amp Beats FETs on Input Current (SNOA624) • AN-31 Op Amp Circuit Collection (SNLA140) • AN-71 Micropower Circuits Using the LM4250 Programmable Op Amp (SNOA652) • AN-127 LM143 Monolithic High Voltage Operational Amplifier Applications (SNVA516) 11.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LMV611 Click here Click here Click here Click here Click here LMV612 Click here Click here Click here Click here Click here LMV614 Click here Click here Click here Click here Click here 11.4 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.5 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 Submit Documentation Feedback 23 LMV611, LMV612, LMV614 SNOSC69C – APRIL 2012 – REVISED JULY 2016 www.ti.com 11.6 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.7 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.8 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 24 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMV611 LMV612 LMV614 PACKAGE OPTION ADDENDUM www.ti.com 7-Jul-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMV611MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AE9A LMV611MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AE9A LMV611MG/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AVA LMV611MGX/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AVA LMV612MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV6 12MA LMV612MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV6 12MA LMV612MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS CU NIPDAUAG | CU SN Level-1-260C-UNLIM & no Sb/Br) -40 to 125 AD9A LMV612MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS CU NIPDAUAG | CU SN Level-1-260C-UNLIM & no Sb/Br) -40 to 125 AD9A LMV614MA/NOPB ACTIVE SOIC D 14 55 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV614MA LMV614MAX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV614MA LMV614MT/NOPB ACTIVE TSSOP PW 14 94 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LMV61 4MT LMV614MTX/NOPB ACTIVE TSSOP PW 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LMV61 4MT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 7-Jul-2016 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 22-Jul-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ LMV611MF/NOPB SOT-23 LMV611MFX/NOPB LMV611MG/NOPB Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.2 1.4 4.0 8.0 Q3 DBV 5 1000 178.0 8.4 SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMV611MGX/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMV612MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMV612MM/NOPB VSSOP DGK 8 1000 178.0 13.4 5.3 3.4 1.4 8.0 12.0 Q1 LMV612MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMV612MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMV612MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMV614MAX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 LMV614MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 LMV614MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 3.2 B0 (mm) PACKAGE MATERIALS INFORMATION www.ti.com 22-Jul-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMV611MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV611MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMV611MG/NOPB SC70 DCK 5 1000 210.0 185.0 35.0 LMV611MGX/NOPB SC70 DCK 5 3000 210.0 185.0 35.0 LMV612MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMV612MM/NOPB VSSOP DGK 8 1000 202.0 201.0 28.0 LMV612MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMV612MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LMV612MMX/NOPB VSSOP DGK 8 3500 364.0 364.0 27.0 LMV614MAX/NOPB SOIC D 14 2500 367.0 367.0 35.0 LMV614MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0 LMV614MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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