Micron AMT36VDDF25672Y-26A Ddr sdram rdimm Datasheet

1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Features
DDR SDRAM RDIMM
MT36VDDF12872 – 1GB
MT36VDDF25672 – 2GB
For component data sheets, refer to Micron’s Web site: www.micron.com
Features
Figure 2:
• 184-pin, registered dual in-line memory module
(RDIMM)
• Tall- and standard-height PCB options
• Fast data transfer rates: PC2100, PC2700, or PC3200
• 1GB (128 Meg x 72) and 2GB (256 Meg x 72)
• Supports ECC error detection and correction
• VDD = VDDQ = +2.5V
(-40B VDD = VDDQ = +2.6V)
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2-compatible)
• Internal, pipelined double data rate (DDR)
2n-prefetch architecture
• Bidirectional data strobe (DQS) transmitted/
received with data—that is, source-synchronous
data capture
• Differential clock inputs (CK and CK#)
• Multiple internal device banks for concurrent
operation
• Dual rank
• Selectable burst lengths (BL): 2, 4, or 8
• Auto precharge option
• Auto refresh and self refresh modes: 7.8125µs
maximum average periodic refresh interval
• Serial presence-detect (SPD) with EEPROM
• Selectable CAS latency (CL) for maximum
compatibility
• Gold edge contacts
PCB height: 30.48mm (1.2in)
Figure 3:
Options
Marking
1
• Operating temperature
– Commercial (0°C ≤ TA ≤ +70°C)
– Industrial (–40°C ≤ TA ≤ +85°C)
• Package
– 184-pin DIMM (standard)
– 184-pin DIMM (Pb-free)
• Memory clock, speed, CAS latency2
– 5.0ns (200 MHz), 400 MT/s, CL = 3
– 6.0ns (166 MHz), 333 MT/s, CL = 2.5
– 7.5ns (133 MHz), 266 MT/s, CL = 2
– 7.5ns (133 MHz), 266 MT/s, CL = 2
– 7.5ns (133 MHz), 266 MT/s, CL = 2.5
Tall-Height Layout – 1GB, 2GB
(MO-206-EA)
None
I
G
Y
-40B
-335
-262
-26A
-265
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency; registered mode
adds one clock cycle to CL.
PCB height: 43.18mm (1.7in)
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Standard-Height Layout – 2GB
(MO-206-CA R/C D)
PCB height: 30.48mm (1.2in)
184-Pin RDIMM Figures
Figure 1:
Standard-Height Layout – 1GB
(MO-206-CA R/C D)
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Features
Table 1:
Key Timing Parameters
Data Rate (MT/s)
Speed
Grade
Industry
Nomenclature
CL = 3
CL = 2.5
CL = 2
RCD
(ns)
t
RP
(ns)
t
RC
(ns)
-40B
-335
-262
-26A
-265
PC3200
PC2700
PC2100
PC2100
PC2100
400
–
–
–
–
333
333
266
266
266
266
266
266
266
200
15
18
15
20
20
15
18
15
20
20
55
60
60
65
65
Notes:
Table 2:
Notes
1
1. The values of tRCD and tRP for -335 modules show 18ns to align with industry specifications;
actual DDR SDRAM device specifications are 15ns.
Addressing
Parameter
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
Table 3:
t
1GB
2GB
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (64 Meg x 4)
2K (A0–A9, A11)
2 (S0#, S1#)
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (128 Meg x 4)
4K (A0–A9, A11, A12)
2 (S0#, S1#)
Part Numbers and Timing Parameters – 1GB Modules
Base device: MT46V64M4,1 256Mb DDR SDRAM
Part Number2
MT36VDDF12872G-40B__
MT36VDDF12872Y-40B__
MT36VDDF12872G-335__
MT36VDDF12872Y-335__
MT36VDDF12872G-262__
MT36VDDF12872G-26A__
MT36VDDF12872Y-26A__
MT36VDDF12872G-265__
MT36VDDF12872Y-265__
Notes:
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Module
Density
Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
3.2 GB/s
3.2 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
5.0ns/400 MT/s
5.0ns/400 MT/s
6.0ns/333 MT/s
6.0ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
3-3-3
3-3-3
3-3-3
3-3-3
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
1. Data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes.
Example: MT36VDDF12872Y-335G3.
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Features
Table 4:
Part Numbers and Timing Parameters – 2GB Modules
Base device: MT46V128M4,1 512Mb DDR SDRAM
Part Number2
MT36VDDF25672G-40B__
MT36VDDF25672Y-40B__
MT36VDDF25672G-335__
MT36VDDF25672Y-335__
MT36VDDF25672G-262__
MT36VDDF25672G-26A__
MT36VDDF25672G-265__
MT36VDDF25672Y-265__
Notes:
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Module
Density
Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
3.2 GB/s
3.2 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
5.0ns/400 MT/s
5.0ns/400 MT/s
6.0ns/333 MT/s
6.0ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
3-3-3
3-3-3
3-3-3
3-3-3
2-2-2
2-3-3
2.5-3-3
2.5-3-3
1. Data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes.
Example: MT36VDDF12872Y-335G3.
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 5:
Pin Assignments
184-Pin DDR RDIMM Front
184-Pin DDR RDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
RESET#
VSS
DQ8
DQ9
DQS1
VDDQ
NC
NC
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VDD
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
DQS8
A0
CB2
VSS
CB3
BA1
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
VDDQ
WE#
DQ41
CAS#
VSS
DQS5
DQ42
DQ43
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDD
NC
DQ48
DQ49
VSS
NC
NC
VDDQ
DQS6
DQ50
DQ51
VSS
NC
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
4
VSS
DQ4
DQ5
VDDQ
DQS9
DQ6
DQ7
VSS
NC
NC
NC
VDDQ
DQ12
DQ13
DQS10
VDD
DQ14
DQ15
CKE1
VDDQ
NC
DQ20
A12
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
VSS
DQ21
A11
DQS11
VDD
DQ22
A8
DQ23
VSS
A6
DQ28
DQ29
VDDQ
DQS12
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
CK0#
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
VSS
DQS17
A10
CB6
VDDQ
CB7
VSS
DQ36
DQ37
VDD
DQS13
DQ38
DQ39
VSS
DQ44
RAS#
DQ45
VDDQ
S0#
S1#
DQS14
VSS
DQ46
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
DQ47
NC
VDDQ
DQ52
DQ53
NC
VDD
DQS15
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DQS16
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Pin Assignments and Descriptions
Table 6:
Pin Descriptions
Symbol
Type
Description
A0–A12
Input
BA0, BA1
Input
CK0, CK0#
Input
CKE0, CKE1
Input
RAS#, CAS#, WE#
Input
RESET#
Input
S0#, S1#
Input
SA0–SA2
Input
SCL
Input
CB0–CB7
DQ0–DQ63
DQS0–DQS17
I/O
I/O
I/O
SDA
I/O
VDD/VDDQ
VDDSPD
VREF
VSS
NC
Supply
Supply
Supply
Supply
–
Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all
device banks (A10 HIGH). The address inputs also provide the op-code during a
MODE REGISTER SET command. BA0 and BA1 define which mode register
(mode register or extended mode register) is loaded during the LOAD MODE
REGISTER command.
Bank address: BA0 and BA1 define the device bank to which an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
Clock: CK and CK# are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and the
negative edge of CK#. Output data (DQ and DQS) is referenced to the
crossings of CK and CK#.
Clock enable: CKE enables (registered HIGH) and CKE disables (registered
LOW) the internal clock, input buffers, and output drivers.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command
being entered.
Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW.
This signal can be used during power-up to ensure that CKE is LOW and DQ are
High-Z.
Chip selects: S# enables (registered LOW) and disables (registered HIGH) the
command decoder.
Presence-detect address inputs: These pins are used to configure the SPD
EEPROM address range on the I2C bus.
Serial clock for SPD EEPROM: SCL is used to synchronize the presence-detect
data transfer to and from the module.
Check bits.
Data input/output: Data bus.
Data strobe: Output with read data. Edge-aligned with read data. Input with
write data. Center-aligned with write data. Used to capture data.
Serial data: SDA is a bidirectional pin used to transfer addresses and data into
and out of the presence-detect portion of the module.
Power supply: +2.5V ±0.2V (-40B: +2.6V ±0.1V).
SPD EEPROM power supply: +2.3V to +3.6V.
SSTL_2 reference voltage (VDD/2).
Ground.
No connect: These pins are not connected on the module.
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Functional Block Diagrams
Functional Block Diagrams
Figure 4:
Functional Block Diagram – Tall-Height Layout (1GB, 2GB)
S1#
S0#
DQS0
DQ0
DQ1
DQ2
DQ3
DQS4
DQS CS#
DQ
DQ
U11
DQ
DQ
DQS CS#
DQ
DQ
U36
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQS CS#
DQ
DQ
U1
DQ
DQ
DQS CS#
DQ
DQ U28
DQ
DQ
DQ36
DQ37
DQ38
DQ39
DQS CS#
DQ
DQ
U12
DQ
DQ
DQS CS#
DQ
DQ U35
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQS
DQ
DQ
DQ
DQ
DQS CS#
DQ
DQ U27
DQ
DQ
DQS9
DQ4
DQ5
DQ6
DQ7
DQS10
U2
DQ44
DQ45
DQ46
DQ47
CS#
U5
DQS CS#
DQ
DQ U24
DQ
DQ
CB4
CB5
CB6
CB7
DQS2
DQS CS#
DQ
DQ U34
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQS CS#
DQ
DQ
U3
DQ
DQ
DQS CS#
DQ
DQ U26
DQ
DQ
DQ52
DQ53
DQ54
DQ55
DQS CS#
DQ
DQ
U31
DQ
DQ
DQS CS#
DQ
DQ U8
DQ
DQ
DQS CS#
DQ
DQ U21
DQ
DQ
DQS
DQ
DQ
DQ
DQ
DQS CS#
DQ
DQ U23
DQ
DQ
CS#
U6
DQS CS#
DQ
DQ U14
DQ
DQ
DQS CS#
DQ
DQ U33
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQS CS#
DQ
DQ
U4
DQ
DQ
DQS CS#
DQ
DQ U25
DQ
DQ
DQS CS#
DQ
DQ
U17
DQ
DQ
DQS CS#
DQ
DQ
U30
DQ
DQ
DQS
DQ
DQ
DQ
DQ
DQS CS#
DQ
DQ U20
DQ
DQ
DQS15
DQS3
CS#
U9
DQS7
DQS12
DQ28
DQ29
DQ30
DQ31
DQS CS#
DQ
DQ U16
DQ
DQ
DQS6
DQS CS#
DQ
DQ U13
DQ
DQ
DQS11
DQ24
DQ25
DQ26
DQ27
U7
DQS17
DQS
DQ
DQ
DQ
DQ
DQ20
DQ21
DQ22
DQ23
DQS CS#
DQ
DQ U22
DQ
DQ
CS#
DQS14
CS#
DQS8
DQ16
DQ17
DQ18
DQ19
DQS
DQ
DQ
DQ
DQ
DQS5
DQ12
DQ13
DQ14
DQ15
CB0
CB1
CB2
CB3
DQS CS#
DQ
DQ U32
DQ
DQ
DQS13
DQS1
DQ8
DQ9
DQ10
DQ11
DQS CS#
DQ
DQ U15
DQ
DQ
DQS CS#
DQ
DQ
U18
DQ
DQ
DQS CS#
DQ
DQ U29
DQ
DQ
DQS CS#
DQ
DQ U10
DQ
DQ
DQS CS#
DQ
DQ U19
DQ
DQ
DQS16
DQ60
DQ61
DQ62
DQ63
Rank 0 = U1–U18
Rank 1 = U19–U36
CAS#
RAS#: DDR SDRAM
CKE0
CKE1
WE#
A0–A12
BA0
BA1
S0#
S1#
R
e
g
i
s
t
e
r
s
SCL
SPD EEPROM
WP A0 A1 A2
CKE0: DDR SDRAM, rank 0
VSS SA0 SA1 SA2
CKE1: DDR SDRAM, rank 1
DDR SDRAM x 4
SDA
CAS#: DDR SDRAM
U40
CK0
CK0#
PLL
VDD
A0–A12: DDR SDRAM
BA0: DDR SDRAM
BA1: DDR SDRAM
S0#: DDR SDRAM, rank 0
S1#: DDR SDRAM, rank 1
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
WE#: DDR SDRAM
RESET#
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
DDR SDRAM x 4
U39
U37, U38
RAS#
VDDSPD
SPD EEPROM
VDD/VDDQ
DDR SDRAM
VREF
DDR SDRAM
VSS
DDR SDRAM
6
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
Register x 2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Functional Block Diagrams
Figure 5:
Functional Block Diagram – Standard-Height Layout (1GB)
S1#
S0#
DQS0
DQS4
DQ0
DQ1
DQ2
DQ3
DQS CS#
DQ
DQ
U1
DQ
DQ
DQS CS#
DQ
DQ
U33
DQ
DQ
DQS CS#
DQ
DQ
U2
DQ
DQ
DQS CS#
DQ
DQ U32
DQ
DQ
DQS CS#
DQ
DQ U13
DQ
DQ
DQS CS#
DQ
DQ U40
DQ
DQ
DQS CS#
DQ
DQ
U3
DQ
DQ
DQS CS#
DQ
DQ U31
DQ
DQ
DQS CS#
DQ
DQ U26
DQ
DQ
DQS
DQ
DQ
DQ
DQ
DQS CS#
DQ
DQ U4
DQ
DQ
DQS CS#
DQ
DQ U30
DQ
DQ
DQS CS#
DQ
DQ U14
DQ
DQ
DQS CS#
DQ
DQ U39
DQ
DQ
DQS CS#
DQ
DQ
U5
DQ
DQ
DQS CS#
DQ
DQ U29
DQ
DQ
DQS CS#
DQ
DQ U15
DQ
DQ
DQS CS#
DQ
DQ U38
DQ
DQ
DQS CS#
DQ
DQ U25
DQ
DQ
DQS CS#
DQ
DQ
U8
DQ
DQ
DQS CS#
DQ
DQ
U36
DQ
DQ
DQS CS#
DQ
DQ U17
DQ
DQ
DQS CS#
DQ
DQ
U24
DQ
DQ
DQS
DQ
DQ
DQ
DQ
DQS CS#
DQ
DQ
U35
DQ
DQ
DQS CS#
DQ
DQ U18
DQ
DQ
DQS CS#
DQ
DQ
U6
DQ
DQ
DQS CS#
DQ
DQ U28
DQ
DQ
DQS CS#
DQ
DQ
U34
DQ
DQ
DQS CS#
DQ
DQ
U20
DQ
DQ
DQS CS#
DQ
DQ U23
DQ
DQ
DQS CS#
DQ
DQ U10
DQ
DQ
DQS CS#
DQ
DQ U21
DQ
DQ
DQS CS#
DQ
DQ U12
DQ
DQ
DQS CS#
DQ
DQ
U22
DQ
DQ
DQS CS#
DQ
DQ U11
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQS9
DQS13
DQ4
DQ5
DQ6
DQ7
DQ36
DQ37
DQ38
DQ39
DQS1
DQS5
DQ8
DQ9
DQ10
DQ11
DQ40
DQ41
DQ42
DQ43
DQS10
DQ12
DQ13
DQ14
DQ15
CS#
U9
DQS14
DQ44
DQ45
DQ46
DQ47
DQS8
DQS17
CB0
CB1
CB2
CB3
CS#
CB4
CB5
CB6
CB7
U7
DQS2
DQS6
DQ16
DQ17
DQ18
DQ19
DQ48
DQ49
DQ50
DQ51
DQS11
DQ20
DQ21
DQ22
DQ23
DQS15
DQ52
DQ53
DQ54
DQ55
DQS3
DQS7
DQ24
DQ25
DQ26
DQ27
DQ56
DQ57
DQ58
DQ59
DQS12
DQ28
DQ29
DQ30
DQ31
DQS16
CAS#
CKE0
CKE1
WE#
A0–A12
BA0
BA1
S0#
S1#
DDR SDRAM x 4
Rank 0 = U1–U6, U13–U15, U21–U26, U34–U36
Rank 1 = U7–U12, U17, U18, U20, U28–U33, U38–U40
U16, U37
RAS#
DQ60
DQ61
DQ62
DQ63
RAS#: DDR SDRAM
R
e
g
i
s
t
e
r
s
CAS#: DDR SDRAM
CKE0: DDR SDRAM, rank 0
CKE1: DDR SDRAM, rank 1
CK0
CK0#
DDR SDRAM x 4
U27
DDR SDRAM x 4
PLL
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
VDD
WE#: DDR SDRAM
DDR SDRAM x 4
DDR SDRAM x 4
A0–A12: DDR SDRAM
DDR SDRAM x 4
Register x 2
BA0: DDR SDRAM
BA1: DDR SDRAM
S0#: DDR SDRAM, rank 0
S1#: DDR SDRAM, rank 1
RESET#
U19
SCL
SPD EEPROM
WP A0 A1 A2
SDA
VDDSPD
SPD EEPROM
VDD/VDDQ
DDR SDRAM
VREF
DDR SDRAM
VSS
DDR SDRAM
VSS SA0 SA1 SA2
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Functional Block Diagrams
Figure 6:
Functional Block Diagram – Standard-Height Layout (2GB)
S1#
S0#
DQS0
DQ0
DQ1
DQ2
DQ3
DQS4
DQS CS#
DQ
DQ
U1
DQ
DQ
DQS CS#
DQ
DQ
U31
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQS CS#
DQ
DQ U11
DQ
DQ
DQS CS#
DQ
DQ U40
DQ
DQ
DQ36
DQ37
DQ38
DQ39
DQS CS#
DQ
DQ
U2
DQ
DQ
DQS CS#
DQ
DQ U30
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQS CS#
DQ
DQ U12
DQ
DQ
DQS CS#
DQ
DQ U39
DQ
DQ
DQS CS#
DQ
DQ U35
DQ
DQ
DQS CS#
DQ
DQ U16
DQ
DQ
DQS
DQ
DQ
DQ
DQ
DQS CS#
DQ
DQ U29
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQS CS#
DQ
DQ U13
DQ
DQ
DQS CS#
DQ
DQ U38
DQ
DQ
DQ52
DQ53
DQ54
DQ55
DQS CS#
DQ
DQ
U4
DQ
DQ
DQS CS#
DQ
DQ U28
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQS CS#
DQ
DQ U14
DQ
DQ
DQS CS#
DQ
DQ U37
DQ
DQ
DQ60
DQ61
DQ62
DQ63
DQS9
DQ4
DQ5
DQ6
DQ7
DQ44
DQ45
DQ46
DQ47
CB4
CB5
CB6
CB7
U3
DQS
DQ
DQ
DQ
DQ
DQS
DQ
DQ
DQ
DQ
DQS CS#
DQ
DQ U27
DQ
DQ
CS#
U5
DQS
DQ
DQ
DQ
DQ
DQS CS#
DQ
DQ U33
DQ
DQ
DQS CS#
DQ
DQ U18
DQ
DQ
DQS CS#
DQ
DQ U21
DQ
DQ
DQS CS#
DQ
DQ U10
DQ
DQ
CKE0
CKE1
WE#
A0–A12
BA0
BA1
S0#
S1#
CS#
DQS CS#
DQ
DQ U32
DQ
DQ
DQS CS#
DQ
DQ U20
DQ
DQ
U9
DQS16
DDR SDRAM x 4
U15, U36
CAS#
U8
DQS CS#
DQ
DQ U22
DQ
DQ
Rank 0 = U1–U5, U11–U14, U21–U25, U32–U35
Rank 1 = U6–U10, U16–U20, U27–U31, U37–U40
RAS#
CS#
DQS7
DQS12
DQ28
DQ29
DQ30
DQ31
DQS CS#
DQ
DQ
U23
DQ
DQ
DQS15
DQS3
DQ24
DQ25
DQ26
DQ27
DQS CS#
DQ
DQ U17
DQ
DQ
U7
DQS6
CS#
DQS11
DQ20
DQ21
DQ22
DQ23
DQS CS#
DQ
DQ U34
DQ
DQ
CS#
DQS17
DQS2
DQ16
DQ17
DQ18
DQ19
DQS
DQ
DQ
DQ
DQ
U6
DQS14
DQS8
CB0
CB1
CB2
CB3
DQS CS#
DQ
DQ U24
DQ
DQ
CS#
DQS5
DQS10
DQ12
DQ13
DQ14
DQ15
DQS
DQ
DQ
DQ
DQ
DQS13
DQS1
DQ8
DQ9
DQ10
DQ11
DQS CS#
DQ
DQ U25
DQ
DQ
R
e
g
i
s
t
e
r
s
DDR SDRAM x 4
RAS#: DDR SDRAM
CAS#: DDR SDRAM
CKE0: DDR SDRAM, rank 0
CK0
CK0#
U26
DDR SDRAM x 4
PLL
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
CKE1: DDR SDRAM, rank 1
VDD
WE#: DDR SDRAM
DDR SDRAM x 4
DDR SDRAM x 4
A0–A12: DDR SDRAM
DDR SDRAM x 4
Register x 2
BA0: DDR SDRAM
BA1: DDR SDRAM
SPD EEPROM
S0#: DDR SDRAM, rank 0
VDDSPD
S1#: DDR SDRAM, rank 1
VDD/VDDQ
DDR SDRAM
VREF
DDR SDRAM
VSS
DDR SDRAM
RESET#
SCL
U19
SPD EEPROM
WP A0 A1 A2
SDA
VSS SA0 SA1 SA2
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
General Description
General Description
The MT36VDDF12872 and MT36VDDF25672 are high-speed, CMOS dynamic random
access 1GB and 2GB memory modules organized in a x72 configuration. These modules
use DDR SDRAM devices with four internal banks.
DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for DDR SDRAM modules effectively consists of a single
2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands are registered at every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of DQS, as well as to both
edges of CK.
Register and PLL Operation
These DDR SDRAM modules operate in registered mode, where the control, command,
and address input signals are latched in the registers on the rising clock edge and sent to
the DDR SDRAM devices on the following rising clock edge (data access is delayed by
one clock cycle). A phase-lock loop (PLL) on the module receives and redrives the differential clock signals (CK, CK#) to the DDR SDRAM devices. The register(s) and PLL reduce
control, command, address, and clock signals loading by isolating DRAM from the
system controller. PLL clock timing is defined by JEDEC specifications and ensured by
use of the JEDEC clock reference board. Registered mode will add one clock cycle to CL.
Serial Presence-Detect Operation
DDR SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module
type and various DDR SDRAM organizations and timing parameters. The remaining 128
bytes of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
I2C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA[2:0],
which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is connected
to VSS, permanently disabling hardware write protect.
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed in Table 7 may cause permanent damage to the
module. This is a stress rating only, and functional operation of the module at these or
any other conditions outside those indicated on the device data sheet is not implied.
Exposure to absolute maximum rating conditions for extended periods may adversely
affect reliability.
Table 7:
Symbol
VDD/VDDQ
VIN, VOUT
II
IOZ
TA
Absolute Maximum Ratings
Parameter
Min
Max
Units
VDD/VDDQ supply voltage relative to VSS
Voltage on any pin relative to VSS
Address inputs,
Input leakage current; Any input 0V ≤ VIN ≤ VDD;
VREF input 0V ≤ VIN ≤ 1.35V (All other pins not under RAS#, CAS#, WE#, BA,
test = 0V)
S#, CKE
CK, CK#
Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ are DQ, DQS
disabled
DRAM ambient operating temperature1
Commercial
Industrial
–1.0
–0.5
–5
+3.6
+3.2
+5
V
V
µA
–10
–10
+10
+10
µA
0
–40
+70
+85
°C
°C
Notes:
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
1. For further information, refer to technical note TN-00-08: “Thermal Applications,” available
on Micron’s Web site.
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Electrical Specifications
DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR component data sheets.
Component specifications are available on Micron’s Web site. Module speed grades
correlate with component speed grades, as shown in table 8.
Table 8:
Module and Component Speed Grades
DDR components may exceed the listed module speed grades
Module Speed Grade
Component Speed Grade
-40B
-335
-262
-26A
-265
-5B
-6
-75E
-75Z
-75
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully
designed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level.
Micron encourages designers to simulate the signal characteristics of the system’s
memory bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to
ensure the required supply voltage is maintained.
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Electrical Specifications
IDD Specifications
Table 9:
IDD Specifications and Conditions – 1GB (Die Revision K)
Values are for the MT46V64M4 DDR SDRAM only and are computed from values specified in the
256Mb (64 Meg x 4) component data sheet
Parameter/Condition
Symbol
t
t
t
t
Operating one bank active-precharge current: RC = RC (MIN); CK = CK (MIN);
DQ and DQS inputs changing once per clock cycle; Address and control inputs changing
once every two clock cycles
Operating one bank active-read-precharge current: BL = 2; tRC = tRC (MIN);
t
CK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle
Precharge power-down standby current: All device banks idle; Power-down mode;
t
CK = tCK (MIN); CKE = LOW
Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN); CKE = HIGH;
Address and other control inputs changing once per clock cycle; VIN = VREF for DQ and
DQS
Active power-down standby current: One device bank active; Power-down mode;
tCK = tCK (MIN); CKE = LOW
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active;
tRC = tRAS (MAX); tCK = tCK (MIN); DQ and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One device bank
active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN);
IOUT = 0mA
Operating burst write current: BL = 2; Continuous burst writes; One device bank
active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ
and DQS inputs changing twice per clock cycle
tRFC = tRFC (MIN)
Auto refresh current
tRFC = 7.8125µs
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving reads
(BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and control
inputs change only during active READ or WRITE commands
Notes:
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
-40B
-335
Units
1
IDD0
1,872
1,692
mA
IDD11
2,232
2,142
mA
IDD2P2
144
144
mA
IDD2F2
1,800
1,800
mA
IDD3P2
1,260
1,080
mA
IDD3N2
2,160
1,980
mA
IDD4R1
3,312
2,952
mA
IDD4W1
3,312
2,952
mA
IDD52
IDD5A2
IDD62
IDD71
5,760
216
144
5,292
5,760
216
144
4,932
mA
mA
mA
mA
1. Value calculated as one module rank in this operating condition; all other module ranks are
in IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Electrical Specifications
Table 10:
IDD Specifications and Conditions – 1GB (All Other Die Revisions)
Values are for the MT46V64M4 DDR SDRAM only and are computed from values specified in the
256Mb (64 Meg x 4) component data sheet
Parameter/Condition
Symbol -40B
IDD01
Operating one bank active-precharge current: tRC = tRC (MIN);
t
t
CK = CK (MIN); DQ and DQS inputs changing once per clock cycle; Address
and control inputs changing once every two clock cycles
IDD11
Operating one bank active-read-precharge current: BL = 2;
t
t
t
t
RC = RC (MIN); CK = CK (MIN); IOUT = 0mA; Address and control inputs
changing once per clock cycle
IDD2P2
Precharge power-down standby current: All device banks idle; Powert
t
down mode; CK = CK (MIN); CKE = LOW
IDD2F2
Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN);
CKE = HIGH; Address and other control inputs changing once per clock cycle;
VIN = VREF for DQ and DQS
IDD3P2
Active power-down standby current: One device bank active; Powerdown mode; tCK = tCK (MIN); CKE = LOW
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; IDD3N2
tRC = tRAS (MAX); tCK = tCK (MIN); DQ and DQS inputs changing twice per
clock cycle; Address and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One device IDD4R1
bank active; Address and control inputs changing once per clock cycle;
tCK = tCK (MIN); IOUT = 0mA
IDD4W1
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle; tCK = tCK (MIN); DQ and DQS inputs changing twice per clock cycle
tRFC = tRFC (MIN)
IDD52
Auto refresh current
tRFC
= 7.8125µs
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving
reads (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address
and control inputs change only during active READ or WRITE commands
Notes:
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
IDD5A2
IDD62
IDD71
-335
-262
-26A/
-265 Units
2,502 2,322 2,322 2,232
mA
3,132 3,132 2,952 2,682
mA
144
144
144
144
mA
2,160 1,800 1,620 1,620
mA
1,440 1,080
mA
900
900/
1,080
2,520 2,160 1,800 1,800
mA
3,672 3,222 2,772 2,772
mA
3,582 3,222 2,772 2,772
mA
9,360 9,180 8,460 8,460/
8,820
216
216
216
216
144
144
144
144
8,532 7,452 6,372 6,372/
6,642
mA
mA
mA
mA
1. Value calculated as one module rank in this operating condition; all other module ranks are
in IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Electrical Specifications
Table 11:
IDD Specifications and Conditions – 2GB
Values are for the MT46V128M4 DDR SDRAM only and are computed from values specified in the
512Mb (128 Meg x 4) component data sheet
Parameter/Condition
Symbol -40B
t
t
Operating one bank active-precharge current: RC = RC (MIN);
t
CK = tCK (MIN); DQ and DQS inputs changing once per clock cycle;
Address and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
RC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs
changing once per clock cycle
Precharge power-down standby current: All device banks idle; Powerdown mode; tCK = tCK (MIN); CKE = LOW
Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN);
CKE = HIGH; Address and other control inputs changing once per clock
cycle; VIN = VREF for DQ and DQS
Active power-down standby current: One device bank active; Powerdown mode; tCK = tCK (MIN); CKE = LOW
Active standby current: CS# = HIGH; CKE = HIGH; One device bank
active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ and DQS inputs changing
twice per clock cycle; Address and other control inputs changing once per
clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One
device bank active; Address and control inputs changing once per clock
cycle; tCK = tCK (MIN); IOUT = 0mA
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle; tCK = tCK (MIN); DQ and DQS inputs changing twice per clock cycle
tRFC = tRFC (MIN)
Auto refresh current
tRFC = 7.8125µs
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank
interleaving reads (BL = 4) with auto precharge; tRC = tRC (MIN);
t
CK = tCK (MIN); Address and control inputs change only during active
READ or WRITE commands
Notes:
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
-335
-262
-26A/
-265
Units
1
IDD0
2,880
2,430
2,430
2,160
mA
IDD11
3,420
2,970
2,970
2,700
mA
IDD2P2
180
180
180
180
mA
IDD2F2
1,980
1,620
1,620
1,440
mA
IDD3P2
1,620
1,260
1,260
1,080
mA
IDD3N2
2,160
1,800
1,800
1,620
mA
IDD4R1
3,510
3,060
3,060
2,700
mA
IDD4W1
3,600
3,240
2,880
2,520
mA
IDD52 12,420 10,440 10,440 10,080
IDD5A2
396
360
360
360
180
180
180
180
IDD62
IDD71
8,190 7,380 7,290 6,390
mA
mA
mA
mA
1. Value calculated as one module rank in this operating condition; all other module ranks are
in IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Register and PLL Specifications
Register and PLL Specifications
Table 12:
Register Specifications
SSTV16859 devices or equivalent JESD82-4B
Parameter
Symbol
Pins
Condition
Min
Max
Units
VIH(DC)
SSTL_25
VREF(DC) + 150
–
mV
SSTL_25
–
VREF(DC) - 150
mV
SSTL_25
VREF(DC) + 310
VDD
mV
SSTL_25
–
VREF(DC) - 310
mV
VOH
VOL
II
IDD
IDD
Control, command,
address
Control, command,
address
Control, command,
address
Control, command,
address
Parity output
Parity output
All pins
All pins
All pins
VDD - 0.2
–
–5.0
–
–
–
0.2
+5.0
100
Varies by
manufacturer
V
V
µA
µA
mA
Dynamic operating
(clock tree)
IDDD
n/a
–
Varies by
manufacturer
µA
Dynamic operating
(per each input)
IDDD
n/a
–
Varies by
manufacturer
µA
Input capacitance
(per device, per pin)
Input capacitance
(per device, per pin)
CI
All inputs except
RESET#
RESET#
LVCMOS
LVCMOS
VI = VDDQ or VSSQ
RESET# = VSSQ (IO = 0)
RESET# = VSSQ;
VI = VIH(AC) or VIL(DC)
IO = 0
RESET# = VDD, VI = VIH(AC)
or VIL(AC), IO = 0; CK and
CK# switching 50% duty
cycle
RESET# = VDD, VI = VIH(AC)
or VIL(AC), IO = 0; CK and
CK# switching 50% duty
cycle; One data input
switching at tCK/2, 50%
duty cycle
VI = VREF ±250mV;
VDDQ = 1.8V
VI = VDDQ or VSSQ
2.5
3.5
pF
–
Varies by
manufacturer
pF
DC high-level
input voltage
DC low-level
input voltage
AC high-level
input voltage
AC low-level
input voltage
Output high voltage
Output low voltage
Input current
Static standby
Static operating
VIL(DC)
VIH(AC)
VIL(AC)
CI
Notes:
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
1. Timing and switching specifications for the register listed above are critical for proper operation of the DDR SDRAM RDIMMs. These are meant to be a subset of the parameters for
the specific device used on the module. Detailed information for this register is available in
JEDEC Standard JESD82.
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Register and PLL Specifications
Table 13:
PLL Specifications
CVF857 device or equivalent JESD82-1A
Parameter
DC high-level input voltage
DC low-level input voltage
Input voltage (limits)
Input differential-pair cross voltage
Input differential voltage
Input differential voltage
Input current
Dynamic supply current
Dynamic supply current
Dynamic supply current
Input capacitance
Table 14:
Symbol
Min
Max
Units
VIH
VIL
VIN
VIX
VID(DC)
VID(AC)
II
IDDPD
IDDQ
IADD
CIN
1.7
–0.3
–0.3
(VDDQ/2) - 0.2
0.36
0.70
–10
–
–
–
2.0
VDDQ + 0.3
0.7
VDDQ + 0.3
(VDDQ/2) + 0.2
VDDQ + 0.6
VDDQ + 0.6
+10
200
300
12
3.5
V
V
V
V
V
V
µA
µA
µA
mA
pF
PLL Clock Driver Timing Requirements and Switching Characteristics
Parameter
Stabilization time
Input clock slew rate
SSC modulation frequency
SSC clock input frequency deviation
PLL loop bandwidth (–3dB from unity gain)
Notes:
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Symbol
Min
Max
Units
tL
–
1.0
30
0
2.0
100
4.0
50
–0.5
–
µs
V/ns
kHz
%
MHz
tslr(i)
–
–
–
1. PLL timing and switching specifications are critical for proper operation of the DDR DIMM.
This is a subset of parameters for the specific PLL used. Detailed PLL information is available
in JEDEC Standard JESD82-1A.
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Serial Presence-Detect
Serial Presence-Detect
Table 15:
Serial Presence-Detect EEPROM DC Operating Conditions
Parameter/Condition
Symbol
Min
Max
Units
VDDSPD
VIH
VIL
VOL
ILI
ILO
ISB
ICC
2.3
VDDSPD × 0.7
–1.0
–
–
–
–
–
3.6
VDDSPD + 0.5
VDDSPD × 0.3
0.4
10
10
30
2.0
V
V
V
V
µA
µA
µA
mA
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: IOUT = 3mA
Input leakage current: VIN = GND to VDD
Output leakage current: VOUT = GND to VDD
Standby current: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD
Power supply current: SCL clock frequency = 100 kHz
Table 16:
Serial Presence-Detect EEPROM AC Operating Conditions
Parameter/Condition
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA fall time
SDA rise time
Data-in hold time
Start condition hold time
Clock HIGH period
Clock LOW period
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Notes:
Symbol
Min
Max
Units
Notes
tAA
0.2
1.3
200
–
–
0
0.6
0.6
1.3
–
100
0.6
0.6
–
0.9
–
–
300
300
–
–
–
–
400
–
–
–
5
µs
µs
ns
ns
ns
µs
µs
µs
µs
kHz
ns
µs
µs
ms
1
tBUF
tHD:DAT
tF
tR
tHD:DI
tHD:STA
tHIGH
tLOW
fSCL
tSU:DAT
tSU:STA
tSU:STO
t
WRC
2
2
3
4
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistance, and the EEPROM does not respond to its slave address.
Serial Presence-Detect Data
For the latest serial presence-detect data, refer to Micron’s SPD page:
www.micron.com/SPD.
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Module Dimensions
Module Dimensions
Figure 7:
184-Pin RDIMM – Tall-Height Layout (1GB, 2GB)
Front view
4.0 (0.157)
MAX
133.50 (5.256)
133.20 (5.244)
U1
U2
U3
U4
U5
U6
U8
U7
U9
U10
U39
2.0 (0.079) R
(4X)
U11
U12
U13
U14
U37
U38
U15
U16
U17
43.31 (1.705)
43.05 (1.695)
U18
17.78 (0.7)
TYP
2.5 (0.098) D
(2X)
2.31 (0.091) TYP
0.9 (0.035) R
Pin 1
2.21 (0.087) TYP
1.27 (0.05)
TYP
64.77 (2.55)
TYP
1.0 (0.039) TYP
1.02 (0.04)
TYP
10.0 (0.394)
TYP
6.35 (0.25) TYP
49.53 (1.95)
TYP
1.37 (0.054)
1.17 (0.046)
Pin 92
120.65 (4.75)
TYP
Back view
U19
U20
U21
U22
U29
U30
U31
U32
U23
U24
U25
U26
U27
U28
U33
U34
U35
U36
U40
3.8 (0.15) TYP
Pin 184
Pin 93
73.28 (2.88)
TYP
Notes:
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions.
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Module Dimensions
Figure 8:
184-Pin RDIMM – Standard-Height Layout (1GB)
Front view
4.0 (0.157)
MAX
133.50 (5.256)
133.20 (5.244)
U2
U1
U3
U4
U5
U7
U6
U8
U9
U11
U10
U12
30.61 (1.205)
30.35 (1.195)
2.0 (0.079) R
(4X)
U13
2.5 (0.098) D
(2X)
U16
U15
U14
U17
U20
U18
17.78 (0.7)
TYP
U19
2.31 (0.091) TYP
0.9 (0.035) R
Pin 1
2.21 (0.087) TYP
1.27 (0.05)
TYP
64.77 (2.55)
TYP
1.0 (0.039) TYP
1.02 (0.04)
TYP
10.0 (0.394)
TYP
6.35 (0.25) TYP
49.53 (1.95)
TYP
1.37 (0.054)
1.17 (0.046)
Pin 92
120.65 (4.75)
TYP
Back view
U21
U22
U34
U23
U24
U35
U25
U26
U36
U27
U37
U28
U29
U38
U30
U39
U31
U33
U32
U40
3.8 (0.15) TYP
Pin 184
Pin 93
73.28 (2.88)
TYP
Notes:
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions.
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Module Dimensions
Figure 9:
184-Pin RDIMM – Standard-Height Layout (2GB)
Front view
4.0 (0.157)
MAX
133.50 (5.256)
133.20 (5.244)
U1
2.0 (0.079) R
(4X)
U3
U2
U4
U6
U5
U8
U7
U9
U10
30.61 (1.205)
30.35 (1.195)
U11
U12
U14
U13
U15
U16
U17
U18
U19
U20
17.78 (0.7)
TYP
2.5 (0.098) D
(2X)
2.31 (0.091) TYP
0.9 (0.035) R
Pin 1
2.21 (0.087) TYP
1.27 (0.05)
TYP
64.77 (2.55)
TYP
1.0 (0.039) TYP
1.02 (0.04)
TYP
10.0 (0.394)
TYP
6.35 (0.25) TYP
49.53 (1.95)
TYP
1.37 (0.054)
1.17 (0.046)
Pin 92
120.65 (4.75)
TYP
Back view
U21
U23
U22
U32
U33
U24
U34
U25
U35
U26
U36
U27
U28
U38
U37
U30
U29
U39
U31
U40
3.8 (0.15) TYP
Pin 184
Pin 93
73.28 (2.88)
TYP
Notes:
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions.
®
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[email protected] www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of
their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth
herein. Although considered final, these specifications are subject to change, as further product development and data
characterization sometimes occur.
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.