TI1 M38510/65302B2A Dual d-type positive-edge-triggered flip-flop Datasheet

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SN54HC74, SN74HC74
SCLS094E – DECEMBER 1982 – REVISED DECEMBER 2015
SNx4HC74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset
1 Features
3 Description
•
•
•
•
•
•
The SNx4HC74 devices contain two independent Dtype positive-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or resets
the outputs, regardless of the levels of the other
inputs. When PRE and CLR are inactive (high), data
at the data (D) input meeting the setup time
requirements are transferred to the outputs on the
positive-going edge of the clock (CLK) pulse. Clock
triggering occurs at a voltage level and is not directly
related to the rise time of CLK. Following the holdtime interval, data at the D input can be changed
without affecting the levels at the outputs.
1
Wide Operating Voltage Range: 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 40-µA Maximum ICC
Typical tpd = 15 ns
±4-mA Output Drive at 5 V
Very Low Input Current of 1 µA
2 Applications
•
•
•
•
•
•
Ultrasound System
Fans
Lab Instrumentation
Vacuum Cleaners
Video Communications System
IP Phone: Wired
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74HC74N
PDIP (14)
19.30 mm x 6.40 mm
SN74HC74NS
SO (14)
10.20 mm x 5.30 mm
SN74HC74D
SOIC (14)
8.70 mm x 3.90 mm
SN74HC74DB
SSOP (14)
6.50 mm x 5.30 mm
SN74HC74PW
TSSOP (14)
5.00 mm x 4.40 mm
SNJ54HC74J
CDIP (14)
21.30 mm x 7.60 mm
SNJ54HC74W
CFP (14)
9.20 mm x 6.29 mm
SNJ54HC74FK
LCCC (20)
8.90 mm x 8.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
PRE
CLK
C
C
Q
TG
C
C
C
C
C
D
TG
TG
TG
Q
C
C
C
CLR
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HC74, SN74HC74
SCLS094E – DECEMBER 1982 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 11
9.1 Application Information .......................................... 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14
14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
Changes from Revision D (July 2003) to Revision E
•
2
Page
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
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5 Pin Configuration and Functions
N, NS, D, DB, PW, J, or W Package
14-Pin PDIP, SO, SOIC, SSOP, TSSOP, CDIP, or CFP
Top View
14
2
13
3
12
4
11
5
10
6
9
7
8
1D
1CLR
NC
VCC
2CLR
1
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
1CLK
NC
1PRE
NC
1Q
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2D
NC
2CLK
NC
2PRE
1Q
GND
NC
2Q
2Q
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
FK Package
20-Pin LCCC
Top View
NC – No internal connection
Pin Functions
PIN
NAME
LCCC
SOIC, SSOP, CDIP,
PDIP, SO, TSSOP, CFP
NO.
I/O
1CLK
4
3
I
Clock input
1CLR
2
1
I
Clear input - Pull low to set 1Q output low
1D
3
2
I
Input
1PRE
6
4
I
Preset input
1Q
8
5
O
Output
1Q
9
6
O
Inverted output
2CLK
16
11
I
Clock input
2CLR
19
13
I
Clear input - Pull low to set 1Q output low
2D
18
12
I
Input
2PRE
14
10
I
Preset input
2Q
13
9
O
Output
2Q
12
8
O
Inverted output
GND
10
7
—
Ground
—
—
No connect (no internal connection)
14
—
Supply
DESCRIPTION
1
5
NC
7
11
15
17
VCC
20
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
VCC Supply voltage range
(2)
MIN
MAX
–0.5
7
UNIT
V
IIK
Input clamp current
VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current (2)
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
Continuous current through VCC or GND
±50
mA
Junction temperature range
150
°C
150
°C
Tj
Tstg Storage temperature range
(1)
(2)
–65
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
See
(1)
SN54HC74
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
SN74HC74
MIN
NOM
MAX
MIN
NOM
MAX
2
5
6
2
5
6
1.5
1.5
3.15
3.15
4.2
4.2
VCC = 2 V
VIL
Low-level input voltage
VCC = 4.5 V
VCC = 6 V
VI
Input voltage
VO
Output voltage
0
0
VCC = 2 V
∆t/∆v Input transition rise and fall time
VCC = 4.5 V
VCC = 6 V
TA
(1)
4
Operating free-air temperature
0.5
1.35
1.35
1.8
1.8
0
VCC
0
V
VCC
V
1000
500
500
125
V
VCC
1000
400
–55
V
V
0.5
VCC
UNIT
ns
400
–40
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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6.4 Thermal Information
SN74HC74
THERMAL METRIC
D
(SOIC)
(1)
SN54HC74
DB
N
NS
(SSOP) (PDIP) (SO)
PW
J
(TSSOP) (CDIP)
14 PINS
W
(CFP)
14 PINS
FK
(LCCC)
20 PINS
RθJA
Junction-to-ambient thermal resistance
86
96
80
76
113
—
—
—
RθJC(top)
Junction-to-case (top) thermal resistance
—
—
—
—
—
15.05
14.65
5.61
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over recommended operating free-air temperature range, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –20 µA
VCC
MIN
TYP
2V
1.9
1.998
4.5 V
4.4
4.499
6V
5.9
5.999
3.98
4.3
TA = 25°C
VOH
VI = VIH or VIL
IOH = –4 mA
SN54HC74
4.5 V
SN74HC74
SN54HC74
VI = VIH or VIL
IOL = 4 mA
SN54HC74
V
5.8
5.2
5.34
2V
0.002
0.1
4.5 V
0.001
0.1
6V
0.001
0.1
0.17
0.26
TA = 25°C
VOL
3.7
5.48
6V
SN74HC74
IOL = 20 µA
4.5 V
0.4
SN74HC74
SN54HC74
0.15
6V
VI = VCC or 0
VI = VCC or 0,
0.33
TA = 25°C
SN54HC74,
SN74HC74
IO = 0
±0.1
6V
SN54HC74
Cpd
No load
nA
4
6V
80
SN74HC74
Ci
±100
±1000
TA = 25°C
ICC
0.26
0.4
SN74HC74
II
V
0.33
TA = 25°C
IOL = 5.2 mA
UNIT
3.84
TA = 25°C
IOH = –5.2 mA
MAX
µA
40
2 V to 6 V
3
2 V to 6 V
35
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pF
pF
5
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6.6 Timing Requirements
over recommended operating free-air temperature range, TA = 25°C (unless otherwise noted)
fclock
Clock frequency
VCC
TA
TA = 25°C
6
2V
SN54HC74
4.2
4.5 V
6V
2V
PRE or CLR low
4.5 V
6V
tw
Pulse duration
2V
CLK high or low
4.5 V
6V
2V
Data
4.5 V
6V
tsu
Setup time before
CLK↑
2V
PRE or CLR inactive
4.5 V
6V
6
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MIN
MAX
SN74HC74
5
TA = 25°C
31
SN54HC74
21
SN74HC74
25
TA = 25°C
0
36
SN54HC74
0
25
SN74HC74
0
29
TA = 25°C
100
SN54HC74
150
SN74HC74
125
TA = 25°C
20
SN54HC74
30
SN74HC74
25
TA = 25°C
14
SN54HC74
25
SN74HC74
21
TA = 25°C
80
SN54HC74
120
SN74HC74
100
TA = 25°C
16
SN54HC74
24
SN74HC74
20
TA = 25°C
14
SN54HC74
20
SN74HC74
17
TA = 25°C
100
SN54HC74
150
SN74HC74
125
TA = 25°C
20
SN54HC74
30
SN74HC74
25
TA = 25°C
17
SN54HC74
25
SN74HC74
21
TA = 25°C
25
SN54HC74
40
SN74HC74
30
TA = 25°C
5
SN54HC74
8
SN74HC74
6
TA = 25°C
4
SN54HC74
7
SN74HC74
5
UNIT
MHz
ns
ns
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Timing Requirements (continued)
over recommended operating free-air temperature range, TA = 25°C (unless otherwise noted)
VCC
th
Hold time, data after CLK↑
TA
MIN
2V
0
4.5 V
0
6V
0
MAX
UNIT
ns
6.7 Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
fmax
4.5 V
6V
TA
MIN
TYP
TA = 25°C
6
10
SN54HC74
4.2
SN74HC74
6
TA = 25°C
31
SN54HC74
21
SN74HC74
25
TA = 25°C
36
SN54HC74
25
SN74HC74
29
TA = 25°C
2V
50
MHz
60
70
SN54HC74
PRE or CLR
Q or Q
4.5 V
290
20
SN54HC74
6V
tpd
Q or Q
4.5 V
59
49
70
250
SN74HC74
220
20
50
SN74HC74
44
15
SN54HC74
TA = 25°C
37
28
Q or Q
4.5 V
95
8
15
SN54HC74
22
SN74HC74
19
TA = 25°C
6V
75
110
SN74HC74
tt
30
42
SN54HC74
TA = 25°C
6
19
SN74HC74
16
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ns
13
SN54HC74
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ns
35
SN54HC74
SN74HC74
2V
175
SN54HC74
TA = 25°C
6V
39
SN74HC74
TA = 25°C
CLK
58
15
SN54HC74
TA = 25°C
2V
46
69
SN74HC74
TA = 25°C
230
345
SN74HC74
TA = 25°C
MAX UNIT
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6.8 Typical Characteristics
75
60
45
tpd(ns)
30
15
0
0
1.5
3
4.5
6
7.5
VCC (V)
Figure 1. Typical Propagation Delay - CLK to Q
8
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7 Parameter Measurement Information
From Output
Under Test
Test
Point
VCC
High-Level
Pulse
50%
50%
0V
CL = 50 pF
(see Note A)
tw
VCC
Low-Level
Pulse
LOAD CIRCUIT
50%
50%
0V
VOLTAGE WAVEFORMS
PULSE DURATIONS
Reference
Input
VCC
50%
Input
VCC
50%
50%
0V
0V
tsu
Data
Input
50%
10%
90%
th
tPLH
90%
tr
VCC
50%
10% 0 V
In-Phase
Output
90%
50%
10%
90%
tr
tf
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
tPHL
tPHL
Out-of-Phase
Output
VOH
50%
10%
VOL
tf
tPLH
90%
50%
10%
50%
10%
90%
tf
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
A.
CL includes probe and test-fixture capacitance.
B.
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having
the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C.
For clock inputs, fmax is measured when the input duty cycle is 50%.
D.
The outputs are measured one at a time with one input transition per measurement.
E.
tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
Figure 3 describes the SNx4HC74 devices. As the SNx4HC74 is a dual D-Type positive-edge-triggered flip-flop
with clear and preset, the diagram below describes one of the two device flip-flops.
8.2 Functional Block Diagram
PRE
CLK
C
C
Q
TG
C
C
C
C
C
D
TG
TG
TG
Q
C
C
C
CLR
Figure 3. Logic Diagram (Positive Logic)
8.3 Feature Description
The SNx4HC74 inputs accept voltage levels up to 5.5 V. Refer to the Recommended Operating Conditions for
appropriate input high and low logic levels.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SNx4HC74.
Table 1. Function Table
INPUTS
(1)
10
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H (1)
H (1)
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive
(high) level.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
The resistor and capacitor at the CLR pin are optional. If they are not used, the CLR pin should be connected
directly to VCC to be inactive.
9.2 Typical Application
5V
5V
5V
SN74LVC1G17
SN74HC74
Figure 4. Device Power Button Circuit
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. Outputs may be combined to produce higher drive, but the
high drive will also create faster edges into light loads. Because of this, routing and load conditions should be
considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifications, see (Δt/ΔV) in Recommended Operating Conditions table.
– For specified high and low levels, see (VIH and VIL) in Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommended Output Conditions:
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Series resistors on the output may be used if the user desires to slow the output edge signal or limit the
output current.
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Typical Application (continued)
9.2.3 Application Curve
75
60
45
tpd(ns)
30
15
0
0
1.5
3
4.5
6
7.5
VCC (V)
Figure 5. Typical Propagation Delay - CLR to Q
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table. Each VCC terminal should have a good bypass capacitor to prevent
power disturbance. For devices with a single supply, a 0.1-μF capacitor is recommended and if there are multiple
VCC terminals then .01-μF or .022-μF capacitors are recommended for each power terminal. It is acceptable to
parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are
commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible
for best results.
12
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11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 6 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally they are tied to GND or
VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it disables the output section of the part when asserted.
This pin keeps the input section of the I/Os from being disabled and floated.
11.2 Layout Example
Vcc
Input
Unused Input
Output
Unused Input
Output
Input
Figure 6. Layout Diagram
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54HC74
Click here
Click here
Click here
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SN74HC74
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12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
14
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Product Folder Links: SN54HC74 SN74HC74
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