TI1 LM26480QSQX-CF/NOPB Lm26480 externally programmable dual high-current step-down dc/dc and dual linear regulator Datasheet

LM26480
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LM26480 Externally Programmable Dual High-Current Step-Down DC/DC and Dual Linear
Regulators
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FEATURES
DESCRIPTION
•
The LM26480 is a multi-functional Power
Management Unit, optimized for low-power digital
applications. This device integrates two highly
efficient 1.5A step-down DC/DC converters and two
300 mA linear regulators. The LM26480 is offered in
a tiny 4 x 4 x 0.8mm WQFN-24 pin package.
1
2
•
•
•
•
•
•
•
•
Compatible with Advanced Applications
Processors and FPGAs
2 LDOs for Powering Internal Processor
Functions and I/Os
Precision Internal Reference
Thermal Overload Protection
Current Overload Protection
24-lead 4 × 4 × 0.8mm WQFN Package
External Power-On-Reset Function for Buck1
and Buck2
Undervoltage Lock-Out Detector to Monitor
Input Supply Voltage
Note: LM26480Q is an Automotive-Grade
Product that is AECQ-100 Grade 1 Qualified.
KEY SPECIFICATIONS
•
APPLICATIONS
•
•
•
Core Digital Power
Applications Processors
Peripheral I/O Power
•
Step-Down DC/DC Converter (Buck)
– 1.5A output current
– VOUT from:
– Buck1 : 0.8V–2.0V @ 1.5A
– Buck2 : 1.0V–3.3V @ 1.5A
– Up to 96% efficiency
– ±3% FB voltage accuracy
– 2 MHz PWM switching frequency
– PWM - PFM automatic mode change under
low loads
– Automatic soft start
Linear Regulators (LDO)
– VOUT of 1.0V–3.5V
– ±3% FB voltage accuracy
– 300 mA output current
– 25 mV (typ) dropout
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Typical Application Circuit
VINLDO12
SYNC
1 µF
ENLDO1
nPOR
100k
ENLDO2
VIN1
10 µF
ENSW1
2.2 µH
ENSW2
SW1
VOUTLDO1
0.47 µF
R1
C1
R1
C2
R2
10 µF
FB1
LDO1_FB
R2
GND_SW1
VINLDO1
LM26480
1 µF
VIN2
VINLDO2
10 µF
1 µF
2.2 µH
VOUTLDO2
SW2
R1
0.47 µF
C1
R1
C2
R2
FB2
LDO2_FB
R2
10 µF
GND_SW2
GND_L
GND_C
DAP
2
AVDD
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1 µF
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LM26480 PMIC
10 µF
10 µF
19
VIN1
10
1 µF
VIN2
24
1 µF
VINLDO1
1
1 µF
AVDD
1 µF
VINLDO2
CVDD
4.7 µF
VINLDO12
Input
Voltage
13
6
LSW 1 2.2 µH
OSC
BUCK1
AVDD
2
SYNC
VBUCK1
5
SW1
FB1
8
C1
R1
C2
R2
1.2V
CSW1
10 µ F
17
ENLDO1
LSW 2 2.2 µH
Power
ONOFF
Logic
16
ENLDO2
7
ENSW1
BUCK2
AVDD
VBUCK2
14
SW2
FB2
11
C1
R1
C2
R2
3.3V
CSW2
10 µ F
12
VINLDO1
ENSW2
Thermal
Shutdown
LDO1
LDO1
RESET
VINLDO12
20
FBL1
21
R1
3.3V
CLDO1
0.47 µF
R2
BIAS
VINLDO2
LDO2
LDO2
Logic
Control and
registers
23
FBL2
22
FB1
FB2
1.8V
R1
CLDO2
0.47 µF
R2
VDD
100k
Power On
Reset
4
GND_SW1
15
GND_SW2
9
GND_C
3
nPOR
18
GND_L
Figure 1. Application Circuit
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Connection Diagram
18
17
16
15
14
13
19
12
20
11
21
10
22
9
23
8
24
7
1
2
3
4
5
6
Figure 2. 24-Lead WQFN Package (top view)
Table 1. Default Options
Order Suffix
Spec
Oscillator
Frequency
Buck Modes
nPOR Delay
UVLO
Sync
AECQ
SQ-AA
NOPB
2.0 MHz
Auto-Mode
60 mS
Enabled
Disabled
No
QSQ-AA
NOPB
2.0 MHz
Auto-Mode
60 mS
Enabled
Disabled
Grade 1
QSQ-CF
NOPB
2.1 MHz
Forced PWM
60 mS
Disabled
Disabled
Grade 1
SQ-BF
NOPB
2.0 MHz
Forced PWM
60 mS
Enabled
Enabled
No
QSQ-8D
NOPB
2.1 MHz
Forced PWM
130 µS
Enabled
Disabled
Grade 1
Table 2. PIN DESCRIPTIONS (1)
WQFN Pin
No.
Name
I/O
Type
1
VINLDO12
I
PWR
Analog Power for Internal Functions (VREF, BIAS, I2C, Logic)
2
SYNC
I
G/(D)
Frequency Synchronization pin which allows the user to connect an external clock
signal to synchronize the PMIC internal oscillator. Default OFF and must be
grounded when not used. Part number LM26480SQ-BF has this feature enabled.
Please contact Texas Instruments Sales Office/Distributors for availability of
LM26480SQ-BF.
3
NPOR
O
D
nPOR Power on reset pin for both Buck1 and Buck 2. Open drain logic output 100K
pullup resistor. nPOR is pulled to ground when the voltages on these supplies are
not good. See Flexible Power-On Reset (i.e., Power Good with Delay) section for
more info.
4
GND_SW1
G
G
Buck1 NMOS Power Ground
5
SW1
O
PWR
Buck1 switcher output pin
6
VIN1
I
PWR
Power in from either DC source or Battery to Buck1
7
ENSW1
I
D
Enable Pin for Buck1 switcher, a logic HIGH enables Buck1. Pin cannot be left
floating.
(1)
4
Description
8
FB1
I
A
Buck1 input feedback terminal
9
GND_C
G
G
Non-switching core ground pin
10
AVDD
I
PWR
11
FB2
I
A
Buck2 input feedback terminal
12
ENSW2
I
D
Enable Pin for Buck2 switcher, a logic HIGH enables Buck2. Pin cannot be left
floating.
13
VIN2
I
PWR
A: Analog Pin
D: Digital Pin
Analog Power for Buck converters
Power in from either DC source or Battery to Buck2
G: Ground Pin
PWR: Power Pin
I: Input Pin
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I/O: Input/Output Pin
O: Output Pin
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Table 2. PIN DESCRIPTIONS(1) (continued)
WQFN Pin
No.
Name
I/O
Type
Description
14
SW2
O
PWR
15
GND_SW2
G
G
Buck2 NMOS
16
ENLDO2
I
D
LDO2 enable pin, a logic HIGH enables LDO2. Pin cannot be left floating.
17
ENLDO1
I
D
LDO1 enable pin, a logic HIGH enables LDO1. Pin cannot be left floating.
18
GND_L
G
G
LDO ground
19
VINLDO1
I
PWR
Power in from either DC source or battery to LDO1
20
LDO1
O
PWR
LDO1 Output
21
FBL1
I
A
LDO1 Feedback Terminal
22
FBL2
I
A
LDO2 Feedback Terminal
23
LDO2
O
PWR
LDO Output
24
VINLDO2
I
PWR
Power in from either DC source or battery to LDO2.
DAP
DAP
GND
GND
Connection isn't necessary for electrical performance, but it is recommended for
better thermal dissipation.
Buck2 switcher output pin
Power Block Operation (1)
Note
Power Block Input
Enabled
Disabled
VINLDO12
VIN+
VIN+
Always Powered
AVDD
VIN+
VIN+
Always Powered
VIN1
VIN+
VIN+ or 0V
VIN2
VIN+
VIN+ or 0V
VINLDO1
≤ VIN+
≤ VIN+
If Enabled, Min VIN is 1.74V
VINLDO2
≤ VIN+
≤ VIN+
If Enabled, Min VIN is 1.74V
(1)
VIN+ is the largest potential voltage on the device.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2) (3)
VINLDO12, VIN1, AVDD, VIN2, VINLDO1, VINLDO2, ENSW1, FB1, FB2,
ENSW2, ENLDO1, ENLDO2, SYNC, FBL1, FBL2
−0.3V to +6V
GND to GND SLUG
±0.3V
Power Dissipation (PD_MAX)
(TA=85°C, TMAX=125°C ) (4)
1.17W
Junction Temperature (TJ-MAX)
150°C
−65°C to +150°C
Storage Temperature Range
Maximum Lead Temperature (Soldering)
ESD Ratings
Human Body Model
(1)
(2)
(3)
(4)
(5)
260°C
(5)
2 kV
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is specified. Operating Ratings do not imply ensured performance limits. For performance limits and
associated test conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
All voltages are with respect to the potential at the GND pin.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP − (θJA × PD-MAX). See Application Notes.
The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MILSTD - 883 3015.7)
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Operating Ratings: Bucks
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(1) (2) (3)
VIN
2.8V to 5.5V
VEN
0 to (VIN + 0.3V)
Junction Temperature (TJ) Range
Ambient Temperature (TA) Range
(1)
(2)
(3)
(4)
–40°C to +125°C
(4)
−40°C to +85°C
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is specified. Operating Ratings do not imply ensured performance limits. For performance limits and
associated test conditions, see the Electrical Characteristics.
All voltages are with respect to the potential at the GND pin.
Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
Thermal Properties (1) (2) (3)
Junction-to-Ambient Thermal Resistance (θJA), RTW0024A
(1)
(2)
(3)
6
34.1°C/W
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160°C (typ.) and
disengages at TJ = 140°C (typ.)
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP − (θJA × PD-MAX). See Application Notes.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
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General Electrical Characteristics (1) (2) (3) (4) (5)
Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing
in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C.
Symbol
IQ
VPOR
Parameter
Conditions
VINLDO12 Shutdown Current
VIN = 3.6V
Power-On Reset Threshold
VDD Falling Edge
TSD
Thermal Shutdown Threshold
(4)
TSDH
Themal Shutdown Hysteresis
(4)
UVLO
(1)
(2)
(3)
(4)
(5)
Under Voltage Lock Out
Min
Typ
Max
0.5
(5)
Units
µA
1.9
V
160
°C
20
°C
Rising
2.9
V
Failing
2.7
V
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is speficied. Operating Ratings do not imply ensure performance limits. For performance limits and
associated test conditions, see the Electrical Characteristics.
All voltages are with respect to the potential at the GND pin.
Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.
Specified by design. Not production tested.
VPOR is voltage at which the EPROM resets. This is different from the UVLO on VINLDO12, which is the voltage at which the
regulators shut off; and is also different from the nPOR function, which signals if the regulators are in a specified range.
Low Drop Out Regulators, LDO1 and LDO2
Unless otherwise noted, VIN = 3.6V, CIN = 1.0 µF, COUT = 0.47 µF. Typical values and limits appearing in normal type apply for
TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to
+125°C. (1) (2) (3) (4)
Symbol
Parameter
VIN
Operational Voltage Range
VFB
FB Voltage Accuracy
Conditions
VINLDO1 and VINLDO2 PMOS
pins (5)
Min
Typ
Max
Units
1.74
5.5
V
−3
3
%
Line Regulation
VIN = (VOUT + 0.3V) to 5.0V
(6)
Load Current = 1 mA
0.15
%/V
Load Regulation
VIN = 3.6V,
Load Current = 1 mA to IMAX
0.011
%/mA
ISC
Short Circuit Current Limit
LDO1-2, VOUT = 0V
VIN – VOUT
Dropout Voltage
Load Current = 50 mA
PSRR
Power Supply Ripple Rejection
F = 10 kHz, Load Current = IMAX
45
dB
θn
Supply Output Noise
10 Hz < F < 100 kHz
150
µVrms
Quiescent Current “On”
IOUT = 0 mA
40
150
µA
Quiescent Current “On”
IOUT = 300 mA
60
200
µA
Quiescent Current “Off”
EN is de-asserted
0.03
1
Turn On Time
Start up from shut-down
300
µsec
ΔVOUT
Iq
TON
COUT
Output Capacitor
(6)
(7)
25
(7)
mA
200
mV
µA
Capacitance for stability 0°C ≤ TJ
≤ 125°C
0.33
0.47
µF
−40°C ≤ TJ ≤ 125°C
0.68
1.0
µF
ESR (Equivalent Series
Resistance)
(1)
(2)
(3)
(4)
(5)
500
5
500
mΩ
All voltages are with respect to the potential at the GND pin.
Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.
CIN, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
The device maintains a stable, regulated output voltage without a load.
Pins 24, 19 can operate from VIN min of 1.74V to a VIN max of 5.5V. This rating is only for the series pass PMOS power FET. It allows
the system design to use a lower voltage rating if the input voltage comes from a buck output.
VIN minimum for line regulation values is 1.8V.
Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its
nominal value.
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Buck Converters SW1, SW2
Unless otherwise noted, VIN = 3.6V, CIN = 10 µF, COUT = 10 µF, LOUT = 2.2 µH. Typical values and limits appearing in normal
type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation,
−40°C to +125°C. ( (1) (2) (3) (4) (5) (6)
Symbol
VFB (6)
Parameter
Conditions
Min
VOUT
Units
+3
%
Line Regulation
0.089
%/V
0.0013
%/mA
Load Regulation
100 mA < IO < IMAX
Efficiency
Load Current = 250 mA
ISHDN
Shutdown Supply Current
EN is de-asserted
96
%
0.01
1
Default oscillator frequency = 2.0
MHz
1.6
2.0
2.4
Default oscillator frequency = 2.1
MHz
1.7
2.1
2.5
Buck1 Peak Switching Current Limit
2.0
2.4
Buck2 Peak Switching Current Limit
2.0
2.4
Internal Oscillator Frequency
IPEAK
Max
2.8 < VIN < 5.5
IO =10 mA
Eff
fOSC
Typ
−3
Feedback Voltage
µA
MHz
No load PFM Mode
33
A
µA
Iq
Quiescent Current “On”
RDSON (P)
Pin-Pin Resistance PFET
200
400
mΩ
RDSON (N)
Pin-Pin Resistance NFET
180
400
mΩ
TON
Turn On Time
Start up from shut-down
CIN
Input Capacitor
Capacitance for stability
10
µF
CO
Output Capacitor
Capacitance for stability
10
µF
(1)
(2)
(3)
(4)
(5)
(6)
No load PWM Mode (Forced PWM)
2
mA
500
µsec
All voltages are with respect to the potential at the GND pin.
Min and Max limits are speficified by design, test, or statistical analysis. Typical numbers represent the most likely norm.
CIN, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
The device maintains a stable, regulated output voltage without a load.
Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT.
VIN ≥ VOUT + RDSON(P) (IOUT + 1/2 IRIPPLE). If these conditions are not met, voltage regulation will degrade as load increases.
I/O Electrical Characteristics
Unless otherwise noted: Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface
type apply over the entire junction temperature range for operation, TJ = −40°C to +125°C.
Symbol
Parameter
VIL
Input Low Level
VIH
Input High Level
Conditions
Limit
Min
Max
0.4
0.7*VDD
Units
V
V
Power On Reset Threshold/Function (POR)
Symbol
Parameter
Conditions
Min
Typ
nPOR
nPOR = Power on reset for Buck1 and
Buck2
Default = 60 mS
Default = 130 µS
130
nPOR
Threshold
Percentage of Target voltage Buck1 or
Buck2
VBUCK1 AND VBUCK2 rising
92
VBUCK1 OR VBUCK2 falling
82
VOL
Output Level Low
Load = IOL = 500 µA
8
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Max
Units
60
mS
µS
0.23
%
0.5
V
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Typical Performance Characteristics — LDO
2.00
1.50
1.00
0.50
0.00
-0.50
-1.00
-1.50
-2.00
VIN
VOUT CHANGE (%)
VOUT CHANGE (%)
Output Voltage Change
vs
Temperature (LDO1)
VIN = 3.6V, VOUT = 2.5V, 100 mA load
Output Voltage Change
vs
Temperature (LDO2)
= 3.6V, VOUT = 1.8V, 100 mA load
2.00
1.50
1.00
0.50
0.00
-0.50
-1.00
-1.50
-2.00
-50 -35 -20 -5 10 25 40 55 70 85 100
-50 -35 -20 -5 10 25 40 55 70 85 100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 3.
Figure 4.
Load Transient
3.6 VIN, 2.5VOUT, 0 – 150 mA load
Load Transient
3.6 VIN, 2.5VOUT, 150–300 mA load
Figure 5.
Figure 6.
Line Transient (LDO1)
3.6 - 4.2 VIN, 2.5 VOUT, 100 mA load
Line Transient (LDO2)
3.6 – 4.2 VIN, 1.8VOUT, 150 mA load
Figure 7.
Figure 8.
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Typical Performance Characteristics — LDO (continued)
10
Enable Start-up time (LDO1)
0-3.6 VIN, 2.5 VOUT, 1 mA load
Enable Start-up time (LDO2)
0 – 3.6 VIN, 1.8VOUT, 1 mA load
Figure 9.
Figure 10.
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Typical Performance Characteristics — Buck
VIN = 2.8V to 5.5V, TA = 25°C
Output Voltage
vs.
Supply Voltage
(VOUT = 1.2V)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-40
VIN = 5.5V
VOUT (V)
TEMPERATURE (°C)
Shutdown Current
vs.
Temp
VIN = 3.6V
VIN = 2.8V
-20
0
20
40
60
80
1.250
1.245
1.240
1.235
1.230
1.225
1.220
1.215
1.210
100
LOAD = 1.5A
LOAD = 750 mA
LOAD = 20 mA
2.5
3.0
3.5
5.0
Figure 12.
Output Voltage
vs.
Supply Voltage
(VOUT = 2.0V)
Output Voltage
vs.
Supply Voltage
(VOUT = 3.0V)
LOAD = 1.5A
5.5
LOAD = 1.5A
3.080
LOAD = 750 mA
LOAD = 750 mA
VOUT (V)
VOUT (V)
4.5
Figure 11.
3.090
2.10
2.09
2.08
2.07
2.06
2.05
2.04
2.03
2.02
2.01
2.00
4.0
SUPPLY VOLTAGE (V)
SHUTDOWN CURRENT (nA)
LOAD = 20 mA
3.070
3.060
3.050
LOAD = 20 mA
3.040
3.0
3.5
4.0
4.5
5.0
5.5
4.0
4.3
4.6
4.9
5.2
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 13.
Figure 14.
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Typical Performance Characteristics — Buck
Output Current transitions from PFM mode to PWM mode for Buck 1
Efficiency
vs.
Output Current
(VOUT = 1.2V, L = 2.2 µH)
Efficiency
vs.
Output Current
(VOUT = 2.0V, L = 2.2 µH)
100
100
VIN = 2.8V
EFFICIENCY (%)
EFFICIENCY (%)
90
VIN = 3.6V
80
70
VIN = 5.5V
60
50
90 VIN = 2.8V
VIN = 3.6V
80
VIN = 5.5V
70
60
50
1
10
100
1000
10000
1
OUTPUT CURRENT (mA)
10
100
1000
10000
OUTPUT CURRENT (mA)
Figure 15.
Figure 16.
Output Current transitions from PWM mode to PFM mode for Buck 2
Efficiency
vs.
Output Current
(VOUT = 3.0V, L = 2.2 µH)
Efficiency
vs.
Output Current
(VOUT = 3.5V, L = 2.2 µH)
100
100
90
VIN = 5.5V
EFFICIENCY (%)
EFFICIENCY (%)
90 VIN = 3.6V
VIN = 4.2V
VIN = 5.5V
80
70
60
80
VIN = 4.2V
70
60
50
1
10
100
1000
10000
50
1
OUTPUT CURRENT (mA)
100
1000
10000
OUTPUT CURRENT (mA)
Figure 17.
12
10
Figure 18.
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Typical Performance Characteristics — Buck
VIN= 3.6V, TA = 25°C, VOUT = 1.2V unless otherwise noted
Load Transient Response
VOUT = 1.2V (PWM Mode)
Mode Change by Load Transients
VOUT = 1.2V (PWM to PFM)
Figure 19.
Figure 20.
Line Transient Response
VIN = 3.6 – 4.2V, VOUT = 1.2V, 250 mA load
Line Transient Response
VIN = 3.0 – 3.6V, VOUT = 3.0V, 250 mA load
Figure 21.
Figure 22.
Start up into PWM Mode
VOUT = 1.2V, 1.5A load
Start up into PWM Mode
VOUT = 3.0 V, 1.5A load
Figure 23.
Figure 24.
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Typical Performance Characteristics — Buck (continued)
VIN= 3.6V, TA = 25°C, VOUT = 1.2V unless otherwise noted
14
Start up into PFM Mode
VOUT = 1.2V, 30 mA load
Start up into PFM Mode
VOUT = 3.0V, 30 mA load
Figure 25.
Figure 26.
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DC/DC CONVERTERS
Overview
The LM26480 provides the DC/DC converters that supply the various power needs of the application by means
of two linear low dropout regulators, LDO1 and LDO2, and two buck converters, SW1 and SW2. The table here
under lists the output characteristics of the various regulators.
Table 3. Supply Specification
Output
Supply
Load
LDO1
LDO2
VOUT Range (V)
IMAX
Maximum Output Current (mA)
analog
1.0 to 3.5
300
analog
1.0 to 3.5
300
SW1
digital
0.8 to 2.0
1500
SW2
digital
1.0 to 3.3
1500
Linear Low Dropout Regulators (LDOs)
LDO1 and LDO2 are identical linear regulators targeting analog loads characterized by low noise requirements.
LDO1 and LDO2 are enabled through the ENLDO pin.
VLDO
VIN
LDO_FB
+
ENLDO
VREF
GND
No-Load Stability
The LDOs will remain stable and in regulation with no external load. This is an important consideration in some
circuits, for example, CMOS RAM keep-alive applications.
SW1, SW2: Synchronous Step-Down Magnetic DC/DC Converters
Functional Description
The LM26480 incorporates two high-efficiency synchronous switching buck regulators, SW1 and SW2, that
deliver a constant voltage from a single Li-Ion battery to the portable system processors. Using a voltage mode
architecture with synchronous rectification, both bucks have the ability to deliver up to 1500 mA depending on the
input voltage and output voltage (voltage head room), and the inductor chosen (maximum current capability).
There are three modes of operation depending on the current required - PWM, PFM, and shutdown. PWM mode
handles current loads of approximately 70 mA or higher, delivering voltage precision of +/-3% with 90% efficiency
or better. Lighter output current loads cause the device to automatically switch into PFM for reduced current
consumption (IQ = 33 µA typ.) and a longer battery life. The Standby operating mode turns off the device, offering
the lowest current consumption. PWM or PFM mode is selected automatically or PWM mode can be forced
through the setting of the buck control register.
Both SW1 and SW2 can operate up to a 100% duty cycle (PMOS switch always on) for low drop out control of
the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage.
Additional features include soft-start, under-voltage lock-out, current overload protection, and thermal overload
protection.
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Circuit Operation Description
A buck converter contains a control block, a switching PFET connected between input and output, a synchronous
rectifying NFET connected between the output and ground (BCKGND pin) and a feedback path. During the first
portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow
from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a
ramp with a slope of
VIN - VOUT
(1)
L
by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET
switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor
draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor
current down with a slope of
-VOUT
(2)
L
The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage
across the load.
Sync Function
The LM26480SQ-BF is the only version of the part that has the ability to use an external oscillator. The source
must be 13 MHz nominal and operate within a range of 15.6 MHz and 10.4 MHz, proportionally the same limits
as the 2.0 MHz internal oscillator. The LM26480SQ-BF has an internal divider which will divide the speed down
by 6.5 to the nominal 2MHz and use it for the regulators. This SYNC function replaces the internal oscillator and
works in forced PWM only. The buck regulators no longer have the PFM function enabled. When the
LM26480SQ-BF is sold with this feature enabled, the part will not function without the external oscillator present.
Please contact Texas Instruments Sales Office/Distributors for availability of LM26480SQ-BF.
PWM Operation
During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This
allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional
to the input voltage. To eliminate this dependence, feed forward voltage inversely proportional to the input
voltage is introduced.
Internal Synchronous Rectification
While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier
diode.
Current Limiting
A current limit feature allows the converter to protect itself and external components during overload conditions.
PWM mode implements current limiting using an internal comparator that trips at 2.0A for both bucks (typ). If the
output is shorted to ground the device enters a timed current limit mode where the NFET is turned on for a
longer duration until the inductor current falls below a low threshold, ensuring inductor current has more time to
decay, thereby preventing runaway.
PFM Operation
At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply
current to maintain high efficiency.
The part will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or
more clock cycles:
A. The inductor current becomes discontinuous
or
B. The peak PMOS switch current drops below the IMODE level
16
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(Typically IMODE < 66 mA +
VIN
)
160:
(3)
During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage
during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy
load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output
FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output
voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on.
It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the IPFM level
set for PFM mode. The typical peak current in PFM mode is:
IPFM = 66 mA +
VIN
80:
(4)
Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps
to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output
voltage is below the ‘high’ PFM comparator threshold (see Figure 27), the PMOS switch is again turned on and
the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM
threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output
switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this
‘sleep’ mode is less than 30 µA, which allows the part to achieve high efficiencies under extremely light load
conditions. When the output drops below the ‘low’ PFM threshold, the cycle repeats to restore the output voltage
to ~1.6% above the nominal PWM output voltage.
If the load current should increase during PFM mode (see Figure 27) causing the output voltage to fall below the
‘low2’ PFM threshold, the part will automatically transition into fixed-frequency PWM mode.
SW1, SW2 Control
SW1 and SW2 are enabled/disabled through the external enable pins.
The Modulation mode PWM/PFM is by default automatic and depends on the load as described above in the
functional description. The modulation mode can be factory trimmed, forcing the buck to operate in PWM mode
regardless of the load condition.
High PFM Threshold
~1.016*Vout
PFM Mode at Light Load
xis
Z-A
Load current
increases
ZAxis
Z-Axis
PFET on
until
IPFM limit
reached
Low1 PFM Threshold
~1.008*Vout
ZA
NFET on
drains
conductor
current
until
I inductor = 0
High PFM
Voltage
Threshold
reached,
go into
sleep mode
xis
Current load
increases,
Low PFM
Threshold,
turn on
PFET
draws VOUT
towards
Low2 PFM
Threshold
Low2 PFM Threshold
Vout
Low2 PFM Threshold,
switch back to PWM mode
PWM Mode at Moderate to
Heavy Loads
ZAx
is
-18
Figure 27.
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Shutdown Mode
During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The
NFET switch will be on in shutdown to discharge the output. When the converter is enabled, soft start is
activated. It is recommended to disable the converter during the system power up and under voltage conditions
when the supply is less than 2.8V.
Soft Start
The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus
reducing startup stresses and surges. The two LM26480 buck converters have a soft-start circuit that limits inrush current during startup. During startup the switch current limit is increased in steps. Soft start is activated
only if EN goes from logic low to logic high after VIN reaches 2.8V. Soft start is implemented by increasing switch
current limit in steps of 250 mA, 500 mA, 950 mA and 2A for both bucks (typ. switch current limit). The startup
time thereby depends on the output capacitor and load current demanded at start-up.
Low Dropout Operation
The LM26480 can operate at 100% duty cycle (no switching; PMOS switch completely on) for low dropout
support of the output voltage. In this way the output voltage will be controlled down to the lowest possible input
voltage. When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV. The
minimum input voltage needed to support the output voltage is
VIN, MIN = ILOAD * (RDSON, PFET + RINDUCTOR) + VOUT
ILOAD
Load current
RDSON, PFET
Drain to source resistance of
PFET switch in the triode region
RINDUCTOR
Inductor resistance
Flexible Power-On Reset (i.e., Power Good with Delay)
The LM26480 is equipped with an internal Power-On-Reset (“POR”) circuit which monitors the output voltage
levels on bucks 1 and 2. The nPOR is an open drain logic output which is logic LOW when either of the buck
outputs are below 92% of the rising value, or when one or both outputs fall below 82% of the desired value. The
time delay between output voltage level and nPOR is enabled is (130 µs, 60 ms, 100 ms, 200 ms), 60 ms by
default. For any other delay option, other than the default, please consult a Texas Instruments Sales
Representative. The system designer can choose the external pull-up resistor (i.e. 100 kΩ ) for the nPOR pin.
18
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t1
t2
Case 1
EN1
EN2
RDY1
RDY2
0V
Counter
delay
NPOR
t1
t2
Case 2
EN1
EN2
0V
RDY1
RDY2
Counter
delay
NPOR
t1
t2
Case 3
EN1
EN2
RDY1
RDY2
Counter
delay
NPOR
Figure 28. NPOR with Counter Delay
The above diagram shows the simplest application of the Power-On Reset, where both switcher enables are tied
together. In Case 1, EN1 causes nPOR to transition LOW and triggers the nPOR delay counter. If the power
supply for Buck2 does not come on within that period, nPOR will stay LOW, indicating a power fail mode. Case 2
indicates the vice versa scenario if Buck1 supply did not come on. In both cases the nPOR remains LOW. Case
3 shows a typical application of the Power-On Reset, where both switcher enables are tied together. Even if
RDY1 ramps up slightly faster than RDY2 (or vice versa), the nPOR signal will trigger a programmable delay
before going HIGH, as explained below.
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t0
t1
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t2
t3
t4
EN1
RDY1
Counter
delay
NPOR
Counter
delay
EN2
RDY2
Figure 29. Faults Occurring in Counter Delay After Startup
The above timing diagram details the Power Good with delay with respect to the enable signals EN1, and EN2.
The RDY1, RDY2 are internal signals derived from the output of two comparators. Each comparator has been
trimmed as follows:
Comparator Level
Buck Supply Level
HIGH
Greater than 92%
LOW
Less than 82%
The circuits for EN1 and RDY1 are symmetrical to EN2 and RDY2, so each reference to EN1 and RDY1 will also
work for EN2 and RDY2 and vice versa.
If EN1 and RDY1 signals are High at time t1, then the RDY1 signal rising edge triggers the programmable delay
counter (130 μs, 60 ms, 100 ms, 200 ms). This delay forces nPOR LOW between time interval t1 and t2. NPOR
is then pulled high after the programmable delay is completed. Now if EN2 and RDY2 are initiated during this
interval the nPOR signal ignores this event.
If either RDY1or RDY2 were to go LOW at t3 then the programmable delay is triggered again.
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t0
t1
t2
t3
t4
EN1
RDY1
Counter
delay
NPOR
Case 1:
EN2
RDY2
Mask Time
Counter
delay
Mask
Window
NPOR
Case 2:
EN2
RDY2
0V
Mask
Window
Mask Time
Counter
delay
NPOR
Figure 30. NPOR Mask Window
In Case 1, we see that case where EN2 and RDY2 are initiated after triggered programmable delay. To prevent
the nPOR being asserted again, a masked window (5 ms) counter delay is triggered off the EN2 rising edge.
NPOR is still held HIGH for the duration of the mask, whereupon the nPOR status afterwards will depend on the
status of both RDY1 and RDY2 lines.
In Case 2, we see the case where EN2 is initiated after the RDY1 triggered programmable delay, but RDY2
never goes HIGH (Buck2 never turns on). Normal operation operation of nPOR occurs wilth respect to EN1 and
RDY1, and the nPOR signal is held HIGH for the duration of the mask window. We see that nPOR goes LOW
after the masking window has timed out because it is now dependent on RDY1 and RDY2, where RDY2 is LOW.
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Delay Mask Counter
EN1
RDY1
EN2
RDY2
S
Q
R
Q
NPOR
Delay
POR
Delay Mask Counter
Figure 31. Design Implementation of the Flexible Power-On Reset
Design implementation of the flexible power-on reset. An internal power-on reset of the IC is used with EN1 and
EN2 to produce a reset signal (LOW) to the delay timer nPOR. EN1 and RDY1 or EN2 and RDY2 are used to
generate the set signal (HIGH) to the delay timer. S=R=1 never occurs. The mask timers are triggered off EN1
and EN2 which are gated with RDY1, and RDY2 to generate outputs to the final AND gate to generate the
nPOR.
Under Voltage Lock Out
The LM26480 features an “under voltage lock out circuit”. The function of this circuit is to continuously monitor
the raw input supply voltage (VINLDO12) and automatically disables the four voltage regulators whenever this
supply voltage is less than 2.8 VDC.
The circuit incorporates a bandgap based circuit that establishes the reference used to determine the 2.8 VDC
trip point for a VIN OK – Not OK detector. This VIN OK signal is then used to gate the enable signals to the four
regulators of the LM26480. When VINLDO12 is greater than 2.8 VDC the four enables control the four
regulators, when VINLDO12 is less than 2.8 VDC the four regulators are disabled by the VIN detector being in
the “Not OK” state. The circuit has built in hysteresis to prevent chattering occurring.
Application Notes
External Component Selection
Buck
LDO
0.47 µF
LM26480
R1
LDO_FB
C1
C2
R2
Ideal Resistor Values
Target
R2 (KΩ)
Vout (V) R1 (KΩ)
22
Common R Values
R1 (KΩ)
R2 (KΩ)
R1
10 µF
Buck_FB
Actual VOUT
W/ Com/R (V)
Actual VOUT
Delta from
Target (V)
R2
Feedback Capacitors
C1(pF)
C2(pF)
0.8
120
200
121
200
0.803
0.002
15
none
Buck1
0.9
160
200
162
200
0.905
0.005
15
none
Only
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Ideal Resistor Values
Target
R2 (KΩ)
Vout (V) R1 (KΩ)
Common R Values
R1 (KΩ)
R2 (KΩ)
Actual VOUT
W/ Com/R (V)
Actual VOUT
Delta from
Target (V)
Feedback Capacitors
C1(pF)
C2(pF)
1
200
200
200
200
1
0
15
none
^
1.1
240
200
240
200
1.1
0
15
none
|
1.2
280
200
280
200
1.2
0
12
none
|
1.3
320
200
324
200
1.31
0.01
12
none
Buck1
1.4
360
200
357
200
1.393
-0.008
10
none
And
1.5
400
200
402
200
1.505
0.005
10
none
Buck2
1.6
440
200
442
200
1.605
0.005
8.2
none
|
1.7
427
178
432
178
1.713
0.013
8.2
none
|
1.8
463
178
464
178
1.803
0.003
8.2
none
|
1.9
498
178
499
178
1.902
0.002
8.2
none
|
2
450
150
453
150
2.01
0.01
8.2
none
>
2.1
480
150
475
150
2.083
-0.017
8.2
none
^
2.2
422
124
422
124
2.202
0.002
8.2
none
|
2.3
446
124
442
124
2.282
-0.018
8.2
none
|
2.4
471
124
475
124
2.415
0.015
8.2
none
|
2.5
400
100
402
100
2.51
0.01
8.2
none
|
2.6
420
100
422
100
2.61
0.01
8.2
none
|
2.7
440
100
442
100
2.71
0.01
8.2
33
Buck2
2.8
460
100
464
100
2.82
0.02
8.2
33
Only
2.9
480
100
475
100
2.875
-0.025
8.2
33
|
3
500
100
499
100
2.995
-0.005
6.8
33
|
3.1
520
100
523
100
3.115
0.015
6.8
33
|
3.2
540
100
536
100
3.18
-0.02
6.8
33
|
3.3
560
100
562
100
3.31
0.01
6.8
33
|
The output voltages of the bucks of the LM26480 are established by the feedback resistor dividers R1 and R2
shown on the application circuit above. The equation for determining V is: VOUT = VFB (R1+R2)/R2 where VFB is
the voltage on the Buck FBx pin.
The Buck control loop will force the voltage on VFB to be 0.50 V ±3%.
The above table shows ideal resistor values to establish buck voltages from 0.8V to 3.3 V along with common
resistor values to establish these voltages. Common resistors do not always produce the target value, error is
given in the delta column.
In addition to the resistor feedback, capacitor feedback C1 is always required, and depending on the output
voltage capacitor C2 is also required. See External Component Selection for these requirements.
Inductor
LSW1,2
Value
Unit
2.2
µH
Description
SW1,2 inductor
Notes
D.C.R. 70 mΩ
Output Inductors & Capacitors for SW1 AND SW2
There are several design considerations related to the selection of output inductors and capacitors:
• Load transient response;
• Stability;
• Efficiency;
• Output ripple voltage; and
• Over-current ruggedness.
The LM26480 has been optimized for use with nominal values 2.2 µH and 10 µF. If other values are needed for
the design, please contact Texas Instruments sales with any concerns.
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Inductor Selection for SW1 AND SW2
A nominal inductor value of 2.2 µH is recommended. It is important to ensure the inductor core does not saturate
during any foreseeable operational situation.
Care should be taken when reviewing the different saturation current ratings that are specified by different
manufacturers. Saturation current ratings are typically specified at 25ºC, so ratings at maximum ambient
temperature of the application should be requested from the manufacturer.
There are two methods to choose the inductor saturation current rating:
Recommended method:
The best way to ensure the inductor does not saturate is to choose an inductor that has saturation current rating
greater than the maximum LM26480 current limit of 2.4A. In this case the device will prevent inductor saturation.
Alternate method:
If the recommended approach cannot be used, care must be taken to ensure that the saturation current is
greater than the peak inductor current:
ISAT > ILPEAK
ILPEAK = IOUTMAX +
IRIPPLE
2
D x (VIN ± VOUT)
LxF
VOUT
D=
VIN x EFF
IRIPPLE =
•
•
•
•
•
•
•
•
•
•
ISAT: Inductor saturation current at operating temperature
ILPEAK: Peak inductor current during worst case conditions
IOUTMAX: Maximum average inductor current
IRIPPLE: Peak-to-Peak inductor current
VOUT: Output voltage
VIN: Input voltage
L: Inductor value in Henries at IOUTMAX
F: Switching frequency, Hertz
D: Estimated duty factor
EFF: Estimated power supply efficiency
ISAT may not be exceeded during any operation, including transients, startup, high temperature, worst case
conditions, etc.
Suggested Inductors and Their Suppliers
Model
Vendor
Dimensions (mm)
DCR (max)
ISATURATION
DO3314-222MX
Coilcraft
3.3 x 3.3 x 1.4
200 mΩ
≈1.8A
LPO3310-222MX
Coilcraft
3.3 x 3.3 x 1
150 mΩ
≈1.3A
ELL6PG2R2N
Panasonic
6.0 x 6.0 x 2.0
37 mΩ
≈2.2A
ELC6GN2R2N
Panasonic
6.0 x 6.0 x 1.5
53 mΩ
≈1.9A
CDRH2D14NP-2R2NC
Sumida
3.2 x 3.2 x 1.5
94 mΩ
≈1.5A
Output Capacitor Selection for SW1 AND SW2
A ceramic output capacitor of 10 µF, 6.3V is recommended with an ESR of less than 500 mΩ.
Output ripple can be estimated from the vector sum of the reactive (Capacitor) voltage component and the real
(ESR) voltage component of the output capacitor.
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IRIPPLE
8 x F x COUT
VCOUT =
VROUT = IRIPPLE x ESRCOUT
VPPOUT =
•
•
•
VCOUT2 + VROUT2
VCOUT: Estimated reactive output ripple
VROUT: Estimated real output ripple
VPPOUT: Estimated peak-to-peak output ripple
(5)
The output capacitor needs to be mounted as close as possible to the output pin of the device. For better
temperature performance, X7R or X5R types are recommended. DC bias characteristics of ceramic capacitors
must be considered when selecting case sizes like 0805 and 0603.
DC bias characteristics vary from manufacturer to manufacturer and by case size. DC bias curves should be
requested from them as part of the capacitor selection process. ESR is typically higher for smaller packages.
The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output
voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with
sufficient capacitance and sufficiently low ESR to perform these functions.
Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series
resistance of the output capacitor (ESRCOUT). ESRCOUT is frequency dependent as well as temperature
dependent. The RESR should be calculated with the applicable switching frequency and ambient temperature.
Input Capacitor Selection for SW1 AND SW2
It is required to use a ceramic input capacitor of at least 4.7 μF and 6.3V with an ESR of less than 500 mΩ.
The input power source supplies average current continuously. During the PFET switch on-time, however, the
demanded di/dt is higher than can be typically supplied by the input power source. This delta is supplied by the
input capacitor.
A simplified “worst case” assumption is that all of the PFET current is supplied by the input capacitor. This will
result in conservative estimates of input ripple voltage and capacitor RMS current. Input ripple voltage is
estimated as follows:
IOUT x D
VPPIN = C x F + IOUT x ESRCIN
IN
•
•
•
•
VPPIN: Estimated peak-to-peak input ripple voltage
IOUT: Output current, Amps
CIN: Input capacitor value, Farads
ESRIN: Input capacitor ESR, Ohms
(6)
This capacitor is exposed to significant RMS current, so it is important to select a capacitor with an adequate
RMS current rating. Capacitor RMS current estimated as follows:
•
D x §IOUT2 +
©
IRIPPLE
12
2
§
©
IRMSCIN =
IRSCIN: Estimated input capacitor RMS current
Model
(7)
Type
Vendor
Voltage Rating
Case Size
C2012X5R0J475K
Ceramic, X5R
TDK
6.3V
0805, (2012)
4.7 µF for CIN
JMK212BJ475K
Ceramic, X5R
Taiyo-Yuden
6.3V
0805, (2012)
GRM21BR60J475K
Ceramic, X5R
Murata
6.3V
0805, (2012)
C1608X5R0J475K
Ceramic, X5R
TDK
6.3V
0603, (1608)
10 µF for COUT
GRM21BR60J106K
Ceramic, X5R
Murata
6.3V
0805, (2012)
JMK212BJ106K
Ceramic, X5R
Taiyo-Yuden
6.3V
0805, (2012)
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Model
Type
Vendor
Voltage Rating
Case Size
C2012X5R0J106K
Ceramic, X5R
TDK
6.3V
0805, (2012)
C1608X5R0J106K
Ceramic, X5R
TDK
6.3V
0603, (1608)
Feedback Resistors for LDOs
Buck
LDO
0.47 µF
LM26480
R1
LDO_FB
C1
C2
R2
Target VOUT (V)
Ideal Resistor Values
R1 (KΩ)
R2 (KΩ)
R1
10 µF
Buck_FB
R2
Common R Values
R1 (KΩ)
R2 (KΩ)
Actual VOUT
W/Com/R (V)
1
200
200
200
200
1
1.1
240
200
240
200
1.1
1.2
280
200
280
200
1.2
1.3
320
200
324
200
1.31
1.4
360
200
357
200
1.393
1.5
400
200
402
200
1.505
1.6
440
200
442
200
1.605
1.7
480
200
562
232
1.711
1.8
520
200
604
232
1.802
1.9
560
200
562
200
1.905
2
600
200
604
200
2.01
2.1
640
200
715
221
2.118
2.2
680
200
681
200
2.203
2.3
720
200
806
226
2.283
2.4
760
200
845
221
2.412
2.5
800
200
750
187
2.505
2.6
840
200
909
215
2.614
2.7
880
200
1100
249
2.709
2.8
920
200
1150
249
2.809
2.9
960
200
1210
255
2.873
3
1000
200
1000
200
3
3.1
1040
200
1000
191
3.118
3.2
1080
200
1000
187
3.174
3.3
1120
200
1210
215
3.314
3.4
1160
200
1210
210
3.381
3.5
1200
200
1210
200
3.525
The output voltages of the LDOs of the LM26480 are established by the feedback resistor dividers R1 and R2
shown on the application circuit above. The equation for determining VOUT is: VOUT = VFB(R1+R2)/R2, where VFB
is the voltage on the LDOX_FB pin.
The LDO control loop will force the voltage on VFB to be 0.50 V ±3%. The above table shows ideal resistor
values to establish LDO voltages from 1.0V to 3.5V along with common resistor values to establish these
voltages. Common resistors do not always produce the target value, error is given in the final column.
To keep the power consumed by the feedback network low it is recommended that R2 be established as about
200 KΩ. Lesser values of R2 are OK at the users discretion..
26
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LDO Dapacitor Selection
Input Capacitor
An input capacitor is required for stability. It is recommended that a 1.0 μF capacitor be connected between the
LDO input pin and ground (this capacitance value may be increased without limit). This capacitor must be located
a distance of not more than 1 cm from the input pin and returned to a clean analog ground. Any good quality
ceramic, tantalum, or film capacitor may be used at the input.
WARNING
Important: Tantalum capacitors can suffer catastrophic failures due to surge
currents when connected to a low impedance source of power (like a battery or
a very large capacitor). If a tantalum capacitor is used at the input, it must be
specified by the manufacturer to have a surge current rating sufficient for the
application.
There are no requirements for the ESR on the input capacitor, but tolerance and
temperature coefficient must be considered when selecting the capacitor to
ensure the capacitance will remain approximately 1.0 μF over the entire
operating temperature range.
Output Capacitor
The LDOs on the LM26480 are designed specifically to work with very small ceramic output capacitors. A 1.0 μF
ceramic capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5 mΩ to 500 mΩ, are suitable in the
application circuit. It is also possible to use tantalum or film capacitors at the device output COUT (or VOUT), but
these are not as attractive for reasons of size and cost. The output capacitor must meet the requirement for the
minimum value of capacitance and also have an ESR value that is within the range 5 mΩ to 500 mΩ for stability.
Capacitor Characteristics
The LDOs are designed to work with ceramic capacitors on the output to take advantage of the benefits they
offer. For capacitance values in the range of 0.47 μF to 4.7 μF, ceramic capacitors are the smallest, least
expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The
ESR of a typical 1.0 μF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR
requirement for stability for the LDOs.
For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure
correct device operation. The capacitor value can change greatly, depending on the operating conditions and
capacitor type.
In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the
specification is met within the application. The capacitance can vary with DC bias conditions as well as
temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging.
The capacitor parameters are also dependent on the particular case size, with smaller sizes giving poorer
performance figures in general. As an example, the graph below shows a typical graph comparing different
capacitor case sizes in a capacitance vs. DC bias plot.
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CAP VALUE (% of NOMINAL 1 PF)
SNVS543I – JANUARY 2008 – REVISED MAY 2013
0603, 10V, X5R
100%
80%
60%
0402, 6.3V, X5R
40%
20%
0
1.0
2.0
3.0
4.0
5.0
DC BIAS (V)
As shown in the graph, increasing the DC bias condition can result in the capacitance value that falls below the
minimum value given in the recommended capacitor specifications table. Note that the graph shows the
capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended
that the capacitor manufacturers’ specifications for the nominal value capacitor are consulted for all conditions,
as some capacitor sizes (e.g. 0402) may not be suitable in the actual application.
The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a
temperature range of −55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R
has a similar tolerance over a reduced temperature range of −55°C to +85°C. Many large value ceramic
capacitors, larger than 1 μF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance
can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over
Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 0.47 μF to 4.7 μF range. Another
important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This
means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it
would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the
same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the
temperature goes from 25°C down to −40°C, so some guard band must be allowed.
Capacitor
Min Value
Unit
Description
Recommended Type
CLDO1
0.47
µF
LDO1 output capacitor
Ceramic, 6.3V, X5R
CLDO2
0.47
µF
LDO2 output capacitor
Ceramic, 6.3V, X5R
CSW1
10
µF
SW1 output capacitor
Ceramic, 6.3V, X5R
CSW2
10
µF
SW2 output capacitor
Ceramic, 6.3V, X5R
Analog Power Signal Routing
All power inputs should be tied to the main VDD source (i.e. battery), unless the user wishes to power it from
another source. (i.e. powering LDO from Buck output).
The analog VDD inputs power the internal bias and error amplifiers, so they should be tied to the main VDD. The
analog VDD inputs must have an input voltage between 2.8 and 5.5 V, as specified in the Electrical
Characteristics section of this datasheet.
The other Vins (VINLDO1, VINLDO2, VIN1, VIN2) can actually have inputs lower than 2.8V, as long as it's higher
than the programmed output (+0.3V, to be safe). The analog and digital grounds should be tied together outside
of the chip to reduce noise coupling.
For more information on board layout techniques, refer to Application Note AN–1187 “Leadless Lead frame
Package (LLP)” on http://www.ti.com This application note also discusses package handling, solder stencil and
the assembly process.
28
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Board Layout Considerations
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss
ii the traces. These can send erroneous signals to the DC-DC converter IC, resulting in poor regulation or
instability. Poor layout can also result in re-flow problems leading to poor solder joints, which can result in erratic
or degraded performance.
Good layout for the LM26480 bucks can be implemented by following a few simple design rules, as illustrated in
Figure 32.
VIN, SW, VOUT,
GND, Cin and Cout
traces should be
thick and carry high
currents.
Cin and Cout caps
should be placed very
close to VIN and GND
pads.
Route feedback network and traces away from switch
node and inductor to reduce noise injection from SW node
Figure 32. Board Layout Design Rules for the LM26480
1. Place the buck inductor and filter capacitors close together and make the trace short. The traces between
these components carry relatively high switching currents and act as antennas. Following this rule reduces
radiated noise. Place the capacitors and inductor close to the buck.
2. Arrange the components so that the switching current loops curl in the same direction. During the first halt of
each cycle, current flows from the input filter capacitor, through the buck and inductor to the output filter
capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled
up from ground, through the buck by the inductor, to the output filter capacitor and then back through ground,
forming a second current loop. Routing these loops so the current curls in the same direction prevents
magnetic field reversal between the two half-cycles and reduces radiated noise.
3. Connect the ground pins of the buck, and filter capacitors together using generous component-side copper
fill as a pseudo-ground plane. Then connect this to the ground-plane (if one is used) with several vias. This
reduces ground—plane noise by preventing the switching currents from circulating through the ground plane.
it also reduces ground bounce at the buck by giving it a low-impedance ground connection.
4. Use wide traces between the power components and for power connections to the DC-DC converter circuit.
This reduces voltage errors caused by resistive losses across the traces
5. Rout noise sensitive traces, such as the voltage feedback path, away from noisy traces between the power
components. The voltage feedback trace must remain close to the buck circuit and should be routed directly
from FB to VOUT at the output capacitor and should be routed opposite to noise components. This reduces
EMI radiated onto the DC-DC converter’s own voltage feedback trace.
In mobile phones, for example, a common practice is to place the DC-DC converter on one corner of the board,
arrange the CMOS digital circuitry around it (since this also generates noise), and then place sensitive
preamplifiers and IF stages on the diagonally opposing corner. Often, the sensitive circuitry is shielded with a
metal pan and power to it is post-regulated to reduce conducted noise, using low-dropout linear regulators.
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High VIN-High Load Operation
Additional inforamtion is provided when the IC is operated at extremes of VIN and regulator loads. These are
described in terms of the junction temperature and buck output ripple management.
Junction Temperature
The maximum junction temperature TJ-MAX-OP of 125°C of the IC package.
The following equations demonstrate junction temperature determination, ambient temperature TA-MAX and total
chip power ust be controlled to keep TJ below this maximum:
TJ-MAX-OP = TA-MAX + (θJA) [°C/Watt] * (PD-MAX) [Watts]
Total IC power dissipation PD-MAX is the sum of the individual power dissipation of the four regulators plus a minor
amount for chip overhead. Chip overhead is bias, TSD and LDO analog.
PD-MAX = PLOD1 + PLDO2 +PBUCK1 + PBUCK2 + (0.0001A * VIN) [Watts].
Power dissipation of LDO1 (PLDO1) = (VINLDO1 − VOUTLDO1) * IOUTLDO1 [V*A]
Power dissipation of LDO2 (PLDO2) = (VINLDO2 − VOUTLDO2) * IOUTLDO2 [V*A]
Power dissipation of Buck1 (PBuck1) = POUT − PIN = VOUTBUCK1 − IOUTBUCK1 * (1 − η2)/ η2 [V*A]
η1 = efficiency of Buck1
Power dissipation of Buck2 (PBuck2) = POUT − PIN = VOUTBUCK2 − IOUTBUCK2 * (1 − η2)/ η2 [V*A]
η2 = efficiency of Buck2
Where η is the efficiency for the specific condition is taken from efficiency graphs.
If VIN and ILOADincrease, the output ripple associated with the Buck Regulators also increases. This mainly
occurs with VIN > 5.2V and a load current greater than 1.20A. To ensure operation in this area of operation, it is
recommended that the system designer circumvents the output ripple issues by installing Schottky diodes on the
bucks(s) that are expected to perform under these extreme conditions.
30
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SNVS543I – JANUARY 2008 – REVISED MAY 2013
REVISION HISTORY
Changes from Revision H (May 2013) to Revision I
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 30
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PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LM26480QSQ-AA/NOPB
ACTIVE
WQFN
RTW
24
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
26480QA
LM26480QSQ-CF/NOPB
ACTIVE
WQFN
RTW
24
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
26480CF
LM26480QSQX-8D/NOPB
PREVIEW
WQFN
RTW
24
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
26480QD
LM26480QSQX-AA/NOPB
ACTIVE
WQFN
RTW
24
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
26480QA
LM26480QSQX-CF/NOPB
ACTIVE
WQFN
RTW
24
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
26480CF
LM26480SQ-AA/NOPB
ACTIVE
WQFN
RTW
24
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
26480AA
LM26480SQ-BF/NOPB
ACTIVE
WQFN
RTW
24
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LM26480SQX-AA/NOPB
ACTIVE
WQFN
RTW
24
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LM26480SQX-BF/NOPB
ACTIVE
WQFN
RTW
24
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
26480BF
-40 to 85
26480AA
26480BF
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(3)
2-May-2013
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM26480, LM26480-Q1 :
• Catalog: LM26480
• Automotive: LM26480-Q1
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM26480QSQ-AA/NOPB
WQFN
RTW
24
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM26480QSQ-CF/NOPB
WQFN
RTW
24
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM26480QSQX-8D/NOPB WQFN
RTW
24
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM26480QSQX-AA/NOPB WQFN
RTW
24
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM26480QSQX-CF/NOPB WQFN
RTW
24
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM26480SQ-AA/NOPB
WQFN
RTW
24
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM26480SQ-BF/NOPB
WQFN
RTW
24
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM26480SQX-AA/NOPB
WQFN
RTW
24
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM26480SQX-BF/NOPB
WQFN
RTW
24
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM26480QSQ-AA/NOPB
WQFN
RTW
24
1000
210.0
185.0
35.0
LM26480QSQ-CF/NOPB
WQFN
RTW
24
1000
210.0
185.0
35.0
LM26480QSQX-8D/NOPB
WQFN
RTW
24
4500
367.0
367.0
35.0
LM26480QSQX-AA/NOPB
WQFN
RTW
24
4500
367.0
367.0
35.0
LM26480QSQX-CF/NOPB
WQFN
RTW
24
4500
367.0
367.0
35.0
LM26480SQ-AA/NOPB
WQFN
RTW
24
1000
210.0
185.0
35.0
LM26480SQ-BF/NOPB
WQFN
RTW
24
1000
210.0
185.0
35.0
LM26480SQX-AA/NOPB
WQFN
RTW
24
4500
367.0
367.0
35.0
LM26480SQX-BF/NOPB
WQFN
RTW
24
4500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
RTW0024A
SQA24A (Rev B)
www.ti.com
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