Product Folder Sample & Buy Technical Documents Support & Community Tools & Software LMK61E2-100M, LMK61E2-125M, LMK61E2-156M, LMK61E2-312M LMK61A2-100M, LMK61A2-125M, LMK61A2-156M, LMK61A2-312M, LMK61I2-100M SNAS676A – OCTOBER 2015 – REVISED NOVEMBER 2015 LMK61XX High-Performance Ultra-Low Jitter Oscillator 1 Features 3 Description • The LMK61XX is an ultra-low jitter oscillator that generates a commonly used reference clock. The device is pre-programmed in factory to support any reference clock frequency; supported output formats are LVPECL up to 1 GHz, LVDS up to 900 MHz, and HCSL up to 400 MHz. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3 V ± 5% supply. 1 • • • • • Ultra-low Noise, High Performance – Jitter: 90 fs RMS typical Fout > 100 MHz – PSRR: -70 dBc, robust supply noise immunity Supported Output Format – LVPECL up to 1 GHz – LVDS up to 900 MHz – HCSL up to 400 MHz Total Frequency Tolerance of ± 50 ppm 3.3 V Operating Voltage Industrial Temperature Range (-40ºC to +85ºC) 7 mm x 5 mm 6-pin Package that is Pincompatible with Industry Standard 7050 XO Package Device Information(1) PART NUMBER OUTPUT FREQ (MHz) AND FORMAT LMK61A2100M00SIA 100 LVDS 2 Applications LMK61A2125M00SIA 125 LVDS • LMK61A2156M25SIA 156.25 LVDS LMK61A2312M50SIA 312.5 LVDS LMK61E2100M00SIA 100 LVPECL LMK61E2125M00SIA 125 LVPECL LMK61E2156M25SIA 156.25 LVPECL LMK61E2312M50SIA 312.5 LVPECL LMK61I2100M00SIA 100 HCSL • • • • High-Performance Replacement for Crystal-, SAW-, or Silicon-based Oscillators Switches, Routers, Network Line Cards, Base Band Units (BBU), Servers, Storage/SAN Test and Measurement Medical Imaging FPGA, Processor Attach PACKAGE BODY SIZE (NOM) 6-pin QFM 7.0 mm x 5.0 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Pinout 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMK61E2-100M, LMK61E2-125M, LMK61E2-156M, LMK61E2-312M LMK61A2-100M, LMK61A2-125M, LMK61A2-156M, LMK61A2-312M, LMK61I2-100M SNAS676A – OCTOBER 2015 – REVISED NOVEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 3 3 3 4 4 4 5 5 5 6 6 6 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics - Power Supply ................. LVPECL Output Characteristics................................ LVDS Output Characteristics .................................... HCSL Output Characteristics.................................... OE Input Characteristics ........................................... Frequency Tolerance Characteristics ..................... Power-On/Reset Characteristics (VDD).................. PSRR Characteristics ............................................. 6.13 PLL Clock Output Jitter Characteristics .................. 6.14 Typical 156.25 MHz Output Phase Noise Characteristics ........................................................... 6.15 Additional Reliability and Qualification .................... 6.16 Typical Performance Characteristics ...................... 6 6 7 8 7 Parameter Measurement Information .................. 9 8 9 Power Supply Recommendations...................... 12 Layout ................................................................... 13 7.1 Device Output Configurations ................................... 9 9.1 Layout Guidelines ................................................... 13 10 Device and Documentation Support ................. 15 10.1 10.2 10.3 10.4 10.5 Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 15 15 15 15 15 11 Mechanical, Packaging, and Orderable Information ........................................................... 15 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (October 2015) to Revision A • 2 Page Product Preview to Production Data Datasheet .................................................................................................................... 1 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61E2-100M LMK61E2-125M LMK61E2-156M LMK61E2-312M LMK61A2-100M LMK61A2125M LMK61A2-156M LMK61A2-312M LMK61I2-100M LMK61E2-100M, LMK61E2-125M, LMK61E2-156M, LMK61E2-312M LMK61A2-100M, LMK61A2-125M, LMK61A2-156M, LMK61A2-312M, LMK61I2-100M www.ti.com SNAS676A – OCTOBER 2015 – REVISED NOVEMBER 2015 5 Pin Configuration and Functions SIA Package 6 pin QFM OE 1 6 VDD NC 2 5 OUTN GND 3 4 OUTP Table 1. Pin Functions PIN NAME I/O NO. DESCRIPTION POWER GND 3 Ground Device Ground. VDD 6 Analog 3.3 V Power Supply. 4, 5 Universal OUTPUT BLOCK OUTP, OUTN Differential Output Pair (LVPECL, LVDS or HCSL). DIGITAL CONTROL / INTERFACES NC 2 N/A No Connect. OE 1 LVCMOS Output Enable (internal pullup). When set to low, output pair is disabled and set at high impedance. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VDD Device Supply Voltage -0.3 3.6 V VIN Output Voltage Range for Logic Inputs -0.3 VDD + 0.3 V VOUT Output Voltage Range for Clock Outputs -0.3 VDD + 0.3 V TJ Junction Temperature 150 °C TSTG Storage Temperature 125 °C (1) -40 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±4000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) V ±1500 JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VDD Device Supply Voltage Copyright © 2015, Texas Instruments Incorporated MIN NOM MAX UNIT 3.135 3.3 3.465 V Submit Documentation Feedback Product Folder Links: LMK61E2-100M LMK61E2-125M LMK61E2-156M LMK61E2-312M LMK61A2-100M LMK61A2125M LMK61A2-156M LMK61A2-312M LMK61I2-100M 3 LMK61E2-100M, LMK61E2-125M, LMK61E2-156M, LMK61E2-312M LMK61A2-100M, LMK61A2-125M, LMK61A2-156M, LMK61A2-312M, LMK61I2-100M SNAS676A – OCTOBER 2015 – REVISED NOVEMBER 2015 www.ti.com Recommended Operating Conditions (continued) over operating free-air temperature range (unless otherwise noted) TA Ambient Temperature TJ Junction Temperature tRAMP VDD Power-Up Ramp Time MIN NOM -40 25 0.1 MAX UNIT 85 °C 125 °C 100 ms 6.4 Thermal Information LMK61XX (2) (3) (4) QFM (SIA) THERMAL METRIC (1) UNIT 6 PINS Airflow (LFM) 0 Airflow (LFM) 200 Airflow (LFM) 400 55.2 46.4 43.7 RθJC(top) Junction-to-case (top) thermal resistance 34.6 n/a n/a RθJB Junction-to-board thermal resistance 37.7 n/a n/a ψJT Junction-to-top characterization parameter 11.3 17.6 22.5 ψJB Junction-to-board characterization parameter 37.7 41.5 40.1 RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a RθJA (1) (2) (3) (4) Junction-to-ambient thermal resistance °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. The package thermal resistance is calculated on a 4 layer JEDEC board. Connected to GND with 3 thermal vias (0.3-mm diameter). ψJB (junction to board) is used when the main heat flow is from the junction to the GND pad. Please refer to Thermal Considerations section for more information on ensuring good system reliability and quality. 6.5 Electrical Characteristics - Power Supply (1) VDD = 3.3 V ± 5%, TA = -40C to 85°C IDD IDD-PD (1) (2) PARAMETER TEST CONDITIONS TYP MAX UNIT Device Current Consumption LVPECL (2) 162 208 mA LVDS 152 196 HCSL 155 196 OE = GND 136 Device Current Consumption when output is disabled MIN Refer to Parameter Measurement Information for relevant test conditions. On-chip power dissipation should exclude 40 mW, dissipated in the 150 ohm termination resistors, from total power dissipation. 6.6 LVPECL Output Characteristics (1) VDD = 3.3 V ± 5%, TA = -40C to 85°C PARAMETER TEST CONDITIONS (2) fOUT Output Frequency VOD Output Voltage Swing (VOH - VOL) (2) VOUT, DIFF, PP Differential Output Peak-toPeak Swing VOS Output Common Mode Voltage tR / tF Output Rise/Fall Time (20% to 80%) (3) PN-Floor Output Phase Noise Floor (fOFFSET > 10 MHz) (1) (2) (3) 4 MIN TYP 10 700 800 UNIT 1000 MHz 1200 mV 2x |VOD| V VDD – 1.55 V 120 156.25 MHz MAX -165 200 ps dBc/Hz Refer to Parameter Measurement Information for relevant test conditions. An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec. Ensured by characterization. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61E2-100M LMK61E2-125M LMK61E2-156M LMK61E2-312M LMK61A2-100M LMK61A2125M LMK61A2-156M LMK61A2-312M LMK61I2-100M LMK61E2-100M, LMK61E2-125M, LMK61E2-156M, LMK61E2-312M LMK61A2-100M, LMK61A2-125M, LMK61A2-156M, LMK61A2-312M, LMK61I2-100M www.ti.com SNAS676A – OCTOBER 2015 – REVISED NOVEMBER 2015 LVPECL Output Characteristics(1) (continued) VDD = 3.3 V ± 5%, TA = -40C to 85°C PARAMETER ODC Output Duty Cycle TEST CONDITIONS (3) MIN TYP 45% MAX UNIT 55% 6.7 LVDS Output Characteristics (1) VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER TEST CONDITIONS MIN fOUT Output Frequency (1) 10 VOD Output Voltage Swing (VOH - VOL) (1) 300 VOUT, DIFF, PP Differential Output Peak-toPeak Swing VOS TYP 390 MAX UNIT 900 MHz 480 mV 2x |VOD| V Output Common Mode Voltage 1.2 V tR / tF Output Rise/Fall Time (20% to 80%) (2) 150 PN-Floor Output Phase Noise Floor (fOFFSET > 10 MHz) ODC Output Duty Cycle (2) ROUT Differential Output Impedance (1) (2) 156.25 MHz 250 -162 45% ps dBc/Hz 55% 125 Ohm An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec. Ensured by characterization. 6.8 HCSL Output Characteristics (1) VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER MAX UNIT 10 400 MHz Output High Voltage 600 850 mV Output Low Voltage -100 100 mV Absolute Crossing Voltage (2) (3) 250 475 mV 0 140 mV 0.8 2 V/ns fOUT Output Frequency VOH VOL VCROSS TEST CONDITIONS VCROSS-DELTA Variation of VCROSS (2) (3) dV/dt Slew Rate (4) PN-Floor Output Phase Noise Floor (fOFFSET > 10 MHz) ODC Output Duty Cycle (4) (1) (2) (3) (4) MIN 100 MHz TYP -164 45% dBc/Hz 55% Refer to Parameter Measurement Information for relevant test conditions. Measured from -150 mV to +150 mV on the differential waveform with the 300 mVpp measurement window centered on the differential zero crossing. Ensured by design. Ensured by characterization. 6.9 OE Input Characteristics VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER TEST CONDITIONS VIH Input High Voltage VIL Input Low Voltage IIH Input High Current VIH = VDD IIL Input Low Current VIL = GND CIN Input Capacitance Copyright © 2015, Texas Instruments Incorporated MIN TYP MAX UNIT 1.4 V 0.6 V -40 40 uA -40 40 uA 2 Submit Documentation Feedback Product Folder Links: LMK61E2-100M LMK61E2-125M LMK61E2-156M LMK61E2-312M LMK61A2-100M LMK61A2125M LMK61A2-156M LMK61A2-312M LMK61I2-100M pF 5 LMK61E2-100M, LMK61E2-125M, LMK61E2-156M, LMK61E2-312M LMK61A2-100M, LMK61A2-125M, LMK61A2-156M, LMK61A2-312M, LMK61I2-100M SNAS676A – OCTOBER 2015 – REVISED NOVEMBER 2015 www.ti.com 6.10 Frequency Tolerance Characteristics (1) VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER fT (1) TEST CONDITIONS Total Frequency Tolerance MIN All output formats, frequency bands and device junction temperature up to 125°C; includes initial freq tolerance, temperature & supply voltage variation, solder reflow and aging (10 years) TYP MAX UNIT 50 ppm MAX UNIT 2.95 V -50 Ensured by characterization. 6.11 Power-On/Reset Characteristics (VDD) VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER TEST CONDITIONS VTHRESH Threshold Voltage VDROOP Allowable Voltage Droop (2) tSTARTUP Startup Time tOE-EN tOE-DIS (1) (2) MIN (1) TYP 2.72 0.1 V Time elapsed from VDD at 3.135 V to output enabled 10 ms Output enable time (2) Time elapsed from OE at VIH to output enabled 50 us Output disable time (2) Time elapsed from OE at VIL to output disabled 50 us MAX UNIT (1) Ensured by characterization. Ensured by design. 6.12 PSRR Characteristics (1) VDD = 3.3 V, TA = 25°C, FS[1:0] = NC, NC PARAMETER PSRR (1) (2) (3) TEST CONDITIONS Spurs Induced by 50 mV Power Supply Ripple (2) (3) at 156.25 MHz output, all output types MIN TYP Sine wave at 50 kHz -70 Sine wave at 100 kHz -70 Sine wave at 500 kHz -70 Sine wave at 1 MHz -70 dBc Refer to Parameter Measurement Information for relevant test conditions. Measured max spur level with 50 mVpp sinusoidal signal between 50 kHz and 1 MHz applied on VDD pin DJSPUR (ps, pk-pk) = [2*10(SPUR/20) / (π*fOUT)]*1e6, where PSRR or SPUR in dBc and fOUT in MHz. 6.13 PLL Clock Output Jitter Characteristics (1) (2) VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER (1) (2) (3) TEST CONDITIONS RMS Phase Jitter (3) (12 kHz – 20 MHz) (1 kHz – 5 MHz) RJ MIN fOUT ≥ 100 MHz, Integer-N PLL, All output types TYP MAX UNIT 100 200 fs RMS Refer to Parameter Measurement Information for relevant test conditions. Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer). Ensured by characterization. 6.14 Typical 156.25 MHz Output Phase Noise Characteristics (1) (2) VDD = 3.3 V, TA = 25°C, Output Type = LVPECL/LVDS/HCSL SYMBOL PARAMETER OUTPUT TYPE UNITS LVPECL LVDS HCSL phn10k Phase noise at 10 kHz offset -143 -143 -143 dBc/Hz Phn20k Phase noise at 20 kHz offset -143 -143 -143 dBc/Hz phn100k Phase noise at 100 kHz offset -144 -144 -144 dBc/Hz Phn200k Phase noise at 200 kHz offset -145 -145 -145 dBc/Hz (1) (2) 6 Refer to Parameter Measurement Information for relevant test conditions. Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer). Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61E2-100M LMK61E2-125M LMK61E2-156M LMK61E2-312M LMK61A2-100M LMK61A2125M LMK61A2-156M LMK61A2-312M LMK61I2-100M LMK61E2-100M, LMK61E2-125M, LMK61E2-156M, LMK61E2-312M LMK61A2-100M, LMK61A2-125M, LMK61A2-156M, LMK61A2-312M, LMK61I2-100M www.ti.com SNAS676A – OCTOBER 2015 – REVISED NOVEMBER 2015 Typical 156.25 MHz Output Phase Noise Characteristics(1)(2) (continued) VDD = 3.3 V, TA = 25°C, Output Type = LVPECL/LVDS/HCSL SYMBOL PARAMETER OUTPUT TYPE UNITS LVPECL LVDS HCSL phn1M Phase noise at 1 MHz offset -150 -150 -150 dBc/Hz phn2M Phase noise at 2 MHz offset -154 -154 -154 dBc/Hz phn10M Phase noise at 10 MHz offset -165 -162 -164 dBc/Hz phn20M Phase noise at 20 MHz offset -165 -162 -164 dBc/Hz 6.15 Additional Reliability and Qualification PARAMETER CONDITION / TEST METHOD Mechanical Shock MIL-STD-202, Method 213 Mechanical Vibration MIL-STD-202, Method 204 Moisture Sensitivity Level J-STD-020, MSL3 Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK61E2-100M LMK61E2-125M LMK61E2-156M LMK61E2-312M LMK61A2-100M LMK61A2125M LMK61A2-156M LMK61A2-312M LMK61I2-100M 7 LMK61E2-100M, LMK61E2-125M, LMK61E2-156M, LMK61E2-312M LMK61A2-100M, LMK61A2-125M, LMK61A2-156M, LMK61A2-312M, LMK61I2-100M SNAS676A – OCTOBER 2015 – REVISED NOVEMBER 2015 www.ti.com 6.16 Typical Performance Characteristics Figure 1. Phase Noise of 156.25 MHz LVPECL Differential Output Figure 2. Phase Noise of 156.25 MHz LVDS Differential Output 10 0 Amplitude (dBm) -10 -20 -30 -40 -50 -60 -70 -80 -90 78.125 10 0 0 -10 -10 -20 -20 Amplitude (dBm) Amplitude (dBm) 10 -40 -50 -60 234.375 D008 Figure 5. 156.25 ± 78.125 MHz LVDS Differential Output Spectrum 8 -60 -80 203.125 Submit Documentation Feedback D007 -50 -80 140.625 171.875 Frequency (MHz) 234.375 -40 -70 109.375 203.125 -30 -70 -90 78.125 140.625 171.875 Frequency (MHz) Figure 4. 156.25 ± 78.125 MHz LVPECL Differential Output Spectrum Figure 3. Phase Noise of 156.25 MHz HCSL Differential Output -30 109.375 -90 78.125 109.375 140.625 171.875 Frequency (MHz) 203.125 234.375 D009 Figure 6. 156.25 ± 78.125 MHz HCSL Differential Output Spectrum Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61E2-100M LMK61E2-125M LMK61E2-156M LMK61E2-312M LMK61A2-100M LMK61A2125M LMK61A2-156M LMK61A2-312M LMK61I2-100M LMK61E2-100M, LMK61E2-125M, LMK61E2-156M, LMK61E2-312M LMK61A2-100M, LMK61A2-125M, LMK61A2-156M, LMK61A2-312M, LMK61I2-100M www.ti.com SNAS676A – OCTOBER 2015 – REVISED NOVEMBER 2015 Typical Performance Characteristics (continued) 0.9 1.7 Output Differential Swing (Vp-p) Output Differential Swing (Vp-p) 1.8 1.6 1.5 1.4 1.3 1.2 1.1 0.8 0.7 0.6 0.5 0 200 400 600 Output Frequency (MHz) 800 1000 0 200 D013 Figure 7. LVPECL Differential Output Swing vs Frequency 400 600 Output Frequency (MHz) 800 1000 D014 Figure 8. LVDS Differential Output Swing vs Frequency Output Differential Swing (Vp-p) 1.5 1.48 1.46 1.44 1.42 1.4 0 100 200 300 Output Frequency (MHz) 400 500 D015 Figure 9. HCSL Differential Output Swing vs Frequency 7 Parameter Measurement Information 7.1 Device Output Configurations High impedance differential probe LMK61XX LVPECL 150 Oscilloscope 150 Figure 10. LVPECL Output DC Configuration during Device Test Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK61E2-100M LMK61E2-125M LMK61E2-156M LMK61E2-312M LMK61A2-100M LMK61A2125M LMK61A2-156M LMK61A2-312M LMK61I2-100M 9 LMK61E2-100M, LMK61E2-125M, LMK61E2-156M, LMK61E2-312M LMK61A2-100M, LMK61A2-125M, LMK61A2-156M, LMK61A2-312M, LMK61I2-100M SNAS676A – OCTOBER 2015 – REVISED NOVEMBER 2015 www.ti.com Device Output Configurations (continued) High impedance differential probe LMK61XX LVDS Oscilloscope Figure 11. LVDS Output DC Configuration during Device Test High impedance differential probe HCSL LMK61XX 50 Oscilloscope 50 Figure 12. HCSL Output DC Configuration during Device Test LMK61XX Balun/ Buffer LVPECL 150 Phase Noise/ Spectrum Analyzer 150 Figure 13. LVPECL Output AC Configuration during Device Test LMK61XX Balun/ Buffer LVDS Phase Noise/ Spectrum Analyzer Figure 14. LVDS Output AC Configuration during Device Test LMK61XX Balun/ Buffer HCSL 50 Phase Noise/ Spectrum Analyzer 50 Figure 15. HCSL Output AC Configuration during Device Test 10 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61E2-100M LMK61E2-125M LMK61E2-156M LMK61E2-312M LMK61A2-100M LMK61A2125M LMK61A2-156M LMK61A2-312M LMK61I2-100M LMK61E2-100M, LMK61E2-125M, LMK61E2-156M, LMK61E2-312M LMK61A2-100M, LMK61A2-125M, LMK61A2-156M, LMK61A2-312M, LMK61I2-100M www.ti.com SNAS676A – OCTOBER 2015 – REVISED NOVEMBER 2015 Device Output Configurations (continued) Sine wave Modulator Power Supply LMK61XX Balun 150 (LVPECL) Open (LVDS) 50 (HCSL) Phase Noise/ Spectrum Analyzer 150 (LVPECL) Open (LVDS) 50 (HCSL) Figure 16. PSRR Test Setup OUT_P VOD OUT_N 80% VOUT,DIFF,PP = 2 x VOD 0V 20% tR tF Figure 17. Differential Output Voltage and Rise/Fall Time Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK61E2-100M LMK61E2-125M LMK61E2-156M LMK61E2-312M LMK61A2-100M LMK61A2125M LMK61A2-156M LMK61A2-312M LMK61I2-100M 11 LMK61E2-100M, LMK61E2-125M, LMK61E2-156M, LMK61E2-312M LMK61A2-100M, LMK61A2-125M, LMK61A2-156M, LMK61A2-312M, LMK61I2-100M SNAS676A – OCTOBER 2015 – REVISED NOVEMBER 2015 www.ti.com 8 Power Supply Recommendations For best electrical performance of LMK61XX, it is preferred to utilize a combination of 10 uF, 1 uF and 0.1 uF on its power supply bypass network. It is also recommended to utilize component side mounting of the power supply bypass capacitors and it is best to use 0201 or 0402 body size capacitors to facilitate signal routing. Keep the connections between the bypass capacitors and the power supply on the device as short as possible. Ground the other side of the capacitor using a low impedance connection to the ground plane. Figure 18 shows the layout recommendation for power supply decoupling of LMK61XX. 12 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61E2-100M LMK61E2-125M LMK61E2-156M LMK61E2-312M LMK61A2-100M LMK61A2125M LMK61A2-156M LMK61A2-312M LMK61I2-100M LMK61E2-100M, LMK61E2-125M, LMK61E2-156M, LMK61E2-312M LMK61A2-100M, LMK61A2-125M, LMK61A2-156M, LMK61A2-312M, LMK61I2-100M www.ti.com SNAS676A – OCTOBER 2015 – REVISED NOVEMBER 2015 9 Layout 9.1 Layout Guidelines The following sections provides recommendations for board layout, solder reflow profile and power supply bypassing when using LMK61XX to ensure good thermal / electrical performance and overall signal integrity of entire system. 9.1.1 Ensuring Thermal Reliability The LMK61XX is a high performance device. Therefore careful attention must be paid to device configuration and printed circuit board (PCB) layout with respect to power consumption. The ground pin needs to be connected to the ground plane of the PCB through three vias or more, as shown in Figure 18, to maximize thermal dissipation out of the package. Equation 1 describes the relationship between the PCB temperature around the LMK61XX and its junction temperature. TB = TJ – ΨJB * P where • • • • TB: PCB temperature around the LMK61XX TJ: Junction temperature of LMK61XX ΨJB: Junction-to-board thermal resistance parameter of LMK61XX (37.7°C/W without airflow) P: On-chip power dissipation of LMK61XX (1) In order to ensure that the maximum junction temperature of LMK61XX is below 125°C, it can be calculated that the maximum PCB temperature without airflow should be at 99°C or below when the device is optimized for best performance resulting in maximum on-chip power dissipation of 0.68 W. 9.1.2 Best Practices for Signal Integrity For best electrical performance and signal integrity of entire system with LMK61XX, it is recommended to route vias into decoupling capacitors and then into the LMK61XX. It is also recommended to increase the via count and width of the traces wherever possible. These steps ensure lowest impedance and shortest path for high frequency current flow. Figure 18 shows the layout recommendation for LMK61XX. Figure 18. LMK61XX Layout Recommendation for Power Supply and Ground Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK61E2-100M LMK61E2-125M LMK61E2-156M LMK61E2-312M LMK61A2-100M LMK61A2125M LMK61A2-156M LMK61A2-312M LMK61I2-100M 13 LMK61E2-100M, LMK61E2-125M, LMK61E2-156M, LMK61E2-312M LMK61A2-100M, LMK61A2-125M, LMK61A2-156M, LMK61A2-312M, LMK61I2-100M SNAS676A – OCTOBER 2015 – REVISED NOVEMBER 2015 www.ti.com Layout Guidelines (continued) 9.1.3 Recommended Solder Reflow Profile It is recommended to follow the solder paste supplier's recommendations to optimize flux activity and to achieve proper melting temperatures of the alloy within the guidelines of J-STD-20. It is preferrable for the LMK61XX to be processed with the lowest peak temperature possible while also remaining below the components peak temperature rating as listed on the MSL label. The exact temperature profile would depend on several factors including maximum peak temperature for the component as rated on the MSL label, Board thickness, PCB material type, PCB geometries, component locations, sizes, densities within PCB, as well solder manufactures recommended profile, and capability of the reflow equipment to as confirmed by the SMT assembly operation. 14 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61E2-100M LMK61E2-125M LMK61E2-156M LMK61E2-312M LMK61A2-100M LMK61A2125M LMK61A2-156M LMK61A2-312M LMK61I2-100M LMK61E2-100M, LMK61E2-125M, LMK61E2-156M, LMK61E2-312M LMK61A2-100M, LMK61A2-125M, LMK61A2-156M, LMK61A2-312M, LMK61I2-100M www.ti.com SNAS676A – OCTOBER 2015 – REVISED NOVEMBER 2015 10 Device and Documentation Support 10.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LMK61E2-100M Click here Click here Click here Click here Click here LMK61E2-125M Click here Click here Click here Click here Click here LMK61E2-156M Click here Click here Click here Click here Click here LMK61E2-312M Click here Click here Click here Click here Click here LMK61A2-100M Click here Click here Click here Click here Click here LMK61A2-125M Click here Click here Click here Click here Click here LMK61A2-156M Click here Click here Click here Click here Click here LMK61A2-312M Click here Click here Click here Click here Click here LMK61I2-100M Click here Click here Click here Click here Click here 10.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 10.3 Trademarks E2E is a trademark of Texas Instruments. 10.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 10.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK61E2-100M LMK61E2-125M LMK61E2-156M LMK61E2-312M LMK61A2-100M LMK61A2125M LMK61A2-156M LMK61A2-312M LMK61I2-100M 15 PACKAGE OPTION ADDENDUM www.ti.com 29-Jan-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMK61A2-100M00SIAR PREVIEW QFM SIA 6 2500 Green (RoHS & no Sb/Br) Call TI | NIAU Level-3-260C-168 HR -40 to 85 LMK61A2 100M00 LMK61A2-100M00SIAT PREVIEW QFM SIA 6 250 Green (RoHS & no Sb/Br) Call TI | NIAU Level-3-260C-168 HR -40 to 85 LMK61A2 100M00 LMK61A2-125M00SIAR PREVIEW QFM SIA 6 2500 Green (RoHS & no Sb/Br) Call TI | NIAU Level-3-260C-168 HR -40 to 85 LMK61A2 125M00 LMK61A2-125M00SIAT PREVIEW QFM SIA 6 250 Green (RoHS & no Sb/Br) Call TI | NIAU Level-3-260C-168 HR -40 to 85 LMK61A2 125M00 LMK61A2-156M25SIAR PREVIEW QFM SIA 6 2500 Green (RoHS & no Sb/Br) Call TI | NIAU Level-3-260C-168 HR -40 to 85 LMK61A2 156M25 LMK61A2-156M25SIAT PREVIEW QFM SIA 6 250 Green (RoHS & no Sb/Br) Call TI | NIAU Level-3-260C-168 HR -40 to 85 LMK61A2 156M25 LMK61A2-312M50SIAR PREVIEW QFM SIA 6 2500 Green (RoHS & no Sb/Br) Call TI | NIAU Level-3-260C-168 HR -40 to 85 LMK61A2 312M50 LMK61A2-312M50SIAT PREVIEW QFM SIA 6 250 Green (RoHS & no Sb/Br) Call TI | NIAU Level-3-260C-168 HR -40 to 85 LMK61A2 312M50 LMK61E2-100M00SIAR ACTIVE QFM SIA 6 2500 Green (RoHS & no Sb/Br) Call TI | NIAU Level-3-260C-168 HR -40 to 85 LMK61E2 100M00 LMK61E2-100M00SIAT ACTIVE QFM SIA 6 250 Green (RoHS & no Sb/Br) Call TI | NIAU Level-3-260C-168 HR -40 to 85 LMK61E2 100M00 LMK61E2-125M00SIAR ACTIVE QFM SIA 6 2500 Green (RoHS & no Sb/Br) Call TI | NIAU Level-3-260C-168 HR -40 to 85 LMK61E2 125M00 LMK61E2-125M00SIAT ACTIVE QFM SIA 6 250 Green (RoHS & no Sb/Br) Call TI | NIAU Level-3-260C-168 HR -40 to 85 LMK61E2 125M00 LMK61E2-156M25SIAR ACTIVE QFM SIA 6 2500 Green (RoHS & no Sb/Br) Call TI | NIAU Level-3-260C-168 HR -40 to 85 LMK61E2 156M25 LMK61E2-156M25SIAT ACTIVE QFM SIA 6 250 Green (RoHS & no Sb/Br) Call TI | NIAU Level-3-260C-168 HR -40 to 85 LMK61E2 156M25 LMK61E2-312M50SIAR ACTIVE QFM SIA 6 2500 Green (RoHS & no Sb/Br) Call TI | NIAU Level-3-260C-168 HR -40 to 85 LMK61E2 312M50 LMK61E2-312M50SIAT ACTIVE QFM SIA 6 250 Green (RoHS & no Sb/Br) Call TI | NIAU Level-3-260C-168 HR -40 to 85 LMK61E2 312M50 LMK61I2-100M00SIAR PREVIEW QFM SIA 6 2500 Green (RoHS & no Sb/Br) Call TI | NIAU Level-3-260C-168 HR -40 to 85 LMK61I2 100M00 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 29-Jan-2016 Status (1) LMK61I2-100M00SIAT PREVIEW Package Type Package Pins Package Drawing Qty QFM SIA 6 250 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) Call TI | NIAU Level-3-260C-168 HR Op Temp (°C) Device Marking (4/5) -40 to 85 LMK61I2 100M00 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 Samples PACKAGE MATERIALS INFORMATION www.ti.com 8-Dec-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMK61E2-100M00SIAR QFM SIA 6 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 16.4 5.5 7.5 1.5 8.0 16.0 Q1 LMK61E2-100M00SIAT QFM SIA 6 250 178.0 16.4 5.5 7.5 1.5 8.0 16.0 Q1 LMK61E2-125M00SIAR QFM SIA 6 2500 330.0 16.4 5.5 7.5 1.5 8.0 16.0 Q1 LMK61E2-125M00SIAT QFM SIA 6 250 178.0 16.4 5.5 7.5 1.5 8.0 16.0 Q1 LMK61E2-156M25SIAR QFM SIA 6 2500 330.0 16.4 5.5 7.5 1.5 8.0 16.0 Q1 LMK61E2-156M25SIAT QFM SIA 6 250 178.0 16.4 5.5 7.5 1.5 8.0 16.0 Q1 LMK61E2-312M50SIAR QFM SIA 6 2500 330.0 16.4 5.5 7.5 1.5 8.0 16.0 Q1 LMK61E2-312M50SIAT QFM SIA 6 250 178.0 16.4 5.5 7.5 1.5 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Dec-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMK61E2-100M00SIAR QFM SIA 6 2500 367.0 367.0 38.0 LMK61E2-100M00SIAT QFM SIA 6 250 213.0 191.0 55.0 LMK61E2-125M00SIAR QFM SIA 6 2500 367.0 367.0 38.0 LMK61E2-125M00SIAT QFM SIA 6 250 213.0 191.0 55.0 LMK61E2-156M25SIAR QFM SIA 6 2500 367.0 367.0 38.0 LMK61E2-156M25SIAT QFM SIA 6 250 213.0 191.0 55.0 LMK61E2-312M50SIAR QFM SIA 6 2500 367.0 367.0 38.0 LMK61E2-312M50SIAT QFM SIA 6 250 213.0 191.0 55.0 Pack Materials-Page 2 PACKAGE OUTLINE SIA0006A QFM - 1.15 mm max height SCALE 2.200 QUAD FLAT MODULE 5.1 4.9 A B PIN 1 INDEX AREA 7.1 6.9 C 1.15 MAX 0.1 C 3X 3.7 6X (0.15) 3 4 4X (0.26) SYMM 2X 5.08 4X 2.54 6X 0.1 0.05 6 1 SYMM 1.43 1.37 6X C A C B 1.03 0.97 4222361/B 10/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com EXAMPLE BOARD LAYOUT SIA0006A QFM - 1.15 mm max height QUAD FLAT MODULE SYMM 6X (1) 6X (1.4) 1 6 SYMM 4X (2.54) 4 3 (R0.05) TYP (3.7) LAND PATTERN EXAMPLE 1:1 RATIO WITH PACKAGE SOLDER PADS SCALE:8X 0.07 MIN ALL AROUND METAL SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4222361/B 10/2015 NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com EXAMPLE STENCIL DESIGN SIA0006A QFM - 1.15 mm max height QUAD FLAT MODULE SYMM 12X (1) 1 6 12X (0.6) METAL TYP (R0.05) SYMM 4X (2.54) 4 3 (0.4) TYP (3.7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL PRINTED SOLDER COVERAGE BY AREA ALL PADS: 86% SCALE:10X 4222361/B 10/2015 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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