Sound Effect Generator Flash MCU HT45F2020/HT45F2022 Revision: V1.00 Date: April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Table of Contents Features................................................................................................................. 5 CPU Features...............................................................................................................................5 Peripheral Features.......................................................................................................................5 General Description.............................................................................................. 6 Selection Table...................................................................................................... 6 Block Diagram....................................................................................................... 7 Pin Assignment..................................................................................................... 7 Pin Description..................................................................................................... 8 Absolute Maximum Ratings................................................................................. 9 D.C. Characteristics.............................................................................................. 9 A.C. Characteristics............................................................................................ 10 Shunt Regulator Electrical Characteristics – for HT45F2020 only................. 11 Power-on Reset Characteristics........................................................................ 12 System Architecture........................................................................................... 12 Clocking and Pipelining...............................................................................................................12 Program Counter.........................................................................................................................13 Stack...........................................................................................................................................14 Arithmetic and Logic Unit – ALU.................................................................................................14 Flash Program Memory...................................................................................... 15 Structure......................................................................................................................................15 Special Vectors...........................................................................................................................15 Look-up Table..............................................................................................................................15 Table Program Example..............................................................................................................16 In Circuit Programming – ICP.....................................................................................................17 On-Chip Debug Support – OCDS...............................................................................................18 Data Memory....................................................................................................... 18 Structure......................................................................................................................................18 General Purpose Data Memory..................................................................................................18 Special Purpose Data Memory...................................................................................................19 Special Function Register Description............................................................. 20 Indirect Addressing Registers – IAR0, IAR1...............................................................................20 Memory Pointers – MP0, MP1....................................................................................................20 Accumulator – ACC.....................................................................................................................21 Program Counter Low Register – PCL........................................................................................21 Look-up Table Registers – TBLP, TBLH......................................................................................21 Status Register – STATUS..........................................................................................................21 Oscillators........................................................................................................... 23 Oscillator Overview.....................................................................................................................23 System Clock Configurations .....................................................................................................23 Rev. 1.00 2 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU High Speed Internal RC Oscillator – HIRC ................................................................................24 Internal 32kHz Oscillator – LIRC ................................................................................................24 Supplementary Oscillators .........................................................................................................24 Operating Modes and System Clocks ............................................................. 24 System Clocks ...........................................................................................................................24 System Operation Modes............................................................................................................25 Control Register..........................................................................................................................27 Operating Mode Switching .........................................................................................................28 Standby Current Considerations ................................................................................................32 Wake-up......................................................................................................................................32 Watchdog Timer.................................................................................................. 33 Watchdog Timer Clock Source....................................................................................................33 Watchdog Timer Control Register...............................................................................................33 Watchdog Timer Operation.........................................................................................................34 Reset and Initialisation....................................................................................... 35 Reset Functions..........................................................................................................................35 Reset Initial Conditions ..............................................................................................................36 Input/Output Ports ............................................................................................. 38 Pull-high Resistors......................................................................................................................38 Port A Wake-up...........................................................................................................................39 I/O Port Control Registers...........................................................................................................39 Pin-shared Functions..................................................................................................................40 I/O Pin Structures........................................................................................................................41 Programming Considerations .....................................................................................................41 Timer Modules – TM........................................................................................... 42 Introduction.................................................................................................................................42 TM Operation..............................................................................................................................42 TM Clock Source.........................................................................................................................42 TM Interrupts...............................................................................................................................42 TM External Pins ........................................................................................................................43 TM Input/Output Pin Selection....................................................................................................43 Programming Considerations......................................................................................................44 Periodic Type TM – PTM..................................................................................... 45 Periodic TM Operation................................................................................................................45 Periodic Type TM Register Description.......................................................................................46 Periodic Type TM Operation Modes............................................................................................50 Shunt Regulator – for HT45F2020 only............................................................. 59 Sound Effect Generator..................................................................................... 60 Interrupts............................................................................................................. 60 Interrupt Registers.......................................................................................................................60 Interrupt Operation......................................................................................................................62 Multi-function Interrupt................................................................................................................63 Rev. 1.00 3 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Time Base Interrupt.....................................................................................................................63 Timer Module Interrupts .............................................................................................................64 Interrupt Wake-up Function.........................................................................................................64 Programming Considerations......................................................................................................64 Application Circuits............................................................................................ 65 Instruction Set..................................................................................................... 69 Introduction.................................................................................................................................69 Instruction Timing........................................................................................................................69 Moving and Transferring Data.....................................................................................................69 Arithmetic Operations..................................................................................................................69 Logical and Rotate Operation.....................................................................................................70 Branches and Control Transfer...................................................................................................70 Bit Operations.............................................................................................................................70 Table Read Operations...............................................................................................................70 Other Operations.........................................................................................................................70 Instruction Set Summary................................................................................... 71 Table Conventions.......................................................................................................................71 Instruction Definition.......................................................................................... 73 Package Information.......................................................................................... 82 8-pin SOP (150mil) Outline Dimensions.....................................................................................83 6-pin SOT23-6 Outline Dimensions............................................................................................84 Rev. 1.00 4 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Features CPU Features • Power Supply input voltage ♦♦ HT45F2020: 8V~16V ♦♦ HT45F2022: 2.2V~5.5V • Internal shunt regulator output: 5V – HT45F2020 only • Operating voltage ♦♦ fSYS=8MHz: 2.2V~5.5V • Up to 0.5μs instruction cycle with 8MHz system clock at VDD=5V • Power down and wake-up functions to reduce power consumption • Oscillators ♦♦ Internal High Speed RC – HIRC ♦♦ Internal 32kHz RC – LIRC • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • Fully integrated internal 8 MHz oscillator requires no external components • All instructions executed in one or two instruction cycles • Table read instructions • 63 powerful instructions • 2-level subroutine nesting • Bit manipulation instruction Peripheral Features • Flash Program Memory: 1K×14 • RAM Data Memory: 32×8 • Watchdog Timer function • 4 bidirectional I/O lines • One 10-bit PTM for time measure, compare match output, capture input, PWM output and single pulse output functions • One Time-Base function for generation of fixed time interrupt signals • Package type: SOT23-6, 8-pin SOP Rev. 1.00 5 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU General Description This series of devices are MCU based waveform generators especially designed for products which require custom sound effect generation. The internal microcontrollers are Flash Memory 8-bit high performance RISC architecture type. Offering users the convenience of Flash Memory multiprogramming features, the devices also includes a wide range of additional functions and features to assist with their custom audio generation. Other memory includes an area of RAM Data Memory. An extremely flexible Timer Module provides timing, pulse generation, capture input, compare match output and PWM generation functions. Protective features such as an internal Watchdog Timer coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of internal high speed and low speed oscillator functions are provided which require no external components for their implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. Additionally, an internal 5.0V shunt regulator is integrated within the HT45F2020 device offering voltage regulation features for a wide range of input operating voltages. When used alongside Holtek’s software development platform, designers are provided with the suite of tools to enable the easy generation and mixing of audio frequencies for the creation of custom sound effects. The inclusion of flexible I/O programming features, Time-Base function along with many other features ensure that the device will find excellent use in applications such as cars, motorcycles and electronic vehicles security alarm applications as well as many others etc. Selection Table The devices in this series offer similar functions differing only in the inclusion of a shunt regulator, which results in different operating voltage range. Part No. VDD Program Memory Data Memory I/O Timer Module Time Base Shunt Regulator Stacks Package HT45F2020 4.75V~ 5.25V 1K×14 32×8 4 10-bit PTM×1 1 √ 2 SOT23-6 8SOP HT45F2022 2.2V~ 5.5V 1K×14 32×8 4 10-bit PTM×1 1 ─ 2 SOT23-6 8SOP Rev. 1.00 6 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Block Diagram Flash Memory Programming Circuitry Flash Program Memory Reset Circuit Watchdog Timer RAM Data Memory 8-bit RISC MCU Core Interrupt Controller Internal HIRC/LIRC Oscillators Timer Module I/O Time Base * Shunt Regulator * The Shunt Regulator is only available for the HT45F2020 device. Pin Assignment PA3/PTP/PTPB PA1/PTP/PTPB PA2/PTCK/ICPCK 6 5 4 2020/2022 1 2 PA3/PTP/PTPB 1 8 VDD 2 7 PA0/PTPI/ICPDA 3 6 PA2/PTCK/ICPCK 4 5 VSS PA1/PTP/PTPB NC NC HT45F2020/HT45F2022 8 SOP-A Top View 3 PA0/PTPI/ICPDA VSS VDD HT45F2020/HT45F2022 SOT23-6-A VDD 1 16 PA3/PTP/PTPB VSS 2 15 PA1/PTP/PTPB PA0/PTPI/ICPDA 3 14 NC 4 13 PA2/PTCK/ICPCK NC NC 5 12 NC NC 6 11 NC NC 7 10 NC OCDSCK 8 9 OCDSDA HT45V2020/HT45V2022 16 NSOP-A Note: 1. If the pin-shared pin functions have multiple outputs simultaneously, the desired pin-shared function is determined by the corresponding software control bits. 2. The OCDSDA and OCDSCK pins are supplied for the OCDS dedicated pins and as such are only available for the HT45V2020 and HT45V2022 EV devices. Rev. 1.00 7 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Pin Description With the exception of the power pins, all pins on the device can be referenced by its Port name, e.g. PA0, PA1 etc., which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Timer Module pins etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. Pin Name PA0/PTPI/ICPDA PA1/PTP/PTPB PA2/PTCK/ICPCK PA3/PTP/PTPB Function OPT I/T O/T PA0 PAPU PAWU PAS0 ST CMOS Description General purpose I/O. Register enabled pull-high and wake-up. PTPI PAS0 ST — PTM capture input ICPDA — ST CMOS ICP Address/Data PA1 PAPU PAWU PAS0 ST CMOS General purpose I/O. Register enabled pull-high and wake-up. PTP PAS0 — CMOS PTM output PTPB PAS0 — CMOS PTM inverted output PA2 PAPU PAWU PAS0 ST CMOS General purpose I/O. Register enabled pull-high and wake-up. PTCK PAS0 ST — PTM clock input ICPCK — ST — ICP Clock pin PA3 PAPU PAWU PAS0 ST CMOS General purpose I/O. Register enabled pull-high and wake-up. PTP PAS0 — CMOS PTM output PTPB PAS0 — CMOS PTM inverted output VDD VDD — PWR — Power Supply VSS VSS — PWR — Ground The following pin are only for the HT45V2020/HT45V2022 NC NC — — — OCDSDA OCDSDA — ST CMOS No connection OCDSCK OCDSCK — ST — OCDS Address/Data, for EV chip only OCDS Clock pin, for EV chip only Legend: I/T: Input type O/T: Output type OPT: Optional by register option PWR: Power ST: Schmitt Trigger input CMOS: CMOS output Rev. 1.00 8 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Absolute Maximum Ratings Supply Voltage....................................................................................................VSS-0.3V to VSS+6.0V Input Voltage...................................................................................................... VSS-0.3V to VDD+0.3V Storage Temperature...................................................................................................... -50°C to 125°C Operating Temperature.................................................................................................... -40°C to 85°C IOL Total........................................................................................................................................ 80mA IOH Total....................................................................................................................................... -80mA Total Power Dissipation............................................................................................................ 500mW Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Ta=25°C Symbol VDD Parameter Max. Unit Typ. — 2.2 — 4.75 — 5.5 V — 5.25 3V No load, all peripherals off, 5V fSYS=fHIRC=8MHz V — 1.0 2.0 mA 3V No load, all peripherals off, 5V fSYS=fHIRC/2 , fHIRC=8MHz — 2.0 3.0 mA — 1.0 1.5 mA — 1.5 2.0 mA 3V No load, all peripherals off, 5V fSYS=fHIRC/4 , fHIRC=8MHz — 0.9 1.3 mA — 1.3 1.8 mA 3V No load, all peripherals off, 5V fSYS=fHIRC/8 , fHIRC=8MHz — 0.8 1.1 mA — 1.1 1.6 mA 3V No load, all peripherals off, 5V fSYS=fHIRC/16 , fHIRC=8MHz — 0.7 1.0 mA — 1.0 1.4 mA 3V No load, all peripherals off, 5V fSYS=fHIRC/32 , fHIRC=8MHz — 0.6 0.9 mA — 0.9 1.2 mA 3V No load, all peripherals off, 5V fSYS=fHIRC/64 , fHIRC=8MHz — 0.5 0.8 mA — 0.8 1.1 mA 3V No load, all peripherals off, 5V fSYS=fLIRC=32kHz — 10 20 μA — 30 50 μA 3V No load, all peripherals off, 5V WDT off — 0.2 0.8 μA — 0.5 1 μA 3V No load, all peripherals off, 5V WDT on — 1.3 5.0 μA — 2.2 10 μA Standby Current (IDLE0 Mode) 3V No load, all peripherals off, 5V fSUB on — 1.3 3.0 μA — 5.0 10 μA Standby Current (IDLE1 Mode, HIRC) 3V No load, all peripherals off, 5V fSUB on, fSYS=fHIRC=8MHz — 0.8 1.6 mA — 1.0 2.0 mA 5V — 0 — 1.5 V — — 0 — 0.2VDD V Operating Voltage – HT45F2022 — Operating Voltage* – HT45F2020 — IDD Operating Current (LIRC) Standby Current (SLEEP Mode) ISTB Rev. 1.00 Min. Conditions Operating Current (HIRC) VIL Test Conditions VDD Input Low Voltage for I/O Ports 9 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Symbol VIH IOL Parameter Input High Voltage for I/O Ports Sink Current for I/O Port IOH Source Current for I/O Ports RPH Pull-high Resistance for I/O Ports and OCDS pins ILEAK IOCDS Input Leakage Current Operating Current (Normal Mode) Test Conditions Min. Typ. Max. Unit — 3.5 — 0.8VDD — 5 V — VDD 3V VOL=0.1VDD V 18 36 — mA 5V VOL=0.1VDD 40 80 — mA 3V VOH=0.9VDD -3 -6 — mA 5V VOH=0.9VDD -7 -14 — mA VDD Conditions 5V — 3V — 20 60 100 kΩ 5V — 10 30 50 kΩ — — ±1 μA — — ±1 μA — 1.4 2.0 mA 3V 5V VIN=VDD or VIN=VSS No load, fSYS=fHIRC=8MHz, 3V WDT enable Note: For the HT45F2020 an external resistor should be serially connected between the supply power and VDD pin. Refer to the “Shunt Regulator” section for the details. A.C. Characteristics Ta=25°C Symbol fSYS fHIRC Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit System Clock (HIRC) 2.2V~5.5V fSYS=fHIRC=8MHz — 8 — MHz System Clock (LIRC) 2.2V~5.5V fSYS=fLIRC=32kHz — 32 — kHz High Speed Internal RC Oscillator (HIRC) 3V/5V Ta=25°C -2% 8 +2% MHz 3V/5V +5% MHz Ta=0°C to 70°C -5% 8 2.2V~5.5V Ta=0°C to 70°C -8% 8 +8% MHz 2.2V~5.5V Ta=-40°C to 85°C -12% 8 +12% MHz 2.2V~5.5V Ta=-40°C ~ 85°C 8 32 50 kHz fLIRC Low Speed Internal RC Oscillator (LIRC) 8 32 50 kHz tTCK PTCK Input Pin Minimum Pulse Width — — 0.3 — — μs tTPI PTPI Input Pin Minimum Pulse Width — — 0.3 — — μs System Reset Delay Time (POR Reset, WDT Software Reset) — — 25 50 100 ms System Reset Delay Time (WDT Time-out Hardware Cold Reset) — — 8.3 16.7 33.3 ms tRSTD System Start-up Timer Period (Wake-up from Power Down Mode and fSYS Off) tSST tSRESET System Start-up Timer Period (Slow Mode ↔ Normal Mode) System Start-up Timer Period (Wake-up from Power Down Mode and fSYS On) 2.2V~5.5V Ta=-40°C ~ 85°C — fSYS=fH ~ fH/64, fH=fHIRC 16 — — tHIRC — fSYS=fSUB=fLIRC 2 — — tLIRC — fHIRC off → on (HIRCF=1) 16 — — tHIRC — fSYS=fH ~ fH/64, fSYS=fHIRC 2 — — fH — fSYS=fLIRC 2 — — fSUB System Start-up Timer Period (WDT Time-out Hardware Cold Reset) — — 0 — — fH Minimum Software Reset Width to Reset — — 45 90 250 μs Note: 1. tSYS=1/fSYS 2.To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor should be connected between VDD and VSS and located as close to the device as possible. Rev. 1.00 10 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Shunt Regulator Electrical Characteristics – for HT45F2020 only Ta=25°C Symbol VUNREG Parameter Condition Supply Voltage Min. Typ. Max. Unit — VUNREG=8V~16V ISUPPLY=ISHUNT(Max) @ VUNREG=16V MCU in SLEEP mode, no load 8 — 16 V -3% 5 +3% V -5% 5 +5% V VOUT1 Load Voltage – No Load in Room Temperature VOUT2 ISUPPLY=ISHUNT(Max) @ VUNREG=16V Select RSER (1) as MCU in SLEEP mode Load Voltage – Load and supply with no load condition voltage within specification 1. VUNREG=8V, ILOAD=ILOAD(Max) 2. VUNREG=16V, ILOAD=0 ILOAD Load Current (2) VUNREG=8V~16V, RSER=(16-VOUT1) / ISHUNT(Max) 0 — 15 mA ISHUNT(Max) Maximum Shunt Current VUNREG=16V 80 — — mA ISTATIC Maximum Static Current VUNREG=16V — — 5 mA Line Regulation VUNREG=8 V to 16V RSER=(16V – VOUT1) / ISHUNT(Max) MCU in SLEEP mode, no load — — 0.3 %/V ∆VOUT_RIPPLE Output Voltage Ripple VUNREG=8 V to 16V, RSER=(16V – VOUT1) / ISHUNT(Max) MCU alternately consumes the average current IMCU and ILOAD(Max). The MCU varies its consumption current once every 0.5ms (3) — — 100 mV ∆VLOAD VUNREG=8V, 12V or 16V RSER=(16V – VOUT1) / ISHUNT(Max) ILOAD=0mA to ILOAD(Max), CBYPASS=4.7μF, MCU in SLEEP mode — — 0.03 %/mA ∆VLINE Load Regulation VUNREG ISUPPLY RSER ILOAD VDD VOUT VDD ISHUNT CBYPASS Feedback VSS VSS Shunt Regulator Operational Block Diagram Note: 1. RSER=(VUNREG – VOUT) / ISUPPLY 2. The load current maximum specification value is calculated based on the following formula. ILOAD(Max)=ISHUNT(Max) × (VUNREG(Min) – VOUT1(Max)) / (VUNREG(Max) – VOUT1(Min)) – ISTATIC(Measured) VUNREG(Max), VOUT1(Max)=Maximum specification value for VUNREG and VOUT1 respectively VUNREG(Min), VOUT1(Min)=Minimum specification value for VUNREG and VOUT1 respectively 3. IMCU=MCU current consumption measured when the MCU toggles two I/O pins every 0.5ms with no load. Rev. 1.00 11 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Power-on Reset Characteristics Ta=25°C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV RRPOR VDD Rising Rate to Ensure Power-on Reset — — 0.035 — — V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms VDD tPOR RRPOR VPOR Time System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The device takes advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O control system with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. Rev. 1.00 12 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU fSYS (System Clock) Phase Clock T1 Phase Clock T2 Phase Clock T3 Phase Clock T4 Program Counter Pipelining PC PC+1 PC+2 Fetch Inst. (PC) Execute Inst. (PC-1) Fetch Inst. (PC+1) Execute Inst. (PC) Fetch Inst. (PC+2) Execute Inst. (PC+1) System Clocking and Pipelining For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. 1 MOV A,[12H] 2 CALL DELAY 3 CPL [12H] 4 : 5 : 6 DELAY: NOP Fetch Inst. 1 Execute Inst. 1 Fetch Inst. 2 Execute Inst. 2 Fetch Inst. 3 Flush Pipeline Fetch Inst. 6 Execute Inst. 6 Fetch Inst. 7 Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as “JMP” or “CALL” that demands a jump to a nonconsecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Program Counter Program Counter High Byte PCL Register PC9~PC8 PCL7~PCL0 Program Counter Rev. 1.00 13 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly. However, as only this low byte is available for manipulation, the jumps are limited to the present page of memory that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is organized into 2 levels and neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. Program Counter Top of Stack Stack Pointer Stack Level 1 Stack Level 2 Bottom of Stack Program Memory Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA • Rotation: RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC • Increment and Decrement: INCA, INC, DECA, DEC • Branch decision: JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Rev. 1.00 14 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, the Flash device offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 1K×14 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. 000H Reset 008H Interrupt Vector 010H 014H 3FFH 14 bits Program Memory Structure Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 0000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP. This register defines the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the “TABRDC[m]” or “TABRDL[m]” instructions respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as “0”. Rev. 1.00 15 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU The accompanying diagram illustrates the addressing data flow of the look-up table. Last page or present page PC9~PC8 Program Memory Address PC High Byte TBLP Register Data 14 bits Register TBLH User Selected Register High Byte Low Byte Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is “300H” which refers to the start address of the last page within the 1K words Program Memory of the device. The table pointer is setup here to have an initial value of “06H”. This will ensure that the first data read from the data table will be at the Program Memory address “306H” or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the specific page if the “TABRDC [m]” instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the “TABRDC [m]” instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a ; to the last page or present page : : tabrdc tempreg1 ; transfers value in table referenced by table pointer, ; data at program memory address “306H” transferred to tempreg1 ; and TBLH dec tblp ; reduce value of table pointer by one tabrdc tempreg2 ; transfers value in table referenced by table pointer, ; data at program memory address “305H” transferred to tempreg2 and ; TBLH in this example the data “1AH” is transferred to tempreg1 and ; data “0FH” to register tempreg2 : : org 300h; sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : Rev. 1.00 16 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. The Holtek Flash MCU to Writer Programming Pin correspondence table is as follows: Holtek Writer Pins MCU Programming Pins Pin Description ICPDA PA0 Programming Serial Data/Address ICPCK PA2 Programming Clock VDD VDD Power Supply VSS VSS Ground The Program Memory can be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply. The technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. During the programming process, the user can take control of the ICPDA and ICPCK pins for data and clock programming purposes to ensure that no other outputs are connected to these two pins. Writer Connector Signals MCU Programming Pins Writer_VDD VDD ICPDA PA0 ICPCK PA2 Writer_VSS VSS * * To other Circuit Note: * may be resistor or capacitor. The resistance of * must be greater than 1kΩ or the capacitance of * must be less than 1nF. Rev. 1.00 17 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU On-Chip Debug Support – OCDS There are EV chips named HT45V2020 and HT45V2022, which are used to emulate the HT45F2020 and HT45F2022 devices. The EV chip device provides an “On-Chip Debug” function to debug the corresponding MCU device during the development process. The EV chip and the actual MCU device are almost functionally compatible except for the “On-Chip Debug” function. Users can use the EV chip device to emulate the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/ Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip for debugging, other functions which are shared with the OCDSDA and OCDSCK pins in the actual MCU device will have no effect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For a more detailed OCDS description, refer to the corresponding document named “Holtek e-Link for 8-bit MCU OCDS User’s Guide”. Holtek e-Link Pins EV Chip Pins Pin Description OCDSDA OCDSDA On-chip Debug Support Data/Address input/output OCDSCK OCDSCK On-chip Debug Support Clock input VDD VDD Power Supply VSS VSS Ground Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into two types, the first of these is an area of RAM, known as the Special Function Data Memory. Here are located registers which are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for general purpose use. All locations within this area are read and write accessible under program control. The start address of the Data Memory for all devices is the address 00H. General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user programing for both reading and writing operations. By using the bit operation instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Rev. 1.00 Capacity Location 32×8 Bank 0: 40H~5FH 18 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value “00H”. Bank 0 00H Bank0 IAR0 20H 01H MP0 21H 02H IAR1 22H PTMC0 03H MP1 23H PTMC1 04H 24H PTMDL 05H ACC 25H PTMDH 06H PCL 26H PTMAL 07H TBLP 27H PTMAH 08H TBLH 28H PTMRPL 29H PTMRPH 09H 0AH STATUS 2AH 0BH 2BH 0CH 2CH 0DH 2DH 0EH 2EH 0FH RSTFC 10H INTC0 30H 11H INTC1 31H 12H MFI 32H 2FH 13H 33H PA 34H 15H PAC 35H 16H PAPU 36H 17H PAWU 14H 37H 18H 38H 19H WDTC 1AH PSCR 1BH TBC 1CH SCC 1DH HIRCC 1EH 1FH PAS0 3FH : Unused, read as "00" Special Purpose Data Memory Rev. 1.00 19 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section, however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of “00H” and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks according to BP register. Direct Addressing can only be used with Bank 0, all other Banks must be addressed indirectly using MP1 and IAR1. Note that for the device, bit 7 of the Memory Pointers is not required to address the full memory space. When bit 7 of the Memory Pointers for the device is read, a value of “1” will be returned. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Indirect Addressing Program Example data .section ´data´ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ´code´ org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp0,a ; setup memory pointer with first RAM address loop: clr IAR0 ; clear the data at address defined by mp0 inc mp0; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Rev. 1.00 20 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user-defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBLH These two special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP is the table pointers and indicate the location where the table data is located. Its value must be setup before any table read commands are executed. Its value can be changed, for example using the “INC” or “DEC” instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the “CLR WDT” or “HALT” instruction. The PDF flag is affected only by executing the “HALT” or “CLR WDT” instruction or during a system power-up. Rev. 1.00 21 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU The Z, OV, AC, and C flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by executing the “HALT” instruction. • TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. STATUS Register Bit 7 6 5 4 3 2 1 0 Name — — TO PDF OV Z AC C R/W R/W — — R R R/W R/W R/W POR — — 0 0 x x x x “x”: unknown Rev. 1.00 Bit 7~6 Unimplemented, read as “0” Bit 5 TO: Watchdog Time-Out flag 0: After power up or executing the “CLR WDT” or “HALT” instruction 1: A watchdog time-out occurred. Bit 4 PDF: Power down flag 0: After power up or executing the “CLR WDT” instruction 1: By executing the “HALT” instruction Bit 3 OV: Overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2 Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1 AC: Auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0 C: Carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction. 22 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Oscillators Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through the relevant control register. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. Two fully integrated internal oscillators, requiring no external components, are provided to form a range of both fast and slow system oscillators. The higher frequency oscillator provides higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillator. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. Type Name Internal High Speed RC HIRC Frequency 8MHz Internal Low Speed RC LIRC 32kHz Oscillator Types System Clock Configurations There are two methods of generating the system clock, a high speed oscillator and a low speed oscillator. The high speed oscillator is the internal 8MHz RC oscillator. The low speed oscillator is the internal 32kHz RC oscillator. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the CKS2 ~ CKS0 bits in the SCC register and as the system clock can be dynamically selected. fH fH /2 High Speed Oscillator HIRCEN fH /4 fH /8 HIRC IDLE0 SLEEP Prescaler fSYS fH /16 fH /32 fH /64 Low Speed Oscillator LIRC CKS2~ CKS0 fLIRC fSUB IDLE2 SLEEP fSUB fLIRC System Clock Configurations Rev. 1.00 23 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU High Speed Internal RC Oscillator – HIRC The high speed internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a fixed frequency of 8MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of either 3V or 5V and at a temperature of 25°C degrees, the fixed oscillation frequency of 8MHz will have a tolerance within 2%. Internal 32kHz Oscillator – LIRC The internal 32kHz System Oscillator is the low frequency oscillator. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Supplementary Oscillators The low speed oscillator, in addition to providing a system clock source is also used to provide a clock source to two other device functions. These are the Watchdog Timer and the Time Base Interrupts. Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided the device with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The device has different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock selections using register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency, fH, or low frequency, fSUB, source, and is selected using the CKS2~CKS0 bits in the SCC register. The high speed system clock is sourced from the HIRC oscillator. The low speed system clock source can be sourced from the LIRC oscillator. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. Rev. 1.00 24 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU fH fH /2 High Speed Oscillator fH /4 fH /8 HIRC HIRCEN IDLE0 SLEEP Prescaler fSYS fH /16 fH /32 fH /64 Low Speed Oscillator LIRC CKS2~ CKS0 fLIRC fSUB IDLE2 SLEEP fSUB fSYS fSYS/4 fPSC fSUB Prescaler Time Base TB[2:0] CLKSEL[1:0] fLIRC WDT Device Clock Configurations Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillator can be stopped to conserve the power or continue to oscillate to provide the clock source, fH~fH/64, for peripheral circuit to use, which is determined by configuring the corresponding high speed oscillator enable control bit. System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP, IDLE0, IDLE1 and IDLE2 Mode are used when the microcontroller CPU is switched off to conserve power. Operation Mode CPU NORMAL Mode SLOW Mode Related Register value fSYS fH fSUB fLIRC On On On On On On/Off(1) On On Off On On On On On On Off On Off Off On/Off(2) FHIDEN FSIDEN CKS[2:0] On x x 000~110 On x x 111 000~110 Off 111 On IDLE0 Mode Off 0 1 IDLE1 Mode Off 1 1 IDLE2 Mode Off 1 0 SLEEP Mode Off 0 0 xxx On 000~110 On 111 Off xxx Off “x”: Don’t care Note: 1. The fH clock will be switched on or off by configuring the corresponding oscillator enable bit in the SLOW mode. 2. The fLIRC clock can be switched on or off which is controlled by the WDT function being enabled or disabled in the SLEEP mode. Rev. 1.00 25 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillators. This mode operates allowing the microcontroller to operate normally with a clock source will come from the high speed oscillators HIRC. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 bits in the SCC register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from fSUB. The fSUB clock is derived from the LIRC oscillator. Running the microcontroller in this mode allows it to run with much lower operating currents. SLEEP Mode The SLEEP Mode is entered when an HALT instruction is executed and when the FHIDEN and FSIDEN bit are low. In the SLEEP mode the CPU will be stopped, and the fSUB clock to peripheral will be stopped too, but the Watchdog Timer function is decided by user application. IDLE0 Mode The IDLE0 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is low and the FSIDEN bit in the SCC register is high. In the IDLE0 Mode the CPU will be switched off but the low speed oscillator will be turned on to drive some peripheral functions. IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is high and the FSIDEN bit in the SCC register is high. In the IDLE1 Mode the CPU will be switched off but both the high and low speed oscillators will be turned on to provide a clock source to keep some peripheral functions operational. IDLE2 Mode The IDLE2 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is high and the FSIDEN bit in the SCC register is low. In the IDLE2 Mode the CPU will be switched off but the high speed oscillator will be turned on to provide a clock source to keep some peripheral functions operational. Rev. 1.00 26 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Control Register The registers, SCC and HIRCC, are used to control the system clock and the corresponding oscillator configurations. Bit Register Name 7 6 5 4 3 2 1 SCC CKS2 CKS1 CKS0 — — — FHIDEN FSIDEN HIRCC — — — — — — HIRCF HIRCEN 0 System Operating Mode Control Registers List SCC Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 — — — FHIDEN FSIDEN R/W R/W R/W R/W — — — R/W R/W POR 0 0 0 — — — 0 0 Bit 7~5 CKS2~CKS0: System clock selection 000: fH 001: fH/2 010: fH/4 011: fH/8 100: fH/16 101: fH/32 110: fH/64 111: fSUB These three bits are used to select which clock is used as the system clock source. In addition to the system clock source directly derived from fH or fSUB, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4~2 Unimplemented, read as “0” Bit 1 FHIDEN: High Frequency oscillator control when CPU is switched off 0: Disable 1: Enable This bit is used to control whether the high speed oscillator is activated or stopped when the CPU is switched off by executing an “HALT” instruction. Bit 0 FSIDEN: Low Frequency oscillator control when CPU is switched off 0: Disable 1: Enable This bit is used to control whether the low speed oscillator is activated or stopped when the CPU is switched off by executing an “HALT” instruction. 27 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU HIRCC Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — HIRCF HIRCEN R/W — — — — — — R/W R/W POR — — — — — — 0 1 Bit 7~2 Unimplemented, read as “0” Bit 1 HIRCF: HIRC oscillator stable flag 0: Unstable 1: Stable This bit is used to indicate whether the HIRC oscillator is stable or not. When the HIRCEN bit is set to 1 to enable the HIRC oscillator, the HIRCF bit will first be cleared to 0 and then set to 1 after the HIRC oscillator is stable. Bit 0 HIRCEN: HIRC oscillator enable control 0: Disable 1: Enable Operating Mode Switching The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the CKS2~CKS0 bits in the SCC register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When an HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the FHIDEN and FSIDEN bits in the SCC register. NORMAL fSYS=fH~fH/64 fH on CPU run fSYS on fSUB on SLOW fSYS=fSUB fSUB on CPU run fSYS on fH on/off SLEEP HALT instruction executed CPU stop FHIDEN=0 FSIDEN=0 fH off fSUB off IDLE0 HALT instruction executed CPU stop FHIDEN=0 FSIDEN=1 fH off fSUB on IDLE2 HALT instruction executed CPU stop FHIDEN=1 FSIDEN=0 fH on fSUB off Rev. 1.00 28 IDLE1 HALT instruction executed CPU stop FHIDEN=1 FSIDEN=1 fH on fSUB on April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the CKS2~CKS0 bits to “111” in the SCC register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LIRC oscillator and therefore requires this oscillator to be stable before full mode switching occurs. NORMAL Mode CKS2~CKS0 = 111 SLOW Mode FHIDEN=0, FSIDEN=0 HALT instruction is executed SLEEP Mode FHIDEN=0, FSIDEN=1 HALT instruction is executed IDLE0 Mode FHIDEN=1, FSIDEN=1 HALT instruction is executed IDLE1 Mode FHIDEN=1, FSIDEN=0 HALT instruction is executed IDLE2 Mode Rev. 1.00 29 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU SLOW Mode to NORMAL Mode Switching In SLOW mode the system clock is derived from fSUB. When system clock is switched back to the NORMAL mode from fSUB, the CKS2~CKS0 bits should be set to “000” ~“110” and then the system clock will respectively be switched to fH~ fH/64. However, if fH is not used in SLOW mode and thus switched off, it will take some time to reoscillate and stabilise when switching to the NORMAL mode from the SLOW Mode. This is monitored using the HIRCF bit in the HIRCC register. The time duration required for the high speed system oscillator stabilization is specified in the A.C. characteristics. SLOW Mode CKS2~CKS0 = 000~110 NORMAL Mode FHIDEN=0, FSIDEN=0 HALT instruction is executed SLEEP Mode FHIDEN=0, FSIDEN=1 HALT instruction is executed IDLE0 Mode FHIDEN=1, FSIDEN=1 HALT instruction is executed IDLE1 Mode FHIDEN=1, FSIDEN=0 HALT instruction is executed IDLE2 Mode Entering the SLEEP Mode There is only one way for the device to enter the SLEEP Mode and that is to execute the “HALT” instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register equal to “0”. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting as the WDT is enabled. If the WDT is disabled then WDT will be cleared and stopped. Rev. 1.00 30 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the “HALT” instruction in the application program with the FHIDEN bit in the SCC register equal to “0” and the FSIDEN bit in the SCC register equal to “1”. When this instruction is executed under the conditions described above, the following will occur: • The fH clock will be stopped and the application program will stop at the “HALT” instruction, but the fSUB clock will be on. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting as the WDT is enabled. If the WDT is disabled then WDT will be cleared and stopped. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the “HALT” instruction in the application program with the FHIDEN bit in SCC register equal to “1” and the FSIDEN bit in the SCC register equal to “1”. When this instruction is executed under the conditions described above, the following will occur: • The fH and fSUB clocks will be on but the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting as the WDT is enabled. If the WDT is disabled then WDT will be cleared and stopped. Entering the IDLE2 Mode There is only one way for the device to enter the IDLE2 Mode and that is to execute the “HALT” instruction in the application program with the FHIDEN bit in the SCC register equal to “1” and the FSIDEN bit in SCC register equal to “0”. When this instruction is executed under the conditions described above, the following will occur: • The fH clock will be on but the fSUB clock will be off and the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting as the WDT is enabled. If the WDT is disabled then WDT will be cleared and stopped. Rev. 1.00 31 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 and IDLE2 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the LIRC oscillator has enabled. In the IDLE1 and IDLE2 Mode the high speed oscillator is on, if the peripheral function clock source is derived from the high speed oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. Wake-up To minimise power consumption the device can enter the SLEEP or any IDLE Mode, where the CPU will be switched off. However, when the device is woken up again, it will take a considerable time for the original system oscillator to restart, stablise and allow normal operation to resume. After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external falling edge on Port A • A system interrupt • A WDT overflow When the device executes the “HALT” instruction, the PDF flag will be set to 1. The PDF flag will be cleared to 0 if the device experiences a system power-up or executes the clear Watchdog Timer instruction. If the system is woken up by a WDT overflow, a Watchdog Timer reset will be initiated and the TO flag will be set to 1. The TO flag is set if a WDT time-out occurs and causes a wake-up that only resets the Program Counter and Stack Pointer, other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the “HALT” instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the “HALT” instruction. In this situation, the interrupt which woke up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Rev. 1.00 32 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal fLIRC clock which is supplied by the LIRC oscillator. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 215 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable and reset MCU operation. This register controls the overall operation of the Watchdog Timer. WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~3 WE4~WE0: WDT function software control 10101: Disable 01010: Enable Other values: Reset MCU(The reset operation will be activated after tSRESET time.) When these bits are changed by the environmental noise or software setting to reset the microcontroller, the reset operation will be activated after a delay time, tSRESET, and the WRF bit in the RSTFC register will be set to 1. Bit 2~0 WS2~WS0: WDT time-out period selection 000: 28/fLIRC 001: 29/fLIRC 010: 210/fLIRC 011: 211/fLIRC 100: 212/fLIRC 101: 213/fLIRC 110: 214/fLIRC 111: 215/fLIRC These three bits determine the division ratio of the Watchdog Timer source clock, which in turn determines the timeout period. RSTFC Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name — — — — — — — WRF R/W — — — — — — — R/W POR — — — — — — — 0 Bit 7~1 Unimplemented, read as “0” Bit 0 WRF: WDT control register software reset flag 0: Not occurred 1: Occurred This bit is set to 1 by the WDT control register software reset and cleared by the application program. Note that this bit can only be cleared to 0 by the application program. 33 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. With regard to the Watchdog Timer enable/disable function, there are five bits, WE4~WE0, in the WDTC register to offer additional enable/disable and reset control of the Watchdog Timer. The WDT function will be disabled when the WE4~WE0 bits are set to a value of 10101B. The WDT function will be enabled if the WE4~WE0 bits value is equal to 01010B. If the WE4~WE0 bits are set to any other values by the environmental noise or software setting, except 01010B and 10101B, it will reset the device after a delay time, tSRESET. After power on these bits will have the value of 01010B. WE4~WE0 Bits WDT Function 10101B Disable 01010B Enable Any other value Reset MCU Watchdog Timer Enable/Disable Control Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is a WDT reset, which means a certain value except 01010B and 10101B written into the WE4~WE0 bit filed, the second is using the Watchdog Timer software clear instruction and the third is via a HALT instruction. There is only one method of using software instruction to clear the Watchdog Timer. That is to use the single “CLR WDT” instruction to clear the WDT. The maximum time out period is when the 215 division ratio is selected. As an example, with a 32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 1 seconds for the 215 division ratio, and a minimum timeout of 8ms for the 28 division ration. WDTC WE4~WE0 bits Register Reset MCU CLR “ HALT ”Instruction “CLR WDT”Instruction LIRC fLIRC 8-stage Divider fLIRC/28 WDT Prescaler WS2~WS0 8-to- 1 MUX WDT Time-out (28 /fLIRC ~ 215 /fLIRC) Watchdog Timer Rev. 1.00 34 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well-defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. Another type of reset is when the Watchdog Timer overflows and resets. All types of reset operations result in different register conditions being setup. Reset Functions There are three ways in which a reset can occur, each of which will be described as follows. Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all I/O ports will be first set to inputs. VDD Power-on Reset tRSTD SST Time-out Note: tRSTD is power-on delay with typical time=50 ms Power-On Reset Timing Chart Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is a little different from Power-on reset. Most of the conditions remain unchanged except that the Watchdog time-out flag TO will be set to “1”. WDT Time-out tRSTD + tSST Internal Reset Note: tRSTD is power-on delay with typical time=16.7 ms WDT Time-out Reset during Normal Operation Timing Chart Rev. 1.00 35 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from Power-on reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to “0” and the TO flag will be set to “1”. Refer to the A.C. Characteristics for tSST details. WDT Time-out tSST Internal Reset WDT Time-out Reset during SLEEP or IDLE Timing Chart Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 0 Power-on reset Reset Conditions 1 u WDT time-out reset during Normal or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation Note: “u” stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Rev. 1.00 Condition after Reset Program Counter Reset to zero Interrupts All interrupts will be disabled WDT,Time Base Clear after reset, WDT begins counting Timer Module Timer Module will be turned off Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack 36 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Reset (Power On) Register Program Counter WDT Time-out (Normal Operation) WDT Time-out (IDLE/SLEEP)* 000H 000H 000H MP0 xxxx xxxx xxxx xxxx uuuu uuuu MP1 xxxx xxxx xxxx xxxx uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu TBLH --xx xxxx --uu uuuu --uu uuuu STATUS --00 xxxx --1u uuuu - - 11 u u u u RSTFC ---- ---0 ---- ---u ---- ---u INTC0 --0- -0-0 --0- -0-0 --u- -u-u INTC1 ---0 ---0 ---0 ---0 ---u ---u MFI --00 --00 --00 --00 --uu --uu PA - - - - 1111 - - - - 1111 ---- uuuu PAC - - - - 1111 - - - - 1111 ---- uuuu PAPU ---- 0000 ---- 0000 ---- uuuu PAWU ---- 0000 ---- 0000 ---- uuuu WDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 uuuu uuuu PSCR ---- --00 ---- --00 ---- --uu TBC 0--- -000 0--- -000 u--- -uuu SCC 000- --00 000- --00 uuu- --uu HIRCC ---- --01 ---- --01 ---- --uu PAS0 0000 0000 0000 0000 uuuu uuuu PTMC0 0000 0--- 0000 0--- uuuu u--- PTMC1 0000 0000 0000 0000 uuuu uuuu PTMDL 0000 0000 0000 0000 uuuu uuuu PTMDH ---- --00 ---- --00 ---- --uu uuuu uuuu PTMAL 0000 0000 0000 0000 PTMAH ---- --00 ---- --00 ---- --uu PTMRPL 0000 0000 0000 0000 uuuu uuuu PTMRPH ---- --00 ---- --00 ---- --uu Note: “u” stands for unchanged “x” stands for unknown “-” stands for unimplemented Rev. 1.00 37 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port name PA. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction “MOV A, [m]”, where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Bit Register Name 7 6 5 4 3 2 1 0 PA — — — — PA3 PA2 PA1 PA0 PAC — — — — PAC3 PAC2 PAC1 PAC0 PAPU — — — — PAPU3 PAPU2 PAPU1 PAPU0 PAWU — — — — PAWU3 PAWU2 PAWU1 PAWU0 I/O Logic Function Register List Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using the relevant pull-high control registers PAPU, and are implemented using weak PMOS transistors. Note that the pull-high resistor can be controlled by the relevant pull-high control registers only when the pin-shared functional pin is selected as a digital input or NMOS output. Otherwise, the pull-high resistors cannot be enabled. PAPU Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name — — — — PAPU3 PAPU2 PAPU1 PAPU0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3~0 PAPU3~PAPU0: Port A bit 3 ~ bit 0 Pull-high Control 0: Disable 1: Enable 38 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. Note that the wake-up function can be controlled by the wake-up control registers only when the pin-shared functional pin is selected as general purpose input/output and the MCU enters the Power down mode. PAWU Register Bit 7 6 5 4 3 2 1 0 Name — — — — PAWU3 PAWU2 PAWU1 PAWU0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3~0 PAWU3~PAWU0: Port A bit 3 ~ bit 0 Wake-up Control 0: Disable 1: Enable I/O Port Control Registers Each I/O port has its own control register known as PAC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a “1”. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a “0”, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. PAC Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name — — — — PAC3 PAC2 PAC1 PAC0 R/W — — — — R/W R/W R/W R/W POR — — — — 1 1 1 1 Bit 7~4 Unimplemented, read as “0” Bit 3~0 PAC3~PAC0: Port A bit 3 ~ bit 0 Input/Output Control 0: Output 1: Input 39 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For these pins, the desired function of the multi-function I/O pins is selected by the application program control. Pin-shared Function Selection Registers The limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. However by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. The device includes Port A output function selection register “n”, labeled as PASn, which can select the desired functions of the multi-function pin-shared pins. When the pin-shared input function is selected to be used, the corresponding input and output functions selection should be properly managed. The most important point to note is to make sure that the desired pin-shared function is properly selected and also deselected. To select the desired pin-shared function, the pin-shared function should first be correctly selected using the corresponding pin-shared control register. After that the corresponding peripheral functional setting should be configured and then the peripheral function can be enabled. To correctly deselect the pin-shared function, the peripheral function should first be disabled and then the corresponding pin-shared function control register can be modified to select other pin-shared functions. PAS0 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PAS07~PAS06: PA3 pin function selection 0x: PA3 10: PTP 11: PTPB Bit 5~4 PAS05~PAS04: PA2 pin function selection 00: PA2/PTCK 01: PA2/PTCK 10: PA2/PTCK 11: PA2/PTCK Bit 3~2 PAS03~PAS02: PA1 pin function selection 0x: PA1 10: PTP 11: PTPB Bit 1~0 PAS01~PAS00: PA0 pin function selection 00: PA0/PTPI 01: PA0/PTPI 10: PA0/PTPI 11: PA0/PTPI 40 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU I/O Pin Structures The accompanying diagram illustrates the internal structure of the I/O logic function. As the exact logical construction of the I/O pin will differ from this diagram, it is supplied as a guide only to assist with the functional understanding of the logic function I/O pins. The wide range of pin-shared structures does not permit all types to be shown. VDD Control Bit Data Bus Write Control Register Chip Reset Read Control Register D Weak Pull-up CK Q S I/O pin Data Bit D Write Data Register Q Pull-high Register Select Q CK Q S Read Data Register System Wake-up M U X wake-up Select PA only Logic Function Input/Output Structure Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control register, PAC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data register, PA, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the “SET [m].i” and “CLR [m].i” instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Rev. 1.00 41 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions the device includes a Periodic Timer Module, generally abbreviated to the name PTM. The PTM are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. The PTM has two individual interrupts. The addition of input and output pins for the PTM ensures that users are provided with timing units with a wide and flexible range of features. The brief features of the Periodic TM are described here with more detailed information provided in the Periodic Type TM section. Introduction The device contains a 10-bit Periodic Type TM. The main features of the PTM are summarised in the accompanying table. TM Function PTM Timer/Counter √ Input Capture √ Compare Match Output √ PWM Channels 1 Single Pulse Output 1 PWM Alignment Edge PWM Adjustment Period & Duty Duty or Period PTM Function Summary TM Operation The Periodic TM offers a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running count-up counter whose value is then compared with the value of pre-programmed internal comparators. When the free running count-up counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. TM Clock Source The clock source which drives the main counter in the PTM can originate from various sources. The selection of the required clock source is implemented using the PTCK2~PTCK0 bits in the PTM control register, PTMC0. The clock source can be a ratio of the system clock, fSYS, or the internal high clock, fH, the fSUB clock source or the external PTCK pin. The PTCK pin clock source is used to allow an external signal to drive the TM as an external clock source for event counting. TM Interrupts The Periodic type TM has two internal interrupts, the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated, it can be used to clear the counter and also to change the state of the TM output pin. Rev. 1.00 42 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU TM External Pins The Periodic type TM has two TM input pins, with the label PTCK and PTPI respectively. The PTM input pin, PTCK, is essentially a clock source for the PTM and is selected using the PTCK2~PTCK0 bits in the PTMC0 register. This external TM input pin allows an external clock source to drive the internal TM. The PTCK input pin can be chosen to have either a rising or falling active edge. The PTCK pin is also used as the external trigger input pin in single pulse output mode for the PTM respectively. The other PTM input pin, PTPI, is the capture input whose active edge can be a rising edge, a falling edge or both rising and falling edges and the active edge transition type is selected using the PTIO1~PTIO0 bits in the PTMC1 register respectively. There is another capture input, PTCK, for PTM capture input mode, which can be used as the external trigger input source except the PTPI pin. The PTM has two output pins, PTP and PTPB. The PTPB is the inverted signal of the PTP output. The TM output pins can be selected using the corresponding pin-shared function selection bits described in the Pin-shared Function section. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external PTP or PTPB output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other functions, the TM output function must first be setup using relevant pin-shared function selection register. PTM Input Output PTCK, PTPI PTP, PTPB TM External Pins TM Input/Output Pin Selection Selecting to have a TM input/output or whether to retain its other shared function is implemented using the relevant pin-shared function selection registers, with the corresponding selection bits in each pin-shared function register corresponding to a TM input/output pin. Configuring the selection bits correctly will setup the corresponding pin as a TM input/output. The details of the pin-shared function selection are described in the pin-shared function section. PTCK CCR capture input PTPI PTM CCR output PTP PTPB PTM Function Pin Control Block Diagram Rev. 1.00 43 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA and CCRP registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way as described above, it is recommended to use the “MOV” instruction to access the CCRA and CCRP low byte registers, named PTMAL and PTMRPL, using the following access procedures. Accessing the CCRA or CCRP low byte registers without following these access procedures will result in unpredictable values. PTM Counter Register (Read only) PTMDL PTMDH 8-bit Buffer PTMAL PTMAH PTM CCRA Register (Read/Write) PTMRPL PTMRPH PTM CCRP Register (Read/Write) Data Bus The following steps show the read and write procedures: • Writing Data to CCRA or CCRP ♦♦ Step 1. Write data to Low Byte PTMAL or PTMRPL ––note that here data is only written to the 8-bit buffer. ♦♦ Step 2. Write data to High Byte PTMAH or PTMRPH ––here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. • Reading Data from the Counter Registers and CCRA or CCRP Rev. 1.00 ♦♦ Step 1. Read data from the High Byte PTMDH, PTMAH or PTMRPH ––here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte PTMDL, PTMAL or PTMRPL ––this step reads data from the 8-bit buffer. 44 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Periodic Type TM – PTM The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can also be controlled with two external input pins and can drive two external output pin. PTM Core PTM Input Pin PTM Output Pin 10-bit PTM PTCK, PTPI PTP, PTPB CCRP fSYS/4 fSYS fH/16 fH/64 fSUB fSUB 10-bit Comparator P 001 PTMPF Interrupt PTOC b0~b9 010 011 10-bit Count-up Counter 100 101 110 PTCK Comparator P Match 000 PTON PTPAU 10-bit Comparator A CCRA Output Control Polarity Control Pin Control PTM1, PTM0 PTIO1, PTIO0 PTPOL PAS0 0 1 PTCCLR b0~b9 111 PTCK2~PTCK0 Counter Clear Comparator A Match PTIO1, PTIO0 PTCAPTS Edge Detector 0 1 PTP PTPB PTMAF Interrupt PAS0 Pin Control PTPI Periodic Type TM Block Diagram Periodic TM Operation The size of Periodic TM is 10-bit wide and its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP and CCRA comparators are 10-bit wide whose value is respectively compared with all counter bits. The only way of changing the value of the 10-bit counter using the application program is to clear the counter by changing the PTON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a PTM interrupt signal will also usually be generated. The Periodic Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control the output pins. All operating setup conditions are selected using relevant internal registers. Rev. 1.00 45 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Periodic Type TM Register Description Overall operation of the Periodic TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA and CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Bit Register Name 7 6 5 4 3 2 1 0 PTMC0 PTPAU PTCK2 PTCK1 PTCK0 PTON — — — PTMC1 PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTMDL D7 D6 D5 D4 D3 D2 D1 D0 PTMDH — — — — — — D9 D8 D0 PTCAPTS PTCCLR PTMAL D7 D6 D5 D4 D3 D2 D1 PTMAH — — — — — — D9 D8 PTMRPL PTRP7 PTRP6 PTRP5 PTRP4 PTRP3 PTRP2 PTRP1 PTRP0 PTMRPH — — — — — — PTRP9 PTRP8 2 1 0 — Periodic TM Registers List PTMC0 Register Rev. 1.00 Bit 7 6 5 4 3 Name PTPAU PTCK2 PTCK1 PTCK0 PTON — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7 PTPAU: PTM Counter Pause control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the PTM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 PTCK2~PTCK0: Select PTM Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: PTCK rising edge clock 111: PTCK falling edge clock These three bits are used to select the clock source for the PTM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. 46 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Bit 3 PTON: PTM Counter On/Off control 0: Off 1: On This bit controls the overall on/off function of the PTM. Setting the bit high enables the counter to run while clearing the bit disables the PTM. Clearing this bit to zero will stop the counter from counting and turn off the PTM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the PTM is in the Compare Match Output Mode or the PWM output Mode or Single Pulse Output Mode, then the PTM output pin will be reset to its initial condition, as specified by the PTOC bit, when the PTON bit changes from low to high. Bit 2~0 Unimplemented, read as “0” PTMC1 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 PTCAPTS PTCCLR Bit 7~6 PTM1~PTM0: Select PTM Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Output Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the PTM. To ensure reliable operation the PTM should be switched off before any changes are made to the PTM1 and PTM0 bits. In the Timer/Counter Mode, the PTM output pin control will be disabled. Bit 5~4 PTIO1~PTIO0: Select PTM external pin PTP or PTPI function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single Pulse Output Capture Input Mode 00: Input capture at rising edge of PTPI or PTCK 01: Input capture at falling edge of PTPI or PTCK 10: Input capture at rising/falling edge of PTPI or PTCK 11: Input capture disabled Timer/Counter Mode Unused These two bits are used to determine how the PTM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the PTM is running. 47 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU In the Compare Match Output Mode, the PTIO1 and PTIO0 bits determine how the PTM output pin changes state when a compare match occurs from the Comparator A. The PTM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the PTM output pin should be setup using the PTOC bit in the PTMC1 register. Note that the output level requested by the PTIO1 and PTIO0 bits must be different from the initial value setup using the PTOC bit otherwise no change will occur on the PTM output pin when a compare match occurs. After the PTM output pin changes state, it can be reset to its initial level by changing the level of the PTON bit from low to high. In the PWM Mode, the PTIO1 and PTIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PTM output function is modified by changing these two bits. It is necessary to only change the values of the PTIO1 and PTIO0 bits only after the PTM has been switched off. Unpredictable PWM outputs will occur if the PTIO1 and PTIO0 bits are changed when the PTM is running. Bit 3 PTOC: PTM PTP Output control Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the PTM output pin. Its operation depends upon whether PTM is being used in the Compare Match Output Mode or in the PWM Mode/Single Pulse Output Mode. It has no effect if the PTM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the PTM output pin before a compare match occurs. In the PWM Mode/Single Pulse Output Mode it determines if the PWM signal is active high or active low. Bit 2 PTPOL: PTM PTP Output polarity control 0: Non-inverted 1: Inverted This bit controls the polarity of the PTP output pin. When the bit is set high the PTM output pin will be inverted and not inverted when the bit is zero. It has no effect if the PTM is in the Timer/Counter Mode. Bit 1PTCAPTS: PTM Capture Triiger Source selection 0: From PTPI pin 1: From PTCK pin Bit 0PTCCLR: PTM Counter Clear condition selection 0: Comparator P match 1: Comparator A match This bit is used to select the method which clears the counter. Remember that the Periodic TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the PTCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The PTCCLR bit is not used in the PWM Output, Single Pulse Output or Capture Input Mode. Rev. 1.00 48 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU PTMDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 PTM Counter Low Byte Register bit 7 ~ bit 0 PTM 10-bit Counter bit 7 ~ bit 0 PTMDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 3 2 1 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0 PTM Counter High Byte Register bit 1 ~ bit 0 PTM 10-bit Counter bit 9 ~ bit 8 PTMAL Register Bit 7 6 5 4 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 PTM CCRA Low Byte Register bit 7 ~ bit 0 PTM 10-bit CCRA bit 7 ~ bit 0 PTMAH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0 PTM CCRA High Byte Register bit 1 ~ bit 0 PTM 10-bit CCRA bit 9 ~ bit 8 PTMRPL Register Bit 7 6 5 4 3 2 1 0 Name PTRP7 PTRP6 PTRP5 PTRP4 PTRP3 PTRP2 PTRP1 PTRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.00 PTM CCRP Low Byte Register bit 7 ~ bit 0 PTM 10-bit CCRP bit 7 ~ bit 0 49 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU PTMRPH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — PTRP9 PTRP8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0 PTM CCRP High Byte Register bit 1 ~ bit 0 PTM 10-bit CCRP bit 9 ~ bit 8 Periodic Type TM Operation Modes The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the PTM1 and PTM0 bits in the PTMC1 register. Compare Match Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the PTCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both PTMAF and PTMPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the PTCCLR bit in the PTMC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the PTMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when PTCCLR is high no PTMPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to “0”. As the name of the mode suggests, after a comparison is made, the PTM output pin will change state. The PTM output pin condition however only changes state when a PTMAF interrupt request flag is generated after a compare match occurs from Comparator A. The PTMPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the PTM output pin. The way in which the PTM output pin changes state are determined by the condition of the PTIO1 and PTIO0 bits in the PTMC1 register. The PTM output pin can be selected using the PTIO1 and PTIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the PTM output pin, which is setup after the PTON bit changes from low to high, is setup using the PTOC bit. Note that if the PTIO1 and PTIO0 bits are zero then no pin change will take place. Rev. 1.00 50 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Counter overflow Counter Value 0x3FF PTCCLR = 0; PTM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value CCRP=0 CCRP > 0 Counter Restart Resume CCRP Pause CCRA Stop Time PTON PTPAU PTPOL CCRP Int. Flag PTMPF CCRA Int. Flag PTMAF PTM O/P Pin Output pin set to initial Level Low if PTOC=0 Output not affected by PTMAF flag. Remains High until reset by PTON bit Output Toggle with PTMAF flag Here PTIO [1:0] = 11 Toggle Output select Note PTIO [1:0] = 10 Active High Output select Output Inverts when PTPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – PTCCLR=0 Note: 1. With PTCCLR=0, a Comparator P match will clear the counter 2. The PTM output pin is controlled only by the PTMAF flag 3. The output pin is reset to its initial state by a PTON bit rising edge Rev. 1.00 51 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Counter Value PTCCLR = 1; PTM [1:0] = 00 CCRA = 0 Counter overflow CCRA > 0 Counter cleared by CCRA value 0x3FF Resume CCRA Pause CCRA=0 Stop Counter Restart CCRP Time PTON PTPAU PTPOL No PTMAF flag generated on CCRA overflow CCRA Int. Flag PTMAF CCRP Int. Flag PTMPF PTM O/P Pin PTMPF not generated Output pin set to initial Level Low if PTOC=0 Output does not change Output Toggle with PTMAF flag Here PTIO [1:0] = 11 Toggle Output select Output not affected by PTMAF flag. Remains High until reset by PTON bit Note PTIO [1:0] = 10 Active High Output select Output Inverts when PTPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – PTCCLR=1 Note: 1. With PTCCLR=1, a Comparator A match will clear the counter 2. The PTM output pin is controlled only by the PTMAF flag 3. The output pin is reset to its initial state by a PTON bit rising edge 4. A PTMPF flag is not generated when PTCCLR =1 Rev. 1.00 52 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Timer/Counter Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the PTM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the PTM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 10 respectively and also the PTIO1 and PTIO0 bits should be set to 10 respectively. The PWM function within the PTM is useful for applications which require functions such as motor control, heating control, illumination control, etc. By providing a signal of fixed frequency but of varying duty cycle on the PTM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the PTCCLR bit has no effect as the PWM period. Both of the CCRP and CCRA registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The PTOC bit in the PTMC1 register is used to select the required polarity of the PWM waveform while the two PTIO1 and PTIO0 bits are used to enable the PWM output or to force the PTM output pin to a fixed high or low level. The PTPOL bit is used to reverse the polarity of the PWM output waveform. • 10-bit PWM Output Mode, Edge-aligned Mode CCRP 1~1023 0 Period 1~1023 1024 Duty CCRA If fSYS=16MHz, TM clock source select fSYS/4, CCRP=512 and CCRA=128, The PTM PWM output frequency=(fSYS/4)/512=fSYS/2048=7.8125kHz, duty=128/512=25%, If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. Rev. 1.00 53 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Counter Value PTM [1:0] = 10 Counter cleared by CCRP Counter Reset when PTON returns high CCRP Pause Resume Counter Stop if PTON bit low CCRA Time PTON PTPAU PTPOL CCRA Int. Flag PTMAF CCRP Int. Flag PTMPF PTM O/P Pin (PTOC=1) PTM O/P Pin (PTOC=0) PWM Duty Cycle set by CCRA PWM Period set by CCRP PWM resumes operation Output controlled by Output Inverts other pin-shared function When PTPOL = 1 PWM Mode Note: 1. The counter is cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when PTIO [1:0]=00 or 01 4. The PTCCLR bit has no influence on PWM operation Rev. 1.00 54 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Single Pulse Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 10 respectively and also the PTIO1 and PTIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the PTM output pin. The trigger for the pulse output leading edge is a low to high transition of the PTON bit, which can be implemented using the application program. However in the Single Pulse Mode, the PTON bit can also be made to automatically change from low to high using the external PTCK pin, which will in turn initiate the Single Pulse output. When the PTON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The PTON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the PTON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the PTON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a PTM interrupt. The counter can only be reset back to zero when the PTON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The PTCCLR is not used in this Mode. S/W Command SET“PTON” or PTCK Pin Transition CCRA Leading Edge CCRA Trailing Edge PTON bit 0→1 PTON bit 1→0 S/W Command CLR“PTON” or CCRA Compare Match PTP Output Pin Pulse Width = CCRA Value Single Pulse Generation Rev. 1.00 55 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Counter Value PTM [1:0] = 10 ; PTIO [1:0] = 11 Counter stopped by CCRA Counter Reset when PTON returns high CCRA Pause Counter Stops by software Resume CCRP Time PTON Software Cleared by Trigger CCRA match Auto. set by PTCK pin PTCK pin Software Trigger Software Trigger Software Clear Software Trigger PTCK pin Trigger PTPAU PTPOL CCRP Int. Flag PTMPF No CCRP Interrupts generated CCRA Int. Flag PTMAF PTM O/P Pin (PTOC=1) PTM O/P Pin (PTOC=0) Pulse Width set by CCRA Output Inverts when PTPOL = 1 Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse triggered by the PTCK pin or by setting the PTON bit high 4. A PTCK pin active edge will automatically set the PTON bit high 5. In the Single Pulse Mode, PTIO [1:0] must be set to “11” and can not be changed. Rev. 1.00 56 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Capture Input Mode To select this mode bits PTM1 and PTM0 in the PTMC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the PTPI or PTCK pin, selected by the PTCAPTS bit in the PTMC1 register. The input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the PTIO1 and PTIO0 bits in the PTMC1 register. The counter is started when the PTON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the PTPI or PTCK pin the present value in the counter will be latched into the CCRA registers and a PTM interrupt generated. Irrespective of what events occur on the PTPI or PTCK pin the counter will continue to free run until the PTON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a PTM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The PTIO1 and PTIO0 bits can select the active trigger edge on the PTPI or PTCK pin to be a rising edge, falling edge or both edge types. If the PTIO1 and PTIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the PTPI or PTCK pin, however it must be noted that the counter will continue to run. As the PTPI or PTCK pin is pin shared with other functions, care must be taken if the PTM is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The PTCCLR, PTOC and PTPOL bits are not used in this Mode. Rev. 1.00 57 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Counter Value PTM [1:0] = 01 Counter cleared by CCRP Counter Stop Counter Reset CCRP Resume YY Pause XX Time PTON PTPAU Active edge Active edge Active edge PTM capture pin PTPI or PTCK CCRA Int. Flag PTMAF CCRP Int. Flag PTMPF CCRA Value PTIO [1:0] Value XX 00 – Rising edge YY 01 – Falling edge XX 10 – Both edges YY 11 – Disable Capture Capture Input Mode Note: 1. PTM [1:0]=01 and active edge set by the PTIO [1:0] bits 2. A PTM Capture input pin active edge transfers the counter value to CCRA 3. PTCCLR bit not used 4. No output function – PTOC and PTPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.00 58 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Shunt Regulator – for HT45F2020 only The HT45F2020 device includes a fully integrated shunt regulator. The device offers the advantages of a fully internal shunt regulator allowing it to be used with a wide range of external power supply voltages with the simple addition of an external resistor and capacitor. The shunt regulator is a common and simple type of regulator whose output is used as the device power supply. It is constructed of a power transistor and a voltage feedback circuit. The power transistor, whose output current is controlled by a voltage feedback circuit, is used to shunt the extra current to maintain a constant regulated voltage on VDD. This power transistor provides a current path from the device supply voltage to ground. An external resistor, RSER, should be properly selected to serially connect VDD to the external power supply. The shunt regulator may not have the expected performance if the RSER resistance is too small or too large. A capacitor is externally connected between VDD and VSS pins to stabilise the regulated voltage. Note that excessive power dissipation in form of heat due to the shunt current through the power transistor should be taken into consideration in the user applications. VUNREG ISUPPLY RSER ILOAD VDD VOUT VDD ISHUNT CBYPASS Feedback VSS VSS Shunt Regulator Block Diagram – HT45F2020 Examination of the shunt regulator block diagram will reveal that the supply current will be determined by the value of the external RSER resistor. For this reason selection of this resistor value is an important issue. It is recommended that the following criteria are used when deciding on the value of RSER. The value of RSER is calculated as follows: RSER = (VUNREG – VDD) / ISUPPLY ; Where ISUPPLY = ISHUNT(Max) ≤ which should be less than or equal to 80mA. The maximum value of the load current is calculated as follows: ILOAD(Max) = ISHUNT(Max) × (VUNREG(Min) – VOUT1(Max)) / (VUNREG(Max) − VOUT1(Min)) − ISTATIC(Measured); Where VUNREG(Max), VOUT1(Max) = Maximum specification value for VUNREG and VOUT1 respectively. And VUNREG(Min), VOUT1(Min) = Minimum specification value for VUNREG and VOUT1 respectively. Rev. 1.00 59 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Sound Effect Generator The sound effect generator is designed to be used in conjunction with the Holtek supplied Sound Effect Generator Wizard, which will allow users to easily and rapidly develop their sound generator applications. Using the Holtek supplied Sound Effect Generator Wizard development tools, sound file production along with programming and play sound evaluation is made into an easy and rapid process. Other functions include a 200ms soft chirp and fade-in features. With its highly integrated range of functions and development platform Holtek has greatly simplified the sound effect generation process and one in which the hardware only requires a minimum of external components. An evaluation board is available from Holtek to enable the easy development of user applications. This is used together with the Sound Effect Generator Wizard software and the Holtek e-Link to enable the user sound files to be programmed into the device. The evaluation board also allows the user to immediately play the files thus allowing for rapid evaluation of the required sound effects. Refer to the “Sound Effect Generator Wizard User Guide” for more detailed information. Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device only contains internal interrupts functions. The internal interrupts are generated by various internal functions such as TMs, and Time Bases. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The first is the INTC0~INTC1 registers which setup the primary interrupts, the second is the MFI register which setup the Multi-function interrupts. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an “E” for enable/ disable bit or “F” for request flag. Function Enable Bit Request Flag Global EMI — Multi-function MFE MFF Time Base PTM TBE TBF PTMPE PTMPF PTMAE PTMAF Interrupt Register Bit Naming Conventions Bit Register Name 7 6 5 4 3 2 1 0 INTC0 — — TBF — — TBE — EMI INTC1 — — — MFF — — — MFE MFI — — PTMAF PTMPF — — PTMAE PTMPE Interrupt Registers List Rev. 1.00 60 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU INTC0 Register Bit 7 6 5 4 3 2 1 0 Name — — TBF — — TBE — EMI R/W — — R/W — — R/W — R/W POR — — 0 — — 0 — 0 Bit 7~6 Unimplemented, read as “0” Bit 5 TBF: Time Base interrupt request flag 0: No request 1: Interrupt request Unimplemented, read as “0” TBE: Time Base interrupt control 0: Disable 1: Enable Unimplemented, read as “0” EMI: Global interrupt control 0: Disable 1: Enable Bit 4~3 Bit 2 Bit 1 Bit 0 INTC1 Register Bit 7 6 5 4 3 2 1 0 Name — — — MFF — — — MFE R/W — — — R/W — — — R/W POR — — — 0 — — — 0 Bit 7~5 Unimplemented, read as “0” Bit 4 MFF: Multi-function interrupt request flag 0: No request 1: Interrupt request Bit 3~1 Unimplemented, read as “0” Bit 0 MFE: Multi-function interrupt control 0: Disable 1: Enable MFI Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name — — PTMAF PTMPF — — PTMAE PTMPE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5 PTMAF: PTM Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4 PTMPF: PTM Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as “0” Bit 1 PTMAE: PTM Comparator A match interrupt control 0: Disable 1: Enable 61 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU PTMPE: PTM Comparator P match interrupt control 0: Disable 1: Enable Bit 0 Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P or Comparator A match etc., the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector, if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a “JMP” which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a “RETI”, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the Accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. Legend xxF Request Flag, no auto reset in ISR xxF Request Flag, auto reset in ISR xxE Enable Bits PTM P PTMPF PTMPE PTM A PTMAF PTMAE EMI auto disabled in ISR Interrupt Name Time Base Request Flags TBF Enable Bits TBE Master Enable EMI Vector M. Funct MFF MFE EMI 10H Priority High 08H Low Interrupts contained within Multi-Function Interrupts Interrupt Scheme Rev. 1.00 62 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Multi-function Interrupt Within the device there is a Multi-function interrupt. Unlike the other independent interrupts, the interrupt has no independent source, but rather are formed from other existing interrupt sources, namely the TM interrupt. A Multi-function interrupt request will take place when any of the Multi-function interrupt request flag MFF is set. The Multi-function interrupt flag will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related MultiFunction request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt request flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupt will not be automatically reset and must be manually reset by the application program. Time Base Interrupt The function of the Time Base Interrupt is to provide regular time signal in the form of an internal interrupt. It is controlled by the overflow signal from its internal timer. When this happens its interrupt request flag, TBF, will be set. To allow the program to branch to its respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bit, TBE, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to its respective vector location will take place. When the interrupt is serviced, the interrupt request flag, TBF, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Its clock source, fPSC, originates from the internal clock source fSYS, fSYS/4 or fSUB and then passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges. The clock source which in turn controls the Time Base interrupt period is selected using the CLKSEL [1:0] in the PSCR register respectively. fSYS fSYS/4 fSUB M U X TBON fPSC Prescaler M U X fPSC/28 ~ fPSC/215 Time Base Interrupt TB[2:0] CLKSEL[1:0] Time Base Interrupt PSCR Register Rev. 1.00 Bit 7 6 5 4 3 2 Name — — — — — — 1 0 CLKSEL1 CLKSEL0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0 CLKSEL1~CLKSEL0: Prescaler clock source selection 00: fSYS 01: fSYS/4 1x: fSUB 63 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU TBC Register Bit 7 6 5 4 3 2 1 0 Name TBON — — — — TB2 TB1 TB0 R/W R/W — — — — R/W R/W R/W POR 0 — — — — 0 0 0 Bit 7 TBON: Time Base Enable Control 0: Disable 1: Enable Bit 6~3 Unimplemented, read as “0” Bit 2~0 TB2~TB0: Time Base time-out period selection 000: 28/fPSC 001: 29/fPSC 010: 210/fPSC 011: 211/fPSC 100: 212/fPSC 101: 213/fPSC 110: 214/fPSC 111: 215/fPSC Timer Module Interrupts The PTM has two interrupts which are both contained within the Multi-function Interrupt. For the PTM there are two interrupt request flags PTMPF and PTMAF and two enable bits PTMPE and PTMAE. A PTM interrupt request will take place when any of the PTM request flags is set, a situation which occurs when a PTM comparator P or comparator A match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the respective PTM Interrupt enable bit, and the associated Multi-function interrupt enable bit, MFF, must first be set. When the interrupt is enabled, the stack is not full and a PTM comparator match situation occurs, a subroutine call to the relevant PTM Interrupt vector locations, will take place. When the PTM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFF flag will be automatically cleared. As the PTM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MFF, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. Rev. 1.00 64 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU It is recommended that programs do not use the “CALL” instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Application Circuits Direct Driving – HT45F2020 12V 150Ω/2W 200Ω/0.5W Speaker PTP PTPB VDD IO2 IO1 100μF VSS Note: The PTP and PTPB signals are the PTM complementary outputs. Rev. 1.00 65 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Single-End Driving – HT45F2020 12V 8Ω/15W Speaker 750Ω/0.25W VDD 100Ω PTP PTPB 10μF IO2 IO1 VSS 47kΩ Note: The PTP and PTPB signals are the PTM complementary outputs. Push-Pull Driving – HT45F2020 12V 220Ω 430Ω/0.25W 470Ω 220Ω 8Ω/15W Speaker 470Ω 820Ω VDD PTP 820Ω 10μF PTPB VSS IO2 IO1 47kΩ 47kΩ Note: The PTP and PTPB signals are the PTM complementary outputs. Rev. 1.00 66 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Direct Driving – HT45F2022 5V 200Ω/0.5W Speaker PTP PTPB VDD IO2 IO1 100μF VSS Note: The PTP and PTPB signals are the PTM complementary outputs. Single-End Driving – HT45F2022 5V 8Ω/15W Speaker VDD 100Ω PTP PTPB 10μF IO2 IO1 VSS 47kΩ Note: The PTP and PTPB signals are the PTM complementary outputs. Rev. 1.00 67 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Push-Pull Driving – HT45F2022 5V 220Ω 220Ω 470Ω 470Ω 8Ω/15W Speaker 820Ω VDD PTP 820Ω 10μF PTPB VSS IO2 IO1 47kΩ 47kΩ Note: The PTP and PTPB signals are the PTM complementary outputs. Rev. 1.00 68 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of several kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions such as INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.00 69 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction “RET” in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the “SET [m].i” or “CLR [m].i” instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the “HALT” instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.00 70 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 1.00 71 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Mnemonic Description Cycles Flag Affected Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Read table (specific page) to TBLH and Data Memory Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note 2Note None None None No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch Operation JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read Operation TABRD [m] TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the “CLR WDT1” and “CLR WDT2” instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both “CLR WDT1” and “CLR WDT2” instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 72 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Instruction Definition ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C ADD A,x Description Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.00 Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z 73 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CALL addr Description Operation Affected flag(s) CLR WDT1 Description Operation Affected flag(s) CLR WDT2 Description Operation Affected flag(s) CPL [m] Description Operation Affected flag(s) Rev. 1.00 Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z 74 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU CPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z DAA [m] Description Operation Operation Affected flag(s) Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z HALT Description Operation Operation Affected flag(s) Rev. 1.00 75 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z JMP addr Description Operation Affected flag(s) OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) Rev. 1.00 Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None 76 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU RET A,x Description Operation Affected flag(s) RETI Description Operation Affected flag(s) RL [m] Description Operation Affected flag(s) RLA [m] Description Operation Affected flag(s) RLC [m] Description Operation Affected flag(s) RLCA [m] Description Operation Affected flag(s) RR [m] Description Operation Affected flag(s) Rev. 1.00 Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None 77 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU RRA [m] Description Operation Affected flag(s) RRC [m] Description Operation Affected flag(s) RRCA [m] Description Operation Affected flag(s) SBC A,[m] Description Operation Affected flag(s) SBCM A,[m] Description Operation Affected flag(s) SDZ [m] Description Operation Affected flag(s) Rev. 1.00 Rotate Data Memory right with result in ACC Data in the specified Data Memory is rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None 78 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None SDZA [m] Description Operation Operation Affected flag(s) SIZA [m] Description Operation Affected flag(s) SNZ [m].i Description Operation Affected flag(s) SUB A,[m] Description Operation Affected flag(s) Rev. 1.00 Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C 79 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SUB A,x Description Operation Affected flag(s) SZ [m] Description Operation Affected flag(s) SZA [m] Description Operation Affected flag(s) SZ [m].i Description Operation Affected flag(s) Rev. 1.00 Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None 80 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU TABRD [m] Description Operation Affected flag(s) TABRDC [m] Description Operation Affected flag(s) TABRDL [m] Description Operation Affected flag(s) XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Rev. 1.00 Read table (specific page) to TBLH and Data Memory The low byte of the program code (specific page) addressed by the table pointer pair (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z 81 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.00 82 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU 8-pin SOP (150mil) Outline Dimensions Symbol A Dimensions in inch Min. Nom. Max. — 0.236 BSC — B — 0.154 BSC — C 0.012 — 0.020 C′ — 0.193 BSC — D — — 0.069 E — 0.050 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° Symbol Rev. 1.00 Dimensions in mm Min. Nom. Max. A — 6.00 BSC — B — 3.90 BSC — C 0.31 — 0.51 C′ — 4.90 BSC — D — — 1.75 E — 1.27 BSC — F 0.10 — 0.25 G 0.40 — 1.27 H 0.10 — 0.25 α 0° — 8° 83 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU 6-pin SOT23-6 Outline Dimensions H Symbol A Min. Nom. Max. — — 0.057 A1 — — 0.006 A2 0.035 0.045 0.051 b 0.012 — 0.020 C 0.003 — 0.009 D — 0.114 BSC — E — 0.063 BSC — e — 0.037 BSC — e1 — 0.075 BSC — H — 0.110 BSC — L1 — 0.024 BSC — θ 0° — 8° Symbol Rev. 1.00 Dimensions in inch Dimensions in mm Min. Nom. Max. A — — 1.45 A1 — — 0.15 A2 0.90 1.15 1.30 b 0.30 — 0.50 C 0.08 — 0.22 D — 2.90 BSC — E — 1.60 BSC — e — 0.95 BSC — e1 — 1.90 BSC — H — 2.80 BSC — L1 — 0.60 BSC — θ 0° — 8° 84 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Copyright© 2017 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com/en/. Rev. 1.00 85 April 11, 2017