Micron MT40A256M16GE-075E Temperature controlled refresh (tcr) Datasheet

4Gb: x4, x8, x16 DDR4 SDRAM
Features
DDR4 SDRAM
MT40A1G4
MT40A512M8
MT40A256M16
Options1
Features
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• Configuration
– 1 Gig x 4
– 512 Meg x 8
– 256 Meg x 16
• FBGA package (Pb-free) – x4, x8
– 78-ball (9mm x 11.5mm) – Rev. A
– 78-ball (9mm x 10.5mm) – Rev. B
• FBGA package (Pb-free) – x16
– 96-ball (9mm x 14mm) – Rev. A
– 96-ball (9mm x 14mm) – Rev. B
• Timing – cycle time
– 0.625ns @ CL = 22 (DDR4-3200)
– 0.682ns @ CL = 20 (DDR4-2933)
– 0.682ns @ CL = 21 (DDR4-2933)
– 0.750ns @ CL = 18 (DDR4-2666)
– 0.750ns @ CL = 19 (DDR4-2666)
– 0.833ns @ CL = 16 (DDR4-2400)
– 0.833ns @ CL = 17 (DDR4-2400)
– 0.937ns @ CL = 15 (DDR4-2133)
– 0.937ns @ CL = 16 (DDR4-2133)
– 1.071ns @ CL = 13 (DDR4-1866)
• Operating temperature
– Commercial (0° ≤ T C ≤ 95°C)
– Industrial (–40° ≤ T C ≤ 95°C)
– Revision
VDD = V DDQ = 1.2V ±60mV
VPP = 2.5V, –125mV/+250mV
On-die, internal, adjustable V REFDQ generation
1.2V pseudo open-drain I/O
TC maximum up to 95°C
– 64ms, 8192-cycle refresh up to 85°C
– 32ms, 8192-cycle refresh at >85°C to 95°C
16 internal banks (x4, x8): 4 groups of 4 banks each
8 internal banks (x16): 2 groups of 4 banks each
8n-bit prefetch architecture
Programmable data strobe preambles
Data strobe preamble training
Command/Address latency (CAL)
Multipurpose register READ and WRITE capability
Write and read leveling
Self refresh mode
Low-power auto self refresh (LPASR)
Temperature controlled refresh (TCR)
Fine granularity refresh
Self refresh abort
Maximum power saving
Output driver calibration
Nominal, park, and dynamic on-die termination
(ODT)
Data bus inversion (DBI) for data bus
Command/Address (CA) parity
Databus write cyclic redundancy check (CRC)
Per-DRAM addressability
Connectivity test (x16)
sPPR and hPPR capability
JEDEC JESD-79-4 compliant
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Notes:
1
Marking
1G4
512M8
256M162
HX
RH
HA
GE
-062E
-068E
-068
-075E
-075
-083E
-083
-093E
-093
-107E
None
IT
:A
:B
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
2. Not available on Rev. A.
3. Restricted and limited availability.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
4Gb: x4, x8, x16 DDR4 SDRAM
Features
Table 1: Key Timing Parameters
Speed Grade
Data Rate (MT/s)
Target tRCD-tRP-CL
-062E6
3200
22-22-22
13.75
13.75
13.75
-068E5
2933
20-20-20
13.64
13.64
13.64
-0685
2933
21-21-21
14.32
14.32
14.32
-075E4
2666
18-18-18
13.5
13.5
13.5
-0754
2666
19-19-19
14.25
14.25
14.25
-083E3
2400
16-16-16
13.32
13.32
13.32
-0833
2400
17-17-17
14.16
14.16
14.16
-093E2
2133
15-15-15
14.06
14.06
14.06
-0932
2133
16-16-16
15
15
15
-107E1
1866
13-13-13
13.92
13.92
13.92
Notes:
tRCD
(ns)
tRP
(ns)
CL (ns)
1.
2.
3.
4.
5.
Backward compatible to 1600, CL = 11.
Backward compatible to 1600, CL = 11 and 1866, CL = 13.
Backward compatible to 1600, CL = 11; 1866, CL = 13; and 2133, CL = 15.
Backward compatible to 1600, CL = 11; 1866, CL = 13; 2133, CL = 15; and 2400, CL = 17.
Backward compatible to 1600, CL = 11; 1866, CL = 13; 2133, CL = 15; 2400, CL = 17; and 2666, CL = 19. Speed
offering may have restricted availability.
6. Backward compatible to 1600, CL = 11; 1866, CL = 13; 2133, CL = 15; 2400, CL = 17; 2666, CL = 19; and 2933,
CL = 20 and CL = 21. Speed offering may have restricted availability.
Table 2: Addressing
Parameter
Number of bank groups
Bank group address
Bank count per group
Bank address in bank group
Row addressing
Column addressing
Page
size1
Notes:
1024 Meg x 4
512 Meg x 8
256 Meg x 16
4
4
2
BG[1:0]
BG[1:0]
BG0
4
4
4
BA[1:0]
BA[1:0]
BA[1:0]
64K (A[15:0])
32K (A[14:0])
32K (A[14:0])
1K (A[9:0])
1K (A[9:0])
1K (A[9:0])
1KB
2KB
512B /
1KB2
1. Page size is per bank, calculated as follows:
Page size = 2COLBITS × ORG/8, where COLBIT = the number of column address bits and ORG = the number of
DQ bits.
2. Die revision dependant.
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Features
Figure 1: Order Part Number Example
Example Part Number: MT40A1G4-083:B
Configuration
Package
Revision
Speed
{
MT40A
:
Revision
Configuration
1 Gig x 4
1G4
512 Meg x 8
512M8
256Meg x 16
256M16
:A, :B
Case Temperature
Commercial
Package
78-ball 9.0mm x 11.5mm FBGA
Mark
HX
78-ball 8.0mm x 10.5mm FBGA
RH
96-ball 9.0mm x 14.0mm FBGA
HA
96-ball 9.0mm x 14.0mm FBGA
GE
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
3
Industrial
None
IT
Speed Grade
–107E
tCK
= 1.071ns, CL = 13
–093
tCK
= 0.937ns, CL = 16
–093E
tCK
= 0.937ns, CL = 15
–083
tCK
= 0.833ns, CL = 17
–083E
tCK
= 0.833ns, CL = 16
–075
tCK
= 0.750ns, CL = 19
–075E
tCK
= 0.750ns, CL = 18
–068
tCK
= 0.682ns, CL = 21
–068E
tCK
= 0.682ns, CL = 20
–062E
tCK
= 0.625ns, CL = 22
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Features
Contents
General Notes and Description .......................................................................................................................
Description ................................................................................................................................................
Industrial Temperature ...............................................................................................................................
General Notes ............................................................................................................................................
Definitions of the Device-Pin Signal Level ...................................................................................................
Definitions of the Bus Signal Level ...............................................................................................................
Functional Block Diagrams .............................................................................................................................
Ball Assignments ............................................................................................................................................
Ball Descriptions ............................................................................................................................................
Package Dimensions .......................................................................................................................................
State Diagram ................................................................................................................................................
Functional Description ...................................................................................................................................
RESET and Initialization Procedure .................................................................................................................
Power-Up and Initialization Sequence .........................................................................................................
RESET Initialization with Stable Power Sequence .........................................................................................
Uncontrolled Power-Down Sequence ..........................................................................................................
Programming Mode Registers .........................................................................................................................
Mode Register 0 ..............................................................................................................................................
Burst Length, Type, and Order .....................................................................................................................
CAS Latency ...............................................................................................................................................
Test Mode ..................................................................................................................................................
Write Recovery(WR)/READ-to-PRECHARGE ...............................................................................................
DLL RESET .................................................................................................................................................
Mode Register 1 ..............................................................................................................................................
DLL Enable/DLL Disable ............................................................................................................................
Output Driver Impedance Control ...............................................................................................................
ODT RTT(NOM) Values ..................................................................................................................................
Additive Latency .........................................................................................................................................
Write Leveling ............................................................................................................................................
Output Disable ...........................................................................................................................................
Termination Data Strobe .............................................................................................................................
Mode Register 2 ..............................................................................................................................................
CAS WRITE Latency ....................................................................................................................................
Low-Power Auto Self Refresh .......................................................................................................................
Dynamic ODT ............................................................................................................................................
Write Cyclic Redundancy Check Data Bus ....................................................................................................
Mode Register 3 ..............................................................................................................................................
Multipurpose Register ................................................................................................................................
WRITE Command Latency When CRC/DM is Enabled .................................................................................
Fine Granularity Refresh Mode ....................................................................................................................
Temperature Sensor Status .........................................................................................................................
Per-DRAM Addressability ...........................................................................................................................
Gear-Down Mode .......................................................................................................................................
Mode Register 4 ..............................................................................................................................................
Hard Post Package Repair Mode ..................................................................................................................
Soft Post Package Repair Mode ....................................................................................................................
WRITE Preamble ........................................................................................................................................
READ Preamble ..........................................................................................................................................
READ Preamble Training ............................................................................................................................
Temperature-Controlled Refresh .................................................................................................................
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59
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Features
Command Address Latency ........................................................................................................................ 59
Internal V REF Monitor ................................................................................................................................. 59
Maximum Power Savings Mode ................................................................................................................... 60
Mode Register 5 .............................................................................................................................................. 61
Data Bus Inversion ..................................................................................................................................... 62
Data Mask .................................................................................................................................................. 63
CA Parity Persistent Error Mode .................................................................................................................. 63
ODT Input Buffer for Power-Down .............................................................................................................. 63
CA Parity Error Status ................................................................................................................................. 63
CRC Error Status ......................................................................................................................................... 63
CA Parity Latency Mode .............................................................................................................................. 63
Mode Register 6 .............................................................................................................................................. 64
tCCD_L Programming ................................................................................................................................. 65
VREFDQ Calibration Enable .......................................................................................................................... 65
VREFDQ Calibration Range ........................................................................................................................... 65
VREFDQ Calibration Value ............................................................................................................................ 65
Truth Tables ................................................................................................................................................... 66
NOP Command .............................................................................................................................................. 69
DESELECT Command .................................................................................................................................... 69
DLL-Off Mode ................................................................................................................................................ 69
DLL-On/Off Switching Procedures .................................................................................................................. 71
DLL Switch Sequence from DLL-On to DLL-Off ........................................................................................... 71
DLL-Off to DLL-On Procedure .................................................................................................................... 73
Input Clock Frequency Change ....................................................................................................................... 74
Write Leveling ................................................................................................................................................ 75
DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode ..................................... 76
Procedure Description ................................................................................................................................ 77
Write Leveling Mode Exit ............................................................................................................................ 78
Command Address Latency ............................................................................................................................ 80
Low-Power Auto Self Refresh Mode ................................................................................................................. 85
Manual Self Refresh Mode .......................................................................................................................... 85
Multipurpose Register .................................................................................................................................... 87
MPR Reads ................................................................................................................................................. 88
MPR Readout Format ................................................................................................................................. 90
MPR Readout Serial Format ........................................................................................................................ 90
MPR Readout Parallel Format ..................................................................................................................... 91
MPR Readout Staggered Format .................................................................................................................. 92
MPR READ Waveforms ............................................................................................................................... 93
MPR Writes ................................................................................................................................................ 95
MPR WRITE Waveforms .............................................................................................................................. 96
MPR REFRESH Waveforms ......................................................................................................................... 97
Gear-Down Mode .......................................................................................................................................... 100
Maximum Power-Saving Mode ....................................................................................................................... 103
Maximum Power-Saving Mode Entry .......................................................................................................... 103
Maximum Power-Saving Mode Entry in PDA .............................................................................................. 104
CKE Transition During Maximum Power-Saving Mode ................................................................................ 104
Maximum Power-Saving Mode Exit ............................................................................................................ 104
Command/Address Parity .............................................................................................................................. 106
Per-DRAM Addressability .............................................................................................................................. 114
VREFDQ Calibration ........................................................................................................................................ 117
VREFDQ Range and Levels ........................................................................................................................... 118
VREFDQ Step Size ........................................................................................................................................ 118
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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4Gb: x4, x8, x16 DDR4 SDRAM
Features
VREFDQ Increment and Decrement Timing .................................................................................................. 119
VREFDQ Target Settings ............................................................................................................................... 123
Connectivity Test Mode ................................................................................................................................. 125
Pin Mapping ............................................................................................................................................. 125
Minimum Terms Definition for Logic Equations ......................................................................................... 126
Logic Equations for a x4 Device, When Supported ....................................................................................... 126
Logic Equations for a x8 Device, When Supported ....................................................................................... 127
Logic Equations for a x16 Device ................................................................................................................ 127
CT Input Timing Requirements .................................................................................................................. 127
Post Package Repair ....................................................................................................................................... 129
Post Package Repair ................................................................................................................................... 129
Hard Post Package Repair .......................................................................................................................... 130
hPPR Row Repair - Entry ........................................................................................................................ 130
hPPR Row Repair – WRA Initiated (REF Commands Allowed) .................................................................. 130
hPPR Row Repair – WR Initiated (REF Commands NOT Allowed) ............................................................. 132
sPPR Row Repair ....................................................................................................................................... 133
hPPR/sPPR Support Identifier .................................................................................................................... 136
Excessive Row Activation ............................................................................................................................... 138
ACTIVATE Command .................................................................................................................................... 138
PRECHARGE Command ................................................................................................................................ 139
REFRESH Command ..................................................................................................................................... 140
Temperature-Controlled Refresh Mode .......................................................................................................... 142
TCR Mode – Normal Temperature Range .................................................................................................... 142
TCR Mode – Extended Temperature Range ................................................................................................. 142
Fine Granularity Refresh Mode ....................................................................................................................... 144
Mode Register and Command Truth Table .................................................................................................. 144
tREFI and tRFC Parameters ........................................................................................................................ 144
Changing Refresh Rate ............................................................................................................................... 147
Usage with TCR Mode ................................................................................................................................ 147
Self Refresh Entry and Exit ......................................................................................................................... 147
SELF REFRESH Operation .............................................................................................................................. 149
Self Refresh Abort ...................................................................................................................................... 151
Self Refresh Exit with NOP Command ......................................................................................................... 152
Power-Down Mode ........................................................................................................................................ 154
Power-Down Clarifications – Case 1 ........................................................................................................... 159
Power-Down Entry, Exit Timing with CAL ................................................................................................... 160
ODT Input Buffer Disable Mode for Power-Down ............................................................................................ 162
CRC Write Data Feature ................................................................................................................................. 164
CRC Write Data ......................................................................................................................................... 164
WRITE CRC DATA Operation ...................................................................................................................... 164
DBI_n and CRC Both Enabled .................................................................................................................... 165
DM_n and CRC Both Enabled .................................................................................................................... 165
DM_n and DBI_n Conflict During Writes with CRC Enabled ........................................................................ 165
CRC and Write Preamble Restrictions ......................................................................................................... 165
CRC Simultaneous Operation Restrictions .................................................................................................. 165
CRC Polynomial ........................................................................................................................................ 165
CRC Combinatorial Logic Equations .......................................................................................................... 166
Burst Ordering for BL8 ............................................................................................................................... 167
CRC Data Bit Mapping ............................................................................................................................... 167
CRC Enabled With BC4 .............................................................................................................................. 168
CRC with BC4 Data Bit Mapping ................................................................................................................ 168
CRC Equations for x8 Device in BC4 Mode with A2 = 0 and A2 = 1 ................................................................ 171
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Features
CRC Error Handling ................................................................................................................................... 172
CRC Write Data Flow Diagram ................................................................................................................... 174
Data Bus Inversion ........................................................................................................................................ 175
DBI During a WRITE Operation .................................................................................................................. 175
DBI During a READ Operation ................................................................................................................... 176
Data Mask ..................................................................................................................................................... 177
Programmable Preamble Modes and DQS Postambles .................................................................................... 179
WRITE Preamble Mode .............................................................................................................................. 179
READ Preamble Mode ............................................................................................................................... 182
READ Preamble Training ........................................................................................................................... 182
WRITE Postamble ...................................................................................................................................... 183
READ Postamble ....................................................................................................................................... 183
Bank Access Operation .................................................................................................................................. 185
READ Operation ............................................................................................................................................ 189
Read Timing Definitions ............................................................................................................................ 189
Read Timing – Clock-to-Data Strobe Relationship ....................................................................................... 190
Read Timing – Data Strobe-to-Data Relationship ........................................................................................ 192
tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) Calculations ............................................................................ 193
tRPRE Calculation ..................................................................................................................................... 194
tRPST Calculation ...................................................................................................................................... 195
READ Burst Operation ............................................................................................................................... 196
READ Operation Followed by Another READ Operation .............................................................................. 198
READ Operation Followed by WRITE Operation .......................................................................................... 203
READ Operation Followed by PRECHARGE Operation ................................................................................ 209
READ Operation with Read Data Bus Inversion (DBI) .................................................................................. 212
READ Operation with Command/Address Parity (CA Parity) ........................................................................ 213
READ Followed by WRITE with CRC Enabled .............................................................................................. 215
READ Operation with Command/Address Latency (CAL) Enabled ............................................................... 216
WRITE Operation .......................................................................................................................................... 218
Write Timing Definitions ........................................................................................................................... 218
Write Timing – Clock-to-Data Strobe Relationship ...................................................................................... 218
tWPRE Calculation .................................................................................................................................... 220
tWPST Calculation ..................................................................................................................................... 221
Write Timing – Data Strobe-to-Data Relationship ........................................................................................ 221
WRITE Burst Operation ............................................................................................................................. 225
WRITE Operation Followed by Another WRITE Operation ........................................................................... 227
WRITE Operation Followed by READ Operation .......................................................................................... 233
WRITE Operation Followed by PRECHARGE Operation ............................................................................... 237
WRITE Operation with WRITE DBI Enabled ................................................................................................ 240
WRITE Operation with CA Parity Enabled ................................................................................................... 242
WRITE Operation with Write CRC Enabled ................................................................................................. 243
Write Timing Violations ................................................................................................................................. 248
Motivation ................................................................................................................................................ 248
Data Setup and Hold Violations ................................................................................................................. 248
Strobe-to-Strobe and Strobe-to-Clock Violations ........................................................................................ 248
ZQ CALIBRATION Commands ....................................................................................................................... 249
On-Die Termination ...................................................................................................................................... 251
ODT Mode Register and ODT State Table ........................................................................................................ 251
ODT Read Disable State Table .................................................................................................................... 252
Synchronous ODT Mode ................................................................................................................................ 253
ODT Latency and Posted ODT .................................................................................................................... 253
Timing Parameters .................................................................................................................................... 253
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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4Gb: x4, x8, x16 DDR4 SDRAM
Features
ODT During Reads .................................................................................................................................... 255
Dynamic ODT ............................................................................................................................................... 256
Functional Description .............................................................................................................................. 256
Asynchronous ODT Mode .............................................................................................................................. 259
Electrical Specifications ................................................................................................................................. 260
Absolute Ratings ........................................................................................................................................ 260
DRAM Component Operating Temperature Range ...................................................................................... 260
Electrical Characteristics – AC and DC Operating Conditions .......................................................................... 261
Supply Operating Conditions ..................................................................................................................... 261
Leakages ................................................................................................................................................... 262
VREFCA Supply ............................................................................................................................................ 262
VREFDQ Supply and Calibration Ranges ....................................................................................................... 263
VREFDQ Ranges ........................................................................................................................................... 264
Electrical Characteristics – AC and DC Single-Ended Input Measurement Levels .............................................. 265
RESET_n Input Levels ................................................................................................................................ 265
Command/Address Input Levels ................................................................................................................ 265
Command, Control, and Address Setup, Hold, and Derating ........................................................................ 267
Data Receiver Input Requirements ............................................................................................................. 269
Connectivity Test (CT) Mode Input Levels .................................................................................................. 273
Electrical Characteristics – AC and DC Differential Input Measurement Levels ................................................. 277
Differential Inputs ..................................................................................................................................... 277
Single-Ended Requirements for CK Differential Signals ............................................................................... 278
Slew Rate Definitions for CK Differential Input Signals ................................................................................ 279
CK Differential Input Cross Point Voltage .................................................................................................... 280
DQS Differential Input Signal Definition and Swing Requirements .............................................................. 281
DQS Differential Input Cross Point Voltage ................................................................................................. 283
Slew Rate Definitions for DQS Differential Input Signals .............................................................................. 284
Electrical Characteristics – Overshoot and Undershoot Specifications ............................................................. 286
Address, Command, and Control Overshoot and Undershoot Specifications ................................................ 286
Clock Overshoot and Undershoot Specifications ......................................................................................... 287
Data, Strobe, and Mask Overshoot and Undershoot Specifications .............................................................. 288
Electrical Characteristics – AC and DC Output Measurement Levels ................................................................ 288
Single-Ended Outputs ............................................................................................................................... 288
Differential Outputs .................................................................................................................................. 290
Reference Load for AC Timing and Output Slew Rate ................................................................................... 291
Connectivity Test Mode Output Levels ........................................................................................................ 292
Electrical Characteristics – AC and DC Output Driver Characteristics ............................................................... 293
Connectivity Test Mode Output Driver Electrical Characteristics ................................................................. 293
Output Driver Electrical Characteristics ..................................................................................................... 295
Output Driver Temperature and Voltage Sensitivity ..................................................................................... 298
Alert Driver ............................................................................................................................................... 298
Electrical Characteristics – On-Die Termination Characteristics ...................................................................... 299
ODT Levels and I-V Characteristics ............................................................................................................ 299
ODT Temperature and Voltage Sensitivity ................................................................................................... 301
ODT Timing Definitions ............................................................................................................................ 301
DRAM Package Electrical Specifications ......................................................................................................... 305
Thermal Characteristics ................................................................................................................................. 309
Current Specifications – Measurement Conditions .......................................................................................... 310
IDD, IPP, and IDDQ Measurement Conditions ................................................................................................ 310
IDD Definitions .......................................................................................................................................... 312
Current Specifications – Patterns and Test Conditions ..................................................................................... 316
Current Test Definitions and Patterns ......................................................................................................... 316
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Features
IDD Specifications ...................................................................................................................................... 325
Current Specifications – Limits ....................................................................................................................... 326
Speed Bin Tables ........................................................................................................................................... 330
Refresh Parameters By Device Density ............................................................................................................ 338
Electrical Characteristics and AC Timing Parameters ...................................................................................... 339
Electrical Characteristics and AC Timing Parameters: 2666 Through 3200 ........................................................ 351
Converting Time-Based Specifications to Clock-Based Requirements .............................................................. 363
Options Tables .............................................................................................................................................. 364
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Features
List of Figures
Figure 1: Order Part Number Example .............................................................................................................. 3
Figure 2: 1 Gig x 4 Functional Block Diagram .................................................................................................. 21
Figure 3: 512 Meg x 8 Functional Block Diagram ............................................................................................. 21
Figure 4: 256 Meg x 16 Functional Block Diagram ........................................................................................... 22
Figure 5: 78-Ball x4, x8 Ball Assignments ........................................................................................................ 23
Figure 6: 96-Ball x16 Ball Assignments ............................................................................................................ 24
Figure 7: 78-Ball FBGA – x4, x8 "HX" .............................................................................................................. 28
Figure 8: 78-Ball FBGA – x4, x8 "RH" .............................................................................................................. 29
Figure 9: 96-Ball FBGA – x16 "HA" .................................................................................................................. 30
Figure 10: 96-Ball FBGA – x16 "GE" ................................................................................................................ 31
Figure 11: Simplified State Diagram ............................................................................................................... 32
Figure 12: RESET and Initialization Sequence at Power-On Ramping ............................................................... 38
Figure 13: RESET Procedure at Power Stable Condition ................................................................................... 39
Figure 14: tMRD Timing ................................................................................................................................ 41
Figure 15: tMOD Timing ................................................................................................................................ 41
Figure 16: DLL-Off Mode Read Timing Operation ........................................................................................... 70
Figure 17: DLL Switch Sequence from DLL-On to DLL-Off .............................................................................. 72
Figure 18: DLL Switch Sequence from DLL-Off to DLL-On .............................................................................. 73
Figure 19: Write Leveling Concept, Example 1 ................................................................................................ 75
Figure 20: Write Leveling Concept, Example 2 ................................................................................................ 76
Figure 21: Write Leveling Sequence (DQS Capturing CK LOW at T1 and CK HIGH at T2) .................................. 78
Figure 22: Write Leveling Exit ......................................................................................................................... 79
Figure 23: CAL Timing Definition ................................................................................................................... 80
Figure 24: CAL Timing Example (Consecutive CS_n = LOW) ............................................................................ 80
Figure 25: CAL Enable Timing – tMOD_CAL ................................................................................................... 81
Figure 26: tMOD_CAL, MRS to Valid Command Timing with CAL Enabled ....................................................... 81
Figure 27: CAL Enabling MRS to Next MRS Command, tMRD_CAL .................................................................. 82
Figure 28: tMRD_CAL, Mode Register Cycle Time With CAL Enabled ............................................................... 82
Figure 29: Consecutive READ BL8, CAL3, 1tCK Preamble, Different Bank Group ............................................... 83
Figure 30: Consecutive READ BL8, CAL4, 1tCK Preamble, Different Bank Group ............................................... 83
Figure 31: Auto Self Refresh Ranges ................................................................................................................ 86
Figure 32: MPR Block Diagram ....................................................................................................................... 87
Figure 33: MPR READ Timing ........................................................................................................................ 93
Figure 34: MPR Back-to-Back READ Timing ................................................................................................... 94
Figure 35: MPR READ-to-WRITE Timing ........................................................................................................ 95
Figure 36: MPR WRITE and WRITE-to-READ Timing ...................................................................................... 96
Figure 37: MPR Back-to-Back WRITE Timing .................................................................................................. 97
Figure 38: REFRESH Timing ........................................................................................................................... 97
Figure 39: READ-to-REFRESH Timing ............................................................................................................ 98
Figure 40: WRITE-to-REFRESH Timing .......................................................................................................... 98
Figure 41: Clock Mode Change from 1/2 Rate to 1/4 Rate (Initialization) ......................................................... 101
Figure 42: Clock Mode Change After Exiting Self Refresh ................................................................................ 101
Figure 43: Comparison Between Gear-Down Disable and Gear-Down Enable ................................................. 102
Figure 44: Maximum Power-Saving Mode Entry ............................................................................................. 103
Figure 45: Maximum Power-Saving Mode Entry with PDA .............................................................................. 104
Figure 46: Maintaining Maximum Power-Saving Mode with CKE Transition ................................................... 104
Figure 47: Maximum Power-Saving Mode Exit ............................................................................................... 105
Figure 48: Command/Address Parity Operation ............................................................................................. 106
Figure 49: Command/Address Parity During Normal Operation ..................................................................... 108
Figure 50: Persistent CA Parity Error Checking Operation ............................................................................... 109
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Features
Figure 51: CA Parity Error Checking – SRE Attempt ........................................................................................ 109
Figure 52: CA Parity Error Checking – SRX Attempt ........................................................................................ 110
Figure 53: CA Parity Error Checking – PDE/PDX ............................................................................................ 110
Figure 54: Parity Entry Timing Example – tMRD_PAR ..................................................................................... 111
Figure 55: Parity Entry Timing Example – tMOD_PAR ..................................................................................... 111
Figure 56: Parity Exit Timing Example – tMRD_PAR ....................................................................................... 111
Figure 57: Parity Exit Timing Example – tMOD_PAR ....................................................................................... 112
Figure 58: CA Parity Flow Diagram ................................................................................................................ 113
Figure 59: PDA Operation Enabled, BL8 ........................................................................................................ 115
Figure 60: PDA Operation Enabled, BC4 ........................................................................................................ 115
Figure 61: MRS PDA Exit ............................................................................................................................... 116
Figure 62: V REFDQ Voltage Range ................................................................................................................... 117
Figure 63: Example of V REF Set Tolerance and Step Size .................................................................................. 119
Figure 64: V REFDQ Timing Diagram for V REF,time Parameter .............................................................................. 120
Figure 65: V REFDQ Training Mode Entry and Exit Timing Diagram ................................................................... 121
Figure 66: V REF Step: Single Step Size Increment Case .................................................................................... 122
Figure 67: V REF Step: Single Step Size Decrement Case ................................................................................... 122
Figure 68: V REF Full Step: From V REF,min to V REF,maxCase .................................................................................. 123
Figure 69: V REF Full Step: From V REF,max to V REF,minCase .................................................................................. 123
Figure 70: V REFDQ Equivalent Circuit ............................................................................................................. 124
Figure 71: Connectivity Test Mode Entry ....................................................................................................... 128
Figure 72: hPPR WRA – Entry ........................................................................................................................ 131
Figure 73: hPPR WRA – Repair and Exit ......................................................................................................... 132
Figure 74: hPPR WR – Entry .......................................................................................................................... 133
Figure 75: hPPR WR – Repair and Exit ............................................................................................................ 133
Figure 76: sPPR – Entry ................................................................................................................................. 136
Figure 77: sPPR – Repair, and Exit ................................................................................................................. 136
Figure 78: tRRD Timing ................................................................................................................................ 139
Figure 79: tFAW Timing ................................................................................................................................. 139
Figure 80: REFRESH Command Timing ......................................................................................................... 141
Figure 81: Postponing REFRESH Commands (Example) ................................................................................. 141
Figure 82: Pulling In REFRESH Commands (Example) ................................................................................... 141
Figure 83: TCR Mode Example 1 ..................................................................................................................... 143
Figure 84: 4Gb with Fine Granularity Refresh Mode Example ......................................................................... 146
Figure 85: OTF REFRESH Command Timing ................................................................................................. 147
Figure 86: Self Refresh Entry/Exit Timing ...................................................................................................... 150
Figure 87: Self Refresh Entry/Exit Timing with CAL Mode ............................................................................... 151
Figure 88: Self Refresh Abort ......................................................................................................................... 152
Figure 89: Self Refresh Exit with NOP Command ............................................................................................ 153
Figure 90: Active Power-Down Entry and Exit ................................................................................................ 155
Figure 91: Power-Down Entry After Read and Read with Auto Precharge ......................................................... 156
Figure 92: Power-Down Entry After Write and Write with Auto Precharge ........................................................ 156
Figure 93: Power-Down Entry After Write ...................................................................................................... 157
Figure 94: Precharge Power-Down Entry and Exit .......................................................................................... 157
Figure 95: REFRESH Command to Power-Down Entry ................................................................................... 158
Figure 96: Active Command to Power-Down Entry ......................................................................................... 158
Figure 97: PRECHARGE/PRECHARGE ALL Command to Power-Down Entry .................................................. 159
Figure 98: MRS Command to Power-Down Entry ........................................................................................... 159
Figure 99: Power-Down Entry/Exit Clarifications – Case 1 .............................................................................. 160
Figure 100: Active Power-Down Entry and Exit Timing with CAL .................................................................... 160
Figure 101: REFRESH Command to Power-Down Entry with CAL ................................................................... 161
Figure 102: ODT Power-Down Entry with ODT Buffer Disable Mode .............................................................. 162
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Features
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ODT Power-Down Exit with ODT Buffer Disable Mode ................................................................. 163
CRC Write Data Operation .......................................................................................................... 164
CRC Error Reporting ................................................................................................................... 173
CA Parity Flow Diagram .............................................................................................................. 174
1tCK vs. 2tCK WRITE Preamble Mode ........................................................................................... 179
1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 4 ............................................................................ 180
1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 5 ............................................................................ 181
1tCK vs. 2 tCK WRITE Preamble Mode, tCCD = 6 ........................................................................... 181
1tCK vs. 2tCK READ Preamble Mode ............................................................................................ 182
READ Preamble Training ............................................................................................................. 183
WRITE Postamble ....................................................................................................................... 183
READ Postamble ........................................................................................................................ 184
Bank Group x4/x8 Block Diagram ................................................................................................ 185
READ Burst tCCD_S and tCCD_L Examples .................................................................................. 186
Write Burst tCCD_S and tCCD_L Examples ................................................................................... 186
tRRD Timing ............................................................................................................................... 187
tWTR_S Timing (WRITE-to-READ, Different Bank Group, CRC and DM Disabled) ......................... 187
tWTR_L Timing (WRITE-to-READ, Same Bank Group, CRC and DM Disabled) .............................. 188
Read Timing Definition ............................................................................................................... 190
Clock-to-Data Strobe Relationship .............................................................................................. 191
Data Strobe-to-Data Relationship ................................................................................................ 192
tLZ and tHZ Method for Calculating Transitions and Endpoints .................................................... 193
tRPRE Method for Calculating Transitions and Endpoints ............................................................. 194
tRPST Method for Calculating Transitions and Endpoints ............................................................. 195
READ Burst Operation, RL = 11 (AL = 0, CL = 11, BL8) ................................................................... 196
READ Burst Operation, RL = 21 (AL = 10, CL = 11, BL8) ................................................................. 197
Consecutive READ (BL8) with 1tCK Preamble in Different Bank Group .......................................... 198
Consecutive READ (BL8) with 2tCK Preamble in Different Bank Group .......................................... 198
Nonconsecutive READ (BL8) with 1tCK Preamble in Same or Different Bank Group ....................... 199
Nonconsecutive READ (BL8) with 2tCK Preamble in Same or Different Bank Group ....................... 199
READ (BC4) to READ (BC4) with 1tCK Preamble in Different Bank Group ...................................... 200
READ (BC4) to READ (BC4) with 2tCK Preamble in Different Bank Group ...................................... 200
READ (BL8) to READ (BC4) OTF with 1tCK Preamble in Different Bank Group ............................... 201
READ (BL8) to READ (BC4) OTF with 2tCK Preamble in Different Bank Group ............................... 201
READ (BC4) to READ (BL8) OTF with 1tCK Preamble in Different Bank Group ............................... 202
READ (BC4) to READ (BL8) OTF with 2tCK Preamble in Different Bank Group ............................... 202
READ (BL8) to WRITE (BL8) with 1 tCK Preamble in Same or Different Bank Group ........................ 203
READ (BL8) to WRITE (BL8) with 2 tCK Preamble in Same or Different Bank Group ........................ 203
READ (BC4) OTF to WRITE (BC4) OTF with 1 tCK Preamble in Same or Different Bank Group ......... 204
READ (BC4) OTF to WRITE (BC4) OTF with 2 tCK Preamble in Same or Different Bank Group ......... 205
READ (BC4) Fixed to WRITE (BC4) Fixed with 1 tCK Preamble in Same or Different Bank Group ..... 205
READ (BC4) Fixed to WRITE (BC4) Fixed with 2 tCK Preamble in Same or Different Bank Group ..... 206
READ (BC4) to WRITE (BL8) OTF with 1 tCK Preamble in Same or Different Bank Group ................ 207
READ (BC4) to WRITE (BL8) OTF with 2 tCK Preamble in Same or Different Bank Group ................ 207
READ (BL8) to WRITE (BC4) OTF with 1 tCK Preamble in Same or Different Bank Group ................ 208
READ (BL8) to WRITE (BC4) OTF with 2 tCK Preamble in Same or Different Bank Group ................ 208
READ to PRECHARGE with 1tCK Preamble .................................................................................. 209
READ to PRECHARGE with 2tCK Preamble .................................................................................. 210
READ to PRECHARGE with Additive Latency and 1tCK Preamble .................................................. 210
READ with Auto Precharge and 1tCK Preamble ............................................................................ 211
READ with Auto Precharge, Additive Latency, and 1tCK Preamble ................................................. 212
Consecutive READ (BL8) with 1tCK Preamble and DBI in Different Bank Group ............................ 212
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
12
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Features
Figure 155: Consecutive READ (BL8) with 1tCK Preamble and CA Parity in Different Bank Group .................... 213
Figure 156: READ (BL8) to WRITE (BL8) with 1 tCK Preamble and CA Parity in Same or Different Bank Group ... 214
Figure 157: READ (BL8) to WRITE (BL8 or BC4: OTF) with 1 tCK Preamble and Write CRC in Same or Different
Bank Group ............................................................................................................................................... 215
Figure 158: READ (BC4: Fixed) to WRITE (BC4: Fixed) with 1 tCK Preamble and Write CRC in Same or Different
Bank Group ............................................................................................................................................... 216
Figure 159: Consecutive READ (BL8) with CAL (3tCK) and 1tCK Preamble in Different Bank Group .................. 216
Figure 160: Consecutive READ (BL8) with CAL (4tCK) and 1tCK Preamble in Different Bank Group .................. 217
Figure 161: Write Timing Definition .............................................................................................................. 219
Figure 162: tWPRE Method for Calculating Transitions and Endpoints ............................................................ 220
Figure 163: tWPST Method for Calculating Transitions and Endpoints ............................................................ 221
Figure 164: Rx Compliance Mask .................................................................................................................. 222
Figure 165: V CENT_DQ VREFDQ Voltage Variation .............................................................................................. 222
Figure 166: Rx Mask DQ-to-DQS Timings ...................................................................................................... 223
Figure 167: Rx Mask DQ-to-DQS DRAM-Based Timings ................................................................................. 224
Figure 168: Example of Data Input Requirements Without Training ................................................................ 225
Figure 169: WRITE Burst Operation, WL = 9 (AL = 0, CWL = 9, BL8) ................................................................. 226
Figure 170: WRITE Burst Operation, WL = 19 (AL = 10, CWL = 9, BL8) ............................................................. 227
Figure 171: Consecutive WRITE (BL8) with 1 tCK Preamble in Different Bank Group ........................................ 227
Figure 172: Consecutive WRITE (BL8) with 2 tCK Preamble in Different Bank Group ........................................ 228
Figure 173: Nonconsecutive WRITE (BL8) with 1 tCK Preamble in Same or Different Bank Group ..................... 229
Figure 174: Nonconsecutive WRITE (BL8) with 2 tCK Preamble in Same or Different Bank Group ..................... 229
Figure 175: WRITE (BC4) OTF to WRITE (BC4) OTF with 1 tCK Preamble in Different Bank Group .................... 230
Figure 176: WRITE (BC4) OTF to WRITE (BC4) OTF with 2 tCK Preamble in Different Bank Group .................... 231
Figure 177: WRITE (BC4) Fixed to WRITE (BC4) Fixed with 1 tCK Preamble in Different Bank Group ................. 231
Figure 178: WRITE (BL8) to WRITE (BC4) OTF with 1 tCK Preamble in Different Bank Group ............................ 232
Figure 179: WRITE (BC4) OTF to WRITE (BL8) with 1 tCK Preamble in Different Bank Group ............................ 233
Figure 180: WRITE (BL8) to READ (BL8) with 1 tCK Preamble in Different Bank Group ..................................... 233
Figure 181: WRITE (BL8) to READ (BL8) with 1 tCK Preamble in Same Bank Group .......................................... 234
Figure 182: WRITE (BC4) OTF to READ (BC4) OTF with 1 tCK Preamble in Different Bank Group ...................... 235
Figure 183: WRITE (BC4) OTF to READ (BC4) OTF with 1 tCK Preamble in Same Bank Group ........................... 235
Figure 184: WRITE (BC4) Fixed to READ (BC4) Fixed with 1 tCK Preamble in Different Bank Group ................. 236
Figure 185: WRITE (BC4) Fixed to READ (BC4) Fixed with 1 tCK Preamble in Same Bank Group ....................... 236
Figure 186: WRITE (BL8/BC4-OTF) to PRECHARGE with 1 tCK Preamble ........................................................ 237
Figure 187: WRITE (BC4-Fixed) to PRECHARGE with 1 tCK Preamble .............................................................. 238
Figure 188: WRITE (BL8/BC4-OTF) to Auto PRECHARGE with 1 tCK Preamble ................................................ 238
Figure 189: WRITE (BC4-Fixed) to Auto PRECHARGE with 1 tCK Preamble ...................................................... 239
Figure 190: WRITE (BL8/BC4-OTF) with 1 tCK Preamble and DBI ................................................................... 240
Figure 191: WRITE (BC4-Fixed) with 1 tCK Preamble and DBI ......................................................................... 241
Figure 192: Consecutive Write (BL8) with 1 tCK Preamble and CA Parity in Different Bank Group ..................... 242
Figure 193: Consecutive WRITE (BL8/BC4-OTF) with 1 tCK Preamble and Write CRC in Same or Different Bank
Group ....................................................................................................................................................... 243
Figure 194: Consecutive WRITE (BC4-Fixed) with 1 tCK Preamble and Write CRC in Same or Different Bank
Group ....................................................................................................................................................... 244
Figure 195: Nonconsecutive WRITE (BL8/BC4-OTF) with 1 tCK Preamble and Write CRC in Same or Different
Bank Group ............................................................................................................................................... 245
Figure 196: Nonconsecutive WRITE (BL8/BC4-OTF) with 2 tCK Preamble and Write CRC in Same or Different
Bank Group ............................................................................................................................................... 246
Figure 197: WRITE (BL8/BC4-OTF/Fixed) with 1 tCK Preamble and Write CRC in Same or Different Bank Group ...
247
Figure 198: ZQ Calibration Timing ................................................................................................................ 250
Figure 199: Functional Representation of ODT .............................................................................................. 251
Figure 200: Synchronous ODT Timing with BL8 ............................................................................................. 254
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
13
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Features
Figure 201:
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Figure 243:
Synchronous ODT with BC4 ........................................................................................................ 254
ODT During Reads ...................................................................................................................... 255
Dynamic ODT (1t CK Preamble; CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled) .......................... 257
Dynamic ODT Overlapped with RTT(NOM) (CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled) .......... 258
Asynchronous ODT Timings with DLL Off ................................................................................... 259
V REFDQ Voltage Range .................................................................................................................. 262
RESET_n Input Slew Rate Definition ............................................................................................ 265
Single-Ended Input Slew Rate Definition ..................................................................................... 267
DQ Slew Rate Definitions ............................................................................................................ 270
Rx Mask Relative to tDS/tDH ....................................................................................................... 272
Rx Mask Without Write Training .................................................................................................. 273
TEN Input Slew Rate Definition ................................................................................................... 274
CT Type-A Input Slew Rate Definition .......................................................................................... 274
CT Type-B Input Slew Rate Definition .......................................................................................... 275
CT Type-C Input Slew Rate Definition .......................................................................................... 276
CT Type-D Input Slew Rate Definition ......................................................................................... 276
Differential AC Swing and “Time Exceeding AC-Level” tDVAC ....................................................... 277
Single-Ended Requirements for CK .............................................................................................. 279
Differential Input Slew Rate Definition for CK_t, CK_c .................................................................. 280
V IX(CK) Definition ........................................................................................................................ 280
Differential Input Signal Definition for DQS_t, DQS_c .................................................................. 281
DQS_t, DQS_c Input Peak Voltage Calculation and Range of Exempt non-Monotonic Signaling ..... 282
V IXDQS Definition ........................................................................................................................ 283
Differential Input Slew Rate and Input Level Definition for DQS_t, DQS_c ..................................... 284
ADDR, CMD, CNTL Overshoot and Undershoot Definition ........................................................... 286
CK Overshoot and Undershoot Definition .................................................................................... 287
Data, Strobe, and Mask Overshoot and Undershoot Definition ..................................................... 288
Single-ended Output Slew Rate Definition ................................................................................... 289
Differential Output Slew Rate Definition ...................................................................................... 291
Reference Load For AC Timing and Output Slew Rate ................................................................... 292
Connectivity Test Mode Reference Test Load ................................................................................ 292
Connectivity Test Mode Output Slew Rate Definition .................................................................... 293
Output Driver During Connectivity Test Mode ............................................................................. 294
Output Driver: Definition of Voltages and Currents ...................................................................... 295
Alert Driver ................................................................................................................................ 299
ODT Definition of Voltages and Currents ..................................................................................... 300
ODT Timing Reference Load ....................................................................................................... 301
tADC Definition with Direct ODT Control .................................................................................... 303
tADC Definition with Dynamic ODT Control ................................................................................ 303
tAOFAS and tAONAS Definitions .................................................................................................. 304
Thermal Measurement Point ....................................................................................................... 310
Measurement Setup and Test Load for I DDx, IDDPx, and IDDQx ........................................................ 311
Correlation: Simulated Channel I/O Power to Actual Channel I/O Power ....................................... 312
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
14
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Features
List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 2
Table 2: Addressing ......................................................................................................................................... 2
Table 3: Ball Descriptions .............................................................................................................................. 25
Table 4: State Diagram Command Definitions ................................................................................................ 33
Table 5: Supply Power-up Slew Rate ............................................................................................................... 35
Table 6: Address Pin Mapping ........................................................................................................................ 43
Table 7: MR0 Register Definition .................................................................................................................... 43
Table 8: Burst Type and Burst Order ............................................................................................................... 45
Table 9: Address Pin Mapping ........................................................................................................................ 47
Table 10: MR1 Register Definition .................................................................................................................. 47
Table 11: Additive Latency (AL) Settings ......................................................................................................... 49
Table 12: TDQS Function Matrix .................................................................................................................... 50
Table 13: Address Pin Mapping ...................................................................................................................... 51
Table 14: MR2 Register Definition .................................................................................................................. 51
Table 15: Address Pin Mapping ...................................................................................................................... 54
Table 16: MR3 Register Definition .................................................................................................................. 54
Table 17: Address Pin Mapping ...................................................................................................................... 57
Table 18: MR4 Register Definition .................................................................................................................. 57
Table 19: Address Pin Mapping ...................................................................................................................... 61
Table 20: MR5 Register Definition .................................................................................................................. 61
Table 21: Address Pin Mapping ...................................................................................................................... 64
Table 22: MR6 Register Definition .................................................................................................................. 64
Table 23: Truth Table – Command .................................................................................................................. 66
Table 24: Truth Table – CKE ........................................................................................................................... 68
Table 25: MR Settings for Leveling Procedures ................................................................................................ 76
Table 26: DRAM TERMINATION Function in Leveling Mode ........................................................................... 76
Table 27: Auto Self Refresh Mode ................................................................................................................... 85
Table 28: MR3 Setting for the MPR Access Mode ............................................................................................. 87
Table 29: DRAM Address to MPR UI Translation ............................................................................................. 87
Table 30: MPR Page and MPRx Definitions ..................................................................................................... 88
Table 31: MPR Readout Serial Format ............................................................................................................. 90
Table 32: MPR Readout – Parallel Format ....................................................................................................... 91
Table 33: MPR Readout Staggered Format, x4 ................................................................................................. 92
Table 34: MPR Readout Staggered Format, x4 – Consecutive READs ................................................................ 92
Table 35: MPR Readout Staggered Format, x8 and x16 ..................................................................................... 93
Table 36: Mode Register Setting for CA Parity ................................................................................................. 108
Table 37: V REFDQ Range and Levels ................................................................................................................ 118
Table 38: V REFDQ Settings (VDDQ = 1.2V) ......................................................................................................... 124
Table 39: Connectivity Mode Pin Description and Switching Levels ................................................................ 126
Table 40: PPR MR0 Guard Key Settings .......................................................................................................... 130
Table 41: DDR4 hPPR Timing Parameters DDR4-1600 through DDR4-3200 ..................................................... 133
Table 42: sPPR Associated Rows .................................................................................................................... 134
Table 43: PPR MR0 Guard Key Settings .......................................................................................................... 135
Table 44: DDR4 sPPR Timing Parameters DDR4-1600 through DDR4-3200 ..................................................... 136
Table 45: DDR4 Repair Mode Support Identifier ............................................................................................ 136
Table 46: MAC Encoding of MPR Page 3 MPR3 ............................................................................................... 138
Table 47: Normal tREFI Refresh (TCR Disabled) ............................................................................................. 142
Table 48: Normal tREFI Refresh (TCR Enabled) .............................................................................................. 143
Table 49: MRS Definition .............................................................................................................................. 144
Table 50: REFRESH Command Truth Table .................................................................................................... 144
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
15
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Features
Table 51: tREFI and tRFC Parameters ............................................................................................................. 145
Table 52: Power-Down Entry Definitions ....................................................................................................... 154
Table 53: CRC Error Detection Coverage ........................................................................................................ 165
Table 54: CRC Data Mapping for x4 Devices, BL8 ........................................................................................... 167
Table 55: CRC Data Mapping for x8 Devices, BL8 ........................................................................................... 167
Table 56: CRC Data Mapping for x16 Devices, BL8 ......................................................................................... 168
Table 57: CRC Data Mapping for x4 Devices, BC4 ........................................................................................... 168
Table 58: CRC Data Mapping for x8 Devices, BC4 ........................................................................................... 169
Table 59: CRC Data Mapping for x16 Devices, BC4 ......................................................................................... 170
Table 60: DBI vs. DM vs. TDQS Function Matrix ............................................................................................. 175
Table 61: DBI Write, DQ Frame Format (x8) ................................................................................................... 175
Table 62: DBI Write, DQ Frame Format (x16) ................................................................................................. 175
Table 63: DBI Read, DQ Frame Format (x8) .................................................................................................... 176
Table 64: DBI Read, DQ Frame Format (x16) .................................................................................................. 176
Table 65: DM vs. TDQS vs. DBI Function Matrix ............................................................................................. 177
Table 66: Data Mask, DQ Frame Format (x8) .................................................................................................. 177
Table 67: Data Mask, DQ Frame Format (x16) ................................................................................................ 177
Table 68: CWL Selection ............................................................................................................................... 180
Table 69: DDR4 Bank Group Timing Examples .............................................................................................. 185
Table 70: Read to Write and Write to Read Command Intervals ....................................................................... 190
Table 71: Termination State Table ................................................................................................................. 252
Table 72: Read Termination Disable Window ................................................................................................. 252
Table 73: ODT Latency at DDR4-1600/-1866/-2133/-2400/-2666/-3200 .......................................................... 253
Table 74: Dynamic ODT Latencies and Timing (1 tCK Preamble Mode and CRC Disabled) ................................ 256
Table 75: Dynamic ODT Latencies and Timing with Preamble Mode and CRC Mode Matrix ............................ 257
Table 76: Absolute Maximum Ratings ............................................................................................................ 260
Table 77: Temperature Range ........................................................................................................................ 260
Table 78: Recommended Supply Operating Conditions .................................................................................. 261
Table 79: V DD Slew Rate ................................................................................................................................ 261
Table 80: Leakages ....................................................................................................................................... 262
Table 81: V REFDQ Specification ...................................................................................................................... 263
Table 82: V REFDQ Range and Levels ................................................................................................................ 264
Table 83: RESET_n Input Levels (CMOS) ....................................................................................................... 265
Table 84: Command and Address Input Levels: DDR4-1600 Through DDR4-2400 ........................................... 265
Table 85: Command and Address Input Levels: DDR4-2666 ............................................................................ 266
Table 86: Command and Address Input Levels: DDR4-2933 and DDR4-3200 ................................................... 266
Table 87: Single-Ended Input Slew Rates ....................................................................................................... 267
Table 88: Command and Address Setup and Hold Values Referenced – AC/DC-Based ..................................... 268
Table 89: Derating Values for tIS/tIH – AC100DC75-Based .............................................................................. 268
Table 90: Derating Values for tIS/tIH – AC90/DC65-Based .............................................................................. 269
Table 91: DQ Input Receiver Specifications .................................................................................................... 270
Table 92: Rx Mask and tDS/tDH without Write Training .................................................................................. 273
Table 93: TEN Input Levels (CMOS) .............................................................................................................. 273
Table 94: CT Type-A Input Levels .................................................................................................................. 274
Table 95: CT Type-B Input Levels .................................................................................................................. 275
Table 96: CT Type-C Input Levels (CMOS) ..................................................................................................... 275
Table 97: CT Type-D Input Levels .................................................................................................................. 276
Table 98: Differential Input Swing Requirements for CK_t, CK_c ..................................................................... 277
Table 99: Minimum Time AC Time tDVAC for CK ........................................................................................... 278
Table 100: Single-Ended Requirements for CK ............................................................................................... 279
Table 101: CK Differential Input Slew Rate Definition ..................................................................................... 279
Table 102: Cross Point Voltage For CK Differential Input Signals at DDR4-1600 through DDR4-2400 ................ 281
09005aef84af6dd0
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16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Features
Table 103:
Table 104:
Table 105:
Table 106:
Table 107:
Table 108:
Table 109:
Table 110:
Table 111:
Table 112:
Table 113:
Table 114:
Table 115:
Table 116:
Table 117:
Table 118:
Table 119:
Table 120:
Table 121:
Table 122:
Table 123:
Table 124:
Table 125:
Table 126:
Table 127:
Table 128:
Table 129:
Table 130:
Table 131:
Table 132:
Table 133:
Table 134:
Table 135:
Table 136:
Table 137:
Table 138:
Table 139:
Table 140:
Table 141:
Table 142:
Table 143:
Table 144:
Table 145:
Table 146:
Table 147:
Table 148:
Table 149:
Table 150:
Table 151:
Table 152:
Table 153:
Table 154:
Cross Point Voltage For CK Differential Input Signals at DDR4-2666 through DDR4-3200 ................ 281
DDR4-1600 through DDR4-2400 Differential Input Swing Requirements for DQS_t, DQS_c ............. 282
DDR4-2633 through DDR4-3200 Differential Input Swing Requirements for DQS_t, DQS_c ............. 282
Cross Point Voltage For Differential Input Signals DQS ................................................................... 283
DQS Differential Input Slew Rate Definition .................................................................................. 284
DDR4-1600 through DDR4-2400 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c ... 284
DDR4-2666 through DDR4-3200 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c ... 285
ADDR, CMD, CNTL Overshoot and Undershoot/Specifications ...................................................... 286
CK Overshoot and Undershoot/ Specifications .............................................................................. 287
Data, Strobe, and Mask Overshoot and Undershoot/ Specifications ................................................ 288
Single-Ended Output Levels ......................................................................................................... 288
Single-Ended Output Slew Rate Definition .................................................................................... 289
Single-Ended Output Slew Rate .................................................................................................... 290
Differential Output Levels ............................................................................................................. 290
Differential Output Slew Rate Definition ....................................................................................... 290
Differential Output Slew Rate ....................................................................................................... 291
Connectivity Test Mode Output Levels .......................................................................................... 292
Connectivity Test Mode Output Slew Rate ..................................................................................... 293
Output Driver Electrical Characteristics During Connectivity Test Mode ......................................... 295
Strong Mode (34Ω) Output Driver Electrical Characteristics ........................................................... 296
Weak Mode (48Ω) Output Driver Electrical Characteristics ............................................................. 297
Output Driver Sensitivity Definitions ............................................................................................ 298
Output Driver Voltage and Temperature Sensitivity ....................................................................... 298
Alert Driver Voltage ...................................................................................................................... 299
ODT DC Characteristics ............................................................................................................... 300
ODT Sensitivity Definitions .......................................................................................................... 301
ODT Voltage and Temperature Sensitivity ..................................................................................... 301
ODT Timing Definitions ............................................................................................................... 302
Reference Settings for ODT Timing Measurements ........................................................................ 302
DRAM Package Electrical Specifications for x4 and x8 Devices ....................................................... 305
DRAM Package Electrical Specifications for x16 Devices ................................................................ 306
Pad Input/Output Capacitance ..................................................................................................... 308
Thermal Characteristics ............................................................................................................... 309
Basic IDD, IPP, and IDDQ Measurement Conditions .......................................................................... 312
IDD0 and IPP0 Measurement-Loop Pattern1 .................................................................................... 316
IDD1 Measurement – Loop Pattern1 ............................................................................................... 317
IDD2N, IDD3N, and IPP3P Measurement – Loop Pattern1 .................................................................... 318
IDD2NT and IDDQ2NT Measurement – Loop Pattern1 ......................................................................... 319
IDD4R Measurement – Loop Pattern1 .............................................................................................. 320
IDD4W Measurement – Loop Pattern1 ............................................................................................. 321
IDD4Wc Measurement – Loop Pattern1 ............................................................................................ 322
IDD5R Measurement – Loop Pattern1 .............................................................................................. 323
IDD7 Measurement – Loop Pattern1 ............................................................................................... 324
Timings used for I DD, IPP, and IDDQ Measurement – Loop Patterns .................................................. 325
IDD, IPP, and IDDQ Current Limits – Rev. A ....................................................................................... 326
IDD, IPP, and IDDQ Current Limits – Rev. B ....................................................................................... 327
DDR4-1600 Speed Bins and Operating Conditions ......................................................................... 330
DDR4-1866 Speed Bins and Operating Conditions ......................................................................... 331
DDR4-2133 Speed Bins and Operating Conditions ......................................................................... 332
DDR4-2400 Speed Bins and Operating Conditions ......................................................................... 333
DDR4-2666 Speed Bins and Operating Conditions ......................................................................... 334
DDR4-2933 Speed Bins and Operating Conditions ......................................................................... 335
09005aef84af6dd0
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17
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Features
Table 155:
Table 156:
Table 157:
Table 158:
Table 159:
Table 160:
DDR4-3200 Speed Bins and Operating Conditions ......................................................................... 337
Refresh Parameters by Device Density ........................................................................................... 338
Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 ................... 339
Electrical Characteristics and AC Timing Parameters ..................................................................... 351
Options - Speed Based .................................................................................................................. 364
Options - Width Based .................................................................................................................. 365
09005aef84af6dd0
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18
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
General Notes and Description
General Notes and Description
Description
The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM for the x16 configuration and as a 16-bank DRAM for the
x4 and x8 configurations. The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface
designed to transfer two data words per clock cycle at the I/O pins.
A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit
wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit
wide, one-half-clock-cycle data transfers at the I/O pins.
Industrial Temperature
An industrial temperature (IT) device option requires that the case temperature not exceed below –40°C or above 95°C. JEDEC specifications require the refresh rate to double
when T C exceeds 85°C; this also requires use of the high-temperature self refresh option.
Additionally, ODT resistance and the input/output impedance must be derated when
operating outside of the commercial temperature range, when T C is between –40°C and
0°C.
General Notes
• The functionality and the timing specifications discussed in this data sheet are for the
DLL enable mode of operation (normal operation), unless specifically stated otherwise.
• Throughout the data sheet, the various figures and text refer to DQs as "DQ." The DQ
term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise.
• The terms "_t" and "_c" are used to represent the true and complement of a differential signal pair. These terms replace the previously used notation of "#" and/or overbar characters. For example, differential data strobe pair DQS, DQS# is now referred
to as DQS_t, DQS_c.
• The term "_n" is used to represent a signal that is active LOW and replaces the previously used "#" and/or overbar characters. For example: CS# is now referred to as
CS_n.
• The terms "DQS" and "CK" found throughout the data sheet are to be interpreted as
DQS_t, DQS_c and CK_t, CK_c respectively, unless specifically stated otherwise.
• Complete functionality may be described throughout the entire document; any page
or diagram may have been simplified to convey a topic and may not be inclusive of all
requirements.
• Any specific requirement takes precedence over a general statement.
• Any functionality not specifically stated here within is considered undefined, illegal,
and not supported, and can result in unknown operation.
• Addressing is denoted as BG[n] for bank group, BA[n] for bank address, and A[n] for
row/col address.
• The NOP command is not allowed, except when exiting maximum power savings
mode or when entering gear-down mode, and only a DES command should be used.
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
19
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
General Notes and Description
• Not all features described within this document may be available on the Rev. A (first)
version.
• Not all specifications listed are finalized industry standards; best conservative estimates have been provided when an industry standard has not been finalized.
• Although it is implied throughout the specification, the DRAM must be used after V DD
has reached the stable power-on level, which is achieved by toggling CKE at least once
every 8192 × tREFI. However, in the event CKE is fixed HIGH, toggling CS_n at least
once every 8192 × tREFI is an acceptable alternative. Placing the DRAM into self refresh mode also alleviates the need to toggle CKE.
• Not all features designated in the data sheet may be supported by earlier die revisions
due to late definition by JEDEC.
Definitions of the Device-Pin Signal Level
•
•
•
•
HIGH: A device pin is driving the logic 1 state.
LOW: A device pin is driving the logic 0 state.
High-Z: A device pin is tri-state.
ODT: A device pin terminates with the ODT setting, which could be terminating or tristate depending on the mode register setting.
Definitions of the Bus Signal Level
• HIGH: One device on the bus is HIGH, and all other devices on the bus are either ODT
or High-Z. The voltage level on the bus is nominally V DDQ.
• LOW: One device on the bus is LOW, and all other devices on the bus are either ODT
or High-Z. The voltage level on the bus is nominally V OL(DC) if ODT was enabled, or
VSSQ if High-Z.
• High-Z: All devices on the bus are High-Z. The voltage level on the bus is undefined as
the bus is floating.
• ODT: At least one device on the bus is ODT, and all others are High-Z. The voltage level on the bus is nominally V DDQ.
• The specification requires 8,192 refresh commands within 64ms between 0 oC and 85
oC. This allows for a tREFI of 7.8125μs (the use of "7.8μs" is truncated from 7.8125μs).
The specification also requires 8,192 refresh commands within 32ms between 85 oC
and 95 oC. This allows for a tREFI of 3.90625μs (the use of "3.9μs" is truncated from
3.90625μs).
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
20
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Functional Block Diagrams
Functional Block Diagrams
DDR4 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally
configured as an 16-bank (4-banks per Bank Group) DRAM.
Figure 2: 1 Gig x 4 Functional Block Diagram
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09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
21
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Functional Block Diagrams
Figure 4: 256 Meg x 16 Functional Block Diagram
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09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
22
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Ball Assignments
Ball Assignments
Figure 5: 78-Ball x4, x8 Ball Assignments
1
2
3
VDD
VSSQ
NF, NF/
TDQS_c
4
5
6
7
8
9
NF, NF/DM_n/
DBI_n/TDQS_t
VSSQ
VSS
A
A
B
B
VPP
VDDQ
DQS_c
DQ1
VDDQ
ZQ
C
C
VDDQ
DQ0
DQS_t
VDD
VSS
VDDQ
VSSQ
DQ4/NC
DQ2
DQ3
DQ5/NC
VSSQ
VSS
VDDQ
DQ6/NC
DQ7/NC
VDDQ
VSS
D
D
E
E
F
F
C2/ODT1 ODT
VDD
CK_t
CK_c
VDD
G
G
C0/CKE1
VSS
CKE
CS_n
C1/CS1_n RFU/TEN
H
H
VDD
CAS_n/
A15
WE_n/A14ACT_n
RAS_n/A16 VSS
J
J
VREFCA
BG0
A10/AP
A12/BC_n BG1
VDD
K
K
VSS
BA0
A4
A3
BA1
VSS
RESET_n
A6
A0
A1
A5
ALERT_n
VDD
A8
A2
A9
A7
VPP
L
L
M
M
N
N
VSS
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
A11
PAR
A17/NF
A13
VDD
1. See Ball Descriptions.
2. A comma “,” separates the configuration; a slash “/” defines a selectable function. For
example: Ball A7 = NF, NF/DM_n/DBI_n/TDQS_t where NF applies to the x4 configuration
only. NF/DM_n/DBI_n/TDQS_t applies to the x8 configuration only and is selectable between NF, DM_n, DBI_n, or TDQS_t via MRS.
3. Address bits (including bank groups) are density- and configuration-dependent (see Addressing).
23
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Ball Assignments
Figure 6: 96-Ball x16 Ball Assignments
1
2
3
4
5
6
7
8
9
A
A
VDDQ
VSSQ
DQ8
UDQS_c
VSSQ
VDDQ
VPP
VSS
VDD
UDQS_t
DQ9
VDD
B
B
C
C
VDDQ
DQ12
DQ11
DQ10
DQ13
VSSQ
D
D
VDD
VSSQ
VSS
NF/UDM_n/
UDBI_n
DQ14
DQ15
VSSQ
NF/LDM_n/
LDBI_n
VSSQ
VDDQ
E
E
VSSQ
VSS
F
F
VSSQ
VDDQ
DQ1
LDQS_c
VDDQ
ZQ
G
G
VDDQ
DQ0
VDD
LDQS_t
VSS
VDDQ
H
H
VSSQ
DQ4
DQ2
DQ3
DQ5
VSSQ
VDD
VDDQ
DQ6
DQ7
VDDQ
VDD
J
J
K
K
VSS
CKE
CK_t
ODT
CK_c
VSS
L
L
VDD WE_n/A14 ACT_n
CS_n RAS_n/A16 VDD
M
M
VREFCA
BG0
A12/BC_n CAS-n/A15 VSS
A10/AP
N
N
VSS
BA0
A4
A3
BA1
TEN
A5
ALERT_n
P
P
RESET_n
A6
A0
A1
R
R
VDD
A8
A2
A9
A7
VPP
VSS
A11
PAR
NC
A13
VDD
T
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
T
1. See Ball Descriptions.
2. A slash “/” defines a selectable function. For example: Ball E7 = NF/LDM_n. If data mask
is enabled via the MRS, ball E7 = LDM_n. If data mask is disabled in the MRS, E7 = NF (no
function).
3. Address bits (including bank groups) are density- and configuration-dependent (see Addressing).
24
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Ball Descriptions
Ball Descriptions
The pin description table below is a comprehensive list of all possible pins for DDR4 devices. All pins listed may not be supported on the device defined in this data sheet. See
the Ball Assignments section to review all pins used on this device.
Table 3: Ball Descriptions
Symbol
Type
Description
A[17:0]
Input
Address inputs: Provide the row address for ACTIVATE commands and the column
address for READ/WRITE commands to select one location out of the memory array in
the respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, RAS_n/A16 have additional functions, see individual entries in this table.) The address inputs also provide
the op-code during the MODE REGISTER SET command. A16 is used on some 8Gb and
16Gb parts, and A17 is only used on some 16Gb parts.
A10/AP
Input
Auto precharge: A10 is sampled during READ and WRITE commands to determine
whether auto precharge should be performed to the accessed bank after a READ or
WRITE operation. (HIGH = auto precharge; LOW = no auto precharge.) A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies
to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged,
the bank is selected by the bank group and bank addresses.
A12/BC_n
Input
Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine if
burst chop (on-the-fly) will be performed. (HIGH = no burst chop; LOW = burst chopped). See the Command Truth Table.
ACT_n
Input
Command input: ACT_n indicates an ACTIVATE command. When ACT_n (along with
CS_n) is LOW, the input pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are treated as
row address inputs for the ACTIVATE command. When ACT_n is HIGH (along with
CS_n LOW), the input pins RAS_n/ A16, CAS_n/A15, and WE_n/A14 are treated as normal commands that use the RAS_n, CAS_n, and WE_n signals. See the Command
Truth Table.
BA[1:0]
Input
Bank address inputs: Define the bank (within a bank group) to which an ACTIVATE,
READ, WRITE, or PRECHARGE command is being applied. Also determines which
mode register is to be accessed during a MODE REGISTER SET command.
BG[1:0]
Input
Bank group address inputs: Define the bank group to which a REFRESH, ACTIVATE,
READ, WRITE, or PRECHARGE command is being applied. Also determines which
mode register is to be accessed during a MODE REGISTER SET command. BG[1:0] are
used in the x4 and x8 configurations. BG1 is not used in the x16 configuration.
C0/CKE1,
C1/CS1_n,
C2/ODT1
Input
Stack address inputs: These inputs are used only when devices are stacked; that is,
they are used in 2H, 4H, and 8H stacks for x4 and x8 configurations (these pins are
not used in the x16 configuration). DDR4 will support a traditional DDP package,
which uses these three signals for control of the second die (CS1_n, CKE1, ODT1).
DDR4 is not expected to support a traditional QDP package. For all other stack configurations, such as a 4H or 8H, it is assumed to be a single-load (master/slave) type of
configuration where C0, C1, and C2 are used as chip ID selects in conjunction with a
single CS_n, CKE, and ODT signal.
CK_t,
CK_c
Input
Clock: Differential clock inputs. All address, command, and control input signals are
sampled on the crossing of the positive edge of CK_t and the negative edge of CK_c.
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25
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Ball Descriptions
Table 3: Ball Descriptions (Continued)
Symbol
Type
Description
CKE
Input
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals, device input buffers, and output drivers. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down
(row active in any bank). CKE is asynchronous for self refresh exit. After VREFCA has
become stable during the power-on and initialization sequence, it must be maintained during all operations (including SELF REFRESH). CKE must be maintained HIGH
throughout read and write accesses. Input buffers (excluding CK_t, CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input buffers (excluding CKE and
RESET_n) are disabled during self refresh.
CS_n
Input
Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides
for external rank selection on systems with multiple ranks. CS_n is considered part of
the command code.
DM_n,
UDM_n
LDM_n
Input
Input data mask: DM_n is an input mask signal for write data. Input data is masked
when DM is sampled LOW coincident with that input data during a write access. DM
is sampled on both edges of DQS. DM is not supported on x4 configurations. The
UDM_n and LDM_n pins are used in the x16 configuration: UDM_n is associated with
DQ[15:8]; LDM_n is associated with DQ[7:0]. The DM, DBI, and TDQS functions are enabled by mode register settings. See the Data Mask section.
ODT
Input
On-die termination: ODT (registered HIGH) enables termination resistance internal
to the DDR4 SDRAM. When enabled, ODT (RTT) is applied only to each DQ, DQS_t,
DQS_c, DM_n/DBI_n/TDQS_t, and TDQS_c signal for the x4 and x8 configurations
(when the TDQS function is enabled via mode register). For the x16 configuration, RTT
is applied to each DQ, DQSU_t, DQSU_c, DQSL_t, DQSL_c, UDM_n, and LDM_n signal.
The ODT pin will be ignored if the mode registers are programmed to disable RTT.
PAR
Input
Parity for command and address: This function can be enabled or disabled via the
mode register. When enabled, the parity signal covers all command and address inputs, including ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, A[17:0], A10/AP, A12/BC_n,
BA[1:0], and BG[1:0] with C0, C1, and C2 on 3DS only devices. Control pins NOT covered by the parity signal are CS_n, CKE, and ODT. Unused address pins that are density- and configuration-specific should be treated internally as 0s by the DRAM parity
logic. Command and address inputs will have parity check performed when commands are latched via the rising edge of CK_t and when CS_n is LOW.
RAS_n/A16,
CAS_n/A15,
WE_n/A14
Input
Command inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n and
ACT_n) define the command and/or address being entered. See the ACT_n description in this table.
RESET_n
Input
Active LOW asynchronous reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_n
is a CMOS rail-to-rail signal with DC HIGH and LOW at 80% and 20% of VDD (960 mV
for DC HIGH and 240 mV for DC LOW).
TEN
Input
Connectivity test mode: TEN is active when HIGH and inactive when LOW. TEN
must be LOW during normal operation. TEN is a CMOS rail-to-rail signal with DC
HIGH and LOW at 80% and 20% of VDD (960mV for DC HIGH and 240mV for DC
LOW).
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26
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Ball Descriptions
Table 3: Ball Descriptions (Continued)
Symbol
Type
Description
DQ
I/O
Data input/output: Bidirectional data bus. DQ represents DQ[3:0], DQ[7:0], and
DQ[15:0] for the x4, x8, and x16 configurations, respectively. If write CRC is enabled
via mode register, the write CRC code is added at the end of data burst. Any one or
all of DQ0, DQ1, DQ2, and DQ3 may be used to monitor the internal VREF level during
test via mode register setting MR[4] A[4] = HIGH, training times change when enabled. During this mode, the RTT value should be set to High-Z. This measurement is
for verification purposes and is NOT an external voltage supply pin.
DBI_n,
UDBI_n,
LDBI_n
I/O
DBI input/output: Data bus inversion. DBI_n is an input/output signal used for data
bus inversion in the x8 configuration. UDBI_n and LDBI_n are used in the x16 configuration; UDBI_n is associated with DQ[15:8], and LDBI_n is associated with DQ[7:0]. The
DBI feature is not supported on the x4 configuration. DBI can be configured for both
READ (output) and WRITE (input) operations depending on the mode register settings. The DM, DBI, and TDQS functions are enabled by mode register settings. See
the Data Bus Inversion section.
DQS_t,
DQS_c,
DQSU_t,
DQSU_c,
DQSL_t,
DQSL_c
I/O
Data strobe: Output with READ data, input with WRITE data. Edge-aligned with
READ data, centered-aligned with WRITE data. For the x16, DQSL corresponds to the
data on DQ[7:0]; DQSU corresponds to the data on DQ[15:8]. For the x4 and x8 configurations, DQS corresponds to the data on DQ[3:0] and DQ[7:0], respectively. DDR4
SDRAM supports a differential data strobe only and does not support a single-ended
data strobe.
ALERT_n
Output
Alert output: This signal allows the DRAM to indicate to the system's memory controller that a specific alert or event has occurred. Alerts will include the command/
address parity error and the CRC data error when either of these functions is enabled
in the mode register.
TDQS_t,
TDQS_c
Output
Termination data strobe: TDQS_t and TDQS_c are used by x8 DRAMs only. When
enabled via the mode register, the DRAM will enable the same RTT termination resistance on TDQS_t and TDQS_c that is applied to DQS_t and DQS_c. When the TDQS
function is disabled via the mode register, the DM/TDQS_t pin will provide the DATA
MASK (DM) function, and the TDQS_c pin is not used. The TDQS function must be disabled in the mode register for both the x4 and x16 configurations. The DM function
is supported only in x8 and x16 configurations.
VDD
Supply
Power supply: 1.2V ±0.060V.
VDDQ
Supply
DQ power supply: 1.2V ±0.060V.
VPP
Supply
DRAM activating power supply: 2.5V –0.125V/+0.250V.
VREFCA
Supply
Reference voltage for control, command, and address pins.
VSS
Supply
Ground.
VSSQ
Supply
DQ ground.
ZQ
Reference
RFU
–
Reserved for future use.
NC
–
No connect: No internal electrical connection is present.
NF
–
No function: May have internal connection present but has no function.
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Reference ball for ZQ calibration: This ball is tied to an external 240Ω resistor
(RZQ), which is tied to VSSQ.
27
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Package Dimensions
Package Dimensions
Figure 7: 78-Ball FBGA – x4, x8 "HX"
0.155
Seating plane
1.8 CTR
Nonconductive
overmold
78X Ø0.45
Dimensions
apply to solder
balls post-reflow
on Ø0.35 SMD
ball pads.
A
0.12
A
Ball A1 ID
9 8 7
Ball A1 ID
3 2 1
A
B
C
D
E
F
G
H
11.5 ±0.1
9.6 CTR
J
K
L
M
N
0.8 TYP
0.8 TYP
1.1 ±0.1
6.4 CTR
0.25 MIN
9 ±0.1
Notes:
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1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (Pb-free 96.5% Sn, 3% Ag, 0.5% Cu).
28
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Package Dimensions
Figure 8: 78-Ball FBGA – x4, x8 "RH"
0.155
Seating plane
A
78X Ø0.47
Dimensions apply
to solder balls postreflow on Ø0.42 SMD
ball pads.
0.12 A
1.8 CTR
Nonconductive
overmold
Ball A1 ID
(covered by SR)
9
8
7
3
2
Ball A1 ID
1
A
B
C
D
E
F
10.5 ±0.1
G
9.6 CTR
H
J
K
L
M
N
0.8 TYP
0.8 TYP
1.1 ±0.1
6.4 CTR
0.34 ±0.05
9 ±0.1
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (Pb-free 96.5% Sn, 3% Ag, 0.5% Cu).
29
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Package Dimensions
Figure 9: 96-Ball FBGA – x16 "HA"
0.155
Seating plane
1.8 CTR
Nonconductive
overmold
96X Ø0.45
Dimensions
apply to solder
balls post-reflow
on Ø0.35 SMD
ball pads.
9
8
7
3
A
2
0.12 A
Ball A1 Index
(covered by SR)
1
Ball A1 Index
A
B
C
D
E
F
G
H
12 CTR
J
14 ±0.1
K
L
M
N
P
R
0.8 TYP
T
0.8 TYP
1.1 ±0.1
6.4 CTR
0.25 MIN
9 ±0.1
Notes:
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (Pb-free 96.5% Sn, 3% Ag, 0.5% Cu).
30
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Package Dimensions
Figure 10: 96-Ball FBGA – x16 "GE"
0.155
Seating plane
A
0.12 A
1.8 CTR
Nonconductive
overmold
96X Ø0.47
Dimensions apply
to solder balls postreflow on Ø0.42 SMD
ball pads.
Ball A1 ID
(covered by SR)
9 8 7
Ball A1 ID
3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
14 ±0.1
12 CTR
0.8 TYP
1.1 ±0.1
0.8 TYP
6.4 CTR
0.29 MIN
9 ±0.1
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (Pb-free 96.5% Sn, 3% Ag, 0.5% Cu).
31
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
State Diagram
State Diagram
This simplified state diagram provides an overview of the possible state transitions and
the commands to control them. Situations involving more than one bank, the enabling
or disabling of on-die termination, and some other events are not captured in full detail.
Figure 11: Simplified State Diagram
IVREFDQ,
RTT, and
so on
MPSM
From any state
RESET
SRX* = SRX with NOP
SRX*
CKE_L
MRS
Power
applied
Power-On
RESET
MRS
SRX*
Reset
procedure
TEN = 1
TEN = 1
MRS, MPR,
write leveling,
VREFDQ training
PDA
mode
Initialization
MRS
MRS
ZQCL
SRX
MRS
SRE
MRS
Connectivity
test
TEN = 0
ZQ
calibration
Self
refresh
ZQCL,ZQCS
REF
Idle
Refreshing
RESET
PDE
ACT
CKE_L
CKE_L
PDX
Active
powerdown
Precharge
powerdown
Activating
PDX
PDE
Bank
active
READ
WRITE
WRITE
WRITE A
READ
Writing
READ
READ A
WRITE
Reading
READ A
WRITE A
WRITE A
READ A
PRE, PREA
Writing
PRE, PREA
PRE, PREA
Precharging
Reading
Automatic
sequence
Command
sequence
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4Gb: x4, x8, x16 DDR4 SDRAM
State Diagram
Table 4: State Diagram Command Definitions
Command
Description
ACT
Active
MPR
Multipurpose register
MRS
Mode register set
PDE
Enter power-down
PDX
Exit power-down
PRE
Precharge
PREA
Precharge all
READ
RD, RDS4, RDS8
READ A
RDA, RDAS4, RDAS8
REF
Refresh, fine granularity refresh
RESET
Start reset procedure
SRE
Self refresh entry
SRX
Self refresh exit
TEN
Boundary scan mode enable
WRITE
WR, WRS4, WRS8 with/without CRC
WRITE A
WRA, WRAS4, WRAS8 with/without CRC
ZQCL
ZQ calibration long
ZQCS
ZQ calibration short
Note:
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1. See the Command Truth Table for more details.
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4Gb: x4, x8, x16 DDR4 SDRAM
Functional Description
Functional Description
The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen banks (4 bank groups with 4 banks for each bank group) for x4/x8 devices, and as eight banks for each bank group (2 bank groups with 4 banks each) for x16
devices. The device uses double data rate (DDR) architecture to achieve high-speed operation. DDR4 architecture is essentially an 8n-prefetch architecture with an interface
designed to transfer two data words per clock cycle at the I/O pins. A single read or
write access for a device module effectively consists of a single 8n-bit-wide, four-clockcycle-data transfer at the internal DRAM core and eight corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins.
Read and write accesses to the device are burst-oriented. Accesses start at a selected location and continue for a burst length of eight or a chopped burst of four in a programmed sequence. Operation begins with the registration of an ACTIVE command, which is
then followed by a READ or WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and row to be accessed (BG[1:0]
select the bank group for x4/x8, and BG0 selects the bank group for x16; BA[1:0] select
the bank, and A[17:0] select the row. See the Addressing section for more details). The
address bits registered coincident with the READ or WRITE command are used to select
the starting column location for the burst operation, determine if the auto PRECHARGE
command is to be issued (via A10), and select BC4 or BL8 mode on-the-fly (OTF) (via
A12) if enabled in the mode register.
Prior to normal operation, the device must be powered up and initialized in a predefined manner. The following sections provide detailed information covering device reset
and initialization, register definition, command descriptions, and device operation.
NOTE: The use of the NOP command is allowed only when exiting maximum power
saving mode or when entering gear-down mode.
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4Gb: x4, x8, x16 DDR4 SDRAM
RESET and Initialization Procedure
RESET and Initialization Procedure
To ensure proper device function, the power-up and reset initialization default values
for the following mode register (MR) settings are defined as:
•
•
•
•
•
•
•
Gear-down mode (MR3 A[3]): 0 = 1/2 rate
Per-DRAM addressability (MR3 A[4]): 0 = disable
Maximum power-saving mode (MR4 A[1]): 0 = disable
CS to command/address latency (MR4 A[8:6]): 000 = disable
CA parity latency mode (MR5 A[2:0]): 000 = disable
Hard Post Package Repair mode (MR4 A[13]) : 0 = Disable
Soft Post Package Repair mode (MR4 A[5]) : 0 = Disable
Power-Up and Initialization Sequence
The following sequence is required for power-up and initialization:
1. Apply power (RESET_n and TEN should be maintained below 0.2 × V DD while supplies ramp up; all other inputs may be undefined). When supplies have ramped to
a valid stable level, RESET_n must be maintained below 0.2 × V DD for a minimum
of tPW_RESET_L and TEN must be maintained below 0.2 × V DD for a minimum of
700μs. CKE is pulled LOW anytime before RESET_n is de-asserted (minimum time
of 10ns). The power voltage ramp time between 300mV to V DD,min must be no
greater than 200ms, and during the ramp, V DD must be greater than or equal to
VDDQ and (VDD - V DDQ) < 0.3V. V PP must ramp at the same time or before V DD, and
VPP must be equal to or higher than V DD at all times. After V DD has ramped and
reached the stable level and after RESET_n goes high, the initialization sequence
must be started within 3 seconds. For debug purposes, the 3 second delay limit
may be extended to 60 minutes provided the DRAM is operated in this debug
mode for no more than 360 cumulative hours.
During power-up, the supply slew rate is governed by the limits stated in the table
below and either Condition A or Condition B must be met.
Table 5: Supply Power-up Slew Rate
Note:
Symbol
Min
Max
Unit Comment
VDD_SL, VDDQ_SL,
VPP_SL
0.004
600
V/ms Measured between 300mV and 80% of
supply minimum
VDD_ona
N/A
200
ms
VDD maximum ramp time from 300mV to
VDD minimum
VDDQ_ona
N/A
200
ms
VDDQ maximum ramp time from 300mV to
VDDQ minimum
1. 20 MHz band-limited measurement.
• Condition A:
– Apply V PP without any slope reversal before or at the same time as V DD and
VDDQ.
– VDD and V DDQ are driven from a single-power converter output and apply
VDD/VDDQ without any slope reversal before or at the same time as V TT and
VREFCA.
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4Gb: x4, x8, x16 DDR4 SDRAM
RESET and Initialization Procedure
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
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– The voltage levels on all balls other than V DD, V DDQ, V SS, and V SSQ must be less
than or equal to V DDQ and V DD on one side and must be greater than or equal
to V SSQ and V SS on the other side.
– VTT is limited to 0.76V MAX when the power ramp is complete.
– VREFCA tracks V DD/2.
• Condition B:
– Apply V PP without any slope reversal before or at the same time as V DD.
– Apply V DD without any slope reversal before or at the same time as V DDQ.
– Apply V DDQ without any slope reversal before or at the same time as V TT and
VREFCA.
– The voltage levels on all pins other than V PP, V DD, V DDQ, V SS, and V SSQ must be
less than or equal to V DDQ and V DD on one side and must be larger than or
equal to V SSQ and V SS on the other side.
After RESET_n is de-asserted, wait for another 500μs but no longer then 3 seconds
until CKE becomes active. During this time, the device will start internal state initialization; this will be done independently of external clocks. A reasonable attempt
was made in the design to power up with the following default MR settings: geardown mode (MR3 A[3]): 0 = 1/2 rate; per-DRAM addressability (MR3 A[4]): 0 = disable; maximum power-down (MR4 A[1]): 0 = disable; CS to command/address latency (MR4 A[8:6]): 000 = disable; CA parity latency mode (MR5 A[2:0]): 000 = disable. However, it should be assumed that at power up the MR settings are undefined and should be programmed as shown below.
Clocks (CK_t, CK_c) need to be started and stabilized for at least 10ns or 5 tCK
(whichever is larger) before CKE goes active. Because CKE is a synchronous signal,
the corresponding setup time to clock (tIS) must be met. Also, a DESELECT command must be registered (with tIS setup time to clock) at clock edge Td. After the
CKE is registered HIGH after RESET, CKE needs to be continuously registered
HIGH until the initialization sequence is finished, including expiration of tDLLK
and tZQINIT.
The device keeps its ODT in High-Z state as long as RESET_n is asserted. Further,
the SDRAM keeps its ODT in High-Z state after RESET_n de-assertion until CKE is
registered HIGH. The ODT input signal may be in an undefined state until tIS before CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal
may be statically held either LOW or HIGH. If RTT(NOM) is to be enabled in MR1,
the ODT input signal must be statically held LOW. In all cases, the ODT input signal remains static until the power-up initialization sequence is finished, including
the expiration of tDLLK and tZQINIT.
After CKE is registered HIGH, wait a minimum of RESET CKE EXIT time, tXPR, before issuing the first MRS command to load mode register (tXPR = MAX (tXS; 5 ×
tCK).
Issue MRS command to load MR3 with all application settings, wait tMRD.
Issue MRS command to load MR6 with all application settings, wait tMRD.
Issue MRS command to load MR5 with all application settings, wait tMRD.
Issue MRS command to load MR4 with all application settings, wait tMRD.
Issue MRS command to load MR2 with all application settings, wait tMRD.
Issue MRS command to load MR1 with all application settings, wait tMRD.
Issue MRS command to load MR0 with all application settings, wait tMOD.
Issue a ZQCL command to start ZQ calibration.
Wait for tDLLK and tZQINIT to complete.
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4Gb: x4, x8, x16 DDR4 SDRAM
RESET and Initialization Procedure
15. The device will be ready for normal operation. Once the DRAM has been initialized, if the DRAM is in an idle state longer than 960ms, then either (a) REF commands must be issued within tREFI constraints (specification for posting allowed)
or (b) CKE or CS_n must toggle once within every 960ms interval of idle time. For
debug purposes, the 960ms delay limit maybe extended to 60 minutes provided
the DRAM is operated in this debug mode for no more than 360 cumulative hours.
A stable valid V DD level is a set DC level (0Hz to 250 KHz) and must be no less than
VDD,min and no greater than V DD,max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC level
is stable. AC noise of ±60mV (greater than 250 KHz) is allowed on V DD provided the
noise doesn't alter V DD to less than V DD,min or greater than V DD,max.
A stable valid V DDQ level is a set DC level (0Hz to 250 KHz) and must be no less than
VDDQ,min and no greater than V DDQ,max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC
level is stable. AC noise of ±60mV (greater than 250 KHz) is allowed on V DDQ provided
the noise doesn't alter V DDQ to less than V DDQ,min or greater than V DDQ,max.
A stable valid V PP level is a set DC level (0Hz to 250 KHz) and must be no less than
VPP,min and no greater than V PP,max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC level
is stable. AC noise of ±120mV (greater than 250KHz) is allowed on V PP provided the
noise doesn't alter V PP to less than V PP,min or greater than V PP,max.
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RESET and Initialization Procedure
Figure 12: RESET and Initialization Sequence at Power-On Ramping
Ta
Tb
Tc
Te
Td
Tf
Th
Tg
Ti
Tj
Tk
CK_t, CK_c
tCKSRX
VPP
VDD, VDDQ
tPW_RESET_L
T = 500μs
RESET_n
T (MIN) = 10ns
tIS
Valid
CKE
tDLLK
tIS
Command
Note 1
BG, BA
tXPR
tMRD
tMRD
tMRD
tZQinit
tMOD
MRS
MRS
MRS
MRS
MRx
MRx
MRx
MRx
ZQCL
Note 1
Valid
tIS
tIS
Static LOW in case RTT(NOM) is enabled at time Tg, otherwise static HIGH or LOW
ODT
Valid
Valid
RTT
Time Break
Notes:
Don’t Care
1. From time point Td until Tk, a DES command must be applied between MRS and ZQCL
commands.
2. MRS commands must be issued to all mode registers that have defined settings.
3. In general, there is no specific sequence for setting the MRS locations (except for dependent or co-related features, such as ENABLE DLL in MR1 prior to RESET DLL in MR0,
for example).
4. TEN is not shown; however, it is assumed to be held LOW.
RESET Initialization with Stable Power Sequence
The following sequence is required for RESET at no power interruption initialization:
1. Assert RESET_n below 0.2 × V DD any time reset is needed (all other inputs may be
undefined). RESET must be maintained for a minimum of 100ns. CKE is pulled
LOW before RESET_n is de-asserted (minimum time 10ns).
2. Follow Steps 2 to 10 in the Reset and Initialization Sequence at Power-on Ramping
procedure.
When the reset sequence is complete, all counters except the refresh counters have
been reset and the device is ready for normal operation.
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RESET and Initialization Procedure
Figure 13: RESET Procedure at Power Stable Condition
Ta
Tb
Tc
Te
Td
Th
Tg
Tf
Ti
Tj
Tk
CK_t, CK_c
tCKSRX
VPP
VDD , VDDQ
tPW_RESET_S
T = 500μs
RESET_n
T (MIN) = 10ns
tIS
Valid
CKE
tDLLK
tIS
Command
Note 1
BG, BA
tXPR
tMRD
tMRD
tMRD
tMOD
MRS
MRS
MRS
MRS
MRx
MRx
MRx
MRx
tZQinit
ZQCL
Note 1
Valid
tIS
tIS
Static LOW in case RTT(NOM) is enabled at time Tg, otherwise static HIGH or LOW
ODT
Valid
Valid
RTT
Time Break
Notes:
Don’t Care
1. From time point Td until Tk, a DES command must be applied between MRS and ZQCL
commands.
2. MRS commands must be issued to all mode registers that have defined settings.
3. In general, there is no specific sequence for setting the MRS locations (except for dependent or co-related features, such as ENABLE DLL in MR1 prior to RESET DLL in MR0,
for example).
4. TEN is not shown; however, it is assumed to be held LOW.
Uncontrolled Power-Down Sequence
In the event of an uncontrolled ramping down of V PP supply, V PP is allowed to be less
than V DD provided the following conditions are met:
• Condition A: V PP and V DD/VDDQ are ramping down (as part of turning off) from normal operating levels.
• Condition B: The amount that V PP may be less than V DD/VDDQ is less than or equal to
500mV.
• Condition C: The time V PP may be less than V DD is ≤10ms per occurrence with a total
accumulated time in this state ≤100ms.
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Programming Mode Registers
• Condition D: The time V PP may be less than 2.0V and above V SS while turning off is
≤15ms per occurrence with a total accumulated time in this state ≤150ms.
Programming Mode Registers
For application flexibility, various functions, features, and modes are programmable in
seven mode registers (MRn) provided by the device as user defined variables that must
be programmed via a MODE REGISTER SET (MRS) command. Because the default values of the mode registers are not defined, contents of mode registers must be fully initialized and/or re-initialized; that is, they must be written after power-up and/or reset
for proper operation. The contents of the mode registers can be altered by re-executing
the MRS command during normal operation. When programming the mode registers,
even if the user chooses to modify only a sub-set of the MRS fields, all address fields
within the accessed mode register must be redefined when the MRS command is issued. MRS and DLL RESET commands do not affect array contents, which means these
commands can be executed any time after power-up without affecting the array contents.
The MRS command cycle time, tMRD, is required to complete the WRITE operation to
the mode register and is the minimum time required between the two MRS commands
shown in the tMRD Timing figure.
Some of the mode register settings affect address/command/control input functionality. In these cases, the next MRS command can be allowed when the function being updated by the current MRS command is completed. These MRS commands don’t apply
tMRD timing to the next MRS command; however, the input cases have unique MR setting procedures, so refer to individual function descriptions:
•
•
•
•
•
•
•
•
Gear-down mode
Per-DRAM addressability
Maximum power saving mode
CS to command/address latency
CA parity latency mode
VREFDQ training value
VREFDQ training mode
VREFDQ training range
Some mode register settings may not be supported because they are not required by
certain speed bins.
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Programming Mode Registers
Figure 14: tMRD Timing
T0
T1
T2
Ta0
Ta1
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
Command
Valid
Valid
Valid
MRS2
DES
DES
DES
DES
DES
MRS2
Valid
Address
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CK_c
CK_t
CKE
tMRD
Updating settings
Old settings
Settings
Time Break
Don’t Care
1. This timing diagram depicts CA parity mode “disabled” case.
2. tMRD applies to all MRS commands with the following exceptions:
Gear-down mode
CA parity mode
CAL mode
Per-DRAM addressability mode
VREFDQ training value, VREFDQ training mode, and VREFDQ training range
Notes:
The MRS command to nonMRS command delay, tMOD, is required for the DRAM to
update features, except for those noted in note 2 in figure below where the individual
function descriptions may specify a different requirement. tMOD is the minimum time
required from an MRS command to a nonMRS command, excluding DES, as shown in
the tMOD Timing figure.
Figure 15: tMOD Timing
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Tb0
Tb1
Tb2
Command
Valid
Valid
Valid
MRS2
DES
DES
DES
DES
DES
Valid
Valid
Address
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CK_c
CK_t
CKE
t
Settings
MOD
Updating settings
Old settings
New settings
Time Break
Notes:
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Don’t Care
1. This timing diagram depicts CA parity mode “disabled” case.
2. tMOD applies to all MRS commands with the following exceptions:
DLL enable, DLL RESET, Gear-down mode
VREFDQ training value, internal VREF training monitor, VREFDQ training mode, and VREFDQ
training range
Maximum power savings mode , Per-DRAM addressability mode, and CA parity mode
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Programming Mode Registers
The mode register contents can be changed using the same command and timing requirements during normal operation as long as the device is in idle state; that is, all
banks are in the precharged state with tRP satisfied, all data bursts are completed, and
CKE is HIGH prior to writing into the mode register. If the RTT(NOM) feature is enabled in
the mode register prior to and/or after an MRS command, the ODT signal must continuously be registered LOW, ensuring RTT is in an off state prior to the MRS command.
The ODT signal may be registered HIGH after tMOD has expired. If the RTT(NOM) feature
is disabled in the mode register prior to and after an MRS command, the ODT signal
can be registered either LOW or HIGH before, during, and after the MRS command. The
mode registers are divided into various fields depending on functionality and modes.
In some mode register setting cases, function updating takes longer than tMOD. This
type of MRS does not apply tMOD timing to the next valid command, excluding DES.
These MRS command input cases have unique MR setting procedures, so refer to individual function descriptions.
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Mode Register 0
Mode Register 0
Mode register 0 (MR0) controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die; only settings required for speed bin support are available. MR0 is written by issuing the MRS
command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR0 Register
Definition table.
Table 6: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9
bus
_n _n _n
Mode
register
21
20
19
18
Note:
17
–
–
–
13
12
11
10
9
A8
A7
A6
A5
A4
A3
A2
A1
A0
8
7
6
5
4
3
2
1
0
1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.
Table 7: MR0 Register Definition
Mode
Register
21
20:18
17
13,11:9
Description
RFU
0 = Must be programmed to 0
1 = Reserved
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
N/A on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
WR (WRITE recovery)/RTP (READ-to-PRECHARGE)
0000 = 10 / 5 clocks1
0001 = 12 / 6 clocks
0010 = 14 / 7 clocks1
0011 = 16 / 8 / clocks
0100 = 18 / 9 clocks1
0101 = 20 /10 clocks
0110 = 24 / 12 clocks
0111 = 22 / 11 clocks1
1000 = 26 / 13 clocks1
1001 = 28 / 14 clocks2
1010 through 1111 = Reserved
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Mode Register 0
Table 7: MR0 Register Definition (Continued)
Mode
Register
Description
8
DLL reset
0 = No
1 = Yes
7
Test mode (TM) – Manufacturer use only
0 = Normal operating mode, must be programmed to 0
12, 6:4, 2
3
1:0
CAS latency (CL) – Delay in clock cycles from the internal READ command to first data-out
00000 = 9 clocks1
00001 = 10 clocks
00010 = 11 clocks1
00011 = 12 clocks
00100 = 13 clocks1
00101 = 14 clocks
00110 = 15 clocks1
00111 = 16 clocks
01000 = 18 clocks
01001 = 20 clocks
01010 = 22 clocks
01011 = 24 clocks
01100 = 23 clocks1
01101 = 17 clocks1
01110 = 19 clocks1
01111 = 21 clocks 1
10000 = 25 clocks (3DS use only)
10001 = 26 clocks
10010 = 27 clocks (3DS use only)
10011 = 28 clocks
10100 = 29 clocks1
10101 = 30 clocks
10110 = 31 clocks1
10111 = 32 clocks
Burst type (BT) – Data burst ordering within a READ or WRITE burst access
0 = Nibble sequential
1 = Interleave
Burst length (BL) – Data burst size associated with each read or write access
00 = BL8 (fixed)
01 = BC4 or BL8 (on-the-fly)
10 = BC4 (fixed)
11 = Reserved
Notes:
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1. Not allowed when 1/4 rate gear-down mode is enabled.
2. If WR requirement exceeds 28 clocks or RTP exceeds 14 clocks, WR should be set to 28
clocks and RTP should be set to 14 clocks.
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Mode Register 0
Burst Length, Type, and Order
Accesses within a given burst may be programmed to sequential or interleaved order.
The ordering of accesses within a burst is determined by the burst length, burst type,
and the starting column address as shown in the following table. Burst length options
include fixed BC4, fixed BL8, and on-the-fly (OTF), which allows BC4 or BL8 to be selected coincidentally with the registration of a READ or WRITE command via A12/BC_n.
Table 8: Burst Type and Burst Order
Note 1 applies to the entire table
Starting
Column Address
Burst
READ/
(A[2, 1, 0])
Length
WRITE
BC4
READ
WRITE
BL8
READ
WRITE
Notes:
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Burst Type = Sequential
(Decimal)
Burst Type = Interleaved
(Decimal)
Notes
000
0, 1, 2, 3, T, T, T, T
0, 1, 2, 3, T, T, T, T
2, 3
001
1, 2, 3, 0, T, T, T, T
1, 0, 3, 2, T, T, T, T
2, 3
010
2, 3, 0, 1, T, T, T, T
2, 3, 0, 1, T, T, T, T
2, 3
011
3, 0, 1, 2, T, T, T, T
3, 2, 1, 0, T, T, T, T
2, 3
100
4, 5, 6, 7, T, T, T, T
4, 5, 6, 7, T, T, T, T
2, 3
101
5, 6, 7, 4, T, T, T, T
5, 4, 7, 6, T, T, T, T
2, 3
110
6, 7, 4, 5, T, T, T, T
6, 7, 4, 5, T, T, T, T
2, 3
111
7, 4, 5, 6, T, T, T, T
7, 6, 5, 4, T, T, T, T
2, 3
0, V, V
0, 1, 2, 3, X, X, X, X
0, 1, 2, 3, X, X, X, X
2, 3
1, V, V
4, 5, 6, 7, X, X, X, X
4, 5, 6, 7, X, X, X, X
2, 3
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
011
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
111
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
V, V, V
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
3
1. 0...7 bit number is the value of CA[2:0] that causes this bit to be the first read during a
burst.
2. When setting burst length to BC4 (fixed) in MR0, the internal WRITE operation starts
two clock cycles earlier than for the BL8 mode, meaning the starting point for tWR and
tWTR will be pulled in by two clocks. When setting burst length to OTF in MR0, the internal WRITE operation starts at the same time as a BL8 (even if BC4 was selected during
column time using A12/BC4_n) meaning that if the OTF MR0 setting is used, the starting
point for tWR and tWTR will not be pulled in by two clocks as described in the BC4
(fixed) case.
3. T = Output driver for data and strobes are in High-Z.
V = Valid logic level (0 or 1), but respective buffer input ignores level on input pins.
X = “Don’t Care.”
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Mode Register 0
CAS Latency
The CAS latency (CL) setting is defined in the MR0 Register Definition table. CAS latency is the delay, in clock cycles, between the internal READ command and the availability
of the first bit of output data. The device does not support half-clock latencies. The
overall read latency (RL) is defined as additive latency (AL) + CAS latency (CL): RL = AL +
CL.
Test Mode
The normal operating mode is selected by MR0[7] and all other bits set to the desired
values shown in the MR0 Register Definition table. Programming MR0[7] to a value of 1
places the device into a DRAM manufacturer-defined test mode to be used only by the
manufacturer, not by the end user. No operations or functionality is specified if MR0[7]
= 1.
Write Recovery(WR)/READ-to-PRECHARGE
The programmed write recovery (WR) value is used for the auto precharge feature along
with tRP to determine tDAL. WR for auto precharge (MIN) in clock cycles is calculated
by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer: WR (MIN)
cycles = roundup (tWR[ns]/tCK[ns]). The WR value must be programmed to be equal to
or larger than tWR (MIN). When both DM and write CRC are enabled in the mode register, the device calculates CRC before sending the write data into the array; tWR values
will change when enabled. If there is a CRC error, the device blocks the WRITE operation and discards the data.
Internal READ-to-PRECHARGE (RTP) command delay for auto precharge (MIN) in
clock cycles is calculated by dividing tRTP (in ns) by tCK (in ns) and rounding up to the
next integer: RTP (MIN) cycles = roundup (tRTP[ns]/tCK[ns]). The RTP value in the
mode register must be programmed to be equal to or larger than RTP (MIN). The programmed RTP value is used with tRP to determine the ACT timing to the same bank.
DLL RESET
The DLL reset bit is self-clearing, meaning that it returns to the value of 0 after the DLL
RESET function has been issued. After the DLL is enabled, a subsequent DLL RESET
should be applied. Any time the DLL RESET function is used, tDLLK must be met before
functions requiring the DLL can be used, such as READ commands or synchronous
ODT operations, for example,).
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Mode Register 1
Mode Register 1
Mode register 1 (MR1) controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die; only settings required for speed bin support are available. MR1 is written by issuing the MRS
command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR1 Register
Definition table.
Table 9: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9
bus
_n _n _n
Mode
register
21
20
19
18
Note:
17
–
–
–
13
12
11
10
9
A8
A7
A6
A5
A4
A3
A2
A1
A0
8
7
6
5
4
3
2
1
0
1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.
Table 10: MR1 Register Definition
Mode
Register
21
20:18
Description
RFU
0 = Must be programmed to 0
1 = Reserved
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
17
N/A on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
13
RFU
0 = Must be programmed to 0
1 = Reserved
12
Data output disable (Qoff) – Output buffer disable
0 = Enabled (normal operation)
1 = Disabled (both ODI and RTT)
11
Termination data strobe (TDQS) – Additional termination pins (x8 configuration only)
0 = TDQS disabled
1 = TDQS enabled
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Mode Register 1
Table 10: MR1 Register Definition (Continued)
Mode
Register
10, 9, 8
7
Description
Nominal ODT (RTT(NOM) – Data bus termination setting
000 = RTT(NOM) disabled
001 = RZQ/4 (60 ohm)
010 = RZQ/2 (120 ohm)
011 = RZQ/6 (40 ohm)
100 = RZQ/1 (240 ohm)
101 = RZQ/5 (48 ohm)
110 = RZQ/3 (80 ohm)
111 = RZQ/7 (34 ohm)
Write leveling (WL) – Write leveling mode
0 = Disabled (normal operation)
1 = Enabled (enter WL mode)
6, 5
RFU
0 = Must be programmed to 0
1 = Reserved
4, 3
Additive latency (AL) – Command additive latency setting
00 = 0 (AL disabled)
01 = CL - 11
10 = CL - 2
11 = Reserved
2, 1
Output driver impedance (ODI) – Output driver impedance setting
00 = RZQ/7 (34 ohm)
01 = RZQ/5 (48 ohm)
10 = Reserved (Although not JEDEC-defined and not tested, this setting will provide RZQ/6 or 40 ohm)
11 = Reserved
0
DLL enable – DLL enable feature
0 = DLL disabled
1 = DLL enabled (normal operation)
Note:
1. Not allowed when 1/4 rate gear-down mode is enabled.
DLL Enable/DLL Disable
The DLL must be enabled for normal operation and is required during power-up initialization and upon returning to normal operation after having the DLL disabled. During
normal operation (DLL enabled with MR1[0]) the DLL is automatically disabled when
entering the SELF REFRESH operation and is automatically re-enabled upon exit of the
SELF REFRESH operation. Any time the DLL is enabled and subsequently reset, tDLLK
clock cycles must occur before a READ or SYNCHRONOUS ODT command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tDQSCK, tAON,
or tAOF parameters.
During tDLLK, CKE must continuously be registered HIGH. The device does not require
DLL for any WRITE operation, except when R TT(WR) is enabled and the DLL is required
for proper ODT operation.
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Mode Register 1
The direct ODT feature is not supported during DLL off mode. The ODT resistors must
be disabled by continuously registering the ODT pin LOW and/or by programming the
RTT(NOM) bits MR1[9,6,2] = 000 via an MRS command during DLL off mode.
The dynamic ODT feature is not supported in DLL off mode; to disable dynamic ODT
externally, use the MRS command to set RTT(WR), MR2[10:9] = 00.
Output Driver Impedance Control
The output driver impedance of the device is selected by MR1[2,1], as shown in the MR1
Register Definition table.
ODT RTT(NOM) Values
The device is capable of providing three different termination values: RTT(Park), RTT(NOM),
and RTT(WR). The nominal termination value, R TT(NOM), is programmed in MR1. A separate value, RTT(WR), may be programmed in MR2 to enable a unique RTT value when
ODT is enabled during WRITE operations. The R TT(WR) value can be applied during
WRITE commands even when RTT(NOM) is disabled. A third RTT value, RTT(Park), is programed in MR5. RTT(Park) provides a termination value when the ODT signal is LOW.
Additive Latency
The ADDITIVE LATENCY (AL) operation is supported to make command and data
buses efficient for sustainable bandwidths in the device. In this operation, the device allows a READ or WRITE command (either with or without auto precharge) to be issued
immediately after the ACTIVATE command. The command is held for the time of AL before it is issued inside the device. READ latency (RL) is controlled by the sum of the AL
and CAS latency (CL) register settings. WRITE latency (WL) is controlled by the sum of
the AL and CAS WRITE latency (CWL) register settings.
Table 11: Additive Latency (AL) Settings
A4
A3
AL
0
0
0 (AL disabled)
0
1
CL - 1
1
0
CL - 2
1
1
Reserved
Note:
1. AL has a value of CL - 1 or CL - 2 based on the CL values programmed in the MR0 register.
Write Leveling
For better signal integrity, the device uses fly-by topology for the commands, addresses,
control signals, and clocks. Fly-by topology benefits from a reduced number of stubs
and their lengths, but it causes flight-time skew between clock and strobe at every
DRAM on the DIMM. This makes it difficult for the controller to maintain tDQSS, tDSS,
and tDSH specifications. Therefore, the device supports a write leveling feature that allows the controller to compensate for skew.
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Mode Register 1
Output Disable
The device outputs may be enabled/disabled by MR1[12] as shown in the MR1 Register
Definition table. When MR1[12] is enabled (MR1[12] = 1) all output pins (such as DQ
and DQS) are disconnected from the device, which removes any loading of the output
drivers. For example, this feature may be useful when measuring module power. For
normal operation, set MR1[12] to 0.
Termination Data Strobe
Termination data strobe (TDQS) is a feature of the x8 device and provides additional
termination resistance outputs that may be useful in some system configurations. Because this function is available only in a x8 configuration, it must be disabled for x4 and
x16 configurations.
While TDQS is not supported in x4 or x16 configurations, the same termination resistance function that is applied to the TDQS pins is applied to the DQS pins when enabled
via the mode register.
The TDQS, DBI, and DATA MASK (DM) functions share the same pin. When the TDQS
function is enabled via the mode register, the DM and DBI functions are not supported.
When the TDQS function is disabled, the DM and DBI functions can be enabled separately.
Table 12: TDQS Function Matrix
TDQS
Data Mask (DM)
WRITE DBI
READ DBI
Disabled
Enabled
Disabled
Enabled or disabled
Enabled
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Disabled
Enabled
Enabled or disabled
Disabled
Disabled
Enabled or disabled
Disabled
Disabled
Disabled
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Mode Register 2
Mode Register 2
Mode register 2 (MR2) controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die; only settings required for speed bin support are available. MR2 is written by issuing the MRS
command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR2 Register
Definition table.
Table 13: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9
bus
_n _n _n
Mode
register
21
20
19
18
Note:
17
–
–
–
13
12
11
10
9
A8
A7
A6
A5
A4
A3
A2
A1
A0
8
7
6
5
4
3
2
1
0
1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.
Table 14: MR2 Register Definition
Mode
Register Description
21
20:18
RFU
0 = Must be programmed to 0
1 = Reserved
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
17
N/A on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
13
RFU
0 = Must be programmed to 0
1 = Reserved
12
WRITE data bus CRC
0 = Disabled
1 = Enabled
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Mode Register 2
Table 14: MR2 Register Definition (Continued)
Mode
Register Description
11:9
Dynamic ODT (RTT(WR)) – Data bus termination setting during WRITEs
000 = RTT(WR) disabled (WRITE does not affect RTT value)
001 = RZQ/2 (120 ohm)
010 = RZQ/1 (240 ohm)
011 = High-Z
100 = RZQ/3 (80 ohm)
101 = Reserved
110 = Reserved
111 = Reserved
7:6
Low-power auto self refresh (LPASR) – Mode summary
00 = Manual mode - Normal operating temperature range (TC: 0°C–85°C)
01 = Manual mode - Reduced operating temperature range (TC: 0°C–45°C)
10 = Manual mode - Extended operating temperature range (TC: 0°C–95°C)
11 = ASR mode - Automatically switching among all modes
5:3
CAS WRITE latency (CWL) – Delay in clock cycles from the internal WRITE command to first data-in
1tCK WRITE preamble
000 = 9 (DDR4-1600)1
001 = 10 (DDR4-1866)
010 = 11 (DDR4-2133/1600)1
011 = 12 (DDR4-2400/1866)
100 = 14 (DDR4-2666/2133)
101 = 16 (DDR4-2933,3200/2400)
110 = 18 (DDR4-2666)
111 = 20 (DDR4-2933, 3200)
CAS WRITE latency (CWL) – Delay in clock cycles from the internal WRITE command to first data-in
2tCK WRITE preamble
000 = N/A
001 = N/A
010 = N/A
011 = N/A
100 = 14 (DDR4-2400)
101 = 16 (DDR4-2666/2400)
110 = 18 (DDR4-2933, 3200/2666)
111 = 20 (DDR4-2933, 3200)
8, 2
RFU
0 = Must be programmed to 0
1 = Reserved
1:0
RFU
0 = Must be programmed to 0
1 = Reserved
Note:
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Mode Register 2
CAS WRITE Latency
CAS WRITE latency (CWL) is defined by MR2[5:3] as shown in the MR2 Register Definition table. CWL is the delay, in clock cycles, between the internal WRITE command and
the availability of the first bit of input data. The device does not support any half-clock
latencies. The overall WRITE latency (WL) is defined as additive latency (AL) + parity latency (PL) + CAS WRITE latency (CWL): WL = AL +PL + CWL.
Low-Power Auto Self Refresh
Low-power auto self refresh (LPASR) is supported in the device. Applications requiring
SELF REFRESH operation over different temperature ranges can use this feature to optimize the IDD6 current for a given temperature range as specified in the MR2 Register
Definition table.
Dynamic ODT
In certain applications and to further enhance signal integrity on the data bus, it is desirable to change the termination strength of the device without issuing an MRS command. This may be done by configuring the dynamic ODT (R TT(WR)) settings in
MR2[11:9]. In write leveling mode, only RTT(NOM) is available.
Write Cyclic Redundancy Check Data Bus
The write cyclic redundancy check (CRC) data bus feature during writes has been added
to the device. When enabled via the mode register, the data transfer size goes from the
normal 8-bit (BL8) frame to a larger 10-bit UI frame, and the extra two UIs are used for
the CRC information.
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Mode Register 3
Mode Register 3
Mode register 3 (MR3) controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die; only settings required for speed bin support are available. MR3 is written by issuing the MRS
command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR3 Register
Definition table.
Table 15: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9
bus
_n _n _n
Mode
register
21
20
19
18
Note:
17
–
–
–
13
12
11
10
9
A8
A7
A6
A5
A4
A3
A2
A1
A0
8
7
6
5
4
3
2
1
0
1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.
Table 16: MR3 Register Definition
Mode
Register
21
20:18
Description
RFU
0 = Must be programmed to 0
1 = Reserved
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
17
N/A on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
13
RFU
0 = Must be programmed to 0
1 = Reserved
12:11
Multipurpose register (MPR) – Read format
00 = Serial
01 = Parallel
10 = Staggered
11 = Reserved
10:9
WRITE CMD latency when CRC/DM enabled
00 = 4CK (DDR4-1600)
01 = 5CK (DDR4-1866/2133/2400/2666)
10 = 6CK (DDR4-2933/3200)
11 = Reserved
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Mode Register 3
Table 16: MR3 Register Definition (Continued)
Mode
Register
8:6
Description
Fine granularity refresh mode
000 = Normal mode (fixed 1x)
001 = Fixed 2x
010 = Fixed 4x
011 = Reserved
100 = Reserved
101 = On-the-fly 1x/2x
110 = On-the-fly 1x/4x
111 = Reserved
5
Temperature sensor status
0 = Disabled
1 = Enabled
4
Per-DRAM addressability
0 = Normal operation (disabled)
1 = Enable
3
Gear-down mode – Ratio of internal clock to external data rate
0 = [1:1]; (1/2 rate data)
1 = [2:1]; (1/4 rate data)
2
Multipurpose register (MPR) access
0 = Normal operation
1 = Data flow from MPR
1:0
MPR page select
00 = Page 0
01 = Page 1
10 = Page 2
11 = Page 3 (restricted for DRAM manufacturer use only)
Multipurpose Register
The multipurpose register (MPR) is used for several features:
• Readout of the contents of the MRn registers
• WRITE and READ system patterns used for data bus calibration
• Readout of the error frame when the command address parity feature is enabled
To enable MPR, issue an MRS command to MR3[2] = 1. MR3[12:11] define the format of
read data from the MPR. Prior to issuing the MRS command, all banks must be in the
idle state (all banks precharged and tRP met). After MPR is enabled, any subsequent RD
or RDA commands will be redirected to a specific mode register.
The mode register location is specified with the READ command using address bits. The
MR is split into upper and lower halves to align with a burst length limitation of 8. Power-down mode, SELF REFRESH, and any other nonRD/RDA or nonWR/WRA commands are not allowed during MPR mode. The RESET function is supported during
MPR mode, which requires device re-initialization.
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Mode Register 3
WRITE Command Latency When CRC/DM is Enabled
The WRITE command latency (WCL) must be set when both write CRC and DM are enabled for write CRC persistent mode. This provides the extra time required when completing a WRITE burst when write CRC and DM are enabled. This means at data rates
less than or equal to 1600 MT/s then 4nCK is used, 5nCK or 6nCK are not allowed; at
data rates greater than 1600 MT/s and less than or equal to 2666 MT/s then 5nCK is
used, 4nCK or 6nCK are not allowed; and at data rates greater than 2666 MT/s and less
than or equal to 3200 MT/s then 6nCK is used; 4nCK or 5nCK are not allowed.
Fine Granularity Refresh Mode
This mode had been added to DDR4 to help combat the performance penalty due to
refresh lockout at high densities. Shortening tRFC and increasing cycle time allows more
accesses to the chip and can produce higher bandwidth.
Temperature Sensor Status
This mode directs the DRAM to update the temperature sensor status at MPR Page 2,
MPR0 [4,3]. The temperature sensor setting should be updated within 32ms; when an
MPR read of the temperature sensor status bits occurs, the temperature sensor status
should be no older than 32ms.
Per-DRAM Addressability
This mode allows commands to be masked on a per device basis providing any device
in a rank (devices sharing the same command and address signals) to be programmed
individually. As an example, this feature can be used to program different ODT or V REF
values on DRAM devices within a given rank.
Gear-Down Mode
The device defaults in 1/2 rate (1N) clock mode and uses a low frequency MRS command followed by a sync pulse to align the proper clock edge for operating the control
lines CS_n, CKE, and ODT when in 1/4 rate (2N) mode. For operation in 1/2 rate mode,
no MRS command or sync pulse is required.
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Mode Register 4
Mode Register 4
Mode register 4 (MR4) controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die; only settings required for speed bin support are available. MR4 is written by issuing the MRS
command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR4 Register
Definition table.
Table 17: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9
bus
_n _n _n
Mode
register
21
20
19
18
Note:
17
–
–
–
13
12
11
10
9
A8
A7
A6
A5
A4
A3
A2
A1
A0
8
7
6
5
4
3
2
1
0
1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET (MRS) command.
Table 18: MR4 Register Definition
Mode
Register
21
20:18
Description
RFU
0 = Must be programmed to 0
1 = Reserved
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
17
N/A on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
13
Hard Post Package Repair (hPPR mode)
0 = Disabled
1 = Enabled
12
WRITE preamble setting
0 = 1tCK toggle1
1 = 2tCK toggle
11
READ preamble setting
0 = 1tCK toggle1
1 = 2tCK toggle (When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value at
least 1 clock greater than the lowest CWL setting supported in the applicable tCK range.)
10
READ preamble training
0 = Disabled
1 = Enabled
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Mode Register 4
Table 18: MR4 Register Definition (Continued)
Mode
Register
9
8:6
Description
Self refresh abort mode
0 = Disabled
1 = Enabled
CMD (CAL) address latency
000 = 0 clocks (disabled)
001 =3 clocks1
010 = 4 clocks
011 = 5 clocks1
100 = 6 clocks
101 = 8 clocks
110 = Reserved
111 = Reserved
5
soft Post Package Repair (sPPR mode)
0 = Disabled
1 = Enabled
4
Internal VREF monitor
0 = Disabled
1 = Enabled
3
Temperature controlled refresh mode
0 = Disabled
1 = Enabled
2
Temperature controlled refresh range
0 = Normal temperature mode
1 = Extended temperature mode
1
Maximum power savings mode
0 = Normal operation
1 = Enabled
0
RFU
0 = Must be programmed to 0
1 = Reserved
Note:
1. Not allowed when 1/4 rate gear-down mode is enabled.
Hard Post Package Repair Mode
The hard post package repair (hPPR) mode feature is JEDEC optional for 4Gb DDR4
memories. Performing an MPR read to page 2 MPR0 [7] indicates whether hPPR mode is
available (A7 = 1) or not available (A7 = 0). hPPR mode provides a simple and easy repair
method of the device after placed in the system. One row per bank can be repaired. The
repair process is irrevocable so great care should be exercised when using.
Soft Post Package Repair Mode
The soft post package repair (sPPR) mode feature is JEDEC optional for 4Gb and 8Gb
DDR4 memories. Performing an MPR read to page 2 MPR0 [6] indicates whether sPPR
mode is available (A6 = 1) or not available (A6 = 0). sPPR mode provides a simple and
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Mode Register 4
easy repair method of the device after placed in the system. One row per bank can be
repaired. The repair process is revocable by either doing a reset or power-down or by
rewriting a new address in the same bank.
WRITE Preamble
Programmable WRITE preamble, tWPRE, can be set to 1tCK or 2tCK via the MR4 register.
The 1tCK setting is similar to DDR3. However, when operating in 2tCK WRITE preamble
mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL
setting supported in the applicable tCK range.
When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK
range. Some even settings will require addition of 2 clocks. If the alternate longer CWL
was used, the additional clocks will not be required.
READ Preamble
Programmable READ preamble tRPRE can be set to 1tCK or 2tCK via the MR4 register.
Both the 1tCK and 2tCK DDR4 preamble settings are different from that defined for the
DDR3 SDRAM. Both DDR4 READ preamble settings may require the memory controller
to train (or read level) its data strobe receivers using the READ preamble training.
READ Preamble Training
Programmable READ preamble training can be set to 1tCK or 2tCK. This mode can be
used by the memory controller to train or READ level its data strobe receivers.
Temperature-Controlled Refresh
When temperature-controlled refresh mode is enabled, the device may adjust the internal refresh period to be longer than tREFI of the normal temperature range by skipping
external REFRESH commands with the proper gear ratio. For example, the DRAM temperature sensor detected less than 45°C. Normal temperature mode covers the range of
0°C to 85°C, while the extended temperature range covers 0°C to 95°C.
Command Address Latency
COMMAND ADDRESS LATENCY (CAL) is a power savings feature and can be enabled
or disabled via the MRS setting. CAL is defined as the delay in clock cycles (tCAL) between a CS_n registered LOW and its corresponding registered command and address.
The value of CAL (in clocks) must be programmed into the mode register and is based
on the roundup (in clocks) of [tCK(ns)/tCAL(ns)].
Internal VREF Monitor
The device generates its own internal V REFDQ. This mode may be enabled during V REFDQ
training, and when enabled, V REF,time-short and V REF,time-long need to be increased by 10ns
if DQ0, DQ1, DQ2, or DQ3 have 0pF loading. An additional 15ns per pF of loading is also
needed.
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Mode Register 4
Maximum Power Savings Mode
This mode provides the lowest power mode where data retention is not required. When
the device is in the maximum power saving mode, it does not need to guarantee data
retention or respond to any external command (except the MAXIMUM POWER SAVING
MODE EXIT command and during the assertion of RESET_n signal LOW).
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Mode Register 5
Mode Register 5
Mode register 5 (MR5) controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die; only settings required for speed bin support are available. MR5 is written by issuing the MRS
command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR5 Register
Definition table.
Table 19: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9
bus
_n _n _n
Mode
register
21
20
19
18
Note:
17
–
–
–
13
12
11
10
9
A8
A7
A6
A5
A4
A3
A2
A1
A0
8
7
6
5
4
3
2
1
0
1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.
Table 20: MR5 Register Definition
Mode
Register
21
20:18
Description
RFU
0 = Must be programmed to 0
1 = Reserved
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
17
N/A on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
13
RFU
0 = Must be programmed to 0
1 = Reserved
12
Data bus inversion (DBI) – READ DBI enable
0 = Disabled
1 = Enabled
11
Data bus inversion (DBI) – WRITE DBI enable
0 = Disabled
1 = Enabled
10
Data mask (DM)
0 = Disabled
1 = Enabled
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Mode Register 5
Table 20: MR5 Register Definition (Continued)
Mode
Register
9
8:6
Description
CA parity persistent error mode
0 = Disabled
1 = Enabled
Parked ODT value (RTT(Park))
000 = RTT(Park) disabled
001 = RZQ/4 (60 ohm)
010 = RZQ/2 (120 ohm)
011 = RZQ/6 (40 ohm)
100 = RZQ/1 (240 ohm)
101 = RZQ/5 (48 ohm)
110 = RZQ/3 (80 ohm)
111 = RZQ/7 (34 ohm)
5
ODT input buffer for power-down
0 = Buffer enabled
1 = Buffer disabled
4
CA parity error status
0 = Clear
1 = Error
3
CRC error status
0 = Clear
1 = Error
2:0
CA parity latency mode
000 = Disable
001 = 4 clocks (DDR4-1600/1866/2133)
010 = 5 clocks (DDR4-2400/2666)1
011 = 6 clocks (DDR4-2933/3200)
100 = 8 clocks (DDR4-2933/3200)
101 = Reserved
110 = Reserved
111 = Reserved
Note:
1. Not allowed when 1/4 rate gear-down mode is enabled.
Data Bus Inversion
The DATA BUS INVERSION (DBI) function has been added to the device and is supported only for x8 and x16 configurations (x4 is not supported). The DBI function shares a
common pin with the DM and TDQS functions. The DBI function applies to both READ
and WRITE operations; Write DBI cannot be enabled at the same time the DM function
is enabled. Refer to the TDQS Function Matrix table for valid configurations for all three
functions (TDQS/DM/DBI). DBI is not allowed during MPR READ operation; during an
MPR read, the DRAM ignores the read DBI enable setting in MR5 bit A12. DBI is not allowed during MPR READ operations.
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Mode Register 5
Data Mask
The DATA MASK (DM) function, also described as a partial write, has been added to the
device and is supported only for x8 and x16 configurations (x4 is not supported). The
DM function shares a common pin with the DBI and TDQS functions. The DM function
applies only to WRITE operations and cannot be enabled at the same time the write DBI
function is enabled. Refer to the TDQS Function Matrix table for valid configurations for
all three functions (TDQS/DM/DBI).
CA Parity Persistent Error Mode
Normal CA parity mode (CA parity persistent mode disabled) no longer performs CA
parity checking while the parity error status bit remains set at 1. However, with CA parity persistent mode enabled, CA parity checking continues to be performed when the
parity error status bit is set to a 1.
ODT Input Buffer for Power-Down
This feature determines whether the ODT input buffer is on or off during power-down.
If the input buffer is configured to be on (enabled during power-down), the ODT input
signal must be at a valid logic level. If the input buffer is configured to be off (disabled
during power-down), the ODT input signal may be floating and the device does not provide RTT(NOM) termination. However, the device may provide RTT(Park) termination depending on the MR settings. This is primarily for additional power savings.
CA Parity Error Status
The device will set the error status bit to 1 upon detecting a parity error. The parity error
status bit remains set at 1 until the device controller clears it explicitly using an MRS
command.
CRC Error Status
The device will set the error status bit to 1 upon detecting a CRC error. The CRC error
status bit remains set at 1 until the device controller clears it explicitly using an MRS
command.
CA Parity Latency Mode
CA parity is enabled when a latency value, dependent on tCK, is programmed; this accounts for parity calculation delay internal to the device. The normal state of CA parity
is to be disabled. If CA parity is enabled, the device must ensure there are no parity errors before executing the command. CA parity signal (PAR) covers ACT_n, RAS_n/A16 ,
CAS_n/A15, WE_n/A14, and the address bus including bank address and bank group
bits. The control signals CKE, ODT, and CS_n are not included in the parity calculation.
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4Gb: x4, x8, x16 DDR4 SDRAM
Mode Register 6
Mode Register 6
Mode register 6 (MR6) controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die; only settings required for speed bin support are available. MR6 is written by issuing the MRS
command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR6 Register
Definition table.
Table 21: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9
bus
_n _n _n
Mode
register
21
20
19
18
Note:
17
–
–
–
13
12
11
10
9
A8
A7
A6
A5
A4
A3
A2
A1
A0
8
7
6
5
4
3
2
1
0
1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.
Table 22: MR6 Register Definition
Mode
Register
21
20:18
Description
RFU
0 = Must be programmed to 0
1 = Reserved
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
17
NA on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
13
RFU
0 = Must be programmed to 0
1 = Reserved
12:10
tCCD_L
000 = 4 clocks (≤1333 Mb/s)
001 = 5 clocks (>1333 Mb/s and ≤1866 Mb/s)
010 = 6 clocks (>1866 Mb/s and ≤2400 Mb/s)
011 = 7 clocks (>2400 Mb/s and ≤2666 Mb/s)
100 = 8 clocks (>2666 Mb/s and ≤3200 Mb/s)
101 = Reserved
110 = Reserved
111 = Reserved
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4Gb: x4, x8, x16 DDR4 SDRAM
Mode Register 6
Table 22: MR6 Register Definition (Continued)
Mode
Register
9, 8
Description
RFU
0 = Must be programmed to 0
1 = Reserved
7
VREF Calibration Enable
0 = Disable
1 = Enable
6
VREF Calibration Range
0 = Range 1
1 = Range 2
5:0
tCCD_L
VREF Calibration Value
See the VREFDQ Range and Levels table in the VREFDQ Calibration section
Programming
The device controller must program the correct tCCD_L value. tCCD_L will be programmed according to the value defined per operating frequency in the AC parameter table.
Although JEDEC specifies the larger of 5nCK or Xns, Micron's DRAM supports the larger
of 4nCK or Xns.
VREFDQ Calibration Enable
VREFDQ calibration is where the device internally generates its own V REFDQ to be used by
the DQ input receivers. The V REFDQ value will be output on any DQ of DQ[3:0] for evaluation only. The device controller is responsible for setting and calibrating the internal
VREFDQ level using an MRS protocol (adjust up, adjust down, and so on). It is assumed
that the controller will use a series of writes and reads in conduction with V REFDQ adjustments to optimize and verify the data eye. Enabling V REFDQ calibration must be used
whenever values are being written to the MR6[6:0] register.
VREFDQ Calibration Range
The device defines two V REFDQ calibration ranges: Range 1 and Range 2. Range 1 supports V REFDQ between 60% and 92% of V DDQ while Range 2 supports V REFDQ between
45% and 77% of V DDQ, as seen in V REFDQ Specification table. Although not a restriction,
Range 1 was targeted for module-based designs and Range 2 was added to target pointto-point designs.
VREFDQ Calibration Value
Fifty settings provide approximately 0.65% of granularity steps sizes for both Range 1
and Range 2 of V REFDQ, as seen in V REFDQ Range and Levels table in the V REFDQ Calibration section.
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Table 23: Truth Table – Command
A[13,11]
L
H
L
L
L
BG
BA
V
H
L
H
L
L
H
V
V
V
V
V
V
V
Self refresh entry
SRE
H
L
L
H
L
L
H
V
V
V
V
V
V
V
8, 9, 10
Self refresh exit
SRX
L
H
H
X
X
X
X
X
X
X
X
X
X
X
L
H
H
H
H
V
V
V
V
V
V
V
8, 9, 10,
11
Single-bank PRECHARGE
A[9:0]
A12/BC_n
H
H
A10/AP
BA [1:0]
H
REF
C[2:0]
BG[1:0]
MRS
REFRESH
Prev. Pres.
CKE CKE
ACT_n
MODE REGISTER SET
Function
CS_n
WE_n/A14
CAS_n/A15
RAS_n/A16
Notes 1–5 apply to the entire table; Note 6 applies to all READ/WRITE commands
Symbol
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Truth Tables
Notes
OP code
7
PRE
H
H
L
H
L
H
L
BG
BA
V
V
V
L
V
PREA
H
H
L
H
L
H
L
V
V
V
V
V
H
V
Reserved for future use
RFU
H
H
L
H
L
H
H
Bank ACTIVATE
ACT
H
H
L
L
BG
BA
V
WRITE
WR
H
H
L
H
H
L
L
BG
BA
V
V
V
L
CA
BC4OTF
WRS4
H
H
L
H
H
L
L
BG
BA
V
L
V
L
CA
BL8OTF
WRS8
H
H
L
H
H
L
L
BG
BA
V
H
V
L
CA
BL8 fixed, BC4 fixed
WRITE
with auto BC4OTF
precharge
BL8OTF
WRA
H
H
L
H
H
L
L
BG
BA
V
V
V
H
CA
WRAS4
H
H
L
H
H
L
L
BG
BA
V
L
V
H
CA
WRAS8
H
H
L
H
H
L
L
BG
BA
V
H
V
H
CA
RD
H
H
L
H
H
L
H
BG
BA
V
V
V
L
CA
BC4OTF
RDS4
H
H
L
H
H
L
H
BG
BA
V
L
V
L
CA
BL8OTF
RDS8
H
H
L
H
H
L
H
BG
BA
V
H
V
L
CA
BL8 fixed, BC4 fixed
READ
with auto BC4OTF
precharge
BL8OTF
RDA
H
H
L
H
H
L
H
BG
BA
V
V
V
H
CA
RDAS4
H
H
L
H
H
L
H
BG
BA
V
L
V
H
CA
RDAS8
H
H
L
H
H
L
H
BG
BA
V
H
V
H
CA
NO OPERATION
NOP
H
H
L
H
H
H
H
V
V
V
V
V
V
V
12
Device DESELECTED
DES
H
H
H
X
X
X
X
X
X
X
X
X
X
X
13
Power-down entry
PDE
H
L
H
X
X
X
X
X
X
X
X
X
X
X
10, 14
10, 14
PRECHARGE all banks
66
BL8 fixed, BC4 fixed
Row address (RA)
Row address (RA)
Power-down exit
PDX
L
H
H
X
X
X
X
X
X
X
X
X
X
X
ZQ CALIBRATION LONG
ZQCL
H
H
L
H
H
H
L
X
X
X
X
X
H
X
ZQ CALIBRATION SHORT
ZQCS
H
H
L
H
H
H
L
X
X
X
X
X
L
X
4Gb: x4, x8, x16 DDR4 SDRAM
Truth Tables
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READ
BL8 fixed, BC4 fixed
RFU
4Gb: x4, x8, x16 DDR4 SDRAM
Truth Tables
Notes:
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1. • BG = Bank group address
• BA = Bank address
• RA = Row address
• CA = Column address
• BC_n = Burst chop
• X = “Don’t Care”
• V = Valid
2. All DDR4 SDRAM commands are defined by states of CS_n, ACT_n, RAS_n/A16, CAS_n/
A15, WE_n/A14, and CKE at the rising edge of the clock. The MSB of BG, BA, RA, and CA
are device density- and configuration-dependent. When ACT_n = H, pins RAS_n/A16,
CAS_n/A15, and WE_n/A14 are used as command pins RAS_n, CAS_n, and WE_n, respectively. When ACT_n = L, pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are used as address
pins A16, A15, and A14, respectively.
3. RESET_n is enabled LOW and is used only for asynchronous reset and must be maintained HIGH during any function.
4. Bank group addresses (BG) and bank addresses (BA) determine which bank within a
bank group is being operated upon. For MRS commands, the BG and BA selects the specific mode register location.
5. V means HIGH or LOW (but a defined logic level), and X means either defined or undefined (such as floating) logic level.
6. READ or WRITE bursts cannot be terminated or interrupted, and fixed/on-the-fly (OTF)
BL will be defined by MRS.
7. During an MRS command, A17 is RFU and is device density- and configuration-dependent.
8. The state of ODT does not affect the states described in this table. The ODT function is
not available during self refresh.
9. VPP and VREF (VREFCA) must be maintained during SELF REFRESH operation.
10. Refer to the Truth Table – CKE table for more details about CKE transition.
11. Controller guarantees self refresh exit to be synchronous. DRAM implementation has
the choice of either synchronous or asynchronous.
12. The NO OPERATION (NOP) command may be used only when exiting maximum power
saving mode or when entering gear-down mode.
13. The NOP command may not be used in place of the DESELECT command.
14. The power-down mode does not perform any REFRESH operation.
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Truth Tables
Table 24: Truth Table – CKE
Notes 1–7, 9, and 20 apply to the entire table
CKE
Previous Cycle
(n - 1)
Present Cycle
(n)
Command (n)
Action (n)
Notes
L
L
X
Maintain power-down
8, 10, 11
L
H
DES
Power-down exit
8, 10, 12
Self refresh
L
L
X
Maintain self refresh
11, 13
L
H
DES
Self refresh exit
8, 13, 14, 15
Bank(s) active
H
L
DES
Active power-down entry
8, 10, 12, 16
Reading
H
L
DES
Power-down entry
8, 10, 12, 16, 17
Writing
H
L
DES
Power-down entry
8, 10, 12, 16, 17
Precharging
H
L
DES
Power-down entry
8, 10, 12, 16, 17
Refreshing
H
L
DES
Precharge power-down entry
8, 12
All banks idle
H
L
DES
Precharge power-down entry
8, 10, 12, 16, 18
H
L
REFRESH
Self refresh
16, 18, 19
Current State
Power-down
Notes:
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1. Current state is defined as the state of the DDR4 SDRAM immediately prior to clock
edge n.
2. CKE (n) is the logic state of CKE at clock edge n; CKE (n-1) was the state of CKE at the
previous clock edge.
3. COMMAND (n) is the command registered at clock edge n, and ACTION (n) is a result of
COMMAND (n); ODT is not included here.
4. All states and sequences not shown are illegal or reserved unless explicitly described
elsewhere in this document.
5. The state of ODT does not affect the states described in this table. The ODT function is
not available during self refresh.
6. During any CKE transition (registration of CKE H->L or CKE H->L), the CKE level must be
maintained until 1 nCK prior to tCKE (MIN) being satisfied (at which time CKE may transition again).
7. DESELECT and NOP are defined in the Truth Table – Command table.
8. For power-down entry and exit parameters, see the Power-Down Modes section.
9. CKE LOW is allowed only if tMRD and tMOD are satisfied.
10. The power-down mode does not perform any REFRESH operations.
11. X = "Don’t Care" (including floating around VREF) in self refresh and power-down. X also applies to address pins.
12. The DESELECT command is the only valid command for power-down entry and exit.
13. VPP and VREFCA must be maintained during SELF REFRESH operation.
14. On self refresh exit, the DESELECT command must be issued on every clock edge occurring during the tXS period. READ or ODT commands may be issued only after tXSDLL is
satisfied.
15. The DESELECT command is the only valid command for self refresh exit.
16. Self refresh cannot be entered during READ or WRITE operations. For a detailed list of
restrictions see the SELF REFRESH Operation and Power-Down Modes sections.
17. If all banks are closed at the conclusion of the READ, WRITE, or PRECHARGE command,
then precharge power-down is entered; otherwise, active power-down is entered.
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NOP Command
18. Idle state is defined as all banks are closed (tRP, tDAL, and so on, satisfied), no data
bursts are in progress, CKE is HIGH, and all timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, and so on), as well as all self refresh exit and power-down exit parameters are satisfied (tXS, tXP, tXSDLL, and so on).
19. Self refresh mode can be entered only from the all banks idle state.
20. For more details about all signals, see the Truth Table – Command table; must be a legal
command as defined in the table.
NOP Command
The NO OPERATION (NOP) command was originally used to instruct the selected
DDR4 SDRAM to perform a NOP (CS_n = LOW and ACT_n, RAS_n/A16, CAS_n/A15, and
WE_n/A14 = HIGH). This prevented unwanted commands from being registered during
idle or wait states. NOP command general support has been removed and the command should not be used unless specifically allowed, which is when exiting maximum
power-saving mode or when entering gear-down mode.
DESELECT Command
The deselect function (CS_n HIGH) prevents new commands from being executed;
therefore, with this command, the device is effectively deselected. Operations already in
progress are not affected.
DLL-Off Mode
DLL-off mode is entered by setting MR1 bit A0 to 0, which will disable the DLL for subsequent operations until the A0 bit is set back to 1. The MR1 A0 bit for DLL control can
be switched either during initialization or during self refresh mode. Refer to the Input
Clock Frequency Change section for more details.
The maximum clock frequency for DLL-off mode is specified by the parameter
tCKDLL_OFF. There is no minimum frequency limit besides the need to satisfy the refresh interval, tREFI.
Due to latency counter and timing restrictions, only one CL value and CWL value (in
MR0 and MR2 respectively) are supported. The DLL-off mode is only required to support setting both CL = 10 and CWL = 9.
DLL-off mode will affect the read data clock-to-data strobe relationship (tDQSCK), but
not the data strobe-to-data relationship (tDQSQ, tQH). Special attention is needed to
line up read data to the controller time domain.
Compared with DLL-on mode, where tDQSCK starts from the rising clock edge (AL +
CL) cycles after the READ command, the DLL-off mode tDQSCK starts (AL + CL - 1) cycles after the READ command. Another difference is that tDQSCK may not be small
compared to tCK (it might even be larger than tCK), and the difference between tDQSCK
(MIN) and tDQSCK (MAX) is significantly larger than in DLL-on mode. The tDQSCK
(DLL-off) values are vendor-specific.
The timing relations on DLL-off mode READ operation are shown in the following diagram, where CL = 10, AL = 0, and BL = 8.
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DLL-Off Mode
Figure 16: DLL-Off Mode Read Timing Operation
T0
CK_c
CK_t
Command
Address
((
))
((
))
((
))
RD
((
))
((
))
((
))
A RD
((
))
((
))
((
))
DQS_t, DQS_c
((
))
T1
T6
T7
T8
T9
DES
DES
DES
DES
DES
T10
T11
DES
T12
DES
T13
DES
DES
T14
DES
RL (DLL-on) = AL + CL = 10
CL = 10, AL = 0
(DLL-on)
tDQSCK
DQS_c
tDQSCK
(MIN)
((
))
DIN
b
(DLL-on)
DIN
b+1
(MAX)
DIN
b+2
DIN
b+3
DIN
b+4
DIN
b+5
DIN
b+6
DIN
b+7
RL (DLL-off) = AL + (CL - 1) = 9
CL = 10, AL = 0
DQS_t, DQS_c
(DLL-off)
DQS_c
(DLL-off)
DQS_t, DQS_c
(DLL-off)
DQS_c
(DLL-off)
tDQSCK
((
))
((
))
DIN
b
DIN
b+1
(DLL-off) MIN
DIN
b+2
DIN
b+3
tDQSCK
((
))
((
))
DIN
b
DIN
b+4
DIN
b+5
DIN
b+6
(DLL-off) MAX
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b+4
Transitioning data
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70
DIN
b+7
DIN
b+5
DIN
b+6
DIN
b+7
Don’t Care
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4Gb: x4, x8, x16 DDR4 SDRAM
DLL-On/Off Switching Procedures
DLL-On/Off Switching Procedures
The DLL-off mode is entered by setting MR1 bit A0 to 0; this will disable the DLL for
subsequent operations until the A0 bit is set back to 1.
DLL Switch Sequence from DLL-On to DLL-Off
To switch from DLL-on to DLL-off requires the frequency to be changed during self refresh, as outlined in the following procedure:
1. Starting from the idle state (all banks pre-charged, all timings fulfilled, and, to disable the DLL, the DRAM on-die termination resistors, RTT(NOM), must be in High-Z
before MRS to MR1.)
2. Set MR1 bit A0 to 1 to disable the DLL.
3. Wait tMOD.
4. Enter self refresh mode; wait until tCKSRE/tCKSRE_PAR is satisfied.
5. Change frequency, following the guidelines in the Input Clock Frequency Change
section.
6. Wait until a stable clock is available for at least tCKSRX at device inputs.
7. Starting with the SELF REFRESH EXIT command, CKE must continuously be registered HIGH until all tMOD timings from any MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers when self refresh
mode was entered, the ODT signal must continuously be registered LOW until all
tMOD timings from any MRS command are satisfied. If R
TT(NOM) was disabled in
the mode registers when self refresh mode was entered, the ODT signal is "Don't
Care."
8. Wait tXS_FAST, tXS_ABORT, or tXS, and then set mode registers with appropriate
values (an update of CL, CWL, and WR may be necessary; a ZQCL command can
also be issued after tXS_FAST).
• tXS_FAST: ZQCL, ZQCS, and MRS commands. For MRS commands, only CL and
WR/RTP registers in MR0, the CWL register in MR2, and gear-down mode in
MR3 may be accessed provided the device is not in per-DRAM addressability
mode. Access to other device mode registers must satisfy tXS timing.
• tXS_ABORT: If MR4 [9] is enabled, then the device aborts any ongoing refresh
and does not increment the refresh counter. The controller can issue a valid
command after a delay of tXS_ABORT. Upon exiting from self refresh, the device
requires a minimum of one extra REFRESH command before it is put back into
self refresh mode. This requirement remains the same regardless of the MRS bit
setting for self refresh abort.
t
• XS: ACT, PRE, PREA, REF, SRE, PDE, WR, WRS4, WRS8, WRA, WRAS4, WRAS8,
RD, RDS4, RDS8, RDA, RDAS4, and RDAS8.
9. Wait tMOD to complete.
The device is ready for the next command.
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4Gb: x4, x8, x16 DDR4 SDRAM
DLL-On/Off Switching Procedures
Figure 17: DLL Switch Sequence from DLL-On to DLL-Off
Ta
Tb0
Tb1
Tc
Td
Te0
Te1
Tf
Tg
Th
Valid
Valid
Valid
Valid 7
Valid 8
Valid 9
Valid
Valid
Valid
CK_c
CK_t
tCKSRE/tCKSRE_PAR
tIS
tCKSRX5
Note 4
tCPDED
CKE
tXS_FAST
Command
SRE3
MRS2
SRX6
DES
Address
tRP
tXS_ABORT
tIS
tXS
tCKESR/tCKESR_PAR
ODT
Valid
Enter self refresh
Exit self refresh
Time Break
Notes:
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1.
2.
3.
4.
5.
6.
7.
Don’t Care
Starting in the idle state. RTT in stable state.
Disable DLL by setting MR1 bit A0 to 0.
Enter SR.
Change frequency.
Clock must be stable tCKSRX.
Exit SR.
Update mode registers allowed with DLL-off settings met.
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DLL-On/Off Switching Procedures
DLL-Off to DLL-On Procedure
To switch from DLL-off to DLL-on (with required frequency change) during self refresh:
1. Starting from the idle state (all banks pre-charged, all timings fulfilled, and DRAM
ODT resistors (RTT(NOM)) must be in High-Z before self refresh mode is entered.)
2. Enter self refresh mode; wait until tCKSRE/tCKSRE_PAR are satisfied.
3. Change frequency (following the guidelines in the Input Clock Frequency Change
section).
4. Wait until a stable clock is available for at least tCKSRX at device inputs.
5. Starting with the SELF REFRESH EXIT command, CKE must continuously be registered HIGH until tDLLK timing from the subsequent DLL RESET command is satisfied. In addition, if any ODT features were enabled in the mode registers when
self refresh mode was entered, the ODT signal must continuously be registered
LOW or HIGH until tDLLK timing from the subsequent DLL RESET command is
satisfied. If RTT(NOM) disabled in the mode registers when self refresh mode was
entered, the ODT signal is "Don't Care."
6. Wait tXS or tXS_ABORT, depending on bit 9 in MR4, then set MR1 bit A0 to 0 to enable the DLL.
7. Wait tMRD, then set MR0 bit A8 to 1 to start DLL reset.
8. Wait tMRD, then set mode registers with appropriate values; an update of CL,
CWL, and WR may be necessary. After tMOD is satisfied from any proceeding MRS
command, a ZQCL command can also be issued during or after tDLLK.
9. Wait for tMOD to complete. Remember to wait tDLLK after DLL RESET before applying any command requiring a locked DLL. In addition, wait for tZQoper in case
a ZQCL command was issued.
The device is ready for the next command.
Figure 18: DLL Switch Sequence from DLL-Off to DLL-On
Ta
Tb0
Tb1
Tc
Td
Te0
Te1
Tf
Tg
Th
Valid
Valid
Valid
Valid 7
Valid 7
Valid 7
Valid
Valid
CK_c
CK_t
tCKSRE/tCKSRE_PAR
Note 1
tIS
tCKSRX5
Note 4
tCPDED
CKE
tXS_ABORT
Command
SRE3
MRS2
SRX6
DES
Address
tXS
tRP
tIS
tCKESR/tCKESR_PAR
ODT
Valid
Enter self refresh
Exit self refresh
Time Break
Notes:
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Valid
tMRD
Don’t Care
1. Starting in the idle state.
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4Gb: x4, x8, x16 DDR4 SDRAM
Input Clock Frequency Change
2.
3.
4.
5.
6.
7.
8.
Enter SR.
Change frequency.
Clock must be stable tCKSRX.
Exit SR.
Set DLL to on by setting MR1 to A0 = 0.
Update mode registers.
Issue any valid command.
Input Clock Frequency Change
After the device is initialized, it requires the clock to be stable during almost all states of
normal operation. This means that after the clock frequency has been set and is in the
stable state, the clock period is not allowed to deviate except for what is allowed by the
clock jitter and spread spectrum clocking (SSC) specifications. The input clock frequency can be changed from one stable clock rate to another stable clock rate only when in
self refresh mode. Outside of self refresh mode, it is illegal to change the clock frequency.
After the device has been successfully placed in self refresh mode and tCKSRE/
tCKSRE_PAR have been satisfied, the state of the clock becomes a "Don’t Care." Following a "Don’t Care," changing the clock frequency is permissible, provided the new clock
frequency is stable prior to tCKSRX. When entering and exiting self refresh mode for the
sole purpose of changing the clock frequency, the self refresh entry and exit specifications must still be met as outlined in SELF REFRESH Operation.
For the new clock frequency, additional MRS commands to MR0, MR2, MR3, MR4, MR5,
and MR6 may need to be issued to program appropriate CL, CWL, gear-down mode,
READ and WRITE preamble, Command Address Latency, and tCCD_L/tDLLK values.
When the clock rate is being increased (faster), the MR settings that require additional
clocks should be updated prior to the clock rate being increased. In particular, the PL
latency must be disabled when the clock rate changes, ie. while in self refresh mode. For
example, if changing the clock rate from DDR4-2133 to DDR4-2933 with CA parity
mode enabled, MR5[2:0] must first change from PL = 4 to PL = disable prior to PL = 6.
The correct procedure would be to (1) change PL = 4 to disable via MR5 [2:0], (2) enter
self refresh mode, (3) change clock rate from DDR4-2133 to DDR4-2933, (4) exit self refresh mode, (5) Enable CA parity mode setting PL = 6 vis MR5 [2:0].
If the MR settings that require additional clocks are updated after the clock rate has
been increased, for example. after exiting self refresh mode, the required MR settings
must be updated prior to removing the DRAM from the IDLE state, unless the DRAM is
RESET. If the DRAM leaves the IDLE state to enter self refresh mode or ZQ Calibration,
the updating of the required MR settings may be deferred to the next time the DRAM
enters the IDLE state.
If MR6 is issued prior to self refresh entry for new the tDLLK value, DLL will relock automatically at self refresh exit. However, if MR6 is issued after self refresh entry, MR0 must
be issued to reset the DLL.
The device input clock frequency can change only within the minimum and maximum
operating frequency specified for the particular speed grade. Any frequency change below the minimum operating frequency would require the use of DLL-on mode to DLLoff mode transition sequence (see DLL-On/Off Switching Procedures).
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Write Leveling
Write Leveling
For better signal integrity, DDR4 memory modules use fly-by topology for the commands, addresses, control signals, and clocks. Fly-by topology has benefits from the reduced number of stubs and their length, but it also causes flight-time skew between
clock and strobe at every DRAM on the DIMM. This makes it difficult for the controller
to maintain tDQSS, tDSS, and tDSH specifications. Therefore, the device supports a
write leveling feature to allow the controller to compensate for skew. This feature may
not be required under some system conditions, provided the host can maintain the
tDQSS, tDSS, and tDSH specifications.
The memory controller can use the write leveling feature and feedback from the device
to adjust the DQS (DQS_t, DQS_c) to CK (CK_t, CK_c) relationship. The memory controller involved in the leveling must have an adjustable delay setting on DQS to align the
rising edge of DQS with that of the clock at the DRAM pin. The DRAM asynchronously
feeds back CK, sampled with the rising edge of DQS, through the DQ bus. The controller
repeatedly delays DQS until a transition from 0 to 1 is detected. The DQS delay established though this exercise would ensure the tDQSS specification. Besides tDQSS, tDSS
and tDSH specifications also need to be fulfilled. One way to achieve this is to combine
the actual tDQSS in the application with an appropriate duty cycle and jitter on the DQS
signals. Depending on the actual tDQSS in the application, the actual values for tDQSL
and tDQSH may have to be better than the absolute limits provided in the AC Timing
Parameters section in order to satisfy tDSS and tDSH specifications. A conceptual timing of this scheme is shown below.
Figure 19: Write Leveling Concept, Example 1
T0
T1
T2
T3
T4
T6
T5
T7
CK_c
CK_t
Source
diff_DQS
Tn
Destination
T0
T1
T2
T3
T4
T5
T6
CK_c
CK_t
diff_DQS
DQ
diff_DQS
DQ
0
0 or 1
0
0
Push DQS to capture
the 0-1 transition
1
0 or 1
1
1
DQS driven by the controller during leveling mode must be terminated by the DRAM
based on the ranks populated. Similarly, the DQ bus driven by the DRAM must also be
terminated at the controller.
All data bits carry the leveling feedback to the controller across the DRAM configurations: x4, x8, and x16. On a x16 device, both byte lanes should be leveled independently.
Therefore, a separate feedback mechanism should be available for each byte lane. The
upper data bits should provide the feedback of the upper diff_DQS(diff_UDQS)-toclock relationship; the lower data bits would indicate the lower diff_DQS(diff_LDQS)to-clock relationship.
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Write Leveling
The figure below is another representative way to view the write leveling procedure. Although it shows the clock varying to a static strobe, this is for illustrative purpose only;
the clock does not actually change phase, the strobe is what actually varies. By issuing
multiple WL bursts, the DQS strobe can be varied to capture with fair accuracy the time
at which the clock edge arrives at the DRAM clock input buffer.
Figure 20: Write Leveling Concept, Example 2
tWLS
CK_c
1 1 1 111 1 1 11 1 1 1 1 1 1 1 1
CK_t
tWLH
CK_c
CK_t
0 000 000 000 000
tWLS tWLH
CK_c
CK_t
0 000 000
X XX X X X 11 1 1 1 1 1 1 1 1
DQS_t/
DQS_c
tWLO
DQ (CK 0 to 1)
DQ (CK 1 to 0)
DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode
The DRAM enters into write leveling mode if A7 in MR1 is HIGH. When leveling is finished, the DRAM exits write leveling mode if A7 in MR1 is LOW (see the MR Leveling
Procedures table). Note that in write leveling mode, only DQS terminations are activated and deactivated via the ODT pin, unlike normal operation (see DRAM DRAM TERMINATION Function in Leveling Mode table).
Table 25: MR Settings for Leveling Procedures
Function
MR1
Enable
Disable
Write leveling enable
A7
1
0
Output buffer mode (Q off)
A12
0
1
Table 26: DRAM TERMINATION Function in Leveling Mode
ODT Pin at DRAM
RTT(NOM) with ODT HIGH
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DQS_t/DQS_c Termination
DQ Termination
On
Off
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Write Leveling
Table 26: DRAM TERMINATION Function in Leveling Mode (Continued)
ODT Pin at DRAM
RTT(Park) with ODT LOW
DQS_t/DQS_c Termination
DQ Termination
On
Off
1. In write leveling mode, with the mode's output buffer either disabled (MR1[bit7] = 1
and MR1[bit12] = 1) or with its output buffer enabled (MR1[bit7] = 1 and MR1[bit12] =
0), all RTT(NOM) and RTT(Park) settings are supported.
2. RTT(WR) is not allowed in write leveling mode and must be set to disable prior to entering write leveling mode.
Notes:
Procedure Description
The memory controller initiates the leveling mode of all DRAM by setting bit 7 of MR1
to 1. When entering write leveling mode, the DQ pins are in undefined driving mode.
During write leveling mode, only the DESELECT command is supported, other than
MRS commands to change the Qoff bit (MR1[A12]) and to exit write leveling (MR1[A7]).
Upon exiting write leveling mode, the MRS command performing the exit (MR1[A7] = 0)
may also change the other MR1 bits. Because the controller levels one rank at a time,
the output of other ranks must be disabled by setting MR1 bit A12 to 1. The controller
may assert ODT after tMOD, at which time the DRAM is ready to accept the ODT signal,
unless DODTLon or DODTLoff have been altered (the ODT internal pipe delay is increased when increasing WRITE latency [WL] or READ latency [RL] by the previous MR
command), then ODT assertion should be delayed by DODTLon after tMOD is satisfied,
which means the delay is now tMOD + DODTLon.
The controller may drive DQS_t LOW and DQS_c HIGH after a delay of tWLDQSEN, at
which time the DRAM has applied ODT to these signals. After tDQSL and tWLMRD, the
controller provides a single DQS_t, DQS_c edge, which is used by the DRAM to sample
CK driven from the controller. tWLMRD (MAX) timing is controller dependent.
The DRAM samples CK status with the rising edge of DQS and provides feedback on all
the DQ bits asynchronously after tWLO timing. There is a DQ output uncertainty of
tWLOE defined to allow mismatch on DQ bits. The tWLOE period is defined from the
transition of the earliest DQ bit to the corresponding transition of the latest DQ bit.
There are no read strobes (DQS_t, DQS_c) needed for these DQs. The controller samples incoming DQ and either increments or decrements DQS delay setting and launches the next DQS pulse after some time, which is controller dependent. After a 0-to-1
transition is detected, the controller locks the DQS delay setting, and write leveling is
achieved for the device. The following figure shows the timing diagram and parameters
for the overall write leveling procedure.
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Write Leveling
Figure 21: Write Leveling Sequence (DQS Capturing CK LOW at T1 and CK HIGH at T2)
T1
tWLS
T2
tWLH
tWLS
tWLH
CK_c5
CK_t
Command
MRS2
DES3
DES
DES
DES
DES
DES
NOP DES
DES
DES
DES
DES
tMOD
ODT
tWLDQSEN
tDQSL6
tDQSH6
tDQSL6
tDQSH6
diff_DQS4
tWLMRD
tWLO
tWLO
Late Prime DQ1
tWLOE
Early Prime DQ1
tWLO
tWLOE
tWLO
Undefined Driving Mode
Notes:
Time Break
Don’t Care
1. The device drives leveling feedback on all DQs.
2. MRS: Load MR1 to enter write leveling mode.
3. diff_DQS is the differential data strobe. Timing reference points are the zero crossings.
DQS_t is shown with a solid line; DQS_c is shown with a dotted line.
4. CK_t is shown with a solid dark line; CK_c is shown with a dotted line.
5. DQS needs to fulfill minimum pulse width requirements, tDQSH (MIN) and tDQSL (MIN),
as defined for regular WRITEs; the maximum pulse width is system dependent.
6. tWLDQSEN must be satisfied following equation when using ODT:
• DLL = Enable, then tWLDQSEN > tMOD (MIN) + DODTLon + tADC
• DLL = Disable, then tWLDQSEN > tMOD (MIN) + tAONAS
Write Leveling Mode Exit
Write leveling mode should be exited as follows:
1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see
~Tc0). Note that from this point on, DQ pins are in undefined driving mode and
will remain undefined, until tMOD after the respective MR command (Te1).
2. Drive ODT pin LOW (tIS must be satisfied) and continue registering LOW (see
Tb0).
3. After RTT is switched off, disable write leveling mode via the MRS command (see
Tc2).
4. After tMOD is satisfied (Te1), any valid command can be registered. (MR commands can be issued after tMRD [Td1]).
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Write Leveling
Figure 22: Write Leveling Exit
CK_c
CK_t
Command
T0
T1
T2
DES
DES
DES
Ta0
Tb0
DES
DES
Tc0
Tc1
Tc2
DES
DES
DES
Td0
DES
Td1
Valid
Te0
DES
Te1
Valid
tMRD
MR1
Address
Valid
tIS
Valid
tMOD
ODT
tADC
ODTL (OFF)
RTT(DQS_t)
RTT(DQS_c)
RTT(Park)
tADC
DQS_t,
DQS_c
RTT(DQ)
(MIN)
RTT(NON)
(MAX)
tWLO
DQ1
result = 1
Undefined Driving Mode
Notes:
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Transitioning
Time Break
Don’t Care
1. The DQ result = 1 between Ta0 and Tc0 is a result of the DQS signals capturing CK_t
HIGH just after the T0 state.
2. See previous figure for specific tWLO timing.
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4Gb: x4, x8, x16 DDR4 SDRAM
Command Address Latency
Command Address Latency
DDR4 supports the command address latency (CAL) function as a power savings feature. This feature can be enabled or disabled via the MRS setting. CAL timing is defined
as the delay in clock cycles (tCAL) between a CS_n registered LOW and its corresponding registered command and address. The value of CAL in clocks must be programmed
into the mode register (see MR1 Register Definition table) and is based on the equation
tCK(ns)/tCAL(ns), rounded up in clocks.
Figure 23: CAL Timing Definition
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CS_n
CMD/ADDR
tCAL
CAL gives the DRAM time to enable the command and address receivers before a command is issued. After the command and the address are latched, the receivers can be
disabled if CS_n returns to HIGH. For consecutive commands, the DRAM will keep the
command and address input receivers enabled for the duration of the command sequence.
Figure 24: CAL Timing Example (Consecutive CS_n = LOW)
1
2
3
4
5
6
7
8
9
10
11
12
CLK
CS_n
CMD/ADDR
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Command Address Latency
When the CAL mode is enabled, additional time is required for the MRS command to
complete. The earliest the next valid command can be issued is tMOD_CAL, which
should be equal to tMOD + tCAL. The two following figures are examples.
Figure 25: CAL Enable Timing – tMOD_CAL
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Tb0
Tb1
Tb2
Tb3
Command
Valid
MRS
DES
DES
DES
DES
DES
DES
DES
Valid
Valid
Address
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CK_c
CK_t
CS_n
tCAL
tMOD_CAL
Settings
Old settings
Updating settings
New settings
Time Break
Note:
Don’t Care
1. CAL mode is enabled at T1.
Figure 26: tMOD_CAL, MRS to Valid Command Timing with CAL Enabled
T0
T1
Valid
DES
Ta0
Ta1
Ta2
Tb0
Tb1
Tb2
DES
MRS
DES
DES
DES
DES
Tc0
Tc1
Tc2
DES
Valid
Valid
Valid
Valid
Valid
CK_c
CK_t
Command
tCAL
Address
Valid
Valid
tCAL
Valid
Valid
Valid
Valid
Valid
Valid
CS_n
tMOD_CAL
Settings
Old settings
Updating settings
New settings
Time Break
Note:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Don’t Care
1. MRS at Ta1 may or may not modify CAL, tMOD_CAL is computed based on new tCAL setting if modified.
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Command Address Latency
When the CAL mode is enabled or being enabled, the earliest the next MRS command
can be issued is tMRD_CAL is equal to tMOD + tCAL. The two following figures are examples.
Figure 27: CAL Enabling MRS to Next MRS Command, tMRD_CAL
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Tb0
Valid
MRS
DES
DES
DES
DES
DES
DES
Tb1
Tb2
Tb3
DES
MRS
DES
Valid
Valid
Valid
CK_c
CK_t
Command
tCAL
Address
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CS_n
tMRD_CAL
Settings
Old settings
Updating settings
Updating settings
Time Break
Note:
Don’t Care
1. Command address latency mode is enabled at T1.
Figure 28: tMRD_CAL, Mode Register Cycle Time With CAL Enabled
7
7
7D
7D
7D
7E
7E
'(6
'(6
056
'(6
'(6
'(6
7E
7F
7F
7F
'(6
'(6
056
'(6
9DOLG
9DOLG
9DOLG
9DOLG
CK_c
CK_t
Command
9DOLG
W &$/
Address
9DOLG
W &$/
9DOLG
9DOLG
9DOLG
9DOLG
9DOLG
9DOLG
CS_n
W 05'B&$/
Settings
2OGVHWWLQJV
8SGDWLQJVHWWLQJV
1HZVHWWLQJV
7LPH%UHDN
Note:
'RQ¶W&DUH
1. MRS at Ta1 may or may not modify CAL, tMRD_CAL is computed based on new tCAL setting if modified.
CAL Examples: Consecutive READ BL8 with two different CALs and 1tCK preamble in
different bank group shown in the following figures.
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Figure 29: Consecutive READ BL8, CAL3, 1tCK Preamble, Different Bank Group
T0
T1
T2
T3
DES
READ
T4
T5
T6
T7
T13
T14
T15
DES
DES
READ
DES
DES
DES
T16
T17
T18
T19
T20
DES
DES
T21
T22
CK_c
CK_t
CS_n
t
t
CAL = 3
DES
Command
CAL = 3
DES
DES
DES
DES
DES
t
CCD_S = 4
Bank Group
Address
Address
BG a
BG b
Bank,
Col n
Bank,
Col b
tRPRE
tRPST
(1nCK)
DQS_t, DQS_c
DQ
DOUT
n
RL = 11
DOUT
n+1
DOUT
n+2
DOUT
n+4
DOUT
n+3
DOUT
n+5
DOUT
n+6
DOUT
n+7
DOUT
b
DOUT
b+7
DOUT
b+2
DOUT
b+3
DOUT
b+4
DOUT
b+5
DOUT
b+6
DOUT
b+7
RL = 11
Transitioning Data
Notes:
Don’t Care
83
BL = 8, AL = 0, CL = 11, CAL = 3, Preamble = 1tCK.
DOUT n = data-out from column n; DOUT b = data-out from column b.
DES commands are shown for ease of illustration, other commands may be valid at these times.
BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T3 and
T7.
5. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable.
6. Enabling CAL mode does not impact ODT control timings. ODT control timings should be maintained with the
same timing relationship relative to the command/address bus as when CAL is disabled.
1.
2.
3.
4.
&.BF
&.BW
7
7
7
7
7
7
'(6
'(6
5($'
'(6
7
7
7
7
7
7
7
7
7
'(6
'(6
5($'
'(6
'(6
'(6
'(6
'(6
'(6
7
7
7
7
'(6
'(6
'(6
&6BQ
W
&RPPDQG
'(6
&$/ W
&$/ W
&&'B6 %DQN*URXS
$GGUHVV
%*D
%*E
$GGUHVV
%DQN
&ROQ
%DQN
&ROE
W 535(
'(6
W 5367
Q&.
'46BW'46BF
'4
'287
Q
5/ '287
Q
'287
Q
'287
Q
'287
Q
'287
Q
'287
Q
'287
Q
'287
E
'287
E
'287
E
'287
E
'287
E
'287
E
'287
E
'287
E
5/ 7UDQVLWLRQLQJ'DWD
Notes:
1.
2.
3.
4.
'RQ¶W&DUH
BL = 8, AL = 0, CL = 11, CAL = 4, Preamble = 1tCK.
DOUT n = data-out from column n; DOUT b = data-out from column b.
DES commands are shown for ease of illustration, other commands may be valid at these times.
BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T4 and
T8.
4Gb: x4, x8, x16 DDR4 SDRAM
Command Address Latency
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Figure 30: Consecutive READ BL8, CAL4, 1tCK Preamble, Different Bank Group
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5. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable.
6. Enabling CAL mode does not impact ODT control timings. ODT control timings should be maintained with the
same timing relationship relative to the command/address bus as when CAL is disabled.
84
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Command Address Latency
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4Gb: x4, x8, x16 DDR4 SDRAM
Low-Power Auto Self Refresh Mode
Low-Power Auto Self Refresh Mode
An auto self refresh mode is provided for application ease. Auto self refresh mode is enabled by setting MR2[6] = 1 and MR2[7] = 1. The device will manage self refresh entry
over the supported temperature range of the DRAM. In this mode, the device will
change its self refresh rate as the DRAM operating temperature changes, going lower at
low temperatures and higher at high temperatures.
Manual Self Refresh Mode
If auto self refresh mode is not enabled, the low-power auto self refresh mode register
must be manually programmed to one of the three self refresh operating modes. This
mode provides the flexibility to select a fixed self refresh operating mode at the entry of
the self refresh, according to the system memory temperature conditions. The user is
responsible for maintaining the required memory temperature condition for the mode
selected during the SELF REFRESH operation. The user may change the selected mode
after exiting self refresh and before entering the next self refresh. If the temperature
condition is exceeded for the mode selected, there is a risk to data retention resulting in
loss of data.
Table 27: Auto Self Refresh Mode
MR2[7] MR2[6]
Low-Power
Auto Self Refresh
Mode
SELF REFRESH Operation
Operating Temperature
Range for Self Refresh Mode
(DRAM TCASE)
0
0
Normal
Fixed normal self refresh rate maintains data
retention at the normal operating temperature. User is required to ensure that 85°C
DRAM TCASE (MAX) is not exceeded to avoid
any risk of data loss.
0°C to 85°C
1
0
Extended
temperature
Fixed high self refresh rate optimizes data retention to support the extended temperature range.
0°C to 95°C
0
1
Reduced
temperature
Variable or fixed self refresh rate or any other DRAM power consumption reduction control for the reduced temperature range. User
is required to ensure 45°C DRAM TCASE
(MAX) is not exceeded to avoid any risk of
data loss.
0°C to 45°C
1
1
Auto self refresh
Auto self refresh mode enabled. Self refresh
power consumption and data retention are
optimized for any given operating temperature condition.
All of the above
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4Gb: x4, x8, x16 DDR4 SDRAM
Low-Power Auto Self Refresh Mode
Figure 31: Auto Self Refresh Ranges
IDD6
2x refresh rate
1x refresh rate
Extended
temperature
range
1/2x refresh rate
Reduced
temperature
range
25°C
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Normal
temperature
range
85°C
45°C
86
95°C
Tc
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4Gb: x4, x8, x16 DDR4 SDRAM
Multipurpose Register
Multipurpose Register
The MULTIPURPOSE REGISTER (MPR) function, MPR access mode, is used to write/
read specialized data to/from the DRAM. The MPR consists of four logical pages, MPR
Page 0 through MPR Page 3, with each page having four 8-bit registers, MPR0 through
MPR3. Page 0 can be read by any of three readout modes (serial, parallel, or staggered)
while Pages 1, 2, and 3 can be read by only the serial readout mode. Page 3 is for DRAM
vendor use only. MPR mode enable and page selection is done with MRS commands.
Data bus inversion (DBI) is not allowed during MPR READ operation.
Once the MPR access mode is enabled (MR3[2] = 1), only the following commands are
allowed: MRS, RD, RDA WR, WRA, DES, REF, and RESET; RDA/WRA have the same functionality as RD/WR which means the auto precharge part of RDA/WRA is ignored. Power-down mode and SELF REFRESH command are not allowed during MPR enable
mode. No other command can be issued within tRFC after a REF command has been
issued; 1x refresh (only) is to be used during MPR access mode. While in MPR access
mode, MPR read or write sequences must be completed prior to a REFRESH command.
Figure 32: MPR Block Diagram
Memory core
(all banks precharged)
Four multipurpose registers (pages),
each with four 8-bit registers:
MR3 [2] = 1
Data patterns (RD/WR)
Error log (RD)
Mode registers (RD)
DRAM manufacture only (RD)
flow
data
PR
M
DQ,s DM_n/DBI_n, DQS_t, DQS_c
Table 28: MR3 Setting for the MPR Access Mode
Address
Operation Mode
A[12:11]
MPR data read format
A2
MPR access
A[1:0]
MPR page selection
Description
00 = Serial ........... 01 = Parallel
10 = Staggered .... 11 = Reserved
0 = Standard operation (MPR not enabled)
1 = MPR data flow enabled
00 = Page 0 .... 01 = Page 1
10 = Page 2 .... 11 = Page 3
Table 29: DRAM Address to MPR UI Translation
MPR Location
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
DRAM address – Ax
A7
A6
A5
A4
A3
A2
A1
A0
MPR UI – UIx
UI0
UI1
UI2
UI3
UI4
UI5
UI6
UI7
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4Gb: x4, x8, x16 DDR4 SDRAM
Multipurpose Register
Table 30: MPR Page and MPRx Definitions
Address
MPR Location
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Note
Read/
Write
(default
value listed)
MPR Page 0 – Read or Write (Data Patterns)
BA[1:0]
00 = MPR0
0
1
0
1
0
1
0
1
01 = MPR1
0
0
1
1
0
0
1
1
10 = MPR2
0
0
0
0
1
1
1
1
11 = MPR3
0
0
0
0
0
0
0
0
MPR Page 1 – Read-only (Error Log)
BA[1:0]
00 = MPR0
01 = MPR1
A7
A6
CAS_n/A WE_n/A1
15
4
10 = MPR2
PAR
ACT_n
11 = MPR3
CRC error status
CA parity error
status
A5
A4
A3
A2
A1
A0
A13
A12
A11
A10
A9
A8
BG1
BG0
BA1
BA0
A17
RAS_n/A
16
C2
C1
C0
CA parity latency: [5] =
MR5[2], [4] = MR5[1], [3] =
MR5[0]
Read-only
MPR Page 2 – Read-only (MRS Readout)
BA[1:0]
00 = MPR0
hPPR
support
01 = MPR1
VREFDQ
trainging
range
MR6[6]
10 = MPR2
11 = MPR3
sPPR
support
RTT(WR)
MR2[11]
Temperature sensor status2
CRC write
enable
MR2[12]
RTT(WR) MR2[10:9]
VREFDQ training value: [6:1] = MR6[5:0]
CAS latency: [7:3] = MR0[6:4,2,12]
RTT(NOM): [7:5] = MR1[10:8]
Read-only
Geardown
enable
MR3[3]
CAS write latency [2:0] =
MR2[5:3]
RTT(Park): [4:2] = MR5[8:6]
RON: [1:0] =
MR2[2:1]
MPR Page 3 – Read-only (Restricted, except for MPR3 [3:0])
BA[1:0]
00 = MPR0
DC
DC
DC
DC
DC
DC
DC
DC
01 = MPR1
DC
DC
DC
DC
DC
DC
DC
DC
10 = MPR2
DC
DC
DC
DC
DC
DC
DC
DC
11 = MPR3
DC
DC
DC
DC
MAC
MAC
MAC
MAC
Notes:
Read-only
1. DC = "Don't Care"
2. MPR[4:3] 00 = Sub 1X refresh; MPR[4:3] 01 = 1X refresh; MPR[4:3] 10 = 2X refresh;
MPR[4:3] 11 = Reserved
MPR Reads
MPR reads are supported using BL8 and BC4 modes. Burst length on-the-fly is not supported for MPR reads. Data bus inversion (DBI) is not allowed during MPR READ operation; the device will ignore the Read DBI enable setting in MR5 [12] when in MPR mode.
READ commands for BC4 are supported with a starting column address of A[2:0] = 000
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4Gb: x4, x8, x16 DDR4 SDRAM
Multipurpose Register
or 100. After power-up, the content of MPR Page 0 has the default values, which are defined in Table 30. MPR page 0 can be rewritten via an MPR WRITE command. The device maintains the default values unless it is rewritten by the DRAM controller. If the
DRAM controller does overwrite the default values (Page 0 only), the device will maintain the new values unless re-initialized or there is power loss.
Timing in MPR mode:
• Reads (back-to-back) from Page 0 may use tCCD_S or tCCD_L timing between READ
commands
• Reads (back-to-back) from Pages 1, 2, or 3 may not use tCCD_S timing between READ
commands; tCCD_L must be used for timing between READ commands
The following steps are required to use the MPR to read out the contents of a mode register (MPR Page x, MPRy).
1. The DLL must be locked if enabled.
2. Precharge all; wait until tRP is satisfied.
3. MRS command to MR3[2] = 1 (Enable MPR data flow), MR3[12:11] = MPR read format, and MR3[1:0] MPR page.
a. MR3[12:11] MPR read format:
1. 00 = Serial read format
2. 01 = Parallel read format
3. 10 = staggered read format
4. 11 = RFU
b. MR3[1:0] MPR page:
1. 00 = MPR Page 0
2. 01 = MPR Page 1
3. 10 = MPR Page 2
4. 11 = MPR Page 3
4. tMRD and tMOD must be satisfied.
5. Redirect all subsequent READ commands to specific MPRx location.
6. Issue RD or RDA command.
a. BA1 and BA0 indicate MPRx location:
1. 00 = MPR0
2. 01 = MPR1
3. 10 = MPR2
4. 11 = MPR3
b. A12/BC = 0 or 1; BL8 or BC4 fixed-only, BC4 OTF not supported.
1. If BL = 8 and MR0 A[1:0] = 01, A12/BC must be set to 1 during MPR
READ commands.
c. A2 = burst-type dependant:
1. BL8: A2 = 0 with burst order fixed at 0, 1, 2, 3, 4, 5, 6, 7
2. BL8: A2 = 1 not allowed
3. BC4: A2 = 0 with burst order fixed at 0, 1, 2, 3, T, T, T, T
4. BC4: A2 = 1 with burst order fixed at 4, 5, 6, 7, T, T, T, T
d. A[1:0] = 00, data burst is fixed nibble start at 00.
e. Remaining address inputs, including A10, and BG1 and BG0 are "Don’t
Care."
7. After RL = AL + CL, DRAM bursts data from MPRx location; MPR readout format
determined by MR3[A12,11,1,0].
8. Steps 5 through 7 may be repeated to read additional MPRx locations.
9. After the last MPRx READ burst, tMPRR must be satisfied prior to exiting.
10. Issue MRS command to exit MPR mode; MR3[2] = 0.
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4Gb: x4, x8, x16 DDR4 SDRAM
Multipurpose Register
11. After the tMOD sequence is completed, the DRAM is ready for normal operation
from the core (such as ACT).
MPR Readout Format
The MPR read data format can be set to three different settings: serial, parallel, and
staggered.
MPR Readout Serial Format
The serial format is required when enabling the MPR function to read out the contents
of an MRx, temperature sensor status, and the command address parity error frame.
However, data bus calibration locations (four 8-bit registers) can be programmed to
read out any of the three formats. The DRAM is required to drive associated strobes
with the read data similar to normal operation (such as using MRS preamble settings).
Serial format implies that the same pattern is returned on all DQ lanes, as shown the
table below, which uses values programmed into the MPR via [7:0] as 0111 1111.
Table 31: MPR Readout Serial Format
Serial
UI0
UI1
UI2
UI3
UI4
UI5
UI6
UI7
DQ0
0
1
1
1
1
1
1
1
DQ1
0
1
1
1
1
1
1
1
DQ2
0
1
1
1
1
1
1
1
DQ3
0
1
1
1
1
1
1
1
DQ0
0
1
1
1
1
1
1
1
DQ1
0
1
1
1
1
1
1
1
DQ2
0
1
1
1
1
1
1
1
DQ3
0
1
1
1
1
1
1
1
DQ4
0
1
1
1
1
1
1
1
DQ5
0
1
1
1
1
1
1
1
DQ6
0
1
1
1
1
1
1
1
DQ7
0
1
1
1
1
1
1
1
DQ0
0
1
1
1
1
1
1
1
DQ1
0
1
1
1
1
1
1
1
DQ2
0
1
1
1
1
1
1
1
DQ3
0
1
1
1
1
1
1
1
DQ4
0
1
1
1
1
1
1
1
DQ5
0
1
1
1
1
1
1
1
DQ6
0
1
1
1
1
1
1
1
DQ7
0
1
1
1
1
1
1
1
DQ8
0
1
1
1
1
1
1
1
x4 Device
x8 Device
x16 Device
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4Gb: x4, x8, x16 DDR4 SDRAM
Multipurpose Register
Table 31: MPR Readout Serial Format (Continued)
Serial
UI0
UI1
UI2
UI3
UI4
UI5
UI6
UI7
DQ9
0
1
1
1
1
1
1
1
DQ10
0
1
1
1
1
1
1
1
DQ11
0
1
1
1
1
1
1
1
DQ12
0
1
1
1
1
1
1
1
DQ13
0
1
1
1
1
1
1
1
DQ14
0
1
1
1
1
1
1
1
DQ15
0
1
1
1
1
1
1
1
MPR Readout Parallel Format
Parallel format implies that the MPR data is returned in the first data UI and then repeated in the remaining UIs of the burst, as shown in the table below. Data pattern location
0 is the only location used for the parallel format. RD/RDA from data pattern locations
1, 2, and 3 are not allowed with parallel data return mode. In this example, the pattern
programmed in the data pattern location 0 is 0111 1111. The x4 configuration only outputs the first four bits (0111 in this example). For the x16 configuration, the same pattern is repeated on both the upper and lower bytes.
Table 32: MPR Readout – Parallel Format
Parallel
UI0
UI1
UI2
UI3
UI4
UI5
UI6
UI7
DQ0
0
0
0
0
0
0
0
0
DQ1
1
1
1
1
1
1
1
1
DQ2
1
1
1
1
1
1
1
1
DQ3
1
1
1
1
1
1
1
1
DQ0
0
0
0
0
0
0
0
0
DQ1
1
1
1
1
1
1
1
1
DQ2
1
1
1
1
1
1
1
1
DQ3
1
1
1
1
1
1
1
1
DQ4
1
1
1
1
1
1
1
1
DQ5
1
1
1
1
1
1
1
1
DQ6
1
1
1
1
1
1
1
1
DQ7
1
1
1
1
1
1
1
1
DQ0
0
0
0
0
0
0
0
0
DQ1
1
1
1
1
1
1
1
1
DQ2
1
1
1
1
1
1
1
1
DQ3
1
1
1
1
1
1
1
1
DQ4
1
1
1
1
1
1
1
1
x4 Device
x8 Device
x16 Device
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4Gb: x4, x8, x16 DDR4 SDRAM
Multipurpose Register
Table 32: MPR Readout – Parallel Format (Continued)
Parallel
UI0
UI1
UI2
UI3
UI4
UI5
UI6
UI7
DQ5
1
1
1
1
1
1
1
1
DQ6
1
1
1
1
1
1
1
1
DQ7
1
1
1
1
1
1
1
1
DQ8
0
0
0
0
0
0
0
0
DQ9
1
1
1
1
1
1
1
1
DQ10
1
1
1
1
1
1
1
1
DQ11
1
1
1
1
1
1
1
1
DQ12
1
1
1
1
1
1
1
1
DQ13
1
1
1
1
1
1
1
1
DQ14
1
1
1
1
1
1
1
1
DQ15
1
1
1
1
1
1
1
1
MPR Readout Staggered Format
Staggered format of data return is defined as the staggering of the MPR data across the
lanes. In this mode, an RD/RDA command is issued to a specific data pattern location
and then the data is returned on the DQ from each of the different data pattern locations. For the x4 configuration, an RD/RDA to data pattern location 0 will result in data
from location 0 being driven on DQ0, data from location 1 being driven on DQ1, data
from location 2 being driven on DQ2, and so on, as shown below. Similarly, an RD/RDA
command to data pattern location 1 will result in data from location 1 being driven on
DQ0, data from location 2 being driven on DQ1, data from location 3 being driven on
DQ2, and so on. Examples of different starting locations are also shown.
Table 33: MPR Readout Staggered Format, x4
x4 READ MPR0 Command
x4 READ MPR1 Command
x4 READ MPR2 Command x4 READ MPR3 Command
Stagger
UI[7:0]
Stagger
UI[7:0]
Stagger
UI[7:0]
Stagger
UI[7:0]
DQ0
MPR0
DQ0
MPR1
DQ0
MPR2
DQ0
MPR3
DQ1
MPR1
DQ1
MPR2
DQ1
MPR3
DQ1
MPR0
DQ2
MPR2
DQ2
MPR3
DQ2
MPR0
DQ2
MPR1
DQ3
MPR3
DQ3
MPR0
DQ3
MPR1
DQ3
MPR2
It is expected that the DRAM can respond to back-to-back RD/RDA commands to the
MPR for all DDR4 frequencies so that a sequence (such as the one that follows) can be
created on the data bus with no bubbles or clocks between read data. In this case, the
system memory controller issues a sequence of RD(MPR0), RD(MPR1), RD(MPR2),
RD(MPR3), RD(MPR0), RD(MPR1), RD(MPR2), and RD(MPR3).
Table 34: MPR Readout Staggered Format, x4 – Consecutive READs
Stagger
UI[7:0]
UI[15:8]
UI[23:16]
UI[31:24]
UI[39:32]
UI[47:40]
UI[55:48]
UI[63:56]
DQ0
MPR0
MPR1
MPR2
MPR3
MPR0
MPR1
MPR2
MPR3
DQ1
MPR1
MPR2
MPR3
MPR0
MPR1
MPR2
MPR3
MPR0
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4Gb: x4, x8, x16 DDR4 SDRAM
Multipurpose Register
Table 34: MPR Readout Staggered Format, x4 – Consecutive READs (Continued)
Stagger
UI[7:0]
UI[15:8]
UI[23:16]
UI[31:24]
UI[39:32]
UI[47:40]
UI[55:48]
UI[63:56]
DQ2
MPR2
MPR3
MPR0
MPR1
MPR2
MPR3
MPR0
MPR1
DQ3
MPR3
MPR0
MPR1
MPR2
MPR3
MPR0
MPR1
MPR2
For the x8 configuration, the same pattern is repeated on the lower nibble as on the upper nibble. READs to other MPR data pattern locations follow the same format as the x4
case. A read example to MPR0 for x8 and x16 configurations is shown below.
Table 35: MPR Readout Staggered Format, x8 and x16
x8 READ MPR0 Command
x16 READ MPR0 Command
x16 READ MPR0 Command
Stagger
UI[7:0]
Stagger
UI[7:0]
Stagger
UI[7:0]
DQ0
MPR0
DQ0
MPR0
DQ8
MPR0
DQ1
MPR1
DQ1
MPR1
DQ9
MPR1
DQ2
MPR2
DQ2
MPR2
DQ10
MPR2
DQ3
MPR3
DQ3
MPR3
DQ11
MPR3
DQ4
MPR0
DQ4
MPR0
DQ12
MPR0
DQ5
MPR1
DQ5
MPR1
DQ13
MPR1
DQ6
MPR2
DQ6
MPR2
DQ14
MPR2
DQ7
MPR3
DQ7
MPR3
DQ15
MPR3
MPR READ Waveforms
The following waveforms show MPR read accesses.
Figure 33: MPR READ Timing
T0
Ta0
Ta1
Tb0
Tc0
Tc1
Tc2
Tc3
Td0
Td1
DES
READ
DES
DES
DES
DES
DES
DES
Te0
Tf0
Tf1
Valid 4
DES
Valid
Valid
CK_c
CK_t
MPE Enable
Command
tRP
Address
Valid
MPE Disable
MRS1
PREA
Valid
MRS3
tMPRR
tMOD
Valid
Add2
Valid
Valid
Valid
Valid
Valid
Valid
tMOD
Valid
CKE
PL5 + AL + CL
DQS_t,
DQS_c
DQ
UI0
UI1
UI2
UI5
UI6
UI7
Time Break
Notes:
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Don’t Care
1. tCCD_S = 4tCK, Read Preamble = 1tCK.
2. Address setting:
A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here)
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4Gb: x4, x8, x16 DDR4 SDRAM
Multipurpose Register
A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7)
BA1 and BA0 indicate the MPR location
A10 and other address pins are "Don’t Care," including BG1 and BG0. A12 is "Don’t
Care" when MR0 A[1:0] = 00 or 10 and must be 1b when MR0 A[1:0] = 01
3. Multipurpose registers read/write disable (MR3 A2 = 0).
4. Continue with regular DRAM command.
5. Parity latency (PL) is added to data output delay when CA parity latency mode is enabled.
Figure 34: MPR Back-to-Back READ Timing
T0
T1
T2
DES
READ
DES
T3
T4
T5
T6
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Ta9
Ta10
DES
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CK_c
CK_t
Command
tCCD_S1
Address
Valid
Add2
Valid
Add2
CKE
PL3 + AL + CL
DQS_t,
DQS_c
DQ
UI0
UI1
UI2
UI3
UI0
UI1
UI2
UI3
UI4
UI5
UI6
UI7
UI0
UI1
UI2
UI3
UI0
UI1
UI2
UI3
UI4
UI5
UI6
UI7
DQS_t,
DQS_c
DQ
Time Break
Notes:
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Don’t Care
1. tCCD_S = 4tCK, Read Preamble = 1tCK.
2. Address setting:
A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here)
A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7; for BC = 4, burst order is
fixed at 0, 1, 2, 3, T, T, T, T)
BA1 and BA0 indicate the MPR location
A10 and other address pins are "Don’t Care," including BG1 and BG0. A12 is "Don’t
Care" when MR0 A[1:0] = 00 or 10 and must be 1b when MR0 A[1:0] = 01
3. Parity latency (PL) is added to data output delay when CA parity latency mode is enabled.
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4Gb: x4, x8, x16 DDR4 SDRAM
Multipurpose Register
Figure 35: MPR READ-to-WRITE Timing
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
Tb0
Tb1
Tb2
WRITE
DES
DES
Add2
Valid
Valid
CK_c
CK_t
Command
tMPRR
Address
Add1
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CKE
PL3 + AL + CL
DQS_t,
DQS_c
DQ
UI0
UI1
UI2
UI3
UI4
UI5
UI6
UI7
Time Break
Notes:
Don’t Care
1. Address setting:
A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here)
A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7)
BA1 and BA0 indicate the MPR location
A10 and other address pins are "Don’t Care," including BG1 and BG0. A12 is "Don’t
Care" when MR0 A[1:0] = 00 and must be 1b when MR0 A[1:0] = 01
2. Address setting:
BA1 and BA0 indicate the MPR location
A[7:0] = data for MPR
BA1 and BA0 indicate the MPR location
A10 and other address pins are "Don’t Care"
3. Parity latency (PL) is added to data output delay when CA parity latency mode is enabled.
MPR Writes
MPR access mode allows 8-bit writes to the MPR Page 0 using the address bus A[7:0].
Data bus inversion (DBI) is not allowed during MPR WRITE operation. The DRAM will
maintain the new written values unless re-initialized or there is power loss.
The following steps are required to use the MPR to write to mode register MPR Page 0.
1. The DLL must be locked if enabled.
2. Precharge all; wait until tRP is satisfied.
3. MRS command to MR3[2] = 1 (enable MPR data flow) and MR3[1:0] = 00 (MPR
Page 0); writes to 01, 10, and 11 are not allowed.
4. tMRD and tMOD must be satisfied.
5. Redirect all subsequent WRITE commands to specific MPRx location.
6. Issue WR or WRA command:
a. BA1 and BA0 indicate MPRx location
1. 00 = MPR0
2. 01 = MPR1
3. 10 = MPR2
4. 11 = MPR3
b. A[7:0] = data for MPR Page 0, mapped A[7:0] to UI[7:0].
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4Gb: x4, x8, x16 DDR4 SDRAM
Multipurpose Register
7.
8.
9.
10.
11.
c. Remaining address inputs, including A10, and BG1 and BG0 are "Don’t
Care."
tWR_MPR must be satisfied to complete MPR WRITE.
Steps 5 through 7 may be repeated to write additional MPRx locations.
After the last MPRx WRITE, tMPRR must be satisfied prior to exiting.
Issue MRS command to exit MPR mode; MR3[2] = 0.
When the tMOD sequence is completed, the DRAM is ready for normal operation
from the core (such as ACT).
MPR WRITE Waveforms
The following waveforms show MPR write accesses.
Figure 36: MPR WRITE and WRITE-to-READ Timing
T0
Ta0
Ta1
Tb0
Tc0
Tc1
Tc2
Td0
Td1
Td2
Td3
Td4
Td5
DES
WRITE
DES
DES
READ
DES
DES
DES
DES
DES
DES
Valid
Add
Valid
Valid
Valid
Add2
Valid
Valid
CK_c
CK_t
MPR Enable
Command
MRS1
PREA
tRP
Address
Valid
tMOD
Valid
tWR_MPR
Valid
Add2
Valid
CKE
PL3 + AL + CL
DQS_t,
DQS_c
DQ
UI0
UI1
UI2
UI3
UI4
UI5
Time Break
Notes:
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UI6
UI7
Don’t Care
1. Multipurpose registers read/write enable (MR3 A2 = 1).
2. Address setting:
BA1 and BA0 indicate the MPR location
A10 and other address pins are "Don’t Care"
3. Parity latency (PL) is added to data output delay when CA parity latency mode is enabled.
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4Gb: x4, x8, x16 DDR4 SDRAM
Multipurpose Register
Figure 37: MPR Back-to-Back WRITE Timing
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Ta9
Ta10
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
Valid
Valid
Add
Valid
Valid
Valid
Valid
Valid
Valid
CK_c
CK_t
Command
tWR_MPR
Address
Add1
Valid
Valid
Add1
CKE
DQS_t,
DQS_c
DQ
Time Break
Note:
Don’t Care
1. Address setting:
BA1 and BA0 indicate the MPR location
A[7:0] = data for MPR
A10 and other address pins are "Don’t Care"
MPR REFRESH Waveforms
The following waveforms show MPR accesses interaction with refreshes.
Figure 38: REFRESH Timing
T0
Ta0
Ta1
Tb0
Tb1
Tb2
Tb3
DES
REF2
DES
DES
DES
Tb4
Tc0
Tc1
Tc2
Tc3
Tc4
DES
DES
DES
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CK_c
CK_t
MPR Enable
Command
MRS1
PREA
tRP
Address
Valid
tMOD
Valid
tRFC
Valid
Valid
Valid
Valid
Valid
Time Break
Notes:
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Don’t Care
1. Multipurpose registers read/write enable (MR3 A2 = 1). Redirect all subsequent read and
writes to MPR locations.
2. 1x refresh is only allowed when MPR mode is enabled.
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4Gb: x4, x8, x16 DDR4 SDRAM
Multipurpose Register
Figure 39: READ-to-REFRESH Timing
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Ta9
Command
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
REF2
DES
DES
Address
Add1
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CK_c
CK_t
CKE
PL + AL + CL
tRFC
(4 + 1) + Clocks
BL = 8
DQS_t, DQS_c
DQ
UI0
UI1
UI2
UI3
UI0
UI1
UI2
UI3
UI4
UI5
UI6
UI7
BC = 4
DQS_t, DQS_c
DQ
Time Break
Notes:
Don’t Care
1. Address setting:
A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here)
A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7)
BA1 and BA0 indicate the MPR location
A10 and other address pins are "Don’t Care," including BG1 and BG0. A12 is "Don’t
Care" when MR0 A[1:0] = 00 or 10, and must be 1b when MR0 A[1:0] = 01
2. 1x refresh is only allowed when MPR mode is enabled.
Figure 40: WRITE-to-REFRESH Timing
T0
T1
WRITE
DES
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
DES
DES
REF2
DES
DES
DES
Ta6
Ta7
Ta8
Ta9
Ta10
DES
DES
DES
DES
DES
Valid
Valid
Valid
Valid
Valid
CK_c
CK_t
Command
tWR_MPR
Address
Add1
Valid
Valid
tRFC
Valid
Valid
Valid
Valid
Valid
CKE
DQS_t,
DQS_c
DQ
Time Break
Notes:
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Don’t Care
1. Address setting:
BA1 and BA0 indicate the MPR location
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4Gb: x4, x8, x16 DDR4 SDRAM
Multipurpose Register
A[7:0] = data for MPR
A10 and other address pins are "Don’t Care"
2. 1x refresh is only allowed when MPR mode is enabled.
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4Gb: x4, x8, x16 DDR4 SDRAM
Gear-Down Mode
Gear-Down Mode
The DDR4 SDRAM defaults in 1/2 rate (1N) clock mode and uses a low-frequency MRS
command (the MRS command has relaxed setup and hold) followed by a sync pulse
(first CS pulse after MRS setting) to align the proper clock edge for operating the control
lines CS_n, CKE, and ODT when in 1/4 rate (2N) mode. Gear-down mode is only supported at DDR4-2666 and faster. For operation in 1/2 rate mode, neither an MRS command or a sync pulse is required. Gear-down mode may only be entered during initialization or self refresh exit and may only be exited during self refresh exit. CAL mode and
CA Parity mode must be disabled prior to Gear-Down mode entry. The two modes may
be enabled after tSYNC_GEAR and tCMD_GEAR periods have been satisfied. The general sequence for operation in 1/4 rate during initialization is as follows:
1. The device defaults to a 1N mode internal clock at power-up/reset.
2. Assertion of reset.
3. Assertion of CKE enables the DRAM.
4. MRS is accessed with a low-frequency N × tCK gear-down MRS command. (NtCK
static MRS command is qualified by 1N CS_n. )
5. The memory controller will send a 1N sync pulse with a low-frequency N × tCK
NOP command. tSYNC_GEAR is an even number of clocks. The sync pulse is on an
even edge clock boundary from the MRS command.
6. Initialization sequence, including the expiration of tDLLK and tZQinit, starts in 2N
mode after tCMD_GEAR from 1N sync pulse.
The device resets to 1N gear-down mode after entering self refresh. The general sequence for operation in gear-down after self refresh exit is as follows:
1. MRS is set to 1, via MR3[3], with a low-frequency N × tCK gear-down MRS command.
a. The NtCK static MRS command is qualified by 1N CS_n, which meets tXS or
tXS_ABORT.
b. Only a REFRESH command may be issued to the DRAM before the NtCK static MRS command.
2. The DRAM controller sends a 1N sync pulse with a low-frequency N × tCK NOP
command.
a. tSYNC_GEAR is an even number of clocks.
b. The sync pulse is on even edge clock boundary from the MRS command.
3. A valid command not requiring locked DLL is available in 2N mode after
tCMD_GEAR from the 1N sync pulse.
a. A valid command requiring locked DLL is available in 2N mode after tXSDLL
or tDLLK from the 1N sync pulse.
4. If operation is in 1N mode after self refresh exit, N × tCK MRS command or sync
pulse is not required during self refresh exit. The minimum exit delay to the first
valid command is tXS, or tXS_ABORT.
The DRAM may be changed from 2N to 1N by entering self refresh mode, which will reset to 1N mode. Changing from 2N to by any other means can result in loss of data and
make operation of the DRAM uncertain.
When operating in 2N gear-down mode, the following MR settings apply:
•
•
•
•
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CAS latency (MR0[6:4,2]): Even number of clocks
Write recovery and read to precharge (MR0[11:9]): Even number of clocks
Additive latency (MR1[4:3]): CL - 2
CAS WRITE latency (MR2 A[5:3]): Even number of clocks
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4Gb: x4, x8, x16 DDR4 SDRAM
Gear-Down Mode
• CS to command/address latency mode (MR4[8:6]): Even number of clocks
• CA parity latency mode (MR5[2:0]): Even number of clocks
Figure 41: Clock Mode Change from 1/2 Rate to 1/4 Rate (Initialization)
TdkN
TdkN + Neven
CK_c
CK_t
tDSRX
DRAM
internal CLK
RESET_n
CKE
tXPR_GEAR
tCMD_GEAR
tSYNC_GEAR
1N sync pulse
2N mode
CS_n
NtCKsetup
Command
NtCKhold
NtCKsetup
MRS
NtCKhold
NOP
Valid
Configure DRAM
to 1/4 rate
Time Break
Don’t Care
Figure 42: Clock Mode Change After Exiting Self Refresh
TdkN
TdkN + Neven
CK_c
CK_t
DRAM
internal CLK
CKE
tCMD_GEAR
tSYNC_GEAR
tXPR_GEAR
1N sync pulse
2N mode
CS_n
NtCKsetup
Command
NtCKhold
MRS
NtCKsetup
NOP
NtCKhold
Valid
Configure DRAM
to 1/4 rate
Time Break
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T0
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ACT
DES
T1
DQ
Command
DQ
Command
ACT
ACT
READ
AL = CL - 1 (geardown = disable)
DQ
Command
AL = 0 (geardown = disable)
CK_c
CK_t
READ
DES
tRCD
DES
T2
DES
= 16
DES
T3
DES
DES
T15
DES
DES
T17
DES
RL =CL= 16 (AL = 0)
DES
T18
DES
AL + CL = RL = 30 (AL = CL - 2 = 14)
DES
READ
RL = AL + CL = 31 (AL = CL - 1 = 15)
DES
READ
READ
T16
DES
DES
T19
DES
DES
DES
T30
DES
DES
T31
Figure 43: Comparison Between Gear-Down Disable and Gear-Down Enable
DO
n
DES
DO
n
DES
DO
n
DES
T32
DO
n+ 2
DO
n+ 1
DO
n+ 1
DO
n+ 2
DO
n+ 2
DES
DO
n+ 1
DES
T33
DO
n+ 4
DO
n+ 4
DO
n+ 4
DO
n+ 5
DO
n+ 5
DO
n+ 6
DO
n+ 6
DES
DO
n+ 6
DES
T35
DO
n+ 5
Time Break
DO
n+ 3
DES
DO
n+ 3
DES
DO
n+ 3
DES
T34
T37
DES
DES
Transitioning Data
DO
n+ 7
DES
DO
n+ 7
DES
DO
n+ 7
DES
T36
Don’t Care
DES
DES
DES
T38
4Gb: x4, x8, x16 DDR4 SDRAM
Gear-Down Mode
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4Gb: x4, x8, x16 DDR4 SDRAM
Maximum Power-Saving Mode
Maximum Power-Saving Mode
Maximum power-saving mode provides the lowest power mode where data retention is
not required. When the device is in the maximum power-saving mode, it does not
maintain data retention or respond to any external command, except the MAXIMUM
POWER SAVING MODE EXIT command and during the assertion of RESET_n signal
LOW. This mode is more like a “hibernate mode” than a typical power-saving mode.
The intent is to be able to park the DRAM at a very low-power state; the device can be
switched to an active state via the per-DRAM addressability (PDA) mode.
Maximum Power-Saving Mode Entry
Maximum power-saving mode is entered through an MRS command. For devices with
shared control/address signals, a single DRAM device can be entered into the maximum power-saving mode using the per-DRAM addressability MRS command. Large
CS_n hold time to CKE upon the mode exit could cause DRAM malfunction; as a result,
CA parity, CAL, and gear-down modes must be disabled prior to the maximum powersaving mode entry MRS command.
The MRS command may use both address and DQ information, as defined in the PerDRAM Addressability section. As illustrated in the figure below, after tMPED from the
mode entry MRS command, the DRAM is not responsive to any input signals except
CKE, CS_n, and RESET_n. All other inputs are disabled (external input signals may become High-Z). The system will provide a valid clock until tCKMPE expires, at which time
clock inputs (CK) should be disabled (external clock signals may become High-Z).
Figure 44: Maximum Power-Saving Mode Entry
Ta0
Ta1
Ta2
Tb0
Tb1
Tb3
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
Tc10
Tc11
CK_c
CK_t
tCKMPE
MR4[A1=1]
MPSM Enable)
Command
DES
MRS
DES
DES
DES
tMPED
Address
Valid
CS_n
CKE
CKE LOW makes CS_n a care; CKE LOW followed by CS_n LOW followed by CKE HIGH exits mode
RESET_n
Time Break
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4Gb: x4, x8, x16 DDR4 SDRAM
Maximum Power-Saving Mode
Maximum Power-Saving Mode Entry in PDA
The sequence and timing required for the maximum power-saving mode with the perDRAM addressability enabled is illustrated in the figure below.
Figure 45: Maximum Power-Saving Mode Entry with PDA
Ta0
Ta1
Ta2
Tb0
Tb1
Tb3
Tb4
Tb5
Tb6
Tb7
Tb8
Tb9
Tc0
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Tc1
Tc2
Td0
Td1
Td2
CK_c
CK_t
MR4[A1 = 1]
MPSM Enable)
Command
DES
MRS
DES
tCKMPE
CS_n
CKE
tMPED
AL + CWL
DQS_t
DQS_c
tPDA_S
tPDA_H
DQ
RESET_n
Time Break
Don’t Care
CKE Transition During Maximum Power-Saving Mode
The following figure shows how to maintain maximum power-saving mode even though
the CKE input may toggle. To prevent the device from exiting the mode, CS_n should be
HIGH at the CKE LOW-to-HIGH edge, with appropriate setup (tMPX_S) and hold
(tMPX_H) timings.
Figure 46: Maintaining Maximum Power-Saving Mode with CKE Transition
CLK
CMD
CS_n
tMPX_S
tMPX_HH
CKE
RESET_n
Don’t Care
Maximum Power-Saving Mode Exit
To exit the maximum power-saving mode, CS_n should be LOW at the CKE LOW-toHIGH transition, with appropriate setup (tMPX_S) and hold (tMPX_LH) timings, as
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4Gb: x4, x8, x16 DDR4 SDRAM
Maximum Power-Saving Mode
shown in the figure below. Because the clock receivers (CK_t, CK_c) are disabled during
this mode, CS_n = LOW is captured by the rising edge of the CKE signal. If the CS_n signal level is detected LOW, the DRAM clears the maximum power-saving mode MRS bit
and begins the exit procedure from this mode. The external clock must be restarted and
be stable by tCKMPX before the device can exit the maximum power-saving mode. During the exit time (tXMP), only NOP and DES commands are allowed: NOP during
tMPX_LH and DES the remainder of tXMP. After tXMP expires, valid commands not requiring a locked DLL are allowed; after tXMP_DLL expires, valid commands requiring a
locked DLL are allowed.
Figure 47: Maximum Power-Saving Mode Exit
Ta0
Ta1
Ta2
Ta3
Tb1
Tb0
Tb2
Tb3
Tc0
NOP
NOP
NOP
Tc1
Tc2
Tc4
Td0
Td1
Td2
Td3
Te0
Te1
NOP
NOP
DES
DES
DES
DES
Valid
DES
DES
CK_c
CK_t
tCKMPX
Command
tMPX_LH
CS_n
tMPX_S
CKE
tXMP
tXMP_DLL
RESET_n
Time Break
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4Gb: x4, x8, x16 DDR4 SDRAM
Command/Address Parity
Command/Address Parity
Command/address (CA) parity takes the CA parity signal (PAR) input carrying the parity
bit for the generated address and commands signals and matches it to the internally
generated parity from the captured address and commands signals. CA Parity is supported in the DLL enabled state only; if the DLL is disabled, CA Parity is not supported.
Figure 48: Command/Address Parity Operation
DRAM Controller
DRAM
CMD/ADDR
CMD/ADDR
Even parity
GEN
Even parity
GEN
CMD/ADDR
Even parity bit
Even parity bit
Compare
parity
bit
CA parity is disabled or enabled via an MRS command. If CA parity is enabled by programming a non-zero value to CA parity latency in the MR, the DRAM will ensure that
there is no parity error before executing commands. There is an additional delay required for executing the commands versus when parity is disabled. The delay is programmed in the MR when CA parity is enabled (parity latency) and applied to all commands which are registered by CS_n (rising edge of CK_t and falling CS_n). The command is held for the time of the parity latency (PL) before it is executed inside the device. The command captured by the input clock has an internal delay before executing
and is determined with PL. When CA parity is enabled, only DES are allowed between
valid commands. PAR will go active when the DRAM detects a CA parity error.
CA parity covers ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, the address bus including
bank address and bank group bits, and C[2:0] on 3DS devices; the control signals CKE,
ODT, and CS_n are not covered. For example, for a 4Gb x4 monolithic device, parity is
computed across BG[1:0], BA[1:0], A16/RAS_n, A15/CAS_n, A14/ WE_n, A[13:0], and
ACT_n. The DRAM treats any unused address pins internally as zeros; for example, if a
common die has stacked pins but the device is used in a monolithic application, then
the address pins used for stacking and not connected are treated internally as zeros.
The convention for parity is even parity; for example, valid parity is defined as an even
number of ones across the inputs used for parity computation combined with the parity signal. In other words, the parity bit is chosen so that the total number of ones in the
transmitted signal, including the parity bit, is even.
If a DRAM device detects a CA parity error in any command qualified by CS_n, it will
perform the following steps:
1. Ignore the erroneous command. Commands in the MAX NnCK window
(tPAR_UNKNOWN) prior to the erroneous command are not guaranteed to be executed. When a READ command in this NnCK window is not executed, the device
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4Gb: x4, x8, x16 DDR4 SDRAM
Command/Address Parity
2.
3.
4.
5.
6.
7.
8.
does not activate DQS outputs. If WRITE CRC is enabled and a WRITE CRC occurs
during the tPAR_UNKNOWN window, the WRITE CRC Error Status Bit located at
MR5[3] may or may not get set. When CA Parity and WRITE CRC are both enabled
and a CA Parity occurs, the WRITE CRC Error Status Bit should be reset.
Log the error by storing the erroneous command and address bits in the MPR error log.
Set the parity error status bit in the mode register to 1. The parity error status bit
must be set before the ALERT_n signal is released by the DRAM (that is,
tPAR_ALERT_ON + tPAR_ALERT_PW (MIN)).
Assert the ALERT_n signal to the host (ALERT_n is active LOW) within
tPAR_ALERT_ON time.
Wait for all in-progress commands to complete. These commands were received
tPAR_UNKOWN before the erroneous command.
Wait for tRAS (MIN) before closing all the open pages. The DRAM is not executing
any commands during the window defined by (tPAR_ALERT_ON +
tPAR_ALERT_PW).
After tPAR_ALERT_PW (MIN) has been satisfied, the device may de-assert
ALERT_n.
a. When the device is returned to a known precharged state, ALERT_n is allowed to be de-asserted.
After (tPAR_ALERT_PW (MAX)) the DRAM is ready to accept commands for normal operation. Parity latency will be in effect; however, parity checking will not resume until the memory controller has cleared the parity error status bit by writing
a zero. The DRAM will execute any erroneous commands until the bit is cleared;
unless persistent mode is enabled.
• The DRAM should have only DES commands issued around ALERT_n going HIGH
such that at least 3 clocks prior and 1 clock plus 3ns after the release of ALERT_n.
• It is possible that the device might have ignored a REFRESH command during
tPAR_ALERT_PW or the REFRESH command is the first erroneous frame, so it is recommended that extra REFRESH cycles be issued, as needed.
• The parity error status bit may be read anytime after tPAR_ALERT_ON +
tPAR_ALERT_PW to determine which DRAM had the error. The device maintains the
error log for the first erroneous command until the parity error status bit is reset to a
zero or a second CA parity occurs prior to resetting.
The mode register for the CA parity error is defined as follows: CA parity latency bits are
write only, the parity error status bit is read/write, and error logs are read-only bits. The
DRAM controller can only program the parity error status bit to zero. If the DRAM controller illegally attempts to write a 1 to the parity error status bit, the DRAM can not be
certain that parity will be checked; the DRAM may opt to block the DRAM controller
from writing a 1 to the parity error status bit.
The device supports persistent parity error mode. This mode is enabled by setting
MR5[9] = 1; when enabled, CA parity resumes checking after the ALERT_n is de-asserted, even if the parity error status bit remains a 1. If multiple errors occur before the error status bit is cleared the error log in MPR Page 1 should be treated as "Don’t Care." In
persistent parity error mode the ALERT_n pulse will be asserted and de-asserted by the
DRAM as defined with the MIN and MAX value tPAR_ALERT_PW. The DRAM controller
must issue DESELECT commands once it detects the ALERT_n signal, this response
time is defined as tPAR_ALERT_RSP. The following figures capture the flow of events on
the CA bus and the ALERT_n signal.
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4Gb: x4, x8, x16 DDR4 SDRAM
Command/Address Parity
Table 36: Mode Register Setting for CA Parity
CA Parity Latency
MR5[2:0]1
Applicable Speed Bin
000 = Disabled
N/A
001 = 4 clocks
1600, 1866, 2133
010 = 5 clocks
2400, 2666
011 = 6 clocks
2933, 3200
100 = 8 clocks
RFU
101 = Reserved
RFU
110 = Reserved
RFU
111 = Reserved
RFU
Notes:
Parity Error Status Parity Persistent Mode
MR5 [4] 0 = Clear
MR5 [4] 1 = Error
Erroneous CA
Frame
C[2:0], ACT_n, BG1,
BG0, BA[1:0], PAR,
MR5 [9] 0 = DisabledMR5
A17, A16/RAS_n, A15/
[9] 1 = Enabled
CAS_n, A14/WE_n,
A[13:0]
1. Parity latency is applied to all commands.
2. Parity latency can be changed only from a CA parity disabled state; for example, a direct
change from PL = 3 to PL = 4 is not allowed. The correct sequence is PL = 3 to disabled to
PL = 4.
3. Parity latency is applied to WRITE and READ latency. WRITE latency = AL + CWL + PL.
READ latency = AL + CL + PL.
Figure 49: Command/Address Parity During Normal Operation
T0
T1
Valid 2
Valid 2
Ta0
Ta1
Ta2
Tb0
Tc0
Tc1
Valid 2
Error
Valid
Valid
Valid
DES2
Td0
Te0
Te1
DES2
Valid 3
Valid 3
CK_c
CK_t
Command/
Address
t > 2nCK
tPAR_UNKNOWN 2
tPAR_ALERT_ON
t > 1nCK + 3ns
tPAR_ALERT_PW 1
ALERT_n
Valid 2
DES2
Command execution unknown
Error
Valid
Command not executed
Valid 3
Don’t Care
Time Break
Command executed
Notes:
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1. DRAM is emptying queues. Precharge all and parity checking are off until parity error
status bit is cleared.
2. Command execution is unknown; the corresponding DRAM internal state change may
or may not occur. The DRAM controller should consider both cases and make sure that
the command sequence meets the specifications. If WRITE CRC is enabled and a WRITE
CRC occurs during the tPAR_UNKNOWN window, the WRITE CRC Error Status Bit located
at MR5[3] may or may not get set.
3. Normal operation with parity latency (CA parity persistent error mode disabled). Parity
checking is off until parity error status bit is cleared.
108
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4Gb: x4, x8, x16 DDR4 SDRAM
Command/Address Parity
Figure 50: Persistent CA Parity Error Checking Operation
T0
T1
Valid 2
Valid 2
CK_c
Ta0
Ta1
Ta2
Tb0
Valid 2
Error
Valid
Valid
Tc0
Tc1
Td0
Te0
Te1
Valid
DES
DES
DES
Valid 3
CK_t
Command/
Address
tPAR_ALERT_RSP
tPAR_UNKNOWN 2
tPAR_ALERT_ON
t > 2nCK
t > 1nCK + 3ns
tPAR_ALERT_PW 1
ALERT_n
Valid 2
DES
Command execution unknown
Error
Valid
Command not executed
Valid 3
Don’t Care
Command executed
Notes:
Time Break
1. DRAM is emptying queues. Precharge all and parity check re-enable finished by
tPAR_ALERT_PW.
2. Command execution is unknown; the corresponding DRAM internal state change may
or may not occur. The DRAM controller should consider both cases and make sure that
the command sequence meets the specifications. If WRITE CRC is enabled and a WRITE
CRC occurs during the tPAR_UNKNOWN window, the WRITE CRC Error Status Bit located
at MR5[3] may or may not get set
3. Normal operation with parity latency and parity checking (CA parity persistent error
mode enabled).
Figure 51: CA Parity Error Checking – SRE Attempt
T1
T0
CK_c
Ta0
Ta1
Tb0
Tb1
Tc0
Tc1
Td0
Td1
Td2
Td3
Te0
Te1
DES5
Valid 3
CK_t
tCPDED
Command/
Address
DES1, 5
tXP
+ PL
DES1
Error2
DES6
tIS
+ PL
DES6
tIS
CKE
t > 2nCK
tIH
tPAR_ALERT_ON
Note 4
t > 1nCK + 3ns
tPAR_ALERT_PW 1
ALERT_n
DES1, 5
DES6
Error2
DES1
Valid 3
DES5
Command execution unknown
Command not executed
Don’t Care
Command executed
Notes:
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Time Break
1. Only DESELECT command is allowed.
2. SELF REFRESH command error. The DRAM masks the intended SRE command and enters
precharge power-down.
3. Normal operation with parity latency (CA parity persistent error mode disabled). Parity
checking is off until the parity error status bit cleared.
4. The controller cannot disable the clock until it has been capable of detecting a possible
CA parity error.
5. Command execution is unknown; the corresponding DRAM internal state change may
or may not occur. The DRAM controller should consider both cases and make sure that
the command sequence meets the specifications.
6. Only a DESELECT command is allowed; CKE may go HIGH prior to Tc2 as long as DES
commands are issued.
109
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4Gb: x4, x8, x16 DDR4 SDRAM
Command/Address Parity
Figure 52: CA Parity Error Checking – SRX Attempt
T0
Ta0
Ta1
SRX1
DES
DES
Tb0
Tb1
Tc0
Tc1
Tc2
Td0
Td1
Te0
Tf0
Error2
Valid 2
Valid 2
Valid 2
DES2, 3
DES2, 3
Valid 2, 4, 5
Valid 2, 4, 6
Valid 2, 4, 7
CK_c
CK_t
Command/
Address
t > 2nCK
tIS
t > 1nCK + 3ns
CKE
tPAR_UNKNOWN
tPAR_ALERT_ON
tPAR_ALERT_PW
ALERT_n
tXS_FAST 8
tXS
tXSDLL
SRX1
DES
Error
Valid
Valid 4,5,6,7
Valid 3, 5
Command execution unknown
Command not executed
Time Break
Don’t Care
Command executed
Notes:
1. Self refresh abort = disable: MR4 [9] = 0.
2. Input commands are bounded by tXSDLL, tXS, tXS_ABORT, and tXS_FAST timing.
3. Command execution is unknown; the corresponding DRAM internal state change may
or may not occur. The DRAM controller should consider both cases and make sure that
the command sequence meets the specifications.
4. Normal operation with parity latency (CA parity persistent error mode disabled). Parity
checking off until parity error status bit cleared.
5. Only an MRS (limited to those described in the SELF REFRESH Operation section), ZQCS,
or ZQCL command is allowed.
6. Valid commands not requiring a locked DLL.
7. Valid commands requiring a locked DLL.
8. This figure shows the case from which the error occurred after tXS_FAST. An error may
also occur after tXS_ABORT and tXS.
Figure 53: CA Parity Error Checking – PDE/PDX
T1
T0
CK_c
Ta0
Ta1
Tb0
Tb1
Tc0
Tc1
Td0
Td1
Td2
Td3
Te0
Te1
DES4
Valid 3
CK_t
tCPDED
Command/
Address
DES1
Error2
tXP
+ PL
DES1
DES5
tIS
+ PL
DES5
tIS
CKE
t > 2nCK
tIH
tPAR_ALERT_ON
t > 1nCK + 3ns
tPAR_ALERT_PW 1
ALERT_n
DES4
DES5
Command execution unknown
Error2
DES1
Command not executed
Valid 3
Don’t Care
Command executed
Notes:
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Time Break
1. Only DESELECT command is allowed.
2. Error could be precharge or activate.
3. Normal operation with parity latency (CA parity persistent error mode disabled). Parity
checking is off until parity error status bit cleared.
110
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4Gb: x4, x8, x16 DDR4 SDRAM
Command/Address Parity
4. Command execution is unknown; the corresponding DRAM internal state change may
or may not occur. The DRAM controller should consider both cases and make sure that
the command sequence meets the specifications.
5. Only a DESELECT command is allowed; CKE may go HIGH prior to Td2 as long as DES
commands are issued.
Figure 54: Parity Entry Timing Example – tMRD_PAR
Ta0
Ta1
Ta2
Tb0
Tb1
Tb2
DES
MRS
DES
DES
MRS
DES
CK_c
CK_t
Command
Parity latency
PL = 0
Updating setting
PL = N
tMRD_PAR
Enable
parity
Don’t Care
Time Break
Note:
1. tMRD_PAR = tMOD + N; where N is the programmed parity latency.
Figure 55: Parity Entry Timing Example – tMOD_PAR
Ta0
Ta1
Ta2
Tb0
Tb1
Tb2
DES
MRS
DES
DES
Valid
DES
CK_c
CK_t
Command
Parity latency
PL = 0
Updating setting
PL = N
tMOD_PAR
Enable
parity
Time Break
Note:
Don’t Care
1. tMOD_PAR = tMOD + N; where N is the programmed parity latency.
Figure 56: Parity Exit Timing Example – tMRD_PAR
Ta0
Ta1
Ta2
Tb0
Tb1
Tb2
DES
MRS
DES
DES
MRS
DES
CK_c
CK_t
Command
Parity latency
PL = N
Updating setting
tMRD_PAR
Disable
parity
Time Break
Note:
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Don’t Care
1. tMRD_PAR = tMOD + N; where N is the programmed parity latency.
111
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4Gb: x4, x8, x16 DDR4 SDRAM
Command/Address Parity
Figure 57: Parity Exit Timing Example – tMOD_PAR
Ta0
Ta1
Ta2
Tb0
Tb1
Tb2
DES
MRS
DES
DES
Valid
DES
CK_c
CK_t
Command
Parity latency
PL = N
Updating setting
tMOD_PAR
Disable
parity
Time Break
Note:
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Don’t Care
1. tMOD_PAR = tMOD + N; where N is the programmed parity latency.
112
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Figure 58: CA Parity Flow Diagram
CA
process start
MR5[2:0] set parity latency (PL)
MR5[4] set parity error status to 0
MR5[9] enable/disable persistent mode
CA
latched in
Yes
CA parity
enabled
Persistent
mode
enabled
Yes
CA parity
error
No
No
No
MR5[4] = 0
@ ADDR/CMD
latched
No
Yes
Yes
CA parity
error
Good CA
processed
Yes
Ignore
bad CMD
Command
execution
unknown
No
Good CA
processed
Ignore
bad CMD
113
Command
execution
unknown
ALERT_n LOW
44 to 144 CKs
MR5[4] = 0 Yes
@ ADDR/CMD
latched
Log error/
set parity status
No
Yes
CA error
ALERT_n LOW
44 to 144 CKs
Internal
precharge all
Internal
precharge all
ALERT_n HIGH
ALERT_n HIGH
Command
execution
unknown
No
Good CA
processed
Normal
operation ready
Bad CA
processed
Operation ready?
Command
execution
unknown
Normal operation ready
MR5[4] reset to 0 if desired
Normal operation ready
MR5[4] reset to 0 if desired
4Gb: x4, x8, x16 DDR4 SDRAM
Command/Address Parity
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Log error/
set parity status
4Gb: x4, x8, x16 DDR4 SDRAM
Per-DRAM Addressability
Per-DRAM Addressability
DDR4 allows programmability of a single, specific DRAM on a rank. As an example, this
feature can be used to program different ODT or V REF values on each DRAM on a given
rank. Because per-DRAM addressability (PDA) mode may be used to program optimal
VREF for the DRAM, the data set up for first DQ0 transfer or the hold time for the last
DQ0 transfer cannot be guaranteed. The DRAM may sample DQ0 on either the first falling or second rising DQS transfer edge. This supports a common implementation between BC4 and BL8 modes on the DRAM. The DRAM controller is required to drive DQ0
to a stable LOW or HIGH state during the length of the data transfer for BC4 and BL8
cases.
1. Before entering PDA mode, write leveling is required.
• BL8 or BC4 may be used.
2. Before entering PDA mode, the following MR settings are possible:
3.
4.
5.
6.
7.
8.
• RTT(Park) MR5 A[8:6] = Enable
• RTT(NOM) MR1 A[10:8] = Enable
Enable PDA mode using MR3 [4] = 1. (The default programed value of MR3[4] = 0.)
In PDA mode, all MRS commands are qualified with DQ0. The device captures
DQ0 by using DQS signals. If the value on DQ0 is LOW, the DRAM executes the
MRS command. If the value on DQ0 is HIGH, the DRAM ignores the MRS command. The controller can choose to drive all the DQ bits.
Program the desired DRAM and mode registers using the MRS command and
DQ0.
In PDA mode, only MRS commands are allowed.
The MODE REGISTER SET command cycle time in PDA mode, AL + CWL + BL/2 0.5tCK + tMRD_PDA + PL, is required to complete the WRITE operation to the
mode register and is the minimum time required between two MRS commands.
Remove the device from PDA mode by setting MR3[4] = 0. (This command requires DQ0 = 0.)
Note: Removing the device from PDA mode will require programming the entire MR3
when the MRS command is issued. This may impact some PDA values programmed
within a rank as the EXIT command is sent to the rank. To avoid such a case, the PDA
enable/disable control bit is located in a mode register that does not have any PDA
mode controls.
In PDA mode, the device captures DQ0 using DQS signals the same as in a normal
WRITE operation; however, dynamic ODT is not supported. Extra care is required for
the ODT setting. If RTT(NOM) MR1 [10:8] = enable, device data termination needs to be
controlled by the ODT pin, and applies the same timing parameters (defined below).
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Symbol
Parameter
DODTLon
Direct ODT turnon latency
DODTLoff
Direct ODT turn off latency
tADC
RTT change timing skew
tAONAS
Asynchronous RTT(NOM) turn-on delay
tAOFAS
Asynchronous RTT(NOM) turn-off delay
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4Gb: x4, x8, x16 DDR4 SDRAM
Per-DRAM Addressability
Figure 59: PDA Operation Enabled, BL8
&.BF
&.BW
05$ 3'$HQDEOH
056
056
056
W 02'
W 05'B3'$
&:/$/3/
'46BW
'46BF
'4
W 3'$B6
W 3'$B+
'2'7/RII :/
2'7
'2'7/RQ :/
577
577 3DUN
Note:
577 120
577 3DUN
1. RTT(Park) = Enable; RTT(NOM) = Enable; WRITE preamble set = 2tCK; and DLL = On.
Figure 60: PDA Operation Enabled, BC4
CK_c
CK_t
MR3 A4 = 1
(PDA enable)
MRS
MRS
MRS
tMOD
tMRD_PDA
CWL+AL+PL
DQS_t
DQS_c
DQ0
tPDA_S
tPDA_H
DODTLoff = WL-3
ODT
DODTLon = WL-3
RTT
RTT(Park)
Note:
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
RTT(NOM)
RTT(Park)
1. RTT(Park) = Enable; RTT(NOM) = Enable; WRITE preamble set = 2tCK; and DLL = On.
115
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4Gb: x4, x8, x16 DDR4 SDRAM
Per-DRAM Addressability
Figure 61: MRS PDA Exit
&.BF
&.BW
05$ 3'$GLVDEOH
056
9DOLG
&:/$/3/
W 02'B3'$
'46BW
'46BF
'4
W 3'$B6
W 3'$B+
'2'7/RII :/
2'7
'2'7/RQ :/
577
577 3DUN
Note:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
577 120
577 3DUN
1. RTT(Park) = Enable; RTT(NOM) = Enable; WRITE preamble set = 2tCK; and DLL = On.
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4Gb: x4, x8, x16 DDR4 SDRAM
VREFDQ Calibration
VREFDQ Calibration
The V REFDQ level, which is used by the DRAM DQ input receivers, is internally generated. The DRAM V REFDQ does not have a default value upon power-up and must be set
to the desired value, usually via V REFDQ calibration mode. If PDA or PPR modes (hPPR or
sPPR) are used prior to V REFDQ calibration, V REFDQ should initially be set at the midpoint
between the V DD,max, and the LOW as determined by the driver and ODT termination
selected with wide voltage swing on the input levels and setup and hold times of approximately 0.75UI. The memory controller is responsible for V REFDQ calibration to determine the best internal V REFDQ level. The V REFDQ calibration is enabled/disabled via
MR6[7], MR6[6] selects Range 1 (60% to 92.5% of V DDQ) or Range 2 (45% to 77.5% of
VDDQ), and an MRS protocol using MR6[5:0] to adjust the V REFDQ level up and down.
MR6[6:0] bits can be altered using the MRS command if MR6[7] is disabled. The DRAM
controller will likely use a series of writes and reads in conjunction with V REFDQ adjustments to obtain the best V REFDQ, which in turn optimizes the data eye.
The internal V REFDQ specification parameters are voltage range, step size, V REF step
time, V REF full step time, and V REF valid level. The voltage operating range specifies the
minimum required V REF setting range for DDR4 SDRAM devices. The minimum range is
defined by V REFDQ,min and V REFDQ,max. As noted, a calibration sequence, determined by
the DRAM controller, should be performed to adjust V REFDQ and optimize the timing
and voltage margin of the DRAM data input receivers. The internal V REFDQ voltage value
may not be exactly within the voltage range setting coupled with the V REF set tolerance;
the device must be calibrated to the correct internal V REFDQ voltage.
Figure 62: VREFDQ Voltage Range
VDDQ
VREF,max
VREF
range
VREF,min
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117
VSWING small
System variance
VSWING large
Total range
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4Gb: x4, x8, x16 DDR4 SDRAM
VREFDQ Calibration
VREFDQ Range and Levels
Table 37: VREFDQ Range and Levels
MR6[5:0]
Range 1 MR6[6] 0
Range 2 MR6[6] 1
MR6[5:0]
Range 1 MR6[6] 0
Range 2 MR6[6] 1
00 0000
60.00%
45.00%
01 1010
76.90%
61.90%
00 0001
60.65%
45.65%
01 1011
77.55%
62.55%
00 0010
61.30%
46.30%
01 1100
78.20%
63.20%
00 0011
61.95%
46.95%
01 1101
78.85%
63.85%
00 0100
62.60%
47.60%
01 1110
79.50%
64.50%
00 0101
63.25%
48.25%
01 1111
80.15%
65.15%
00 0110
63.90%
48.90%
10 0000
80.80%
65.80%
00 0111
64.55%
49.55%
10 0001
81.45%
66.45%
00 1000
65.20%
50.20%
10 0010
82.10%
67.10%
00 1001
65.85%
50.85%
10 0011
82.75%
67.75%
00 1010
66.50%
51.50%
10 0100
83.40%
68.40%
00 1011
67.15%
52.15%
10 0101
84.05%
69.05%
00 1100
67.80%
52.80%
10 0110
84.70%
69.70%
00 1101
68.45%
53.45%
10 0111
85.35%
70.35%
00 1110
69.10%
54.10%
10 1000
86.00%
71.00%
00 1111
69.75%
54.75%
10 1001
86.65%
71.65%
01 0000
70.40%
55.40%
10 1010
87.30%
72.30%
01 0001
71.05%
56.05%
10 1011
87.95%
72.95%
01 0010
71.70%
56.70%
10 1100
88.60%
73.60%
01 0011
72.35%
57.35%
10 1101
89.25%
74.25%
01 0100
73.00%
58.00%
10 1110
89.90%
74.90%
01 0101
73.65%
58.65%
10 1111
90.55%
75.55%
01 0110
74.30%
59.30%
11 0000
91.20%
76.20%
01 0111
74.95%
59.95%
11 0001
91.85%
76.85%
01 1000
75.60%
60.60%
11 0010
92.50%
77.50%
01 1001
76.25%
61.25%
11 0011 to 11 1111 = Reserved
VREFDQ Step Size
The V REF step size is defined as the step size between adjacent steps. V REF step size ranges from 0.5% V DDQ to 0.8% V DDQ. However, for a given design, the device has one value
for V REF step size that falls within the range.
The V REF set tolerance is the variation in the V REF voltage from the ideal setting. This accounts for accumulated error over multiple steps. There are two ranges for V REF set tolerance uncertainty. The range of V REF set tolerance uncertainty is a function of number
of steps n.
The V REF set tolerance is measured with respect to the ideal line, which is based on the
MIN and MAX V REF value endpoints for a specified range. The internal V REFDQ voltage
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118
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4Gb: x4, x8, x16 DDR4 SDRAM
VREFDQ Calibration
value may not be exactly within the voltage range setting coupled with the V REF set tolerance; the device must be calibrated to the correct internal V REFDQ voltage.
Figure 63: Example of VREF Set Tolerance and Step Size
Actual VREF
output
Straight line
(endpoint fit)
VREF
VREF set
tolerance
VREF set
tolerance
VREF
step size
Digital Code
Note:
1. Maximum case shown.
VREFDQ Increment and Decrement Timing
The V REF increment/decrement step times are defined by V REF,time. V REF,time is defined
from t0 to t1, where t1 is referenced to the V REF voltage at the final DC level within the
VREF valid tolerance (VREF,val_tol). The V REF valid level is defined by V REF,val tolerance to
qualify the step time t1. This parameter is used to insure an adequate RC time constant
behavior of the voltage level change after any V REF increment/decrement adjustment.
Note:
t0 is referenced to the MRS command clock
t1 is referenced to V REF,tol
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VREFDQ Calibration
Figure 64: VREFDQ Timing Diagram for VREF,time Parameter
CK_c
CK_t
MRS
Command
VREF setting
adjustment
DQ VREF
Old VREF setting
Updating VREF setting
New VREF setting
VREF_time
t0
t1
Don’t Care
VREFDQ calibration mode is entered via an MRS command, setting MR6[7] to 1 (0 disables V REFDQ calibration mode) and setting MR6[6] to either 0 or 1 to select the desired
range (MR6[5:0] are "Don't Care"). After V REFDQ calibration mode has been entered,
VREFDQ calibration mode legal commands may be issued once tVREFDQE has been satisfied. Legal commands for V REFDQ calibration mode are ACT, WR, WRA, RD, RDA, PRE,
DES, and MRS to set V REFDQ values, and MRS to exit V REFDQ calibration mode. Also, after
VREFDQ calibration mode has been entered, “dummy” WRITE commands are allowed
prior to adjusting the V REFDQ value the first time V REFDQ calibration is performed after
initialization.
Setting V REFDQ values requires MR6[7] be set to 1 and MR6[6] be unchanged from the
initial range selection; MR6[5:0] may be set to the desired V REFDQ values. If MR6[7] is set
to 0, MR6[6:0] are not written. V REF,time-short or V REF,time-long must be satisfied after each
MR6 command to set V REFDQ value before the internal V REFDQ value is valid.
If PDA mode is used in conjunction with V REFDQ calibration, the PDA mode requirement that only MRS commands are allowed while PDA mode is enabled is not waived.
That is, the only V REFDQ calibration mode legal commands noted above that may be
used are the MRS commands: MRS to set V REFDQ values and MRS to exit V REFDQ calibration mode.
The last MR6[6:0] setting written to MR6 prior to exiting V REFDQ calibration mode is the
range and value used for the internal V REFDQ setting. V REFDQ calibration mode may be
exited when the DRAM is in idle state. After the MRS command to exit V REFDQ calibration mode has been issued, DES must be issued until tVREFDQX has been satisfied
where any legal command may then be issued. V REFDQ setting should be updated if the
die temperature changes too much from the calibration temperature.
The following are typical script when applying the above rules for V REFDQ calibration
routine when performing V REFDQ calibration in Range 1:
• MR6[7:6]10 [5:0]XXXXXXX.
– Subsequent legal commands while in V REFDQ calibration mode: ACT, WR, WRA, RD,
RDA, PRE, DES, and MRS (to set V REFDQ values and exit V REFDQ calibration mode).
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VREFDQ Calibration
• All subsequent V REFDQ calibration MR setting commands are MR6[7:6]10
[5:0]VVVVVV.
– "VVVVVV" are desired settings for V REFDQ.
• Issue ACT/WR/RD looking for pass/fail to determine V CENT (midpoint) as needed.
• To exit V REFDQ calibration, the last two V REFDQ calibration MR commands are:
– MR6[7:6]10 [5:0]VVVVVV* where VVVVVV* = desired value for V REFDQ.
– MR6[7]0 [6:0]XXXXXXX to exit V REFDQ calibration mode.
The following are typical script when applying the above rules for V REFDQ calibration
routine when performing V REFDQ calibration in Range 2:
• MR6[7:6]11 [5:0]XXXXXXX.
– Subsequent legal commands while in V REFDQ calibration mode: ACT, WR, WRA, RD,
RDA, PRE, DES, and MRS (to set V REFDQ values and exit V REFDQ calibration mode).
• All subsequent V REFDQ calibration MR setting commands are MR6[7:6]11
[5:0]VVVVVV.
– "VVVVVV" are desired settings for V REFDQ.
• Issue ACT/WR/RD looking for pass/fail to determine V CENT (midpoint) as needed.
• To exit V REFDQ calibration, the last two V REFDQ calibration MR commands are:
– MR6[7:6]11 [5:0]VVVVVV* where VVVVVV* = desired value for V REFDQ.
– MR6[7]0 [6:0]XXXXXXX to exit V REFDQ calibration mode.
Note:
Range may only be set or changed when entering V REFDQ calibration mode; changing
range while in or exiting V REFDQ calibration mode is illegal.
Figure 65: VREFDQ Training Mode Entry and Exit Timing Diagram
T0
T1
DES
MRS
Ta0
Ta1
Tb0
Tb1
Tc0
Tc1
DES
CMD
DES
CMD
DES
MRS1,2
Td0
Td1
Td2
DES
WR
DES
CK_c
CK_t
Command
tVREFDQE
VREFDQ training on
tVREFDQX
New VREFDQ
value or write
New VREFDQ
value or write
VREFDQ training off
Don’t Care
Notes:
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1. New VREFDQ values are not allowed with an MRS command during calibration mode entry.
2. Depending on the step size of the latest programmed VREF value, VREF must be satisfied
before disabling VREFDQ training mode.
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4Gb: x4, x8, x16 DDR4 SDRAM
VREFDQ Calibration
Figure 66: VREF Step: Single Step Size Increment Case
VREF
Voltage
VREF
(VDDQ(DC))
VREF,val_tol
Step size
t1
Time
Figure 67: VREF Step: Single Step Size Decrement Case
VREF
Voltage
t1
Step size
VREF,val_tol
VREF
(VDDQ(DC))
Time
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VREFDQ Calibration
Figure 68: VREF Full Step: From VREF,min to VREF,maxCase
VREF
Voltage
VREF,max
VREF,val_tol
Full range
step
VREF
(VDDQ(DC))
t1
VREF,min
Time
Figure 69: VREF Full Step: From VREF,max to VREF,minCase
VREF
Voltage
VREF,max
Full range
step
t1
VREF,val_tol
VREF,min
VREF
(VDDQ(DC))
Time
VREFDQ Target Settings
The V REFDQ initial settings are largely dependant on the ODT termination settings. The
table below shows all of the possible initial settings available for V REFDQ training; it is
unlikely the lower ODT settings would be used in most cases.
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4Gb: x4, x8, x16 DDR4 SDRAM
VREFDQ Calibration
Table 38: VREFDQ Settings (VDDQ = 1.2V)
RON
34 ohm
48 ohm
ODT
Vx – VIN LOW (mV)
VREFDQ (mv)
VREFDQ (%VDDQ)
34 ohm
600
900
75%
40 ohm
550
875
73%
48 ohm
500
850
71%
60 ohm
435
815
68%
80 ohm
360
780
65%
120 ohm
265
732
61%
240 ohm
150
675
56%
34 ohm
700
950
79%
40 ohm
655
925
77%
48 ohm
600
900
75%
60 ohm
535
865
72%
80 ohm
450
825
69%
120 ohm
345
770
64%
240 ohm
200
700
58%
Figure 70: VREFDQ Equivalent Circuit
VDDQ
VDDQ
ODT
RXer
Vx
VREFDQ
(internal)
RON
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4Gb: x4, x8, x16 DDR4 SDRAM
Connectivity Test Mode
Connectivity Test Mode
Connectivity test (CT) mode is similar to boundary scan testing but is designed to significantly speed up the testing of electrical continuity of pin interconnections between
the device and the memory controller on the PC boards. Designed to work seamlessly
with any boundary scan device, CT mode is supported in all x4,x8, and x16 devices (JEDEC states CT mode for x4 and x8 is not required on 4Gb and is an optional feature on
8Gb and above).
Contrary to other conventional shift-register-based test modes, where test patterns are
shifted in and out of the memory devices serially during each clock, the CT mode allows
test patterns to be entered on the test input pins in parallel and the test results to be
extracted from the test output pins of the device in parallel. These two functions are also performed at the same time, significantly increasing the speed of the connectivity
check. When placed in CT mode, the device appears as an asynchronous device to the
external controlling agent. After the input test pattern is applied, the connectivity test
results are available for extraction in parallel at the test output pins after a fixed propagation delay time.
Note: A reset of the device is required after exiting CT mode (see RESET and Initialization Procedure).
Pin Mapping
Only digital pins can be tested using the CT mode. For the purposes of a connectivity
check, all the pins used for digital logic in the device are classified as one of the following types:
• Test enable (TEN): When asserted HIGH, this pin causes the device to enter CT mode.
In CT mode, the normal memory function inside the device is bypassed and the I/O
pins appear as a set of test input and output pins to the external controlling agent.
Additionally, the device will set the internal V REFDQ to V DDQ × 0.5 during CT mode
(this is the only time the DRAM takes direct control over setting the internal V REFDQ).
The TEN pin is dedicated to the connectivity check function and will not be used during normal device operation.
• Chip select (CS_n): When asserted LOW, this pin enables the test output pins in the
device. When de-asserted, these output pins will be High-Z. The CS_n pin in the device serves as the CS_n pin in CT mode.
• Test input: A group of pins used during normal device operation designated as test
input pins. These pins are used to enter the test pattern in CT mode.
• Test output: A group of pins used during normal device operation designated as test
output pins. These pins are used for extraction of the connectivity test results in CT
mode.
• RESET_n: This pin must be fixed high level during CT mode, as in normal function.
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Connectivity Test Mode
Table 39: Connectivity Mode Pin Description and Switching Levels
CT Mode
Pins
Pin Name During Normal Memory Operation
Switching Level
Test enable
TEN
CMOS (20%/80% VDD)
Chip select
Test
input
Test
output
Notes
1, 2
VREFCA ±200mV
3
BA[1:0], BG[1:0], A[9:0], A10/AP, A11, A12/BC_n, A13, WE_n/A14,
A
CAS_n/A15, RAS_n/A16, CKE, ACT_n, ODT, CLK_t, CLK_c, PAR
VREFCA ±200mV
3
B LDM_n/LDBI_n, UDM_n/UDBI_n; DM_n/DBI_n
VREFDQ ±200mV
4
C ALERT_n
CMOS (20%/80% VDD)
2, 5
D RESET_n
CMOS (20%/80% VDD)
2
VTT ±100mV
6
CS_n
DQ[15:0], UDQS_t, UDQS_c, LDQS_t, LDQS_c; DQS_t, DQS_c
Notes:
1. TEN: Connectivity test mode is active when TEN is HIGH and inactive when TEN is LOW.
TEN must be LOW during normal operation.
2. CMOS is a rail-to-rail signal with DC HIGH at 80% and DC LOW at 20% of VDD (960mV
for DC HIGH and 240mV for DC LOW.)
3. VREFCA should be VDD/2.
4. VREFDQ should be VDDQ/2.
5. ALERT_n switching level is not a final setting.
6. VTT should be set to VDD/2.
Minimum Terms Definition for Logic Equations
The test input and output pins are related by the following equations, where INV denotes a logical inversion operation and XOR a logical exclusive OR operation:
MT0 = XOR (A1, A6, PAR)
MT1 = XOR (A8, ALERT_n, A9)
MT2 = XOR (A2, A5, A13)
MT3 = XOR (A0, A7, A11)
MT4 = XOR (CK_c, ODT, CAS_n/A15)
MT5 = XOR (CKE, RAS_n/A16, A10/AP)
MT6 = XOR (ACT_n, A4, BA1)
MT7 = x16: XOR (DMU_n/DBIU_n , DML_n/DBIL_n, CK_t)
= x8: XOR (BG1, DML_n/DBIL_n, CK_t)
= x4: XOR (BG1, CK_t)
MT8 = XOR (WE_n/A14, A12 / BC, BA0)
MT9 = XOR (BG0, A3, RESET_n and TEN)
Logic Equations for a x4 Device, When Supported
DQ0 = XOR (MT0, MT1)
DQ1 = XOR (MT2, MT3)
DQ2 = XOR (MT4, MT5)
DQ3 = XOR (MT6, MT7)
DQS_t = MT8
DQS_c = MT9
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Connectivity Test Mode
Logic Equations for a x8 Device, When Supported
DQ0 = MT0
DQ1 = MT1
DQ2 = MT2
DQ3 = MT3
DQ4 = MT4
DQ5 = MT5
DQ6 = MT6
DQ7 = MT7
DQS_t = MT8
DQS_c = MT9
Logic Equations for a x16 Device
DQ0 = MT0
DQ1 = MT1
DQ2 = MT2
DQ3 = MT3
DQ4 = MT4
DQ5 = MT5
DQ6 = MT6
DQ7 = MT7
DQ8 = INV DQ0
DQ9 = INV DQ1
DQ10 = INV DQ2
DQ11 = INV DQ3
DQ12 = INV DQ4
DQ13 = INV DQ5
DQ14 = INV DQ6
DQ15 = INV DQ7
LDQS_t = MT8
LDQS_c = MT9
UDQS_t = INV LDQS_t
UDQS_c = INV LDQS_c
CT Input Timing Requirements
Prior to the assertion of the TEN pin, all voltage supplies, including VrefCA, must be valid and stable and RESET_n registered High prior to entering CT mode. Upon the assertion of the TEN pin HIGH with RESET_n, CKE and CS_n held HIGH; CLK_t, CLK_c, and
CKE signals become test inputs within tCTECT_Valid. The remaining CT inputs become
valid tCT_Enable after TEN goes HIGH when CS_n allows input to begin sampling, provided inputs were valid for at least tCT_Valid. While in CT mode, refresh activities in the
memory arrays are not allowed; they are initiated either externally (auto refresh) or internally (self refresh).
The TEN pin may be asserted after the DRAM has completed power-on. After the DRAM
is initialized and V REFDQ is calibrated, CT mode may no longer be used. The TEN pin
may be de-asserted at any time in CT mode. Upon exiting CT mode, the states and the
integrity of the original content of the memory array are unknown. A full reset of the
memory device is required.
After CT mode has been entered, the output signals will be stable within tCT_Valid after
the test inputs have been applied as long as TEN is maintained HIGH and CS_n is maintained LOW.
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Connectivity Test Mode
Figure 71: Connectivity Test Mode Entry
Ta
Tb
Tc
Td
CK_t
Valid input
CK_c
tCKSRX
tCT_IS
tIS
T = 10ns
Valid input
tCT_IS
CKE
Valid input
Valid input
tCTCKE_Valid
T = 200μs
T = 500μs
RESET_n
tCT_IS
TEN
tCTCKE_Valid>10ns
tCT_Enable
tCT_IS >0ns
CS_n
tCT_IS
CT Inputs
Valid input
Valid input
tCT_Valid
tCT_Valid
tCT_Valid
CT Outputs
Valid
Valid
Don’t Care
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Post Package Repair
Post Package Repair
Post Package Repair
JEDEC defines two modes of Post Package Repair (PPR): soft Post Package Repair (sPPR)
and hard Post Package Repair (hPPR). sPPR is non-persistent so the repair row maybe
altered; that is, sPPR is NOT a permanent repair and even though it will repair a row, the
repair can be reversed, reassigned via another sPPR, or made permanent via hPPR.
Hard Post Package Repair is persistent so once the repair row is assigned for a hPPR address, further PPR commands to a previous hPPR section should not be performed, that
is, hPPR is a permanent repair; once repaired, it cannot be reversed. The controller provides the failing row address in the hPPR/sPPR sequence to the device to perform the
row repair. hPPR Mode and sPPR Mode may not be enabled at the same time.
JEDEC states hPPR is optional for 4Gb and sPPR is optional for 4Gb and 8Gb parts however Micron 4Gb and 8Gb DDR4 DRAMs should have both sPPR and hPPR support. The
hPPR support is identified via an MPR read from MPR Page 2, MPR0[7] and sPPR support is identified via an MPR read from MPR Page 2, MPR0[6].
The JEDEC minimum support requirement for DDR4 PPR (hPPR or sPPR) is to provide
one row of repair per bank group (BG), x4/x8 have 4 BG and x16 has 2 BG; this is a total
of 4 repair rows available on x4/x8 and 2 repair rows available on x16. Micron PPR support exceeds the JEDEC minimum requirements; Micron DDR4 DRAMs have at least
one row of repair for each bank which is essentially 4 row repairs per BG for a total of 16
repair rows for x4 and x8 and 8 repair rows for x16; a 4x increase in repair rows.
JEDEC requires the user to have all sPPR row repair addresses reset and cleared prior to
enabling hPPR Mode. Micron DDR4 PPR does not have this restriction, the existing
sPPR row repair addresses are not required to be cleared prior to entering hPPR mode.
Each bank in a BG is PPR independent: sPPR or hPPR issued to a bank will not alter a
sPPR row repair existing in a different bank.
sPPR followed by sPPR to same bank
When PPR is issued to a bank for the first time and is a sPPR command, the repair row
will be a sPPR. When a subsequent sPPR is issued to the same bank, the previous sPPR
repair row will be cleared and used for the subsequent sPPR address as the sPPR operation is non-persistent.
sPPR followed by hPPR to same bank
When a PPR is issued to a bank for the first time and is a sPPR command, the repair row
will be a sPPR. When a subsequent hPPR is issued to the same bank, the initial sPPR
repair row will be cleared and used for the hPPR address. If a further subsequent PPR
(hPPR or sPPR) is issued to the same bank, the further subsequent PPR ( hPPR or sPPR)
repair row will not clear or overwrite the previous hPPR address as the hPPR operation
is persistent.
hPPR followed by hPPR or sPPR to same bank
When a PPR is issued to a bank for the first time and is a hPPR command, the repair row
will be a hPPR. When a subsequent PPR (hPPR or sPPR) is issued to the same bank, the
subsequent PPR ( hPPR or sPPR) repair row will not clear or overwrite the initial hPPR
address as the initial hPPR is persistent.
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Post Package Repair
Hard Post Package Repair
All banks must be precharged and idle. DBI and CRC modes must be disabled. Both
sPPR and hPPR must be disabled. sPPR is disabled with MR4[5] = 0. hPPR is disabled
with MR4[13] = 0, which is the normal state, and hPPR is enabled with MR4 [13]= 1,
which is the hPPR enabled state. There are two forms of hPPR mode. Both forms of
hPPR have the same entry requirement as defined in the sections below. The first command sequence uses a WRA command and supports data retention with a REFRESH
operation except for the bank containing the row that is being repaired; JEDEC has relaxed this requirement and allows BA[0] to be a don't care regarding the banks which
are not required to maintain data a REFRESH operation during hPPR. The second command sequence uses a WR command (a REFRESH operation can't be performed in this
command sequence). The second command sequence doesn't support data retention
for the target DRAM.
hPPR Row Repair - Entry
As stated above, all banks must be precharged and idle. DBI and CRC modes must be
disabled, and all timings must be followed as shown in the timing diagram that follows.
All other commands except those listed in the following sequences are illegal.
1. Issue MR4[13] 1 to enter hPPR mode enable.
a. All DQ are driven HIGH.
2. Issue four consecutive guard key commands (shown in the table below) to MR0
with each command separated by tMOD. The PPR guard key settings are the same
whether performing sPPR or hPPR mode.
a. Any interruption of the key sequence by other commands, such as ACT, WR,
RD, PRE, REF, ZQ, and NOP, are not allowed.
b. If the guard key bits are not entered in the required order or interrupted with
other MR commands, hPPR will not be enabled, and the programming cycle
will result in a NOP.
c. When the hPPR entry sequence is interrupted and followed by ACT and WR
commands, these commands will be conducted as normal DRAM commands.
d. JEDEC allows A6:0 to be "Don't Care" on 4Gb and 8Gb devices from a supplier perspective and the user should rely on vendor datasheet.
Table 40: PPR MR0 Guard Key Settings
MR0
BG1:0
BA1:0
A17:12
A11
A10
A9
A8
A7
A6:0
First guard key
0
0
xxxxxx
1
1
0
0
1
1111111
Second guard key
0
0
xxxxxx
0
1
1
1
1
1111111
Third Guard key
0
0
xxxxxx
1
0
1
1
1
1111111
Fourth guard key
0
0
xxxxxx
0
0
1
1
1
1111111
hPPR Row Repair – WRA Initiated (REF Commands Allowed)
1. Issue an ACT command with failing BG and BA with the row address to be repaired.
2. Issue a WRA command with BG and BA of failing row address.
a. The address must be at valid levels, but the address is "Don't Care."
3. All DQ of the target DRAM should be driven LOW for 4nCK (bit 0 through bit 7)
after WL (WL = CWL + AL + PL) in order for hPPR to initiate repair.
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Post Package Repair
a. Repair will be initiated to the target DRAM only if all DQ during bit 0 through
bit 7 are LOW. The bank under repair does not get the Refresh command applied to it.
b. Repair will not be initiated to the target DRAM if any DQ during bit 0 through
bit 7 is HIGH.
1. JEDEC states: All DQs of target DRAM should be LOW for 4tCK. If HIGH
is driven to all DQs of a DRAM consecutively for equal to or longer than
2tCK, then DRAM does not conduct hPPR and retains data if REF command is properly issued; if all DQs are neither LOW for 4tCK nor HIGH
for equal to or longer than 2tCK, then hPPR mode execution is unknown.
c. DQS should function normally.
4. REF command may be issued anytime after the WRA command followed by WL +
4nCK + tWR + tRP.
a. Multiple REF commands are issued at a rate of tREFI or tREFI/2, however
back-to-back REF commands must be separated by at least tREFI/4 when the
DRAM is in hPPR mode.
b. All banks except the bank under repair will perform refresh.
5. Issue PRE after tPGM time so that the device can repair the target row during tPGM
time.
a. Wait tPGM_Exit after PRE to allow the device to recognize the repaired target
row address.
6. Issue MR4[13] 0 command to hPPR mode disable.
a. Wait tPGMPST for hPPR mode exit to complete.
b. After tPGMPST has expired, any valid command may be issued.
The entire sequence from hPPR mode enable through hPPR mode disable may be repeated if more than one repair is to be done.
After completing hPPR mode, MR0 must be re-programmed to a prehPPR mode state if
the device is to be accessed.
After hPPR mode has been exited, the DRAM controller can confirm if the target row
was repaired correctly by writing data into the target row and reading it back.
Figure 72: hPPR WRA – Entry
7
7
7D
7D
7E
7E
7F
7F
7G
&0'
056
'(6
056
'(6
056
'(6
056
'(6
056
%*
9DOLG
1$
1$
1$
1$
&.BF
7G
7H
7I
7J
'(6
$&7
:5$
'(6
1$
%*I
%*I
1$
&.BW
%$
9DOLG
1$
1$
1$
1$
1$
%$I
%$I
1$
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9DOLG
$ 1$
VW.H\
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QG .H\
1$
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1$
9DOLG
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09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
131
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Post Package Repair
Figure 73: hPPR WRA – Repair and Exit
Te0
Tf0
CMD
ACT
BG
BGf
BA
ADDR
CK_c
Tg0
Tg1
Th0
Th1
Tj0
Tj1
Tj2
WRA
DES
DES
DES
BGf
N/A
N/A
N/A
BAf
BAf
N/A
N/A
Valid
Valid
N/A
N/A
Tk0
DES
DES
REF/DES
REF/DES
PRE
N/A
N/A
N/A
N/A
Valid
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Tk1
Tm0
Tm1
Tn0
REF/DES
MRSx
DES
Valid
N/A
Valid
N/A
Valid
Valid
N/A
Valid
N/A
Valid
Valid
N/A
Valid
(A13 = 0)
N/A
Valid
CK_t
CKE
WL = CWL+AL+PL
tWR +tRP + 1nCK
4nCK
DQS_t
DQS_c
DQs1
bit 0
All Banks
Precharged
and idle state
bit 1
bit 6
bit 7
tPGM
tRCD
hPPR Repair
tPGM_Exit
hPPR Repair
hPPR Repair
hPPR Recognition
tPGMPST
Normal
mode
hPPR Exit
Don’t Care
hPPR Row Repair – WR Initiated (REF Commands NOT Allowed)
1. Issue an ACT command with failing BG and BA with the row address to be repaired.
2. Issue a WR command with BG and BA of failing row address.
a. The address must be at valid levels, but the address is "Don't Care."
3. All DQ of the target DRAM should be driven LOW for 4nCK (bit 0 through bit 7)
after WL (WL = CWL + AL + PL) in order for hPPR to initiate repair.
a. Repair will be initiated to the target DRAM only if all DQ during bit 0 through
bit 7 are LOW.
b. Repair will not be initiated to the target DRAM if any DQ during bit 0 through
bit 7 is HIGH.
1. JEDEC states: All DQs of target DRAM should be LOW for 4tCK. If HIGH
is driven to all DQs of a DRAM consecutively for equal to or longer than
2tCK, then DRAM does not conduct hPPR and retains data if REF command is properly issued; if all DQs are neither LOW for 4tCK nor HIGH
for equal to or longer than 2tCK, then hPPR mode execution is unknown.
c. DQS should function normally.
4. REF commands may NOT be issued at anytime while in PPT mode.
5. Issue PRE after tPGM time so that the device can repair the target row during tPGM
time.
a. Wait tPGM_Exit after PRE to allow the device to recognize the repaired target
row address.
6. Issue MR4[13] 0 command to hPPR mode disable.
a. Wait tPGMPST for hPPR mode exit to complete.
b. After tPGMPST has expired, any valid command may be issued.
The entire sequence from hPPR mode enable through hPPR mode disable may be repeated if more than one repair is to be done.
After completing hPPR mode, MR0 must be re-programmed to a prehPPR mode state if
the device is to be accessed.
After hPPR mode has been exited, the DRAM controller can confirm if the target row
was repaired correctly by writing data into the target row and reading it back.
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4Gb: x4, x8, x16 DDR4 SDRAM
Post Package Repair
Figure 74: hPPR WR – Entry
7
7
7D
7D
7E
7E
7F
7F
7G
&0'
056
'(6
056
'(6
056
'(6
056
'(6
056
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9DOLG
1$
1$
1$
1$
&.BF
7G
7H
7I
7J
'(6
$&7
:5
'(6
1$
%*I
%*I
1$
&.BW
%$
9DOLG
1$
1$
1$
1$
1$
%$I
%$I
1$
$''5
9DOLG
$ 1$
VW.H\
1$
QG .H\
1$
UG .H\
1$
WK .H\
1$
9DOLG
9DOLG
1$
&.(
:/ &:/
'46BW
'46BF
'4V
1RUPDO
0RGH
W 5&'
W 02'
W 02'
W 02'
W 02'
W 02'
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Figure 75: hPPR WR – Repair and Exit
Te0
Tf0
CMD
ACT
BG
BGf
BA
ADDR
CK_c
Tg0
Tg1
Th0
Th1
Tj0
Tj1
Tj2
WR
DES
DES
DES
BGf
N/A
N/A
N/A
BAf
BAf
N/A
N/A
Valid
Valid
N/A
N/A
Tk0
DES
DES
DES
DES
PRE
N/A
N/A
N/A
N/A
Valid
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Tk1
Tm0
Tm1
Tn0
DES
MRSx
DES
Valid
N/A
Valid
N/A
Valid
Valid
N/A
Valid
N/A
Valid
Valid
N/A
Valid
(A13 = 0)
N/A
Valid
CK_t
CKE
WL = CWL + AL + PL
4nCK
DQS_t
DQS_c
DQs1
bit 0
All Banks
Precharged
and idle state
bit 1
bit 6
bit 7
tPGM
tRCD
hPPR Repair
tPGM_Exit
hPPR Repair
tPGMPST
hPPR Recognition
hPPR Repair
Normal
mode
hPPR Exit
Don’t Care
Table 41: DDR4 hPPR Timing Parameters DDR4-1600 through DDR4-3200
Parameter
hPPR programming time
hPPR precharge exit time
hPPR exit time
Symbol
tPGM
Min
Max
Unit
x4, x8
1000
–
ms
x16
2000
–
ms
tPGM_Exit
15
–
ns
tPGMPST
50
–
μs
sPPR Row Repair
Soft post package repair (sPPR) is a way to quickly, but temporarily, repair a row element in a bank on a DRAM device, where hPPR takes longer but permanently repairs a
row element. sPPR mode is entered in a similar fashion as hPPR, sPPR uses MR4[5]
while hPPR uses MR4[13]. sPPR is disabled with MR4[5] = 0, which is the normal state,
and sPPR is enabled with MR4[5] = 1, which is the sPPR enabled state.
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4Gb: x4, x8, x16 DDR4 SDRAM
Post Package Repair
sPPR requires the same guard key sequence as hPPR to qualify the MR4 PPR entry. After
sPPR entry, an ACT command will capture the target bank and target row, herein seed
row, where the row repair will be made. After tRCD time, a WR command is used to select the individual DRAM, through the DQ bits, to transfer the repair address into an internal register in the DRAM. After a write recovery time and PRE command, the sPPR
mode can be exited and normal operation can resume.
The DRAM will retain the soft repair information as long as V DD remains within the operating region unless rewritten by a subsequent sPPR entry to the same bank. If DRAM
power is removed or the DRAM is reset, the soft repair will revert to the unrepaired
state. hPPR and sPPR should not be enabled at the same time; Micron sPPR does not
have to be disabled and cleared prior to entering hPPR mode.
With sPPR, Micron DDR4 can repair one row per bank. When a subsequent sPPR request is made to the same bank, the subsequently issued sPPR address will replace the
previous sPPR address. When the hPPR resource for a bank is used up, the bank should
be assumed to not have available resources for sPPR. If a repair sequence is issued to a
bank with no repair resource available, the DRAM will ignore the programming sequence.
The bank receiving sPPR change is expected to retain memory array data in all rows except for the seed row and its associated row addresses. If the data in the memory array
in the bank under sPPR repair is not required to be retained, then the handling of the
seed row’s associated row addresses is not of interest and can be ignored. If the data in
the memory array is required to be retained in the bank under sPPR mode, then prior to
executing the sPPR mode, the seed row and its associated row addresses should be
backed up and subsequently restored after sPPR has been completed. sPPR associated
seed row addresses are specified in the Table below; BA0 is not required by Micron
DRAMs however it is JEDEC reserved.
Table 42: sPPR Associated Rows
sPPR Associated Row Address
BA0*
A17
A16
A15
A14
A13
A1
A0
All banks must be precharged and idle. DBI and CRC modes must be disabled, and all
sPPR timings must be followed as shown in the timing diagram that follows.
All other commands except those listed in the following sequences are illegal.
1. Issue MR4[5] 1 to enter sPPR mode enable.
a. All DQ are driven HIGH.
2. Issue four consecutive guard key commands (shown in the table below) to MR0
with each command separated by tMOD. Please note that JEDEC recently added
the four guard key entry used for hPPR to sPPR entry; early DRAMs may not require four guard key entry code. A prudent controller design should accommodate
either option in case an earlier DRAM is used.
a. Any interruption of the key sequence by other commands, such as ACT, WR,
RD, PRE, REF, ZQ, and NOP, are not allowed.
b. If the guard key bits are not entered in the required order or interrupted with
other MR commands, sPPR will not be enabled, and the programming cycle
will result in a NOP.
c. When the sPPR entry sequence is interrupted and followed by ACT and WR
commands, these commands will be conducted as normal DRAM commands.
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4Gb: x4, x8, x16 DDR4 SDRAM
Post Package Repair
d. JEDEC allows A6:0 to be "Don't Care" on 4Gb and 8Gb devices from a supplier perspective and the user should rely on vendor datasheet.
Table 43: PPR MR0 Guard Key Settings
MR0
BG1:0
BA1:0
A17:12
A11
A10
A9
A8
A7
A6:0
First guard key
0
0
xxxxxx
1
1
0
0
1
1111111
Second guard key
0
0
xxxxxx
0
1
1
1
1
1111111
Third Guard key
0
0
xxxxxx
1
0
1
1
1
1111111
Fourth guard key
0
0
xxxxxx
0
0
1
1
1
1111111
3. After tMOD, issue an ACT command with failing BG and BA with the row address
to be repaired.
4. After tRCD, issue a WR command with BG and BA of failing row address.
a. The address must be at valid levels, but the address is a "Don't Care."
5. All DQ of the target DRAM should be driven LOW for 4nCK (bit 0 through bit 7)
after WL (WL = CWL + AL + PL) in order for sPPR to initiate repair.
a. Repair will be initiated to the target DRAM only if all DQ during bit 0 through
bit 7 are LOW.
b. Repair will not be initiated to the target DRAM if any DQ during bit 0 through
bit 7 is HIGH.
1. JEDEC states: All DQs of target DRAM should be LOW for 4tCK. If HIGH
is driven to all DQs of a DRAM consecutively for equal to or longer than
the first 2tCK, then DRAM does not conduct hPPR and retains data if
REF command is properly issued; if all DQs are neither LOW for 4tCK
nor HIGH for equal to or longer than the first 2tCK, then hPPR mode execution is unknown.
c. DQS should function normally.
6. REF command may NOT be issued at anytime while in sPPR mode.
7. Issue PRE after tWR time so that the device can repair the target row during tWR
time.
a. Wait tPGM_Exit_s after PRE to allow the device to recognize the repaired target row address.
8. Issue MR4[5] 0 command to sPPR mode disable.
a. Wait tPGMPST_s for sPPR mode exit to complete.
b. After tPGMPST_s has expired, any valid command may be issued.
The entire sequence from sPPR mode enable through sPPR mode disable may be repeated if more than one repair is to be done.
After sPPR mode has been exited, the DRAM controller can confirm if the target row
was repaired correctly by writing data into the target row and reading it back.
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4Gb: x4, x8, x16 DDR4 SDRAM
Post Package Repair
Figure 76: sPPR – Entry
7
7
7D
7D
7E
7E
7F
7F
7G
&0'
056
'(6
056
'(6
056
'(6
056
'(6
056
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9DOLG
1$
1$
1$
1$
&.BF
7G
7H
7I
'(6
$&7
:5
1$
%*I
7J
&.BW
'(6
1$
%*I
%$
9DOLG
1$
1$
1$
1$
1$
%$I
%$I
1$
$''5
9DOLG
$ 1$
VW.H\
1$
QG .H\
1$
UG .H\
1$
WK .H\
1$
9DOLG
9DOLG
1$
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W 02'
W 02'
W 02'
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V3355HSDLU
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Figure 77: sPPR – Repair, and Exit
Te0
Tf0
CMD
ACT
BG
BGf
BA
ADDR
CK_c
Tg0
Tg1
Th0
Th1
Tj0
Tj1
Tj2
Tk0
WR
DES
DES
DES
DES
DES
DES
DES
PRE
BGf
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Valid
BAf
BAf
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Valid
Valid
Valid
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Valid
Tk1
Tm0
Tm1
Tn0
DES
MRS4
DES
Valid
N/A
Valid
N/A
Valid
N/A
Valid
N/A
Valid
N/A
Valid
(A5=0)
N/A
Valid
CK_t
CKE
WL = CWL + AL + PL
tWR
4nCK
DQS_t
DQS_c
DQs1
bit 0
All Banks
Precharged
and idle state
bit 1
bit 6
bit 7
tPGM_s
tRCD
sPPR Repair
sPPR Repair
tPGM_Exit_s
sPPR Repair
tPGMPST_s
sPPR Recognition
sPPR Repair
Normal
Mode
sPPR Exit
Don’t Care
Table 44: DDR4 sPPR Timing Parameters DDR4-1600 through DDR4-3200
Parameter
Symbol
Max
Unit
RCD (MIN)+ WL + 4nCK
+ tWR (MIN)
–
ns
sPPR programming time
sPPR precharge exit time
tPGM_Exit_s
20
–
ns
tPGMPST_s
tMOD
–
ns
sPPR exit time
t
Min
tPGM_s
hPPR/sPPR Support Identifier
Table 45: DDR4 Repair Mode Support Identifier
MPR Page 2
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
A7
A6
A5
A4
A3
A2
A1
A0
UI0
UI1
UI2
UI3
UI4
UI5
UI6
UI7
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4Gb: x4, x8, x16 DDR4 SDRAM
Post Package Repair
Table 45: DDR4 Repair Mode Support Identifier (Continued)
MPR0
hPPR1
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
sPPR2
RTT_WR
Temp sensor
CRC
RTT_WR
1. 0 = hPPR mode is not available, 1 = hPPR mode is available.
2. 0 = sPPR mode is not available, 1 = sPPR mode is available.
3. Gray shaded areas are for reference only.
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4Gb: x4, x8, x16 DDR4 SDRAM
Excessive Row Activation
Excessive Row Activation
Rows can be accessed a limited number of times within a certain time period before adjacent rows require refresh. The maximum activate count (MAC) is the maximum number of activates that a single row can sustain within a time interval of equal to or less
than the maximum activate window (tMAW) before the adjacent rows need to be refreshed, regardless of how the activates are distributed over tMAW.
Micron's DDR4 devices automatically perform a type of TRR mode in the background
and provide an MPR Page 3 MPR3[3:0] of 1000, indicating there is no restriction to the
number of ACTIVATE commands to a given row in a refresh period provided DRAM timing specifications are not violated.
Table 46: MAC Encoding of MPR Page 3 MPR3
[7] [6] [5] [4] [3] [2] [1] [0]
x
x
x
0
0
0
0
Untested
x
x
x
x
0
0
0
1
tMAC
x
x
x
x
0
0
1
0
tMAC
= 600K
x
x
x
x
0
0
1
1
tMAC
= 500K
0
tMAC
= 400K
tMAC
= 300K
x
Note:
x
MAC
x
x
x
0
1
0
= 700K
x
x
x
x
0
1
0
1
x
x
x
x
0
1
1
0
x
x
x
x
0
1
1
1
x
x
x
x
1
0
0
0
Unlimited
x
x
x
x
1
0
0
1
Reserved
x
x
x
x
:
:
:
:
Reserved
x
x
x
x
1
1
1
1
Reserved
Comments
The device has not been tested for MAC.
Reserved
tMAC
= 200K
There is no restriction to the number of ACTIVATE commands to a given row in a refresh period provided DRAM timing specifications are not violated.
1. MAC encoding in MPR Page 3 MPR3.
ACTIVATE Command
The ACTIVATE command is used to open (activate) a row in a particular bank for subsequent access. The values on the BG[1:0] inputs select the bank group, the BA[1:0] inputs
select the bank within the bank group, and the address provided on inputs A[17:0] selects the row within the bank. This row remains active (open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. Bank-to-bank command timing for ACTIVATE commands uses two different timing parameters, depending on whether the
banks are in the same or different bank group. tRRD_S (short) is used for timing between banks located in different bank groups. tRRD_L (long) is used for timing between
banks located in the same bank group. Another timing restriction for consecutive ACTIVATE commands [issued at tRRD (MIN)] is tFAW (fifth activate window). Because there
is a maximum of four banks in a bank group, the tFAW parameter applies across differ-
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4Gb: x4, x8, x16 DDR4 SDRAM
PRECHARGE Command
ent bank groups (five ACTIVATE commands issued at tRRD_L (MIN) to the same bank
group would be limited by tRC).
Figure 78: tRRD Timing
CK_c
CK_t
Command
T0
T1
ACT
DES
T2
T3
T4
T5
T6
DES
DES
ACT
DES
DES
T8
T9
T10
T11
DES
DES
DES
ACT
DES
tRRD_L
tRRD_S
Bank
Group
(BG)
T7
BG a
BG b
BG b
Bank
Bank c
Bank c
Bank d
Address
Row n
Row n
Row n
Don’t Care
Notes:
1. tRRD_S; ACTIVATE-to-ACTIVATE command period (short); applies to consecutive ACTIVATE commands to different bank groups (that is, T0 and T4).
2. tRRD_L; ACTIVATE-to-ACTIVATE command period (long); applies to consecutive ACTIVATE commands to the different banks in the same bank group (that is, T4 and T10).
Figure 79: tFAW Timing
CK_c
CK_t
Command
T0
ACT
Ta0
Valid
ACT
tRRD
Tb0
Valid
ACT
tRRD
Valid
Tc0
Tc1
Tc2
ACT
Valid
Valid
tRRD
Valid
Td0
Td1
ACT
NOP
tFAW
Bank
Group
(BG)
Valid
Valid
Valid
Valid
Valid
Bank
Valid
Valid
Valid
Valid
Valid
Address
Valid
Valid
Valid
Valid
Valid
Don’t Care
Note:
Time Break
1. tFAW; four activate windows.
PRECHARGE Command
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row activation
for a specified time (tRP) after the PRECHARGE command is issued. An exception to
this is the case of concurrent auto precharge, where a READ or WRITE command to a
different bank is allowed as long as it does not interrupt the data transfer in the current
bank and does not violate any other timing parameters.
After a bank is precharged, it is in the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank. A PRECHARGE command is allowed if
there is no open row in that bank (idle state) or if the previously open row is already in
the process of precharging. However, the precharge period will be determined by the
last PRECHARGE command issued to the bank.
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4Gb: x4, x8, x16 DDR4 SDRAM
REFRESH Command
The auto precharge feature is engaged when a READ or WRITE command is issued with
A10 HIGH. The auto precharge feature uses the RAS lockout circuit to internally delay
the PRECHARGE operation until the ARRAY RESTORE operation has completed. The
RAS lockout circuit feature allows the PRECHARGE operation to be partially or completely hidden during burst READ cycles when the auto precharge feature is engaged.
The PRECHARGE operation will not begin until after the last data of the burst write sequence is properly stored in the memory array.
REFRESH Command
The REFRESH command (REF) is used during normal operation of the device. This
command is nonpersistent, so it must be issued each time a refresh is required. The device requires REFRESH cycles at an average periodic interval of tREFI. When CS_n,
RAS_n/A16, and CAS_n/A15 are held LOW and WE_n/A14 HIGH at the rising edge of
the clock, the device enters a REFRESH cycle. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time, tRP (MIN), before the REFRESH
command can be applied. The refresh addressing is generated by the internal DRAM refresh controller. This makes the address bits “Don’t Care” during a REFRESH command.
An internal address counter supplies the addresses during the REFRESH cycle. No control of the external address bus is required once this cycle has started. When the REFRESH cycle has completed, all banks of the SDRAM will be in the precharged (idle)
state. A delay between the REFRESH command and the next valid command, except
DES, must be greater than or equal to the minimum REFRESH cycle time tRFC (MIN),
as shown in Figure 80 (page 141).
Note: The tRFC timing parameter depends on memory density.
In general, a REFRESH command needs to be issued to the device regularly every tREFI
interval. To allow for improved efficiency in scheduling and switching between tasks,
some flexibility in the absolute refresh interval is provided for postponing and pullingin the REFRESH command. A limited number REFRESH commands can be postponed
depending on refresh mode: a maximum of 8 REFRESH commands can be postponed
when the device is in 1X refresh mode; a maximum of 16 REFRESH commands can be
postponed when the device is in 2X refresh mode; and a maximum of 32 REFRESH
commands can be postponed when the device is in 4X refresh mode.
When 8 consecutive REFRESH commands are postponed, the resulting maximum interval between the surrounding REFRESH commands is limited to 9 × tREFI (see Figure 81
(page 141)). For both the 2X and 4X refresh modes, the maximum consecutive REFRESH commands allowed is limited to 17 × tREFI2 and 36 × tREFI4, respectively.
A limited number REFRESH commands can be pulled-in as well. A maximum of 8 additional REFRESH commands can be issued in advance or “pulled-in” in 1X refresh mode,
a maximum of 16 additional REFRESH commands can be issued when in advance in 2X
refresh mode, and a maximum of 32 additional REFRESH commands can be issued in
advance when in 4X refresh mode. Each of these REFRESH commands reduces the
number of regular REFRESH commands required later by one. Note that pulling in
more than the maximum allowed REFRESH commands in advance does not further reduce the number of regular REFRESH commands required later, so that the resulting
maximum interval between two surrounding REFRESH commands is limited to 9 × tREFI (Figure 82 (page 141)), 18 × tRFEI2, or 36 × tREFI4. At any given time, a maximum of
16 REF commands can be issued within 2 × tREFI, 32 REF2 commands can be issued
within 4 × tREFI2, and 64 REF4 commands can be issued within 8 × tREFI4.
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4Gb: x4, x8, x16 DDR4 SDRAM
REFRESH Command
Figure 80: REFRESH Command Timing
CK_c
T0
T1
REF
DES
Ta0
Ta1
Tb0
Tb1
Tb2
Tb3
Valid
Valid
Valid
Valid
Tc0
Tc1
Tc2
Tc3
REF
Valid
Valid
Valid
CK_t
Command
DES
REF
tRFC
DES
DES
tRFC
Valid
(MIN)
tREFI
(MAX 9 × tREFI)
DRAM must be idle
DRAM must be idle
Time Break
Notes:
Don’t Care
1. Only DES commands are allowed after a REFRESH command is registered until tRFC
(MIN) expires.
2. Time interval between two REFRESH commands may be extended to a maximum of 9 ×
tREFI.
Figure 81: Postponing REFRESH Commands (Example)
tREFI
9 × tREFI
W
tRFC
8 REF-Commands postponed
Figure 82: Pulling In REFRESH Commands (Example)
9 × tREFI
tREFI
W
tRFC
8 REF-Commands pulled-in
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4Gb: x4, x8, x16 DDR4 SDRAM
Temperature-Controlled Refresh Mode
Temperature-Controlled Refresh Mode
During normal operation, temperature-controlled refresh (TCR) mode disabled, the device must have a REFRESH command issued once every tREFI, except for what is allowed by posting (see REFRESH Command section). This means a REFRESH command
must be issued once every 3.9μs if T C is greater than or equal to 85°C, and once every
7.8μs if T C is less than 85°C. This Mode is disabled setting MR4[3] = 0 while mode is enabled setting MR4[3] = 1. When enabled (MR4[3] = 1), the temperature range must be selected where MR4[2] = 0 enables the Normal Temperature range while MR4[2] = 1 enables the Extended Temperature range
Table 47: Normal tREFI Refresh (TCR Disabled)
Normal Temperature
Temperature
External Refresh
Period
Internal Refresh
Period
7.8μs
7.8μs
TC < 45°C
45°C ≤ TC < 85°C
85°C ≤ TC < 95°C
Extended Temperature
External Refresh
Period
Internal Refresh
Period
3.9μs1
3.9μs1
N/A
Note:
1. If TC is less than 85°C, the external refresh period can be 7.8μs instead of 3.9μs.
When TCR mode is enabled, the device will register the externally supplied REFRESH
command and adjust the internal refresh period to be longer than tREFI of the normal
temperature range, when allowed, by skipping REFRESH commands with the proper
gear ratio. TCR mode has two ranges to select between the normal temperature range
and the extended temperature range; the correct range must be selected so the internal
control operates correctly. The DRAM must have the correct refresh rate applied externally; the internal refresh rate is determined by the DRAM based upon the temperature.
TCR Mode – Normal Temperature Range
REFRESH commands should be issued to the device with the refresh period equal to or
shorter than tREFI of normal temperature range (0°C to 85°C). In this mode, the system
must guarantee that the T C does not exceed 85°C. The device may adjust the internal
refresh period to be longer than tREFI of the normal temperature range by skipping external REFRESH commands with the proper gear ratio when T C is below 45°C. The internal refresh period is automatically adjusted inside the DRAM, and the DRAM controller does not need to provide any additional control.
TCR Mode – Extended Temperature Range
REFRESH commands should be issued to the device with the refresh period equal to or
shorter than tREFI of extended temperature range (85°C to 95°C). In this mode, the system must guarantee that the T C does not exceed 95°C. Even though the external refresh
supports the extended temperature range, the device will adjust its internal refresh period to tREFI of the normal temperature range by skipping external REFRESH commands
with proper gear ratio when operating in the normal temperature range (0°C to 85°C).
The device may adjust the internal refresh period to be longer than tREFI of the normal
temperature range by skipping external REFRESH commands with the proper gear ratio
when T C is below 45°C. The internal refresh period is automatically adjusted inside the
DRAM, and the DRAM controller does not need to provide any additional control.
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4Gb: x4, x8, x16 DDR4 SDRAM
Temperature-Controlled Refresh Mode
Table 48: Normal tREFI Refresh (TCR Enabled)
Normal Temperature Range
Extended Temperature Range
Temperature
External Refresh
Period
Internal Refresh
Period
TC < 45°C
7.8μs
> 7.8μs
45°C ≤ TC < 85°C
7.8μs
85°C ≤ TC < 95°C
External Refresh
Period
>>3.9μs
3.9μs1
7.8μs
>3.9μs
N/A
Note:
Internal Refresh
Period
3.9μs
1. If the external refresh period is slower than 3.9μs, the device will refresh internally at
too slow of a refresh rate and will violate refresh specifications.
Figure 83: TCR Mode Example1
Controller
External
tREFI
<3.9μs
REFRESH
Internal
tREFI
3.9μs
REFRESH
95°C to 85°C
85°C to 45°C
Below 45°C
REFRESH
REFRESH
REFRESH
REFRESH
Internal
tREFI
>3.9μs
Internal
tREFI
REFRESH
REFRESH
REFRESH
REFRESH
REFRESH
REFRESH
REFRESH
REFRESH
REFRESH
REFRESH
REFRESH
Controller issues REFRESH
commands at extended
temperature rate
External REFRESH
commands are not
ignored
Every other
external REFRESH
ignored
At low temperature,
more REFRESH commands
can be ignored
Note:
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REFRESH
>>3.9μs
REFRESH
REFRESH
REFRESH
1. TCR enabled with extended temperature range selected.
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4Gb: x4, x8, x16 DDR4 SDRAM
Fine Granularity Refresh Mode
Fine Granularity Refresh Mode
Mode Register and Command Truth Table
The REFRESH cycle time (tRFC) and the average refresh interval (tREFI) can be programmed by the MRS command. The appropriate setting in the mode register will set a
single set of REFRESH cycle times and average refresh interval for the device (fixed
mode), or allow the dynamic selection of one of two sets of REFRESH cycle times and
average refresh interval for the device (on-the-fly mode [OTF]). OTF mode must be enabled by MRS before any OTF REFRESH command can be issued.
Table 49: MRS Definition
MR3[8]
MR3[7]
MR3[6]
Refresh Rate Mode
0
0
0
Normal mode (fixed 1x)
0
0
1
Fixed 2x
0
1
0
Fixed 4x
0
1
1
Reserved
1
0
0
Reserved
1
0
1
On-the-fly 1x/2x
1
1
0
On-the-fly 1x/4x
1
1
1
Reserved
There are two types of OTF modes (1x/2x and 1x/4x modes) that are selectable by programming the appropriate values into the mode register MR3 [8:6]. When either of the
two OTF modes is selected, the device evaluates the BG0 bit when a REFRESH command is issued, and depending on the status of BG0, it dynamically switches its internal
refresh configuration between 1x and 2x (or 1x and 4x) modes, and then executes the
corresponding REFRESH operation.
Table 50: REFRESH Command Truth Table
Refresh
RAS_n/A CAS_n/A
15
14
WE_n/
A13
BG1
BG0
A10/
AP
A[9:0],
A[12:11],
A[20:16]
MR3[8:6
]
CS_n
ACT_n
Fixed rate
L
H
L
L
H
V
V
V
V
0vv
OTF: 1x
L
H
L
L
H
V
L
V
V
1vv
OTF: 2x
L
H
L
L
H
V
H
V
V
101
OTF: 4x
L
H
L
L
H
V
H
V
V
110
tREFI
and tRFC Parameters
The default refresh rate mode is fixed 1x mode where REFRESH commands should be
issued with the normal rate; that is, tREFI1 = tREFI(base) (for T C ≤ 85°C), and the duration of each REFRESH command is the normal REFRESH cycle time (tRFC1). In 2x
mode (either fixed 2x or OTF 2x mode), REFRESH commands should be issued to the
device at the double frequency (tREFI2 = tREFI(base)/2) of the normal refresh rate. In 4x
mode, the REFRESH command rate should be quadrupled (tREFI4 = tREFI(base)/4). Per
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4Gb: x4, x8, x16 DDR4 SDRAM
Fine Granularity Refresh Mode
each mode and command type, the tRFC parameter has different values as defined in
the following table.
For discussion purposes, the REFRESH command that should be issued at the normal
refresh rate and has the normal REFRESH cycle duration may be referred to as an REF1x
command. The REFRESH command that should be issued at the double frequency
(tREFI2 = tREFI(base)/2) may be referred to as a REF2x command. Finally, the REFRESH
command that should be issued at the quadruple rate (tREFI4 = tREFI(base)/4) may be
referred to as a REF4x command.
In the fixed 1x refresh rate mode, only REF1x commands are permitted. In the fixed 2x
refresh rate mode, only REF2x commands are permitted. In the fixed 4x refresh rate
mode, only REF4x commands are permitted. When the on-the-fly 1x/2x refresh rate
mode is enabled, both REF1x and REF2x commands are permitted. When the OTF
1x/4x refresh rate mode is enabled, both REF1x and REF4x commands are permitted.
Table 51: tREFI and tRFC Parameters
Refresh
Mode
Parameter
tREFI
1x mode
2Gb
(base)
tREFI1
2x mode
4x mode
tRFC4
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16Gb
Units
μs
7.8
7.8
7.8
7.8
tREFI(base)
tREFI(base)
tREFI(base)
μs
85°C ≤ TC ≤ 95°C
tREFI(base)/2
tREFI(base)/2
tREFI(base)/2
tREFI(base)/2
μs
160
260
350
550
ns
0°C ≤ TC ≤ 85°C
tREFI(base)/2
tREFI(base)/2
tREFI(base)/2
tREFI(base)/2
μs
85°C ≤ TC ≤ 95°C
tREFI(base)/4
tREFI(base)/4
tREFI(base)/4
tREFI(base)/4
μs
110
160
260
350
ns
0°C ≤ TC ≤ 85°C
tREFI(base)/4
tREFI(base)/4
tREFI(base)/4
tREFI(base)/4
μs
85°C ≤ TC ≤ 95°C
tREFI(base)/8
tREFI(base)/8
tREFI(base)/8
tREFI(base)/8
μs
90
110
160
260
ns
0°C ≤ TC ≤ 85°C
tRFC2
tREFI4
8Gb
tREFI(base)
tRFC1
tREFI2
4Gb
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Extended Temperature Operation – 0°C to 95°C
Normal Temperature Operation – 0°C to 85°C
2x Mode
(0°C to 85°C)
4x Mode
(0°C to 85°C)
1x Mode
(0°C to 95°C)
2x Mode
(0°C to 95°C)
4x Mode
(0°C to 95°C)
REF@260ns
REF@160ns
REF@110ns
REF@260ns
REF@160ns
REF@110ns
97
0.
=
μs
=
s
5μ
1.
Rt E
FI
95
FI
REF@110ns
s
s
5μ
=
1.
Rt E
FI
95
=
μs
0.
FI
Rt E
REF@260ns
REF@160ns
s
5μ
REF@110ns
REF@110ns
=
μs
5μ
97
0.
=
s
FI
9μ
5μ
=
FI
5μ
s
Rt E
95
1.
=
97
FI
REF@110ns
REF@160ns
5μ
REF@260ns
REF@110ns
97
REF@110ns
=
FI
μs
5μ
97
0.
=
FI
5μ
s
Rt E
=
s
97
REF@160ns
5μ
REF@260ns
REF@110ns
97
REF@110ns
FI
μs
=
s
5μ
1.
Rt E
95
s
=
Rt E
0.
FI
REF@110ns
97
μs
95
1.
=
FI
Rt E
s
Rt E
FI
9μ
3.
=
5μ
s
9μ
3.
97
REF@110ns
0.
REF@160ns
FI
5μ
97
0.
=
Rt E
FI
Rt E
s
Rt E
REF@110ns
Rt E
FI
FI
=
=
1.
1.
95
95
μs
μs
=
FI
REF@110ns
Rt E
=
FI
Rt E
=
0.
REF@160ns
s
Rt E
Rt E
FI
FI
=
Rt E
0.
FI
=
FI
Rt E
5μ
1.
Rt E
95
FI
μs
=
0.
97
FI
μs
95
1.
s
8μ
7.
REF@110ns
REF@260ns
REF@160ns
REF@110ns
REF@260ns
REF@160ns
REF@110ns
4Gb: x4, x8, x16 DDR4 SDRAM
Fine Granularity Refresh Mode
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=
s
Rt E
95
1.
FI
Rt E
s
9μ
3.
REF@110ns
REF@160ns
Rt E
FI
REF@110ns
Rt E
REF@110ns
=
=
3.
9μ
s
Rt E
FI
=
1.
95
μs
0.
REF@160ns
=
146
REF@260ns
s
Rt E
FI
=
0.
Rt E
Rt E
FI
=
1.
95
μs
0.
97
FI
Rt E
s
Rt E
3.
REF@110ns
REF@160ns
μs
Rt E
FI
REF@110ns
s
Rt E
FI
95
1.
=
Rt E
FI
REF@110ns
=
=
3.
9μ
s
Rt E
FI
=
1.
95
Rt E
μs
FI
0.
97
REF@160ns
=
7.
8μ
s
Rt E
FI
=
0.
97
FI
REF@110ns
Rt E
FI
=
1.
95
μs
97
REF@110ns
REF@160ns
Rt E
5μ
=
Rt E
3.
FI
9μ
=
s
0.
Rt E
97
95
1.
=
FI
Rt E
s
9μ
3.
=
FI
REF@110ns
Rt E
5μ
s
1x Mode
(0°C to 85°C)
μs
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Figure 84: 4Gb with Fine Granularity Refresh Mode Example
4Gb: x4, x8, x16 DDR4 SDRAM
Fine Granularity Refresh Mode
Changing Refresh Rate
If the refresh rate is changed by either MRS or OTF. New tREFI and tRFC parameters will
be applied from the moment of the rate change. When the REF1x command is issued to
the DRAM, tREF1 and tRFC1 are applied from the time that the command was issued;
when the REF2x command is issued, tREF2 and tRFC2 should be satisfied.
Figure 85: OTF REFRESH Command Timing
CK_c
CK_t
Command
DES
REF1
DES
DES
tRFC1
DES
Valid
Valid
REF2
DES
tRFC2
(MIN)
tREFI1
DES
Valid
DES
REF2
DES
(MIN)
tREFI2
Don’t Care
The following conditions must be satisfied before the refresh rate can be changed. Otherwise, data retention cannot be guaranteed.
• In the fixed 2x refresh rate mode or the OTF 1x/2x refresh mode, an even number of
REF2x commands must be issued because the last change of the refresh rate mode
with an MRS command before the refresh rate can be changed by another MRS command.
• In the OTF1x/2x refresh rate mode, an even number of REF2x commands must be issued between any two REF1x commands.
• In the fixed 4x refresh rate mode or the OTF 1x/4x refresh mode, a multiple-of-four
number of REF4x commands must be issued because the last change of the refresh
rate with an MRS command before the refresh rate can be changed by another MRS
command.
• In the OTF1x/4x refresh rate mode, a multiple-of-four number of REF4x commands
must be issued between any two REF1x commands.
There are no special restrictions for the fixed 1x refresh rate mode. Switching between
fixed and OTF modes keeping the same rate is not regarded as a refresh rate change.
Usage with TCR Mode
If the temperature controlled refresh mode is enabled, only the normal mode (fixed 1x
mode, MR3[8:6] = 000) is allowed. If any other refresh mode than the normal mode is
selected, the temperature controlled refresh mode must be disabled.
Self Refresh Entry and Exit
The device can enter self refresh mode anytime in 1x, 2x, and 4x mode without any restriction on the number of REFRESH commands that have been issued during the
mode before the self refresh entry. However, upon self refresh exit, extra REFRESH command(s) may be required, depending on the condition of the self refresh entry.
The conditions and requirements for the extra REFRESH command(s) are defined as
follows:
• In the fixed 2x refresh rate mode or the enable-OTF 1x/2x refresh rate mode, it is recommended there be an even number of REF2x commands before entry into self refresh after the last self refresh exit, REF1x command, or MRS command that set the
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4Gb: x4, x8, x16 DDR4 SDRAM
Fine Granularity Refresh Mode
refresh mode. If this condition is met, no additional REFRESH commands are required upon self refresh exit. In the case that this condition is not met, either one extra REF1x command or two extra REF2x commands must be issued upon self refresh
exit. These extra REFRESH commands are not counted toward the computation of the
average refresh interval (tREFI).
• In the fixed 4x refresh rate mode or the enable-OTF 1x/4x refresh rate mode, it is recommended there be a multiple-of-four number of REF4x commands before entry into self refresh after the last self refresh exit, REF1x command, or MRS command that
set the refresh mode. If this condition is met, no additional refresh commands are required upon self refresh exit. When this condition is not met, either one extra REF1x
command or four extra REF4x commands must be issued upon self refresh exit. These
extra REFRESH commands are not counted toward the computation of the average
refresh interval (tREFI).
There are no special restrictions on the fixed 1x refresh rate mode.
This section does not change the requirement regarding postponed REFRESH commands. The requirement for the additional REFRESH command(s) described above is
independent of the requirement for the postponed REFRESH commands.
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SELF REFRESH Operation
SELF REFRESH Operation
The SELF REFRESH command can be used to retain data in the device, even if the rest
of the system is powered down. When in self refresh mode, the device retains data without external clocking. The device has a built-in timer to accommodate SELF REFRESH
operation. The SELF REFRESH command is defined by having CS_n, RAS_n, CAS_n,
and CKE held LOW with WE_n and ACT_n HIGH at the rising edge of the clock.
Before issuing the SELF REFRESH ENTRY command, the device must be idle with all
banks in the precharge state and tRP satisfied. Idle state is defined as: All banks are
closed (tRP, tDAL, and so on, satisfied), no data bursts are in progress, CKE is HIGH, and
all timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper,
tZQCS, and so on). After the SELF REFRESH ENTRY command is registered, CKE must
be held LOW to keep the device in self refresh mode. The DRAM automatically disables
ODT termination, regardless of the ODT pin, when it enters self refresh mode and automatically enables ODT upon exiting self refresh. During normal operation (DLL_on),
the DLL is automatically disabled upon entering self refresh and is automatically enabled (including a DLL reset) upon exiting self refresh.
When the device has entered self refresh mode, all of the external control signals, except
CKE and RESET_n, are “Don’t Care.” For proper SELF REFRESH operation, all power
supply and reference pins (VDD, V DDQ, V SS, V SSQ, V PP, and V REFCA) must be at valid levels.
The DRAM internal V REFDQ generator circuitry may remain on or be turned off depending on the MRx bit Y setting. If the internal V REFDQ circuit is on in self refresh, the first
WRITE operation or first write-leveling activity may occur after tXS time after self refresh exit. If the DRAM internal V REFDQ circuitry is turned off in self refresh, it ensures
that the V REFDQ generator circuitry is powered up and stable within the tXSDLL period
when the DRAM exits the self refresh state. The first WRITE operation or first write-leveling activity may not occur earlier than tXSDLL after exiting self refresh. The device initiates a minimum of one REFRESH command internally within the tCKE period once it
enters self refresh mode.
The clock is internally disabled during a SELF REFRESH operation to save power. The
minimum time that the device must remain in self refresh mode is tCKESR/
tCKESR_PAR. The user may change the external clock frequency or halt the external
clock tCKSRE/tCKSRE_PAR after self refresh entry is registered; however, the clock must
be restarted and tCKSRX must be stable before the device can exit SELF REFRESH operation.
The procedure for exiting self refresh requires a sequence of events. First, the clock must
be stable prior to CKE going back HIGH. Once a SELF REFRESH EXIT command (SRX,
combination of CKE going HIGH and DESELECT on the command bus) is registered,
the following timing delay must be satisfied:
Commands that do not require locked DLL:
• tXS = ACT, PRE, PREA, REF, SRE, and PDE.
• tXS_FAST = ZQCL, ZQCS, and MRS commands. For an MRS command, only DRAM
CL, WR/RTP register, and DLL reset in MR0; R TT(NOM) register in MR1; the CWL and
RTT(WR) registers in MR2; and gear-down mode register in MR3; WRITE and READ preamble registers in MR4; RTT(PARK) register in MR5; tCCD_L/tDLLK and V REFDQ calibration value registers in MR6 may be accessed provided the DRAM is not in per-DRAM
mode. Access to other DRAM mode registers must satisfy tXS timing. WRITE commands (WR, WRS4, WRS8, WRA, WRAS4, and WRAS8) that require synchronous ODT
and dynamic ODT controlled by the WRITE command require a locked DLL.
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4Gb: x4, x8, x16 DDR4 SDRAM
SELF REFRESH Operation
Commands that require locked DLL in the normal operating range:
• tXSDLL – RD, RDS4, RDS8, RDA, RDAS4, and RDAS8 (unlike DDR3, WR, WRS4, WRS8,
WRA, WRAS4, and WRAS8 because synchronous ODT is required).
Depending on the system environment and the amount of time spent in self refresh, ZQ
CALIBRATION commands may be required to compensate for the voltage and temperature drift described in the ZQ CALIBRATION Commands section. To issue ZQ CALIBRATION commands, applicable timing requirements must be satisfied (see the ZQ Calibration Timing figure).
CKE must remain HIGH for the entire self refresh exit period tXSDLL for proper operation except for self refresh re-entry. Upon exit from self refresh, the device can be put
back into self refresh mode or power-down mode after waiting at least tXS period and
issuing one REFRESH command (refresh period of tRFC). The DESELECT command
must be registered on each positive clock edge during the self refresh exit interval tXS.
ODT must be turned off during tXSDLL.
The use of self refresh mode introduces the possibility that an internally timed refresh
event can be missed when CKE is raised for exit from self refresh mode. Upon exit from
self refresh, the device requires a minimum of one extra REFRESH command before it is
put back into self refresh mode.
Figure 86: Self Refresh Entry/Exit Timing
T0
T1
Ta0
Tb0
Tc0
Td0
Td1
Te0
Tf0
Tg0
Valid
Valid
Valid
CK_c
CK_t
tCKSRX
tCKSRE/tCKSRE_PAR
tIS
tCPDED
CKE
tCKESR/tCKESR_PAR
Valid
ODT
tXS_FAST
Command
DES
SRE
SRX
DES
ADDR
Valid 1
Valid 2
Valid 3
Valid
Valid
Valid
tXS
tRP
tXSDLL
Enter Self Refresh
Exit Self Refresh
Don’t Care
Notes:
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Time Break
1. Only MRS (limited to those described in the SELF REFRESH Operation section), ZQCS, or
ZQCL commands are allowed.
2. Valid commands not requiring a locked DLL.
3. Valid commands requiring a locked DLL.
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4Gb: x4, x8, x16 DDR4 SDRAM
SELF REFRESH Operation
Figure 87: Self Refresh Entry/Exit Timing with CAL Mode
7
7
7
7
7
7
7
7D
7D
7D
7D
7D 7E
7E
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7E
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1. tCAL = 3nCK, tCPDED = 4nCK, tCKSRE/tCKSRE_PAR = 8nCK, tCKSRX = 8nCK, tXS_FAST =
tREFC4 (MIN) + 10ns.
2. CS_n = HIGH, ACT_n = "Don't Care," RAS_n/A16 = "Don't Care," CAS_n/A15 = "Don't
Care," WE_n/A14 = "Don't Care."
3. Only MRS (limited to those described in the SELF REFRESH Operations section), ZQCS, or
ZQCL commands are allowed.
Notes:
Self Refresh Abort
The exit timing from self refresh exit to the first valid command not requiring a locked
DLL is tXS. The value of tXS is (tRFC + 10ns). This delay allows any refreshes started by
the device time to complete. tRFC continues to grow with higher density devices, so tXS
will grow as well. An MRS bit enables the self refresh abort mode. If the bit is disabled,
the controller uses tXS timings (location MR4, bit 9). If the bit is enabled, the device
aborts any ongoing refresh and does not increment the refresh counter. The controller
can issue a valid command not requiring a locked DLL after a delay of tXS_ABORT.
Upon exit from self refresh, the device requires a minimum of one extra REFRESH command before it is put back into self refresh mode. This requirement remains the same
irrespective of the setting of the MRS bit for self refresh abort.
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4Gb: x4, x8, x16 DDR4 SDRAM
SELF REFRESH Operation
Figure 88: Self Refresh Abort
T0
T1
Ta0
Tb0
Tc0
Td0
Td1
Te0
Tf0
Tg0
Valid
Valid
Valid
CK_c
CK_t
tCKSRX
tCKSRE/tCKSRE_PAR
tIS
tCPDED
CKE
tCKESR/tCKESR_PAR
ODT
Valid
tXS_FAST
Command
DES
SRE
SRX
DES
ADDR
Valid 1
Valid 2
Valid 3
Valid
Valid
Valid
tXS_ABORT
tRP
tXSDLL
Enter Self Refresh
Exit Self Refresh
Don’t Care
Notes:
Time Break
1. Only MRS (limited to those described in the SELF REFRESH Operation section), ZQCS, or
ZQCL commands are allowed.
2. Valid commands not requiring a locked DLL with self refresh abort mode enabled in the
mode register.
3. Valid commands requiring a locked DLL.
Self Refresh Exit with NOP Command
Exiting self refresh mode using the NO OPERATION command (NOP) is allowed under a
specific system application. This special use of NOP allows for a common command/
address bus between active DRAM devices and DRAM(s) in maximum power saving
mode. Self refresh mode may exit with NOP commands provided:
• The device entered self refresh mode with CA parity and CAL disabled.
• tMPX_S and tMPX_LH are satisfied.
• NOP commands are only issued during tMPX_LH window.
No other command is allowed during the tMPX_LH window after an SELF REFRESH EXIT (SRX) command is issued.
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4Gb: x4, x8, x16 DDR4 SDRAM
SELF REFRESH Operation
Figure 89: Self Refresh Exit with NOP Command
7D
7D
7D
7D
7E
7E
7E
7E
7F
7F
7F
7F
7F
7G
7G
7G
7G
7H
7H
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&.BW
W
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123
123
123
123
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9DOLG
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4Gb: x4, x8, x16 DDR4 SDRAM
Power-Down Mode
Power-Down Mode
Power-down is synchronously entered when CKE is registered LOW (along with a DESELECT command). CKE is not allowed to go LOW when the following operations are in
progress: MRS command, MPR operations, ZQCAL operations, DLL locking, or READ/
WRITE operations. CKE is allowed to go LOW while any other operations, such as ROW
ACTIVATION, PRECHARGE or auto precharge, or REFRESH, are in progress, but the
power-down IDD specification will not be applied until those operations are complete.
The timing diagrams that follow illustrate power-down entry and exit.
For the fastest power-down exit timing, the DLL should be in a locked state when power-down is entered. If the DLL is not locked during power-down entry, the DLL must be
reset after exiting power-down mode for proper READ operation and synchronous ODT
operation. DRAM design provides all AC and DC timing and voltage specification as
well as proper DLL operation with any CKE intensive operations as long as the controller complies with DRAM specifications.
During power-down, if all banks are closed after any in-progress commands are completed, the device will be in precharge power-down mode; if any bank is open after inprogress commands are completed, the device will be in active power-down mode.
Entering power-down deactivates the input and output buffers, excluding CK, CKE, and
RESET_n. In power-down mode, DRAM ODT input buffer deactivation is based on MRx
bit Y. If it is configured to 0b, the ODT input buffer remains on and the ODT input signal
must be at valid logic level. If it is configured to 1b, the ODT input buffer is deactivated
and the DRAM ODT input signal may be floating and the device does not provide
RTT(NOM) termination. Note that the device continues to provide RTT(Park) termination if
it is enabled in the mode register MRa bit B. To protect internal delay on the CKE line to
block the input signals, multiple DES commands are needed during the CKE switch off
and on cycle(s); this timing period is defined as tCPDED. CKE LOW will result in deactivation of command and address receivers after tCPDED has expired.
Table 52: Power-Down Entry Definitions
DRAM Status
DLL
PowerDown Exit
Active
(a bank or more open)
On
Fast
tXP
to any valid command.
Precharged
(all banks precharged)
On
Fast
tXP
to any valid command.
Relevant Parameters
The DLL is kept enabled during precharge power-down or active power-down. In power-down mode, CKE is LOW, RESET_n is HIGH, and a stable clock signal must be maintained at the inputs of the device. ODT should be in a valid state, but all other input signals are "Don't Care." (If RESET_n goes LOW during power-down, the device will be out
of power-down mode and in the reset state.) CKE LOW must be maintained until tCKE
has been satisfied. Power-down duration is limited by 9 × tREFI.
The power-down state is synchronously exited when CKE is registered HIGH (along
with DES command). CKE HIGH must be maintained until tCKE has been satisfied. The
ODT input signal must be at a valid level when the device exits from power-down mode,
independent of MRx bit Y if R TT(NOM) is enabled in the mode register. If RTT(NOM) is disabled, the ODT input signal may remain floating. A valid, executable command can be
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4Gb: x4, x8, x16 DDR4 SDRAM
Power-Down Mode
applied with power-down exit latency, tXP, after CKE goes HIGH. Power-down exit latency is defined in the AC Specifications table.
Figure 90: Active Power-Down Entry and Exit
T0
T1
T2
Valid
DES
DES
Ta0
Ta1
Tb0
Tb1
Tc0
CK_c
CK_t
Command
DES
DES
DES
Valid
Valid
Valid
tPD
tIS
tIH
CKE
tIH
tCKE
tIS
ODT (ODT buffer enabled - MR5 [5] = 0)2
tIS
ODT (ODT buffer disbled - MR5 [5] =
Address
1)3
Valid
Valid
tCPDED
tXP
Enter
power-down
mode
Exit
power-down
mode
Time Break
Notes:
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Don’t Care
1. Valid commands at T0 are ACT, DES, or PRE with one bank remaining open after completion of the PRECHARGE command.
2. ODT pin driven to a valid state; MR5[5] = 0 (normal setting).
3. ODT pin driven to a valid state; MR5[5] = 1.
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4Gb: x4, x8, x16 DDR4 SDRAM
Power-Down Mode
Figure 91: Power-Down Entry After Read and Read with Auto Precharge
CK_c
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Tb0
Tb1
RD or
RDA
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Valid
CK_t
Command
tIS
tCPDED
Valid
CKE
Valid
Valid
Address
RL = AL + CL
tPD
DQS_t, DQS_c
DQ BL8
DI
b
DI
b+1
DI
b+2
DI
b+3
DQ BC4
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
tRDPDEN
Power-Down
entry
Transitioning Data
Note:
Don’t Care
Time Break
1. DI n (or b) = data-in from column n (or b).
Figure 92: Power-Down Entry After Write and Write with Auto Precharge
CK_c
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Tb1
Tb2
Tc0
Tc1
DES
DES
Valid
CK_t
Command
DES
tIS
tCPDED
Valid
CKE
Address
Bank,
Col n
Valid
A10
WL = AL + CWL
tPD
WR
DQS_t, DQS_c
DQ BL8
DI
b
DI
b+1
DI
b+2
DI
b+3
DQ BC4
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
Start internal
precharge
tWRAPDEN
Power-Down
entry
Transitioning Data
Notes:
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'RQ¶W&DUH
1. DI n (or b) = data-in from column n (or b).
2. Valid commands at T0 are ACT, DES, or PRE with one bank remaining open after completion of the PRECHARGE command.
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4Gb: x4, x8, x16 DDR4 SDRAM
Power-Down Mode
Figure 93: Power-Down Entry After Write
CK_c
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Tb1
Tb2
Tc0
Tc1
DES
DES
Valid
CK_t
Command
DES
tIS
tCPDED
Valid
CKE
Address
Bank,
Col n
Valid
A10
WL = AL + CWL
tPD
tWR
DQS_t, DQS_c
DQ BL8
DI
b
DI
b+1
DI
b+2
DI
b+3
DQ BC4
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
tWRPDEN
Power-Down
entry
Transitioning Data
Note:
Time Break
Don’t Care
1. DI n (or b) = data-in from column n (or b).
Figure 94: Precharge Power-Down Entry and Exit
T0
T1
T2
Ta0
Ta1
Tb0
Tb1
Tc0
DES
DES
DES
DES
DES
DES
Valid
Valid
Valid
CK_c
CK_t
Command
tCPDED
tCKE
tIS
tIH
CKE
tIS
tPD
tXP
Exit
power-down
mode
Enter
power-down
mode
Time Break
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Don’t Care
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4Gb: x4, x8, x16 DDR4 SDRAM
Power-Down Mode
Figure 95: REFRESH Command to Power-Down Entry
T0
T1
T2
Ta0
Tb0
Tb1
REF
DES
DES
DES
DES
CK_c
CK_t
Command
Address
Valid
tCPDED
tIS
tPD
tCKE
CKE
Valid
tREFPDEN
Time Break
Don’t Care
Figure 96: Active Command to Power-Down Entry
T0
T1
T2
Ta0
Tb0
Tb1
ACT
DES
DES
DES
DES
CK_c
CK_t
Command
Address
Valid
tCPDED
tIS
tPD
tCKE
CKE
Valid
tACTPDEN
Time Break
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Don’t Care
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4Gb: x4, x8, x16 DDR4 SDRAM
Power-Down Mode
Figure 97: PRECHARGE/PRECHARGE ALL Command to Power-Down Entry
T0
T1
T2
Ta0
Tb0
Tb1
PRE or
PREA
DES
DES
DES
Valid
CK_c
CK_t
Command
Address
Valid
tCPDED
tIS
tPD
tCKE
CKE
tPREPDEN
Time Break
Don’t Care
Figure 98: MRS Command to Power-Down Entry
T0
T1
Ta0
Ta1
Command
MRS
DES
DES
DES
Address
Valid
Tb0
Tb1
CK_c
CK_t
DES
tCPDED
tIS
tPD
tCKE
CKE
Valid
tMRSPDEN
Time Break
Don’t Care
Power-Down Clarifications – Case 1
When CKE is registered LOW for power-down entry, tPD (MIN) must be satisfied before
CKE can be registered HIGH for power-down exit. The minimum value of parameter
tPD (MIN) is equal to the minimum value of parameter tCKE (MIN) as shown in the
Timing Parameters by Speed Bin table. A detailed example of Case 1 follows.
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4Gb: x4, x8, x16 DDR4 SDRAM
Power-Down Mode
Figure 99: Power-Down Entry/Exit Clarifications – Case 1
T0
T1
T2
Ta0
Valid
DES
DES
Ta1
Tb0
Tb1
Tb2
CK_c
CK_t
Command
DES
DES
DES
DES
tPD
tPD
tIH
tIS
tIS
CKE
tIS
tIH
Address
tCKE
Valid
tCPDED
tCPDED
Enter
power-down
mode
Exit
power-down
mode
Enter
power-down
mode
Time Break
Don’t Care
Power-Down Entry, Exit Timing with CAL
Command/Address latency is used and additional timing restrictions are required when
entering power-down, as noted in the following figures.
Figure 100: Active Power-Down Entry and Exit Timing with CAL
7
7
7D
7D
7D
'(6
'(6
9DOLG
'(6
'(6
7E
7E
7F
7F
7G
7G
7H
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W ,+
W 3'
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W ,6
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'RQ¶W&DUH
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4Gb: x4, x8, x16 DDR4 SDRAM
Power-Down Mode
Figure 101: REFRESH Command to Power-Down Entry with CAL
7
7
7D
7E
7E
7F
'(6
'(6
5()
'(6
'(6
'(6
7F
7G
7G
7H
7H
7I
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'(6
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W &$/
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W &3'('
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W ;3
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W ,+
W &$/
W ,6
W,+
7LPH%UHDN
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'RQ¶W&DUH
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4Gb: x4, x8, x16 DDR4 SDRAM
ODT Input Buffer Disable Mode for Power-Down
ODT Input Buffer Disable Mode for Power-Down
ODT input buffer disable mode, when enabled via MR5[5], will prevent the device from
providing RTT(NOM) termination during power-down for additional power savings.
The internal delay on the CKE path to disable the ODT buffer and block the sampled
output must be accounted for; therefore, ODT must be continuously driven to a valid
level, either LOW or HIGH, when entering power-down. However, after tCPDED (MIN)
has been satisfied, the ODT signal may float.
When ODT input buffer disable mode is enabled, RTT(NOM) termination corresponding
to sampled ODT after CKE is first registered LOW (and tANPD before that) may not be
provided. tANPD is equal to (WL - 1) and is counted backward from PDE, with CKE registered LOW.
Figure 102: ODT Power-Down Entry with ODT Buffer Disable Mode
diff_CK
CKE
tDODTLoff
tCPDED
+1
(MIN)
Floating
ODT
tADC
DRAM_RTT_sync
(DLL enabled)
CA parity disabled
(MIN)
RTT(NOM)
RTT(Park)
tCPDED
DODTLoff
tADC
DRAM_RTT_sync
(DLL enabled)
CA parity enabled
RTT(NOM)
DRAM_RTT_async
(DLL disabled)
RTT(NOM)
(MIN)
RTT(Park)
tCPDED
DODTLoff
(MIN) + tADC (MAX) + PL
RTT(Park)
tAONAS
(MIN)
tCPDED
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(MIN) + tADC (MAX)
162
(MIN) + tAOFAS (MAX)
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4Gb: x4, x8, x16 DDR4 SDRAM
ODT Input Buffer Disable Mode for Power-Down
Figure 103: ODT Power-Down Exit with ODT Buffer Disable Mode
diff_CK
CKE
ODT_A
(DLL enabled)
Floating
tADC
tXP
RTT(NOM)
RTT(Park)
DRAM_RTT_A
DODTLon
ODT_B
(DLL disabled)
(MAX)
tADC
(MIN)
Floating
tXP
DRAM_RTT_B
RTT(Park)
tAONAS
RTT(NOM)
(MIN)
tAOFAS
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(MAX)
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4Gb: x4, x8, x16 DDR4 SDRAM
CRC Write Data Feature
CRC Write Data Feature
CRC Write Data
The CRC write data feature takes the CRC generated data from the DRAM controller and
compares it to the internally CRC generated data and determines whether the two
match (no CRC error) or do not match (CRC error).
Figure 104: CRC Write Data Operation
DRAM
DRAM Controller
Data
Data
CRC
engine
CRC
engine
CRC
Code
Data
CRC Code
CRC Code
Compare
CRC
WRITE CRC DATA Operation
A DRAM controller generates a CRC checksum using a 72-bit CRC tree and forms the
write data frames, as shown in the following CRC data mapping tables for the x4, x8, and
x16 configurations. A x4 device has a CRC tree with 32 input data bits used, and the remaining upper 40 bits D[71:32] being 1s. A x8 device has a CRC tree with 64 input data
bits used, and the remaining upper 8 bits dependant upon whether DM_n/DBI_n is
used (1s are sent when not used). A x16 device has two identical CRC trees each, one for
the lower byte and one for the upper byte, with 64 input data bits used by each, and the
remaining upper 8 bits on each byte dependant upon whether DM_n/DBI_n is used (1s
are sent when not used). For a x8 and x16 DRAMs, the DRAM memory controller must
send 1s in transfer 9 location whether or not DM_n/DBI_n is used.
The DRAM checks for an error in a received code word D[71:0] by comparing the received checksum against the computed checksum and reports errors using the
ALERT_n signal if there is a mismatch. The DRAM can write data to the DRAM core
without waiting for the CRC check for full writes when DM is disabled. If bad data is
written to the DRAM core, the DRAM memory controller will try to overwrite the bad
data with good data; this means the DRAM controller is responsible for data coherency
when DM is disabled. However, in the case where both CRC and DM are enabled via
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4Gb: x4, x8, x16 DDR4 SDRAM
CRC Write Data Feature
MRS (that is, persistent mode), the DRAM will not write bad data to the core when a
CRC error is detected.
DBI_n and CRC Both Enabled
The DRAM computes the CRC for received written data D[71:0]. Data is not inverted
back based on DBI before it is used for computing CRC. The data is inverted back based
on DBI before it is written to the DRAM core.
DM_n and CRC Both Enabled
When both DM and write CRC are enabled in the DRAM mode register, the DRAM calculates CRC before sending the write data into the array. If there is a CRC error, the
DRAM blocks the WRITE operation and discards the data. The Nonconsecutive WRITE
(BL8/BC4-OTF) with 2tCK Preamble and Write CRC in Same or Different Bank Group and
the WRITE (BL8/BC4-OTF/Fixed) with 1tCK Preamble and Write CRC in Same or Different
BankGroup figures in the WRITE Operation section show timing differences when DM
is enabled.
DM_n and DBI_n Conflict During Writes with CRC Enabled
Both write DBI_n and DM_n can not be enabled at the same time; read DBI_n and
DM_n can be enabled at the same time.
CRC and Write Preamble Restrictions
When write CRC is enabled:
• And 1tCK WRITE preamble mode is enabled, a tCCD_S or tCCD_L of 4 clocks is not
allowed.
• And 2tCK WRITE preamble mode is enabled, a tCCD_S or tCCD_L of 6 clocks is not
allowed.
CRC Simultaneous Operation Restrictions
When write CRC is enabled, neither MPR writes nor per-DRAM mode is allowed.
CRC Polynomial
The CRC polynomial used by DDR4 is the ATM-8 HEC, X8 + X2 + X1 + 1.
A combinatorial logic block implementation of this 8-bit CRC for 72 bits of data includes 272 two-input XOR gates contained in eight 6-XOR-gate-deep trees.
The CRC polynomial and combinatorial logic used by DDR4 is the same as used on
GDDR5.
The error coverage from the DDR4 polynomial used is shown in the following table.
Table 53: CRC Error Detection Coverage
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Error Type
Detection Capability
Random single-bit errors
100%
Random double-bit errors
100%
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4Gb: x4, x8, x16 DDR4 SDRAM
CRC Write Data Feature
Table 53: CRC Error Detection Coverage (Continued)
Error Type
Detection Capability
Random odd count errors
100%
Random multibit UI vertical column error
detection excluding DBI bits
100%
CRC Combinatorial Logic Equations
module CRC8_D72;
// polynomial: (0 1 2 8)
// data width: 72
// convention: the first serial data bit is D[71]
//initial condition all 0 implied
// "^" = XOR
function [7:0]
nextCRC8_D72;
input [71:0] Data;
input [71:0] D;
reg [7:0] CRC;
begin
D = Data;
CRC[0] =
D[69]^D[68]^D[67]^D[66]^D[64]^D[63]^D[60]^D[56]^D[54]^D[53]^D[52]^D[50]^D[49
]^D[48]^D[45]^D[43]^D[40]^D[39]^D[35]^D[34]^D[31]^D[30]^D[28]^D[23]^D[21]^D[1
9]^D[18]^D[16]^D[14]^D[12]^D[8]^D[7]^D[6]^D[0] ;
CRC[1] =
D[70]^D[66]^D[65]^D[63]^D[61]^D[60]^D[57]^D[56]^D[55]^D[52]^D[51]^D[48]^D[46
]^D[45]^D[44]^D[43]^D[41]^D[39]^D[36]^D[34]^D[32]^D[30]^D[29]^D[28]^D[24]^D[2
3]^D[22]^D[21]^D[20]^D[18]^D[17]^D[16]^D[15]^D[14]^D[13]^D[12]^D[9]^D[6]^D[1
]^D[0];
CRC[2] =
D[71]^D[69]^D[68]^D[63]^D[62]^D[61]^D[60]^D[58]^D[57]^D[54]^D[50]^D[48]^D[47
]^D[46]^D[44]^D[43]^D[42]^D[39]^D[37]^D[34]^D[33]^D[29]^D[28]^D[25]^D[24]^D[2
2]^D[17]^D[15]^D[13]^D[12]^D[10]^D[8]^D[6]^D[2]^D[1]^D[0];
CRC[3] =
D[70]^D[69]^D[64]^D[63]^D[62]^D[61]^D[59]^D[58]^D[55]^D[51]^D[49]^D[48]^D[47
]^D[45]^D[44]^D[43]^D[40]^D[38]^D[35]^D[34]^D[30]^D[29]^D[26]^D[25]^D[23]^D[1
8]^D[16]^D[14]^D[13]^D[11]^D[9]^D[7]^D[3]^D[2]^D[1];
CRC[4] =
D[71]^D[70]^D[65]^D[64]^D[63]^D[62]^D[60]^D[59]^D[56]^D[52]^D[50]^D[49]^D[48
]^D[46]^D[45]^D[44]^D[41]^D[39]^D[36]^D[35]^D[31]^D[30]^D[27]^D[26]^D[24]^D[1
9]^D[17]^D[15]^D[14]^D[12]^D[10]^D[8]^D[4]^D[3]^D[2];
CRC[5] =
D[71]^D[66]^D[65]^D[64]^D[63]^D[61]^D[60]^D[57]^D[53]^D[51]^D[50]^D[49]^D[47
]^D[46]^D[45]^D[42]^D[40]^D[37]^D[36]^D[32]^D[31]^D[28]^D[27]^D[25]^D[20]^D[1
8]^D[16]^D[15]^D[13]^D[11]^D[9]^D[5]^D[4]^D[3];
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4Gb: x4, x8, x16 DDR4 SDRAM
CRC Write Data Feature
CRC[6] =
D[67]^D[66]^D[65]^D[64]^D[62]^D[61]^D[58]^D[54]^D[52]^D[51]^D[50]^D[48]^D[47
]^D[46]^D[43]^D[41]^D[38]^D[37]^D[33]^D[32]^D[29]^D[28]^D[26]^D[21]^D[19]^D[1
7]^D[16]^D[14]^D[12]^D[10]^D[6]^D[5]^D[4];
CRC[7] =
D[68]^D[67]^D[66]^D[65]^D[63]^D[62]^D[59]^D[55]^D[53]^D[52]^D[51]^D[49]^D[48
]^D[47]^D[44]^D[42]^D[39]^D[38]^D[34]^D[33]^D[30]^D[29]^D[27]^D[22]^D[20]^D[1
8]^D[17]^D[15]^D[13]^D[11]^D[7]^D[6]^D[5];
nextCRC8_D72 = CRC;
Burst Ordering for BL8
DDR4 supports fixed WRITE burst ordering [A2:A1:A0 = 0:0:0] when write CRC is enabled in BL8 (fixed).
CRC Data Bit Mapping
Table 54: CRC Data Mapping for x4 Devices, BL8
Transfer
Function
0
1
2
3
4
5
6
7
8
9
DQ0
D0
D1
D2
D3
D4
D5
D6
D7
CRC0
CRC4
DQ1
D8
D9
D10
D11
D12
D13
D14
D15
CRC1
CRC5
DQ2
D16
D17
D18
D19
D20
D21
D22
D23
CRC2
CRC6
DQ3
D24
D25
D26
D27
D28
D29
D30
D31
CRC3
CRC7
6
7
8
9
Table 55: CRC Data Mapping for x8 Devices, BL8
Transfer
Function
0
1
DQ0
D0
D1
D2
D3
D4
D5
D6
D7
CRC0
1
DQ1
D8
D9
D10
D11
D12
D13
D14
D15
CRC1
1
DQ2
D16
D17
D18
D19
D20
D21
D22
D23
CRC2
1
DQ3
D24
D25
D26
D27
D28
D29
D30
D31
CRC3
1
DQ4
D32
D33
D34
D35
D36
D37
D38
D39
CRC4
1
DQ5
D40
D41
D42
D43
D44
D45
D46
D47
CRC5
1
DQ6
D48
D49
D50
D51
D52
D53
D54
D55
CRC6
1
DQ7
D56
D57
D58
D59
D60
D61
D62
D63
CRC7
1
DM_n/
DBI_n
D64
D65
D66
D67
D68
D69
D70
D71
1
1
2
3
4
5
A x16 device is treated as two x8 devices; a x16 device will have two identical CRC trees
implemented. CRC[7:0] covers data bits D[71:0], and CRC[15:8] covers data bits
D[143:72].
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4Gb: x4, x8, x16 DDR4 SDRAM
CRC Write Data Feature
Table 56: CRC Data Mapping for x16 Devices, BL8
Transfer
Function
0
1
2
3
4
5
6
7
8
9
DQ0
D0
D1
D2
D3
D4
D5
D6
D7
CRC0
1
DQ1
D8
D9
D10
D11
D12
D13
D14
D15
CRC1
1
DQ2
D16
D17
D18
D19
D20
D21
D22
D23
CRC2
1
DQ3
D24
D25
D26
D27
D28
D29
D30
D31
CRC3
1
DQ4
D32
D33
D34
D35
D36
D37
D38
D39
CRC4
1
DQ5
D40
D41
D42
D43
D44
D45
D46
D47
CRC5
1
DQ6
D48
D49
D50
D51
D52
D53
D54
D55
CRC6
1
DQ7
D56
D57
D58
D59
D60
D61
D62
D63
CRC7
1
LDM_n/
LDBI_n
D64
D65
D66
D67
D68
D69
D70
D71
1
1
DQ8
D72
D73
D74
D75
D76
D77
D78
D79
CRC8
1
DQ9
D80
D81
D82
D83
D84
D85
D86
D87
CRC9
1
DQ10
D88
D89
D90
D91
D92
D93
D94
D95
CRC10
1
DQ11
D96
D97
D98
D99
D100
D101
D102
D103
CRC11
1
DQ12
D104
D105
D106
D107
D108
D109
D110
D111
CRC12
1
DQ13
D112
D113
D114
D115
D116
D117
D118
D119
CRC13
1
DQ14
D120
D121
D122
D123
D124
D125
D126
D127
CRC14
1
DQ15
D128
D129
D130
D131
D132
D133
D134
D135
CRC15
1
UDM_n/
UDBI_n
D136
D137
D138
D139
D140
D141
D142
D143
1
1
CRC Enabled With BC4
If CRC and BC4 are both enabled, then address bit A2 is used to transfer critical data
first for BC4 writes.
CRC with BC4 Data Bit Mapping
For a x4 device, the CRC tree inputs are 16 data bits, and the inputs for the remaining
bits are 1.
When A2 = 1, data bits D[7:4] are used as inputs for D[3:0], D[15:12] are used as inputs to
D[11:8], and so forth, for the CRC tree.
Table 57: CRC Data Mapping for x4 Devices, BC4
Transfer
Function
0
1
2
3
DQ0
D0
D1
D2
D3
DQ1
D8
D9
D10
DQ2
D16
D17
D18
4
5
6
7
8
9
1
1
1
1
CRC0
CRC4
D11
1
1
1
1
CRC1
CRC5
D19
1
1
1
1
CRC2
CRC6
A2 = 0
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4Gb: x4, x8, x16 DDR4 SDRAM
CRC Write Data Feature
Table 57: CRC Data Mapping for x4 Devices, BC4 (Continued)
Transfer
Function
0
1
2
3
4
5
6
7
8
9
DQ3
D24
D25
D26
D27
1
1
1
1
CRC3
CRC7
A2 = 1
DQ0
D4
D5
D6
D7
1
1
1
1
CRC0
CRC4
DQ1
D12
D13
D14
D15
1
1
1
1
CRC1
CRC5
DQ2
D20
D21
D22
D23
1
1
1
1
CRC2
CRC6
DQ3
D28
D29
D30
D31
1
1
1
1
CRC3
CRC7
For a x8 device, the CRC tree inputs are 36 data bits.
When A2 = 0, the input bits D[67:64]) are used if DBI_n or DM_n functions are enabled;
if DBI_n and DM_n are disabled, then D[67:64]) are 1.
When A2 = 1, data bits D[7:4] are used as inputs for D[3:0], D[15:12] are used as inputs to
D[11:8], and so forth, for the CRC tree. The input bits D[71:68]) are used if DBI_n or
DM_n functions are enabled; if DBI_n and DM_n are disabled, then D[71:68]) are 1.
Table 58: CRC Data Mapping for x8 Devices, BC4
Transfer
Function
0
1
2
3
DQ0
D0
D1
D2
D3
DQ1
D8
D9
D10
DQ2
D16
D17
DQ3
D24
DQ4
D32
DQ5
4
5
6
7
8
9
1
1
1
1
CRC0
1
D11
1
1
1
1
CRC1
1
D18
D19
1
1
1
1
CRC2
1
D25
D26
D27
1
1
1
1
CRC3
1
D33
D34
D35
1
1
1
1
CRC4
1
D40
D41
D42
D43
1
1
1
1
CRC5
1
DQ6
D48
D49
D50
D51
1
1
1
1
CRC6
1
DQ7
D56
D57
D58
D59
1
1
1
1
CRC7
1
DM_n/DBI_n
D64
D65
D66
D67
1
1
1
1
1
1
A2 = 0
A2 = 1
DQ0
D4
D5
D6
D7
1
1
1
1
CRC0
1
DQ1
D12
D13
D14
D15
1
1
1
1
CRC1
1
DQ2
D20
D21
D22
D23
1
1
1
1
CRC2
1
DQ3
D28
D29
D30
D31
1
1
1
1
CRC3
1
DQ4
D36
D37
D38
D39
1
1
1
1
CRC4
1
DQ5
D44
D45
D46
D47
1
1
1
1
CRC5
1
DQ6
D52
D53
D54
D55
1
1
1
1
CRC6
1
DQ7
D60
D61
D62
D63
1
1
1
1
CRC7
1
DM_n/DBI_n
D68
D69
D70
D71
1
1
1
1
1
1
There are two identical CRC trees for x16 devices, each have CRC tree inputs of 36 bits.
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4Gb: x4, x8, x16 DDR4 SDRAM
CRC Write Data Feature
When A2 = 0, input bits D[67:64] are used if DBI_n or DM_n functions are enabled; if
DBI_n and DM_n are disabled, then D[67:64] are 1s. The input bits D[139:136] are used
if DBI_n or DM_n functions are enabled; if DBI_n and DM_n are disabled, then
D[139:136] are 1s.
When A2 = 1, data bits D[7:4] are used as inputs for D[3:0], D[15:12] are used as inputs
for D[11:8], and so forth, for the CRC tree. Input bits D[71:68] are used if DBI_n or DM_n
functions are enabled; if DBI_n and DM_n are disabled, then D[71:68] are 1s. The input
bits D[143:140] are used if DBI_n or DM_n functions are enabled; if DBI_n and DM_n
are disabled, then D[143:140] are 1s.
Table 59: CRC Data Mapping for x16 Devices, BC4
Transfer
Function
0
1
2
3
4
5
6
7
8
9
A2 = 0
DQ0
D0
D1
D2
D3
1
1
1
1
CRC0
1
DQ1
D8
D9
D10
D11
1
1
1
1
CRC1
1
DQ2
D16
D17
D18
D19
1
1
1
1
CRC2
1
DQ3
D24
D25
D26
D27
1
1
1
1
CRC3
1
DQ4
D32
D33
D34
D35
1
1
1
1
CRC4
1
DQ5
D40
D41
D42
D43
1
1
1
1
CRC5
1
DQ6
D48
D49
D50
D51
1
1
1
1
CRC6
1
DQ7
D56
D57
D58
D59
1
1
1
1
CRC7
1
LDM_n/LDBI_n
D64
D65
D66
D67
1
1
1
1
1
1
DQ8
D72
D73
D74
D75
1
1
1
1
CRC8
1
DQ9
D80
D81
D82
D83
1
1
1
1
CRC9
1
DQ10
D88
D89
D90
D91
1
1
1
1
CRC10
1
DQ11
D96
D97
D98
D99
1
1
1
1
CRC11
1
DQ12
D104
D105
D106
D107
1
1
1
1
CRC12
1
DQ13
D112
D113
D114
D115
1
1
1
1
CRC13
1
DQ14
D120
D121
D122
D123
1
1
1
1
CRC14
1
DQ15
D128
D129
D130
D131
1
1
1
1
CRC15
1
UDM_n/UDBI_n
D136
D137
D138
D139
1
1
1
1
1
1
A2 = 1
DQ0
D4
D5
D6
D7
1
1
1
1
CRC0
1
DQ1
D12
D13
D14
D15
1
1
1
1
CRC1
1
DQ2
D20
D21
D22
D23
1
1
1
1
CRC2
1
DQ3
D28
D29
D30
D31
1
1
1
1
CRC3
1
DQ4
D36
D37
D38
D39
1
1
1
1
CRC4
1
DQ5
D44
D45
D46
D47
1
1
1
1
CRC5
1
DQ6
D52
D53
D54
D55
1
1
1
1
CRC6
1
DQ7
D60
D61
D62
D63
1
1
1
1
CRC7
1
LDM_n/LDBI_n
D68
D69
D70
D71
1
1
1
1
1
1
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4Gb: x4, x8, x16 DDR4 SDRAM
CRC Write Data Feature
Table 59: CRC Data Mapping for x16 Devices, BC4 (Continued)
Transfer
Function
0
1
2
3
4
5
6
7
8
9
DQ8
D76
D77
D78
D79
1
1
1
1
CRC8
1
DQ9
D84
D85
D86
D87
1
1
1
1
CRC9
1
DQ10
D92
D93
D94
D95
1
1
1
1
CRC10
1
DQ11
D100
D101
D102
D103
1
1
1
1
CRC11
1
DQ12
D108
D109
D110
D111
1
1
1
1
CRC12
1
DQ13
D116
D117
D118
D119
1
1
1
1
CRC13
1
DQ14
D124
D125
D126
D127
1
1
1
1
CRC14
1
DQ15
D132
D133
D134
D135
1
1
1
1
CRC15
1
UDM_n/UDBI_n
D140
D141
D142
D143
1
1
1
1
1
1
CRC Equations for x8 Device in BC4 Mode with A2 = 0 and A2 = 1
The following example is of a CRC tree when x8 is used in BC4 mode (x4 and x16 CRC
trees have similar differences).
CRC[0], A2=0 =
1^1^D[67]^D[66]^D[64]^1^1^D[56]^1^1^1^D[50]^D[49]^D[48]^1^D[43]^D[40]^1^D[3
5]^D[34]^1^1^1^1^1^D[19]^D[18]^D[16]^1^1^D[8] ^1^1^ D[0] ;
CRC[0], A2=1 =
1^1^D[71]^D[70]^D[68]^1^1^D[60]^1^1^1^D[54]^D[53]^D[52]^1^D[47]^D[44]^1^D[3
9]^D[38]^1^1^1^1^1^D[23]^D[22]^D[20]^1^1^D[12]^1^1^D[4] ;
CRC[1], A2=0 =
1^D[66]^D[65]^1^1^1^D[57]^D[56]^1^1^D[51]^D[48]^1^1^1^D[43]^D[41]^1^1^D[34
]^D[32]^1^1^1^D[24]^1^1^1^1^D[18]^D[17]^D[16]^1^1^1^1^D[9] ^1^ D[1]^D[0];
CRC[1], A2=1 =
1^D[70]^D[69]^1^1^1^D[61]^D[60]^1^1^D[55]^D[52]^1^1^1^D[47]^D[45]^1^1^D[38
]^D[36]^1^1^1^D[28]^1^1^1^1^D[22]^D[21]^D[20]^1^1^1^1^D[13]^1^D[5]^D[4];
CRC[2], A2=0 =
1^1^1^1^1^1^1^D[58]^D[57]^1^D[50]^D[48]^1^1^1^D[43]^D[42]^1^1^D[34]^D[33]^1
^1^D[25]^D[24]^1^D[17]^1^1^1^D[10]^D[8] ^1^D[2]^D[1]^D[0];
CRC[2], A2=1 =
1^1^1^1^1^1^1^D[62]^D[61]^1^D[54]^D[52]^1^1^1^D[47]^D[46]^1^1^D[38]^D[37]^1
^1^D[29]^D[28]^1^D[21]^1^1^1^D[14]^D12]^1^D[6]^D[5]^D[4];
CRC[3], A2=0 =
1^1^D[64]^1^1^1^D[59]^D[58]^1^D[51]^D[49]^D[48]^1^1^1^D[43]^D[40]^1^D[35]^
D[34]^1^1^D[26]^D[25]^1^D[18]^D[16]^1^1^D[11]^D[9] ^1^D[3]^D[2]^D[1];
CRC[3], A2=1 =
1^1^D[68]^1^1^1^D[63]^D[62]^1^D[55]^D[53]^D[52]^1^1^1^D[47]^D[44]^1^D[39]^
D[38]^1^1^D[30]^D[29]^1^D[22]^D[20]^1^1^D[15]^D[13]^1^D[7]^D[6]^D[5];
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4Gb: x4, x8, x16 DDR4 SDRAM
CRC Write Data Feature
CRC[4], A2=0 =
1^1^D[65]^D[64]^1^1^1^D[59]^D[56]^1^D[50]^D[49]^D[48]^1^1^1^D[41]^1^1^D[35
]^1^1^D[27]^D[26]^D[24]^D[19]^D[17]^1^1^1^D[10]^D[8] ^1^D[3]^D[2];
CRC[4], A2=1 =
1^1^D[69]^D[68]^1^1^1^D[63]^D[60]^1^D[54]^D[53]^D[52]^1^1^1^D[45]^1^1^D[39
]^1^1^D[31]^D[30]^D[28]^D[23]^D[21]^1^1^1^D[14]^D[12]^1^D[7]^D[6];
CRC[5], A2=0 =
1^D[66]^D[65]^D[64]^1^1^1^D[57]^1^D[51]^D[50]^D[49]^1^1^1^D[42]^D[40]^1^1^
D[32]^1^1^D[27]^D[25]^1^D[18]^D[16]^1^1^D[11]^D[9] ^1^1^D[3];
CRC[5], A2=1 =
1^D[70]^D[69]^D[68]^1^1^1^D[61]^1^D[55]^D[54]^D[53]^1^1^1^D[46]^D[44]^1^1^
D[36]^1^1^D[31]^D[29]^1^D[22]^D[20]^1^1^D[15]^D[13]^1^1^D[7];
CRC[6], A2=0 =
D[67]^D[66]^D[65]^D[64]^1^1^D[58]^1^1^D[51]^D[50]^D[48]^1^1^D[43]^D[41]^1^1
^D[33]^D[32]^1^1^D[26]^1^D[19]^D[17]^D[16]^1^1^D[10]^1^1^1;
CRC[6], A2=1 =
D[71]^D[70]^D[69]^D[68]^1^1^D[62]^1^1^D[55]^D[54]^D[52]^1^1^D[47]^D[45]^1^1
^D[37]^D[36]^1^1^D[30]^1^D[23]^D[21]^D[20]^1^1^D[14]^1^1^1;
CRC[7], A2=0 =
1^D[67]^D[66]^D[65]^1^1^D[59]^1^1^1^D[51]^D[49]^D[48]^1^1^D[42]^1^1^D[34]^
D[33]^1^1^D[27]^1^1^D[18]^D[17]^1^1^D[11]^1^1^1;
CRC[7], A2=1 =
1^D[71]^D[70]^D[69]^1^1^D[63]^1^1^1^D[55]^D[53]^D[52]^1^1^D[46]^1^1^D[38]^
D[37]^1^1^D[31]^1^1^D[22]^D[21]^1^1^D[15]^1^1^1;
CRC Error Handling
The CRC error mechanism shares the same ALERT_n signal as CA parity for reporting
write errors to the DRAM. The controller has two ways to distinguish between CRC errors and CA parity errors: 1) Read DRAM mode/MPR registers, and 2) Measure time
ALERT_n is LOW. To speed up recovery for CRC errors, CRC errors are only sent back as
a "short" pulse; the maximum pulse width is roughly ten clocks (unlike CA parity where
ALERT_n is LOW longer than 45 clocks). The ALERT_n LOW could be longer than the
maximum limit at the controller if there are multiple CRC errors as the ALERT_n signals
are connected by a daisy chain bus. The latency to ALERT_n signal is defined as
tCRC_ALERT in the following figure.
The DRAM will set the error status bit located at MR5[3] to a 1 upon detecting a CRC
error, which will subsequently set the CRC error status flag in the MPR error log HIGH
(MPR Page1, MPR3[7]). The CRC error status bit (and CRC error status flag) remains set
at 1 until the DRAM controller clears the CRC error status bit using an MRS command
to set MR5[3] to a 0. The DRAM controller, upon seeing an error as a pulse width, will
retry the write transactions. The controller should consider the worst-case delay for
ALERT_n (during initialization) and backup the transactions accordingly. The DRAM
controller may also be made more intelligent and correlate the write CRC error to a specific rank or a transaction.
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4Gb: x4, x8, x16 DDR4 SDRAM
CRC Write Data Feature
Figure 105: CRC Error Reporting
CK_c
CK_t
DQIN
T0
T1
Dx
T2
Dx+1
T3
Dx+2 Dx+3
Dx+4
T4
Dx+5
Dx+6
T5
Dx+7
CRCy
T6
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
1
CRC ALERT_PW (MAX)
tCRC_ALERT
ALERT_n
CRC ALERT_PW (MIN)
Transition Data
Notes:
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1. D[71:1] CRC computed by DRAM did not match CRC[7:0] at T5 and started error generating process at T6.
2. CRC ALERT_PW is specified from the point where the DRAM starts to drive the signal
LOW to the point where the DRAM driver releases and the controller starts to pull the
signal up.
3. Timing diagram applies to x4, x8, and x16 devices.
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CRC Write Data Flow Diagram
Figure 106: CA Parity Flow Diagram
DRAM write
process start
MR2 12 enable CRC
MR5 3 set CRC error clear to 0
MR5 10 enable/disable DM
MR3[10:9] WCL if DM enabled
Capture data
CRC
enabled
Persistent
mode
enabled
Yes
DRAM
CRC same as
controller
CRC
Yes
Yes
No
No
Transfer data
internally
Transfer data
internally
Transfer Data
Internally
DRAM
CRC same as
controller
CRC
Yes
CA error
174
Yes
No
No
MR5[3] = 0
at WRITE
ALERT_n LOW
6 to 10 CKs
ALERT_n HIGH
WRITE burst
completed
WRITE burst
completed
No
MR5[A3] and
PAGE1 MPR3[7]
remain set to 1
Yes
MR5[3] = 0
at WRITE
Set error flag
MR5[A3] 1
ALERT_n LOW
6 to 10 CKs
Set error status
PAGE1 MPR3[7] 1
WRITE burst
completed
Bad data written
MR5 3 reset to 0 if desired
ALERT_n HIGH
WRITE burst
completed
No
MR5[A3] and
PAGE1 MPR3[7]
remain set to 1
Yes
Set error flag
MR5[A3] 1
Set error status
PAGE1 MPR3[7] 1
WRITE burst
rejected
Bad data not written
MR5 3 reset to 0 if desired
4Gb: x4, x8, x16 DDR4 SDRAM
CRC Write Data Feature
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WRITE burst
completed
No
4Gb: x4, x8, x16 DDR4 SDRAM
Data Bus Inversion
Data Bus Inversion
The DATA BUS INVERSION (DBI) function is supported only for x8 and x16 configurations (it is not supported on x4 devices). DBI opportunistically inverts data bits, and in
conjunction with the DBI_n I/O, less than half of the DQs will switch LOW for a given
DQS strobe edge. The DBI function shares a common pin with the DATA MASK (DM)
and TDQS functions. The DBI function applies to either or both READ and WRITE operations: Write DBI cannot be enabled at the same time the DM function is enabled, and
DBI is not allowed during MPR READ operation. Valid configurations for TDQS, DM,
and DBI functions are shown below.
Table 60: DBI vs. DM vs. TDQS Function Matrix
Read DBI
Write DBI
Data Mask (DM)
TDQS (x8 only)
Enabled (or Disabled)
MR5[12]=1 (or
MR5[12] = 0)
Disabled
MR5[11] = 0
Disabled
MR5[10] = 0
Disabled
MR1[11] = 0
Enabled
MR5[11] = 1
Disabled
MR5[10] = 0
Disabled
MR1[11] = 0
Disabled
MR5[11] = 0
Enabled
MR5[10] = 1
Disabled
MR1[11] = 0
Disabled
MR5[11] = 0
Disabled
MR5[10] = 0
Enabled
MR1[11] = 1
Disabled
MR5[12] = 0
DBI During a WRITE Operation
If DBI_n is sampled LOW on a given byte lane during a WRITE operation, the DRAM inverts write data received on the DQ inputs prior to writing the internal memory array. If
DBI_n is sampled HIGH on a given byte lane, the DRAM leaves the data received on the
DQ inputs noninverted. The write DQ frame format is shown below for x8 and x16 configurations (the x4 configuration does not support the DBI function).
Table 61: DBI Write, DQ Frame Format (x8)
Transfer
Function
0
1
2
3
4
5
6
7
DQ[7:0]
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
DM_n or
DBI_n
DM0 or
DBI0
DM1 or
DBI1
DM2 or
DBI2
DM3 or
DBI3
DM4 or
DBI4
DM5 or
DBI5
DM6 or
DBI6
DM7 or
DBI7
Table 62: DBI Write, DQ Frame Format (x16)
Transfer, Lower (L) and Upper(U)
Function
0
1
2
3
4
5
6
7
DQ[7:0]
LByte 0
LByte 1
LByte 2
LByte 3
LByte 4
LByte 5
LByte 6
LByte 7
LDM_n or
LDBI_n
LDM0 or
LDBI0
LDM1 or
LDBI1
LDM2 or
LDBI2
LDM3 or
LDBI3
LDM4 or
LDBI4
LDM5 or
LDBI5
LDM6 or
LDBI6
LDM7 or
LDBI7
DQ[15:8]
UByte 0
UByte 1
UByte 2
UByte 3
UByte 4
UByte 5
UByte 6
UByte 7
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4Gb: x4, x8, x16 DDR4 SDRAM
Data Bus Inversion
Table 62: DBI Write, DQ Frame Format (x16) (Continued)
Transfer, Lower (L) and Upper(U)
Function
0
1
2
3
4
5
6
7
UDM_n or
UDBI_n
UDM0 or
UDBI0
UDM1 or
UDBI1
UDM2 or
UDBI2
UDM3 or
UDBI3
UDM4 or
UDBI4
UDM5 or
UDBI5
UDM6 or
UDBI6
UDM7 or
UDBI7
DBI During a READ Operation
If the number of 0 data bits within a given byte lane is greater than four during a READ
operation, the DRAM inverts read data on its DQ outputs and drives the DBI_n pin
LOW; otherwise, the DRAM does not invert the read data and drives the DBI_n pin
HIGH. The read DQ frame format is shown below for x8 and x16 configurations (the x4
configuration does not support the DBI function).
Table 63: DBI Read, DQ Frame Format (x8)
Transfer Byte
Function
0
1
2
3
4
5
6
7
DQ[7:0]
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
DBI_n
DBI0
DBI1
DBI2
DBI3
DBI4
DBI5
DBI6
DBI7
Table 64: DBI Read, DQ Frame Format (x16)
Transfer Byte, Lower (L) and Upper(U)
Function
0
1
2
3
4
5
6
7
DQ[7:0]
LByte 0
LByte 1
LByte 2
LByte 3
LByte 4
LByte 5
LByte 6
LByte 7
LDBI_n
LDBI0
LDBI1
LDBI2
LDBI3
LDBI4
LDBI5
LDBI6
LDBI7
DQ[15:8]
UByte 0
UByte 1
UByte 2
UByte 3
UByte 4
UByte 5
UByte 6
UByte 7
UDBI_n
UDBI0
UDBI1
UDBI2
UDBI3
UDBI4
UDBI5
UDBI6
UDBI7
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4Gb: x4, x8, x16 DDR4 SDRAM
Data Mask
Data Mask
The DATA MASK (DM) function, also described as PARTIAL WRITE, is supported only
for x8 and x16 configurations (it is not supported on x4 devices). The DM function
shares a common pin with the DBI_n and TDQS functions. The DM function applies
only to WRITE operations and cannot be enabled at the same time the WRITE DBI
function is enabled. The valid configurations for the TDQS, DM, and DBI functions are
shown here.
Table 65: DM vs. TDQS vs. DBI Function Matrix
Data Mask (DM)
TDQS (x8 only)
Write DBI
Read DBI
Enabled
MR5[10] = 1
Disabled
MR1[11] = 0
Disabled
MR5[11] = 0
Enabled or Disabled
MR5[12] = 1 or
MR5[12] = 0
Disabled
MR5[10] = 0
Enabled
MR1[11] = 1
Disabled
MR5[11] = 0
Disabled
MR5[12] = 0
Disabled
MR1[11] = 0
Enabled
MR5[11] = 1
Enabled or Disabled
MR5[12] = 1 or
MR5[12] = 0
Disabled
MR1[11] = 0
Disabled
MR5[11] = 0
Enabled (or Disabled)
MR5[12] = 1 (or
MR5[12] = 0)
When enabled, the DM function applies during a WRITE operation. If DM_n is sampled
LOW on a given byte lane, the DRAM masks the write data received on the DQ inputs. If
DM_n is sampled HIGH on a given byte lane, the DRAM does not mask the data and
writes this data into the DRAM core. The DQ frame format for x8 and x16 configurations
is shown below. If both CRC write and DM are enabled (via MRS), the CRC will be
checked and valid prior to the DRAM writing data into the DRAM core. If a CRC error
occurs while the DM feature is enabled, CRC write persistent mode will be enabled and
data will not be written into the DRAM core. In the case of CRC write enabled and DM
disabled (via MRS), that is, CRC write nonpersistent mode, data is written to the DRAM
core even if a CRC error occurs.
Table 66: Data Mask, DQ Frame Format (x8)
Transfer
Function
0
1
2
3
4
5
6
7
DQ[7:0]
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
DM_n or
DBI_n
DM0 or
DBI0
DM1 or
DBI1
DM2 or
DBI2
DM3 or
DBI3
DM4 or
DBI4
DM5 or
DBI5
DM6 or
DBI6
DM7 or
DBI7
Table 67: Data Mask, DQ Frame Format (x16)
Transfer, Lower (L) and Upper (U)
Function
0
1
2
3
4
5
6
7
DQ[7:0]
LByte 0
LByte 1
LByte 2
LByte 3
LByte 4
LByte 5
LByte 6
LByte 7
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4Gb: x4, x8, x16 DDR4 SDRAM
Data Mask
Table 67: Data Mask, DQ Frame Format (x16) (Continued)
Transfer, Lower (L) and Upper (U)
Function
0
1
2
3
4
5
6
7
LDM_n or
LDBI_n
LDM0 or
LDBI0
LDM1 or
LDBI1
LDM2 or
LDBI2
LDM3 or
LDBI3
LDM4 or
LDBI4
LDM5 or
LDBI5
LDM6 or
LDBI6
LDM7 or
LDBI7
DQ[15:8]
UByte 0
UByte 1
UByte 2
UByte 3
UByte 4
UByte 5
UByte 6
UByte 7
UDM_n or
UDBI_n
UDM0 or
UDBI0
UDM1 or
UDBI1
UDM2 or
UDBI2
UDM3 or
UDBI3
UDM4 or
UDBI4
UDM5 or
UDBI5
UDM6 or
UDBI6
UDM7 or
UDBI7
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4Gb: x4, x8, x16 DDR4 SDRAM
Programmable Preamble Modes and DQS Postambles
Programmable Preamble Modes and DQS Postambles
The device supports programmable WRITE and READ preamble modes, either the normal 1tCK preamble mode or special 2tCK preamble mode. The 2 tCK preamble mode
places special timing constraints on many operational features as well as being supported for data rates of DDR4-2400 and faster. The WRITE preamble 1 tCK or 2tCK mode
can be selected independently from READ preamble 1tCK or 2tCK mode.
READ preamble training is also supported; this mode can be used by the DRAM controller to train or "read level" the DQS receivers.
There are tCCD restrictions under some circumstances:
• When 2tCK READ preamble mode is enabled, a tCCD_S or tCCD_L of 5 clocks is not
allowed.
• When 2tCK WRITE preamble mode is enabled and write CRC is not enabled, a tCCD_S
or tCCD_L of 5 clocks is not allowed.
• When 2tCK WRITE preamble mode is enabled and write CRC is enabled, a tCCD_S or
tCCD_L of 6 clocks is not allowed.
WRITE Preamble Mode
MR4[12] = 0 selects 1tCK WRITE preamble mode while MR4[12] = 1 selects 2 tCK WRITE
preamble mode. Examples are shown in the figures below.
Figure 107: 1tCK vs. 2tCK WRITE Preamble Mode
1tCK Mode
WR
WL
CK_c
CK_t
Preamble
DQS_t,
DQS_c
DQ
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
2tCK Mode
WR
WL
CK_c
CK_t
Preamble
DQS_t,
DQS_c
DQ
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4Gb: x4, x8, x16 DDR4 SDRAM
Programmable Preamble Modes and DQS Postambles
CWL has special considerations when in the 2tCK WRITE preamble mode. The CWL value selected in MR2[5:3], as seen in table below, requires at least one additional clock
when the primary CWL value and 2tCK WRITE preamble mode are used; no additional
clocks are required when the alternate CWL value and 2tCK WRITE preamble mode are
used.
Table 68: CWL Selection
CWL - Primary Choice
Speed Bin
1tCK
2tCK
Preamble
CWL - Alternate Choice
1tCK
Preamble
2tCK Preamble
Preamble
DDR4-1600
9
N/A
11
N/A
DDR4-1866
10
N/A
12
N/A
DDR4-2133
11
N/A
14
N/A
DDR4-2400
12
14
16
16
DDR4-2666
14
16
18
18
DDR4-2933
16
18
20
20
DDR4-3200
16
18
20
20
1. CWL programmable requirement for MR2[5:3].
Note:
When operating in 2tCK WRITE preamble mode, tWTR (command based) and tWR
(MR0[11:9]) must be programmed to a value 1 clock greater than the tWTR and tWR setting normally required for the applicable speed bin to be JEDEC compliant; however,
Micron's DDR4 DRAMs do not require these additional tWTR and tWR clocks. The
CAS_n-to-CAS_n command delay to either a different bank group (tCCD_S) or the same
bank group (tCCD_L) have minimum timing requirements that must be satisfied between WRITE commands and are stated in the Timing Parameters by Speed Bin tables.
Figure 108: 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 4
1t CK Mode
CMD
WRITE
WRITE
CK_c
CK_t
tCCD
=4
WL
DQS_t,
DQS_c
Preamble
D0
DQ
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D1
D2
D3
D4
D5
D6
D7
D0
D1
2t CK Mode
CMD
WRITE
WRITE
CK_c
CK_t
tCCD
DQS_t,
DQS_c
=4
WL
Preamble
D0
DQ
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4Gb: x4, x8, x16 DDR4 SDRAM
Programmable Preamble Modes and DQS Postambles
Figure 109: 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 5
1t CK Mode
CMD
WRITE
WRITE
CK_c
CK_t
tCCD
=5
WL
DQS_t,
DQS_c
Preamble
Preamble
D0
DQ
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
2t CK Mode: t CCD = 5 is not allowed in 2t CK mode.
Note:
1. tCCD_S and tCCD_L = 5 tCKs is not allowed when in 2tCK WRITE preamble mode.
Figure 110: 1tCK vs. 2 tCK WRITE Preamble Mode, tCCD = 6
1t CK Mode
CMD
WRITE
WRITE
CK_c
CK_t
tCCD
=6
WL
DQS_t,
DQS_c
Preamble
Preamble
D0
DQ
D1
D2
D3
D4
D5
D6
D7
D5
D6
D7
D0
D1
D2
D3
D0
D1
D2
D3
2t CK Mode
CMD
WRITE
WRITE
CK_c
CK_t
tCCD
DQS_t,
DQS_c
=6
WL
Preamble
Preamble
D0
DQ
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D1
D2
D3
D4
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4Gb: x4, x8, x16 DDR4 SDRAM
Programmable Preamble Modes and DQS Postambles
READ Preamble Mode
MR4[11] = 0 selects 1tCK READ preamble mode and MR4[11] = 1 selects 2tCK READ preamble mode. Examples are shown in the following figure.
Figure 111: 1tCK vs. 2tCK READ Preamble Mode
1tCK Mode
RD
CL
CK_c
CK_t
Preamble
DQS_t,
DQS_c
DQ
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
2tCK Mode
RD
CL
CK_c
CK_t
Preamble
DQS_t,
DQS_c
DQ
READ Preamble Training
DDR4 supports READ preamble training via MPR reads; that is, READ preamble training is allowed only when the DRAM is in the MPR access mode. The READ preamble
training mode can be used by the DRAM controller to train or "read level" its DQS receivers. READ preamble training is entered via an MRS command (MR4[10] = 1 is enabled and MR4[10] = 0 is disabled). After the MRS command is issued to enable READ
preamble training, the DRAM DQS signals are driven to a valid level by the time tSDO is
satisfied. During this time, the data bus DQ signals are held quiet, that is, driven HIGH.
The DQS_t signal remains driven LOW and the DQS_c signal remains driven HIGH until
an MPR Page0 READ command is issued (MPR0 through MPR3 determine which pattern is used), and when CAS latency (CL) has expired, the DQS signals will toggle normally depending on the burst length setting. To exit READ preamble training mode, an
MRS command must be issued, MR4[10] = 0.
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4Gb: x4, x8, x16 DDR4 SDRAM
Programmable Preamble Modes and DQS Postambles
Figure 112: READ Preamble Training
CMD
MRS
MPR RD
tSDO
CL
DQS_c
DQS_t,
DQs (Quiet/Driven HIGH)
D0
D1
D2
D3
D4
D5
D6
D7
WRITE Postamble
Whether the 1tCK or 2tCK WRITE preamble mode is selected, the WRITE postamble remains the same at ½tCK.
Figure 113: WRITE Postamble
1tCK Mode
WR
WL
CK_c
CK_t
Postamble
DQS_t,
DQS_c
D0
DQ
D1
D2
D3
D4
D5
D6
D7
2tCK Mode
WR
WL
CK_c
CK_t
Postamble
DQS_t,
DQS_c
DQ
D0
D1
D2
D3
D4
D5
D6
D7
READ Postamble
Whether the 1tCK or 2tCK READ preamble mode is selected, the READ postamble remains the same at ½tCK.
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4Gb: x4, x8, x16 DDR4 SDRAM
Programmable Preamble Modes and DQS Postambles
Figure 114: READ Postamble
1tCK Mode
RD
CL
CK_c
CK_t
Postamble
DQS_t,
DQS_c
D0
DQ
D1
D2
D3
D4
D5
D6
D7
2tCK Mode
RD
CL
CK_c
CK_t
Postamble
DQS_t,
DQS_c
DQ
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D0
184
D1
D2
D3
D4
D5
D6
D7
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4Gb: x4, x8, x16 DDR4 SDRAM
Bank Access Operation
Bank Access Operation
DDR4 supports bank grouping: x4/x8 DRAMs have four bank groups (BG[1:0]), and
each bank group is comprised of four subbanks (BA[1:0]); x16 DRAMs have two bank
groups (BG[0]), and each bank group is comprised of four subbanks. Bank accesses to
different banks' groups require less time delay between accesses than bank accesses to
within the same bank's group. Bank accesses to different bank groups require tCCD_S
(or short) delay between commands while bank accesses within the same bank group
require tCCD_L (or long) delay between commands.
Figure 115: Bank Group x4/x8 Block Diagram
Bank 3
Bank 2
Bank 1
Bank 0
Memory Array
Bank Group 0
CMD/ADDR
Bank 3
Bank 2
Bank 1
Bank 0
Memory Array
Bank 3
Bank 2
Bank 1
Bank 0
Memory Array
Bank Group 1
Bank Group 2
Bank 3
Bank 2
Bank 1
Bank 0
Memory Array
Bank Group 3
CMD/ADDR
register
Sense amplifiers
Sense amplifiers
Sense amplifiers
Sense amplifiers
Local I/O gating
Local I/O gating
Local I/O gating
Local I/O gating
Global I/O gating
Data I/O
1. Bank accesses to different bank groups require tCCD_S.
2. Bank accesses within the same bank group require tCCD_L.
Notes:
Table 69: DDR4 Bank Group Timing Examples
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Parameter
DDR4-1600
DDR4-2133
DDR4-2400
tCCD_S
4nCK
4nCK
4nCK
tCCD_L
4nCK or 6.25ns
4nCK or 5.355ns
4nCK or 5ns
tRRD_S
(½K)
4nCK or 5ns
4nCK or 3.7ns
4nCK or 3.3ns
tRRD_L
(½K)
4nCK or 6ns
4nCK or 5.3ns
4nCK or 4.9ns
tRRD_S
(1K)
4nCK or 5ns
4nCK or 3.7ns
4nCK or 3.3ns
tRRD_L
(1K)
4nCK or 6ns
4nCK or 5.3ns
4nCK or 4.9ns
tRRD_S
(2K)
4nCK or 6ns
4nCK or 5.3ns
4nCK or 5.3ns
tRRD_L
(2K)
4nCK or 7.5ns
4nCK or 6.4ns
4nCK or 6.4ns
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4Gb: x4, x8, x16 DDR4 SDRAM
Bank Access Operation
Table 69: DDR4 Bank Group Timing Examples (Continued)
Notes:
Parameter
DDR4-1600
DDR4-2133
DDR4-2400
tWTR_S
2nCK or 2.5ns
2nCK or 2.5ns
2nCK or 2.5ns
tWTR_L
4nCK or 7.5ns
4nCK or 7.5ns
4nCK or 7.5ns
1. Refer to Timing Tables for actual specification values, these values are shown for reference only and are not verified for accuracy.
2. Timings with both nCK and ns require both to be satisfied; that is, the larger time of the
two cases must be satisfied.
Figure 116: READ Burst tCCD_S and tCCD_L Examples
CK_c
CK_t
Command
T0
T1
READ
DES
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
DES
DES
READ
DES
DES
DES
DES
DES
READ
DES
tCCD_L
tCCD_S
Bank Group
(BG)
BG a
BG b
BG b
Bank
Bank c
Bank c
Bank c
Address
Col n
Col n
Col n
Don’t Care
Notes:
1. tCCD_S; CAS_n-to-CAS_n delay (short). Applies to consecutive CAS_n to different bank
groups (T0 to T4).
2. tCCD_L; CAS_n-to-CAS_n delay (long). Applies to consecutive CAS_n to the same bank
group (T4 to T10).
Figure 117: Write Burst tCCD_S and tCCD_L Examples
CK_c
CK_t
Command
T0
T1
WRITE
DES
T2
T3
T4
T5
T6
DES
DES
WRITE
DES
DES
T7
T8
T9
T10
T11
DES
DES
DES
WRITE
DES
tCCD_L
tCCD_S
Bank Group
(BG)
BG a
BG b
BG b
Bank
Bank c
Bank c
Bank c
Coln
Coln
Coln
Address
Don’t Care
Notes:
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1. tCCD_S; CAS_n-to-CAS_n delay (short). Applies to consecutive CAS_n to different bank
groups (T0 to T4).
2. tCCD_L; CAS_n-to-CAS_n delay (long). Applies to consecutive CAS_n to the same bank
group (T4 to T10).
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4Gb: x4, x8, x16 DDR4 SDRAM
Bank Access Operation
Figure 118: tRRD Timing
CK_c
CK_t
Command
T0
T1
ACT
DES
T2
T3
T4
T5
T6
DES
DES
ACT
DES
DES
T8
T9
T10
T11
DES
DES
DES
ACT
DES
tRRD_L
tRRD_S
Bank
Group
(BG)
T7
BG a
BG b
BG b
Bank
Bank c
Bank c
Bank d
Address
Row n
Row n
Row n
Don’t Care
1. tRRD_S; ACTIVATE-to-ACTIVATE command period (short); applies to consecutive ACTIVATE commands to different bank groups (T0 and T4).
2. tRRD_L; ACTIVATE-to-ACTIVATE command period (long); applies to consecutive ACTIVATE commands to the different banks in the same bank group (T4 and T10).
Notes:
Figure 119: tWTR_S Timing (WRITE-to-READ, Different Bank Group, CRC and DM Disabled)
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
Tb1
WRITE
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
READ
Valid
CK_c
CK_t
Command
tWTR_S
Bank
Group
Bank
Address
BGa
BGb
Bank c
Bank c
Col n
Col n
tWPRE
tWPST
DQS, DQS_c
DI
n
DQ
DI
n+ 1
DI
n+ 2
DI
n+ 3
DI
n+ 4
DI
n+ 5
DI
n+ 6
DI
n+ 7
RL
WL
Time Break
Note:
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Transitioning Data
Don’t Care
1. tWTR_S: delay from start of internal write transaction to internal READ command to a
different bank group.
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4Gb: x4, x8, x16 DDR4 SDRAM
Bank Access Operation
Figure 120: tWTR_L Timing (WRITE-to-READ, Same Bank Group, CRC and DM Disabled)
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
Tb1
WRITE
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
READ
Valid
CK_c
CK_t
Command
tWTR_L
Bank
Group
Bank
Address
BGa
BGa
Bank c
Bank c
Col n
Col n
tWPRE
tWPST
DQS, DQS_c
DI
n
DQ
DI
n+ 1
DI
n+ 2
DI
n+ 3
DI
n+ 4
DI
n+ 5
DI
n+ 6
DI
n+ 7
RL
WL
Time Break
Note:
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Transitioning Data
Don’t Care
1. tWTR_L: delay from start of internal write transaction to internal READ command to the
same bank group.
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
READ Operation
Read Timing Definitions
The read timings shown below are applicable in normal operation mode, that is, when
the DLL is enabled and locked.
Note: tDQSQ = both rising/falling edges of DQS; no tAC defined.
Rising data strobe edge parameters:
• tDQSCK (MIN)/(MAX) describes the allowed range for a rising data strobe edge relative to CK.
• tDQSCK is the actual position of a rising strobe edge relative to CK.
• tQSH describes the DQS differential output HIGH time.
• tDQSQ describes the latest valid transition of the associated DQ pins.
• tQH describes the earliest invalid transition of the associated DQ pins.
Falling data strobe edge parameters:
• tQSL describes the DQS differential output LOW time.
• tDQSQ describes the latest valid transition of the associated DQ pins.
• tQH describes the earliest invalid transition of the associated DQ pins.
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
Figure 121: Read Timing Definition
CK_c
CK_t
tDQSCK
tDQSCK
tDQSCK
(MIN) tDQSCK (MAX) tDQSCK (MIN) tDQSCK (MAX)
MAX
center
tDQSCK
MIN
tDQSCKi
tDQSCKi
Rising strobe
region
window
Rising strobe
region
window
tDQSCKi
tDQSCKi
Rising strobe
region
window
Rising strobe
region
window
tDQSCKi
tDQSCKi
Rising strobe
region
window
Rising strobe
region
window
tDQSCK
tDQSCK
tQSH/DQS_c
tQSH/DQS_t
DQS_c
DQS_t
tQH
tQH
tDQSQ
tDQSQ
Associated
DQ Pins
Table 70: Read to Write and Write to Read Command Intervals
Access Type
Bank Group
Timing Parameters
Note
Read to Write, minimum
Same
CL - CWL + RBL/2 + 1tCK + tWPRE
1,2
Write to Read, minimum
Notes:
Different
CL - CWL + RBL/2 +
Same
Different
1tCK
+
tWPRE
1,2
CWL + WBL/2 +
tWTR_L
1,3
CWL + WBL/2 +
tWTR_S
1,3
1. These timings require extended calibrations times tZQinit and tZQCS.
2. RBL : Read burst length associated with Read command, RBL = 8 for fixed 8 and on-thefly mode 8 and RBL = 4 for fixed BC4 and on-the-fly mode BC4.
3. WBL : Write burst length associated with Write command, WBL = 8 for fixed 8 and onthe-fly mode 8 or BC4 and WBL = 4 for fixed BC4 only.
Read Timing – Clock-to-Data Strobe Relationship
The clock-to-data strobe relationship shown below is applicable in normal operation
mode, that is, when the DLL is enabled and locked.
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
Rising data strobe edge parameters:
• tDQSCK (MIN)/(MAX) describes the allowed range for a rising data strobe edge relative to CK.
t
• DQSCK is the actual position of a rising strobe edge relative to CK.
• tQSH describes the data strobe high pulse width.
• tHZ(DQS) DQS strobe going to high, nondrive level (shown in the postamble section
of the figure below).
Falling data strobe edge parameters:
• tQSL describes the data strobe low pulse width.
• tLZ(DQS) DQS strobe going to low, initial drive level (shown in the preamble section
of the figure below).
Figure 122: Clock-to-Data Strobe Relationship
RL measured
to this point
CK_t
CK_c
tDQSCK (MIN)
tDQSCK (MIN)
tDQSCK (MIN)
tDQSCK (MIN)
tHZ(DQS) MIN
tLZ(DQS) MIN
DQS_t, DQS_c
Early Strobe
tQSH
tQSL
tQSH
tQSL
tQSH
tQSL
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
tRPRE
Bit 7
tRPST
tDQSCK (MAX)
tDQSCK (MAX)
tDQSCK (MAX)
tDQSCK (MAX)
tLZ(DQS) MAX
DQS_t, DQS_c
Late Strobe
Bit 0
tRPRE
Notes:
Bit 1
tQSL
Bit 2
tQSH
Bit 3
Bit 4
Bit 5
Bit 6
tRPST
Bit 7
tQSL
1. Within a burst, the rising strobe edge will vary within tDQSCKj while at the same voltage and temperature. However, when the device, voltage, and temperature variations
are incorporated, the rising strobe edge variance window can shift between tDQSCK
(MIN) and tDQSCK (MAX).
2.
3.
4.
5.
6.
7.
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tQSH
tHZ(DQS) MAX
A timing of this window's right edge (latest) from rising CK_t, CK_c is limited by a device's actual tDQSCK (MAX). A timing of this window's left inside edge (earliest) from rising CK_t, CK_c is limited by tDQSCK (MIN).
Notwithstanding Note 1, a rising strobe edge with tDQSCK (MAX) at T(n) can not be immediately followed by a rising strobe edge with tDQSCK (MIN) at T(n + 1) because other
timing relationships (tQSH, tQSL) exist: if tDQSCK(n + 1) < 0: tDQSCK(n) < 1.0 tCK - (tQSH
(MIN) + tQSL (MIN)) - | tDQSCK(n + 1) |.
The DQS_t, DQS_c differential output HIGH time is defined by tQSH, and the DQS_t,
DQS_c differential output LOW time is defined by tQSL.
tLZ(DQS) MIN and tHZ(DQS) MIN are not tied to tDQSCK (MIN) (early strobe case), and
tLZ(DQS) MAX and tHZ(DQS) MAX are not tied to tDQSCK (MAX) (late strobe case).
The minimum pulse width of READ preamble is defined by tRPRE (MIN).
The maximum READ postamble is bound by tDQSCK (MIN) plus tQSH (MIN) on the left
side and tHZDSQ (MAX) on the right side.
The minimum pulse width of READ postamble is defined by tRPST (MIN).
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
8. The maximum READ preamble is bound by tLZDQS (MIN) on the left side and tDQSCK
(MAX) on the right side.
Read Timing – Data Strobe-to-Data Relationship
The data strobe-to-data relationship is shown below and is applied when the DLL is enabled and locked.
Note: tDQSQ: both rising/falling edges of DQS; no tAC defined.
Rising data strobe edge parameters:
• tDQSQ describes the latest valid transition of the associated DQ pins.
• tQH describes the earliest invalid transition of the associated DQ pins.
Falling data strobe edge parameters:
• tDQSQ describes the latest valid transition of the associated DQ pins.
• tQH describes the earliest invalid transition of the associated DQ pins.
Data valid window parameters:
• tDVWd is the Data Valid Window per device per UI and is derived from [ tQH - tDQSQ]
of each UI on a given DRAM
• tDVWp is the Data Valid Window per pin per UI and is derived [ tQH - tDQSQ] of each
UI on a pin of a given DRAM
Figure 123: Data Strobe-to-Data Relationship
T0
T1
READ
DES
T2
T9
T10
T11
T12
T13
T14
T15
T16
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command3
RL = AL + CL
Address4
Bank,
Col n
tDQSQ
tRPRE
tDQSQ
(MAX)
(MAX)
tRPST
(1nCK)
DQS_t, DQS_c
tQH
DQ2
(Last data )
tQH
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
n+4
DOUT
n+5
DOUT
n+6
DOUT
n+7
tDVWp
DQ2
(First data no longer)
DOUT
n+1
DOUT
n
DOUT
n+2
DOUT
n+3
DOUT
n+4
DOUT
n+5
DOUT
n+6
DOUT
n+7
tDVWp
DOUT
n
All DQ collectively
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
n+4
DOUT
n+5
tDVWd
Notes:
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DOUT
n+6
DOUT
n+7
tDVWd
Don’t Care
1. BL = 8, RL = 11 (AL = 0, CL = 1) , Premable = 1tCK.
2. DOUTn = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during
READ commands at T0.
5. Output timings are referenced to VDDQ, and DLL on for locking.
6. tDQSQ defines the skew between DQS to data and does not define DQS to clock.
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ
can vary (either early or late) within a burst.
tLZ(DQS), tLZ(DQ), tHZ(DQS),
and tHZ(DQ) Calculations
tHZ
and tLZ transitions occur in the same time window as valid data transitions. These
parameters are referenced to a specific voltage level that specifies when the device output is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and
tLZ(DQ). The figure below shows a method to calculate the point when the device is no
longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ), by
measuring the signal at two different voltages. The actual voltage measurement points
are not critical as long as the calculation is consistent. tLZ(DQS), tLZ(DQ), tHZ(DQS),
and tHZ(DQ) are defined as singled-ended parameters.
Figure 124: tLZ and tHZ Method for Calculating Transitions and Endpoints
tLZ(DQ):
CK_t, CK_c rising crossing at RL
tHZ(DQ)
tHZ(DQ)
with BL8: CK_t, CK_c rising crossing at RL + 4CK
with BC4: CK_t, CK_c rising crossing at RL + 2CK
CK_t
CK_c
Begin point:
Extrapolated point at VDDQ
DQ
tLZ
tHZ
VDDQ
VDDQ
VSW2
DQ
VSW2
0.7 × VDDQ
0.7 × VDDQ
VSW1
VSW1
0.4 × VDDQ
0.4 × VDDQ
Begin point: Extrapolated point (low level)
Notes:
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1. Vsw1 = (0.70 - 0.04) × VDDQ for both tLZ and tHZ.
2. Vsw2 = (0.70 + 0.04) × VDDQ for both tLZ and tHZ.
3. Extrapolated point (low level) = VDDQ/(50 + 34) × 34 = 0.4 × VDDQ
Driver impedance = RZQ/7 = 34Ω
VTT test load = 50Ω to VDDQ.
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
tRPRE
Calculation
Figure 125: tRPRE Method for Calculating Transitions and Endpoints
CK_t
VDD /2
CK_c
Single-ended signal provided as background information
VDDQ
DQS_t
0.7 × VDDQ
0.4 × VDDQ
DQS_c
VDDQ
0.7 × VDDQ
0.4 × VDDQ
DQS_t
DQS_t
DQS_c
VDDQ
0.7 × VDDQ
DQS_c
0.4 × VDDQ
Resulting differential signal relevanttRPRE
for specification
0.6 × VDDQ
VSW2
0.3 × VDDQ
VSW1
DQS_t, DQS_c
0V
tRPRE
Notes:
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beginst1)
(
tRPRE
ends t(2)
1. Vsw1 = (0.3 - 0.04) × VDDQ.
2. Vsw2 = (0.30 + 0.04) × VDDQ.
3. DQS_t and DQS_c low level = VDDQ/(50 + 34) × 34 = 0.4 × VDDQ
Driver impedance = RZQ/7 = 34Ω
VTT test load = 50Ω to VDDQ.
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READ Operation
tRPST
Calculation
Figure 126: tRPST Method for Calculating Transitions and Endpoints
CK_t
VDD /2
CK_c
Single-ended signal provided as background information
VDDQ
0.7 × VDDQ
0.4 × VDDQ
DQS_t
VDDQ
DQS_c
0.7 × VDDQ
0.4 × VDDQ
VDDQ
DQS_c
0.7 × VDDQ
DQS_t
Resulting differential signal relevanttRPST
for specification
tRPST
beginst(1)
0V
VSW2
–0.3 × VDDQ
VSW1
–0.6 × VDDQ
DQS_t, DQS_c
tRPST
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
ends t(2)
1. Vsw1 = (–0.3 - 0.04) × VDDQ.
2. Vsw2 = (–0.30 + 0.04) × VDDQ.
3. DQS_t and DQS_c low level = VDDQ/(50 + 34) × 34 = 0.4 × VDDQ
Driver impedance = RZQ/7 = 34Ω
VTT test load = 50Ω to VDDQ.
195
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
READ Burst Operation
DDR4 READ commands support bursts of BL8 (fixed), BC4 (fixed), and BL8/BC4 onthe-fly (OTF); OTF uses address A12 to control OTF when OTF is enabled:
• A12 = 0, BC4 (BC4 = burst chop)
• A12 = 1, BL8
READ commands can issue precharge automatically with a READ with auto precharge
command (RDA), and is enabled by A10 HIGH:
• READ command with A10 = 0 (RD) performs standard read, bank remains active after
READ burst.
• READ command with A10 = 1 (RDA) performs read with auto precharge, bank goes in
to precharge after READ burst.
Figure 127: READ Burst Operation, RL = 11 (AL = 0, CL = 11, BL8)
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Ta9
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
Bank Group
Address
BGa
Address
Bank
col n
tRPRE
tRPST
DQS_t
DQS_c
DO
n
DQ
DO
n+ 1
DO
n+ 2
DO
n+ 3
DO
n+ 4
DO
n+ 5
DO
n+ 6
DO
n+ 7
CL = 11
RL = AL + CL
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL8, RL = 0, AL = 0, CL = 11, Preamble = 1tCK.
2. DO n = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
command at T0.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
196
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
Figure 128: READ Burst Operation, RL = 21 (AL = 10, CL = 11, BL8)
T0
T1
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
Tb2
Tb3
Tb4
Tb5
Tb6
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
Bank Group
Address
BGa
Address
Bank
col n
tRPRE
tRPST
DQS_t
DQS_c
DO
n
DQ
AL = 10
DO
n+ 1
DO
n+ 2
DO
n+ 3
DO
n+ 4
DO
n+ 5
DO
n+ 6
DO
n+ 7
CL = 11
RL = AL + CL
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL8, RL = 21, AL = (CL - 1), CL = 11, Preamble = 1tCK.
2. DO n = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
command at T0.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
197
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
READ Operation Followed by Another READ Operation
Figure 129: Consecutive READ (BL8) with 1tCK Preamble in Different Bank Group
T0
T1
READ
DES
T3
T4
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T2
CK_c
CK_t
Command
DES
tCCD_S
=4
Bank Group
Address
BGa
BGb
Address
Bank
Col n
Bank
Col b
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
DO
b
DO
b+1
DO
b+2
DO
b+3
DO
b+4
DO
b+5
DO
b+6
DO
b+7
RL = 11
Time Break
Transitioning Data
Don’t Care
1. BL8, AL = 0, CL = 11, Preamble = 1tCK.
2. DO n (or b) = data-out from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
Notes:
Figure 130: Consecutive READ (BL8) with 2tCK Preamble in Different Bank Group
T0
T1
READ
DES
T3
T4
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T2
CK_c
CK_t
Command
DES
tCCD_S
=4
Bank Group
Address
BGa
BGb
Address
Bank
Col n
Bank
Col b
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
DO
b
DO
b+1
DO
b+2
DO
b+3
DO
b+4
DO
b+5
DO
b+6
DO
b+7
RL = 11
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL8, AL = 0, CL = 11, Preamble = 2tCK.
2. DO n (or b) = data-out from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
198
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
Figure 131: Nonconsecutive READ (BL8) with 1tCK Preamble in Same or Different Bank Group
T0
T1
READ
DES
T2
T3
T4
DES
DES
T5
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
DES
tCCD_S/L
=5
Bank Group
Address
BGa
BGb
Address
Bank
Col n
Bank
Col b
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
DO
b
DO
b+1
DO
b+2
DO
b+3
DO
b+4
DO
b+5
DO
b+6
DO
b+7
RL = 11
Time Break
Don’t Care
Transitioning Data
1. BL8, AL = 0, CL = 11, Preamble = 1tCK, tCCD_S/L = 5.
2. DO n (or b) = data-out from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and T5.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
Notes:
Figure 132: Nonconsecutive READ (BL8) with 2tCK Preamble in Same or Different Bank Group
T0
T1
READ
DES
T5
T6
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T2
CK_c
CK_t
Command
DES
tCCD_S/L
=6
Bank Group
Address
BGa
BGa or
BGb
Address
Bank
Col n
Bank
Col b
tRPRE
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
DO
b
DO
b+1
DO
b+2
DO
b+3
DO
b+4
DO
b+5
DO
b+6
DO
b+7
RL = 11
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL8, AL = 0, CL = 11, Preamble = 2tCK, tCCD_S/L = 6.
2. DO n (or b) = data-out from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during
READ commands at T0 and T6.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
6. 6 tCCD_S/L = 5 isn’t allowed in 2tCK preamble mode.
199
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
Figure 133: READ (BC4) to READ (BC4) with 1tCK Preamble in Different Bank Group
T0
T1
READ
DES
T3
T4
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T2
CK_c
CK_t
Command
DES
tCCD_S
=4
Bank Group
Address
BGa
BGb
Address
Bank
Col n
Bank
Col b
tRPRE
tRPST
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DO
b
DO
b+1
DO
b+2
DO
b+3
RL = 11
Time Break
Transitioning Data
Don’t Care
1. BL8, AL = 0, CL = 11, Preamble = 1tCK.
2. DO n (or b) = data-out from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ
commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
Notes:
Figure 134: READ (BC4) to READ (BC4) with 2tCK Preamble in Different Bank Group
T0
T1
READ
DES
T2
T3
T4
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
DES
tCCD_S
=4
Bank Group
Address
BGa
BGb
Address
Bank
Col n
Bank
Col b
tRPRE
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DO
b
DO
b+1
DO
b+2
DO
b+3
RL = 11
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL8, AL = 0, CL = 11, Preamble = 2tCK.
2. DO n (or b) = data-out from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ
commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
200
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
Figure 135: READ (BL8) to READ (BC4) OTF with 1tCK Preamble in Different Bank Group
T0
T1
READ
DES
T3
T4
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T2
CK_c
CK_t
Command
DES
tCCD_S
=4
Bank Group
Address
BGa
BGb
Address
Bank
Col n
Bank
Col b
t RPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
DO
b
DO
b+1
DO
b+2
DO
b+3
RL = 11
Time Break
Notes:
Transitioning Data
Don’t Care
1. BL = 8, AL =0, CL = 11, Preamble = 1tCK.
2. DO n (or b) = data-out from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0. BC4
setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
Figure 136: READ (BL8) to READ (BC4) OTF with 2tCK Preamble in Different Bank Group
T0
T1
READ
DES
T2
T3
T4
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
DES
tCCD_S
=4
Bank Group
Address
BGa
BGb
Address
Bank
Col n
Bank
Col b
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
DO
b
DO
b+1
DO
b+2
DO
b+3
RL = 11
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL = 8, AL =0, CL = 11, Preamble = 2tCK.
2. DO n (or b) = data-out from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0. BC4
setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
Figure 137: READ (BC4) to READ (BL8) OTF with 1tCK Preamble in Different Bank Group
T0
T1
READ
DES
T2
T3
T4
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
DES
tCCD_S
Bank Group
Address
Address
=4
BGa
BGb
Bank
Col n
Bank
Col b
tRPST
tRPRE
tRPST
tRPRE
DQS_t,
DQS_c
RL = 11
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DO
b
DO
b+1
DO
b+2
DO
b+3
DO
b+4
DO
b+5
DO
b+6
DO
b+7
RL = 11
Time Break
Notes:
Transitioning Data
Don’t Care
1. BL = 8, AL =0, CL = 11, Preamble = 1tCK.
2. DO n (or b) = data-out from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0. BL8
setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
Figure 138: READ (BC4) to READ (BL8) OTF with 2tCK Preamble in Different Bank Group
T0
T1
READ
DES
T2
T3
T4
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
DES
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
tCCD_S
Bank Group
Address
Address
=4
BGa
BGb
Bank
Col n
Bank
Col b
tRPST
tRPRE
DQS_t,
DQS_c
RL = 11
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DO
b
DO
b+1
DO
b+2
DO
b+3
DO
b+4
DO
b+5
DO
b+6
DO
b+7
RL = 11
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL = 8, AL = 0, CL = 11, Preamble = 2tCK.
2. DO n (or b) = data-out from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0. BL8
setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
202
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
READ Operation Followed by WRITE Operation
Figure 139: READ (BL8) to WRITE (BL8) with 1tCK Preamble in Same or Different Bank Group
T0
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T22
CK_c
CK_t
Command
READ
DES
tWR
READ to WRITE command delay
= RL +BL/2 - WL + 2 tCK
Bank Group
Address
Address
tWTR
4 Clocks
BGa
BGa or
BGb
Bank
Col n
Bank
Col b
tRPRE
tWPST
tWPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
WL = 9
Time Break
Notes:
Transitioning Data
Don’t Care
1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE
preamble = 1tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and WRITE commands at T8.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
Figure 140: READ (BL8) to WRITE (BL8) with 2tCK Preamble in Same or Different Bank Group
T0
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
READ
READ to WRITE command delay
= RL +BL/2 - WL + 3 tCK
Bank Group
Address
Address
4 Clocks
BGa
BGa or
BGb
Bank
Col n
Bank
Col b
t
t
RPRE
RPST
t
t
WPRE
t
WR
t
WTR
WPST
DQS_t,
DQS_c
RL = 11
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
WL = 10
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 10 (CWL = 9+1 [see Note
5], AL = 0), WRITE preamble = 2tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
203
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and WRITE commands at T8.
5. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
Figure 141: READ (BC4) OTF to WRITE (BC4) OTF with 1tCK Preamble in Same or Different Bank
Group
T0
T1
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
READ
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
tWR
READ to WRITE command delay
= RL +BL/2 - WL + 2 tCK
Bank Group
Address
Address
tWTR
4 Clocks
BGa
BGa or
BGb
Bank
Col n
Bank
Col b
tRPRE
tRPST
tWPST
tWPRE
DQS_t,
DQS_c
RL = 11
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DI
b
DI
b+1
DI
b+2
DI
b+3
WL = 9
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0),
WRITE preamble = 1tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 (OTF) setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0
and WRITE commands at T6.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
204
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
Figure 142: READ (BC4) OTF to WRITE (BC4) OTF with 2tCK Preamble in Same or Different Bank
Group
T0
T1
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
READ
tWR
READ to WRITE command delay
= RL +BL/2 - WL + 3 tCK
Bank Group
Address
Address
tWTR
4 Clocks
BGa
BGa or
BGb
Bank
Col n
Bank
Col b
tRPRE
tWPST
tWPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DI
b
DI
b+1
DI
b+2
DI
b+3
WL = 10
Time Break
Notes:
Transitioning Data
Don’t Care
1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 10 (CWL = 9 + 1 [see Note
5], AL = 0), WRITE preamble = 2tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 (OTF) setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0
and WRITE commands at T6.
5. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
Figure 143: READ (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Preamble in Same or Different Bank
Group
T0
T1
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T19
T20
DES
DES
CK_c
CK_t
Command
READ
tWR
READ to WRITE command delay
= RL +BL/2 - WL + 2 tCK
Bank Group
Address
Address
tWTR
2 Clocks
BGa
BGa or
BGb
Bank
Col n
Bank
Col b
tRPRE
tRPST
tWPST
tWPRE
DQS_t,
DQS_c
RL = 11
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DI
b
DI
b+1
DI
b+2
DI
b+3
WL = 9
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0),
WRITE preamble = 1tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
205
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 (fixed) setting activated by MR0[1:0] = 01.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
Figure 144: READ (BC4) Fixed to WRITE (BC4) Fixed with 2tCK Preamble in Same or Different Bank
Group
T0
T1
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
READ
tWR
READ to WRITE command delay
= RL +BL/2 - WL + 3 tCK
Bank Group
Address
Address
tWTR
2 Clocks
BGa
BGa or
BGb
Bank
Col n
Bank
Col b
tRPRE
tRPST
tWPST
tWPRE
DQS_t,
DQS_c
RL = 11
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DI
b
DI
b+1
DI
b+2
DI
b+3
WL = 10
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 9 (CWL = 9 + 1 [see Note
5], AL = 0), WRITE preamble = 2tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 (fixed) setting activated by MR0[1:0] = 10.
5. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
206
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
Figure 145: READ (BC4) to WRITE (BL8) OTF with 1tCK Preamble in Same or Different Bank Group
T0
T1
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T20
CK_c
CK_t
Command
READ
DES
tWR
READ to WRITE command delay
= RL +BL/2 - WL + 2 tCK
Bank Group
Address
Address
tWTR
4 Clocks
BGa
BGa or
BGb
Bank
Col n
Bank
Col b
tRPST
tRPRE
tWPST
tWPRE
DQS_t,
DQS_c
RL = 11
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
WL = 9
Time Break
Notes:
Transitioning Data
Don’t Care
1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE
preamble = 1tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0.
BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T6.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
Figure 146: READ (BC4) to WRITE (BL8) OTF with 2tCK Preamble in Same or Different Bank Group
T0
T1
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
READ
tWR
READ to WRITE command delay
= RL +BL/2 - WL + 3 tCK
Bank Group
Address
Address
tWTR
4 Clocks
BGa
BGa or
BGb
Bank
Col n
Bank
Col b
tRPST
tRPRE
tWPST
tWPRE
DQS_t,
DQS_c
RL = 11
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
WL = 10
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 10 (CWL = 9 + 1 [see Note
5], AL = 0), WRITE preamble = 2tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0.
BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T6.
207
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
Figure 147: READ (BL8) to WRITE (BC4) OTF with 1tCK Preamble in Same or Different Bank Group
T0
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T22
CK_c
CK_t
Command
READ
DES
tWR
READ to WRITE command delay
= RL +BL/2 - WL + 2 tCK
Bank Group
Address
Address
tWTR
4 Clocks
BGa
BGa or
BGb
Bank
Col n
Bank
Col b
tRPRE
tWPST
tWPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
DI
b
DI
b+1
DI
b+2
DI
b+3
WL = 9
Time Break
Notes:
Transitioning Data
Don’t Care
1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE
preamble = 1tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0.
BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T8.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
Figure 148: READ (BL8) to WRITE (BC4) OTF with 2tCK Preamble in Same or Different Bank Group
T0
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
READ
tWR
READ to WRITE command delay
= RL +BL/2 - WL + 3 tCK
Bank Group
Address
Address
4 Clocks
BGa
BGa or
BGb
Bank
Col n
Bank
Col b
tRPRE
tRPST
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
RL = 11
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
DI
b
DI
b+1
DI
b+2
DI
b+3
WL = 10
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 10 (CWL = 9 + 1 [see Note
5], AL = 0), WRITE preamble = 2tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
208
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0.
BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T8.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
READ Operation Followed by PRECHARGE Operation
The minimum external READ command to PRECHARGE command spacing to the same
bank is equal to AL + tRTP with tRTP being the internal READ command to PRECHARGE
command delay. Note that the minimum ACT to PRE timing, tRAS, must be satisfied as
well. The minimum value for the internal READ command to PRECHARGE command
delay is given by tRTP (MIN) = MAX (4 × nCK, 7.5ns). A new bank ACTIVATE command
may be issued to the same bank if the following two conditions are satisfied simultaneously:
• The minimum RAS precharge time (tRP [MIN]) has been satisfied from the clock at
which the precharge begins.
• The minimum RAS cycle time (tRC [MIN]) from the previous bank activation has been
satisfied.
Figure 149: READ to PRECHARGE with 1tCK Preamble
T0
T1
T2
T3
T6
T7
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
DES
READ
DES
DES
DES
PRE
DES
DES
DES
DES
DES
DES
DES
DES
ACT
DES
DES
DES
CK_c
CK_t
Command
Bank Group
Address
Address
BGa
or BGb
BGa
Bank a
Col n
BGa
Bank a
(or all)
tRTP
Bank a
Row b
tRP
RL = AL + CL
BC4 Opertaion
DQS_t,
DQS_c
DQ
DO
n
DO
n+1
DO
n+2
DO
n+3
DO
n
DO
n+1
DO
n+2
DO
n+3
BL8 Opertaion
DQS_t,
DQS_c
DQ
DO
n+4
DO
n+5
DO
n+6
DO
n+7
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. RL = 11 (CL = 11, AL = 0 ), Preamble = 1tCK, tRTP = 6, tRP = 11.
2. DO n = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. The example assumes that tRAS (MIN) is satisfied at the PRECHARGE command time (T7)
and that tRC (MIN) is satisfied at the next ACTIVATE command time (T18).
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
209
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
Figure 150: READ to PRECHARGE with 2tCK Preamble
T0
T1
T2
T3
T6
T7
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
DES
READ
DES
DES
DES
PRE
DES
DES
DES
DES
DES
DES
DES
DES
ACT
DES
DES
DES
CK_c
CK_t
Command
Bank Group
Address
BGa or
BGb
BGa
Bank a
Col n
Address
BGa
Bank a
(or all)
Bank a
Row b
tRTP
tRP
RL = AL + CL
BC4 Opertaion
DQS_t,
DQS_c
DQ
DO
n
DO
n+1
DO
n+2
DO
n+3
DO
n
DO
n+1
DO
n+2
DO
n+3
BL8 Opertaion
DQS_t,
DQS_c
DQ
DO
n+4
DO
n+5
DO
n+6
DO
n+7
Time Break
Notes:
Transitioning Data
Don’t Care
1. RL = 11 (CL = 11, AL = 0 ), Preamble = 2tCK, tRTP = 6, tRP = 11.
2. DO n = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. The example assumes that tRAS (MIN) is satisfied at the PRECHARGE command time (T7)
and that tRC (MIN) is satisfied at the next ACTIVATE command time (T18).
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
Figure 151: READ to PRECHARGE with Additive Latency and 1tCK Preamble
T0
T1
T2
T3
T10
T11
T12
T13
T16
T19
T20
T21
T22
T23
T24
T25
T26
T27
DES
READ
DES
DES
DES
DES
DES
DES
PRE
DES
DES
DES
DES
DES
DES
DES
DES
ACT
CK_c
CK_t
Command
Bank Group
Address
Address
BGa or
BGb
BGa
Bank a
Col n
BGa
Bank a
(or all)
AL = CL - 2 = 9
tRTP
Bank a
Row b
tRP
CL = 11
BC4 Opertaion
DQS_t,
DQS_c
DQ
DO
n
DO
n+1
DO
n+2
DO
n+3
DO
n
DO
n+1
DO
n+2
DO
n+3
BL8 Opertaion
DQS_t,
DQS_c
DQ
DO
n+4
DO
n+5
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
DO
n+6
DO
n+7
Transitioning Data
Don’t Care
1. RL =20 (CL = 11, AL = CL - 2), Preamble = 1tCK, tRTP = 6, tRP = 11.
2. DO n = data-out from column n.
210
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. The example assumes that tRAS (MIN) is satisfied at the PRECHARGE command time
(T16) and that tRC (MIN) is satisfied at the next ACTIVATE command time (T27).
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
Figure 152: READ with Auto Precharge and 1tCK Preamble
T0
T1
T2
T3
T6
T7
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
DES
RDA
DES
DES
DES
PRE
DES
DES
DES
DES
DES
DES
DES
DES
ACT
DES
DES
DES
CK_c
CK_t
Command
Bank Group
Address
Address
BGa or
BGb
BGa
Bank a
Col n
BGa
Bank a
Col n
tRTP
Bank a
Row b
tRP
RL = AL + CL
BC4 Opertaion
DQS_t,
DQS_c
DQ
DO
n
DO
n+1
DO
n+2
DO
n+3
DO
n
DO
n+1
DO
n+2
DO
n+3
BL8 Opertaion
DQS_t,
DQS_c
DQ
DO
n+4
DO
n+5
DO
n+6
DO
n+7
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. RL = 11 (CL = 11, AL = 0 ), Preamble = 1tCK, tRTP = 6, tRP = 11.
2. DO n = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. tRTP = 6 setting activated by MR0[A11:9 = 001].
5. The example assumes that tRC (MIN) is satisfied at the next ACTIVATE command time
(T18).
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
211
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
Figure 153: READ with Auto Precharge, Additive Latency, and 1tCK Preamble
T0
T1
T2
T3
T10
T11
T12
T13
T16
T19
T20
T21
T22
T23
T24
T25
T26
T27
DES
RDA
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
ACT
CK_c
CK_t
Command
Bank Group
Address
BGa
BGa
Bank a
Col n
Address
Bank a
Row b
tRTP
AL = CL - 2 = 9
tRP
CL = 11
BC4 Opertaion
DQS_t,
DQS_c
DQ
DO
n
DO
n+1
DO
n+2
DO
n+3
DO
n
DO
n+1
DO
n+2
DO
n+3
BL8 Opertaion
DQS_t,
DQS_c
DQ
DO
n+4
DO
n+5
DO
n+6
Time Break
Notes:
DO
n+7
Transitioning Data
Don’t Care
1. RL = 20 (CL = 11, AL = CL - 2), Preamble = 1tCK, tRTP = 6, tRP = 11.
2. DO n = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. tRTP = 6 setting activated by MR0[11:9] = 001.
5. The example assumes that tRC (MIN) is satisfied at the next ACTIVATE command time
(T27).
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
READ Operation with Read Data Bus Inversion (DBI)
Figure 154: Consecutive READ (BL8) with 1tCK Preamble and DBI in Different Bank Group
T0
T1
READ
DES
T2
T3
T4
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
DES
tCCD_S
=4
Bank Group
Address
BGa
BGb
Address
Bank
Col n
Bank
Col b
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11 + 2 (Read DBI adder)
DQ
DO
n
DO
n+1
DO
n+2
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
DO
b
DO
b+1
DO
b+2
DO
DO
DO
b + 3 b +4 _ b + 5
DO
b+6
DO
b+7
DBI
n
DBI
n+1
DBI
n+2
DBI
n+3
DBI
n+4
DBI
n+5
DBI
n+6
DBI
n+7
DBI
b
DBI
b+1
DBI
b+2
DBI
b+3
DBI
b+6
DBI
b+7
RL = 11 + 2 (Read DBI adder)
DBI_n
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
DBI
DBI
b+4 b+5
Transitioning Data
Don’t Care
1. BL = 8, AL = 0, CL = 11, Preamble = 1tCK, RL = 11 + 2 (Read DBI adder).
212
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
2. DO n (or b) = data-out from column n (or b); DBI n (or b) = data bus inversion from column n (or b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Enable.
READ Operation with Command/Address Parity (CA Parity)
Figure 155: Consecutive READ (BL8) with 1tCK Preamble and CA Parity in Different Bank Group
T0
T1
READ
DES
T3
T4
T7
T8
T13
T14
T15
T16
T17
T18
T19
T20
T21
T20
T21
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T2
CK_c
CK_t
Command
DES
tCCD_S
Bank Group
Address
Address
Parity
=4
BGa
BGb
Bank
Col n
Bank
Col b
tRPRE
tRPST
DQS_t,
DQS_c
RL = 15
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
DO
b
DO
b+1
DO
b+2
DO
DO
DO
b + 3 b +4 _ b + 5
DO
b+6
DO
b+7
RL = 15
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL = 8, AL = 0, CL = 11, PL = 4, (RL = CL + AL + PL = 15), Preamble = 1tCK.
2. DO n (or b) = data-out from column n (or b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[A1:A0 = 00] or MR0[A1:A0 = 01] and A12 = 1 during
READ commands at T0 and T4.
5. CA parity = Enable, CS to CA latency = Disable, Read DBI = Disable.
213
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
Figure 156: READ (BL8) to WRITE (BL8) with 1tCK Preamble and CA Parity in Same or Different Bank
Group
T0
T1
T7
T8
T9
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T26
CK_c
CK_t
Command
READ
DES
tWR
READ to WRITE command delay
= RL +BL/2 - WL + 2 tCK
Bank Group
Address
Address
Parity
4 Clocks
BGa
BGa or
BGb
Bank
Col n
Bank
Col b
tRPRE
tRPST
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
RL = 15
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
WL = 13
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL = 8, AL = 0, CL = 11, PL = 4, (RL = CL + AL + PL = 15), READ preamble = 1tCK, CWL = 9,
AL = 0, PL = 4, (WL = CL + AL + PL = 13), WRITE preamble = 1tCK.
2. DO n = data-out from column n, DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and WRITE command at T8.
5. CA parity = Enable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
214
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
READ Followed by WRITE with CRC Enabled
Figure 157: READ (BL8) to WRITE (BL8 or BC4: OTF) with 1tCK Preamble and Write CRC in Same or
Different Bank Group
T0
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
READ
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T22
CK_c
CK_t
Command
DES
tWR
READ to WRITE command delay
= RL +BL/2 - WL + 2 tCK
Bank Group
Address
Address
4 Clocks
BGa
BGa or
BGb
Bank
Col n
Bank
Col b
tRPRE
tRPST
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
RL = 11
DO
n
DO
n+1
DO
n+2
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
CRC
DO
n
DO
n+1
DO
n+2
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
CRC
DQ x4,
READ: BL = 8,
WRITE: BC = 4 (OTF)
DO
n
DO
n+1
DO
n+2
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
DI
b
DI
b+1
DI
b+2
DI
b+3
CRC
DQ x8/X16,
READ: BL = 8,
WRITE: BC = 4 (OTF)
DO
n
DO
n+1
DO
n+2
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
DI
b
DI
b+1
DI
b+2
DI
b+3
CRC
DQ x4,
BL = 8
CRC
WL = 9
DQ x8/X16,
BL = 8
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
CRC
Don’t Care
1. BL = 8 (or BC = 4: OTF for Write), RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL =
9 (CWL = 9, AL = 0), WRITE preamble = 1tCK.
2. DO n = data-out from column n, DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and WRITE commands at T8.
5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T8.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Enable.
215
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
Figure 158: READ (BC4: Fixed) to WRITE (BC4: Fixed) with 1tCK Preamble and Write CRC in Same or
Different Bank Group
T0
T1
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
READ
tWR
READ to WRITE command delay
= RL +BL/2 - WL + 2 tCK
Bank Group
Address
Address
tWTR
2 Clocks
BGa
BGa or
BGb
Bank
Col n
Bank
Col b
tRPRE
tWPST
tWPRE
tRPST
DQS_t,
DQS_c
RL = 11
DQ x4,
BC = 4 (Fixed)
DO
n
DO
n+1
DO
n+2
DO
n+3
DI
b
DI
b+1
DI
b+2
DI
b+3
CRC
DO
n
DO
n+1
DO
n+2
DO
n+3
DI
b
DI
b+1
DI
b+2
DI
b+3
CRC
CRC
WL = 9
DQ x8/X16,
BC = 4 (Fixed)
Time Break
Notes:
Transitioning Data
Don’t Care
1. BC = 4 (Fixed), RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL =
0), WRITE preamble = 1tCK.
2. DO n = data-out from column n, DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Enable.
READ Operation with Command/Address Latency (CAL) Enabled
Figure 159: Consecutive READ (BL8) with CAL (3tCK) and 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T5
T6
T7
T8
T13
T14
T15
T17
T18
T19
T21
T22
T23
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
tCAL
Command
w/o CS_n
DES
tCAL
=3
DES
READ
DES
DES
=3
CS_n
tCCD_S
Bank Group
Address
Address
=4
BGa
BGb
Bank
Col n
Bank
Col b
tRPST
tRPRE
DQS_t,
DQS_c
RL = 11
DI
n
DQ
DI
n+1
DI
n+2
DI
n+5
DI
n+6
DI
n+7
DI
b
DI
b+1
DI
b+2
DI
b+5
DI
b+6
DI
b+7
RL = 11
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK.
216
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
2. DI n (or b) = data-in from column n (or b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T3 and T7.
5. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. Enabling CAL mode does not impact ODT control timings. The same timing relationship
relative to the command/address bus as when CAL is disabled should be maintained.
Figure 160: Consecutive READ (BL8) with CAL (4tCK) and 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T5
READ
DES
DES
T6
T7
T8
T14
T15
T16
T18
T19
T21
T22
T23
T24
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
tCAL
Command
w/o CS_n
DES
tCAL
=4
DES
=4
DES
CS_n
tCCD_S
Bank Group
Address
Address
=4
BGa
BGb
Bank
Col n
Bank
Col b
tRPST
tRPRE
DQS_t,
DQS_c
RL = 11
DI
n
DQ
DI
n+1
DI
n+2
DI
n+5
DI
n+6
DI
n+7
DI
b
DI
b+1
DI
b+2
DI
b+5
DI
b+6
DI
b+7
RL = 11
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK.
2. DI n (or b) = data-in from column n (or b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T3 and T8.
5. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. Enabling CAL mode does not impact ODT control timings. The same timing relationship
relative to the command/address bus as when CAL is disabled should be maintained.
217
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
WRITE Operation
Write Timing Definitions
The write timings shown in the following figures are applicable in normal operation
mode, that is, when the DLL is enabled and locked.
Write Timing – Clock-to-Data Strobe Relationship
The clock-to-data strobe relationship is shown below and is applicable in normal operation mode, that is, when the DLL is enabled and locked.
Rising data strobe edge parameters:
• tDQSS (MIN) to tDQSS (MAX) describes the allowed range for a rising data strobe edge
relative to CK.
• tDQSS is the actual position of a rising strobe edge relative to CK.
• tDQSH describes the data strobe high pulse width.
• tWPST strobe going to HIGH, nondrive level (shown in the postamble section of the
graphic below).
Falling data strobe edge parameters:
• tDQSL describes the data strobe low pulse width.
• tWPRE strobe going to LOW, initial drive level (shown in the preamble section of the
graphic below).
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 161: Write Timing Definition
CK_c
CK_t
Command3
T0
T1
T2
T7
T8
T9
T10
WRITE
DES
DES
DES
DES
DES
DES
T11
T12
T13
T14
DES
DES
DES
DES
WL = AL + CWL
Address4
Bank,
Col n
tDQSS tDSH
tDQSS
tDSH
tDSH
tDSH
tWPSTaa
tWPRE(1nCK)
(MIN)
DQS_t, DQS_c
tDQSL
tDQSH
tDQSH
tDQSL
tDQSH
tDQSH
tDQSL
tDQSH
tDQSL
tDSS
DQ2
tDSS
DIN
n
tDSS
DIN
n+ 2
tDSS
DIN
n+ 4
DIN
n+ 3
tDSH
tDQSS
tDQSL
(MIN)
DIN
n+ 6
tDSH
DIN
n+ 7
tDSH
tDSH
tWPST
tWPRE(1nCK)
(nominal)
(MIN)
tDSS
(MIN)
DQS_t, DQS_c
tDQSL
tDQSH
tDQSH
tDQSL
tDQSH
tDQSL
tDQSH
tDQSL
tDQSH
tDQSL
(MIN)
tDSS
DQ2
tDSS
DIN
n
tDSS
DIN
n+ 2
DIN
n+ 3
tDSS
DIN
n+ 4
(MIN)
tDSS
DIN
n+ 6
DIN
n+ 7
tDQSS
tDSH
tDQSS
tDSH
tDSH
tDSH
tWPRE(1nCK)
(MAX)
tWPST
(MIN)
tDQSL
(MIN)
DQS_t, DQS_c
tDQSL
tDQSH
tDQSH
tDQSL
tDQSH
tDQSL
tDQSH
tDQSL
tDQSH
(MIN)
tDSS
tDSS
DIN
n
DQ2
tDSS
DIN
n+ 2
DIN
n+ 3
tDSS
DIN
n+ 4
tDSS
DIN
n+ 6
DIN
n+ 7
DM_n
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL8, WL = 9 (AL = 0, CWL = 9).
2. DINn = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0.
5. tDQSS must be met at each rising clock edge.
219
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
tWPRE
Calculation
Figure 162: tWPRE Method for Calculating Transitions and Endpoints
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09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
W :35(HQGV W 9
1. Vsw1 = (0.1) × VIH,diff,DQS.
2. Vsw2 = (0.9) × VIH,diff,DQS.
220
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
tWPST
Calculation
Figure 163: tWPST Method for Calculating Transitions and Endpoints
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9,/',))3HDN
W :367HQGV W Notes:
1. Vsw1 =(0.9) × VIL,diff,DQS.
2. Vsw2 = (0.1) × VIL,diff,DQS.
Write Timing – Data Strobe-to-Data Relationship
The DQ input receiver uses a compliance mask (Rx) for voltage and timing as shown in
the figure below. The receiver mask (Rx mask) defines the area where the input signal
must not encroach in order for the DRAM input receiver to be able to successfully capture a valid input signal. The Rx mask is not the valid data-eye. TdiVW and V diVW define
the absolute maximum Rx mask.
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
221
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 164: Rx Compliance Mask
VDIVW
Rx Mask
VCENTDQ,midpoint
TdiVW
VCENTDQ,midpoint is defined as the midpoint between the largest V REFDQ voltage level and
the smallest V REFDQ voltage level across all DQ pins for a given DRAM. Each DQ pin's
VREFDQ is defined by the center (widest opening) of the cumulative data input eye as depicted in the following figure. This means a DRAM's level variation is accounted for
within the DRAM Rx mask. The DRAM V REFDQ level will be set by the system to account
for RON and ODT settings.
Figure 165: VCENT_DQ VREFDQ Voltage Variation
DQx
DQy
(smallest VREFDQ Level)
DQz
(largest VREFDQ Level)
VCENTDQz
VCENTDQx
VCENTDQ,midpoint
VCENTDQy
VREF variation
(component)
The following figure shows the Rx mask requirements both from a midpoint-to-midpoint reference (left side) and from an edge-to-edge reference. The intent is not to add
any new requirement or specification between the two but rather how to convert the
relationship between the two methodologies. The minimum data-eye shown in the
composite view is not actually obtainable due to the minimum pulse width requirement.
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 166: Rx Mask DQ-to-DQS Timings
DQS, DQs Data-In at DRAM Ball
DQS, DQs Data-In at DRAM Ball
Rx Mask
Rx Mask – Alternative View
DQS_c
DQS_c
DQS_t
DQS_t
VdiVW
DRAMa
DQx–z
Rx Mask
DRAMa
DQx–z
VdiVW
0.5 × TdiVW 0.5 × TdiVW
0.5 × TdiVW 0.5 × TdiVW
Rx Mask
TdiVW
TdiVW
tDQS2DQ
+0.5 × TdiVW
DRAMb
DQy
Rx Mask
VdiVW
Rx Mask
TdiVW
tDQ2DQ
VdiVW
DRAMb
DQz
tDQ2DQ
Rx Mask
DRAMb
DQz
Rx Mask
VdiVW
DRAMb
DQy
VdiVW
tDQS2DQ
TdiVW
tDQ2DQ
tDQ2DQ
Rx Mask
TdiVW
tDQ2DQ
VdiVW
DRAMc
DQy
Rx Mask
DRAMc
DQz
DRAMc
DQy
Rx Mask
TdiVW
VdiVW
Rx Mask
VdiVW
DRAMc
DQz
+0.5 × TdiVW
VdiVW
tDQS2DQ
tDQS2DQ
tDQ2DQ
Notes:
1. DQx represents an optimally centered mask.
DQy represents earliest valid mask.
DQz represents latest valid mask.
2. DRAMa represents a DRAM without any DQS/DQ skews.
DRAMb represents a DRAM with early skews (negative tDQS2DQ).
DRAMc represents a DRAM with delayed skews (positive tDQS2DQ).
3. This figure shows the skew allowed between DRAM-to-DRAM and between DQ-to-DQ
for a DRAM. Signals assume data is center-aligned at DRAM latch.
TdiPW is not shown; composite data-eyes shown would violate TdiPW.
VCENTDQ,midpoint is not shown but is assumed to be midpoint of VdiVW.
The previous figure shows the basic Rx mask requirements. Converting the Rx mask requirements to a classical DQ-to-DQS relationship is shown in the following figure. It
should become apparent that DRAM write training is required to take full advantage of
the Rx mask.
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 167: Rx Mask DQ-to-DQS DRAM-Based Timings
DQS, DQs Data-In at DRAM Ball
DQS, DQs Data-In at DRAM Ball
Rx Mask vs. Composite Data-Eye
Rx Mask vs. UI Data-Eye
DQS_c
DQS_c
DQS_t
tDSx
TdiPW
Rx Mask
VdiVW
DRAMa
DQx , y, z
TdiVW
DRAMa
DQx–z
TdiPW
tDHx
Rx Mask
VdiVW
DQS_t
TdiVW
TdiPW
tDSy
tDHy
DRAMb
DQz
Rx Mask
TdiVW
tDQ2DQ
Rx Mask
tDQ2DQ
TdiVW
VdiVW
DRAMb
DQy
VdiVW
*Skew
TdiPW
tDSz
tDHz
DRAMc
DQz
tDQ2DQ
Rx Mask
Rx Mask
TdiVW
TdiVW
tDQ2DQ
VdiVW
DRAMc
DQy
VdiVW
*Skew
TdiPW
Notes:
1. DQx represents an optimally centered mask.
DQy represents earliest valid mask.
DQz represents latest valid mask.
2. *Skew = tDQS2DQ + 0.5 × TdiVW
DRAMa represents a DRAM without any DQS/DQ skews.
DRAMb represents a DRAM with the earliest skews (negative tDQS2DQ, tDQSy > *Skew).
DRAMc represents a DRAM with the latest skews (positive tDQS2DQ, tDQHz > *Skew).
t
3. DS/tDH are traditional data-eye setup/hold edges at DC levels.
tDS and tDH are not specified; tDH and tDS may be any value provided the pulse width
and Rx mask limits are not violated.
tDH (MIN) > TdiVW + tDS (MIN) + tDQ2DQ.
The DDR4 SDRAM's input receivers are expected to capture the input data with an Rx
mask of TdiVW provided the minimum pulse width is satisfied. The DRAM controller
will have to train the data input buffer to utilize the Rx mask specifications to this maxi-
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
mum benefit. If the DRAM controller does not train the data input buffers, then the
worst case limits have to be used for the Rx mask (TdiVW + 2 × tDQS2DQ), which will
generally be the classical minimum ( tDS and tDH) and is required as well.
Figure 168: Example of Data Input Requirements Without Training
TdiVW + 2 × tDQS2DQ
VdiVW
VIH(DC)
0.5 × VdiVW
Rx Mask
VCENTDQ,midpoint
0.5 × VdiVW
VIL(DC)
tDS
tDH
0.5 × TdiVW + tDQS2DQ 0.5 × TdiVW + tDQS2DQ
DQS_c
DQS_t
WRITE Burst Operation
The following write timing diagrams are intended to help understand each write parameter's meaning and are only examples. Each parameter will be defined in detail separately. In these write timing diagrams, CK and DQS are shown aligned, and DQS and
DQ are shown center-aligned for the purpose of illustration.
DDR4 WRITE command supports bursts of BL8 (fixed), BC4 (fixed), and BL8/BC4 onthe-fly (OTF); OTF uses address A12 to control OTF when OTF is enabled:
• A12 = 0, BC4 (BC4 = burst chop)
• A12 = 1, BL8
WRITE commands can issue precharge automatically with a WRITE with auto precharge (WRA) command, which is enabled by A10 HIGH.
• WRITE command with A10 = 0 (WR) performs standard write, bank remains active after WRITE burst
• WRITE command with A10 = 1 (WRA) performs write with auto precharge, bank goes
into precharge after WRITE burst
The DATA MASK (DM) function is supported for the x8 and x16 configurations only (the
DM function is not supported on x4 devices). The DM function shares a common pin
with the DBI_n and TDQS functions. The DM function only applies to WRITE operations and cannot be enabled at the same time the DBI function is enabled.
• If DM_n is sampled LOW on a given byte lane, the DRAM masks the write data received on the DQ inputs.
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
• If DM_n is sampled HIGH on a given byte lane, the DRAM does not mask the data and
writes this data into the DRAM core.
• If CRC write is enabled, then DM enabled (via MRS) will be selected between write
CRC nonpersistent mode (DM disabled) and write CRC persistent mode (DM enabled).
Figure 169: WRITE Burst Operation, WL = 9 (AL = 0, CWL = 9, BL8)
T0
T1
T2
T7
T8
T9
WRITE
DES
DES
DES
DES
DES
T10
T11
T12
T13
T14
T15
T16
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
Bank Group
Address
BGa
Address
Bank
Col n
DES
tWPST
tWPRE
DQS_t,
DQS_c
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
WL = AL + CWL = 9
Time Break
Notes:
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL8, WL = 0, AL = 0, CWL = 9, Preamble = 1tCK.
2. DI n = Data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0.
5. CA parity = Disable, CS to CA atency = Disable, Read DBI = Disable.
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 170: WRITE Burst Operation, WL = 19 (AL = 10, CWL = 9, BL8)
T0
T1
T2
T9
T10
T11
T17
T18
T19
T20
T21
T22
T23
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
Bank Group
Address
BGa
Bank
Col n
Address
tWPST
tWPRE
DQS_t,
DQS_c
DI
n
DQ
AL = 10
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
CWL = 9
WL = AL + CWL = 19
Time Break
Notes:
Transitioning Data
Don’t Care
1. BL8, WL = 19, AL = 10 (CL - 1), CWL = 9, Preamble = 1tCK.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
WRITE Operation Followed by Another WRITE Operation
Figure 171: Consecutive WRITE (BL8) with 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
tWR
tCCD_S
Bank Group
Address
Address
4 Clocks
=4
BGa
BGb
Bank
Col n
Bank
Col b
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
WL = AL + CWL = 9
Time Break
Notes:
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Transitioning Data
Don’t Care
1. BL8, AL = 0, CWL = 9, Preamble = 1tCK.
2. DI n (or b) = data-in from column n (or column b).
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.
Figure 172: Consecutive WRITE (BL8) with 2tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
tWR
tCCD_S
Bank Group
Address
Address
4 Clocks
=4
BGa
BGb
Bank
Col n
Bank
Col b
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 10
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
WL = AL + CWL = 10
Time Break
Notes:
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL8, AL = 0, CWL = 9 + 1 = 10 (see Note 7), Preamble = 2tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.
7. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting supported in the applicable
tCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE preamble mode.
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 173: Nonconsecutive WRITE (BL8) with 1tCK Preamble in Same or Different Bank Group
T0
T1
T2
T3
T4
T5
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
WRITE
DES
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
tWR
tCCD_S/L
Bank Group
Address
Address
4 Clocks
=5
BGa
BGa
or BGb
Bank
Col n
Bank
Col b
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
WL = AL + CWL = 9
Time Break
Notes:
Don’t Care
Transitioning Data
1. BL8, AL = 0, CWL = 9, Preamble = 1tCK, tCCD_S/L = 5tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T5.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T18.
Figure 174: Nonconsecutive WRITE (BL8) with 2tCK Preamble in Same or Different Bank Group
T0
T1
T2
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
WRITE
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
tWR
tCCD_S/L
Bank Group
Address
Address
4 Clocks
=6
BGa
BGa
or BGb
Bank
Col n
Bank
Col b
tWPRE
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 10
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
WL = AL + CWL = 10
Time Break
Notes:
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL8, AL = 0, CWL = 9 + 1 = 10 (see Note 8), Preamble = 2tCK, tCCD_S/L = 6tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T6.
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. tCCD_S/L = 5 isn’t allowed in 2tCK preamble mode.
7. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T20.
8. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting supported in the applicable
tCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE preamble mode.
Figure 175: WRITE (BC4) OTF to WRITE (BC4) OTF with 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
tWR
tCCD_S
Bank Group
Address
Address
4 Clocks
=4
BGa
BGb
Bank
Col n
Bank
Col b
tWPST
tWPRE
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
b
DI
b+1
DI
b+2
DI
b+3
WL = AL + CWL = 9
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BC4, AL = 0, CWL = 9, Preamble = 1tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and
T4.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 176: WRITE (BC4) OTF to WRITE (BC4) OTF with 2tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T19
CK_c
CK_t
Command
DES
tWR
tCCD_S
Bank Group
Address
Address
4 Clocks
=4
BGa
BGb
Bank
Col n
Bank
Col b
tWPRE
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 10
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
b
DI
b+1
DI
b+2
DI
b+3
WL = AL + CWL = 10
Time Break
Notes:
Transitioning Data
Don’t Care
1. BC4, AL = 0, CWL = 9 + 1 = 10 (see Note 7), Preamble = 2tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and
T4.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T18.
7. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting supported in the applicable
tCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE preamble mode.
Figure 177: WRITE (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
tWR
tCCD_S
Bank Group
Address
Address
2 Clocks
=4
BGa
BGb
Bank
Col n
Bank
Col b
tWPST
tWPRE
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
b
DI
b+1
DI
b+2
DI
b+3
WL = AL + CWL = 9
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BC4, AL = 0, CWL = 9, Preamble = 1tCK.
2. DI n (or b) = data-in from column n (or column b).
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 (fixed) setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T15.
Figure 178: WRITE (BL8) to WRITE (BC4) OTF with 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T19
CK_c
CK_t
Command
DES
t
4 Clocks
t
CCD_S = 4
Bank Group
Address
Address
BGa
BGb
Bank
Col n
Bank
Col b
t
t
WPRE
WR
t
WTR
WPST
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
DI
b
DI
b+1
DI
b+2
DI
b+3
WL = AL + CWL = 9
Time Break
Notes:
Transitioning Data
Don’t Care
1. BL = 8/BC = 4, AL = 0, CL = 9, Preamble = 1tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE command at T0.
BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
232
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 179: WRITE (BC4) OTF to WRITE (BL8) with 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T19
CK_c
CK_t
Command
DES
tWR
tCCD_S
Bank Group
Address
Address
4 Clocks
=4
BGa
BGb
Bank
Col n
Bank
Col b
tWPST
tWPRE
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
WL = AL + CWL = 9
Time Break
Don’t Care
Transitioning Data
1. BL = 8/BC = 4, AL = 0, CL = 9, Preamble = 1tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0.
Notes:
BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE command at T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.
WRITE Operation Followed by READ Operation
Figure 180: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Different Bank Group
T0
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T24
T25
T26
T27
T28
T29
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
READ
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
4 Clocks
Bank Group
Address
Address
tWTR_S
BGa
=2
BGb
Bank
Col n
Bank
Col b
tWPST
tWPRE
tRPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
RL = AL + CL = 11
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
DI
b
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
DI
b+1
DI
b+2
DI
b+3
Transitioning Data
DI
b+4
DI
b+5
DI
b+6
Don’t Care
1. BL = 8, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble =
1tCK.
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
233
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0 and READ command at T15.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (tWTR_S) is referenced from the first rising clock edge after
the last write data shown at T13.
Figure 181: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Same Bank Group
T0
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T26
T27
T28
T29
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
READ
DES
DES
DES
DES
DES
CK_c
CK_t
Command
4 Clocks
Bank Group
Address
Address
tWTR_L
BGa
=4
BGa
Bank
Col n
Bank
Col b
tWPST
tWPRE
tRPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
RL = AL + CL = 11
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
DI
b
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
DI
b+1
DI
b+2
Don’t Care
1. BL = 8, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble =
1tCK.
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0 and READ command at T17.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (tWTR_L) is referenced from the first rising clock edge after
the last write data shown at T13.
234
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 182: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Different Bank Group
T0
T1
T7
T8
T9
T10
WRITE
DES
DES
DES
DES
DES
T11
T12
T13
DES
DES
DES
T14
T15
T16
T24
T25
T26
T27
T28
T29
DES
READ
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
4 Clocks
Bank Group
Address
Address
tWTR_S
=2
BGa
BGb
Bank
Col n
Bank
Col b
tWPST
tWPRE
tRPST
tRPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
RL = AL + CL = 11
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
b
Time Break
DI
b+1
DI
b+2
DI
b+3
Transitioning Data
Don’t Care
1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble =
1tCK.
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0 and
READ command at T15.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (tWTR_S) is referenced from the first rising clock edge after
the last write data shown at T13.
Notes:
Figure 183: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Same Bank Group
T0
T1
T7
T8
T9
T10
WRITE
DES
DES
DES
DES
DES
T11
T12
T13
T14
DES
DES
DES
DES
T15
T16
T17
T18
T26
T27
T28
T29
DES
DES
READ
DES
DES
DES
DES
DES
CK_c
CK_t
Command
4 Clocks
Bank Group
Address
Address
tWTR_L
BGa
=4
BGa
Bank
Col n
Bank
Col b
tWPST
tWPRE
tRPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
RL = AL + CL = 11
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
b
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
DI
b+1
DI
b+2
Don’t Care
1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble =
1tCK.
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0 and
READ command at T17.
235
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (tWTR_L) is referenced from the first rising clock edge after
the last write data shown at T13.
Figure 184: WRITE (BC4) Fixed to READ (BC4) Fixed with 1 tCK Preamble in Different Bank Group
T0
T1
T7
T8
T9
WRITE
DES
DES
DES
DES
T10
T11
DES
DES
T12
T13
T14
T22
T23
T24
T25
T26
T27
T28
T29
DES
DES
DES
DES
DES
READ
DES
DES
DES
DES
DES
CK_c
CK_t
Command
2 Clocks
Bank Group
Address
Address
tWTR_S
=2
BGa
BGb
Bank
Col n
Bank
Col b
tWPST
tWPRE
tRPST
tRPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
RL = AL + CL = 11
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
b
DI
b+1
DI
b+2
DI
b+3
Time Break
Transitioning Data
Don’t Care
1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1 tCK, WRITE preamble =
1tCK.
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (tWTR_S) is referenced from the first rising clock edge after
the last write data shown at T11.
Notes:
Figure 185: WRITE (BC4) Fixed to READ (BC4) Fixed with 1tCK Preamble in Same Bank Group
T0
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T24
T25
T26
T27
T28
T29
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
READ
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
2 Clocks
Bank Group
Address
Address
tWTR_L
=4
BGa
BGa
Bank
Col n
Bank
Col b
tWPST
tWPRE
tRPST
tRPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
RL = AL + CL = 11
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
b
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
DI
b+1
DI
b+2
DI
b+3
Transitioning Data
Don’t Care
1. BC = 4, WL = 9 (CWL = 9, AL = 0), C L = 11, READ preamble = 1tCK, WRITE preamble =
1tCK.
2. DI b = data-in from column b.
236
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (tWTR_L) is referenced from the first rising clock edge after
the last write data shown at T11.
WRITE Operation Followed by PRECHARGE Operation
The minimum external WRITE command to PRECHARGE command spacing is equal to
WL (AL + CWL) plus either 4tCK (BL8/BC4-OTF) or 2tCK (BC4-fixed) plus tWR. The minimum ACT to PRE timing, tRAS, must be satisfied as well.
Figure 186: WRITE (BL8/BC4-OTF) to PRECHARGE with 1tCK Preamble
T0
T1
T2
WRITE
DES
DES
T3
T4
T7
T8
T9
T10
DES
DES
DES
DES
DES
DES
T11
T12
T13
T14
T22
DES
DES
DES
DES
DES
T23
T24
T25
DES
DES
PRE
T26
CK_c
CK_t
Command
WL = AL + CWL = 9
tWR
4 Clocks
BGa, Bank b
Col n
DES
tRP
= 12
BGa, Bank b
(or all)
Address
BC4 (OTF) Opertaion
DQS_t,
DQS_c
DQ
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n
DI
n+1
DI
n+2
DI
n+3
BL8 Opertaion
DQS_t,
DQS_c
DQ
DI
n+4
DI
n+5
DI
n+6
DI
n+7
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL = 8 with BC4-OTF, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0. BL8
setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command
at T0.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable.
6. The write recovery time (tWR) is referenced from the first rising clock edge after the last
write data shown at T13. tWR specifies the last burst WRITE cycle until the PRECHARGE
command can be issued to the same bank.
237
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 187: WRITE (BC4-Fixed) to PRECHARGE with 1tCK Preamble
T0
T1
T2
WRITE
DES
DES
T3
T4
T7
T8
T9
DES
DES
DES
DES
DES
T10
T11
T12
T13
DES
DES
DES
DES
T14
T22
T23
DES
DES
PRE
T24
T25
T26
DES
DES
DES
CK_c
CK_t
Command
WL = AL + CWL = 9
tWR
2 Clocks
tRP
= 12
BGa, Bank b
Col n
BGa, Bank b
(or all)
Address
BC4 (Fixed) Opertaion
DQS_t,
DQS_c
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
Time Break
Notes:
Transitioning Data
Don’t Care
1. BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable.
6. The write recovery time (tWR) is referenced from the first rising clock edge after the last
write data shown at T11. tWR specifies the last burst WRITE cycle until the PRECHARGE
command can be issued to the same bank.
Figure 188: WRITE (BL8/BC4-OTF) to Auto PRECHARGE with 1tCK Preamble
T0
T1
T2
WRITE
DES
DES
T3
T4
T7
T8
T9
T10
DES
DES
DES
DES
DES
DES
T11
T12
T13
T14
T22
DES
DES
DES
DES
DES
T23
T24
T25
DES
DES
DES
T26
CK_c
CK_t
Command
WL = AL + CWL = 9
tWR
4 Clocks
DES
tRP
= 12
BGa, Bank b
Col n
Address
BC4 (OTF) Opertaion
DQS_t,
DQS_c
DQ
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n
DI
n+1
DI
n+2
DI
n+3
BL8 Opertaion
DQS_t,
DQS_c
DQ
DI
n+4
DI
n+5
DI
n+6
DI
n+7
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL = 8 with BC4-OTF, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0.
BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable.
238
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
6. The write recovery time (tWR) is referenced from the first rising clock edge after the last
write data shown at T13. tWR specifies the last burst WRITE cycle until the PRECHARGE
command can be issued to the same bank.
Figure 189: WRITE (BC4-Fixed) to Auto PRECHARGE with 1tCK Preamble
T0
T1
T2
WRITE
DES
DES
T3
T4
T7
T8
T9
DES
DES
DES
DES
DES
T10
T11
T12
T13
DES
DES
DES
DES
T14
T22
T23
T24
DES
DES
DES
DES
T25
T26
DES
DES
CK_c
CK_t
Command
WL = AL + CWL = 9
tWR
2 Clocks
tRP
= 12
BGa, Bank b
Col n
Address
BC4 (Fixed) Opertaion
DQS_t,
DQS_c
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable.
6. The write recovery time (tWR) is referenced from the first rising clock edge after the last
write data shown at T11. tWR specifies the last burst WRITE cycle until the PRECHARGE
command can be issued to the same bank.
239
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
WRITE Operation with WRITE DBI Enabled
Figure 190: WRITE (BL8/BC4-OTF) with 1tCK Preamble and DBI
T0
T1
T2
WRITE
DES
DES
T3
T4
T5
T6
T7
T8
T9
T10
DES
DES
DES
DES
DES
DES
DES
DES
T11
T12
T13
T14
DES
DES
DES
DES
T15
T16
T17
DES
DES
DES
CK_c
CK_t
Command
WL = AL + CWL = 9
tWR
4 Clocks
tWTR
Address
BGa
Address
Bank,
Col n
BC4 (OTF) Opertaion
DQS_t,
DQS_c
DQ
DI
n
DI
n+1
DI
n+2
DI
n+3
DBI_n
DI
n
DI
n+1
DI
n+2
DI
n+3
DQ
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
DBI_n
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
BL8 Opertaion
DQS_t,
DQS_c
Transitioning Data
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Don’t Care
1. BL = 8 with BC4-OTF, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0.
BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disabled.
6. The write recovery time (tWR_DBI) is referenced from the first rising clock edge after the
last write data shown at T13.
240
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 191: WRITE (BC4-Fixed) with 1tCK Preamble and DBI
T0
T1
T2
WRITE
DES
DES
T3
T4
T5
T6
T7
T8
T9
DES
DES
DES
DES
DES
DES
DES
T10
T11
T12
T13
T14
DES
DES
DES
DES
DES
T15
T16
T17
DES
DES
DES
CK_c
CK_t
Command
WL = AL + CWL = 9
tWR
2 Clocks
tWTR
Address
BGa
Address
Bank,
Col n
BC4 (Fixed) Opertaion
DQS_t,
DQS_c
DQ
DI
n
DI
n+1
DI
n+2
DI
n+3
DBI_n
DI
n
DI
n+1
DI
n+2
DI
n+3
Transitioning Data
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Don’t Care
1. BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disabled.
241
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
WRITE Operation with CA Parity Enabled
Figure 192: Consecutive Write (BL8) with 1tCK Preamble and CA Parity in Different Bank Group
T0
T1
T2
T3
T4
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
tWR
tCCD_S
Bank Group
Address
4 Clocks
=4
BGa
BGb
Address
Bank
Col n
Bank
Col b
Parity
Valid
Valid
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = PL + AL + CWL = 13
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
WL = PL + AL + CWL = 13
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL = 8, WL = 9 (CWL = 13, AL = 0 ), Preamble = 1tCK.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T4.
5. CA parity = Enable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T21.
242
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
WRITE Operation with Write CRC Enabled
Figure 193: Consecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Different Bank Group
T0
T1
T2
T3
T4
T5
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
WRITE
DES
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T19
CK_c
CK_t
Command
DES
tWR
tCCD_S/L
Bank Group
Address
Address
4 Clocks
=5
BGa
BGa or
BGb
Bank
Col n
Bank
Col b
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
CRC
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
CRC
DQ x4,
BC = 4 (OTF)
DI
n
DI
n+1
DI
n+2
DI
n+3
CRC
DQ x8/X16,
BC = 4 (OTF)
DI
n
DI
n+1
DI
n+2
DI
n+3
CRC
DQ x4,
BL = 8
CRC
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
CRC
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
CRC
DI
b
DI
b+1
DI
b+2
DI
b+3
CRC
DI
b
DI
b+1
DI
b+2
DI
b+3
CRC
CRC
WL = AL + CWL = 9
DQ x8/X16,
BL = 8
CRC
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
CRC
Don’t Care
1. BL8/BC4-OTF, AL = 0, CWL = 9, Preamble = 1tCK, tCDD_S/L = 5tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T5.
5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and
T5.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable.
7. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T18.
243
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 194: Consecutive WRITE (BC4-Fixed) with 1tCK Preamble and Write CRC in Same or Different
Bank Group
T0
T1
T2
T3
T4
T5
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
WRITE
DES
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T18
T19
DES
DES
CK_c
CK_t
Command
tWR
tCCD_S/L
Bank Group
Address
Address
2 Clocks
=5
BGa
BGa or
BGb
Bank
Col n
Bank
Col b
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DQ x4,
BC = 4 (Fixed)
DI
n
DI
n+1
DI
n+2
DI
n+3
CRC
DI
n
DI
n+1
DI
n+2
DI
n+3
CRC
CRC
DI
b
DI
b+1
DI
b+2
DI
b+3
CRC
DI
b
DI
b+1
DI
b+2
DI
b+3
CRC
CRC
WL = AL + CWL = 9
DQ x8/X16,
BC = 4 (Fixed)
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BC4-fixed, AL = 0, CWL = 9, Preamble = 1tCK, tCDD_S/L = 5tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10 during WRITE commands at T0 and T5.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,
DM = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T16.
244
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 195: Nonconsecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Different Bank Group
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
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Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
7UDQVLWLRQLQJ'DWD
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1. BL8/BC4-OTF, AL = 0, CWL = 9, Preamble = 1tCK, tCDD_S/L = 6tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T6.
5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and
T6.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,
DM = Disable.
7. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T19.
245
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 196: Nonconsecutive WRITE (BL8/BC4-OTF) with 2tCK Preamble and Write CRC in Same or Different Bank Group
T0
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
WRITE
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T22
CK_c
CK_t
Command
DES
tWR
tCCD_S/L
Bank Group
Address
Address
4 Clocks
=7
BGa
BGa or
BGb
Bank
Col n
Bank
Col b
tWPRE
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 10
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
CRC
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
CRC
DQ x4,
BC = 4 (OTF)
DI
n
DI
n+1
DI
n+2
DI
n+3
CRC
DQ x8/X16,
BC = 4 (OTF)
DI
n
DI
n+1
DI
n+2
DI
n+3
CRC
DQ x4,
BL = 8
CRC
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
CRC
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
CRC
DI
b
DI
b+1
DI
b+2
DI
b+3
CRC
DI
b
DI
b+1
DI
b+2
DI
b+3
CRC
CRC
WL = AL + CWL = 10
DQ x8/X16,
BL = 8
CRC
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
CRC
Don’t Care
1. BL8/BC4-OTF, AL = 0, CWL = 9 + 1 = 10 (see Note 9), Preamble = 2tCK, tCDD_S/L = 7tCK
(see Note 7).
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T7.
5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and
T7.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,
DM = Disable.
7. tCDD_S/L = 6tCK is not allowed in 2tCK preamble mode if minimum tCDD_S/L allowed in
1tCK preamble mode would have been 6 clocks.
8. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T21.
9. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting supported in the applicable
tCK range. That means CWL = 9 is not allowed when operating in 2tCK WRITE preamble
mode.
246
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4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 197: WRITE (BL8/BC4-OTF/Fixed) with 1tCK Preamble and Write CRC in Same or Different Bank
Group
T0
T1
T2
T6
T7
T8
T9
T10
T11
T12
T13
T14
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T15
T16
T17
T18
T19
T20
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
tWR_CRC_DM
4 Clocks
Bank Group
Address
Address
tWTR_S_CRC_DM/tWTR_L_CRC_DM
BGa
Bank
Col n
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DQ x4,
BL = 8
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
CRC
DQ x8/X16,
BL = 8
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
CRC
DM
n
DM
n+1
DM
n+2
DM
n+3
DM
n+4
DM
n+5
DM
n+6
DM
n+7
DQ x4,
BC = 4 (OTF/Fixed)
DI
n
DI
n+1
DI
n+2
DI
n+3
CRC
DQ x8/X16,
BC = 4 (OTF/Fixed)
DI
n
DI
n+1
DI
n+2
DI
n+3
CRC
DM
n
DM
n+1
DM
n+2
DM
n+3
DMx4/x8/x16
BL = 8
DM x4/x8/x16
BC = 4 (OTF / Fixed)
CRC
CRC
Time Break
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Transitioning Data
Don’t Care
1. BL8/BC4, AL = 0, CWL = 9, Preamble = 1tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0.
5. BC4 setting activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during
WRITE command at T0.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,
DM = Enable.
7. The write recovery time (tWR_CRC_DM) and write timing parameter (tWTR_S_CRC_DM/
tWTR_L_CRC_DM) are referenced from the first rising clock edge after the last write data shown at T13.
247
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4Gb: x4, x8, x16 DDR4 SDRAM
Write Timing Violations
Write Timing Violations
Motivation
Generally, if timing parameters are violated, a complete reset/initialization procedure
has to be initiated to make sure that the device works properly. However, for certain minor violations, it is desirable that the device is guaranteed not to "hang up" and that errors are limited to that specific operation. A minor violation does not include a major
timing violation (for example, when a DQS strobe misses in the tDQSCK window).
For the following, it will be assumed that there are no timing violations with regard to
the WRITE command itself (including ODT, and so on) and that it does satisfy all timing
requirements not mentioned below.
Data Setup and Hold Violations
If the data-to-strobe timing requirements (tDS, tDH) are violated, for any of the strobe
edges associated with a WRITE burst, then wrong data might be written to the memory
location addressed with this WRITE command.
In the example, the relevant strobe edges for WRITE Burst A are associated with the
clock edges: T5, T5.5, T6, T6.5, T7, T7.5, T8, and T8.5.
Subsequent reads from that location might result in unpredictable read data; however,
the device will work properly otherwise.
Strobe-to-Strobe and Strobe-to-Clock Violations
If the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock
timing requirements (tDSS, tDSH, tDQSS) are violated, for any of the strobe edges associated with a WRITE burst, then wrong data might be written to the memory location
addressed with the offending WRITE command. Subsequent reads from that location
might result in unpredictable read data; however, the device will work properly otherwise with the following constraints:
• Both write CRC and data burst OTF are disabled; timing specifications other than
tDQSH, tDQSL, tWPRE, tWPST, tDSS, tDSH, tDQSS are not violated.
• The offending write strobe (and preamble) arrive no earlier or later than six DQS transition edges from the WRITE latency position.
• A READ command following an offending WRITE command from any open bank is
allowed.
• One or more subsequent WR or a subsequent WRA (to same bank as offending WR)
may be issued tCCD_L later, but incorrect data could be written. Subsequent WR and
WRA can be either offending or non-offending writes. Reads from these writes may
provide incorrect data.
• One or more subsequent WR or a subsequent WRA (to a different bank group) may be
issued tCCD_S later, but incorrect data could be written. Subsequent WR and WRA
can be either offending or non-offending writes. Reads from these writes may provide
incorrect data.
• After one or more precharge commands (PRE or PREA) are issued to the device after
an offending WRITE command and all banks are in precharged state (idle state), a
subsequent, non-offending WR or WRA to any open bank will be able to write correct
data.
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
248
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
ZQ CALIBRATION Commands
ZQ CALIBRATION Commands
A ZQ CALIBRATION command is used to calibrate DRAM RON and ODT values. The device needs a longer time to calibrate the output driver and on-die termination circuits
at initialization and a relatively smaller time to perform periodic calibrations.
The ZQCL command is used to perform the initial calibration during the power-up initialization sequence. This command may be issued at any time by the controller depending on the system environment. The ZQCL command triggers the calibration engine inside the DRAM and, after calibration is achieved, the calibrated values are transferred from the calibration engine to DRAM I/O, which is reflected as an updated output driver and ODT values.
The first ZQCL command issued after reset is allowed a timing period of tZQinit to perform the full calibration and the transfer of values. All other ZQCL commands except
the first ZQCL command issued after reset are allowed a timing period of tZQoper.
The ZQCS command is used to perform periodic calibrations to account for voltage and
temperature variations. A shorter timing window is provided to perform the calibration
and transfer of values as defined by timing parameter tZQCS. One ZQCS command can
effectively correct a minimum of 0.5 % (ZQ correction) of RON and RTT impedance error
within 64 nCK for all speed bins assuming the maximum sensitivities specified in the
Output Driver and ODT Voltage and Temperature Sensitivity tables. The appropriate interval between ZQCS commands can be determined from these tables and other application-specific parameters. One method for calculating the interval between ZQCS
commands, given the temperature (Tdrift_rate) and voltage (Vdrift_rate) drift rates that the
device is subjected to in the application, is illustrated. The interval could be defined by
the following formula:
ZQcorrection
(Tsense x Tdrift_rate
) + (Vsense x Tdrift_rate
)
Where T sense = MAX(dRTTdT, dRONdTM) and V sense = MAX(dRTTdV, dRONdVM) define
the temperature and voltage sensitivities.
For example, if T sens = 1.5%/°C, V sens = 0.15%/mV, T driftrate = 1 °C/sec and V driftrate = 15
mV /sec, then the interval between ZQCS commands is calculated as:
0.5
= 0.133 §128ms
(1.5 × 1) + (0.15 × 15)
No other activities should be performed on the DRAM channel by the controller for the
duration of tZQinit, tZQoper, or tZQCS. The quiet time on the DRAM channel allows accurate calibration of output driver and on-die termination values. After DRAM calibration is achieved, the device should disable the ZQ current consumption path to reduce
power.
All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued
by the controller.
ZQ CALIBRATION commands can also be issued in parallel to DLL lock time when
coming out of self refresh. Upon self refresh exit, the device will not perform an I/O cali09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
249
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
ZQ CALIBRATION Commands
bration without an explicit ZQ CALIBRATION command. The earliest possible time for a
ZQ CALIBRATION command (short or long) after self refresh exit is tXS, tXS_Abort, or t
XS_FAST depending on operation mode.
In systems that share the ZQ resistor between devices, the controller must not allow any
overlap of tZQoper, tZQinit, or tZQCS between the devices.
Figure 198: ZQ Calibration Timing
T0
T1
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
Tc0
Tc1
Tc2
ZQCL
DES
DES
DES
Valid
Valid
ZQCS
DES
DES
DES
Valid
Address
Valid
Valid
Valid
A10
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CK_c
CK_t
Command
CKE
Note 1
Note 2
ODT
DQ Bus
High-Z or RTT(Park)
Activities
High-Z or RTT(Park)
Activities
Note 3
tZQinit_tZQoper
tZQCS
Time Break
Notes:
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Don’t Care
1. CKE must be continuously registered HIGH during the calibration procedure.
2. During ZQ Calibration, the ODT signal must be held LOW and DRAM continues to provide RTT_PARK.
3. All devices connected to the DQ bus should be High-Z during the calibration procedure.
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4Gb: x4, x8, x16 DDR4 SDRAM
On-Die Termination
On-Die Termination
The on-die termination (ODT) feature enables the device to change termination resistance for each DQ, DQS, and DM_n/DBI_n signal for x4 and x8 configurations (and
TDQS for the x8 configuration when enabled via A11 = 1 in MR1) via the ODT control
pin, WRITE command, or default parking value with MR setting. For the x16 configuration, ODT is applied to each DQU, DQL, DQSU, DQSL, DMU_n/DBIU_n, and DML_n/
DBIL_n signal. The ODT feature is designed to improve the signal integrity of the memory channel by allowing the DRAM controller to independently change termination resistance for any or all DRAM devices. If DBI read mode is enabled while the DRAM is in
standby, either DM mode or DBI write mode must also be enabled if RTT(NOM) or
RTT(Park) is desired. More details about ODT control modes and ODT timing modes can
be found further along in this document.
The ODT feature is turned off and not supported in self refresh mode.
Figure 199: Functional Representation of ODT
ODT
To other
circuitry
such as
RCV,
...
VDDQ
RTT
Switch
DQ, DQS, DM, TDQS
The switch is enabled by the internal ODT control logic, which uses the external ODT
pin and other control information. The value of R TT is determined by the settings of
mode register bits (see Mode Register). The ODT pin will be ignored if the mode register
MR1 is programmed to disable RTT(NOM) [MR1[10,9,8] = 0,0,0] and in self refresh mode.
ODT Mode Register and ODT State Table
The ODT mode of the DDR4 device has four states: data termination disable, RTT(NOM),
RTT(WR), and RTT(Park). The ODT mode is enabled if any of MR1[10:8] (R TT(NOM)),
MR2[11:9] (RTT(WR)), or MR5[8:6] (RTT(Park)) are non-zero. When enabled, the value of
RTT is determined by the settings of these bits.
RTT control of each RTT condition is possible with a WR or RD command and ODT pin.
• RTT(WR): The DRAM (rank) that is being written to provide termination regardless of
ODT pin status (either HIGH or LOW).
• RTT(NOM): DRAM turns ON RTT(NOM) if it sees ODT asserted HIGH (except when ODT
is disabled by MR1).
• RTT(Park): Default parked value set via MR5 to be enabled and RTT(NOM) is not turned
on.
• The Termination State Table that follows shows various interactions.
The RTT values have the following priority:
•
•
•
•
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Data termination disable
RTT(WR)
RTT(NOM)
RTT(Park)
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ODT Mode Register and ODT State Table
Table 71: Termination State Table
Case
RTT(Park)
RTT(NOM)1
RTT(WR)2
ODT Pin
ODT READS3
ODT Standby
ODT WRITES
A4
Disabled
Disabled
Disabled
Don't Care
Off (High-Z)
Off (High-Z)
Off (High-Z)
Enabled
Don't Care
Off (High-Z)
Off (High-Z)
RTT(WR)
RTT(Park)
RTT(Park)
B5
Enabled
Disabled
Disabled
Don't Care
Off (High-Z)
Enabled
Don't Care
Off (High-Z)
RTT(Park)
RTT(WR)
C6
Disabled
Enabled
Disabled
Low
Off (High-Z)
Off (High-Z)
Off (High-Z)
High
Off (High-Z)
RTT(NOM)
RTT(NOM)
Low
Off (High-Z)
Off (High-Z)
RTT(WR)
High
Off (High-Z)
RTT(NOM)
RTT(WR)
Low
Off (High-Z)
RTT(Park)
RTT(Park)
High
Off (High-Z)
RTT(NOM)
RTT(NOM)
Low
Off (High-Z)
RTT(Park)
RTT(WR)
High
Off (High-Z)
RTT(NOM)
RTT(WR)
Enabled
D6
Enabled
Enabled
Disabled
Enabled
Notes:
1. If RTT(NOM) MR is disabled, power to the ODT receiver will be turned off to save power.
2. If RTT(WR) is enabled, RTT(WR) will be activated by a WRITE command for a defined period
time independent of the ODT pin and MR setting of RTT(Park)/RTT(NOM). This is described in
the Dynamic ODT section.
3. When a READ command is executed, the DRAM termination state will be High-Z for a
defined period independent of the ODT pin and MR setting of RTT(Park)/RTT(NOM). This is
described in the ODT During Read section.
4. Case A is generally best for single-rank memories.
5. Case B is generally best for dual-rank, single-slotted memories.
6. Case C and Case D are generally best for multi-slotted memories.
ODT Read Disable State Table
Upon receiving a READ command, the DRAM driving data disables ODT after RL - (2 or
3) clock cycles, where 2 = 1tCK preamble mode and 3 = 2tCK preamble mode. ODT stays
off for a duration of BL/2 + (2 or 3) + (0 or 1) clock cycles, where 2 = 1tCK preamble
mode, 3 = 2tCK preamble mode, 0 = CRC disabled, and 1 = CRC enabled.
Table 72: Read Termination Disable Window
Preamble
CRC
Start ODT Disable After
Read
Duration of ODT Disable
1tCK
Disabled
RL - 2
BL/2 + 2
Enabled
RL - 2
BL/2 + 3
2tCK
Disabled
RL - 3
BL/2 + 3
Enabled
RL - 3
BL/2 + 4
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Synchronous ODT Mode
Synchronous ODT Mode
Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based
on the power-down definition, these modes include the following:
•
•
•
•
•
Any bank active with CKE HIGH
Refresh with CKE HIGH
Idle mode with CKE HIGH
Active power-down mode (regardless of MR1 bit A10)
Precharge power-down mode
In synchronous ODT mode, RTT(NOM) will be turned on DODTLon clock cycles after
ODT is sampled HIGH by a rising clock edge and turned off DODTLoff clock cycles after
ODT is registered LOW by a rising clock edge. The ODT latency is determined by the
programmed values for: CAS WRITE latency (CWL), additive latency (AL), and parity latency (PL), as well as the programmed state of the preamble.
ODT Latency and Posted ODT
The ODT latencies for synchronous ODT mode are summarized in the table below. For
details, refer to the latency definitions.
Table 73: ODT Latency at DDR4-1600/-1866/-2133/-2400/-2666/-3200
Applicable when write CRC is disabled
Symbol
Parameter
1tCK Preamble
2tCK Preamble
Unit
tCK
DODTLon
Direct ODT turn-on latency
CWL + AL + PL - 2
CWL + AL + PL - 3
DODTLoff
Direct ODT turn-off latency
CWL + AL + PL - 2
CWL + AL + PL - 3
RODTLoff
READ command to internal ODT turn-off
latency
CL + AL + PL - 2
CL + AL + PL - 3
RODTLon4
READ command to RTT(Park) turn-on latency in BC4-fixed
RODTLoff + 4
RODTLoff + 5
RODTLon8
READ command to RTT(Park) turn-on latency in BL8/BC4-OTF
RODTLoff + 6
RODTLoff + 7
ODTH4
ODT Assertion time, BC4 mode
4
5
ODTH8
ODT Assertion time, BL8 mode
6
7
Timing Parameters
In synchronous ODT mode, the following parameters apply:
• DODTLon, DODTLoff, RODTLoff, RODTLon4, RODTLon8, and tADC (MIN)/(MAX).
• tADC (MIN) and tADC (MAX) are minimum and maximum RTT change timing skew
between different termination values. These timing parameters apply to both the synchronous ODT mode and the data termination disable mode.
When ODT is asserted, it must remain HIGH until minimum ODTH4 (BC = 4) or
ODTH8 (BL = 8) is satisfied. If write CRC mode or 2tCK preamble mode is enabled,
ODTH should be adjusted to account for it. ODTHx is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of a WRITE command.
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Synchronous ODT Mode
Figure 200: Synchronous ODT Timing with BL8
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7 diff_CK
Command
ODT
DODTLon = WL - 2
DODTLoff = WL - 2
t ADC
DRAM_RTT
tADC
(MAX)
tADC
tADC
(MIN)
RTT(Park)
RTT(NOM)
(MAX)
(MIN)
RTT(Park)
Transitioning
Notes:
1. Example for CWL = 9, AL = 0, PL = 0; DODTLon = AL + PL + CWL - 2 = 7; DODTLoff = AL +
PL + CWL - 2 = 7.
2. ODT must be held HIGH for at least ODTH8 after assertion (T1).
Figure 201: Synchronous ODT with BC4
T0
T1
T2
T3
T4
T5
T18
T19
T20
T21
T22
T23
T36
T37
T38
T39
T40
T41
42
diff_CK
WRS4
Command
ODTH4
ODT
DODTLoff = WL - 2
ODTLcnw= WL - 2
ODTLcwn4 = ODTLcnw + 4
DODTLon = CWL - 2
tADC
(MAX)
tADC
RTT(Park)
(MIN)
tADC
(MAX)
tADC
(MIN)
RTT(NOM)
RTT(Park)
tADC
(MAX)
tADC
(MIN)
RTT(WR)
tADC
tADC
(MAX)
(MIN)
RTT(Park)
DRAM_RTT
Transitioning
Notes:
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
1. Example for CWL = 9, AL = 10, PL = 0; DODTLon/off = AL + PL+ CWL - 2 = 17; ODTcnw =
AL + PL+ CWL - 2 = 17.
2. ODT must be held HIGH for at least ODTH4 after assertion (T1).
254
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4Gb: x4, x8, x16 DDR4 SDRAM
Synchronous ODT Mode
ODT During Reads
Because the DRAM cannot terminate with RTT and drive with RON at the same time, RTT
may nominally not be enabled until the end of the postamble as shown in the example
below. At cycle T25 the device turns on the termination when it stops driving, which is
determined by tHZ. If the DRAM stops driving early (that is, tHZ is early), then tADC
(MIN) timing may apply. If the DRAM stops driving late (that is, tHZ is late), then the
DRAM complies with tADC (MAX) timing.
Using CL = 11 as an example for the figure below: PL = 0, AL = CL - 1 = 10, RL = PL + AL +
CL = 21, CWL= 9; RODTLoff = RL - 2 = 19, DODTLon = PL + AL + CWL - 2 = 17, 1tCK
preamble.
Figure 202: ODT During Reads
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
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09005aef84af6dd0
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Dynamic ODT
Dynamic ODT
In certain application cases and to further enhance signal integrity on the data bus, it is
desirable that the termination strength of the device can be changed without issuing an
MRS command. This requirement is supported by the dynamic ODT feature.
Functional Description
Dynamic ODT mode is enabled if bit A9 or A10 of MR2 is set to 1.
• Three RTT values are available: RTT(NOM), RTT(WR), and RTT(Park).
– The value for RTT(NOM) is preselected via bits MR1[10:8].
– The value for RTT(WR) is preselected via bits MR2[11:9].
– The value for RTT(Park) is preselected via bits MR5[8:6].
• During operation without WRITE commands, the termination is controlled as follows:
– Nominal termination strength RTT(NOM) or RTT(Park) is selected.
– RTT(NOM) on/off timing is controlled via ODT pin and latencies DODTLon and
DODTLoff, and RTT(Park) is on when ODT is LOW.
• When a WRITE command (WR, WRA, WRS4, WRS8, WRAS4, and WRAS8) is registered, and if dynamic ODT is enabled, the termination is controlled as follows:
– Latency ODTLcnw after the WRITE command, termination strength R TT(WR) is selected.
– Latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for
BC4, fixed by MRS or selected OTF) after the WRITE command, termination
strength RTT(WR) is de-selected.
One or two clocks will be added into or subtracted from ODTLcwn8 and ODTLcwn4,
depending on write CRC mode and/or 2tCK preamble enablement.
The following table shows latencies and timing parameters relevant to the on-die termination control in dynamic ODT mode. The dynamic ODT feature is not supported in
DLL-off mode. An MRS command must be used to set RTT(WR) to disable dynamic ODT
externally (MR2[11:9] = 000).
Table 74: Dynamic ODT Latencies and Timing (1tCK Preamble Mode and CRC Disabled)
Name and Description
Abbr.
Defined from
Defined to
Definition for All
DDR4 Speed Bins
Unit
ODTLcnw = WL - 2
tCK
ODT latency for change from
RTT(Park)/RTT(NOM) to RTT(WR)
ODTLcnw
Registering external Change RTT strength
WRITE command
from RTT(Park)/RTT(NOM)
to RTT(WR)
ODT latency for change from
RTT(WR) to RTT(Park)/RTT(NOM) (BC =
4)
ODTLcwn
4
Registering external
WRITE command
Change RTT strength
from RTT(WR) to
RTT(Park)/RTT(NOM)
ODTLcwn4 = 4 +
ODTLcnw
tCK
ODT latency for change from
RTT(WR) to RTT(Park)/RTT(NOM) (BL =
8)
ODTLcwn
8
Registering external
WRITE command
Change RTT strength
from RTT(NOM) to
RTT(WR)
ODTLcwn8 = 6 +
ODTLcnw
tCK
(AVG)
tADC
ODTLcnw
ODTLcwn
RTT valid
RTT change skew
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tADC
tADC
(MIN) = 0.3
(MAX) = 0.7
tCK
(AVG)
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4Gb: x4, x8, x16 DDR4 SDRAM
Dynamic ODT
Table 75: Dynamic ODT Latencies and Timing with Preamble Mode and CRC Mode Matrix
1tCK Parameter
2tCK Parameter
Symbol
CRC Off
CRC On
CRC Off
CRC On
Unit
ODTLcnw1
WL - 2
WL - 2
WL - 3
WL - 3
tCK
ODTLcwn4
ODTLcnw + 4
ODTLcnw + 7
ODTLcnw + 5
ODTLcnw + 8
ODTLcwn8
ODTLcnw + 6
ODTLcnw + 7
ODTLcnw + 7
ODTLcnw + 8
1. ODTLcnw = WL - 2 (1tCK preamble) or WL - 3 (2tCK preamble).
Note:
Figure 203: Dynamic ODT (1t CK Preamble; CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled)
T0
T1
T2
T5
T6
T7
T8
T9
T10
T11
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
diff_CK
Command
WR
ODT
DODTLon = WL - 2
DODTLoff = WL - 2
tADC
RTT
tADC
(MAX)
RTT(Park)
tADC
(MAX)
RTT(WR)
tADC
RTT(NOM)
RTT(Park)
tADC
(MIN)
(MIN)
tADC
tADC
(MAX)
(MIN)
(MAX)
RTT(Park)
tADC
(MIN)
ODTLcnw
ODTLcwn
Transitioning
Notes:
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1. ODTLcnw = WL - 2 (1tCK preamble) or WL - 3 (2tCK preamble).
2. If BC4, then ODTLcwn = WL + 4 if CRC disabled or WL + 5 if CRC enabled; If BL8, then
ODTLcwn = WL + 6 if CRC disabled or WL + 7 if CRC enabled.
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Dynamic ODT
Figure 204: Dynamic ODT Overlapped with RTT(NOM) (CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled)
T0
T1
T2
T5
T6
T7
T9
T10
T11
T12
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
diff_CK
Command
WR
ODT
ODTLcnw
ODTLcwn8
tADC
RTT
tADC
(MAX)
RTT_NOM
tADC
(MAX)
RTT_WR
tADC
RTT_NOM
tADC
(MIN)
(MIN)
(MAX)
RTT_PARK
tADC
(MIN)
DODTLoff = CWL -2
Note:
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1. Behavior with WR command issued while ODT is registered HIGH.
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Asynchronous ODT Mode
Asynchronous ODT Mode
Asynchronous ODT mode is selected when the DRAM runs in DLL-off mode. In asynchronous ODT timing mode, the internal ODT command is not delayed by either additive latency (AL) or the parity latency (PL) relative to the external ODT signal (RTT(NOM)).
In asynchronous ODT mode, two timing parameters apply: tAONAS (MIN/MAX), and
tAOFAS (MIN/MAX).
RTT(NOM) Turn-on Time
• Minimum RTT(NOM) turn-on time (tAONAS [MIN]) is when the device termination circuit leaves RTT(Park) and ODT resistance begins to turn on.
• Maximum RTT(NOM) turn-on time (tAONAS [MAX]) is when the ODT resistance has
reached RTT(NOM).
• tAONAS (MIN) and tAONAS (MAX) are measured from ODT being sampled HIGH.
RTT(NOM) Turn-off Time
• Minimum RTT(NOM) turn-off time (tAOFAS [MIN]) is when the device's termination
circuit starts to leave RTT(NOM).
• Maximum RTT(NOM) turn-off time (tAOFAS [MAX]) is when the on-die termination has
reached RTT(Park).
• tAOFAS (MIN) and tAOFAS (MAX) are measured from ODT being sampled LOW.
Figure 205: Asynchronous ODT Timings with DLL Off
T0
T1
T2
T3
T4
T5
T6
Ti
Ti + 1
Ti + 2
Ti + 3
Ti + 4
Ti + 5
Ti + 6
Ta
Tb
diff_CK
CKE
tIH
tIS
tIH
tIS
ODT
tAONAS
RTT
(MAX)
tAONAS
RTT(Park)
(MIN)
RTT(NOM)
tAONAS
(MIN)
tAONAS
(MAX)
Transitioning
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Electrical Specifications
Electrical Specifications
Absolute Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Although "unlimited" row accesses to the same row is allowed
within the refresh period; excessive row accesses to the same row over a long term can
result in degraded operation.
Table 76: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
V
1
VDD
Voltage on VDD pin relative to VSS
–0.4
1.5
VDDQ
Voltage on VDDQ pin relative to VSS
–0.4
1.5
V
1
VPP
Voltage on VPP pin relative to VSS
–0.4
3.0
V
3
VIN, VOUT
Voltage on any pin relative to VSS
–0.4
1.5
V
Storage temperature
–55
150
°C
TSTG
2
1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be
greater than 0.6 × VDDQ. When VDD and VDDQ are <500mV, VREF can be ≤300mV.
2. Storage temperature is the case surface temperature on the center/top side of the
DRAM. For the measurement conditions, please refer to the JESD51-2 standard.
3. VPP must be equal to or greater than VDD/VDDQ at all times when powered.
Notes:
DRAM Component Operating Temperature Range
Operating temperature, T OPER, is the case surface temperature on the center/top side of
the DRAM. For measurement conditions, refer to the JEDEC document JESD51-2.
Table 77: Temperature Range
Symbol
TOPER
Parameter
Normal operating temperature range
Extended temperature range (optional)
Notes:
Min
Max
Unit
Notes
0
85
°C
1
>85
95
°C
2
1. The normal temperature range specifies the temperatures at which all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0°C to 85°C under all operating conditions for the commercial offering;
The industrial temperature offering allows the case temperature to go below 0°C to
-40°C.
2. Some applications require operation of the commercial and industrial temperature
DRAMs in the extended temperature range (between 85°C and 95°C case temperature).
Full specifications are supported in this range, but the following additional conditions
apply:
• REFRESH commands must be doubled in frequency, reducing the refresh interval tREFI
to 3.9μs. It is also possible to specify a component with 1X refresh (tREFI to 7.8μs) in
the extended temperature range.
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4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics – AC and DC Operating Conditions
• If SELF REFRESH operation is required in the extended temperature range, it is mandatory to use either the manual self refresh mode with extended temperature range capability (MR2[6] = 0 and MR2 [7] = 1) or enable the optional auto self refresh mode
(MR2 [6] = 1 and MR2 [7] = 1).
Electrical Characteristics – AC and DC Operating Conditions
Supply Operating Conditions
Table 78: Recommended Supply Operating Conditions
Rating
Symbol
Parameter
Min
Typ
Max
Unit
Notes
VDD
Supply voltage
1.14
1.2
1.26
V
1, 2, 3, 4, 5
VDDQ
Supply voltage for output
1.14
1.2
1.26
V
1, 2, 6
Wordline supply voltage
2.375
2.5
2.750
V
7
VPP
Notes:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. VDD slew rate between 300mV and 80% of VDD,min shall be between 0.004 V/ms and 600
V/ms, 20 MHz band-limited measurement.
4. VDD ramp time from 300mV to VDD,min shall be no longer than 200ms.
5. A stable valid VDD level is a set DC level (0 Hz to 250 KHz) and must be no less than
VDD,min and no greater than VDD,max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC level
is final. AC noise of ±60mV (greater than 250 KHz) is allowed on VDD provided the noise
doesn't alter VDD to less than VDD,min or greater than VDD,max.
6. A stable valid VDDQ level is a set DC level (0 Hz to 250 KHz) and must be no less than
VDDQ,min and no greater than VDDQ,max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC
level is final. AC noise of ±60mV (greater than 250 KHz) is allowed on VDDQ provided the
noise doesn't alter VDDQ to less than VDDQ,min or greater than VDDQ,max.
7. A stable valid VPP level is a set DC level (0 Hz to 250 KHz) and must be no less than
VPP,min and no greater than VPP,max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC level
is final. AC noise of ±120mV (greater than 250 KHz) is allowed on VPP provided the noise
doesn't alter VPP to less than VPP,min or greater than VPP,max.
Table 79: VDD Slew Rate
Symbol
Min
Max
Unit
Notes
VDD_sl
0.004
600
V/ms
1, 2
VDD_on
–
200
ms
3
Notes:
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1. Measurement made between 300mV and 80% VDD (minimum level).
2. The DC bandwidth is limited to 20 MHz.
3. Maximum time to ramp VDD from 300 mV to VDD minimum.
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Electrical Characteristics – AC and DC Operating Conditions
Leakages
Table 80: Leakages
Condition
Symbol
Min
Max
Unit
Notes
Input leakage (excluding ZQ and TEN)
IIN
–2
2
μA
1
ZQ leakage
IZQ
–3
3
μA
1
TEN leakage
ITEN
–6
10
μA
1, 2
VREFCA leakage
IVREFCA
–2
2
μA
3
Output leakage: VOUT = VDDQ
IOZpd
–
5
μA
4
Output leakage: VOUT = VSSQ
IOZpu
–50
–
μA
4, 5
Notes:
1.
2.
3.
4.
5.
Input under test 0V < VIN < 1.1V.
Additional leakage due to weak pull-down.
VREFCA = VDD/2, VDD at valid level after initialization.
DQs are disabled.
ODT is disabled with the ODT input HIGH.
VREFCA Supply
VREFCA is to be supplied to the DRAM and equal to V DD/2. The V REFCA is a reference supply input and therefore does not draw biasing current.
The DC-tolerance limits and AC-noise limits for the reference voltages V REFCA are illustrated in the figure below. The figure shows a valid reference voltage V REF(t) as a function
of time (VREF stands for V REFCA). V REF(DC) is the linear average of V REF(t) over a very long
period of time (1 second). This average has to meet the MIN/MAX requirements. Furthermore, V REF(t) may temporarily deviate from V REF(DC) by no more than ±1% V DD for
the AC-noise limit.
Figure 206: VREFDQ Voltage Range
Voltage
VDD
VREF(t)
VREF AC-noise
VREF(DC) MAX
VREF(DC)
VDD/2
VREF(DC) MIN
VSS
Time
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Electrical Characteristics – AC and DC Operating Conditions
The voltage levels for setup and hold time measurements are dependent on V REF. V REF is
understood as V REF(DC), as defined in the above figure. This clarifies that DC-variations
of V REF affect the absolute voltage a signal has to reach to achieve a valid HIGH or LOW
level, and therefore, the time to which setup and hold is measured. System timing and
voltage budgets need to account for V REF(DC) deviations from the optimum position
within the data-eye of the input signals. This also clarifies that the DRAM setup/hold
specification and derating values need to include time and voltage associated with V REF
AC-noise. Timing and voltage effects due to AC-noise on V REF up to the specified limit
(±1% of V DD) are included in DRAM timings and their associated deratings.
VREFDQ Supply and Calibration Ranges
The device internally generates its own V REFDQ. DRAM internal V REFDQ specification parameters: voltage range, step size, V REF step time, V REF full step time, and V REF valid level
are used to help provide estimated values for the internal V REFDQ and are not pass/fail
limits. The voltage operating range specifies the minimum required range for DDR4
SDRAM devices. The minimum range is defined by V REFDQ,min and V REFDQ,max. A calibration sequence should be performed by the DRAM controller to adjust V REFDQ and
optimize the timing and voltage margin of the DRAM data input receivers.
Table 81: VREFDQ Specification
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Range 1 VREFDQ operating points
VREFDQ R1
60%
–
92%
VDDQ
1, 2
Range 2 VREFDQ operating points
VREFDQ R2
45%
–
77%
VDDQ
1, 2
VREF,step
0.5%
0.65%
0.8%
VDDQ
3
VREF,set_tol
–1.625%
0%
1.625%
VDDQ
4, 5, 6
–0.15%
0%
0.15%
VDDQ
4, 7, 8
VREF step size
VREF set tolerance
VREF step time
VREF valid tolerance
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
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VREF,time
–
–
150
ns
9, 10, 11
VREF_val_tol
–0.15%
0%
0.15%
VDDQ
12
VREF(DC) voltage is referenced to VDDQ(DC). VDDQ(DC) is 1.2V.
DRAM range 1 or range 2 is set by the MRS6[6]6.
VREF step size increment/decrement range. VREF at DC level.
VREF,new = VREF,old ±n × VREF,step; n = number of steps. If increment, use “+,” if decrement,
use “-.”
For n >4, the minimum value of VREF setting tolerance = VREF,new - 1.625% × VDDQ. The
maximum value of VREF setting tolerance = VREF,new + 1.625% × VDDQ.
Measured by recording the MIN and MAX values of the VREF output over the range,
drawing a straight line between those points, and comparing all other VREF output settings to that line.
For n ≤4, the minimum value of VREF setting tolerance = VREF,new - 0.15% × VDDQ. The
maximum value of VREF setting tolerance = VREF,new + 0.15% × VDDQ.
Measured by recording the MIN and MAX values of the VREF output across four consecutive steps (n = 4), drawing a straight line between those points, and comparing all VREF
output settings to that line.
Time from MRS command to increment or decrement one step size for VREF.
Time from MRS command to increment or decrement more than one step size up to the
full range of VREF.
If the VREF monitor is enabled, VREF must be derated by +10ns if DQ bus load is 0pF and
an additional +15 ns/pF of DQ bus loading.
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Electrical Characteristics – AC and DC Operating Conditions
12. Only applicable for DRAM component-level test/characterization purposes. Not applicable for normal mode of operation. VREF valid qualifies the step times, which will be characterized at the component level.
VREFDQ Ranges
MR6[6] selects range 1 (60% to 92.5% of V DDQ) or range 2 (45% to 77.5% of V DDQ), and
MR6[5:0] sets the V REFDQ level, as listed in the following table. The values in MR6[6:0]
will update the V DDQ range and level independent of MR6[7] setting. It is recommended
MR6[7] be enabled when changing the settings in MR6[6:0], and it is highly recommended MR6[7] be enabled when changing the settings in MR6[6:0] multiple times during a
calibration routine.
Table 82: VREFDQ Range and Levels
MR6[5:0]
MR6[6] 0 =
Range 1
MR6[6] 1 =
Range 2
MR6[5:0]
MR6[6] 0 =
Range 1
MR6[6] 1 =
Range 2
00 0000
60.00%
45.00%
01 1010
76.90%
61.90%
00 0001
60.65%
45.65%
01 1011
77.55%
62.55%
00 0010
61.30%
46.30%
01 1100
78.20%
63.20%
00 0011
61.95%
46.95%
01 1101
78.85%
63.85%
00 0100
62.60%
47.60%
01 1110
79.50%
64.50%
00 0101
63.25%
48.25%
01 1111
80.15%
65.15%
00 0110
63.90%
48.90%
10 0000
80.80%
65.80%
00 0111
64.55%
49.55%
10 0001
81.45%
66.45%
00 1000
65.20%
50.20%
10 0010
82.10%
67.10%
00 1001
65.85%
50.85%
10 0011
82.75%
67.75%
00 1010
66.50%
51.50%
10 0100
83.40%
68.40%
00 1011
67.15%
52.15%
10 0101
84.05%
69.05%
00 1100
67.80%
52.80%
10 0110
84.70%
69.70%
00 1101
68.45%
53.45%
10 0111
85.35%
70.35%
00 1110
69.10%
54.10%
10 1000
86.00%
71.00%
00 1111
69.75%
54.75%
10 1001
86.65%
71.65%
01 0000
70.40%
55.40%
10 1010
87.30%
72.30%
01 0001
71.05%
56.05%
10 1011
87.95%
72.95%
01 0010
71.70%
56.70%
10 1100
88.60%
73.60%
01 0011
72.35%
57.35%
10 1101
89.25%
74.25%
01 0100
73.00%
58.00%
10 1110
89.90%
74.90%
01 0101
73.65%
58.65%
10 1111
90.55%
75.55%
01 0110
74.30%
59.30%
11 0000
91.20%
76.20%
01 0111
74.95%
59.95%
11 0001
91.85%
76.85%
01 1000
75.60%
60.60%
11 0010
92.50%
77.50%
01 1001
76.25%
61.25%
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11 0011 to 11 1111 are reserved
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Electrical Characteristics – AC and DC Single-Ended Input Measurement
Levels
RESET_n Input Levels
Table 83: RESET_n Input Levels (CMOS)
Parameter
Symbol
Min
Max
Unit
Note
AC input high voltage
VIH(AC)_RESET
0.8 × VDD
VDD
V
1
DC input high voltage
VIH(DC)_RESET
0.7 × VDD
VDD
V
2
DC input low voltage
VIL(DC)_RESET
VSS
0.3 × VDD
V
3
AC input low voltage
VIL(AC)_RESET
VSS
0.2 × VDD
V
4
tR_RESET
–
1
μs
5
RESET pulse width after power-up
tPW_RESET_S
1
–
μs
6, 7
RESET pulse width during power-up
tPW_RESET_L
200
–
μs
6
Rising time
Notes:
1. Overshoot should not exceed the VIN shown in the Absolute Maximum Ratings table.
2. After RESET_n is registered HIGH, the RESET_n level must be maintained above
VIH(DC)_RESET, otherwise operation will be uncertain until it is reset by asserting RESET_n
signal LOW.
3. After RESET_n is registered LOW, the RESET_n level must be maintained below VIL(DC)_REt
SET during PW_RESET, otherwise the DRAM may not be reset.
4. Undershoot should not exceed the VIN shown in the Absolute Maximum Ratings table.
5. Slope reversal (ring-back) during this level transition from LOW to HIGH should be mitigated as much as possible.
6. RESET is destructive to data contents.
7. See RESET Procedure at Power Stable Condition figure.
Figure 207: RESET_n Input Slew Rate Definition
tPW_RESET
VIH(AC)_RESET,min
VIH(DC)_RESET,min
VIL(DC)_RESET,max
VIL(AC)_RESET,max
tR_RESET
Command/Address Input Levels
Table 84: Command and Address Input Levels: DDR4-1600 Through DDR4-2400
Parameter
Symbol
Min
Max
Unit
Note
AC input high voltage
VIH(AC)
VREF + 100
VDD5
mV
1, 2, 3
DC input high voltage
VIH(DC)
VREF + 75
VDD
mV
1, 2
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Table 84: Command and Address Input Levels: DDR4-1600 Through DDR4-2400 (Continued)
Parameter
Symbol
Min
Max
Unit
Note
DC input low voltage
VIL(DC)
VSS
VREF - 75
mV
1, 2
AC input low voltage
VIL(AC)
VSS5
VREF - 100
mV
1, 2, 3
VREFFCA(DC)
0.49 × VDD
0.51 × VDD
V
4
Reference voltage for CMD/ADDR inputs
Notes:
1.
2.
3.
4.
For input except RESET_n. VREF = VREFCA(DC).
VREF = VREFCA(DC).
Input signal must meet VIL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings.
The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than
±1% VDD (for reference: approximately ±12mV).
5. Refer to “Overshoot and Undershoot Specifications.”
Table 85: Command and Address Input Levels: DDR4-2666
Parameter
Symbol
Min
Max
Unit
Note
AC input high voltage
VIH(AC)
VREF + 90
VDD5
mV
1, 2, 3
DC input high voltage
VIH(DC)
VREF + 65
VDD
mV
1, 2
DC input low voltage
VIL(DC)
VSS
VREF - 65
mV
1, 2
AC input low voltage
VIL(AC)
VSS5
VREF - 90
mV
1, 2, 3
VREFFCA(DC)
0.49 × VDD
0.51 × VDD
V
4
Reference voltage for CMD/ADDR inputs
Notes:
1.
2.
3.
4.
For input except RESET_n. VREF = VREFCA(DC).
VREF = VREFCA(DC).
Input signal must meet VIL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings.
The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than
±1% VDD (for reference: approximately ±12mV).
5. Refer to “Overshoot and Undershoot Specifications.”
Table 86: Command and Address Input Levels: DDR4-2933 and DDR4-3200
Parameter
Symbol
Min
Max
Unit
Note
AC input high voltage
VIH(AC)
VREF + 90
VDD5
mV
1, 2, 3
DC input high voltage
VIH(DC)
VREF + 65
VDD
mV
1, 2
DC input low voltage
VIL(DC)
VSS
VREF - 65
mV
1, 2
AC input low voltage
VIL(AC)
VSS5
VREF - 90
mV
1, 2, 3
VREFFCA(DC)
0.49 × VDD
0.51 × VDD
V
4
Reference voltage for CMD/ADDR inputs
Notes:
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1.
2.
3.
4.
For input except RESET_n. VREF = VREFCA(DC).
VREF = VREFCA(DC).
Input signal must meet VIL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings.
The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than
±1% VDD (for reference: approximately ±12mV).
5. Refer to “Overshoot and Undershoot Specifications.”
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Table 87: Single-Ended Input Slew Rates
Parameter
Single-ended input slew rate – CA
Notes:
1.
2.
3.
4.
Symbol
Min
Max
Unit
Note
SRCA
1.0
7.0
V/ns
1, 2, 3, 4
For input except RESET_n.
VREF = VREFCA(DC).
tIS/tIH timings assume SR
CA = 1V/ns.
Measured between VIH(AC) and VIL(AC) for falling edges and between VIL(AC) and VIH(AC)
for rising edges
Figure 208: Single-Ended Input Slew Rate Definition
TRse
TFse
VIH(AC)
VIH(DC)
VREFCA
VIL(DC)
VIL(AC)
Command, Control, and Address Setup, Hold, and Derating
The total tIS (setup time) and tIH (hold time) required is calculated to account for slew
rate variation by adding the data sheet tIS (base) values, the V IL(AC)/VIH(AC) points, and
tIH (base) values, the V
t
t
IL(DC)/VIH(DC) points; to the Δ IS and Δ IH derating values, respectively. The base values are derived with single-end signals at 1V/ns and differential
clock at 2 V/ns. Example: tIS (total setup time) = tIS (base) + ΔtIS. For a valid transition,
the input signal has to remain above/below V IH(AC)/VIL(AC) for the time defined by tVAC.
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V IH(AC)/VIL(AC) at the time of the rising clock transition), a valid input signal is still required to complete the transition and to reach
VIH(AC)/VIL(AC). For slew rates that fall between the values listed in derating tables, the
derating values may be obtained by linear interpolation.
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V IL(DC)max and the first crossing of V IH(AC)min that does not ring back below V IH(DC)min . Setup (tIS) nominal slew rate for a falling signal is defined as the slew
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
rate between the last crossing of V IH(DC)min and the first crossing of V IL(AC)max that does
not ring back above V IL(DC)max.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V IL(DC)max and the first crossing of V IH(AC)min that does not ring back below V IH(DC)min. Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate
between the last crossing of V IH(DC)min and the first crossing of V IL(AC)minthat does not
ring back above V IL(DC)max.
Table 88: Command and Address Setup and Hold Values Referenced – AC/DC-Based
Symbol
tIS(base,
1600
1866
2133
2400
2666
2933
3200
Unit
Reference
115
100
80
62
–
–
–
ps
VIH(AC)/VIL(AC)
AC100)
tIH(base,
DC75)
140
125
105
87
–
–
–
ps
VIH(DC)/VIL(DC)
tIS(base,
AC90)
–
–
–
–
55
48
40
ps
VIH(AC)/VIL(AC)
tIH(base,
DC65)
tIS/tIH(Vref)
–
–
–
–
80
73
65
ps
VIH(DC)/VIL(DC)
215
200
180
162
145
138
130
ps
VIH(DC)/VIL(DC)
Table 89: Derating Values for tIS/tIH – AC100DC75-Based
ΔtIS with AC100 Threshold, ΔtIH with DC75 Threshold Derating (ps) – AC/DC-Based
CMD/
ADDR
Slew Rate
V/ns
CK, CK# Differential Slew Rate
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIH
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
7.0
76
54
76
55
77
56
79
58
82
60
86
64
94
73
111
89
6.0
73
53
74
53
75
54
77
56
79
58
83
63
92
71
108
88
5.0
70
50
71
51
72
52
74
54
76
56
80
60
88
68
105
85
4.0
65
46
66
47
67
48
69
50
71
52
75
56
83
65
100
81
3.0
57
40
57
41
58
42
60
44
63
46
67
50
75
58
92
75
2.0
40
28
41
28
42
29
44
31
46
33
50
38
58
46
75
63
1.5
23
15
24
16
25
17
27
19
29
21
33
25
42
33
58
50
1.0
–10
–10
–9
–9
–8
–8
–6
–6
–4
–4
0
0
8
8
25
25
0.9
–17
–14
–16
–14
–15
–13
–13
–10
–11
–8
–7
–4
1
4
18
21
0.8
–26
–19
–25
–19
–24
–18
–22
–16
–20
–14
–16
–9
–7
–1
9
16
0.7
–37
–26
–36
–25
–35
–24
–33
–22
–31
–20
–27
–16
–18
–8
–2
9
0.6
–52
–35
–51
–34
–50
–33
–48
–31
–46
–29
–42
–25
–33
–17
–17
0
0.5
–73
–48
–72
–47
–71
–46
–69
–44
–67
–42
–63
–38
–54
–29
–38
–13
0.4
–104
–66
–103
–66
–102
–65
–100
–63
–98
–60
–94
–56
–85
–48
–69
–31
10.0 V/ns
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8.0 V/ns
6.0 V/ns
4.0 V/ns
268
3.0 V/ns
2.0 V/ns
1.5 V/ns
1.0 V/ns
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Table 90: Derating Values for tIS/tIH – AC90/DC65-Based
ΔtIS with AC90 Threshold, ΔtIH with DC65 Threshold Derating (ps) – AC/DC-Based
CMD/
ADDR
Slew Rate
V/ns
CK, CK# Differential Slew Rate
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIH
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
7.0
68
47
69
47
70
48
72
50
73
52
77
56
85
63
100
78
6.0
66
45
67
46
68
47
69
49
71
50
75
54
83
62
98
77
5.0
63
43
64
44
65
45
66
46
68
48
72
52
80
60
95
75
4.0
59
40
59
40
60
41
62
43
64
45
68
49
75
56
90
71
3.0
51
34
52
35
53
36
54
38
56
40
60
43
68
51
83
66
2.0
36
24
37
24
38
25
39
27
41
29
45
33
53
40
68
55
1.5
21
13
22
13
23
14
24
16
26
18
30
22
38
29
53
44
1.0
–9
–9
–8
–8
–8
–8
–6
–6
–4
–4
0
0
8
8
23
23
0.9
–15
–13
–15
–12
–14
–11
–12
–9
–10
–7
–6
–4
1
4
16
19
0.8
–23
–17
–23
–17
–22
–16
–20
–14
–18
–12
–14
–8
–7
–1
8
14
0.7
–34
–23
–33
–22
–32
–21
–30
–20
–28
–18
–25
–14
–17
–6
–2
9
0.6
–47
–31
–47
–30
–46
–29
–44
–27
–42
–25
–38
–22
–31
–14
–16
1
0.5
–67
–42
–66
–41
–65
–40
–63
–38
–61
–36
–58
–33
–50
–25
–35
–10
0.4
–95
–58
–95
–57
–94
–56
–92
–54
–90
–53
–86
–49
–79
–41
–64
–26
10.0 V/ns
8.0 V/ns
6.0 V/ns
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.5 V/ns
1.0 V/ns
Data Receiver Input Requirements
The following parameters apply to the data receiver Rx MASK operation detailed in the
Write Timing section, Data Strobe-to-Data Relationship.
The rising edge slew rates are defined by srr1 and srr2. The slew rate measurement
points for a rising edge are shown in the figure below. A LOW-to-HIGH transition time,
tr1, is measured from 0.5 × V diVW,max below V CENTDQ,midpoint to the last transition
through 0.5 × V diVW,max above V CENTDQ,midpoint; tr2 is measured from the last transition
through 0.5 × V diVW,max above V CENTDQ,midpoint to the first transition through the 0.5 ×
VIHL(AC)min above V CENTDQ,midpoint.
The falling edge slew rates are defined by srf1 and srf2. The slew rate measurement
points for a falling edge are shown in the figure below. A HIGH-to-LOW transition time,
tf1, is measured from 0.5 × V diVW,max above V CENTDQ,midpoint to the last transition
through 0.5 × V diVW,max below V CENTDQ,midpoint; tf2 is measured from the last transition
through 0.5 × V diVW,max below V CENTDQ,midpoint to the first transition through the 0.5 ×
VIHL(AC)min below V CENTDQ,midpoint.
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Figure 209: DQ Slew Rate Definitions
VCENTDQ,midpoint
0.5 × VdiVW,max
VdiVW,max
0.5 ×
VIHL(AC)min
tr1
tf1
0.5 × VdiVW,max
Rx Mask
VCENTDQ,midpoint
0.5 × VdiVW,max
VdiVW,max
0.5 ×
VIHL(AC)min
0.5 ×
VIHL(AC)min
0.5 × VdiVW,max
Rx Mask
0.5 ×
VIHL(AC)min
VIHL(AC)min
VIHL(AC)min
tr2
tf2
Notes:
1.
2.
3.
4.
Rising edge slew rate equation srr1 = VdiVW,max/(tr1).
Rising edge slew rate equation srr2 = (VIHL(AC)min - VdiVW,max )/(2 × tr2).
Falling edge slew rate equation srf1 = VdiVW,max/(tf1).
Falling edge slew rate equation srf2 = (VIHL(AC)min - VdiVW,max )/(2 × tf2).
Table 91: DQ Input Receiver Specifications
Note 1 applies to the entire table
DDR4-1600,
1866, 2133
DDR4-2400
DDR4-2666
DDR4-2933
DDR4-3200
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Not
es
VIN Rx mask input
peak-to-peak
VdiVW
–
136
–
130
–
120
–
115
–
110
mV
2, 3
DQ Rx input timing window
TdiVW
–
0.2
–
0.2
–
0.22
–
0.23
–
0.23
UI
2, 3
DQ AC input
swing peak-topeak
VIHL(AC)
186
–
160
–
150
–
145
–
140
–
mV
4, 5
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Table 91: DQ Input Receiver Specifications (Continued)
Note 1 applies to the entire table
DDR4-1600,
1866, 2133
DDR4-2400
DDR4-2666
DDR4-2933
DDR4-3200
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Not
es
DQ input pulse
width
TdiPW
0.58
–
0.58
–
0.58
–
0.58
–
0.58
–
UI
6
DQS-to-DQ Rx
mask offset
tDQS2D
–0.17
0.17
–0.17
0.17
–0.19
0.19
–0.22
0.22
–0.22
0.22
UI
7
DQ-to-DQ Rx mask
offset
tDQ2DQ
–
0.1
–
0.1
–
0.105
–
0.115
–
0.125
UI
8
srr1, srf1
Input slew rate
over VdiVW if tCK ≥
0.925ns
1
9
1
9
1
9
1
9
1
9
V/ns
9
Input slew rate
over VdiVW if
0.935ns > tCK ≥
0.625ns
srr1, srf1
–
–
1.25
9
1.25
9
1.25
9
1.25
9
V/ns
9
Rising input slew
rate over 1/2
VIHL(AC)
srr2
0.2 ×
srr1
9
0.2 ×
srr1
9
0.2 ×
srr1
9
0.2 ×
srr1
9
0.2 ×
srr1
9
V/ns
10
Falling input slew
rate over 1/2
VIHL(AC)
srf2
0.2 ×
srf1
9
0.2 ×
srf1
9
0.2 ×
srf1
9
0.2 ×
srf1
9
0.2 ×
srf1
9
V/ns
10
Q
Notes:
1. All Rx mask specifications must be satisfied for each UI. For example, if the minimum input pulse width is violated when satisfying TdiVW (MIN), VdiVW,max, and minimum slew
rate limits, then either TdiVW (MIN) or minimum slew rates would have to be increased
to the point where the minimum input pulse width would no longer be violated.
2. Data Rx mask voltage and timing total input valid window where VdiVW is centered
around VCENTDQ,midpoint after VREFDQ training is completed. The data Rx mask is applied
per bit and should include voltage and temperature drift terms. The input buffer design
specification is to achieve at least a BER =1e- 16 when the Rx mask is not violated.
3. Defined over the DQ internal VREF range 1.
4. Overshoot and undershoot specifications apply.
5. DQ input pulse signal swing into the receiver must meet or exceed VIHL(AC)min. VIHL(AC)min
is to be achieved on an UI basis when a rising and falling edge occur in the same UI (a
valid TdiPW).
6. DQ minimum input pulse width defined at the VCENTDQ,midpoint.
7. DQS-to-DQ Rx mask offset is skew between DQS and DQ within a nibble (x4) or word
(x8, x16 [for x16, the upper and lower bytes are treated as separate x8s]) at the SDRAM
balls over process, voltage, and temperature.
8. DQ-to-DQ Rx mask offset is skew between DQs within a nibble (x4) or word (x8, x16) at
the SDRAM balls for a given component over process, voltage, and temperature.
9. Input slew rate over VdiVW mask centered at VCENTDQ,midpoint. Slowest DQ slew rate to
fastest DQ slew rate per transition edge must be within 1.7V/ns of each other.
10. Input slew rate between VdiVW mask edge and VIHL(AC)min points.
The following figure shows the Rx mask relationship to the input timing specifications
relative to system tDS and tDH. The classical definition for tDS/tDH required a DQ rising
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
and falling edges to not violate tDS and tDH relative to the DQS strobe at any time; however, with the Rx mask tDS and tDH can shift relative to the DQS strobe provided the
input pulse width specification is satisfied and the Rx mask is not violated.
Figure 210: Rx Mask Relative to tDS/tDH
TdiPW
VIH(DC)
VdiVW
0.5 × VdiVW
VCENTDQ,pin mean
Rx
Mask
0.5 × VdiVW
VIL(DC)
tf1
tr1
TdiVW
tDS
tDH
= Greater of 0.5 × TdiVW
or
0.5 × (TdiPW + VdiVW/tf1)
= Greater of 0.5 × TdiVW
or
0.5 × (TdiPW + VdiVW/tr1)
DQS_c
DQS_t
The following figure and table show an example of the worst case Rx mask required if
the DQS and DQ pins do not have DRAM controller to DRAM write DQ training. The
figure and table show that without DRAM write DQ training, the Rx mask would increase from 0.2UI to essentially 0.54UI. This would also be the minimum tDS and tDH
required as well.
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Figure 211: Rx Mask Without Write Training
TdiVW + 2 × tDQS2DQ
VdiVW
VIH(DC)
0.5 × VdiVW
Rx Mask
VCENTDQ,midpoint
0.5 × VdiVW
VIL(DC)
tDS
tDH
0.5 × TdiVW + tDQS2DQ 0.5 × TdiVW + tDQS2DQ
DQS_c
DQS_t
Table 92: Rx Mask and tDS/tDH without Write Training
Rx Mask
with Write
Train
(ps)
DDR4
VIHL(AC)
(mV)
TdiPW
(UI)
VdiVW
(mV)
TdiVW
(UI)
tDQS2DQ
tDQ2DQ
(UI)
(UI)
1600
186
0.58
136
0.2
±0.17
0.1
125
1866
186
0.58
136
0.2
±0.17
0.1
107.1
289
2133
186
0.58
136
0.2
±0.17
0.1
94
253
2400
160
0.58
130
0.2
±0.17
0.1
83.3
225
2666
150
0.58
120
0.22
±0.19
0.105
82.5
225
2933
145
0.58
115
0.23
±0.22
0.115
78.4
228
3200
140
0.58
110
0.23
±0.22
0.125
71.8
209
Note:
tDS
+ tDH
(ps)
338
1. VIHL(AC), VdiVW, and VILH(DC) referenced to VCENTDQ,midpoint.
Connectivity Test (CT) Mode Input Levels
Table 93: TEN Input Levels (CMOS)
Parameter
Symbol
Min
Max
Unit
Note
TEN AC input high voltage
VIH(AC)_TEN
0.8 × VDD
VDD
V
1
TEN DC input high voltage
VIH(DC)_TEN
0.7 × VDD
VDD
V
TEN DC input low voltage
VIL(DC)_TEN
VSS
0.3 × VDD
V
TEN AC input low voltage
VIL(AC)_TEN
VSS
0.2 × VDD
V
tF_TEN
–
10
ns
TEN falling time
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Table 93: TEN Input Levels (CMOS) (Continued)
Parameter
TEN rising time
Symbol
Min
Max
Unit
tR_TEN
–
10
ns
Note
1. Overshoot should not exceed the VIN values in the Absolute Maximum Ratings table.
2. Undershoot should not exceed the VIN values in the Absolute Maximum Ratings table.
Notes:
Figure 212: TEN Input Slew Rate Definition
VIH(AC)_TENmin
VIH(DC)_TENmin
VIL(DC)_TENmin
VIL(AC)_TENmin
tF_TEN
tR_TEN
Table 94: CT Type-A Input Levels
Parameter
Symbol
Min
Max
Unit
Note
CTipA AC input high voltage
VIH(AC)
VREF + 200
VDD11
V
2, 3
CTipA DC input high voltage
VIH(DC)
VREF + 150
VDD
V
2, 3
CTipA DC input low voltage
VIL(DC)
VSS
VREF - 150
V
2, 3
1
VIL(AC)
VSS1
VREF - 200
V
2, 3
CTipA falling time
tF_CTipA
–
5
ns
2
CTipA rising time
tR_CTipA
–
5
ns
2
CTipA AC input low voltage
Notes:
1. Refer to Overshoot and Undershoot Specifications.
2. CT Type-A inputs: CS_n, BG[1:0], BA[1:0], A[9:0], A10/AP, A11, A12/BC_n, A13, WE_n/A14,
CAS_n/A15, RAS_n/A16, CKE, ACT_n, ODT, CLK_t, CLK_C, PAR.
3. VREFCA = 0.5 × VDD.
Figure 213: CT Type-A Input Slew Rate Definition
VIH(AC)_CTipAmin
VIH(DC)_CTipAmin
VREFCA
VIL(DC)_CTipAmax
VIL(AC)_CTipAmax
tR_CTipA
tF_CTipA
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Table 95: CT Type-B Input Levels
Parameter
Symbol
Min
Max
Unit
Note
CTipB AC input high voltage
VIH(AC)
VREF + 300
VDD11
V
2, 3
CTipB DC input high voltage
VIH(DC)
VREF + 200
VDD
V
2, 3
CTipB DC input low voltage
VIL(DC)
VSS
VREF - 200
V
2, 3
1
VIL(AC)
VSS1
VREF - 300
V
2, 3
CTipB falling time
tF_CTipB
–
5
ns
2
CTipB rising time
tR_CTipB
–
5
ns
2
CTipB AC input low voltage
Notes:
1. Refer to Overshoot and Undershoot Specifications.
2. CT Type-B inputs: DML_n/DBIL_n, DMU_n/DBIU_n and DM_n/DBI_n.
3. VREFDQ should be 0.5 × VDD
Figure 214: CT Type-B Input Slew Rate Definition
VIH(AC)_CTipBmin
VIH(DC)_CTipBmin
VREFDQ
VIL(DC)_CTipBmax
VIL(AC)_CTipBmax
tF_CTipB
tR_CTipB
Table 96: CT Type-C Input Levels (CMOS)
Parameter
Symbol
Min
Max
Unit
Note
1
V
2
CTipC AC input high voltage
VIH(AC)_CTipC
0.8 × VDD
VDD
CTipC DC input high voltage
VIH(DC)_CTipC
0.7 × VDD
VDD
V
2
CTipC DC input low voltage
VIL(DC)_CTipC
VSS
0.3 × VDD
V
2
CTipC AC input low voltage
VIL(AC)_CTipC
VSS1
0.2 × VDD
V
2
CTipC falling time
tF_CTipC
–
10
ns
2
CTipC rising time
tR_CTipC
–
10
ns
2
Notes:
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1. Refer to Overshoot and Undershoot Specifications.
2. CT Type-C inputs: Alert_n.
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Figure 215: CT Type-C Input Slew Rate Definition
VIH(AC)_TENmin
VIH(DC)_TENmin
VIL(DC)_TENmin
VIL(AC)_TENmin
tF_TEN
tR_TEN
Table 97: CT Type-D Input Levels
Parameter
Symbol
Min
Max
Unit
Note
CTipD AC input high voltage
VIH(AC)_CTipD
0.8 × VDD
VDD
V
4
CTipD DC input high voltage
VIH(DC)_CTipD
0.7 × VDD
VDD
V
2
CTipD DC input low voltage
VIL(DC)_CTipD
VSS
0.3 × VDD
V
1
CTipD AC input low voltage
VIL(AC)_CTipD
VSS
0.2 × VDD
V
5
tR_RESET
–
1
μs
3
RESET pulse width - after power-up
tPW_RESET_S
1
–
μs
RESET pulse width - during power-up
tPW_RESET_L
200
–
μs
Rising time
Notes:
1. After RESET_n is registered LOW, the RESET_n level must be maintained below VIL(DC)_REt
SET during PW_RESET, otherwise, the DRAM may not be reset.
2. After RESET_n is registered HIGH, the RESET_n level must be maintained above
VIH(DC)_RESET, otherwise, operation will be uncertain until it is reset by asserting RESET_n
signal LOW.
3. Slope reversal (ring-back) during this level transition from LOW to HIGH should be mitigated as much as possible.
4. Overshoot should not exceed the VIN values in the Absolute Maximum Ratings table.
5. Undershoot should not exceed the VIN values in the Absolute Maximum Ratings table.
6. CT Type-D inputs: RESET_n; same requirements as in normal mode.
Figure 216: CT Type-D Input Slew Rate Definition
tPW_RESET
VIH(AC)_RESETmin
VIH(DC)_RESETmin
VIL(DC)_RESETmax
VIL(AC)_RESETmax
tR_RESET
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Electrical Characteristics – AC and DC Differential Input Measurement Levels
Electrical Characteristics – AC and DC Differential Input Measurement
Levels
Differential Inputs
Figure 217: Differential AC Swing and “Time Exceeding AC-Level” tDVAC
tDVAC
VIH,diff(AC)min
VIH,diff,min
CK_t, CK_c
0.0
VIL,diff,max
VIL,diff(AC)max
tDVAC
Half cycle
Notes:
1. Differential signal rising edge from VIL,diff,max to VIH,diff(AC)min must be monotonic slope.
2. Differential signal falling edge from IH,diff,min to VIL,diff(AC)max must be monotonic slope.
Table 98: Differential Input Swing Requirements for CK_t, CK_c
DDR4-1600 / 1866 /
2133 / 2400
Parameter
DDR4-2666 / 2933 /
3200
Symbol
Min
Max
Min
Max
Unit
Notes
Differential input high
VIHdiff
0.150
Note 3
0.120
Note 3
V
1
Differential input low
VILdiff
Note 3
–0.150
Note 3
-0.120
V
1
Differential input high (AC)
VIHdiff(AC)
2 × (VIH(AC)
- VREF)
Note 3
2 × (VIH(AC)
- VREF)
Note 3
V
2
Differential input low (AC)
VILdiff(AC)
Note 3
2 × (VIL(AC) VREF)
Note 3
2 × (VIL(AC) VREF)
V
2
Notes:
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1. Used to define a differential signal slew-rate.
2. For CK_t, CK_c use VIH(AC) and VIL(AC) of ADD/CMD and VREFCA.
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Electrical Characteristics – AC and DC Differential Input Measurement Levels
3. These values are not defined; however, the differential signals (CK_t, CK_c) need to be
within the respective limits, VIH(DC)max and VIL(DC)min for single-ended signals as well as
the limitations for overshoot and undershoot.
Table 99: Minimum Time AC Time tDVAC for CK
tDVAC
Note:
(ps) at |VIH,diff(AC) to VIL,diff(AC)|
Slew Rate (V/ns)
200mV
TBDmV
>4.0
120
TBD
4.0
115
TBD
3.0
110
TBD
2.0
105
TBD
1.9
100
TBD
1.6
95
TBD
1.4
90
TBD
1.2
85
TBD
1.0
80
TBD
<1.0
80
TBD
1. Below VIL(AC).
Single-Ended Requirements for CK Differential Signals
Each individual component of a differential signal (CK_t, CK_c) has to comply with certain requirements for single-ended signals. CK_t and CK_c have to reach approximately
VSEHmin/VSEL,max, which are approximately equal to the AC levels V IH(AC) and V IL(AC) for
ADD/CMD signals in every half-cycle. The applicable AC levels for ADD/CMD might
differ per speed-bin, and so on. For example, if a value other than 100mV is used for
ADD/CMD V IH(AC) and V IL(AC) signals, then these AC levels also apply for the singleended signals CK_t and CK_c.
While ADD/CMD signal requirements are with respect to V REFCA, the single-ended components of differential signals have a requirement with respect to V DD/2; this is nominally the same. The transition of single-ended signals through the AC levels is used to
measure setup time. For single-ended components of differential signals the requirement to reach V SEL,max/VSEH,min has no bearing on timing, but adds a restriction on the
common mode characteristics of these signals.
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Electrical Characteristics – AC and DC Differential Input Measurement Levels
Figure 218: Single-Ended Requirements for CK
VDD or VDDQ
VSEH,min
VDD/2 or VDDQ/2
VSEH
CK
VSEL,max
VSEL
VSS or VSSQ
Table 100: Single-Ended Requirements for CK
DDR4-1600 / 1866 /
2133 / 2400
Parameter
DDR4-2666 / 2933 /
3200
Symbol
Min
Max
Min
Max
Unit
Notes
Single-ended high level for CK_t,
CK_c
VSEH
VDD/2 +
0.100
Note 3
VDD/2 +
0.90
Note 3
V
1, 2
Single-ended low level for CK_t, CK_c
VSEL
Note 3
VDD/2 0.100
Note 3
VDD/2 - 0.90
V
1, 2
Notes:
1. For CK_t, CK_c use VIH(AC) and VIL(AC) of ADD/CMD and VREFCA.
2. ADDR/CMD VIH(AC) and VIL(AC) based on VREFCA.
3. These values are not defined; however, the differential signal (CK_t, CK_c) need to be
within the respective limits, VIH(DC)max and VIL(DC)min for single-ended signals as well as
the limitations for overshoot and undershoot.
Slew Rate Definitions for CK Differential Input Signals
Table 101: CK Differential Input Slew Rate Definition
Measured
Description
From
To
Defined by
Differential input slew rate for rising edge
VIL,diff,max
VIH,diff,min
|VIH,diff,min - VIL,diff,maxΔTRdiff
Differential input slew rate for falling edge
VIH,diff,min
VIL,diff,max
|VIH,diff,min - VIL,diff,maxΔTFdiff
Note:
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1. The differential signal CK_t, CK_c must be monotonic between these thresholds.
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Electrical Characteristics – AC and DC Differential Input Measurement Levels
Figure 219: Differential Input Slew Rate Definition for CK_t, CK_c
TRdiff
CK Differential Input Voltage
VIH,diff,min
0
VIL,diff,max
TFdiff
CK Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect
to clock and strobe, each cross point voltage of differential input signal CK_t, CK_c must
meet the requirements shown below. The differential input cross point voltage V IX(CK) is
measured from the actual cross point of true and complement signals to the midlevel
between V DD and V SS.
Figure 220: VIX(CK) Definition
VDD
CK_c
VIX(CK)
VIX(CK)
VIX(CK)
VDD/2
CK_t
VSEH
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VSEL
280
VSS
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Electrical Characteristics – AC and DC Differential Input Measurement Levels
Table 102: Cross Point Voltage For CK Differential Input Signals at DDR4-1600 through DDR4-2400
DDR4-1600, 1866, 2133
DDR4-2400
Parameter
Sym
Input Level
Min
Max
Min
Max
Differential
input cross
point voltage relative
to VDD/2 for
CK_t, CK_c
VIX(CK)
VSEH > VDD/2 + 145mV
N/A
120mV
N/A
120mV
VDD/2 + 100mV ≤ VSEH ≤ VDD/2
+ 145mV
N/A
(VSEH - VDD/2) 25mV
N/A
(VSEH - VDD/2) 25mV
VDD/2 - 145mV ≤ VSEL ≤ VDD/2 100mV
–(VDD/2-VSEL)
+25mV
N/A
–(VDD/2-VSEL) +
25mV
N/A
VSEL ≤ VDD/2 - 145mV
–120mV
N/A
–120mV
N/A
Table 103: Cross Point Voltage For CK Differential Input Signals at DDR4-2666 through DDR4-3200
DDR4-2666
DDR4-2933, 3200
Parameter
Sym
Input Level
Min
Max
Min
Max
Differential
input cross
point voltage relative
to VDD/2 for
CK_t, CK_c
VIX(CK)
VSEH > VDD/2 + 135mV
N/A
110mV
N/A
110mV
VDD/2 + 90mV ≤ VSEH ≤ VDD/2 +
135mV
N/A
(VSEH - VDD/2) 30mV
N/A
(VSEH - VDD/2) 30mV
N/A
–(VDD/2-VSEL) +
30mV
N/A
N/A
–110mV
N/A
VDD/2 - 135mV ≤ VSEL ≤ VDD/2 - –(VDD/2-VSEL) +
90mV
30mV
VSEL ≤ VDD/2 - 135mV
–110mV
DQS Differential Input Signal Definition and Swing Requirements
DQS_t, DQS_c: Differential Input Voltage
Figure 221: Differential Input Signal Definition for DQS_t, DQS_c
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VIH,diff,peak
Half cycle
0.0V
Half cycle
VIL,diff,peak
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Electrical Characteristics – AC and DC Differential Input Measurement Levels
Table 104: DDR4-1600 through DDR4-2400 Differential Input Swing Requirements for DQS_t, DQS_c
DDR4-1600, 1866,
2133
Parameter
DDR4-2400
Symbol
Min
Max
Min
Max
Unit
Notes
Peak differential input high voltage
VIH,diff,peak
186
VDDQ
160
VDDQ
mV
1,2
Peak differential input low voltage
VIL,diff,peak
VSSQ
–186
VSSQ
–160
mV
1,2
1. Minimum and maximum limits are relative to single-ended portion and can be exceeded
within allowed overshoot and undershoot limits.
2. Minimum value point is used to determine differential signal slew-rate.
Notes:
Table 105: DDR4-2633 through DDR4-3200 Differential Input Swing Requirements for DQS_t, DQS_c
DDR4-2666
DDR4-2933
DDR4-3200
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Peak differential input high voltage
VIH,diff,peak
150
VDDQ
145
VDDQ
140
VDDQ
mV
1,2
Peak differential input low voltage
VIL,diff,peak
VSSQ
–150
VSSQ
–145
VSSQ
–140
mV
1,2
Parameter
1. Minimum and maximum limits are relative to single-ended portion and can be exceeded
within allowed overshoot and undershoot limits.
2. Minimum value point is used to determine differential signal slew-rate.
Notes:
The peak voltage of the DQS signals are calculated using the following equations:
VIH,dif,Peak voltage = MAX(ft)
VIL,dif,Peak voltage = MIN(ft)
(ft) = DQS_t, DQS_c.
The MAX(f(t)) or MIN(f(t)) used to determine the midpoint from which to reference the
±35% window of the exempt non-monotonic signaling shall be the smallest peak voltage observed in all UIs.
DQS_t, DQS_c: Single-Ended Input Voltages
Figure 222: DQS_t, DQS_c Input Peak Voltage Calculation and Range of Exempt non-Monotonic Signaling
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DQS_t
+35%
+50%
MIN(ft)
MAX(ft)
–35%
–50%
DQS_c
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Electrical Characteristics – AC and DC Differential Input Measurement Levels
DQS Differential Input Cross Point Voltage
To achieve tight RxMask input requirements as well as output skew parameters with respect to strobe, the cross point voltage of differential input signals (DQS_t, DQS_c) must
meet V IX_DQS,ratio in the table below. The differential input cross point voltage V IX_DQS
(VIX_DQS_FR and V IX_DQS_RF) is measured from the actual cross point of DQS_t, DQS_c
relative to the V DQS,mid of the DQS_t and DQS_c signals.
VDQS,mid is the midpoint of the minimum levels achieved by the transitioning DQS_t
and DQS_c signals, and noted by V DQS_trans. V DQS_trans is the difference between the lowest horizontal tangent above V DQS,mid of the transitioning DQS signals and the highest
horizontal tangent below V DQS,mid of the transitioning DQS signals. A non-monotonic
transitioning signal’s ledge is exempt or not used in determination of a horizontal tangent provided the said ledge occurs within ±35% of the midpoint of either V IH.DIFF.Peak
voltage (DQS_t rising) or V IL.DIFF.Peak voltage (DQS_c rising), as shown in the figure below.
A secondary horizontal tangent resulting from a ring-back transition is also exempt in
determination of a horizontal tangent. That is, a falling transition’s horizontal tangent is
derived from its negative slope to zero slope transition (point A in the figure below), and
a ring-back’s horizontal tangent is derived from its positive slope to zero slope transition (point B in the figure below) and is not a valid horizontal tangent; a rising transition’s horizontal tangent is derived from its positive slope to zero slope transition (point
C in the figure below), and a ring-back’s horizontal tangent derived from its negative
slope to zero slope transition (point D in the figure below) and is not a valid horizontal
tangent.
Figure 223: VIXDQS Definition
Lowest horizontal tanget above VDQS,mid
of the transitioning signals
VIX_DQS,RF
VIX_DQS,FR
VDQS,mid
VIX_DQS,FR
VIX_DQS,RF
B
VDQS_trans
D
VDQS_trans/2
DQS_t, DQS_c: Single-Ended Input Voltages
C
DQS_t
DQS_c
A
Highest horizontal tanget below VDQS,mid
of the transitioning signals
VSSQ
Table 106: Cross Point Voltage For Differential Input Signals DQS
DDR4-1600, 1866, 2133, 2400,
2666, 2933, 3200
Parameter
DQS_t and DQS_c crossing relative to the
midpoint of the DQS_t and DQS_c signal
swings
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Symbol
Min
Max
Unit
Notes
VIX_DQS,ratio
–
25
%
1, 2
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Electrical Characteristics – AC and DC Differential Input Measurement Levels
Table 106: Cross Point Voltage For Differential Input Signals DQS (Continued)
DDR4-1600, 1866, 2133, 2400,
2666, 2933, 3200
Parameter
VDQS,mid to Vcent(midpoint) offset
Symbol
Min
Max
Unit
Notes
VDQS,mid_to_Vcent
–
Note 3
mV
2
1. VIX_DQS,ratio is DQS VIX crossing (VIX_DQS,FR or VIX_DQS,RF) divided by VDQS_trans. VDQS_trans is
the difference between the lowest horizontal tangent above VDQS,midd of the transitioning DQS signals and the highest horizontal tangent below VDQS,mid of the transitioning
DQS signals.
2. VDQS,mid will be similar to the VREFDQ internal setting value (Vcent(midpoint) offset) obtained during VREF Training if the DQS and DQs drivers and paths are matched.
3. The maximum limit shall not exceed the smaller of VIH,diff,DQS minimum limit or 50mV.
Notes:
Slew Rate Definitions for DQS Differential Input Signals
Table 107: DQS Differential Input Slew Rate Definition
Measured
From
To
Defined by
Differential input slew rate for rising edge
Description
V IL,diff,DQS
V IH,diff,DQS
|VIH,diff,DQS - VIL,diff,DQSΔTRdiff
Differential input slew rate for falling edge
V IH,diff,DQS
V IL,diff,DQS
|VIHdiffDQS - VIL,diff,DQSΔTFdiff
1. The differential signal DQS_t, DQS_c must be monotonic between these thresholds.
Note:
DQS_t, DQS_c: Differential Input Voltage
Figure 224: Differential Input Slew Rate and Input Level Definition for DQS_t, DQS_c
VIH,diff,peak
VIH,diff,DQS
0.0V
VIL,diff,DQS
TRdiff
TFdiff
VIL,diff,peak
Table 108: DDR4-1600 through DDR4-2400 Differential Input Slew Rate and Input Levels for DQS_t,
DQS_c
DDR4-1600, 1866, 2133
Parameter
DDR4-2400
Symbol
Min
Max
Min
Max
Unit
Notes
Peak differential input high voltage
VIH,diff,peak
186
VDDQ
160
VDDQ
mV
1
Differential input high voltage
VIH,diff,DQS
136
–
130
–
mV
2, 3
Differential input low voltage
VIL,diff,DQS
–
–136
–
–130
mV
2, 3
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Electrical Characteristics – AC and DC Differential Input Measurement Levels
Table 108: DDR4-1600 through DDR4-2400 Differential Input Slew Rate and Input Levels for DQS_t,
DQS_c (Continued)
DDR4-1600, 1866, 2133
Parameter
Peak differential input low voltage
DQS differential input slew rate
Notes:
DDR4-2400
Symbol
Min
Max
Min
Max
Unit
Notes
VIL,diff,peak
VSSQ
–186
VSSQ
–160
mV
1
SRIdiff
3.0
18
3.0
18
V/ns
4, 5
1. Minimum and maximum limits are relative to single-ended portion and can be exceeded
within allowed overshoot and undershoot limits.
2. Differential signal rising edge from VIL,diff,DQS to VIH,diff,DQS must be monotonic slope.
3. Differential signal falling edge from VIH,diff,DQS to VIL,diff,DQS must be monotonic slope.
4. Differential input slew rate for rising edge from VIL,diff,DQS to VIH,diff,DQS is defined by |
VIL,diff,min - VIH,diff,maxΔTRdiff.
5. Differential input slew rate for falling edge from VIH,diff,DQS to VIL,diff,DQS is defined by |
VIL,diff,min - VIH,diff,maxΔTFdiff.
Table 109: DDR4-2666 through DDR4-3200 Differential Input Slew Rate and Input Levels for DQS_t,
DQS_c
DDR4-2666
Parameter
DDR4-2933
DDR4-3200
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Peak differential input
high voltage
VIH,diff,peak
150
VDDQ
145
VDDQ
140
VDDQ
mV
1
Differential input high
voltage
VIH,diff,DQS
120
–
115
–
110
–
mV
2, 3
Differential input low
voltage
VIL,diff,DQS
–
–120
–
–115
–
–110
mV
2, 3
Peak differential input
low voltage
VIL,diff,peak
VSSQ
–150
VSSQ
–145
VSSQ
–140
mV
1
DQS differential input
slew rate
SRIdiff
3.0
18
3.0
18
3.0
18
V/ns
4, 5
Notes:
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1. Minimum and maximum limits are relative to single-ended portion and can be exceeded
within allowed overshoot and undershoot limits.
2. Differential signal rising edge from VIL,diff,DQS to VIH,diff,DQS must be monotonic slope.
3. Differential signal falling edge from VIH,diff,DQS to VIL,diff,DQS must be monotonic slope.
4. Differential input slew rate for rising edge from VIL,diff,DQS to VIH,diff,DQS is defined by |
VIL,diff,min - VIH,diff,maxΔTRdiff.
5. Differential input slew rate for falling edge from VIH,diff,DQS to VIL,diff,DQS is defined by |
VIL,diff,min - VIH,diff,maxΔTFdiff.
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Electrical Characteristics – Overshoot and Undershoot Specifications
Electrical Characteristics – Overshoot and Undershoot Specifications
Address, Command, and Control Overshoot and Undershoot Specifications
Table 110: ADDR, CMD, CNTL Overshoot and Undershoot/Specifications
DDR41600
Description
DDR41866
DDR42133
DDR42400
DDR42666
DDR4- DDR42933 3200
Unit
Address and control pins (A[17:0], BG[1:0], BA[1:0], CS_n, RAS_n, CAS_n, WE_n, CKE, ODT, C2-0)
Area A: Maximum peak amplitude above VDD
absolute MAX
0.06
0.06
0.06
0.06
0.06
0.06
0.06
V
Area B: Amplitude allowed between VDD and
VDD absolute MAX
0.24
0.24
0.24
0.24
0.24
0.24
0.24
V
Area C: Maximum peak amplitude allowed for
undershoot below VSS
0.30
0.30
0.30
0.30
0.30
0.30
0.30
V
Area A maximum overshoot area per 1tCK
0.0083
0.0071
0.0062
0.0055
0.0055
0.0055
0.0055
V/ns
1tCK
0.2550
0.2185
0.1914
0.1699
0.1699
0.1699
0.1699
V/ns
0.2644
0.2265
0.1984
0.1762
0.1762
0.1762
0.1762
V/ns
Area B maximum overshoot area per
Area C maximum undershoot area per
1tCK
Figure 225: ADDR, CMD, CNTL Overshoot and Undershoot Definition
Absolute MAX overshoot
Volts (V)
VDD absolute MAX
VDD
A
Overshoot area above VDD absolute MAX
B
Overshoot area below VDD absolute MAX
and above VDD MAX
1tCK
VSS
C
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Undershoot area below VSS
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Electrical Characteristics – Overshoot and Undershoot Specifications
Clock Overshoot and Undershoot Specifications
Table 111: CK Overshoot and Undershoot/ Specifications
DDR41600
DDR41866
DDR42133
DDR42400
DDR42666
Area A: Maximum peak amplitude above VDD
absolute MAX
0.06
0.06
0.06
0.06
0.06
0.06
0.06
V
Area B: Amplitude allowed between VDD and
VDD absolute MAX
0.24
0.24
0.24
0.24
0.24
0.24
0.24
V
Area C: Maximum peak amplitude allowed for
undershoot below VSS
0.30
0.30
0.30
0.30
0.30
0.30
0.30
V
Area A maximum overshoot area per 1UI
0.0038
0.0032
0.0028
0.0025
0.0025
0.0025
0.0025
V/ns
Area B maximum overshoot area per 1UI
0.1125
0.0964
0.0844
0.0750
0.0750
0.0750
0.0750
V/ns
Area C maximum undershoot area per 1UI
0.1144
0.0980
0.0858
0.0762
0.0762
0.0762
0.0762
V/ns
Description
DDR4- DDR42933 3200
Unit
CLK_t, CLK_n
Figure 226: CK Overshoot and Undershoot Definition
Absolute MAX overshoot
Volts (V)
VDD absolute MAX
A
Overshoot area above VDD absolute MAX
B
Overshoot area below VDD absolute MAX
and above VDD MAX
VDD
1UI
VSS
C
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Undershoot area below VSS
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Electrical Characteristics – AC and DC Output Measurement
Levels
Data, Strobe, and Mask Overshoot and Undershoot Specifications
Table 112: Data, Strobe, and Mask Overshoot and Undershoot/ Specifications
DDR41600
Description
DDR41866
DDR42133
DDR42400
DDR42666
DDR4- DDR42933 3200
Unit
DQS_t, DQS_n, DQSL_t, DQSL_n, DQSU_t, DQSU_n, DQ[0:15], DM/DBI, UDM/UDBI, LDM/LDBI,
Area A: Maximum peak amplitude above VDDQ
absolute MAX
0.16
0.16
0.16
0.16
0.16
0.16
0.16
V
Area B: Amplitude allowed between VDDQ and
VDDQ absolute MAX
0.24
0.24
0.24
0.24
0.24
0.24
0.24
V
Area C: Maximum peak amplitude allowed for
undershoot below VSSQ
0.30
0.30
0.30
0.30
0.30
0.30
0.30
V
Area D: Maximum peak amplitude below VSSQ
absolute MIN
0.10
0.10
0.10
0.10
0.10
0.10
0.10
V
Area A maximum overshoot area per 1UI
0.0150
0.0129
0.0113
0.0100
0.0129
0.0113
0.0100
V/ns
Area B maximum overshoot area per 1UI
0.1050
0.0900
0.0788
0.0700
0.0900
0.0788
0.0700
V/ns
Area C maximum undershoot area per 1UI
0.1050
0.0900
0.0788
0.0700
0.0900
0.0788
0.0700
V/ns
Area D maximum undershoot area per 1UI
0.0150
0.0129
0.0113
0.0100
0.0129
0.0113
0.0100
V/ns
Figure 227: Data, Strobe, and Mask Overshoot and Undershoot Definition
Absolute MAX overshoot
Volts (V)
VDDQ absolute MAX
A
Overshoot area above VDDQ absolute MAX
B
Overshoot area below VDDQ absolute MAX
and above VDDQ MAX
VDDQ
1UI
VSSQ
C
VSSQ absolute MIN
Undershoot area below VSSQ MIN and
above VSSQ absolute MIN
D
Undershoot area below VSSQ absolute MIN
Absolute MAX undershoot
Electrical Characteristics – AC and DC Output Measurement Levels
Single-Ended Outputs
Table 113: Single-Ended Output Levels
Parameter
Symbol
DDR4-1600 to DDR4-3200
Unit
DC output high measurement level (for IV curve linearity)
VOH(DC)
1.1 × VDDQ
V
DC output mid measurement level (for IV curve linearity)
VOM(DC)
0.8 × VDDQ
V
DC output low measurement level (for IV curve linearity)
VOL(DC)
0.5 × VDDQ
V
AC output high measurement level (for output slew rate)
VOH(AC)
(0.7 + 0.15) × VDDQ
V
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Electrical Characteristics – AC and DC Output Measurement
Levels
Table 113: Single-Ended Output Levels (Continued)
Parameter
AC output low measurement level (for output slew rate)
Symbol
DDR4-1600 to DDR4-3200
Unit
VOL(AC)
(0.7 - 0.15) × VDDQ
V
1. The swing of ±0.15 × VDDQ is based on approximately 50% of the static single-ended
output peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load
of 50Ω to VTT = VDDQ.
Note:
Using the same reference load used for timing measurements, output slew rate for falling and rising edges is defined and measured between V OL(AC) and V OH(AC) for singleended signals.
Table 114: Single-Ended Output Slew Rate Definition
Measured
Description
From
To
Defined by
Single-ended output slew rate for rising edge
VOL(AC)
VOH(AC)
[VOH(AC) - VOL(AC)ΔTRse
Single-ended output slew rate for falling edge
VOH(AC)
VOL(AC)
[VOH(AC) - VOL(AC)ΔTFse
Figure 228: Single-ended Output Slew Rate Definition
TRse
Single-Ended Output Voltage (DQ)
VOH(AC)
VOL(AC)
TFse
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Electrical Characteristics – AC and DC Output Measurement
Levels
Table 115: Single-Ended Output Slew Rate
For RON = RZQ/7
DDR4-1600/ 1866 / 2133 /
2400
Parameter
DDR4-2666
DDR4-2933 / 3200
Symbol
Min
Max
Min
Max
Min
Max
Unit
SRQse
4
9
4
9
4
9
V/ns
Single-ended output
slew rate
1. SR = slew rate; Q = query output; se = single-ended signals
2. In two cases a maximum slew rate of 12V/ns applies for a single DQ signal within a byte
lane:
Notes:
• Case 1 is defined for a single DQ signal within a byte lane that is switching into a certain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ signals in the same byte lane are static (they stay at either HIGH or LOW).
• Case 2 is defined for a single DQ signal within a byte lane that is switching into a certain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ signals in the same byte lane are switching into the opposite direction (from LOW-toHIGH or HIGH-to-LOW, respectively). For the remaining DQ signal switching into the
opposite direction, the standard maximum limit of 9 V/ns applies.
Differential Outputs
Table 116: Differential Output Levels
Parameter
Symbol
DDR4-1600 to DDR4-3200
Unit
AC differential output high measurement level (for output slew
rate)
VOH,diff(AC)
0.3 × VDDQ
V
AC differential output low measurement level (for output slew
rate)
VOL,diff(AC)
–0.3 × VDDQ
V
Note:
1. The swing of ±0.3 × VDDQ is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load of
50Ω to VTT = VDDQ at each differential output.
Using the same reference load used for timing measurements, output slew rate for falling and rising edges is defined and measured between V OL,diff(AC) and V OH,diff(AC) for differential signals.
Table 117: Differential Output Slew Rate Definition
Measured
Description
From
To
Defined by
Differential output slew rate for rising edge
VOL,diff(AC)
VOH,diff(AC)
[VOH,diff(AC) - VOL,diff(AC)ΔTRdiff
Differential output slew rate for falling edge
VOH,diff(AC)
VOL,diff(AC)
[VOH,diff(AC) - VOL,diff(AC)ΔTFdiff
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Electrical Characteristics – AC and DC Output Measurement
Levels
Figure 229: Differential Output Slew Rate Definition
Differential Input Voltage (DQS_t, DQS_c)
TRdiff
VOH,diff(AC)
VOL,diff(AC)
TFdiff
Table 118: Differential Output Slew Rate
For RON = RZQ/7
DDR4-1600 / 1866 /
2133 / 2400
Parameter
Differential output slew
rate
Note:
DDR4-2666
DDR4-2933 / 3200
Symbol
Min
Max
Min
Max
Min
Max
Unit
SRQdiff
8
18
8
18
8
18
V/ns
1. SR = slew rate; Q = query output; diff = differential signals.
Reference Load for AC Timing and Output Slew Rate
The effective reference load of 50Ω to V TT = V DDQ and driver impedance of RZQ/7 for
each output was used in defining the relevant AC timing parameters of the device as
well as output slew rate measurements.
Ron nominal of DQ, DQS_t and DQS_c drivers uses 34 ohms to specify the relevant AC
timing paraeter values of the device. The maximum DC High level of Output signal = 1.0
* VDDQ, the minimum DC Low level of Output signal = { 34 /( 34 + 50 ) } *VDDQ = 0.4*
VDDQ
The nominal reference level of an Output signal can be approximated by the following:
The center of maximum DC High and minimum DC Low = { ( 1 + 0.4 ) / 2 } * VDDQ = 0.7
* VDDQ. The actual reference level of Output signal might vary with driver Ron and reference load tolerances. Thus, the actual reference level or midpoint of an output signal
is at the widest part of the output signal’s eye.
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Electrical Characteristics – AC and DC Output Measurement
Levels
Figure 230: Reference Load For AC Timing and Output Slew Rate
VDDQ
VTT = VDDQ
DQ, DQS_t, DQS_c,
DM, TDQS_t, TDQS_c
CK_t, CK_c
DUT
RTT = 50ȍ
VSSQ
Timing reference point
Connectivity Test Mode Output Levels
Table 119: Connectivity Test Mode Output Levels
Parameter
Symbol
DDR4-1600 to DDR4-3200
Unit
DC output high measurement level (for IV curve linearity)
VOH(DC)
1.1 × VDDQ
V
DC output mid measurement level (for IV curve linearity)
VOM(DC)
0.8 × VDDQ
V
DC output low measurement level (for IV curve linearity)
VOL(DC)
0.5 × VDDQ
V
DC output below measurement level (for IV curve linearity)
VOB(DC)
0.2 × VDDQ
V
AC output high measurement level (for output slew rate)
VOH(AC)
VTT + (0.1 × VDDQ)
V
AC output low measurement level (for output slew rate)
VOL(AC)
VTT - (0.1 × VDDQ)
V
Note:
1. Driver impedance of RZQ/7 and an effective test load of 50Ω to VTT = VDDQ.
Figure 231: Connectivity Test Mode Reference Test Load
VDDQ
CT_Inputs
DUT
DQ, DQS_t, DQS_c,
DQSL_t, DQSL_c, DQSU_t, DQSU_c,
DM, DML, DMH, TDQS_t, TDQS_c
0.5 × VDDQ
RTT = 50ȍ
VSSQ
Timing reference point
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Electrical Characteristics – AC and DC Output Driver Characteristics
Figure 232: Connectivity Test Mode Output Slew Rate Definition
VOH(AC)
VTT
0.5 x VDD
VOL(AC)
TFoutput_CT
TRoutput_CT
Table 120: Connectivity Test Mode Output Slew Rate
DDR4-1600 / 1866 /
2133 / 2400
Parameter
DDR4-2666
DDR4-2933 /
3200
Symbol
Min
Max
Min
Max
Min
Max
Unit
Output signal falling time
TF_output_CT
–
10
–
10
–
10
ns/V
Output signal rising time
TR_output_CT
–
10
–
10
–
10
ns/V
Electrical Characteristics – AC and DC Output Driver Characteristics
Connectivity Test Mode Output Driver Electrical Characteristics
The DDR4 driver supports special values during connectivity test mode. These R ON values are referenced in this section. A functional representation of the output buffer is
shown in the figure below.
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Electrical Characteristics – AC and DC Output Driver Characteristics
Figure 233: Output Driver During Connectivity Test Mode
Chip in drive mode
Output driver
VDDQ
IPU_CT
To
other
circuitry
like
RCV,
...
RONPU_CT
DQ
RONPD_CT
IPD_CT
IOUT
VOUT
VSSQ
The output driver impedance, RON, is determined by the value of the external reference
resistor RZQ as follows: RON = RZQ/7. This targets 34Ω with nominal RZQ Ω; however,
connectivity test mode uses uncalibrated drivers and only a maximum target is defined.
Mismatch between pull up and pull down is undefined.
The individual pull-up and pull-down resistors (RONPu_CT and RONPd_CT) are defined as
follows:
RONPu_CT when RONPd_CT is off:
52138B&7 9''49287
,287
RONPD_CT when RONPU_CT is off:
5213'B&7 09005aef84af6dd0
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,287
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Electrical Characteristics – AC and DC Output Driver Characteristics
Table 121: Output Driver Electrical Characteristics During Connectivity Test Mode
Assumes RZQ Ω; ZQ calibration not required
RON,nom_CT
Resistor
RONPD_CT
Ω
RONPU_CT
VOUT
Min
Nom
Max
Unit
VOB(DC) = 0.2 × VDDQ
N/A
N/A
1.9
RZQ/7
VOL(DC) = 0.5 × VDDQ
N/A
N/A
2.0
RZQ/7
VOM(DC) = 0.8 × VDDQ
N/A
N/A
2.2
RZQ/7
VOH(DC) = 1.1 × VDDQ
N/A
N/A
2.5
RZQ/7
VOB(DC) = 0.2 × VDDQ
N/A
N/A
1.9
RZQ/7
VOL(DC) = 0.5 × VDDQ
N/A
N/A
2.0
RZQ/7
VOM(DC) = 0.8 × VDDQ
N/A
N/A
2.2
RZQ/7
VOH(DC) = 1.1 × VDDQ
N/A
N/A
2.5
RZQ/7
Output Driver Electrical Characteristics
The DDR4 driver supports two RON values. These R ON values are referred to as strong
mode (low RONΩ) and weak mode (high RONΩ). A functional representation of
the output buffer is shown in the figure below.
Figure 234: Output Driver: Definition of Voltages and Currents
Chip in drive mode
Output driver
VDDQ
IPU
To
other
circuitry
like
RCV,
...
RONPU
DQ
IOUT
RONPD
VOUT
IPD
VSSQ
The output driver impedance, RON, is determined by the value of the external reference
resistor RZQ as follows: RON(34) = RZQ/7, or RON(48) = RZQ/5. This provides either a nominal 34.3Ω ±10% or 48Ω ±10% with nominal RZQ Ω
The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows:
RONPu when RONPd is off:
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Electrical Characteristics – AC and DC Output Driver Characteristics
RONPU =
VDDQ - VOUT
IOUT
RONPD when RONPU is off:
RONPD =
VOUT
IOUT
Table 122: Strong Mode (34Ω
Ω) Output Driver Electrical Characteristics
Assumes RZQ Ω; Entire operating temperature range after proper ZQ calibration
RON,nom
Resistor
VOUT
Min
Nom
RON34PD
Ω
RON34PU
Max
Unit
Notes
1.1
RZQ/7
1, 2, 3
VOL(DC) = 0.5 × VDDQ
0.8
1.0
VOM(DC) = 0.8 × VDDQ
0.9
1.0
1.1
RZQ/7
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.9
1.0
1.25
RZQ/7
1, 2, 3
VOL(DC) = 0.5 × VDDQ
0.9
1.0
1.25
RZQ/7
1, 2, 3
VOM(DC) = 0.8 × VDDQ
0.9
1.0
1.1
RZQ/7
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.8
1.0
1.1
RZQ/7
1, 2, 3
Mismatch between DQ to DQ within
byte variation pull-up, MMPUdd
VOM(DC) = 0.8 × VDDQ
–10
–
10
%
1, 2, 3, 4,
5
Mismatch between DQ to DQ within
byte variation pull-down, MMPDdd
VOM(DC) = 0.8 × VDDQ
–
–
10
%
1, 2, 3, 4,
6, 7
Mismatch between pull-up and pulldown, MMPUPD
VOM(DC) = 0.8 × VDDQ
–
–
10
%
1, 2, 3, 4,
6, 7
Notes:
1. The tolerance limits are specified after calibration with stable voltage and temperature.
For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity.
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ =
VSS.
3. Micron recommends calibrating pull-down and pull-up output driver impedances at 0.8
× VDDQ. Other calibration schemes may be used to achieve the linearity specification
shown above; for example, calibration at 0.5 × VDDQ and 1.1 VDDQ.
4. DQ-to-DQ mismatch within byte variation for a given component including DQS_t and
DQS_c (characterized).
5. Measurement definition for mismatch between pull-up and pull-down, MMPUPD:
Measure both RONPU and RONPD at 0.8 × VDDQ separately; RON,nom is the nominal RON value:
MMPUPD =
RONPU - RONPD
× 100
RON,nom
6. RON variance range ratio to RON nominal value in a given component, including DQS_t
and DQS_c:
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Electrical Characteristics – AC and DC Output Driver Characteristics
MMPUDD =
MMPDDD =
RONPU,max - RONPU,min
RON,nom
RONPD,max - RONPD,min
RON,nom
× 100
× 100
7. The lower and upper bytes of a x16 are each treated on a per byte basis.
8. For IT and AT devices, the minimum values are derated by 9% when the device operates
between –40°C and 0°C (TC).
Table 123: Weak Mode (48Ω
Ω) Output Driver Electrical Characteristics
Assumes RZQ Ω; Entire operating temperature range after proper ZQ calibration
RON,nom
Resistor
VOUT
Min
Nom
Ω
Max
Unit
Notes
VOL(DC) = 0.5 × VDDQ
0.8
1.0
1.1
RZQ/5
1, 2, 3
VOM(DC) = 0.8 × VDDQ
0.9
1.0
1.1
RZQ/5
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.9
1.0
1.25
RZQ/5
1, 2, 3
VOL(DC) = 0.5 × VDDQ
0.9
1.0
1.25
RZQ/5
1, 2, 3
VOM(DC) = 0.8 × VDDQ
0.9
1.0
1.1
RZQ/5
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.8
1.0
1.1
RZQ/5
1, 2, 3
Mismatch between DQ to DQ
within byte variation pull-up,
MMPUdd
VOM(DC) = 0.8 × VDDQ
-10
–
10
%
1, 2, 3, 4, 5
Mismatch between DQ to DQ
within byte variation pull-down,
MMPDdd
VOM(DC) = 0.8 × VDDQ
–
–
10
%
1, 2, 3, 4,
6, 7
Mismatch between pull-up and
pull-down, MMPUPD
VOM(DC) = 0.8 × VDDQ
–
–
10
%
1, 2, 3, 4,
6, 7
RON34PD
RON34PU
Notes:
1. The tolerance limits are specified after calibration with stable voltage and temperature.
For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity.
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ =
VSS.
3. Micron recommends calibrating pull-down and pull-up output driver impedances at 0.8
× VDDQ. Other calibration schemes may be used to achieve the linearity specification
shown above; for example, calibration at 0.5 × VDDQ and 1.1 VDDQ.
4. DQ-to-DQ mismatch within byte variation for a given component including DQS_t and
DQS_c (characterized).
5. Measurement definition for mismatch between pull-up and pull-down, MMPUPD:
Measure both RONPU and RONPD at 0.8 × VDDQ separately; RON,nom is the nominal RON value:
MMPUPD =
RONPU - RONPD
× 100
RON,nom
6. RON variance range ratio to RON nominal value in a given component, including DQS_t
and DQS_c:
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Electrical Characteristics – AC and DC Output Driver Characteristics
MMPUDD =
MMPDDD =
RONPU,max - RONPU,min
RON,nom
RONPD,max - RONPD,min
RON,nom
× 100
× 100
7. The lower and upper bytes of a x16 are each treated on a per byte basis.
8. For IT and AT devices, the minimum values are derated by 9% when the device operates
between –40°C and 0°C (TC).
Output Driver Temperature and Voltage Sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to the equations and tables below.
ΔT = T - T(@calibration); ΔV = V DDQ - V DDQ(@ calibration); V DD = V DDQ
Table 124: Output Driver Sensitivity Definitions
Symbol
Min
Max
Unit
RONPU@ VOH(DC)
0.6 - dRONdTH × |ΔT| - dRONdVH × |ΔV|
1.1 _ dRONdTH × |ΔT| + dRONdVH × |ΔV|
RZQ/6
RON@ VOM(DC)
0.9 - dRONdTM × |ΔT| - dRONdVM × |ΔV|
1.1 + dRONdTM × |ΔT| + dRONdVM × |ΔV|
RZQ/6
RONPD@ VOL(DC)
0.6 - dRONdTL × |ΔT| - dRONdVL × |ΔV|
1.1 + dRONdTL × |ΔT| + dRONdVL × |ΔV|
RZQ/6
Table 125: Output Driver Voltage and Temperature Sensitivity
Voltage and Temperature Range
Symbol
Min
Max
Unit
dRONdTM
0
1.5
%/°C
dRONdVM
0
0.15
%/mV
dRONdTL
0
1.5
%/°C
dRONdVL
0
0.15
%/mV
dRONdTH
0
1.5
%/°C
dRONdVM
0
0.15
%/mV
Alert Driver
A functional representation of the alert output buffer is shown in the figure below. Output driver impedance, RON, is defined as follows.
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Electrical Characteristics – On-Die Termination Characteristics
Figure 235: Alert Driver
Alert driver
'5$0
Alert
RONPD
IOUT
IPD
VOUT
VSSQ
RONPD when RONPU is off:
VOUT
RONPD =
IOUT
Table 126: Alert Driver Voltage
RON,nom
Register
N/A
RONPD
Note:
VOUT
Min
Nom
Max
Unit
VOL(DC) = 0.1 × VDDQ
0.3
N/A
1.2
RZQ/7
VOM(DC) = 0.8 × VDDQ
0.4
N/A
1.12
RZQ/7
VOH(DC) = 1.1 × VDDQ
0.4
N/A
1.4
RZQ/7
1. VDDQ voltage is at VDDQ(DC).
Electrical Characteristics – On-Die Termination Characteristics
ODT Levels and I-V Characteristics
On-die termination (ODT) effective resistance settings are defined and can be selected
by any or all of the following options:
• MR1[10:8] (RTT(NOM)): Disable, 240 ohms, 120 ohms, 80 ohms, 60 ohms, 48 ohms, 40
ohms, and 34 ohms.
• MR2[11:9] (RTT(WR)): Disable, 240 ohms,120 ohms, and 80 ohms.
• MR5[8:6] (RTT(Park)): Disable, 240 ohms, 120 ohms, 80 ohms, 60 ohms, 48 ohms, 40
ohms, and 34 ohms.
ODT is applied to the following inputs:
• x4: DQ, DM_n, DQS_t, and DQS_c inputs.
• x8: DQ, DM_n, DQS_t, DQS_c, TDQS_t, and TDQS_c inputs.
• x16: DQ, LDM_n, UDM_n, LDQS_t, LDQS_c, UDQS_t, and UDQS_c inputs.
A functional representation of ODT is shown in the figure below.
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Electrical Characteristics – On-Die Termination Characteristics
Figure 236: ODT Definition of Voltages and Currents
Chip in termination mode
ODT
To other
circuitry
like RCV,
...
VDDQ
RTT
DQ
IOUT
VOUT
VSSQ
Table 127: ODT DC Characteristics
RTT
VOUT
Min
Nom
Max
Unit
Notes
240 ohm
VOL(DC) = 0.5 × VDDQ
0.9
1
1.25
RZQ
1, 2, 3
120 ohm
80 ohm
60 ohm
48 ohm
40 ohm
34 ohm
DQ-to-DQ mismatch
within byte
VOM(DC) = 0.8 × VDDQ
0.9
1
1.1
RZQ
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.8
1
1.1
RZQ
1, 2, 3
VOL(DC) = 0.5 × VDDQ
0.9
1
1.25
RZQ/2
1, 2, 3
VOM(DC) = 0.8 × VDDQ
0.9
1
1.1
RZQ/2
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.8
1
1.1
RZQ/2
1, 2, 3
VOL(DC) = 0.5 × VDDQ
0.9
1
1.25
RZQ/3
1, 2, 3
VOM(DC) = 0.8 × VDDQ
0.9
1
1.1
RZQ/3
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.8
1
1.1
RZQ/3
1, 2, 3
VOL(DC) = 0.5 × VDDQ
0.9
1
1.25
RZQ/4
1, 2, 3
VOM(DC) = 0.8 × VDDQ
0.9
1
1.1
RZQ/4
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.8
1
1.1
RZQ/4
1, 2, 3
VOL(DC) = 0.5 × VDDQ
0.9
1
1.25
RZQ/5
1, 2, 3
VOM(DC) = 0.8 × VDDQ
0.9
1
1.1
RZQ/5
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.8
1
1.1
RZQ/5
1, 2, 3
VOL(DC) = 0.5 × VDDQ
0.9
1
1.25
RZQ/6
1, 2, 3
VOM(DC) = 0.8 × VDDQ
0.9
1
1.1
RZQ/6
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.8
1
1.1
RZQ/6
1, 2, 3
VOL(DC) = 0.5 × VDDQ
0.9
1
1.25
RZQ/7
1, 2, 3
VOM(DC) = 0.8 × VDDQ
0.9
1
1.1
RZQ/7
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.8
1
1.1
RZQ/7
1, 2, 3
VOM(DC) = 0.8 × VDDQ
0
–
10
%
1, 2, 4, 5, 6
Notes:
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1. The tolerance limits are specified after calibration to 240 ohm ±1% resistor with stable
voltage and temperature. For the behavior of the tolerance limits if temperature or
voltage changes after calibration, see ODT Temperature and Voltage Sensitivity.
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Electrical Characteristics – On-Die Termination Characteristics
2. Micron recommends calibrating pull-up ODT resistors at 0.8 × VDDQ. Other calibration
schemes may be used to achieve the linearity specification shown here.
3. The tolerance limits are specified under the condition that VDDQ = VDD and VSSQ = VSS.
4. The DQ-to-DQ mismatch within byte variation for a given component including DQS_t
and DQS_c.
5. RTT variance range ratio to RTT nominal value in a given component, including DQS_t
and DQS_c.
DQ-to-DQ mismatch =
RTT(MAX) - RTT(MIN)
RTT(NOM)
× 100
6. DQ-to-DQ mismatch for a x16 device is treated as two separate bytes.
7. For IT, AT, and UT devices, the minimum values are derated by 9% when the device operates between –40°C and 0°C (TC).
ODT Temperature and Voltage Sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to the following equations and tables.
ΔT = T - T(@ calibration); ΔV = V DDQ - V DDQ(@ calibration); V DD = V DDQ
Table 128: ODT Sensitivity Definitions
Parameter
Min
Max
Unit
RTT@
0.9 - dRTTdT × |ΔT| - dRTTdV × |ΔV|
1.6 + dRTTdTH × |ΔT| + dRTTdVH × |ΔV|
RZQ/n
Table 129: ODT Voltage and Temperature Sensitivity
Parameter
Min
Max
Unit
dRTTdT
0
1.5
%/°C
dRTTdV
0
0.15
%/mV
ODT Timing Definitions
The reference load for ODT timings is different than the reference load used for timing
measurements.
Figure 237: ODT Timing Reference Load
VDDQ
DQ, DQS_t, DQS_c,
DM, TDQS_t, TDQS_c
CK_t, CK_c
DUT
VSSQ
RTT = 50ȍ
VTT = VSSQ
Timing reference point
ODT Timing Definitions and Waveforms
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4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics – On-Die Termination Characteristics
Definitions for tADC, tAONAS, and tAOFAS are provided in the Table 130 (page 302) and
shown in Figure 238 (page 303) and Figure 240 (page 304). Measurement reference settings are provided in the subsequent Table 131 (page 302).
The tADC for the dynamic ODT case and read disable ODT cases are represented by
tADC of Direct ODT Control case.
Table 130: ODT Timing Definitions
Parameter
tADC
Begin Point Definition
End Point Definition
Figure
Rising edge of CK_t, CK_c defined by the end point of
DODTLoff
Extrapolated point at VRTT,nom
Figure 238
(page 303)
Rising edge of CK_t, CK_c defined by the end point of
DODTLon
Extrapolated point at VSSQ
Figure 238
(page 303)
Rising edge of CK_t, CK_c defined by the end point of
ODTLcnw
Extrapolated point at VRTT,nom
Figure 239
(page 303)
Rising edge of CK_t, CK_c defined by the end point of
ODTLcwn4 or ODTLcwn8
Extrapolated point at VSSQ
Figure 239
(page 303)
tAONAS
Rising edge of CK_t, CK_c with ODT being first registered
HIGH
Extrapolated point at VSSQ
Figure 240
(page 304)
tAOFAS
Rising edge of CK_t, CK_c with ODT being first registered
LOW
Extrapolated point at VRTT,nom
Figure 240
(page 304)
Table 131: Reference Settings for ODT Timing Measurements
Measure
Parameter
RTT(Park)
RTT(NOM)
RTT(WR)
VSW1
VSW2
Note
tADC
Disable
RZQΩ
–
0.20V
0.40V
1, 2, 4
–
RZQΩ
High-Z
0.20V
0.40V
1, 3, 5
tAONAS
Disable
RZQΩ
–
0.20V
0.40V
1, 2, 6
tAOFAS
Disable
RZQΩ
–
0.20V
0.40V
1, 2, 6
Notes:
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
1. MR settings are as follows: MR1 has A10 = 1, A9 = 1, A8 = 1 for RTT(NOM) setting; MR5 has
A8 = 0, A7 = 0, A6 = 0 for RTT(Park) setting; and MR2 has A11 = 0, A10 = 1, A9 = 1 for
RTT(WR) setting.
2. ODT state change is controlled by ODT pin.
3. ODT state change is controlled by a WRITE command.
4. Refer to Figure 238 (page 303).
5. Refer to Figure 239 (page 303).
6. Refer to Figure 240 (page 304).
302
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4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics – On-Die Termination Characteristics
Figure 238: tADC Definition with Direct ODT Control
DODTLoff
Begin point: Rising edge
of CK_t, CK_c defined
by the end point of
DODTLoff
DODTLon
Begin point: Rising edge
of CK_t, CK_c defined
by the end point of
DODTLon
CK_c
CK_t
tADC
VRTT,nom
tADC
End point: Extrapolated
point at VRTT,nom
VRTT,nom
Vsw2
DQ, DM
DQS_t, DQS_c
TDQS_t, TDQS_c
Vsw1
VSSQ
VSSQ
End point: Extrapolated
point at VSSQ
Figure 239: tADC Definition with Dynamic ODT Control
ODTLcnw
Begin point: Rising edge
of CK_t, CK_c defined
by the end point of
ODTLcnw
ODTLcnw4/8
Begin point: Rising edge
of CK_t, CK_c defined
by the end point of
ODTLcnw4 or ODTLcnw8
CK_c
CK_t
tADC
VRTT,nom
tADC
End point: Extrapolated
point at VRTT,nom
Vsw2
DQ, DM
DQS_t, DQS_c
TDQS_t, TDQS_c
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VRTT,nom
Vsw1
VSSQ
303
VSSQ
End point: Extrapolated
point at VSSQ
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4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics – On-Die Termination Characteristics
Figure 240: tAOFAS and tAONAS Definitions
Rising edge of CK_t, CK_c
with ODT being first
registered LOW
Rising edge of CK_t, CK_c
with ODT being first
registered HIGH
CK_c
CK_t
tAOFAS
VRTT,nom
tAONAS
End point: Extrapolated
point at VRTT_NOM
Vsw2
DQ, DM
DQS_t, DQS_c
TDQS_t, TDQS_c
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VRTT,nom
Vsw1
VSSQ
304
VSSQ
End point: Extrapolated
point at VSSQ
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4Gb: x4, x8, x16 DDR4 SDRAM
DRAM Package Electrical Specifications
DRAM Package Electrical Specifications
Table 132: DRAM Package Electrical Specifications for x4 and x8 Devices
1600/1866/2133/
2400/2666
Parameter
Input/
output
DQS_t,
DQS_c
Input CTRL
pins
Input CMD
ADD pins
CK_t, CK_c
2933
3200
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
ZIO
45
85
48
85
48
85
ohm
1, 2, 4
TdIO
14
42
14
40
14
40
ps
1, 3, 4
Lpkg
LIO
–
3.3
–
3.3
–
3.3
nH
Cpkg
CIO
–
0.78
–
0.78
–
0.78
pF
Zpkg
Package delay
ZIO DQS
45
85
48
85
48
85
ohm
1, 2
Package delay
TdIO DQS
14
42
14
40
14
40
ps
1, 3
Delta Zpkg
DZIO DQS
–
10
–
10
–
10
ohm
1, 2, 6
Delta delay
DTdIO DQS
–
5
–
5
–
5
ps
1, 3, 6
Zpkg
Lpkg
LIO DQS
–
3.3
–
3.3
–
3.3
nH
Cpkg
CIO DQS
–
0.78
–
0.78
–
0.78
pF
Zpkg
ZI CTRL
50
90
50
90
50
90
ohm
1, 2, 8
TdI CTRL
14
42
14
40
14
40
ps
1, 3, 8
Package delay
Lpkg
LI CTRL
–
3.4
–
3.4
–
3.4
nH
Cpkg
CI CTRL
–
0.7
–
0.7
–
0.7
pF
Zpkg
ZI ADD CMD
50
90
50
90
50
90
ohm
1, 2, 7
TdI ADD CMD
14
45
14
40
14
40
ps
1, 3, 7
Package delay
Lpkg
LI ADD CMD
–
3.6
–
3.6
–
3.6
nH
Cpkg
CI ADD CMD
–
0.74
–
0.74
–
0.74
pF
Zpkg
ZCK
50
90
50
90
50
90
ohm
1, 2
TdCK
14
42
14
42
14
42
ps
1, 3
Delta Zpkg
DZDCK
–
10
–
10
–
10
ohm
1, 2, 5
Delta delay
DTdDCK
–
5
–
5
–
5
ps
1, 3, 5
Lpkg
LI CLK
–
3.4
–
3.4
–
3.4
nH
Cpkg
CI CLK
–
0.7
–
0.7
–
0.7
pF
Package delay
ZQ Zpkg
ZO ZQ
–
100
–
100
–
100
ohm
1, 2
ZQ delay
TdO ZQ
20
55
20
55
20
55
ps
1, 3
ALERT Zpkg
ZO ALERT
40
100
40
100
40
100
ohm
1, 2
ALERT delay
TdO ALERT
20
55
20
55
20
55
ps
1, 3
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
1. The package parasitic (L and C) are validated using package only samples. The capacitance is measured with VDD, VDDQ, VSS, and VSSQ shorted with all other signal pins floating. The inductance is measured with VDD, VDDQ, VSS, and VSSQ shorted and all other signal pins shorted at the die, not pin, side.
2. Package-only impedance (Zpkg) is calculated based on the Lpkg and Cpkg total for a
given pin where: Zpkg (total per pin) = SQRT (Lpkg/Cpkg).
3. Package-only delay (Tpkg) is calculated based on Lpkg and Cpkg total for a given pin
where: Tdpkg (total per pin) = SQRT (Lpkg × Cpkg).
4. ZIO and TdIO apply to DQ, DM, DQS_c, DQS_t, TDQS_t, and TDQS_c.
305
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4Gb: x4, x8, x16 DDR4 SDRAM
DRAM Package Electrical Specifications
5. Absolute value of ZCK_t, ZCK_c for impedance (Z) or absolute value of TdCK_t, TdCK_c
for delay (Td).
6. Absolute value of ZIO (DQS_t), ZIO (DQS_c) for impedance (Z) or absolute value of TdIO
(DQS_t), TdIO (DQS_c) for delay (Td).
7. ZI ADD CMD and TdI ADD CMD apply to A[17:0], BA[1:0], BG[1:0], RAS_n CAS_n, and WE_n.
8. ZI CTRL and TdI CTRL apply to ODT, CS_n, and CKE.
9. Package implementations will meet specification if the Zpkg and package delay fall
within the ranges shown, and the maximum Lpkg and Cpkg do not exceed the maximum values shown.
10. It is assumed that Lpkg can be approximated as Lpkg = ZO × Td.
11. It is assumed that Cpkg can be approximated as Cpkg = Td/ZO.
Table 133: DRAM Package Electrical Specifications for x16 Devices
1600/1866/2133/
2400/2666
Parameter
Input/
output
DQSL_t/
DQSL_c/
DQSU_t/
DQSU_c
2933
3200
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
ZIO
45
85
45
85
45
85
ohm
1, 2, 4
TdIO
14
45
14
45
14
45
ps
1, 3, 4
Lpkg
LIO
–
3.4
–
3.4
–
3.4
nH
Cpkg
CIO
–
0.82
–
0.82
–
0.82
pF
Zpkg
ZIO DQS
45
85
45
85
45
85
ohm
1, 2
TdIO DQS
14
45
14
45
14
45
ps
1, 3
Zpkg
Package delay
Package delay
Lpkg
LIO DQS
–
3.4
–
3.4
–
3.4
nH
Cpkg
CIO DQS
–
0.82
–
0.82
–
0.82
pF
DQSL_t/
DQSL_c,
DQSU_t/
DQSU_c,
Delta Zpkg
DZIO DQS
–
10
–
10
–
10
ohm
1, 2, 6
Delta delay
DTdIO DQS
–
5
–
5
–
5
ps
1, 3, 6
Input CTRL
pins
Zpkg
ZI CTRL
50
90
50
90
50
90
ohm
1, 2, 8
1, 3, 8
Input CMD
ADD pins
CK_t, CK_c
TdI CTRL
14
42
14
42
14
42
ps
Lpkg
LI CTRL
–
3.4
–
3.4
–
3.4
nH
Cpkg
CI CTRL
–
0.7
–
0.7
–
0.7
pF
Zpkg
ZI ADD CMD
50
90
50
90
50
90
ohm
1, 2, 7
1, 3, 7
Package delay
TdI ADD CMD
14
52
14
52
14
52
ps
Lpkg
LI ADD CMD
–
3.9
–
3.9
–
3.9
nH
Cpkg
CI ADD CMD
–
0.86
–
0.86
–
0.86
pF
Zpkg
ZCK
50
90
50
90
50
90
ohm
Package delay
TdCK
14
42
14
42
14
42
ps
1, 3
Delta Zpkg
DZDCK
–
10
–
10
–
10
ohm
1, 2, 5
Delta delay
DTdDCK
–
5
–
5
–
5
ps
1, 3, 5
Lpkg
LI CLK
–
3.4
–
3.4
–
3.4
nH
Cpkg
Package delay
Input CLK
1, 2
CI CLK
–
0.7
–
0.7
–
0.7
pF
ZQ Zpkg
ZO ZQ
–
100
–
100
–
100
ohm
1, 2
ZQ delay
TdO ZQ
20
90
20
90
20
90
ps
1, 3
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
DRAM Package Electrical Specifications
Table 133: DRAM Package Electrical Specifications for x16 Devices (Continued)
1600/1866/2133/
2400/2666
2933
3200
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
ALERT Zpkg
ZO ALERT
40
100
40
100
40
100
ohm
1, 2
ALERT delay
TdO ALERT
20
55
20
55
20
55
ps
1, 3
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
1. The package parasitic (L and C) are validated using package only samples. The capacitance is measured with VDD, VDDQ, VSS, and VSSQ shorted with all other signal pins floating. The inductance is measured with VDD, VDDQ, VSS, and VSSQ shorted and all other signal pins shorted at the die, not pin, side.
2. Package-only impedance (Zpkg) is calculated based on the Lpkg and Cpkg total for a
given pin where: Zpkg (total per pin) = SQRT (Lpkg/Cpkg).
3. Package-only delay (Tpkg) is calculated based on Lpkg and Cpkg total for a given pin
where: Tdpkg (total per pin) = SQRT (Lpkg × Cpkg).
4. ZIO and TdIO apply to DQ, DM, DQS_c, DQS_t, TDQS_t, and TDQS_c.
5. Absolute value of ZCK_t, ZCK_c for impedance (Z) or absolute value of TdCK_t, TdCK_c
for delay (Td).
6. Absolute value of ZIO (DQS_t), ZIO (DQS_c) for impedance (Z) or absolute value of TdIO
(DQS_t), TdIO (DQS_c) for delay (Td).
7. ZI ADD CMD and TdI ADD CMD apply to A[17:0], BA[1:0], BG[1:0], RAS_n CAS_n, and WE_n.
8. ZI CTRL and TdI CTRL apply to ODT, CS_n, and CKE.
9. Package implementations will meet specification if the Zpkg and package delay fall
within the ranges shown, and the maximum Lpkg and Cpkg do not exceed the maximum values shown.
10. It is assumed that Lpkg can be approximated as Lpkg = ZO × Td.
11. It is assumed that Cpkg can be approximated as Cpkg = Td/ZO.
307
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4Gb: x4, x8, x16 DDR4 SDRAM
DRAM Package Electrical Specifications
Table 134: Pad Input/Output Capacitance
DDR4-1600,
1866, 2133
DDR4-2400,
2666
DDR4-2933
DDR4-3200
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Input/output capacitance:
DQ, DM, DQS_t, DQS_c,
TDQS_t, TDQS_c
CIO
0.55
1.4
0.55
1.15
0.55
1.00
0.55
1.00
pF
1, 2, 3
Input capacitance: CK_t and
CK_c
CCK
0.2
0.8
0.2
0.7
0.2
0.7
0.2
0.7
pF
1, 2, 3,
4
Input capacitance delta: CK_t
and CK_c
CDCK
0
0.05
0
0.05
0
0.05
0
0.05
pF
1, 2, 3,
5
Input/output capacitance delta: DQS_t and DQS_c
CDDQS
0
0.05
0
0.05
0
0.05
0
0.05
pF
1, 2, 3
Input capacitance: CTRL,
ADD, CMD input-only pins
CI
0.2
0.8
0.2
0.7
0.2
0.6
0.2
0.55
pF
1, 2, 3,
6
Input capacitance delta: All
CTRL input-only pins
CDI_CTRL
–0.1
0.1
–0.1
0.1
–0.1
0.1
–0.1
0.1
pF
1, 2, 3,
7
Input capacitance delta: All
ADD/CMD input-only pins
CDI_ADD_CM
–0.1
0.1
–0.1
0.1
–0.1
0.1
–0.1
0.1
pF
1, 2, 3,
8, 9
CDIO
–0.1
0.1
–0.1
0.1
–0.1
0.1
–0.1
0.1
pF
1, 2, 10,
11
CALERT
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
pF
1, 2, 2,
3
Input/output capacitance: ZQ
pin
CZQ
–
2.3
–
2.3
–
2.3
–
2.3
pF
1, 2, 3,
12
Input/output capacitance:
TEN pin
CTEN
0.2
2.3
0.2
2.3
0.2
2.3
0.2
2.3
pF
1, 2, 3,
13
Parameter
D
Input/output capacitance delta: DQ, DM, DQS_t, DQS_c,
TDQS_t, TDQS_c
Input/output capacitance:
ALERT pin
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
1. Although the DM, TDQS_t, and TDQS_c pins have different functions, the loading
matches DQ and DQS.
2. This parameter is not subject to a production test; it is verified by design and characterization. The capacitance is measured according to the JEP147 specification, “Procedure
for Measuring Input Capacitance Using a Vector Network Analyzer (VNA),” with VDD,
VDDQ, VSS, and VSSQ applied and all other pins floating (except the pin under test, CKE,
RESET_n and ODT, as necessary). VDD = VDDQ = 1.5V, VBIAS = VDD/2 and on-die termination
off. Measured data is rounded using industry standard half-rounded up methodology to
the nearest hundredth of the MSB.
3. This parameter applies to monolithic die, obtained by de-embedding the package L and
C parasitics.
4. CDIO = CIO(DQ, DM) - 0.5 × (CIO(DQS_t) + CIO(DQS_c)).
5. Absolute value of CIO (DQS_t), CIO (DQS_c)
6. Absolute value of CCK_t, CCK_c
7. CI applies to ODT, CS_n, CKE, A[15:0], BA[1:0], RAS_n, CAS_n, and WE_n.
8. CDI_CTRL applies to ODT, CS_n, and CKE.
9. CDI_CTRL = CI(CTRL) - 0.5 × (CI(CLK_t) + CI(CLK_c)).
10. CDI_ADD_CMD applies to A[15:0], BA1:0], RAS_n, CAS_n and WE_n.
308
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Thermal Characteristics
11. CDI_ADD_CMD = CI(ADD_CMD) - 0.5 × (CI(CLK_t) + CI(CLK_c)).
12. Maximum external load capacitance on ZQ pin: 5pF.
13. Only applicable if TEN pin does not have an internal pull-up.
Thermal Characteristics
Table 135: Thermal Characteristics
Parameter/Condition
Operating case temperature:
Commercial
Value
Units
Symbol
Notes
0 to +85
°C
TC
1, 2, 3
0 to +95
°C
TC
1, 2, 3, 4
Operating case temperature:
Industrial
–40 to +85
°C
TC
1, 2, 3
–40 to +95
°C
TC
1, 2, 3, 4
Operating case temperature:
Automotive
–40 to +85
°C
TC
1, 2, 3
78-ball “HX”
REV A
96-ball “HA”
78-ball “RH”
REV B
96-ball “GE”
78-ball
REV C
96-ball
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
–40 to +105
°C
TC
1, 2, 3, 4
Junction-to-case (TOP)
4.4
°C/W
ΘJC
5
Junction-to-board
12.7
°C/W
ΘJB
Junction-to-case (TOP)
3.6
°C/W
ΘJC
Junction-to-board
12.0
°C/W
ΘJB
Junction-to-case (TOP)
7.7
°C/W
ΘJC
Junction-to-board
20.9
°C/W
ΘJB
Junction-to-case (TOP)
5.0
°C/W
ΘJC
Junction-to-board
19.0
°C/W
ΘJB
Junction-to-case (TOP)
TBD
°C/W
ΘJC
Junction-to-board
TBD
°C/W
ΘJB
Junction-to-case (TOP)
TBD
°C/W
ΘJC
Junction-to-board
TBD
°C/W
ΘJB
5
5
5
5
5
1. MAX operating case temperature. TC is measured in the center of the package.
2. A thermal solution must be designed to ensure the DRAM device does not exceed the
maximum TC during operation.
3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation.
4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9μs
interval refresh rate.
5. The thermal resistance data is based off of a number of samples from multiple lots and
should be viewed as a typical number.
309
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Current Specifications – Measurement Conditions
Figure 241: Thermal Measurement Point
TC test point
(L/2)
L
(W/2)
W
Current Specifications – Measurement Conditions
IDD, IPP, and IDDQ Measurement Conditions
IDD, IPP, and IDDQ measurement conditions, such as test load and patterns, are defined
in this section.
• IDD currents (IDD0, IDD1, IDD2N, IDD2NT, IDD2P, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5R,
IDD6N, IDD6E, IDD6R, IDD7, and IDD8) are measured as time-averaged currents with all
VDD balls of the device under test grouped together. IPP and IDDQ currents are not included in IDD currents.
• IPP currents are IPPSB for standby cases (IDD2N, IDD2NT, IDD2P, IDD2Q, IDD3N, IDD3P, IDD8);
IPP0 for active cases (IDD0,IDD1, IDD4R, IDD4W); IPP5R and IPP6N for self refresh cases
(IDD6N, IDD6E, IDD6R), and IPP7. These have the same definitions as the I DD currents referenced but are measured on the V PP supply.
• IDDQ currents (IDDQ2NT) are measured as time-averaged currents with V DDQ balls of
the device under test grouped together. IDD current is not included in IDDQ currents.
Note: IDDQ values cannot be directly used to calculate the I/O power of the device. They
can be used to support correlation of simulated I/O power to actual I/O power. In
DRAM module application, IDDQ cannot be measured separately because V DD and V DDQ
are using a merged-power layer in the module PCB.
The following definitions apply for IDD, IDDP and IDDQ measurements.
“0” and “LOW” are defined as V IN ≤VIL(AC)max
“1” and “HIGH” are defined as V IN ≥VIH(AC)min
“Midlevel” is defined as inputs V REF = V DD/2
Timings used for IDD, IDDP and IDDQ measurement-loop patterns are provided in the
Current Test Definition and Patterns section.
• Basic IDD, IPP, and IDDQ measurement conditions are described in the Current Test
Definition and Patterns section.
•
•
•
•
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Current Specifications – Measurement Conditions
• Detailed IDD, IPP, and IDDQ measurement-loop patterns are described in the Current
Test Definition and Patterns section.
• Current measurements are done after properly initializing the device. This includes,
but is not limited to, setting:
RON = RZQ/7 (34 ohm in MR1);
Qoff = 0B (output buffer enabled in MR1);
RTT(NOM) = RZQ/6 (40 ohm in MR1);
RTT(WR) = RZQ/2 (120 ohm in MR2);
RTT(Park) = disabled;
TDQS feature disabled in MR1; CRC disabled in MR2; CA parity feature disabled in
MR3; Gear-down mode disabled in MR3; Read/Write DBI disabled in MR5; DM disabled in MR5
• Define D = {CS_n, RAS_n, CAS_n, WE_n}: = {HIGH, LOW, LOW, LOW}; apply BG/BA
changes when directed.
• Define D_n = {CS_n, RAS_n, CAS_n, WE_n}: = {HIGH, HIGH, HIGH, HIGH}; apply invert of BG/BA changes when directed above.
Note: The measurement-loop patterns must be executed at least once before actual current measurements can be taken.
Figure 242: Measurement Setup and Test Load for IDDx, IDDPx, and IDDQx
IDD
VDD
RESET_n
CK_t/CK_c
IPP
IDDQ
VPP
VDDQ
DDR4
SDRAM
CKE
CS_n
C
ACT_n, RAS_n, CAS_n, WE_n
A, BG, BA
ODT
ZQ
V
DQ
DM_n
VSSQ
SS
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DQS_t, DQS_c
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Current Specifications – Measurement Conditions
Figure 243: Correlation: Simulated Channel I/O Power to Actual Channel I/O Power
Applic ation-s pe c ific
memory c ha nne l
env ironmen t
C hanne l I/O
pow er simulation
I DD Q
tes t loa d
I DD Q
simulation
IDD Q
meas ure ment
C or relation
C orre c tion
C hanne l I/O
pow er n umber
Note:
1. Supported by IDDQ measurement.
IDD Definitions
Table 136: Basic IDD, IPP, and IDDQ Measurement Conditions
Symbol
Description
IDD0
Operating One Bank Active-Precharge Current (AL = 0)
CKE: HIGH; External clock: On; tCK, nRC, nRAS, CL: see the previous table; BL: 8;1 AL: 0; CS_n: HIGH between
ACT and PRE; Command, address, bank group address, bank address inputs: partially toggling according to the
next table; Data I/O: VDDQ; DM_n: stable at 0; Bank activity: cycling with one bank active at a time: 0, 0, 1, 1, 2,
2, ... (see the IDD0 Measurement-Loop Pattern table); Output buffer and RTT: enabled in mode registers;2 ODT
signal: stable at 0; Pattern details: see the IDD0 Measurement-Loop Pattern table
IPP0
Operating One Bank Active-Precharge IPP Current (AL = 0)
Same conditions as IDD0 above
IDD1
Operating One Bank Active-Read-Precharge Current (AL = 0)
CKE: HIGH; External clock: on; tCK, nRC, nRAS, nRCD, CL: see the previous table; BL: 8;1, 5 AL: 0; CS_n: HIGH
between ACT, RD, and PRE; Command, address, bank group address, bank address inputs, Data I/O: partially
toggling according to the IDD1 Measurement-Loop Pattern table; DM_n: stable at 0; Bank activity: cycling with
one bank active at a time: 0, 0, 1, 1, 2, 2, ... (see the following table); Output buffer and RTT: enabled in mode
registers;2 ODT Signal: stable at 0; Pattern details: see the IDD1 Measurement-Loop Pattern table
IDD2N
Precharge Standby Current (AL = 0)
CKE: HIGH; External clock: On; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address Inputs: partially toggling according to the IDD2N and IDD3N Measurement-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and
RTT: enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD2N and IDD3N MeasurementLoop Pattern table
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Current Specifications – Measurement Conditions
Table 136: Basic IDD, IPP, and IDDQ Measurement Conditions (Continued)
Symbol
Description
IDD2NT
Precharge Standby ODT Current
CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank gropup address, bank address inputs: partially toggling according to the IDD2NT and IDDQ2NT Measurement-Loop Pattern table; Data I/O: VSSQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer
and RTT: enabled in mode registers;2 ODT signal: toggling according to the IDD2NT and IDDQ2NT MeasurementLoop Pattern table; Pattern details: see the IDD2NT and IDDQ2NT Measurement-Loop Pattern table
IDDQ2NT
Precharge Standby ODT IDDQ Current
Has the same definition as IDD2NT above, with the exception of measuring IDDQ current instead of IDD current
IDD2P
Precharge Power-Down Current
CKE: LOW; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all
banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0
IDD2Q
Precharge Quiet Standby Current
CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all
banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0
IDD3N
Active Standby Current (AL = 0)
CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: partially toggling according to the IDD2N and IDD3N Measurement-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks open; Output buffer and
RTT: Enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD2N and IDD3N MeasurementLoop Pattern table
IPPSB
Active Standby IPPSB Current (AL = 0)
Same conditions as IDD3N above
IDD3P
Active Power-Down Current (AL = 0)
CKE: LOW; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: stable at 1; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all
banks open; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0
IDD4R
Operating Burst Read Current (AL = 0)
CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;15 AL: 0; CS_n: HIGH between RD; Command, address, bank group address, bank address inputs: partially toggling according to the IDD4R Measurement-Loop Pattern table; Data I/O: seamless read data burst with different data between one burst and the
next one according to the IDD4R Measurement-Loop Pattern table; DM_n: stable at 1; Bank activity: all banks
open, RD commands cycling through banks: 0, 0, 1, 1, 2, 2, ... (see the IDD4R Measurement-Loop Pattern table);
Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD4R Measurement-Loop Pattern table
IDD4W
Operating Burst Write Current (AL = 0)
CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: HIGH between WR; Command, address, bank group address, bank address inputs: partially toggling according to the IDD4W Measurement-Loop Pattern table; Data I/O: seamless write data burst with different data between one burst and the
next one according to the IDD4W Measurement-Loop Pattern table; DM: stable at 0; Bank activity: all banks
open, WR commands cycling through banks: 0, 0, 1, 1, 2, 2, ... (see IDD4W Measurement-Loop Pattern table);
Output buffer and RTT: enabled in mode registers (see note2); ODT signal: stable at HIGH; Pattern details: see
the IDD4W Measurement-Loop Pattern table
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Current Specifications – Measurement Conditions
Table 136: Basic IDD, IPP, and IDDQ Measurement Conditions (Continued)
Symbol
Description
IDD5R
Burst Refresh Current (1X REF)
CKE: HIGH; External clock: on; tCK, CL, nREFI: see the previous table; BL: 8;1 AL: 0; CS_n: HIGH between REF;
Command, address, bank group address, bank address inputs: partially toggling according to the IDD5R Measurement-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: REF command every nREFI (see
the IDD5R Measurement-Loop Pattern table); Output buffer and RTT: enabled in mode registers2; ODT signal:
stable at 0; Pattern details: see the IDD5R Measurement-Loop Pattern table
IPP5R
Burst Refresh Current (1X REF)
Same conditions as IDD5R above
IDD6N
Self Refresh Current: Normal Temperature Range
TC: 0–85°C; Auto self refresh (ASR): disabled;3 Self refresh temperature range (SRT): normal;4 CKE: LOW; External clock: off; CK_t and CK_c: LOW; CL: see the table above; BL: 8;1 AL: 0; CS_n, command, address, bank group
address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: SELF REFRESH operation; Output buffer
and RTT: enabled in mode registers;2 ODT signal: midlevel
IPP6N
Self Refresh IPP Current: Normal Temperature Range
Same conditions as IDD6N above
IDD6E
Self Refresh Current: Extended Temperature Range 4
TC: 0–95°C; Auto self refresh (ASR): disabled4; Self refresh temperature range (SRT): extended;4 CKE: LOW; External clock: off; CK_t and CK_c: LOW; CL: see the previous table; BL: 8;1 AL: 0; CS_n, command, address, group
bank address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: EXTENDED TEMPERATURE SELF
REFRESH operation; Output buffer and RTT: enabled in mode registers;2 ODT signal: midlevel
IDD6R
Self Refresh Current: Reduced Temperature Range
TC: 0–45°C; Auto self refresh (ASR): disabled; Self refresh temperature range (SRT): reduced;4 CKE: LOW; External clock: off; CK_t and CK_c: LOW; CL: see the previous table; BL: 8;1 AL: 0; CS_n, command, address, bank
group address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: EXTENDED TEMPERATURE SELF
REFRESH operation; Output buffer and RTT: enabled in mode registers;2 ODT signal: midlevel
IDD7
Operating Bank Interleave Read Current
CKE: HIGH; External clock: on; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see the previous table; BL: 8;15 AL: CL 1; CS_n: HIGH between ACT and RDA; Command, address, group bank adress, bank address inputs: partially
toggling according to the IDD7 Measurement-Loop Pattern table; Data I/O: read data bursts with different data
between one burst and the next one according to the IDD7 Measurement-Loop Pattern table; DM: stable at 1;
Bank activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see the IDD7
Measurement-Loop Pattern table; Output buffer and RTT: enabled in mode registers;2 ODT signal: stable at 0;
Pattern details: see the IDD7 Measurement-Loop Pattern table
IPP7
Operating Bank Interleave Read IPP Current
Same conditions as IDD7 above
IDD8
Maximum Power Down Current
Place DRAM in MPSM then CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n:
stable at 1; Command, address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n:
stable at 1; Bank activity: all banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0
Notes:
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1. Burst length: BL8 fixed by MRS: set MR0[1:0] 00.
2. Output buffer enable: set MR1[12] 0 (output buffer enabled); set MR1[2:1] 00 (RON =
RZQ/7); RTT(NOM) enable: set MR1[10:8] 011 (RZQ/6); RTT(WR) enable: set MR2[11:9] 001
(RZQ/2), and RTT(Park) enable: set MR5[8:6] 000 (disabled).
3. Auto self refresh (ASR): set MR2[6] 0 to disable or MR2[6] 1 to enable feature.
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Current Specifications – Measurement Conditions
4. Self refresh temperature range (SRT): set MR2[7] 0 for normal or MR2[7] 1 for extended
temperature range.
5. READ burst type: Nibble sequential, set MR0[3] 0.
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Current Specifications – Patterns and Test Conditions
Current Specifications – Patterns and Test Conditions
Current Test Definitions and Patterns
Sub-Loop
Cycle
Number
Command
CS_n
ACT_n
RAS_n/A16
CAS_n/A15
WE_n/A14
ODT
BG[1:0]2
BA[1:0]
A12/BC_n
A[17,13,11]]
A[10]/AP
A[9:7]
A[6:3]
A[2:0]
CKE
CK_t, CK_c
Table 137: IDD0 and IPP0 Measurement-Loop Pattern1
Data3
0
0
ACT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
1, 2
D, D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
–
3, 4
D_n,
D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
–
PRE
0
1
0
...
Repeat pattern 1...4 until nRAS - 1; truncate if necessary
Static High
Toggling
nRAS
1
0
0
0
0
0
0
0
0
0
0
...
Repeat pattern 1...4 until nRC - 1; truncate if necessary
1
1 × nRC
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 1 instead
2
2 × nRC
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
3
3 × nRC
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 3 instead
4
4 × nRC
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
5
5 × nRC
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 2 instead
6
6 × nRC
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
7
7 × nRC
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 0 instead
8
8 × nRC
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4
9
9 × nRC
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 1 instead4
10
10 × nRC
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4
11
11 × nRC
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 3 instead4
12
12 × nRC
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4
13
13 × nRC
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 2 instead4
14
14 × nRC
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4
15
15 × nRC
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 0 instead4
Notes:
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1.
2.
3.
4.
–
DQS_t, DQS_c are VDDQ.
BG1 is a "Don't Care" for x16 devices.
DQ signals are VDDQ.
For x4 and x8 only.
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4Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Patterns and Test Conditions
Sub-Loop
Cycle
Number
Command
CS_n
ACT_n
RAS_n/A16
CAS_n/A15
WE_n/A14
ODT
BG[1:0]2
BA[1:0]
A12/BC_n
A[17,13,11]]
A[10]/AP
A[9:7]
A[6:3]
A[2:0]
CKE
CK_c, CK_t,
Table 138: IDD1 Measurement – Loop Pattern1
Data3
0
0
ACT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
1, 2
D, D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
–
3, 4
D_n, D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
–
RD
0
...
Repeat pattern 1...4 until nRCD - AL - 1; truncate if necessary
nRCD - AL
...
PRE
...
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
D0 = 00, D1 =
FF,
D2 = FF, D3 =
00,
D4 = FF, D5 =
00,
D5 = 00, D7 = FF
1 × nRC + 0
ACT
0
0
0
1
1
0
1
1
0
0
0
0
0
0
–
1 × nRC + 1,
2
D, D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
–
1
1
1
1
1
0
3
3
0
0
0
7
F
0
–
...
Repeat pattern nRC + 1...4 until 1 × nRC + nRAS - 1; truncate if necessary
1 × nRC
+nRCD - AL
Static High
0
Repeat pattern 1...4 until nRC - 1; truncate if necessary
1 × nRC + 3, D_n, D_n
4
Toggling
1
Repeat pattern 1...4 until nRAS - 1; truncate if necessary
nRAS
1
1
RD
...
0
1
1
0
1
0
1
1
0
0
0
0
0
0
0
0
Repeat pattern 1...4 until nRAS - 1; truncate if necessary
1 × nRC +
nRAS
...
PRE
0
1
0
1
0
0
1
1
0
0
0
0
Repeat pattern nRC + 1...4 until 2 × nRC - 1; truncate if necessary
2
2 × nRC
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
3
3 × nRC
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 3 instead
4
4 × nRC
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
5
5 × nRC
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 2 instead
6
6 × nRC
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
7
7 × nRC
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 0 instead
8
9 × nRC
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4
9
10 × nRC
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 1 instead4
10
11 × nRC
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4
11
12 × nRC
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 3 instead4
12
13 × nRC
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4
13
14 × nRC
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 2 instead4
14
15 × nRC
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4
15
16 × nRC
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 0 instead4
Notes:
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D0 = FF, D1 =
00,
D2 = 00, D3 =
FF,
D4 = 00, D5 =
FF,
D5 = FF, D7 = 00
1. DQS_t, DQS_c are VDDQ when not toggling.
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Current Specifications – Patterns and Test Conditions
2. BG1 is a "Don't Care" for x16 devices.
3. DQ signals are VDDQ except when burst sequence drives each DQ signal by a READ command.
4. For x4 and x8 only.
Static High
0
Toggling
A[2:0]
A[6:3]
A[9:7]
A[10]/AP
A[17,13,11]]
A12/BC_n
BA[1:0]
BG[1:0]2
ODT
WE_n/A14
CAS_n/A15
RAS_n/A16
ACT_n
CS_n
Command
Cycle
Number
Sub-Loop
CKE
CK_c, CK_t,
Table 139: IDD2N, IDD3N, and IPP3P Measurement – Loop Pattern1
0
D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
–
1
D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
–
2
D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
–
3
D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
–
1
4–7
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 1 instead
2
8–11
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
3
12–15
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 3 instead
4
16–19
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
5
20–23
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 2 instead
6
24–27
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
7
28–31
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 0 instead
8
32–35
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4
9
36–39
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 1 instead4
10
40–43
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4
11
44–47
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 3 instead4
12
48–51
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4
13
52–55
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 2 instead4
14
56–59
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4
15
60–63
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 0 instead4
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Data3
1.
2.
3.
4.
DQS_t, DQS_c are VDDQ.
BG1 is a "Don't Care" for x16 devices.
DQ signals are VDDQ.
For x4 and x8 only.
318
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Patterns and Test Conditions
Sub-Loop
Cycle
Number
Command
CS_n
ACT_n
RAS_n/A16
CAS_n/A15
WE_n/A14
ODT
BG[1:0]2
BA[1:0]
A12/BC_n
A[17,13,11]]
A[10]/AP
A[9:7]
A[6:3]
A[2:0]
CKE
Static High
Toggling
CK_c, CK_t,
Table 140: IDD2NT and IDDQ2NT Measurement – Loop Pattern1
Data3
0
0
D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
–
1
D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
–
2
D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
–
3
D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
–
1
4–7
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 1 instead
2
8–11
Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
3
12–15
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 3 instead
4
16–19
Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
5
20–23
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 2 instead
6
24–27
Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
7
28–31
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 0 instead
8
32–35
Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4
9
36–39
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 1 instead4
10
40–43
Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4
11
44–47
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 3 instead4
12
48–51
Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4
13
52–55
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 2 instead4
14
56–59
Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4
15
60–63
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 0 instead4
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
1.
2.
3.
4.
DQS_t, DQS_c are VSSQ.
BG1 is a "Don't Care" for x16 devices.
DQ signals are VSSQ.
For x4 and x8 only.
319
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Patterns and Test Conditions
Sub-Loop
Cycle
Number
Command
CS_n
ACT_n
RAS_n/A16
CAS_n/A15
WE_n/A14
ODT
BG[1:0]2
BA[1:0]
A12/BC_n
A[17,13,11]]
A[10]/AP
A[9:7]
A[6:3]
A[2:0]
CKE
CK_c, CK_t,
Table 141: IDD4R Measurement – Loop Pattern1
0
0
RD
0
1
1
0
1
0
0
0
0
0
0
0
0
0
1
D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
2, 3
D_n,
D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
4
RD
0
1
1
0
1
0
1
1
0
0
0
7
F
0
5
D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
6, 7
D_n,
D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
Static High
Toggling
1
2
8–11
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
3
12–15
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead
4
16–19
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
5
20–23
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead
6
24–27
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
7
28–31
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead
8
32–35
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4
9
36–39
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead4
10
40–43
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4
11
44–47
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead4
12
48–51
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4
13
52–55
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead4
14
56–59
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4
15
60–63
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead4
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Data3
D0 = 00, D1 =
FF,
D2 = FF, D3 =
00,
D4 = FF, D5 =
00,
D5 = 00, D7 =
FF
D0 = FF, D1 = 00
D2 = 00, D3 =
FF
D4 = 00, D5 =
FF
D5 = FF, D7 = 00
1. DQS_t, DQS_c are VDDQ when not toggling.
2. BG1 is a "Don't Care" for x16 devices.
3. Burst sequence driven on each DQ signal by a READ command. Outside burst operation,
DQ signals are VDDQ.
4. For x4 and x8 only.
320
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Patterns and Test Conditions
Cycle
Number
Command
CS_n
ACT_n
WE_n/A14
ODT
BG[1:0]2
BA[1:0]
A12/BC_n
A[17,13,1
1]]
A[10]/AP
A[9:7]
A[6:3]
A[2:0]
0
0
WR
0
1
1
0
0
1
0
0
0
0
0
0
0
0
1
D
1
0
0
0
0
1
0
0
0
0
0
0
0
0
2, 3
D_n,
D_n
1
1
1
1
0
1
3
3
0
0
0
7
F
0
4
WR
0
1
1
0
0
1
1
1
0
0
0
7
F
0
5
D
1
0
0
0
0
1
0
0
0
0
0
0
0
0
6, 7
D_n,
D_n
1
1
1
1
0
1
3
3
0
0
0
7
F
0
Static High
Toggling
1
RAS_n/A1
6
CAS_n/A1
5
Sub-Loop
CKE
CK_c,
CK_t,
Table 142: IDD4W Measurement – Loop Pattern1
2
8–11
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
3
12–15
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead
4
16–19
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
5
20–23
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead
6
24–27
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
7
28–31
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead
8
32–35
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4
9
36–39
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead4
10
40–43
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4
11
44–47
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead4
12
48–51
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4
13
52–55
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead4
14
56–59
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4
15
60–63
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead4
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Data3
D0 = 00, D1 = FF,
D2 = FF, D3 = 00,
D4 = FF, D5 = 00,
D5 = 00, D7 = FF
D0 = FF, D1 = 00
D2 = 00, D3 = FF
D4 = 00, D5 = FF
D5 = FF, D7 = 00
1. DQS_t, DQS_c are VDDQ when not toggling.
2. BG1 is a "Don't Care" for x16 devices.
3. Burst sequence driven on each DQ signal by WRITE command. Outside burst operation,
DQ signals are VDDQ.
4. For x4 and x8 only.
321
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Patterns and Test Conditions
Sub-Loop
Cycle
Number
Command
CS_n
ACT_n
RAS_n/A16
CAS_n/A15
WE_n/A14
ODT
BG[1:0]3
BA[1:0]
A12/BC_n
A[17,13,11]]
A[10]/AP
A[9:7]
A[6:3]
A[2:0]
CKE
CK_c, CK_t,
Table 143: IDD4Wc Measurement – Loop Pattern1
0
0
WR
0
1
1
0
0
1
0
0
0
0
0
0
0
0
1, 2
D, D
1
0
0
0
0
1
0
0
0
0
0
0
0
0
3, 4
D_n,
D_n
1
1
1
1
0
1
3
3
0
0
0
7
F
0
Static High
Toggling
1
5
WR
0
1
1
0
0
1
1
1
0
0
0
7
F
0
6, 7
D, D
1
0
0
0
0
1
0
0
0
0
0
0
0
0
8, 9
D_n,
D_n
1
1
1
1
0
1
3
3
0
0
0
7
F
0
2
10–14
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
3
15–19
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead
4
20–24
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
5
25–29
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead
6
30–34
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
7
35–39
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead
8
40–44
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4
9
45–49
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead4
10
50–54
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4
11
55–59
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead4
12
60–64
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4
13
65–69
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead4
14
70–74
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4
15
75–79
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead4
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Data4
D0 = 00, D1 = FF,
D2 = FF, D3 = 00,
D4 = FF, D5 = 00,
D8 = CRC
D0 = FF, D1 = 00,
D2 = 00, D3 = FF,
D4 = 00, D5 = FF,
D5 = FF, D7 = 00
D8 = CRC
1.
2.
3.
4.
Pattern provided for reference only.
DQS_t, DQS_c are VDDQ when not toggling.
BG1 is a "Don't Care" for x16 devices.
Burst sequence driven on each DQ signal by WRITE command. Outside burst operation,
DQ signals are VDDQ.
5. For x4 and x8 only.
322
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Patterns and Test Conditions
Sub-Loop
Cycle
Number
Command
CS_n
ACT_n
RAS_n/A16
CAS_n/A15
WE_n/A14
ODT
BG[1:0]2
BA[1:0]
A12/BC_n
A[17,13,11]]
A[10]/AP
A[9:7]
A[6:3]
A[2:0]
CKE
Data3
0
0
REF
0
1
0
0
1
0
0
0
0
0
0
0
0
0
–
1
1
D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
–
2
D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
–
3
D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
–
4
D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
–
Static High
Toggling
CK_c, CK_t,
Table 144: IDD5R Measurement – Loop Pattern1
2
5–8
Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 1 instead
9–12
Repeat pattern 1...4, use BG[1:0] = 0, use BA[1:0] = 2 instead
13–16
Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 3 instead
17–20
Repeat pattern 1...4, use BG[1:0] = 0, use BA[1:0] = 1 instead
21–24
Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 2 instead
25–28
Repeat pattern 1...4, use BG[1:0] = 0, use BA[1:0] = 3 instead
29–32
Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 0 instead
33–36
Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 0 instead4
37–40
Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 1 instead4
41–44
Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 2 instead4
45–48
Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 3 instead4
49–52
Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 1 instead4
53–56
Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 2 instead4
57–60
Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 3 instead4
61–64
Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 0 instead4
65...nREFI 1
Repeat sub-loop 1; truncate if necessary
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
1.
2.
3.
4.
DQS_t, DQS_c are VDDQ.
BG1 is a "Don't Care" for x16 devices.
DQ signals are VDDQ.
For x4 and x8 only.
323
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Patterns and Test Conditions
Sub-Loop
Cycle
Number
Command
CS_n
ACT_n
RAS_n/A16
CAS_n/A15
WE_n/A14
ODT
BG[1:0]2
BA[1:0]
A12/BC_n
A[17,13,11]]
A[10]/AP
A[9:7]
A[6:3]
A[2:0]
CKE
CK_t, CK_c
Table 145: IDD7 Measurement – Loop Pattern1
Data3
0
0
ACT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
1
RDA
0
1
1
0
1
0
0
0
0
0
1
0
0
0
2
D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
–
3
D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
–
...
Static High
Toggling
1
Repeat pattern 2...3 until nRRD - 1, if nRRD > 4. Truncate if necessary
nRRD
ACT
0
0
0
0
0
0
1
1
0
0
0
0
0
0
nRRD+1
RDA
0
1
1
0
1
0
1
1
0
0
1
0
0
0
–
...
Repeat pattern 2...3 until 2 × nRRD - 1, if nRRD > 4. Truncate if necessary
2
2 × nRRD
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
3
3 × nRRD
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead
4
4 × nRRD
Repeat pattern 2...3 until nFAW - 1, if nFAW > 4 × nRRD. Truncate if necessary
5
nFAW
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
6
nFAW + nRRD
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead
7
nFAW + 2 × nRRD
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
8
nFAW + 3 × nRRD
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead
9
nFAW + 4 × nRRD
Repeat sub-loop 4
10
2 × nFAW
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead
11
2 × nFAW + nRRD
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead
12
2 × nFAW + 2 ×
nRRD
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead
13
2 × nFAW + 3 ×
nRRD
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead
14
2 × nFAW + 4 ×
nRRD
Repeat sub-loop 4
15
3 × nFAW
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead
16
3 × nFAW + nRRD
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead
17
3 × nFAW + 2 ×
nRRD
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead
18
3 × nFAW + 3 ×
nRRD
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead
19
3 × nFAW + 4 ×
nRRD
Repeat sub-loop 4
20
4 × nFAW
Repeat pattern 2...3 until nRC - 1, if nRC > 4 × nFAW. Truncate if necessary
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
1. DQS_t, DQS_c are VDDQ.
2. BG1 is a "Don't Care" for x16 devices.
3. DQ signals are VDDQ except when burst sequence drives each DQ signal by a READ command.
324
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4Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Patterns and Test Conditions
4. For x4 and x8 only.
IDD Specifications
19-19-19
20-20-20
22-22-22
20-20-20
24-24-24
12
12
13
14
14
15
16
15
16
17
17
18
19
20
21
22
20
22
24
CK
CWL
9
11
11
10
12
12
11
14
14
12
16
16
14
18
18
14
18
18
16
20
20
CK
nRCD
10
11
12
12
13
14
14
15
16
15
16
17
17
18
19
19
20
21
20
22
24
CK
nRC
38
39
40
44
45
46
50
51
52
54
55
57
60
61
62
66
67
68
72
74
76
CK
nRP
10
11
12
12
13
14
14
15
16
15
16
17
17
18
19
19
20
21
20
22
24
CK
nRAS
0.937
0.833
0.75
0.682
22-22-22
17-17-17
11
1.071
21-21-21
17-17-17
10
1.25
18-18-18
15-15-15
CL
tCK
16-16-16
16-16-16
Uni
t
Symbol
15-15-15
DDR4-3200
14-14-14
DDR4-2933
14-14-14
DDR4-2666
13-13-13
DDR4-2400
12-12-12
DDR4-2133
12-12-12
DDR4-1866
11-11-11
DDR4-1600
10-10-10
Table 146: Timings used for IDD, IPP, and IDDQ Measurement – Loop Patterns
0.625
ns
28
32
36
39
43
47
52
CK
x41
16
16
16
16
16
16
16
CK
x8
20
22
23
26
28
31
34
CK
x1
6
28
28
32
36
40
44
48
CK
nRRD x4
_S
x8
4
4
4
4
4
4
4
CK
4
4
4
4
4
4
4
CK
x1
6
5
5
6
7
7
8
9
CK
nRRD x4
_L
x8
5
5
6
6
7
8
8
CK
5
5
6
6
7
8
8
CK
x1
6
6
6
7
8
9
10
11
CK
nFA
W
nCCD_S
4
4
4
4
4
4
4
CK
nCCD_L
5
5
6
6
7
8
8
CK
nWTR_S
2
3
3
3
4
4
4
CK
nWTR_L
6
7
8
9
10
11
12
CK
nREFI
6,240
7,283
8,324
9,364
10,400
11,437
12,480
CK
nRFC 2Gb
128
150
171
193
214
235
256
CK
nRFC 4Gb
208
243
278
313
347
382
416
CK
nRFC 8Gb
280
327
374
421
467
514
560
CK
nRFC
16Gb
440
514
587
660
734
807
880
CK
Note:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
1. 1KB based x4 use same numbers of clocks for nFAW as the x8.
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4Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Limits
Current Specifications – Limits
Table 147: IDD, IPP, and IDDQ Current Limits – Rev. A
Symbol
Width
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Unit
IDD0: One bank ACTIVATE-to-PRECHARGE current
x4, x8
58
58
60
64
mA
x16
66
66
68
70
mA
IPP0: One bank ACTIVATE-to-PRECHARGE
IPP current
x4, x8
4
4
4
4
mA
x16
4.6
4.6
4.6
4.6
mA
IDD1: One bank ACTIVATE-to-READ-toPRECHARGE current
x4, x8
63
63
65
68
mA
IDD2N: Precharge standby current
IDD2NT: Precharge standby ODT current
x16
78
78
80
83
mA
ALL
44
44
46
50
mA
x4, x8
50
50
54
58
mA
x16
60
60
64
68
mA
IDD2P: Precharge power-down current
ALL
30
30
30
32
mA
IDD2Q: Precharge quiet standby current
ALL
39
39
39
41
mA
IDD3N: Active standby current
ALL
61
61
63
67
mA
IPP3N: Active standby IPP current
ALL
3
3
3
3
mA
IDD3P: Active power-down current
ALL
44
44
44
44
mA
x4, x8
140
140
150
160
mA
x16
200
200
215
230
mA
IDD4W: Burst write current
x4, x8
156
156
176
196
mA
x16
246
246
276
314
mA
IDD5R: Burst refresh current (1X REF)
x4, x8
68
68
70
73
mA
x16
68
68
70
73
mA
x4, x8
4
4
4
4
mA
IDD4R: Burst read current
IPP5R: Burst refresh IPP current (1X REF)
x16
4
4
4
4
mA
IDD6N: Self refresh current; 0–85°C1
ALL
20
20
20
20
mA
IDD6E: Self refresh current;
0–95°C2
ALL
27
27
27
27
mA
IDD6R: Self refresh current;
0–45C3, 4
ALL
10
10
10
10
mA
(25°C)4
ALL
9
9
9
9
mA
IDD6A: Auto self refresh current (45°C)4
ALL
10
10
10
10
mA
IDD6A: Auto self refresh current (75°C)4
ALL
16
16
16
16
mA
ALL
3
3
3
3
mA
x4, x8
160
160
185
210
mA
x16
230
230
240
250
mA
x4, x8
10
10
12
14
mA
x16
12
12
14
16
mA
ALL
18
18
18
18
mA
IDD6A: Auto self refresh current
IPP6x: Auto self refresh
current on page
IDD7: Bank interleave read current
IPP7: Bank interleave read IPP current
IDD8: Maximum power-down current
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature
range of operation (0–85°C).
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4Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Limits
2. Applicable for MR2 settings A7 = 1 and A7 = 0; manual mode with extended temperature range of operation (0–95°C).
3. Applicable for MR2 settings A7 = 0 and A7 = 1; manual mode with reduced temperature
range of operation (0–45°C).
4. IDD6R and IDD6A values are typical.
5. When additive latency is enabled for IDD0, current changes by approximately 0%.
6. When additive latency is enabled for IDD1 , current changes by approximately +5% (x4/
x8), +4% (x16).
7. When additive latency is enabled for IDD2N , current changes by approximately +0.6%.
8. When DLL is disabled for IDD2N, current changes by approximately 0%.
9. When CAL is enabled for IDD2N, current changes by approximately –44%.
10. When gear-down is enabled for IDD2N, current changes by approximately 0%.
11. When CA parity is enabled for IDD2N, current changes by approximately +14%.
12. When additive latency is enabled for IDD3N, current changes by approximately +0.6%.
13. When additive latency is enabled for IDD4R, current changes by approximately +5%.
14. When read DBI is enabled for IDD4R, current changes by approximately 0%.
15. When additive latency is enabled for IDD4W, current changes by approximately +1.6%
(x4/8), +1% (x16).
16. When write DBI is enabled for IDD4W, current changes by approximately 0%.
17. When write CRC is enabled for IDD4W, current changes by approximately
–8% (2133/2400), –5% (1600/1866).
18. When CA parity is enabled for IDD4W, current changes by approximately +14% (x8), +8%
(x16).
19. When 2X REF is enabled for IDD5R, current changes by approximately –14%.
20. When 4X REF is enabled for IDD5R, current changes by approximately –33%.
21. IPP0 test and limit is applicable for IDD0 and IDD1 conditions.
22. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x and IDD8 conditions; that is, testing IPP3N should satisfy the IPPs for the noted IDD tests.
23. IPP6x is applicable to IDD6N, IDD6E, IDD6R and IDD6A conditions.
Table 148: IDD, IPP, and IDDQ Current Limits – Rev. B
Symbol
Width DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit
IDD0: One bank ACTIVATE- x4, x8
to-PRECHARGE current
x16
54
54
56
59
61
64
mA
68
68
69
72
76
80
mA
4
4
4
4
4
4
mA
IDD1: One bank ACTIVATE- x4, x8
to-READ-to- PRECHARGE
x16
current
71
71
73
76
81
86
mA
93
93
97
100
105
110
mA
IDD2N: Precharge standby
current
ALL
40
40
41
42
44
46
mA
IDD2NT: Precharge standby
ODT current
x4, x8
49
49
50
54
58
62
mA
x16
54
54
56
58
62
66
mA
IDD2P: Precharge powerdown current
ALL
22
22
22
22
22
23
mA
IDD2Q: Precharge quiet
standby current
ALL
35
35
36
36
37
38
mA
IPP0: One bank ACTIVATEto-PRECHARGE IPP current
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
ALL
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4Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Limits
Table 148: IDD, IPP, and IDDQ Current Limits – Rev. B (Continued)
Symbol
Width DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit
IDD3N: Active standby current
ALL
56
56
57
58
60
63
mA
IPP3N: Active standby IPP
current
ALL
3
3
3
3
3
3
mA
IDD3P: Active power-down
current
ALL
33
33
33
33
34
35
mA
IDD4R: Burst read current
IDD4W: Burst write current
x4
135
135
135
145
160
170
mA
x8
153
153
157
169
169
206
mA
x16
230
230
236
255
287
315
mA
x4
117
117
117
125
130
145
mA
x8
130
130
130
140
155
169
mA
x16
175
175
179
193
216
236
mA
IDD5R: Burst refresh current (1X REF)
ALL
64
64
65
66
68
71
mA
IPP5R: Burst refresh IPP current (1X REF)
ALL
5
5
5
5
5
5
mA
IDD6N: Self refresh current;
0–85°C1
ALL
24
24
24
24
24
24
mA
IDD6E: Self refresh current;
0–95°C2
ALL
47
47
47
47
47
47
mA
IDD6R: Self refresh current;
0–45C3, 4
ALL
25
25
25
25
25
25
mA
IDD6A: Auto self refresh
current (25°C)4
ALL
9
9
9
9
9
9
mA
IDD6A: Auto self refresh
current (45°C)4
ALL
12
12
12
12
12
12
mA
IDD6A: Auto self refresh
current (75°C)4
ALL
47
47
47
47
47
47
mA
IPP6x: Auto self refresh
current23
ALL
3
3
3
3
3
3
mA
x4
191
191
196
210
225
240
mA
IDD7: Bank interleave read
current
IPP7: Bank interleave read
IPP current
IDD8: Maximum powerdown current
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
x8
206
206
211
225
240
255
x16
281
281
289
297
320
348
mA
x4, x8
14
14
14
14
14
15
mA
x16
21
21
21
21
21
24
mA
ALL
19
19
19
19
19
19
mA
1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature
range of operation (0–85°C).
2. Applicable for MR2 settings A7 = 1 and A7 = 0; manual mode with extended temperature range of operation (0–95°C).
328
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4Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Limits
3. Applicable for MR2 settings A7 = 0 and A7 = 1; manual mode with reduced temperature
range of operation (0–45°C).
4. IDD6R and IDD6A values are typical.
5. When additive latency is enabled for IDD0, current changes by approximately 9%.
6. When additive latency is enabled for IDD1 , current changes by approximately +14% (x4/
x8), +14% (x16).
7. When additive latency is enabled for IDD2N , current changes by approximately +0.0%.
8. When DLL is disabled for IDD2N, current changes by approximately 1%.
9. When CAL is enabled for IDD2N, current changes by approximately –34%.
10. When gear-down is enabled for IDD2N, current changes by approximately 0%.
11. When CA parity is enabled for IDD2N, current changes by approximately +15%.
12. When additive latency is enabled for IDD3N, current changes by approximately +9%.
13. When additive latency is enabled for IDD4R, current changes by approximately +6%.
14. When read DBI is enabled for IDD4R, current changes by approximately -8%.
15. When additive latency is enabled for IDD4W, current changes by approximately +6%
(x4/8), +4% (x16).
16. When write DBI is enabled for IDD4W, current changes by approximately 13%.
17. When write CRC is enabled for IDD4W, current changes by approximately 4%.
18. When CA parity is enabled for IDD4W, current changes by approximately +15% (x4/x8),
+10% (x16).
19. When 2X REF is enabled for IDD5R, current changes by approximately –16%.
20. When 4X REF is enabled for IDD5R, current changes by approximately –35%.
21. IPP0 test and limit is applicable for IDD0 and IDD1 conditions.
22. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x and IDD8 conditions; that is, testing IPP3N should satisfy the IPPs for the noted IDD tests.
23. IPP6x is applicable to IDD6N, IDD6E, IDD6R and IDD6A conditions.
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Speed Bin Tables
Speed Bin Tables
DDR4 DRAM timing is primarily covered by two types of tables: the speed bin tables in
this section and those tables found in the Electrical Characteristics and AC Timing Parameters section. The timing parameter tables define the applicable timing specifications based on the speed rating. The speed bin tables below list the tAA, tRCD, tRP, tRAS
and tRC limits of a given speed mark and are applicable to the CL settings in the lower
half of the table provided they are applied in the correct clock range, which is noted.
Table 149: DDR4-1600 Speed Bins and Operating Conditions
DDR4-1600 Speed Bin
CL-nRCD-nRP
Parameter
Symbol
-125E
-125
11-11-11
12-12-12
Max
Min
Max
Min
Max
Unit
12.50
19.00
13.755
19.00
15.00
19.00
ns
tAA
tAA
tAA
tAA
tAA
tAA
ns
(MIN) +
2nCK
(MAX) +
2nCK
(MIN) +
2nCK
(MAX) +
2nCK
(MIN) +
2nCK
(MAX) +
2nCK
tRCD
12.50
–
13.755
–
15.00
–
ns
tRP
12.50
–
13.755
–
15.00
Internal READ command to first data
tAA
Internal READ command to first data
with read DBI enabled
tAA_DBI
ACTIVATE to internal READ or WRITE
delay time
PRECHARGE command period
-125F
10-10-10
Min
ACTIVATE-to-PRECHARGE command
period
tRAS
35
ACTIVATE-to-ACTIVATE or REFRESH
command period
tRC6
tRAS
READ: nonDBI
READ: DBI
CL = 9
CL = 10
CL = 11
CL = 12
WRITE
9×
+
tREFI
–
tRP
35
9×
tRAS
+
tREFI
–
tRP
35
tRAS
–
ns
tREFI
ns
–
ns
Max
Unit
9×
+
tRP
Symbol
Min
Max
Min
Max
CWL = 9
tCK4
1.5
1.9
1.5
1.9
CWL = 9
tCK4
1.5
1.9
1.5
1.9
CL = 10
CL = 12
CWL = 9, 11
tCK4
1.25
<1.5
CL = 11
CL = 13
CWL = 9, 11
tCK4
1.25
<1.5
1.25
<1.5
CL = 12
CL = 14
CWL = 9, 11
tCK4
1.25
<1.5
1.25
<1.5
Reserved
Min
Reserved
1.5
1.9
ns
ns
Reserved
ns
Reserved
ns
1.25
<1.5
ns
Supported CL settings
9–12
9, 11, 12
10, 12
nCK
Supported CL settings with read DBI
11–14
11, 13, 14
12, 14
nCK
Supported CWL settings
9, 11
9, 11
9, 11
nCK
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
1. Speed Bin table is only valid with DLL enabled and gear-down mode disabled.
2. When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK
range.
3. The programmed value of CWL must be less than or equal to programmed value of CL.
4. tCK (AVG) MIN.
5. The DRAM supports 13.5ns with CL9 operation at defined clock rates.
6. When calculating tRC and tRP in clocks, values may not be used in a combination that
would violate tRAS.
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4Gb: x4, x8, x16 DDR4 SDRAM
Speed Bin Tables
Table 150: DDR4-1866 Speed Bins and Operating Conditions
DDR4-1866 Speed Bin
CL-nRCD-nRP
Parameter
-107F
-107E
-107
12-12-12
13-13-13
14-14-14
Symbol
Min
Max
Min
Max
Min
Max
Unit
Internal READ command to first data
tAA
12.85
19.00
13.927
19.00
15.00
19.00
ns
Internal READ command to first data
with read DBI enabled
tAA_DBI
tAA
tAA
tAA
tAA
tAA
tAA
ns
(MIN) +
2nCK
(MAX) +
2nCK
(MIN) +
2nCK
(MAX) +
2nCK
(MIN) +
2nCK
(MAX) +
2nCK
ACTIVATE to internal READ or WRITE
delay time
tRCD
12.85
–
13.92 7
–
15.00
–
tRP
12.85
–
13.92 7
–
15.00
–
ns
ACTIVATE-to-PRECHARGE command
period
tRAS
34
9 × tREFI
34
9 × tREFI
34
9 × tREFI
ns
ACTIVATE-to-ACTIVATE or REFRESH
command period
tRC8
tRAS
–
ns
Max
Unit
PRECHARGE command period
READ:
nonDBI
READ: DBI
WRITE
+
–
tRP
Max
Min
Max
1.5
1.9
1.5
1.9
1.5
1.9
1.5
1.9
CL = 11
CWL = 9
CL = 12
CWL = 9
tCK6
CWL = 11
tCK6
Reserved
CWL = 9, 11
tCK6
Reserved
CL = 13
Reserved
1.25
<1.5
1.25
<1.5
CL = 12
CL = 14
CWL = 9, 11
tCK6
1.25
<1.5
CL = 12
CL = 14
CWL = 10, 12
tCK6
1.071
<1.25
CL = 13
CL = 15
CWL = 10, 12
tCK6
1.071
<1.25
1.071
<1.25
CWL = 10, 12
tCK6
1.071
<1.25
1.071
<1.25
CL = 14
CL = 16
tRAS
+
tRP
Min
CL = 10
CL = 11
–
Symbol
CL = 9
CL = 12
+
tRP
tCK6
CL = 10
tRAS
ns
Reserved
Min
Reserved
1.5
1.9
ns
ns
Reserved
ns
Reserved
ns
1.25
<1.5
ns
Reserved
ns
Reserved
ns
1.071
<1.25
ns
Supported CL settings
9, 10, 12–14
9, 11–14
10, 12, 14
nCK
Supported CL settings with read DBI
11,12,14-16
11, 13–16
12, 14, 16
nCK
9–12
9–12
9–12
nCK
Supported CWL settings
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
1. Speed Bin table is only valid with DLL enabled and gear-down mode disabled.
2. When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK
range.
3. The programmed value of CWL must be less than or equal to programmed value of CL.
4. 12.85ns is the minimum value of tAA and tRP when operating at DDR4-1866 at tCK
(AVG) MIN = 1.071ns and is only a reference that does not consider the down binning
strategy that 12.5ns supports.
5. 13.92ns is the minimum value of tAA and tRP when operating at DDR4-1866 at tCK
(AVG) MIN = 1.071ns and is only a reference that does not consider the down binning
strategy that 13.75ns supports.
6. tCK (AVG) MIN.
7. The DRAM supports 13.5ns with CL9 operation and 13.75ns with CL11 operation at defined clock rates.
8. When calculating tRC and tRP in clocks, values may not be used in a combination that
would violate tRAS.
331
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Speed Bin Tables
Table 151: DDR4-2133 Speed Bins and Operating Conditions
DDR4-2133 Speed Bin
CL-nRCD-nRP
Parameter
-093F
-093E
-093
14-14-14
15-15-15
16-16-16
Symbol
Min
Max
Min
Max
Min
Max
Unit
Internal READ command to first data
tAA
13.13
19.00
14.065
19.00
15.00
19.00
ns
Internal READ command to first data
with read DBI enabled
tAA_DBI
tAA
tAA
tAA
tAA
tAA
tAA
ns
(MIN) +
2nCK
(MAX) +
2nCK
(MIN) +
2nCK
(MAX) +
2nCK
(MIN) +
2nCK
(MAX) +
2nCK
ACTIVATE to internal READ or WRITE
delay time
tRCD
13.13
–
14.065
–
15.00
–
tRP
13.13
–
14.065
–
15.00
–
ns
ACTIVATE-to-PRECHARGE command
period
tRAS
33
9 × tREFI
33
9 × tREFI
33
9 × tREFI
ns
ACTIVATE-to-ACTIVATE or REFRESH
command period
tRC7
tRAS
–
ns
Max
Unit
PRECHARGE command period
READ:
nonDBI
READ: DBI
WRITE
tRAS
+
Min
Max
1.5
1.9
1.5
1.9
1.5
1.9
1.5
1.9
1.25
<1.5
1.25
<1.5
1.071
<1.25
1.071
<1.25
CL = 11
CWL = 9
CL = 12
CWL = 9
tCK4
CL = 11
CL = 13
CWL = 9 , 11
tCK4
CWL = 9, 11
tCK4
Reserved
1.25
<1.5
CL = 13
CL = 15
CWL = 10, 12
tCK4
CL = 14
CL = 16
CWL = 10, 12
tCK4
1.071
<1.25
CL = 14
CL = 17
CWL = 11, 14
tCK4
0.9376
<1.071
CWL = 11, 14
tCK4
0.937
<1.071
0.937
CWL = 11, 14
tCK4
0.937
<1.071
0.937
CL = 16
CL = 18
CL = 19
Reserved
tRAS
+
tRP
Max
CL = 10
CL = 15
–
tRP
Min
CL = 9
CL = 14
–
Symbol
tCK4
CL = 12
+
tRP
ns
Reserved
<1.071
<1.071
Min
Reserved
1.5
Reserved
1.25
<1.5
Reserved
1.071
ns
1.9
<1.25
ns
ns
ns
ns
Reserved
ns
Reserved
ns
0.937
<1.071
ns
Supported CL settings
9, 10, 12, 14–16
9–16
10, 12, 14, 16
nCK
Supported CL settings with read DBI
11, 12, 14, 16–19
11, 13–16,18,19
12, 14, 16, 19
nCK
Supported CWL settings
9, 10, 11, 12, 14
9, 10, 11, 12, 14
9, 10, 11, 12, 14
nCK
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
1. Speed Bin table is only valid with DLL enabled and gear-down mode disabled.
2. When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK
range.
3. The programmed value of CWL must be less than or equal to programmed value of CL.
4. tCK (AVG) MIN.
5. The DRAM supports 13.5ns with CL9 operation and 13.75ns with CL11 operation 13.92ns
with CL13 operation at defined clock rates.
6. If the clock period is less than 0.938ns and greater than or equal to 0.937ns, timing parameters that are derived off the clock will use 0.938ns as its reference. For example, if
tCK (MIN) = 0.938ns and tRP = 14.06ns, then tRP would require 15nCKs (14.06ns/
0.938ns), but if tCK (MIN) = 0.937ns and tRP = 14.06ns, then tRP would still require
15nCKs (14.06ns/ 0.938ns) and not 16nCKs (14.06ns/ 0.937ns).
7. When calculating tRC and tRP in clocks, values may not be used in a combination that
would violate tRAS.
332
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Speed Bin Tables
Table 152: DDR4-2400 Speed Bins and Operating Conditions
DDR4-2400 Speed Bin
CL-nRCD-nRP
Parameter
-083F
-083E
-083
15-15-15
16-16-16
17-17-17
Symbol
Min
Max
Min
Max
Min
Max
Unit
Internal READ command to first data
tAA
12.5
19.00
13.32
19.00
14.16
19.00
ns
Internal READ command to first data
with read DBI enabled
tAA_DBI
tAA
tAA
tAA
tAA
tAA
tAA
ns
(MIN) +
3nCK
(MAX) +
3nCK
(MIN) +
3nCK
(MAX) +
3nCK
(MIN) +
3nCK
(MAX) +
3nCK
ACTIVATE to internal READ or WRITE
delay time
tRCD
12.5
–
13.32
–
14.16
–
ns
tRP
12.5
–
13.32
–
14.16
–
ns
ACTIVATE-to-PRECHARGE command
period
tRAS
32
9 × tREFI
32
9 × tREFI
32
9 × tREFI
ns
ACTIVATE-to-ACTIVATE or REFRESH
command period
tRC6
tRAS
–
ns
Max
Unit
PRECHARGE command period
READ:
nonDBI
READ: DBI
WRITE
CL = 9
CL = 11
CL = 10
CL = 12
CL = 10
CL = 11
CL = 12
CL = 13
+
Max
Min
Max
CWL = 9
tCK4
1.5
1.9
1.5
1.9
CWL = 9
tCK4
1.5
1.9
1.5
1.9
CWL = 9, 11
tCK4
Reserved
CWL = 9, 11
tCK4
Reserved
CL = 14
CWL = 9, 11
CL = 14
CWL = 10, 12
tCK4
Reserved
CWL = 10, 12
tCK4
Reserved
CWL = 10, 12
tCK4
Reserved
Reserved
CL = 16
1.25
1.071
CL = 14
CL =17
CWL = 11, 14
CL = 15
CL = 18
CWL = 11, 14
tCK4
CL = 16
CL = 19
CWL = 11, 14
tCK4
0.937
<1.071
CWL = 12, 16
tCK4
0.833
<0.937
CL = 18
+
Min
Reserved
1.5
1.9
Reserved
ns
ns
ns
1.25
<1.5
1.25
<1.5
ns
1.25
<1.5
1.25
<1.5
ns
Reserved
<1.25
tCK4
CL = 15
Reserved
<1.5
tRAS
tRP
Min
CL = 12
CL = 14
–
Symbol
CL = 12
CL = 15
+
tRP
tCK4
CL = 13
tRAS
–
tRP
Reserved
ns
1.071
<1.25
1.071
<1.25
ns
1.071
<1.25
1.071
<1.25
ns
Reserved
Reserved
ns
0.9375
<1.071
0.937
<1.071
ns
0.937
<1.071
0.937
<1.071
ns
Reserved
Reserved
ns
Reserved
ns
CL = 16
CL = 19
CWL = 12, 16
tCK4
0.833
<0.937
0.833
<0.937
CL = 17
CL = 20
CWL = 12, 16
tCK4
0.833
<0.937
0.833
<0.937
0.833
<0.937
ns
CWL = 12, 16
tCK4
0.833
<0.937
0.833
<0.937
0.833
<0.937
ns
CL = 18
CL = 21
Supported CL settings
9, 10, 12, 14–18
9–18
10–18
nCK
Supported CL settings with read DBI
11, 12, 14, 16, 18-21
11, 13–16, 18–21
12–16, 18–21
nCK
Supported CWL settings
9, 10, 11, 12, 14, 16
9, 10, 11, 12, 14, 16
9, 10, 11, 12, 14, 16
nCK
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
1. Speed Bin table is only valid with DLL enabled and gear-down mode disabled.
2. When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK
range.
3. The programmed value of CWL must be less than or equal to programmed value of CL.
4. tCK (AVG) MIN.
333
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Speed Bin Tables
5. If the clock period is less than 0.938ns and greater than or equal to 0.937ns, timing parameters that are derived off the clock will use 0.938ns as its reference. For example, if
tCK (MIN) = 0.938ns and tRP = 14.06ns, then tRP would require 15nCKs (14.06ns/
0.938ns), but if tCK (MIN) = 0.937ns and tRP = 14.06ns, then tRP would still require
15nCKs (14.06ns/ 0.938ns) and not 16nCKs (14.06ns/ 0.937ns).
6. When calculating tRC and tRP in clocks, values may not be used in a combination that
would violate tRAS.
Table 153: DDR4-2666 Speed Bins and Operating Conditions
DDR4-2666 Speed Bin
CL-nRCD-nRP
Parameter
Symbol
-075F
-075E
-075
17-17-17
18-18-18
19-19-19
Min
Max
Max
Min
Max
Unit
13.5
19.00
14.255
19.00
ns
tAA
tAA
tAA
tAA
ns
(MAX) +
3nCK
(MIN) +
3nCK
(MAX) +
3nCK
(MIN) +
3nCK
(MAX) +
3nCK
12.75
–
13.5
–
14.255
–
ns
12.75
–
13.5
–
14.255
Internal READ command to first data
tAA
12.75
19.00
Internal READ command to first data
with read DBI enabled
tAA_DBI
tAA
tAA
(MIN) +
3nCK
ACTIVATE to internal READ or WRITE
delay time
tRCD
tRP
PRECHARGE command period
ACTIVATE-to-PRECHARGE command
period
tRAS
32
ACTIVATE-to-ACTIVATE or REFRESH
command period
tRC7
tRAS
READ:
nonDBI
READ: DBI
WRITE
CL = 9
CL = 11
CWL = 9
CL = 10
CL = 12
9×
+
tREFI
–
tRP
Symbol
Min
32
tRAS
9×
+
tREFI
–
tRP
32
tRAS
9×
+
–
ns
tREFI
ns
–
ns
tRP
Min
Max
Min
Max
tCK4
1.5
1.9
1.5
1.9
CWL = 9
tCK4
1.5
1.9
1.5
1.9
Min
Max
Reserved
1.5
1.9
Unit
ns
ns
CL = 10
CL = 12
CWL = 9, 11
tCK4
CL = 11
CL = 13
CWL = 9, 11
tCK4
1.25
<1.5
1.25
<1.5
1.25
<1.5
ns
CL = 12
CL = 14
CWL = 9, 11
tCK4
1.25
<1.5
1.25
<1.5
1.25
<1.5
ns
CWL = 10, 12
tCK4
1.071
<1.25
1.071
<1.25
1.071
<1.25
ns
1.071
<1.25
1.071
<1.25
1.071
<1.25
ns
CL = 12
CL = 14
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ns
ns
CL = 13
CL = 15
CWL = 10, 12
tCK4
CL = 14
CL = 16
CWL = 10, 12
tCK4
CWL = 11, 14
tCK4
CWL = 11, 14
tCK4
0.9376
<1.071
0.937
<1.071
0.937
<1.071
ns
0.937
<1.071
0.937
<1.071
0.937
<1.071
ns
CL = 14
CL = 15
CL =17
CL = 18
Reserved
Reserved
Reserved
ns
CL = 16
CL = 19
CWL = 11, 14
tCK4
CL = 15
CL = 18
CWL = 12, 16
tCK4
CWL = 12, 16
tCK4
0.833
<0.937
CWL = 12, 16
tCK4
0.833
<0.937
0.833
<0.937
0.833
<0.937
ns
0.833
<0.937
0.833
<0.937
ns
CL = 16
CL = 17
CL = 19
CL = 20
Reserved
Reserved
Reserved
ns
Reserved
Reserved
ns
CL = 18
CL = 21
CWL = 12, 16
tCK4
0.833
<0.937
CL = 17
CL = 20
CWL = 14, 18
tCK4
0.750
<0.833
CWL = 14, 18
tCK4
0.750
<0.833
0.750
<0.833
CWL = 14, 18
tCK4
0.750
<0.833
0.750
<0.833
0.750
<0.833
ns
CWL = 14, 18
tCK4
0.750
<0.833
0.750
<0.833
0.750
<0.833
ns
CL = 18
CL = 19
CL = 20
CL = 21
CL = 22
CL = 23
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
334
Reserved
Reserved
ns
Reserved
ns
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Speed Bin Tables
Table 153: DDR4-2666 Speed Bins and Operating Conditions (Continued)
DDR4-2666 Speed Bin
CL-nRCD-nRP
Parameter
Symbol
-075F
-075E
-075
17-17-17
18-18-18
19-19-19
Min
Max
Supported CL settings
Min
9–20
Supported CL settings with read DBI
Supported CWL settings
Notes:
Max
9–20
Min
Max
Unit
10,12-–20
nCK
11–16, 18–23
11–16, 18–23
12, 14–16, 18–23
nCK
9, 10, 11, 12, 14, 16,
18
9, 10, 11, 12, 14, 16,
18
9, 10, 11, 12, 14, 16,
18
nCK
1. Speed Bin table is only valid with DLL enabled and gear-down mode disabled.
2. When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK
range.
3. The programmed value of CWL must be less than or equal to programmed value of CL.
4. tCK (AVG) MIN.
5. The DRAM supports 13.92ns with CL13 operation, 14.07ns with CL15 operation, and
14.16ns with CL17 operation at defined clock rates.
6. If the clock period is less than 0.938ns and greater than or equal to 0.937ns, timing parameters that are derived off the clock will use 0.938ns as its reference. For example, if
tCK (MIN) = 0.938ns and tRP = 14.06ns, then tRP would require 15nCKs (14.06ns/
0.938ns), but if tCK (MIN) = 0.937ns and tRP = 14.06ns, then tRP would still require
15nCKs (14.06ns/ 0.938ns) and not 16nCKs (14.06ns/ 0.937ns).
7. When calculating tRC and tRP in clocks, values may not be used in a combination that
would violate tRAS.
Table 154: DDR4-2933 Speed Bins and Operating Conditions
DDR4-2933 Speed Bin
CL-nRCD-nRP
Parameter
-068E
-068
-068D
20-20-20
21-21-21
22-22-22
Symbol
Min
Max
Min
Max
Min
Max
Unit
Internal READ command to first data
tAA
13.645
19.00
14.32
19.00
15
19.00
ns
Internal READ command to first data
with read DBI enabled
tAA_DBI
tAA
tAA
tAA
tAA
tAA
tAA
ns
(MIN) +
4nCK
(MAX) +
4nCK
(MIN) +
4nCK
(MAX) +
4nCK
(MIN) +
4nCK
(MAX) +
4nCK
ACTIVATE to internal READ or WRITE
delay time
tRCD
13.64
–
14.32
–
15
–
ns
tRP
13.64
–
14.32
–
15
–
ns
ACTIVATE-to-PRECHARGE command
period
tRAS
32
9 × tREFI
32
9 × tREFI
32
9 × tREFI
ns
ACTIVATE-to-ACTIVATE or REFRESH
command period
tRC6
tRAS
–
ns
PRECHARGE command period
READ:
nonDBI
READ: DBI
WRITE
CL = 9
CL = 11
CWL = 9
CL = 10
CL = 12
CL = 10
CL = 12
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
+
–
tRP
Symbol
tRAS
+
–
tRP
Min
Max
tCK4
1.5
1.9
CWL = 9
tCK4
1.5
1.9
CWL = 9, 11
tCK4
Reserved
335
Min
+
tRP
Max
Reserved
1.5
tRAS
1.9
Reserved
Min
Max
Reserved
1.5
1.9
Reserved
Unit
ns
ns
ns
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Speed Bin Tables
Table 154: DDR4-2933 Speed Bins and Operating Conditions (Continued)
DDR4-2933 Speed Bin
CL-nRCD-nRP
Parameter
CL = 11
CL = 13
-068E
-068
-068D
20-20-20
21-21-21
22-22-22
Symbol
Min
Max
Min
Max
CWL = 9, 11
tCK4
1.25
<1.5
1.25
<1.5
1.25
<1.5
1.25
<1.5
CL = 12
CL = 14
CWL = 9, 11
tCK4
CL = 12
CL = 14
CWL = 10, 12
tCK4
CWL = 10, 12
tCK4
1.071
<1.25
1.071
<1.25
CWL = 10, 12
tCK4
1.071
<1.25
1.071
<1.25
CL = 13
CL = 14
CL = 15
CL = 16
Reserved
Reserved
CL = 14
CL =17
CWL = 11, 14
tCK4
CL = 15
CL = 18
CWL = 11, 14
tCK4
0.9376
<1.071
0.937
<1.071
CL = 16
CL = 19
CWL = 11, 14
tCK4
0.937
<1.071
0.937
<1.071
CWL = 12, 16
tCK4
CL = 15
CL = 18
Reserved
Reserved
Reserved
Reserved
CL = 16
CL = 19
CWL = 12, 16
tCK4
CL = 17
CL = 20
CWL = 12, 16
tCK4
0.833
<0.937
0.833
<0.937
CL = 18
CL = 21
CWL = 12, 16
tCK4
0.833
<0.937
0.833
<0.937
CWL = 14, 18
tCK4
CL = 17
CL = 20
Reserved
Reserved
Reserved
Reserved
Min
Max
Reserved
1.25
<1.5
Unit
ns
ns
Reserved
ns
Reserved
ns
1.071
<1.25
ns
Reserved
ns
Reserved
ns
0.937
<1.071
Reserved
ns
ns
Reserved
ns
Reserved
ns
0.833
<0.937
Reserved
ns
ns
CL = 18
CL = 21
CWL = 14, 18
tCK4
CL = 19
CL = 22
CWL = 14, 18
tCK4
0.750
<0.833
0.750
<0.833
0.750
<0.833
ns
CL = 20
CL = 23
CWL = 14, 18
tCK4
0.750
<0.833
0.750
<0.833
0.750
<0.833
ns
CWL = 16, 20
tCK4
CL = 19
CL = 23
Reserved
Reserved
Reserved
Reserved
ns
Reserved
Reserved
ns
Reserved
ns
CL = 20
CL = 24
CWL = 16, 20
0.682
<0.750
CL = 21
CL = 26
CWL = 16, 20
tCK4
0.682
<0.750
0.682
<0.750
CWL = 16, 20
tCK4
0.682
<0.750
0.682
<0.750
CL = 26
Supported CL settings
Supported CL settings with read DBI
Supported CWL settings
Notes:
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
ns
Reserved
tCK4
CL = 22
Reserved
0.682
<0.750
ns
9-22
10-22
10, 12, 14, 16, 18, 20
nCK
11-24, 26
12-24, 26
12, 14, 16, 19, 21,
23, 26
nCK
9, 10, 11, 12, 14, 16,
18, 20
9, 10, 11, 12, 14, 16,
18, 20
9, 10, 11, 12, 14, 16,
18, 20
nCK
1. Speed Bin table is only valid with DLL enabled and gear-down mode disabled.
2. When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK
range.
3. The programmed value of CWL must be less than or equal to programmed value of CL.
4. tCK (AVG) MIN.
5. The DRAM supports 13.5ns with CL9 operation.
6. If the clock period is less than 0.938ns and greater than or equal to 0.937ns, timing parameters that are derived off the clock will use 0.938ns as its reference. For example, if
tCK (MIN) = 0.938ns and tRP = 14.06ns, then tRP would require 15nCKs (14.06ns/
0.938ns), but if tCK (MIN) = 0.937ns and tRP = 14.06ns, then tRP would still require
15nCKs (14.06ns/ 0.938ns) and not 16nCKs (14.06ns/ 0.937ns).
7. When calculating tRC and tRP in clocks, values may not be used in a combination that
would violate tRAS.
336
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4Gb: x4, x8, x16 DDR4 SDRAM
Speed Bin Tables
Table 155: DDR4-3200 Speed Bins and Operating Conditions
DDR4-3200 Speed Bin
CL-nRCD-nRP
Parameter
Symbol
-062E
-062
22-22-22
24-24-24
Max
Min
Max
12.5
19.00
13.755
tAA
tAA
tAA
(MIN) +
4nCK
(MAX) +
4nCK
tRCD
12.5
tRP
12.5
Internal READ command to first data
tAA
Internal READ command to first data
with read DBI enabled
tAA_DBI
ACTIVATE to internal READ or WRITE
delay time
PRECHARGE command period
-062F
20-20-20
Min
ACTIVATE-to-PRECHARGE command
period
tRAS
32
ACTIVATE-to-ACTIVATE or REFRESH
command period
tRC6
tRAS
READ:
nonDBI
READ: DBI
WRITE
CL = 9
CL = 11
CWL = 9
CL = 10
CL = 12
9×
+
Min
Max
Unit
19.00
15
19.00
ns
tAA
tAA
tAA
ns
(MIN) +
4nCK
(MAX) +
4nCK
(MIN) +
4nCK
(MAX) +
4nCK
–
13.755
–
15
–
ns
–
13.755
–
15
–
ns
32
tREFI
ns
–
ns
tREFI
–
tRP
Symbol
32
tRAS
9×
+
tREFI
–
tRP
Min
Max
tCK4
1.5
1.9
CWL = 9
tCK4
1.5
1.9
Min
Max
1.9
CL = 10
CL = 12
CWL = 9, 11
tCK4
CL = 11
CL = 13
CWL = 9, 11
tCK4
1.25
<1.5
1.25
<1.5
CL = 12
CL = 14
CWL = 9, 11
tCK4
1.25
<1.5
1.25
<1.5
CWL = 10, 12
tCK4
1.071
<1.25
1.071
<1.25
1.071
<1.25
1.071
<1.25
CL = 12
CL = 14
Reserved
Reserved
Reserved
Reserved
CL = 13
CL = 15
CWL = 10, 12
tCK4
CL = 14
CL = 16
CWL = 10, 12
tCK4
CWL = 11, 14
tCK4
CWL = 11, 14
tCK4
0.9376
<1.071
0.937
<1.071
0.937
<1.071
0.937
<1.071
CL = 14
CL = 15
CL =17
CL = 18
Reserved
Reserved
CL = 16
CL = 19
CWL = 11, 14
tCK4
CL = 15
CL = 18
CWL = 12, 16
tCK4
CWL = 12, 16
tCK4
0.833
<0.937
CWL = 12, 16
tCK4
0.833
<0.937
0.833
<0.937
0.833
<0.937
0.833
<0.937
CL = 16
CL = 17
CL = 19
CL = 20
Reserved
CWL = 14, 18
tCK4
0.750
<0.833
CWL = 14, 18
tCK4
1.25
<1.5
ns
Reserved
ns
Reserved
ns
1.071
<1.25
ns
Reserved
ns
Reserved
ns
0.937
<1.071
ns
0.750
<0.833
0.750
<0.833
0.750
<0.833
0.833
<0.937
ns
Reserved
Reserved
ns
Reserved
Reserved
ns
Reserved
ns
CL = 20
CL = 23
CWL = 14, 18
tCK4
0.750
<0.833
CL = 20
CL = 24
CWL = 16, 20
tCK4
0.625
<0.750
CWL = 16, 20
tCK4
0.625
<0.750
0.625
<0.750
CWL = 16, 20
tCK4
0.625
<0.750
0.625
<0.750
CL = 28
ns
ns
ns
tCK4
CL = 24
Reserved
Reserved
Reserved
CWL = 14, 18
CL = 26
ns
ns
CWL = 12, 16
CL = 22
1.9
Reserved
CL = 20
CL = 22
1.5
ns
Reserved
CL = 21
CL = 19
Reserved
Unit
ns
CL = 17
CL = 21
Max
Reserved
CL = 18
CL = 18
Min
Reserved
tCK4
Reserved
+
tRP
Reserved
1.5
tRAS
9×
Reserved
0.750
<0.833
ns
Reserved
ns
Reserved
ns
0.625
<0.750
ns
Supported CL settings
9–20, 22, 24
10–20, 22, 24
10–20, 22, 24
nCK
Supported CL settings with read DBI
11–24, 26, 28
12–16, 18–24, 26, 28
12, 14, 16, 19, 21,
23, 28
nCK
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4Gb: x4, x8, x16 DDR4 SDRAM
Refresh Parameters By Device Density
Table 155: DDR4-3200 Speed Bins and Operating Conditions (Continued)
DDR4-3200 Speed Bin
CL-nRCD-nRP
Parameter
Symbol
Supported CWL settings
Notes:
-062F
-062E
-062
20-20-20
22-22-22
24-24-24
Min
Max
Min
9, 10, 11, 12, 14, 16,
18, 20
Max
9, 10, 11, 12, 14, 16,
18, 20
Min
Max
9, 10, 11, 12, 14, 16,
18, 20
Unit
nCK
1. Speed Bin table is only valid with DLL enabled and gear-down mode disabled.
2. When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK
range.
3. The programmed value of CWL must be less than or equal to programmed value of CL.
4. tCK (AVG) MIN.
5. The DRAM requires 13.5ns for CL9 operation; JEDEC doesn't require CL9 support for a
CL22 device.
6. If the clock period is less than 0.938ns and greater than or equal to 0.937ns, timing parameters that are derived off the clock will use 0.938ns as its reference. For example, if
tCK (MIN) = 0.938ns and tRP = 14.06ns, then tRP would require 15nCKs (14.06ns/
0.938ns), but if tCK (MIN) = 0.937ns and tRP = 14.06ns, then tRP would still require
15nCKs (14.06ns/ 0.938ns) and not 16nCKs (14.06ns/ 0.937ns).
7. When calculating tRC and tRP in clocks, values may not be used in such a combination
that would violate tRAS.
Refresh Parameters By Device Density
Table 156: Refresh Parameters by Device Density
Parameter
Symbol
REF command to ACT or REF command time
Average periodic refresh interval
Note:
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tRFC
tREFI
2Gb
4Gb
8Gb
16Gb
Unit
160
260
350
550
ns
0°C ≤ TC ≤ 85°C
7.8
7.8
7.8
7.8
μs
0°C < TC ≤ 95°C
3.9
3.9
3.9
3.9
μs
(All bank groups)
Notes
1
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine
if the devices support these options or requirements.
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Electrical Characteristics and AC Timing Parameters
Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400
Parameter
Symbol
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Min
Min
Min
Min
Max
Max
Max
Max
Unit
Notes
Clock Timing
Clock period average (DLL off mode)
tCK
(DLL_OFF)
Clock period average
tCK
High pulse width average
tCH
Low pulse width average
tCL
(AVG,
DLL_ON)
(AVG)
8
20
8
20
8
20
8
20
ns
1.25
1.9
1.071
1.9
0.937
1.9
0.833
1.9
ns
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
tCK
14
(AVG)
(AVG)
tCK
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
tJITper_tot
–63
63
–54
54
–47
47
–42
42
ps
18 , 19
Deterministic
tJITper_dj
–31
31
–27
27
–23
23
–21
21
ps
18
DLL locking
tJITper,lck
–50
50
–43
43
–38
38
-33
33
ps
Clock absolute period
tCK
(ABS)
MIN = tCK (AVG) MIN + tJITper_tot MIN; MAX = tCK (AVG) MAX +
tJITper_tot MAX
ps
Clock absolute high pulse width
(includes duty cycle jitter)
tCH
(ABS)
0.45
–
0.45
–
0.45
–
0.45
–
Clock absolute low pulse width
(includes duty cycle jitter)
tCL
(ABS)
0.45
–
0.45
–
0.45
–
0.45
–
tCK
(AVG)
Cycle-to-cycle jitter
tJITcc
–
125
–
107
–
94
–
83
ps
–
100
–
86
–
75
–
67
ps
(AVG)
Total
339
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Total
DLL locking
tCK
(AVG)
_tot
tJITcc,lck
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters
Clock period jitter
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Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Symbol
Cumulative error across 2 cycles
tERR2per
–92
92
–79
79
–69
69
–61
61
ps
3 cycles
tERR3per
–109
109
–94
94
–82
82
–73
73
ps
4 cycles
tERR4per
–121
121
–104
104
–91
91
–81
81
ps
5 cycles
tERR5per
–131
131
–112
112
–98
98
–87
87
ps
6 cycles
tERR6per
–139
139
–119
119
–104
104
–92
92
ps
7 cycles
tERR7per
–145
145
–124
124
–109
109
–97
97
ps
8 cycles
tERR8per
–151
151
–129
129
–113
113
–101
101
ps
9 cycles
tERR9per
–156
156
–134
134
–117
117
–104
104
ps
10 cycles
tERR10per
–160
160
–137
137
–120
120
–107
107
ps
11 cycles
tERR11per
–164
164
–141
141
–123
123
–110
110
ps
12 cycles
tERR12per
–168
168
–144
144
–126
126
–112
112
ps
n = 13, 14 . . . 49,
50 cycles
tERRnper
tERRnper
tERRnper
MIN = (1 + 0.68ln[n]) ×
tJITper_tot
MIN
MAX = (1 + 0.68ln[n]) ×
tJITper_tot
MAX
ps
340
DQ Input Timing
Data setup time to
DQS_t, DQS_c
Base (calibrated
VREF)
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Noncalibrated
VREF
Data hold time from
DQS_t, DQS_c
Base (calibrated
VREF)
Noncalibrated
VREF
tDS
Refer to DQ Input Receiver Specification section
(approximately 0.15tCK to 0.28tCK )
–
tPDA_S
minimum of 0.5UI
UI
tDH
Refer to DQ Input Receiver Specification section
(approximately 0.15tCK to 0.28tCK )
–
tPDA_H
minimum of 0.5UI
UI
DQ and DM minimum data pulse width
for each input
tDIPW
DQS_t, DQS_c to DQ skew, per group, per
access
tDQSQ
–
0.16
–
DQ output hold time from DQS_t, DQS_c
tQH
0.76
–
0.76
0.58
–
0.58
–
0.58
–
0.58
–
UI
0.16
–
0.16
–
0.17
UI
–
0.76
–
0.74
–
UI
DQ Output Timing (DLL enabled)
tQH
Data Valid Window per device:
tDQSQ each device’s output per UI
tDVW
Data Valid Window per device, per pin:
- tDQSQ each device’s output per UI
tDVW
tQH
d
0.63
p
0.66
0.63
–
0.66
0.64
–
0.69
0.64
–
0.72
UI
–
UI
Notes
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters
Parameter
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Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
DQ Low-Z time from CK_t, CK_c
tLZDQ
–450
225
–390
195
–360
180
–330
175
ps
DQ High-Z time from CK_t, CK_c
tHZDQ
–
225
–
195
–
180
–
175
ps
Parameter
Notes
DQ Strobe Input Timing
DQS_t, DQS_c rising edge to CK_t, CK_c
rising edge for 1tCKpreamble
tDQSS
1ck
–0.27
0.27
–0.27
0.27
–0.27
0.27
–0.27
0.27
CK
DQS_t, DQS_c rising edge to CK_t, CK_c
rising edge for 2tCKpreamble
tDQSS
2ck
–0.50
0.50
–0.50
0.50
–0.50
0.50
–0.50
0.50
CK
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tDQSL
0.46
0.54
0.46
0.54
0.46
0.54
0.46
0.54
CK
DQS_t, DQS_c differential input high
pulse width
tDQSH
0.46
0.54
0.46
0.54
0.46
0.54
0.46
0.54
CK
DQS_t, DQS_c falling edge setup to CK_t,
CK_c rising edge
tDSS
0.18
–
0.18
–
0.18
–
0.18
–
CK
DQS_t, DQS_c falling edge hold from
CK_t, CK_c rising edge
tDSH
0.18
–
0.18
–
0.18
–
0.18
–
CK
DQS_t, DQS_c differential WRITE preamble for 1tCKpreamble
tWPRE
1ck
0.9
–
0.9
–
0.9
–
0.9
–
CK
DQS_t, DQS_c differential WRITE preamble for 2tCKpreamble
tWPRE
2ck
1.8
–
1.8
–
1.8
–
1.8
–
CK
DQS_t, DQS_c differential WRITE postamble
tWPST
0.33
–
0.33
–
0.33
–
0.33
–
CK
DQS Strobe Output Timing (DLL enabled)
DQS_t, DQS_c rising edge output access
time from rising CK_t, CK_c
tDQSCK
–225
225
–195
195
–180
180
–175
175
ps
DQS_t, DQS_c rising edge output variance window per DRAM
tDQSCKi
–
370
–
330
–
310
–
290
ps
DQS_t, DQS_c differential output high
time
tQSH
0.4
–
0.4
–
0.4
–
0.4
–
CK
DQS_t, DQS_c differential output low
time
tQSL
0.4
–
0.4
–
0.4
–
0.4
–
CK
DQS_t, DQS_c Low-Z time (RL - 1)
tLZDQS
–450
225
–390
195
–360
180
–330
175
ps
DQS_t, DQS_c High-Z time (RL + BL/2)
tHZDQS
–
225
–
195
–
180
–
175
ps
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters
341
DQS_t, DQS_c differential input low pulse
width
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Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
DQS_t, DQS_c differential READ preamble for 1tCKpreamble
tRPRE
1ck
0.9
–
0.9
–
0.9
–
0.9
–
CK
21
DQS_t, DQS_c differential READ preamble for 2tCK preamble
tRPRE
2ck
1.8
–
1.8
–
1.8
–
1.8
–
CK
21
DQS_t, DQS_c differential READ postamble
tRPST
0.33
–
0.33
–
0.33
–
0.33
–
CK
22
DLL locking time
tDLLK
597
–
768
–
768
–
CK
2, 4
tIS
115
–
100
–
80
–
62
–
ps
215
–
200
–
180
–
162
–
ps
140
–
125
–
105
–
87
–
ps
215
–
200
–
180
–
162
–
ps
600
–
525
–
460
–
410
–
ps
Command and Address Timing
342
CMD, ADDR hold time Base
to CK_t, CK_c Base ref- VREFCA
erenced to VIH(DC) and
VIL(DC) levels
tIS
VREF
tIH
tIH
VREF
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CTRL, ADDR pulse width for each input
tIPW
ACTIVATE to internal READ or WRITE delay
tRCD
PRECHARGE command period
See Speed Bin Tables for
tRP
ACTIVATE-to-PRECHARGE command period
tRAS
ACTIVATE-to-ACTIVATE or REF command
period
tRC
ACTIVATE-to-ACTIVATE command period
to different bank groups for 1/2KB page
size
tRRD_S
(1/2KB)
ACTIVATE-to-ACTIVATE command period
to different bank groups for 1KB page
size
tRRD_S
ACTIVATE-to-ACTIVATE command period
to different bank groups for 2KB page
size
tRRD_S
(1KB)
(2KB)
–
tRCD
ns
See Speed Bin Tables for tRP
See Speed Bin Tables for
ns
tRAS
See Speed Bin Tables for tRC
ns
13
ns
13
MIN = greater
of 4CK or 5ns
MIN = greater
of 4CK or 4.2ns
MIN = greater
of 4CK or 3.7ns
MIN = greater
of 4CK or 3.3ns
CK
1
MIN = greater
of 4CK or 5ns
MIN = greater
of 4CK or 4.2ns
MIN = greater
of 4CK or 3.7ns
MIN = greater
of 4CK or 3.3ns
CK
1
MIN = greater
of 4CK or 6ns
MIN = greater
of 4CK or 5.3ns
MIN = greater
of 4CK or 5.3ns
MIN = greater
of 4CK or 5.3ns
CK
1
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters
CMD, ADDR setup time Base
to CK_t, CK_c Base ref- VREFCA
erenced to VIH(AC) and
VIL(AC) levels
597
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Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)
Parameter
ACTIVATE-to-ACTIVATE command period
to same bank groups for 1/2KB page size
Symbol
tRRD_L
DDR4-2400
Min
Min
Min
Min
Max
Unit
Notes
MIN = greater
of 4CK or 6ns
MIN = greater
of 4CK or 5.3ns
MIN = greater
of 4CK or 5.3ns
MIN = greater
of 4CK or 4.9ns
CK
1
MIN = greater
of 4CK or 7.5ns
MIN = greater
of 4CK or 6.4ns
MIN = greater
of 4CK or 6.4ns
MIN = greater
of 4CK or 6.4ns
CK
1
MIN = greater
MIN = greater
MIN = greater
MIN = greater
of 16CK or 20ns of 16CK or 17ns of 16CK or 15ns of 16CK or 13ns
ns
MIN = greater
MIN = greater
MIN = greater
MIN = greater
of 20CK or 25ns of 20CK or 23ns of 20CK or 21ns of 20CK or 21ns
ns
MIN = greater
MIN = greater
MIN = greater
MIN = greater
of 28CK or 35ns of 28CK or 30ns of 28CK or 30ns of 28CK or 30ns
ns
(2KB)
tWR
MIN = 15ns
ns
6, 10, 1
CK
6, 11, 1
CK
7, 10, 1
MIN = 1CK + tWR_CRC_DM
CK
7, 11, 1
MIN = greater of 4CK or 7.5ns
CK
6, 10, 1
CK
6, 11, 1
CK
7, 10, 1
MIN = 1CK + tWTR_L_CRC_DM
CK
7, 11, 1
tWTR_S
MIN = greater of (2CK or 2.5ns)
CK
6, 8, 9,
10, 1
tWTR_S
2
MIN = 1CK + tWTR_S
CK
6, 8, 9,
11, 1
(1KB)
(2KB)
(1/2KB)
tFAW
(1KB)
tFAW
tWR
2
MIN = 1CK +
343
tWR_CRC_DM
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tWR_CRC_DM
tWR
MIN =
+
greater of (4CK
or 3.75ns)
2
tWTR_L
tWTR_L
2
tWTR_L_CRC_D
M
tWTR_L_CRC_D
MIN =
tWR
+ greater of (5CK or 3.75ns)
MIN = 1CK +
MIN = tWTR_L +
greater of (4CK
or 3.75ns)
tWR
tWTR_L
MIN = tWTR_L + greater of (5CK or 3.75ns)
M2
Delay from start of internal WRITE transaction to internal READ command – Different bank group
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters
1
tFAW
Delay from start of internal WRITE transaction to internal READ command – Same
bank group when CRC and DM are both
enabled
Max
CK
Four ACTIVATE windows for 1/2KB page
size
Delay from start of internal WRITE transaction to internal READ command – Same
bank group
Max
MIN = greater
of 4CK or 4.9ns
tRRD_L
WRITE recovery time when CRC and DM
are both enabled
Max
MIN = greater
of 4CK or 5.3ns
ACTIVATE-to-ACTIVATE command period
to same bank groups for 2KB page size
WRITE recovery time
DDR4-2133
MIN = greater
of 4CK or 5.3ns
tRRD_L
Four ACTIVATE windows for 2KB page
size
DDR4-1866
MIN = greater
of 4CK or 6ns
(1/2KB)
ACTIVATE-to-ACTIVATE command period
to same bank groups for 1KB page size
Four ACTIVATE windows for 1KB page
size
DDR4-1600
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Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)
Parameter
Delay from start of internal WRITE transaction to internal READ command – Different bank group when CRC and DM are
both enabled
Symbol
tWTR_S_CRC_D
M
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Min
Min
Min
Min
Max
Unit
Notes
CK
7, 8, 9,
10, 1
MIN = 1CK + tWTR_S_CRC_DM
CK
7, 8, 9,
11, 1
MIN = greater of 4CK or 7.5ns
CK
1
tWTR_S
MIN =
MIN =
+
greater of (4CK
or 3.75ns)
tWTR_S_CRC_D
Max
tWTR_S
Max
Max
+ greater of (5CK or 3.75ns)
M2
READ-to-PRECHARGE time
tRTP
4
–
4
–
4
–
4
–
CK
CAS_n-to-CAS_n command delay to same
bank group
tCCD_L
MIN =
greater
of 4CK
or
6.25ns
–
MIN =
greater
of 4CK
or
5.355ns
–
MIN =
greater
of 4CK
or
5.355ns
–
MIN =
greater
of 4CK
or 5ns
–
CK
344
Auto precharge write recovery + precharge time
tDAL
MIN = WR + ROUNDUPtRP/tCK (AVG); MAX = N/A
(MIN)
15
CK
MRS Command Timing
MRS command cycle time
tMRD
8
–
8
–
8
–
8
–
CK
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‹ 2014 Micron Technology, Inc. All rights reserved.
MRS command cycle time in PDA mode
tMRD_PDA
MIN = greater of (16nCK, 10ns)
CK
MRS command cycle time in CAL mode
tMRD_CAL
MIN = tMOD + tCAL
CK
tMOD
MIN = greater of (24nCK, 15ns)
CK
MRS command update delay
MRS command update delay in PDA
mode
tMOD_PDA
MRS command update delay in CAL
mode
tMOD_CAL
MIN = tMOD + tCAL
tSDO
MIN = tMOD + 9ns
MRS command to DQS drive in preamble
training
MIN =
tMOD
CK
CK
MPR Command Timing
Multipurpose register recovery time
Multipurpose register write recovery time
tMPRR
MIN = 1CK
tWR_MPRR
MIN =
tMOD
CK
+ AL + PL
CRC Error Reporting Timing
CRC error to ALERT_n latency
CRC ALERT_n pulse width
tCRC_ALERT
3
13
3
13
3
13
3
13
ns
tCRC_ALERT_P
6
10
6
10
6
10
6
10
CK
W
1
1
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters
CAS_n-to-CAS_n command delay to different bank group
tCCD_S
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Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)
Parameter
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Symbol
Min
Min
Max
Min
Max
Min
Max
Unit
PL
4
–
4
–
4
–
5
–
CK
tPAR_UN-
–
PL
–
PL
–
PL
–
PL
CK
–
PL +
6ns
–
PL+
6ns
–
PL +
6ns
–
PL +
6ns
CK
48
96
56
112
64
128
72
144
CK
–
43
–
50
–
57
–
64
CK
Max
Notes
CA Parity Timing
Parity latency
Commands uncertain to be executed during this time
KNOWN
Delay from errant command to ALERT_n
assertion
tPAR_ALERT_O
Pulse width of ALERT_n signal when asserted
tPAR_ALERT_P
Time from alert asserted until DES commands required in persistent CA parity
mode
tPAR_ALERT_RS
N
W
P
3
–
4
–
4
–
5
–
CK
CS_n to command address latency in
gear-down mode
tCALg
N/A
–
N/A
–
N/A
–
N/A
–
CK
Command path disable delay upopn
MPSM entry
tMPED
MIN = tMOD (MIN) + tCPDED (MIN)
CK
1
Valid clock requirement after MPSM
entry
tCKMPE
MIN = tMOD (MIN) + tCPDED (MIN)
CK
1
Valid clock requirement before MPSM
exit
tCKMPX
MIN = tCKSRX (MIN)
CK
1
CS_n to command address latency
20
345
MPSM Timing
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‹ 2014 Micron Technology, Inc. All rights reserved.
Exit MPSM to commands not requiring a
locked DLL
Exit MPSM to commands requiring a
locked DLL
CS setup time to CKE
tXMP
tXS
(MIN)
CK
tXMPDLL
MIN = tXMP (MIN) + tXSDLL (MIN)
CK
tMPX_S
MIN = tIS (MIN) + tIH (MIN)
ns
CS_n HIGH hold time to CKE rising edge
tMPX_HH
CS_n LOW hold time to CKE rising edge
tMPX_LH
MIN =
12
tXMP-1
12
tXMP-1
0ns
tXP
12
0ns
ns
tXMP-1
12
0ns
tXMP-1
ns
0ns
Connectivity Test Timing
TEN pin HIGH to CS_n LOW – Enter CT
mode
tCT_Enable
200
–
200
–
200
–
200
–
ns
1
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters
CAL Timing
tCAL
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Min
Max
Min
Max
Min
Max
Parameter
Symbol
Min
Max
CS_n LOW and valid input to valid output
tCT_Valid
Unit
–
200
–
200
–
200
–
200
ns
CK_t, CK_c valid and CKE HIGH after TEN
goes HIGH
tCTCKE_Valid
10
–
10
–
10
–
10
–
ns
Notes
Calibration and VREFDQ Train Timing
ZQCL command: Long
calibration time
POWER-UP and
RESET operation
Normal operation
ZQCS command: Short calibration time
The VREF increment/decrement step time
tZQinit
1024
–
1024
–
1024
–
1024
–
CK
tZQoper
512
–
512
–
512
–
512
–
CK
tZQCS
128
–
128
–
128
–
128
–
CK
Enter VREFDQ training mode to the first
write or VREFDQ MRS command delay
tVREFDQE
MIN = 150ns
ns
1
Exit VREFDQ training mode to the first
WRITE command delay
tVREFDQX
MIN = 150ns
ns
1
MIN = greater of 5CK or tRFC (MIN) + 10ns
CK
1
Initialization and Reset Timing
Exit reset from CKE HIGH to a valid command
tXPR
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RESET_L pulse low after power stable
tPW_REST_S
0.1
–
0.1
–
0.1
–
0.1
–
μs
RESET_L pulse low at power-up
tPW_REST_L
200
–
200
–
200
–
200
–
μs
tVDDPR
MIN = N/A; MAX = 200
ms
RESET_n LOW to power supplies stable
tRPS
MIN = 0; MAX = 0
ns
RESET_n LOW to I/O and RTT High-Z
tIOZ
MIN = N/A; MAX = undefined
ns
Begin power supply ramp to power supplies stable
Refresh Timing
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters
MIN = 150ns
346
VREF_time
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)
Parameter
REFRESH-to-ACTIVATE
or REFRESH command
period (all bank
groups)
Symbol
4Gb
8Gb
16Gb
DDR4-1866
DDR4-2133
DDR4-2400
Min
Min
Min
Min
Max
Max
Max
Max
Unit
Notes
MIN = 260
ns
1, 12
MIN = 160
ns
1, 12
ns
1, 12
tRFC1
tRFC2
tRFC4
MIN = 110
tRFC1
MIN = 350
ns
1, 12
tRFC2
MIN = 260
ns
1, 12
tRFC4
MIN = 160
ns
1, 12
tRFC1
MIN = 550
ns
1, 12
tRFC2
MIN = 350
ns
1, 12
tRFC4
MIN = 260
ns
1, 12
0°C ≤ TC ≤ 85°C
tREFI
MIN = N/A; MAX = 7.8
μs
12
85°C < TC ≤ 95°C
tREFI
MIN = N/A; MAX = 3.9
μs
12
ns
1
ns
1
Self Refresh Timing
347
Exit self refresh to commands not requiring a locked DLL SRX to commands not
requiring a locked DLL in self refresh
abort
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‹ 2014 Micron Technology, Inc. All rights reserved.
Exit self refresh to ZQCL, ZQCS and MRS
(CL, CWL, WR, RTP and gear-down)
tXS
MIN = tRFC + 10ns
tXS_ABORT
MIN =
tRFC4
MIN =
tRFC4
tXS_FAST
+ 10ns
+ 10ns
1
ns
Exit self refresh to commands requiring a
locked DLL
tXSDLL
MIN = tDLLK (MIN)
CK
1
Minimum CKE low pulse width for self refresh entry to self refresh exit timing
tCKESR
MIN = tCKE (MIN) + 1nCK
CK
1
Minimum CKE low pulse width for self refresh entry to self refresh exit timing
when CA parity is enabled
tCKESR_PAR
MIN = tCKE (MIN) + 1nCK + PL
CK
1
Valid clocks after self refresh entry (SRE)
or power-down entry (PDE)
tCKSRE
MIN = greater of (5CK, 10ns)
CK
1
Valid clock requirement after self refresh
entry or power-down when CA parity is
enabled
tCKSRE_PAR
MIN = greater of (5CK, 10ns) + PL
CK
1
Valid clocks before self refresh exit (SRX)
or power-down exit (PDX), or reset exit
tCKSRX
MIN = greater of (5CK, 10ns)
CK
1
Power-Down Timing
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters
Average periodic refresh interval
DDR4-1600
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)
Parameter
Exit power-down with DLL on to any valid command
Exit power-down with DLL on to any valid command when CA Parity is enabled.
CKE MIN pulse width
Command pass disable delay
Symbol
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Min
Min
Min
Min
Max
Unit
Notes
MIN = greater of 4CK or 6ns
CK
1
MIN = (greater of 4CK or 6ns) + PL
CK
1
MIN = greater of 3CK or 5ns
CK
1
tXP
tXP
tCKE
_PAR
(MIN)
tCPDED
4
–
4
Max
–
Max
4
–
4
Max
–
CK
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tPD
MIN = tCKE (MIN); MAX = 9 × tREFI
CK
Begin power-down period prior to CKE
registered HIGH
tANPD
WL - 1CK
CK
Power-down entry period: ODT either
synchronous or asynchronous
PDE
Greater of tANPD or tRFC - REFRESH command to CKE LOW time
CK
Power-down exit period: ODT either synchronous or asynchronous
PDX
ACTIVATE command to power-down entry
tACTPDEN
1
–
1
–
2
–
2
–
CK
PRECHARGE/PRECHARGE ALL command
to power-down entry
tPRPDEN
1
–
1
–
2
–
2
–
CK
REFRESH command to power-down entry
tREFPDEN
1
–
1
–
2
–
2
–
MRS command to power-down entry
tMRSPDEN
MIN = tMOD (MIN)
CK
1
READ/READ with auto precharge command to power-down entry
tRDPDEN
MIN = RL + 4 + 1
CK
1
WRITE command to power-down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRPDEN
MIN = WL + 4 + tWR/tCK (AVG)
CK
1
WRITE command to power-down entry
(BC4MRS)
tWRPBC4DEN
MIN = WL + 2 + tWR/tCK (AVG)
CK
1
WRITE with auto precharge command to
power-down entry (BL8OTF,
BL8MRS,BC4OTF)
tWRAPDEN
MIN = WL + 4 + WR + 1
CK
1
WRITE with auto precharge command to
power-down entry (BC4MRS)
tWRAPBC4DEN
MIN = WL + 2 + WR + 1
CK
1
tANPD
+ tXSDLL
CK
Power-Down Entry Minimum Timing
ODT Timing
CK
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters
348
Power-down entry to power-down exit
timing
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)
Parameter
Symbol
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Min
Min
Min
Min
Max
Max
Max
Max
Unit
Direct ODT turn-on latency
DODTLon
WL - 2 = CWL + AL + PL - 2
CK
Direct ODT turn-off latency
DODTLoff
WL - 2 = CWL + AL + PL - 2
CK
0.3
0.7
0.3
0.7
0.3
0.7
0.3
0.7
CK
Asynchronous RTT(NOM) turn-on delay
(DLL off)
tAONAS
1
9
1
9
1
9
1
9
ns
Asynchronous RTT(NOM) turn-off delay
(DLL off)
tAOFAS
1
9
1
9
1
9
1
9
ns
ODT HIGH time with WRITE command
and BL8
ODTH8 1tCK
6
–
6
–
6
–
6
–
CK
ODTH8 2tCK
7
–
7
–
7
–
7
–
ODTH4 1tCK
4
–
4
–
4
–
4
–
5
–
5
–
5
–
5
–
RTT dynamic change skew
ODT HIGH time without WRITE command
or with WRITE command and BC4
ODTH4
2tCK
CK
Write Leveling Timing
349
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tWLMRD
40
–
40
–
40
–
40
–
CK
tWLDQSEN
25
–
25
–
25
–
25
–
CK
Write leveling setup from rising CK_t,
CK_c crossing to rising DQS_t, DQS_c
crossing
tWLS
0.13
–
0.13
–
0.13
–
0.13
–
tCK
Write leveling hold from rising DQS_t,
DQS_c crossing to rising CK_t, CK_c crossing
tWLH
First DQS_t, DQS_c rising edge after write
leveling mode is programmed
DQS_t, DQS_c delay after write leveling
mode is programmed
(AVG)
0.13
–
0.13
–
0.13
–
0.13
–
tCK
(AVG)
Write leveling output delay
tWLO
0
9.5
0
9.5
0
9.5
0
9.5
ns
Write leveling output error
tWLOE
0
2
0
2
0
2
0
2
ns
Gear-Down Timing (Not Supported Below DDR4-2666)
tXPR_GEAR
N/A
N/A
N/A
N/A
CK
tXS_GEAR
N/A
N/A
N/A
N/A
CK
MRS command to sync pulse time
tSYNC_GEAR
N/A
N/A
N/A
N/A
CK
Sync pulse to first valid command
tCMD_GEAR
N/A
N/A
N/A
N/A
CK
Gear-down setup time
tGEAR_setup
N/A
–
N/A
–
N/A
–
N/A
–
CK
Gear-down hold time
tGEAR_hold
N/A
–
N/A
–
N/A
–
N/A
–
CK
Exit reset from CKE HIGH to a valid MRS
gear-down
CKE HIGH assert to gear-down enable
time)
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters
tADC
Notes
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters
Notes:
1. Maximum limit not applicable.
2. tCCD_L and tDLLK should be programmed according to the value defined per operating
frequency.
3. Although unlimited row accesses to the same row is allowed within the refresh period,
excessive row accesses to the same row over a long term can result in degraded operation.
4. Data rate is greater than or equal to 1066 Mb/s.
5. RFUcorr
6. WRITE-to-READ when CRC and DM are both not enabled.
7. WRITE-to-READ delay when CRC and DM are both enabled.
8. The start of internal write transactions is defined as follows:
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
• For BL8 (fixed by MRS and on-the-fly): rising clock edge four clock cycles after WL
• For BC4 (on-the-fly): rising clock edge four clock cycles after WL
• For BC4 (fixed by MRS): rising clock edge two clock cycles after WL
For these parameters, the device supports tnPARAM [nCK] = RU{tPARAM [ns]/tCK (AVG)
[ns]}, in clock cycles, assuming all input clock jitter specifications are satisfied.
When operating in 1tCK WRITE preamble mode.
When operating in 2tCK WRITE preamble mode.
When CA parity mode is selected and the DLLoff mode is used, each REF command requires an additional "PL" added to tRFC refresh time.
DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row address may result in reduction of the product lifetime and/or
reduction in data retention ability.
Applicable from tCK (AVG) MIN to tCK (AVG) MAX as stated in the Speed Bin tables.
JEDEC specifies a minimum of five clocks.
The maximum read postamble is bound by tDQSCK (MIN) plus tQSH (MIN) on the left
side and tHZ(DQS) MAX on the right side.
The reference level of DQ output signal is specified with a midpoint as a widest part of
output signal eye, which should be approximately 0.7 × VDDQ as a center level of the
static single-ended output peak-to-peak swing with a driver impedance of 34 ohms and
an effective test load of 50 ohms to VTT = VDDQ.
JEDEC hasn't agreed upon the definition of the deterministic jitter; the user should focus on meeting the total limit.
Spread spectrum is not included in the jitter specification values. However, the input
clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with
an additional 1% of tCK (AVG) as a long-term jitter component; however, the spread
spectrum may not use a clock rate below tCK (AVG) MIN.
The actual tCAL minimum is the larger of 3 clocks or 3.748ns/tCK; the table lists the applicable clocks required at targeted speed bin.
The maximum READ preamble is bounded by tLZ(DQS) MIN on the left side and tDQSCK
(MAX) on the right side. See figure in the Clock to Data Strobe Relationship section.
Boundary of DQS Low-Z occur one cycle earlier in 2tCK toggle mode, which is illustrated
in the READ Preamble section.
DQ falling signal middle-point of transferring from HIGH to LOW to first rising edge of
DQS differential signal cross-point.
350
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09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Electrical Characteristics and AC Timing Parameters: 2666 Through 3200
Table 158: Electrical Characteristics and AC Timing Parameters
Parameter
Symbol
DDR4-2666
DDR4-2933
DDR4-3200
Min
Min
Min
Max
Max
Max
Reserved
Min
Max
Unit
Notes
Clock Timing
Clock period average (DLL off mode)
tCK
(DLL_OFF)
tCK
High pulse width average
tCH
Low pulse width average
tCL
(AVG,
DLL_ON)
(AVG)
8
20
8
20
8
20
ns
0.75
1.9
0.682
1.9
0.625
1.9
ns
0.48
0.52
0.48
0.52
0.48
0.52
tCK
14
(AVG)
(AVG)
tCK
0.48
0.52
0.48
0.52
0.48
0.52
tJITper_tot
–38
38
-34
34
–32
32
ps
18 , 19
Deterministic
tJITper_dj
–19
19
-17
17
–16
16
ps
18
DLL locking
tJITper,lck
–30
30
-27
27
–25
25
Clock absolute period
tCK
(ABS)
MIN = tCK (AVG) MIN + tJITper_tot MIN; MAX = tCK (AVG) MAX +
tJITper_tot MAX
Clock absolute high pulse width
(includes duty cycle jitter)
tCH
(ABS)
0.45
–
0.45
–
0.45
–
Clock absolute low pulse width
(includes duty cycle jitter)
tCL
(ABS)
0.45
–
0.45
–
0.45
–
tCK
(AVG)
Cycle-to-cycle jitter
tJITcc
–
75
–
68
–
62
ps
–
60
–
55
–
62
ps
(AVG)
Clock period jitter
Total
351
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‹ 2014 Micron Technology, Inc. All rights reserved.
Total
DLL locking
ps
ps
tCK
(AVG)
_tot
tJITcc,lck
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters: 2666
Through 3200
Clock period average
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Table 158: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-2666
DDR4-2933
DDR4-3200
Reserved
Symbol
Min
Max
Min
Max
Min
Max
Cumulative error across 2 cycles
tERR2per
–55
55
-50
50
–46
46
ps
3 cycles
tERR3per
–66
66
-60
60
–55
55
ps
4 cycles
tERR4per
–73
73
-66
66
–61
61
ps
5 cycles
tERR5per
–78
78
-71
71
–65
65
ps
6 cycles
tERR6per
–83
83
-75
75
–69
69
ps
7 cycles
tERR7per
–87
87
-79
79
–73
73
ps
8 cycles
tERR8per
–91
91
-83
83
–76
76
ps
9 cycles
tERR9per
–94
94
-85
85
–78
78
ps
10 cycles
tERR10per
–96
96
-88
88
–80
80
ps
11 cycles
tERR11per
–99
99
-90
90
–83
83
ps
12 cycles
tERR12per
–101
101
-92
92
–84
84
ps
n = 13, 14 . . . 49,
50 cycles
tERRnper
tERRnper
tERRnper
Min
MIN = (1 + 0.68ln[n]) ×
tJITper_tot
MIN
MAX = (1 + 0.68ln[n]) ×
tJITper_tot
MAX
Max
Unit
ps
352
DQ Input Timing
Data setup time to
DQS_t, DQS_c
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
Data hold time from
DQS_t, DQS_c
Base (calibrated
VREF)
tDS
Refer to DQ Input Receiver Specification section
(approximately 0.15tCK to 0.28tCK )
–
Non-calibrated
VREF
tPDA_S
minimum of 0.5ui
UI
Base (calibrated
VREF)
tDH
Refer to DQ Input Receiver Specification section
(approximately 0.15tCK to 0.28tCK )
–
Non-calibrated
VREF
tPDA_H
minimum of 0.5UI
UI
DQ and DM minimum data pulse width
for each input
tDIPW
DQS_t, DQS_c to DQ skew, per group, per
access
tDQSQ
–
0.18
–
DQ output hold time from DQS_t, DQS_c
tQH
0.74
–
d
0.64
p
0.72
0.58
–
0.58
–
0.58
–
UI
0.19
–
0.22
UI
0.74
–
0.74
–
UI
–
0.64
–
0.64
–
UI
–
0.72
–
0.72
–
UI
DQ Output Timing (DLL enabled)
tQH
Data Valid Window per device:
tDQSQ each device’s output per IU
tDVW
Data Valid Window per device, per pin:
- tDQSQ each device’s output per IU
tDVW
tQH
Notes
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters: 2666
Through 3200
Parameter
09005aef84af6dd0
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Table 158: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-2666
DDR4-2933
DDR4-3200
Symbol
Min
Max
Min
Max
Min
Max
DQ Low-Z time from CK_t, CK_c
tLZDQ
–310
170
–280
165
–250
160
ps
DQ High-Z time from CK_t, CK_c
tHZDQ
–
170
–
165
–
160
ps
Parameter
Reserved
Min
Max
Unit
Notes
DQ Strobe Input Timing
DQS_t, DQS_c rising edge to CK_t, CK_c
rising edge for 1tCKpreamble
tDQSS
1ck
–0.27
0.27
–0.27
0.27
–0.27
0.27
CK
DQS_t, DQS_c rising edge to CK_t, CK_c
rising edge for 2tCKpreamble
tDQSS
2ck
–0.50
0.50
–0.50
0.50
–0.50
0.50
CK
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
tDQSL
0.46
0.54
0.46
0.54
0.46
0.54
CK
DQS_t, DQS_c differential input high
pulse width
tDQSH
0.46
0.54
0.46
0.54
0.46
0.54
CK
DQS_t, DQS_c falling edge setup to CK_t,
CK_c rising edge
tDSS
0.18
–
0.18
–
0.18
–
CK
DQS_t, DQS_c falling edge hold from
CK_t, CK_c rising edge
tDSH
0.18
–
0.18
–
0.18
–
CK
DQS_t, DQS_c differential WRITE preamble for 1tCKpreamble
tWPRE
1ck
0.9
–
0.9
–
0.9
–
CK
DQS_t, DQS_c differential WRITE preamble for 2tCKpreamble
tWPRE
2ck
1.8
–
1.8
–
1.8
–
CK
DQS_t, DQS_c differential WRITE postamble
tWPST
0.33
–
0.33
–
0.33
–
CK
DQS Strobe Output Timing (DLL enabled)
DQS_t, DQS_c rising edge output access
time from rising CK_t, CK_c
tDQSCK
–170
170
–165
165
–160
160
ps
DQS_t, DQS_c rising edge output variance window per DRAM
tDQSCKi
–
270
–
265
–
260
ps
DQS_t, DQS_c differential output high
time
tQSH
0.40
–
0.40
–
0.40
–
CK
DQS_t, DQS_c differential output low
time
tQSL
0.40
–
0.40
–
0.40
–
CK
DQS_t, DQS_c Low-Z time (RL - 1)
tLZDQS
–310
170
–280
165
–250
160
ps
DQS_t, DQS_c High-Z time (RL + BL/2)
tHZDQS
–
170
–
165
–
160
ps
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters: 2666
Through 3200
353
DQS_t, DQS_c differential input low pulse
width
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Table 158: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-2666
DDR4-2933
DDR4-3200
Parameter
Symbol
Min
Max
Min
Max
Min
Max
DQS_t, DQS_c differential READ preamble for 1tCKpreamble
tRPRE
1ck
0.9
–
0.9
–
0.9
DQS_t, DQS_c differential READ preamble for 2tCKpreamble
tRPRE
2ck
1.8
–
1.8
–
DQS_t, DQS_c differential READ postamble
tRPST
0.33
–
0.33
–
DLL locking time
tDLLK
Reserved
Min
Max
Unit
Notes
–
CK
21
1.8
–
CK
21
0.33
–
CK
22
1024
–
CK
2, 3
Command and Address Timing
354
CMD, ADDR hold time
to CK_t, CK_c referenced to VIH(DC) and
VIL(DC) levels
Base
VREFCA
–
55
tIS
VREF
145
tIH
tIH
VREF
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
CTRL, ADDR pulse width for each input
tIPW
ACTIVATE to internal READ or WRITE delay
tRCD
PRECHARGE command period
940
–
–
48
–
40
–
ps
–
138
–
130
–
ps
80
–
73
–
65
–
ps
145
–
138
–
130
–
ps
385
–
365
–
350
–
ps
See Speed Bin Tables for
tRP
ACTIVATE-to-PRECHARGE command period
tRAS
ACTIVATE-to-ACTIVATE or REF command
period
tRC
ACTIVATE-to-ACTIVATE command period
to different bank groups for 1/2KB page
size
tRRD_S
(1/2KB)
ACTIVATE-to-ACTIVATE command period
to different bank groups for 1KB page
size
tRRD_S
ACTIVATE-to-ACTIVATE command period
to different bank groups for 2KB page
size
tRRD_S
(1KB)
(2KB)
tRCD
See Speed Bin Tables for tRP
See Speed Bin Tables for
tRAS
See Speed Bin Tables for tRC
ns
ns
ns
13
ns
13
MIN = greater
of 4CK or 3.0ns
MIN = greater
of 4CK or 2.7ns
MIN = greater
of 4CK or 2.5ns
CK
1
MIN = greater
of 4CK or 3.0ns
MIN = greater
of 4CK or 2.7ns
MIN = greater
of 4CK or 2.5ns
CK
1
MIN = greater
of 4CK or 5.3ns
MIN = greater
of 4CK or 5.3ns
MIN = greater
of 4CK or 5.3ns
CK
1
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters: 2666
Through 3200
CMD, ADDR setup time Base
to CK_t, CK_c referVREFCA
enced to VIH(AC) and
VIL(AC) levels
854
tIS
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Table 158: Electrical Characteristics and AC Timing Parameters (Continued)
Parameter
ACTIVATE-to-ACTIVATE command period
to same bank groups for 1/2KB page size
Symbol
tRRD_L
(1/2KB)
tRRD_L
ACTIVATE-to-ACTIVATE command period
to same bank groups for 2KB page size
tRRD_L
Four ACTIVATE windows for 1/2KB page
size
tFAW
Four ACTIVATE windows for 1KB page
size
Four ACTIVATE windows for 2KB page
size
WRITE recovery time
(1KB)
(2KB)
(1/2KB)
tFAW
(1KB)
tFAW
(2KB)
DDR4-2933
DDR4-3200
Min
Min
Min
Max
Max
Notes
CK
1
MIN = greater
of 4CK or 4.9ns
MIN = greater
of 4CK or 4.9ns
MIN = greater
of 4CK or 4.9ns
CK
1
MIN = greater
of 4CK or 6.4ns
MIN = greater
of 4CK or 6.4ns
MIN = greater
of 4CK or 6.4ns
CK
1
MIN = greater
of 16CK or 12ns
MIN = greater
of 16CK or
10.875ns
MIN = greater
of 16CK or 10ns
ns
MIN = greater
MIN = greater
MIN = greater
of 20CK or 21ns of 20CK or 21ns of 20CK or 21ns
ns
MIN = greater
MIN = greater
MIN = greater
of 28CK or 30ns of 28CK or 30ns of 28CK or 30ns
ns
355
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‹ 2014 Micron Technology, Inc. All rights reserved.
ns
5, 10, 1
CK
5, 11, 1
CK
6, 10, 1
MIN = 1CK + tWR_CRC_DM
CK
6, 11, 1
MIN = greater of 4CK or 7.5ns
CK
5, 10, 1
CK
5, 11, 1
MIN = tWTR_L + greater of (5CK or 3.75ns)
CK
6, 10, 1
MIN = 1CK + tWTR_L_CRC_DM
CK
6, 11, 1
tWTR_S
MIN = greater of (2CK or 2.5ns)
CK
5, 7, 8,
10, 1
tWTR_S
2
MIN = 1CK + tWTR_S
CK
5, 7, 8,
11, 1
tWTR_S_CRC_D
MIN = tWTR_S + greater of (5CK or 3.75ns)
CK
6, 7, 8,
10, 1
MIN = 1CK + tWTR_S_CRC_DM
CK
6, 7, 8,
11, 1
MIN = 1CK +
WRITE recovery time when CRC and DM
are both enabled
tWR_CRC_DM
Delay from start of internal WRITE transaction to internal READ command – Different bank group when CRC and DM are
both enabled
Unit
MIN = greater
of 4CK or 4.9ns
MIN = 15ns
WRITE recovery time when CRC and DM
are both enabled
Delay from start of internal WRITE transaction to internal READ command – Different bank group
Max
MIN = greater
of 4CK or 4.9ns
tWR
tWR_CRC_DM
Delay from start of internal WRITE transaction to internal READ command – Same
bank group when CRC and DM are both
enabled
Min
MIN = greater
of 4CK or 4.9ns
tWR
2
Delay from start of internal WRITE transaction to internal READ command – Same
bank group
Max
Reserved
2
tWTR_L
tWTR_L
2
tWTR_L_CRC_D
MIN =
tWR
tWR
+ greater of (5CK or 3.75ns)
MIN = 1CK +
tWTR_L
M
tWTR_L_CRC_D
M2
M
tWTR_S_CRC_D
M2
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters: 2666
Through 3200
ACTIVATE-to-ACTIVATE command period
to same bank groups for 1KB page size
DDR4-2666
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Table 158: Electrical Characteristics and AC Timing Parameters (Continued)
Parameter
READ-to-PRECHARGE time
Symbol
DDR4-2666
DDR4-2933
DDR4-3200
Min
Max
Min
Min
tRTP
Max
Max
Reserved
Min
MIN = greater of 4CK or 7.5ns
Max
Unit
Notes
CK
1
CAS_n-to-CAS_n command delay to different bank group
tCCD_S
4
–
4
–
4
–
CK
CAS_n-to-CAS_n command delay to same
bank group
tCCD_L
MIN =
greater
of 4CK
or 5ns
–
MIN =
greater
of 4CK
or 5ns
–
MIN =
greater
of 4CK
or 5ns
–
CK
tDAL
MIN = WR + ROUNDUPtRP/tCK (AVG); MAX = N/A
(MIN)
CK
MRS Command Timing
MRS command cycle time
tMRD
8
–
8
–
8
–
MRS command cycle time in PDA mode
tMRD_PDA
MIN = greater of (16nCK, 10ns)
MRS command cycle time in CAL mode
tMRD_CAL
tMOD
MIN =
+
tCAL
CK
1
CK
tMOD
MIN = greater of (24nCK, 15ns)
CK
MRS command update delay in PDA
mode
tMOD_PDA
MIN = tMOD
CK
MRS command update delay in CAL
mode
tMOD_CAL
MIN = tMOD + tCAL
CK
tSDO
MIN = tMOD + 9ns
MRS command update delay
356
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‹ 2014 Micron Technology, Inc. All rights reserved.
MRS command to DQS drive in preamble
training
MPR Command Timing
tMPRR
MIN = 1nCK
Multipurpose register write recovery time
tWR_MPRR
MIN = tMOD + AL + PL
CRC error to ALERT_n latency
tCRC_ALERT
3
13
3
13
3
13
ns
tCRC_ALERT_P
6
10
6
10
6
10
CK
Multipurpose register recovery time
CK
CRC Error Reporting Timing
CRC ALERT_n pulse width
W
CA Parity Timing
Parity latency
Commands uncertain to be executed during this time
Delay from errant command to ALERT_n
assertion
PL
5
–
6
–
6
–
CK
tPAR_UN-
–
PL
–
PL
–
PL
CK
–
PL +
6ns
–
PL +
6ns
–
PL +
6ns
CK
KNOWN
tPAR_ALERT_O
N
1
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters: 2666
Through 3200
Auto precharge write recovery + precharge time
15
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Table 158: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-2666
DDR4-2933
DDR4-3200
Symbol
Min
Max
Min
Max
Min
Max
Pulse width of ALERT_n signal when asserted
tPAR_ALERT_P
80
160
88
176
96
192
CK
Time from alert asserted until DES commands required in persistent CA parity
mode
tPAR_ALERT_RS
–
71
–
78
–
85
CK
Parameter
Reserved
Min
Max
Unit
Notes
W
P
CAL Timing
tCAL
5
–
6
–
6
–
CK
CS_n to command address latency in
gear-down mode
tCALg
6
–
8
–
8
–
CK
Command path disable delay upopn
MPSM entry
tMPED
MIN = tMOD (MIN) + tCPDED (MIN)
CK
1
Valid clock requirement after MPSM
entry
tCKMPE
MIN = tMOD (MIN) + tCPDED (MIN)
CK
1
Valid clock requirement before MPSM
exit
tCKMPX
MIN = tCKSRX (MIN)
CK
1
CS_n to command address latency
20
357
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‹ 2014 Micron Technology, Inc. All rights reserved.
Exit MPSM to commands not requiring a
locked DLL
tXMP
tXS
(MIN)
CK
tXMPDLL
MIN = tXMP (MIN) + tXSDLL (MIN)
tMPX_S
MIN = tIS (MIN) + tIH (MIN)
ns
CS_n HIGH hold time to CKE rising edge
tMPX_HH
MIN = tXP
ns
CS_n LOW hold time to CKE rising edge
tMPX_LH
Exit MPSM to commands requiring a
locked DLL
CS setup time to CKE
12
tXMP-1
12
tXMP-1
0ns
12
0ns
tXMP-1
CK
ns
0ns
Connectivity Test Timing
TEN pin HIGH to CS_n LOW – Enter CT
mode
tCT_Enable
200
–
200
–
200
–
ns
CS_n LOW and valid input to valid output
tCT_Valid
–
200
–
200
–
200
ns
CK_t, CK_c valid and CKE HIGH after TEN
goes HIGH
tCTCKE_Valid
10
–
10
–
10
–
ns
Calibration and VREFDQ Train Timing
1
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters: 2666
Through 3200
MPSM Timing
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Table 158: Electrical Characteristics and AC Timing Parameters (Continued)
Parameter
ZQCL command: Long
calibration time
POWER-UP and
RESET operation
Normal operation
ZQCS command: Short calibration time
The VREF increment/decrement step time
Exit VREFDQ training mode to the first
WRITE command delay
DDR4-2933
DDR4-3200
Reserved
Symbol
Min
Max
Min
Max
Min
Max
tZQinit
1024
–
1024
–
1024
–
CK
tZQoper
512
–
512
–
512
–
CK
tZQCS
128
–
128
–
128
–
CK
Min
Max
Unit
Notes
VREF_time
tVREFDQE
MIN = 150ns
MIN = 150ns
ns
1
tVREFDQX
MIN = 150ns
ns
1
MIN = greater of 5CK or tRFC (MIN) + 10ns
CK
1
Initialization and Reset Timing
Exit reset from CKE HIGH to a valid command
tXPR
358
RESET_L pulse low after power stable
tPW_REST_S
0.1
–
0.1
–
0.1
–
μs
RESET_L pulse low at power-up
tPW_REST_L
200
–
200
–
200
–
μs
Begin power supply ramp to power supplies stable
tVDDPR
MIN = N/A; MAX = 200
ms
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.
RESET_n LOW to power supplies stable
tRPS
MIN = 0; MAX = 0
ns
RESET_n LOW to I/O and RTT High-Z
tIOZ
MIN = N/A; MAX = undefined
ns
Refresh Timing
REFRESH-to-ACTIVATE
or REFRESH command
period (all bank
groups)
tRFC1
MIN = 260
ns
1, 12
tRFC2
MIN = 160
ns
1, 12
tRFC4
MIN = 110
ns
1, 12
tRFC1
MIN = 350
ns
1, 12
tRFC2
MIN = 260
ns
1, 12
tRFC4
MIN = 160
ns
1, 12
tRFC1
MIN = 550
ns
1, 12
tRFC2
MIN = 350
ns
1, 12
tRFC4
MIN = 260
ns
1, 12
0°C ≤ TC ≤ 85°C
tREFI
MIN = N/A; MAX = 7.8
μs
12
85°C < TC ≤ 95°C
tREFI
MIN = N/A; MAX = 3.9
μs
12
4Gb
8Gb
16Gb
Average periodic refresh interval
Self Refresh Timing
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters: 2666
Through 3200
Enter VREFDQ training mode to the first
write or VREFDQ MRS command delay
DDR4-2666
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Table 158: Electrical Characteristics and AC Timing Parameters (Continued)
Parameter
Exit self refresh to commands not requiring a locked DLL SRX to commands not
requiring a locked DLL in self refresh
abort
Symbol
DDR4-2666
DDR4-2933
Min
Min
Max
DDR4-3200
Max
tXS
MIN =
tRFC
Min
Min
Max
+ 10ns
tXS_ABORT
MIN = tRFC4 + 10ns
tXS_FAST
MIN = tRFC4 + 10ns
Exit self refresh to commands requiring a
locked DLL
tXSDLL
tDLLK
Minimum CKE low pulse width for self refresh entry to self refresh exit timing
tCKESR
Minimum CKE low pulse width for self refresh entry to self refresh exit timing
when CA parity is enabled
Exit self refresh to ZQCL, ZQCS and MRS
(CL, CWL, WR, RTP and gear-down)
Max
Reserved
Unit
Notes
ns
1
ns
1
1
ns
MIN =
(MIN)
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‹ 2014 Micron Technology, Inc. All rights reserved.
1
MIN = tCKE (MIN) + 1nCK
CK
1
tCKESR_par
MIN = tCKE (MIN) + 1nCK + PL
CK
1
Valid clocks after self refresh entry (SRE)
or power-down entry (PDE)
tCKSRE
MIN = greater of (5CK, 10ns)
CK
1
Valid clock requirement after self refresh
entry or power-down when CA parity is
enabled
tCKSRE_par
MIN = greater of (5CK, 10ns) + PL
CK
1
Valid clocks before self refresh exit (SRX)
or power-down exit (PDX), or reset exit
tCKSRX
MIN = greater of (5CK, 10ns)
CK
1
Exit power-down with DLL on to any valid command
tXP
MIN = greater of 4CK or 6ns
CK
1
MIN = (greater of 4CK or 6ns) + PL
CK
1
MIN = greater of 3CK or 5ns
CK
1
4
CK
Power-Down Timing
Exit precharge power-down with DLL frozen to commands not requiring a locked
DLL when CA Parity is enabled.
CKE MIN pulse width
Command pass disable delay
tXP
tCKE
_PAR
(MIN)
tCPDED
4
–
–
4
–
Power-down entry to power-down exit
timing
tPD
MIN = tCKE (MIN); MAX = 9 × tREFI
CK
Begin power-down period prior to CKE
registered HIGH
tANPD
WL - 1CK
CK
PDE
Greater of tANPD or tRFC - REFRESH command to CKE LOW time
CK
Power-down entry period: ODT either
synchronous or asynchronous
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters: 2666
Through 3200
359
CK
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
Table 158: Electrical Characteristics and AC Timing Parameters (Continued)
Parameter
Symbol
DDR4-2666
DDR4-2933
Min
Min
Max
DDR4-3200
Max
Min
tANPD
tXSDLL
Max
Reserved
Min
Max
Unit
Power-down exit period: ODT either synchronous or asynchronous
PDX
ACTIVATE command to power-down entry
tACTPDEN
2
–
2
–
2
–
CK
PRECHARGE/PRECHARGE ALL command
to power-down entry
tPRPDEN
2
–
2
–
2
–
CK
REFRESH command to power-down entry
tREFPDEN
2
–
2
–
2
–
CK
MRS command to power-down entry
tMRSPDEN
+
Notes
CK
Power-Down Entry Minimum Timing
360
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‹ 2014 Micron Technology, Inc. All rights reserved.
CK
1
READ/READ with auto precharge command to power-down entry
tRDPDEN
MIN = RL + 4 + 1
(MIN)
CK
1
WRITE command to power-down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRPDEN
MIN = WL + 4 + tWR/tCK (AVG)
CK
1
WRITE command to power-down entry
(BC4MRS)
tWRPBC4DEN
MIN = WL + 2 + tWR/tCK (AVG)
CK
1
WRITE with auto precharge command to
power-down entry (BL8OTF,
BL8MRS,BC4OTF)
tWRAPDEN
MIN = WL + 4 + WR + 1
CK
1
WRITE with auto precharge command to
power-down entry (BC4MRS)
tWRAPBC4DEN
MIN = WL + 2 + WR + 1
CK
1
WL - 2 = CWL + AL + PL - 2
CK
ODT Timing
Direct ODT turn-on latency
DODTLon
Direct ODT turn-off latency
DODTLoff
WL - 2 = CWL + AL + PL - 2
CK
tADC
0.3
0.7
0.28
0.72
0.28
0.72
CK
Asynchronous RTT(NOM) turn-on delay
(DLL off)
tAONAS
1
9
1
9
1
9
ns
Asynchronous RTT(NOM) turn-off delay
(DLL off)
tAOFAS
1
9
1
9
1
9
ns
ODT HIGH time with WRITE command
and BL8
ODTH8 1tCK
6
–
6
–
6
–
CK
ODTH8
2tCK
7
–
7
–
7
–
ODTH4
1tCK
4
–
4
–
4
–
ODTH4 2tCK
5
–
5
–
5
–
RTT dynamic change skew
ODT HIGH time without WRITE command
or with WRITE command and BC4
Write Leveling Timing
CK
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters: 2666
Through 3200
MIN =
tMOD
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Table 158: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-2666
DDR4-2933
DDR4-3200
Reserved
Symbol
Min
Max
Min
Max
Min
Max
First DQS_t, DQS_c rising edge after write
leveling mode is programmed
tWLMRD
40
–
40
–
40
–
CK
tWLDQSEN
25
–
25
–
25
–
CK
Write leveling setup from rising CK_t,
CK_c crossing to rising DQS_t, DQS_c
crossing
tWLS
0.13
–
0.13
–
0.13
–
CK
Write leveling hold from rising DQS_t,
DQS_c crossing to rising CK_t, CK_c crossing
tWLH
0.13
–
0.13
–
0.13
–
CK
Write leveling output delay
tWLO
0
9.5
0
9.5
0
9.5
ns
Write leveling output error
tWLOE
0
2
0
2
0
2
ns
DQS_t, DQS_c delay after write leveling
mode is programmed
Min
Max
Unit
Gear-Down Timing
361
Exit reset from CKE HIGH to a valid MRS
gear-down
CKE HIGH assert to gear-down enable
time)
tXPR_GEAR
tXPR
tXPR
tXPR
CK
tXS_GEAR
tXS
tXS
tXS
CK
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‹ 2014 Micron Technology, Inc. All rights reserved.
MRS command to sync pulse time
tSYNC_GEAR
Sync pulse to first valid command
tCMD_GEAR
tMOD
Gear-down setup time
tGEAR_setup
2CK
–
2CK
–
2CK
–
CK
Gear-down hold time
tGEAR_hold
2CK
–
2CK
–
2CK
–
CK
+ 4CK
tMOD
tMOD
+ 4CK
tMOD
tMOD
+ 4CK
tMOD
CK
CK
Notes
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters: 2666
Through 3200
Parameter
4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters: 2666
Through 3200
Notes:
1. Maximum limit not applicable.
2. tCCD_L and tDLLK should be programmed according to the value defined per operating
frequency.
3. Data rate is greater than or equal to 1066 Mb/s.
4. RFU.
5. WRITE-to-READ when CRC and DM are both not enabled.
6. WRITE-to-READ delay when CRC and DM are both enabled.
7. The start of internal write transactions is defined as follows:
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
• For BL8 (fixed by MRS and on-the-fly): rising clock edge four clock cycles after WL
• For BC4 (on-the-fly): rising clock edge four clock cycles after WL
• For BC4 (fixed by MRS): rising clock edge two clock cycles after WL
For these parameters, the device supports tnPARAM [nCK] = RU{tPARAM [ns]/tCK (AVG)
[ns]}, in clock cycles, assuming all input clock jitter specifications are satisfied.
Although unlimited row accesses to the same row is allowed within the refresh period,
excessive row accesses to the same row over a long term can result in degraded operation.
When operating in 1tCK WRITE preamble mode.
When operating in 2tCK WRITE preamble mode.
When CA parity mode is selected and the DLLoff mode is used, each REF command requires an additional "PL" added to tRFC refresh time.
DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row address may result in reduction of the product lifetime and/or
reduction in data retention ability.
Applicable from tCK (AVG) MIN to tCK (AVG) MAX as stated in the Speed Bin tables.
JEDEC specifies a minimum of five clocks.
The maximum read postamble is bound by tDQSCK (MIN) plus tQSH (MIN) on the left
side and tHZ(DQS) MAX on the right side.
The reference level of DQ output signal is specified with a midpoint as a widest part of
output signal eye, which should be approximately 0.7 × VDDQ as a center level of the
static single-ended output peak-to-peak swing with a driver impedance of 34 ohms and
an effective test load of 50 ohms to VTT = VDDQ.
JEDEC hasn't agreed upon the definition of the deterministic jitter; the user should focus on meeting the total limit.
Spread spectrum is not included in the jitter specification values. However, the input
clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with
an additional 1% of tCK (AVG) as a long-term jitter component; however, the spread
spectrum may not use a clock rate below tCK (AVG) MIN.
The actual tCAL minimum is the larger of 3 clocks or 3.748ns/tCK; the table lists the applicable clocks required at targeted speed bin.
The maximum READ preamble is bounded by tLZ(DQS) MIN on the left side and tDQSCK
(MAX) on the right side. See figure in Clock to Data Strobe Relationship. Boundary of
DQS Low-Z occur one cycle earlier in 2tCK toggle mode which is illustrated in READ Preamble.
DQ falling signal middle-point of transferring from HIGH to LOW to first rising edge of
DQS differential signal cross-point.
362
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Converting Time-Based Specifications to Clock-Based Requirements
Converting Time-Based Specifications to Clock-Based Requirements
Software algorithms for calculation of timing parameters are subject to potential rounding errors when converting DRAM timing requirements to system clocks; for example, a
memory clock with a nominal frequency of 933.33...3 MHz, or a clock period of
1.071428571429...ns. Similarly, a system with a memory clock frequency of 1066.66...6
MHz mathematically yields a clock period of 0.9375ns. It is unrealistic to represent all
digits after the decimal point exactly and some sort of rounding needs to be done.
DDR4 SDRAM SPD-based specifications use a minimum granularity for SPD-associated
timing parameters of 1ps. Clock periods such as tCK (AVG) MIN are defined to the nearest picosecond. For example, 0.9375ns is stated as 937ps and 1.0714ns is stated as
1071ps. Parameters such as tAA MIN, and tRCD MIN are specified in units of time
(nanoseconds) and require mathematical computation to convert to system clocks
(nCK). Rules for rounding allows optimization of device performance without violating
device parameters. These SPD algorithms rely on results that are within adjustment factors on device testing and specification to avoid losing performance due to rounding errors when using SPD-based parameters.
Guidance converting SPD associated timing parameters to system clock requirements:
• Divide the time base specification (in ns) by the clock period (in ns).
• Subtract an adjustment factor of 0.025. This is results in a –2.5% tCK adjustment factor.
• The resultant is set to the next higher integer number of clocks.
• nCK = ceiling [ (parameter in ns / application tCK in ns) - 0.025 ].
Alternatively, the following algorithm provides the same results as above:
• Use integer math expressing timing specification and application clock period in picoseconds; scaling a nanosecond-based parameter value by 1000.
• Divide the picosecond-based parameter by the picoseconds based application clock
period.
• Add an inverse adjustment factor of 97.4%.
• Divide the result by 1000.
• Truncate down to the next lower integer value.
• nCK = truncate [ {(parameter in ps × 1000) / (application tCK in ps) + 974} / 1000 ].
Guidance converting nonSPD associated timing parameters to system clock requirements:
• Divide the time base specification (in ns) and divided by the clock period (in ns).
• The resultant is set to the next higher integer number of clocks.
• nCK = ceiling [ (parameter in ns / application tCK in ns) ].
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4Gb: x4, x8, x16 DDR4 SDRAM
Options Tables
Options Tables
Table 159: Options - Speed Based
Data Rate
Function
Acronym
1600
1866
2133
2400
2666
2933
3200
Write leveling
WL
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Temperature controlled refresh
TCR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
LPASR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
FGR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Low-power auto self refresh
Fine granularity refresh
Multipurpose register
MR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Data mask
DM
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Data bus inversion
DBI
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–
Yes
Yes
Yes
Yes
Yes
Yes
Yes
TDQS
ZQ calibration
VREFDQ calibration
Per-DRAM addressability
Mode register readout
ZQ CAL
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Per DRAM
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Command/Address latency
CAL
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Write CRC
CRC
Yes
Yes
Yes
Yes
Yes
Yes
Yes
CA parity
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Gear-down mode
-
No
No
No
No
Yes
Yes
Yes
Programmable preamble
–
No
No
No
Yes
Yes
Yes
Yes
MPSM
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Additive latency
AL
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Connectivity test mode
CT
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Maximum power saving mode
Hard post package repair mode
hPPR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Soft post package repair mode
sPPR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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‹ 2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Options Tables
Table 160: Options - Width Based
Width
Function
Acronym
x4
x8
x16
Write leveling
WL
Yes
Yes
Yes
Temperature controlled refresh
TCR
Yes
Yes
Yes
LPASR
Yes
Yes
Yes
FGR
Yes
Yes
Yes
Multipurpose register
MR
Yes
Yes
Yes
Data mask
DM
No
Yes
Yes
Data bus inversion
DBI
No
Yes
Yes
–
No
Yes
No
ZQ CAL
Yes
Yes
Yes
–
Yes
Yes
Yes
Per DRAM
Yes
Yes
Yes
–
Yes
Yes
Yes
Command/Address latency
CAL
Yes
Yes
Yes
Write CRC
CRC
Yes
Yes
Yes
CA parity
–
Yes
Yes
Yes
Gear-down mode
–
Yes
Yes
Yes
Low-power auto self refresh
Fine granularity refresh
TDQS
ZQ calibration
VREFDQ calibration
Per-DRAM addressability
Mode regsiter readout
Programmable preamble
–
Yes
Yes
Yes
MPSM
Yes
Yes
No
Additive latency
AL
Yes
Yes
Yes
Connectivity test mode
CT
Maximum power-down mode
JEDEC optional on 8Gb and larger densities
Micron supports on all densities
Hard post package repair mode
hPPR
JEDEC optional on 4Gb
Micron supports on all densities
Soft post package repair mode
sPPR
JEDEC optional on 4Gb and 8Gb
Micron supports on all densities
Yes
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www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
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‹ 2014 Micron Technology, Inc. All rights reserved.