EVALUATION KIT AVAILABLE MAX17525 High-Accuracy, Adjustable Power Limiter General Description Benefits and Features The MAX17525 adjustable overvoltage, undervoltage, and overcurrent protection device guards systems against overcurrent faults in addition to positive overvoltage and reverse-voltage faults. When used with an optional external pMOSFET, the device also protects downstream circuitry from voltage faults up to ±60V (for -60V external pFET rating. The device features a low, 31mΩ, on-resistance integrated FET. During startup, the devices are designed to charge large capacitances on the output in a continuous mode for applications where large reservoir capacitors are used on the inputs to downstream devices. Additionally, the devices feature a dual-stage, current-limit mode in which the current is continuously limited to 1x, 1.5x, and 2x the programmed limit, respectively, for a short time after startup. This enables faster charging of large loads during startup. The MAX17525 also feature reverse-current and overtemperature protection. The devices are available in a 20-pin (5mm x 5mm) TQFN package and operate over the -40ºC to 125ºC temperature range. ●● Robust, High-Power Protection Reduces System Downtime • Wide Operating Input Range: +5.5V to +60V • -60V Negative Input Tolerance with External pFET (for -(60 + VOUT) External pFET Rating) • Low 31mΩ (typ) RON • Reverse Current-Blocking Protection with External pFET ●● Enables Fast Startup and Brownout Recovery • Thermal Foldback Current-Limit Protection ●● Flexible Design Enables Reuse and Less Requalification • Adjustable OVLO and UVLO Thresholds • Programmable Forward Current Limit From 0.6A to 6A with ±15% Accuracy Over Full Temperature Range • Normal and High-Voltage Enable Inputs (EN and HVEN) • Protected External pFET Gate Drive ●● Saves Board Space and Reduces External BOM Count • 20-Pin 5mm x 5mm TQFN Package • Integrated nFET Applications ●● ●● ●● ●● ●● Industrial Power Systems Control and Automation Motion System Drives Human Machine Interfaces High-Power Applications Ordering Information appears at end of data sheet. Typical Application Circuit VIN *R1, R2, R3, AND R 4 ARE ONLY REQURED FOR ADJUSTABLE UVLO/OVLO FUNCTIONALITY . OTHERWISE , TIE THE PIN TO GND TO USE THE INTERNAL , PRE-PROGRAMMED POWER THRESHOLD . SYSTEM INPUT HVEN CIN CIN_IC GP VIN R1* 220kΩ IN IN IN OUT OUT MAX17525 R3* OUT OUT OVLO SYSTEM CONTROLLER PROTECTED POWER ADC COUT OUT R4* SETI GND x 10kΩ 19-8572; Rev 0; 6/16 IN UVLO R2* VIN IN HVEN RIPEN CLTS2 FLAG CLTS1 EN GND ENB FAULT EN MAX17525 High-Accuracy, Adjustable Power Limiter Absolute Maximum Ratings (All voltages referenced to GND.) IN (Note 1)..............................................................-0.3V to +62V OUT............................................................... -0.3V to VIN + 0.3V HVEN (Note 1).............................................. -0.3V to VIN + 0.3V GP......................................max (-0.3V, VIN - 20V) to VIN + 0.3V UVLO, OVLO................................-0.3V to min (VIN + 0.3V, 20V) FLAG, EN, RIPEN, CLTS1, CLTS2..........................-0.3V to +6V Maximum Current Into IN (DC) (Note 2)..................................6A SETI...............................................-0.3V to min (VIN + 0.3V, 6V) Continuous Power Dissipation (TA = +70ºC) TQFN (derate 34.5mW/ºC above +70ºC)...................2758mW Operating Temperature Range...........................-40ºC to +125°C Junction Temperature.......................................................+150°C Storage Temperature Range..............................-65ºC to +150°C Lead Temperature (soldering, 10s).................................. +300°C Soldering Temperature (reflow)........................................+260°C Note 1: An external pFET or diode is required to achieve negative input protection. Note 2: DC current-limited by RSETI, as well as by thermal design. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Thermal Characteristics (Note 3) TQFN Junction-to-Ambient Thermal Resistance (θJA)...........29°C/W Junction-to-Case Thermal Resistance (θJC)..................2°C/W Note 3: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Electrical Characteristics (VIN = 5.5V to 60V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VIN = 12V, TA = +25°C) (Note 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 60 V POWER SUPPLY IN Voltage Range Shutdown IN Current Supply Current Shutdown OUT Current VIN ISHDN IIN IOFF 5.5 VEN = 0V, VHVEN = 5V, VIN < 40V 4 15 VEN = 0V, VHVEN = 5V 4 150 VIN = VOUT = 24V, VHVEN = 0V 1.4 2.16 mA VEN = 0V, VHVEN = 5V 50 100 µA µA UVLO, OVLO Internal UVLO Trip Level VUVLO UVLO Hysteresis Internal OVLO Trip Level VIN falling, UVLO trip point 11.5 12 12.5 VIN rising 11.9 12.4 13.1 VIN falling 32.2 34.1 35.8 VIN rising, OVLO trip point 34.7 36.2 37.6 % of typical UVLO VOVLO OVLO Hysteresis External UVLO Adjustment Range (Note 5) 3 % of typical OVLO % 6 5.5 V V % 24 V 0.5 V External UVLO Select Voltage VUVLO_SEL 0.15 External UVLO Leakage Current IUVLO_LEAK -250 +250 nA 6 40 V External OVLO Adjustment Range (Note 5) External OVLO Select Voltage VOVLO_SEL 0.15 External OVLO Leakage Current IOVLO_LEAK -250 VSET 1.18 External UVLO/OVLO Set Voltage www.maximintegrated.com 0.38 0.38 1.22 0.5 V +250 nA 1.27 V Maxim Integrated │ 2 MAX17525 High-Accuracy, Adjustable Power Limiter Electrical Characteristics (continued) (VIN = 5.5V to 60V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VIN = 12V, TA = +25°C) (Note 4) PARAMETER Undervoltage Trip Level on OUT SYMBOL VUVLO_OUT MIN TYP MAX VOUT falling, UVLO trip point CONDITIONS 11.5 12 12.5 UNITS VOUT rising 11.9 12.4 13 10 16.1 20 11 22 47 110 µA MΩ V GP Gate Clamp Voltage VGP Gate Active Pullup Gate Active Pulldown VEN = 5V Shutdown Gate Active Pullup VEN = 0V, VHVEN = 5V 2.4 ILOAD = 100mA, VIN ≥ 10V, TA = +25ºC 31 V Ω INTERNAL FETs Internal FETs On-Resistance RON Current Limit Adjustment Range ILIM Current Limit Accuracy FLAG Assertion Drop Voltage Threshold ILIM_ACC VFA 44 mΩ 0.6 6 A 1A ≤ ILIM ≤ 6A (TA = +25°C) -10 +10 0.6A ≤ ILIM ≤ 6A -15 +15 Increase in (VIN - VOUT) drop until FLAG asserts, VIN = 24V Slow Reverse Current-Blocking Threshold VRIB_SLOW VIN - VOUT Slow Reverse Current-Blocking Response Time tRIB_SLOW See the Slow Reverse-Current Fault Timing Diagram Fast Reverse Current-Blocking Threshold VRIB_FAST VIN - VOUT tRIB_FAST (VIN - VOUT) changes from 0.2V to -0.3V in 100nsec, tRIB is the interval between VIN - VOUT = VRIB_FAST and VIN-GP = 0.5V with CIN-GP = 5nF Fast Reverse Current-Blocking Response Time Reverse-Blocking Supply Current IRBS 490 -0.5 -85 VOUT = 24V % mV -5.4 -10.5 mV 17 30 µs -100 -115 mV 0.7 1 µs 3280 5110 µA 2 3.1 V 72 µA LOGIC INPUT (HVEN, CLTS1, CLTS2, EN, RIPEN) HVEN Threshold Voltage VHVEN _TH 1 HVEN Threshold Hysteresis HVEN Input Leakage Current 5 IHVEN_LEAK EN, RIPEN, CLTS1, CLTS2 Input Logic-High VIH EN, RIPEN, CLTS1, CLTS2 Input Logic-Low VIL EN Input Leakage Current IEN_LEAK CLTS_ Leakage Current RIPEN Leakage Current www.maximintegrated.com IRIBEN_LEAK VHVEN = 60V 51 % 1.4 VEN = 0V, 5V V -1 0.4 V +1 µA CLTS_ = GND 25 µA RIPEN = GND 25 µA Maxim Integrated │ 3 MAX17525 High-Accuracy, Adjustable Power Limiter Electrical Characteristics (continued) (VIN = 5.5V to 60V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VIN = 12V, TA = +25°C) (Note 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LOGIC OUTPUT (FLAG) Logic-Low Voltage ISINK = 1mA Input Leakage Current VIN = 5.5V, FLAG deasserted 0.4 V 1 µA SETI RSETI x ILIM Current Mirror Output Ratio VRI See the Setting the Current-Limit Threshold section 1.5 CIRATIO See the Setting the Current-Limit Threshold section 25000 V DYNAMIC PERFORMANCE (NOTE 6) tON VIN = 24V, switch OFF to ON, RLOAD = 240Ω, ILIM = 1A, COUT = 4.7µF, VOUT from 20% to 80% of VIN 68 Fault Recovery nFET Turn-On Time tON_NFET Turn-on delay after fault timers expired 200 500 µs Fault Recovery pFET Turn-on Time tON_PFET VOUT > VUVLO_OUT, turn-on delay of pFET after fault timers expired 1.08 1.2 1.32 ms Reverse-Current Fault Recovery Time tREV_REC 0.4 0.45 0.5 ms OVP Switch Response Time tOVP_RES Overcurrent Switch Response time tOCP_RES Switch Turn-On Time ILIM = 4A µs 3 µs 3 µs Startup Timeout tSTO Initial start current-limit foldback timeout (Figure 1) 1090 1200 1320 ms Startup Initial Time tSTI Current is continuously limited to 1x/1.5x/2x in this interval (Figure 1) 21.8 24 26.4 ms IN Debounce Time tDEB Additional turn-on delay if VOUT < VUVLO_OUT, see the Timing Diagrams 1.09 1.2 1.32 ms Blanking Time tBLANK (Figures 3 and 4) 21.8 24 26.4 ms Autoretry Time tRETRY (Figure 3, Note 7) 554 720 792 ms THERMAL PROTECTION Thermal Foldback TJ_FB 150 °C Thermal Shutdown TJ_MAX 170 °C 20 °C Thermal-Shutdown Hysteresis Note 4: All devices are 100% production-tested at TA = +25°C. Specifications over the operating temperature range are guaranteed by design. Note 5: Not production-tested, user-adjustable. See the Overvoltage Lockout (OVLO) and Undervoltage Lockout (UVLO) sections. Note 6: All timing is measured using 20% and 80% levels, unless otherwise specified. Note 7: The autoretry time-to-blanking time ratio is fixed and is equal to 30. www.maximintegrated.com Maxim Integrated │ 4 MAX17525 High-Accuracy, Adjustable Power Limiter Timing Diagrams tDEB + tON_NFET tSTO* tSTI OVLO IN IOUT UVLO ILIMIT VIN OUT GND THERMALLY CONTROLLED CURRENT FOLDBACK TJ_FB TJ NOT DRAWN TO SCALE *IF OUT DOES NOT REACH V IN - VFA WITHIN t STO, THE DEVICE IS LATCHED OFF , AND EN , HVEN, OR IN MUST BE TOGGLED TO RESUME NORMAL OPERATION . Figure 1. Startup Timing < tDEB < tDEB tDEB + tON_NFET OVLO IN UVLO ON SWITCH STATUS OFF NOT DRAWN TO SCALE Figure 2. Debounce Timing www.maximintegrated.com Maxim Integrated │ 5 MAX17525 High-Accuracy, Adjustable Power Limiter Typical Operating Characteristics (VIN = 12V, CIN = 1µF, COUT = 4.7µF, TA = +25°C, unless otherwise noted.) QUIESCENT IN CURRENT vs. IN VOLTAGE QUIESCENT IN CURRENT vs. TEMPERATURE 2.0 toc02 90 1.6 1.6 80 1.2 1 0.8 0.6 0.4 1.4 1.2 VIN = 24V 1.0 VIN = 34V VIN = 13V 0.8 0.6 0.4 0.2 0.2 0 HVEN INPUT CURRENT (µA) 1.8 1.4 0.0 5 10 15 20 25 30 35 40 45 50 55 60 NORMALIZED ON-RESISTANCE vs. SUPPLY VOLTAGE -25 0 25 50 75 100 125 1.00 0.95 TA = 85°C 40 TA = 25°C 30 TA = -40°C 20 0 150 0 12 24 36 NORMALIZED ON-RESISTANCE vs. TEMPERATURE 2 48 60 toc05 VIN = 24V IOUT = 1A VEN = 5V 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0.90 TA = 125°C 50 VHVEN (V) NORMALIZED ON-RESISTANCE NORMALIZED ON-RESISTANCE 1.05 60 10 -50 toc04 NORMALIZED TO VIN = 12V IOUT = 1A VEN = 5V toc03 70 TEMPERATURE (°C) IN VOLTAGE (V) 1.10 HVEN INPUT CURRENT vs. VHVEN 100 1.8 QUIESCENT CURRENT (mA) QUIESCENT CURRENT (mA) 2 toc01 5 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (°C) 10 15 20 25 30 35 40 45 50 55 60 IN VOLTAGE (V) NORMALIZED ON-RESISTANCE vs. OUTPUT CURRENT 2 NORMALIZED TO VIN = 24V IOUT = 1A VEN = 5V 1.6 1.04 1.4 1.2 1 0.8 0.6 toc07 NORMALIZED TO VIN = 12V RILIM = 37.5kΩ 1.03 1.02 1.01 1 0.99 0.98 0.97 0.4 0.2 0 NORMALIZED CURRENT LIMIT vs. SUPPLY VOLTAGE 1.05 NORMALIZED CURRENT LIMIT 1.8 NORMALIZED ON-RESISTANCE toc06 0.96 VEN = 5V 0.6 1.2 1.8 2.4 3.0 3.6 4.2 OUTPUT CURRENT (A) www.maximintegrated.com 4.8 5.4 6.0 0.95 5 10 15 20 25 30 35 40 45 50 55 60 IN VOLTAGE (V) Maxim Integrated │ 6 MAX17525 High-Accuracy, Adjustable Power Limiter Typical Operating Characteristics (continued) (VIN = 12V, CIN = 1µF, COUT = 4.7µF, TA = +25°C, unless otherwise noted.) NORMALIZED CURRENT LIMIT vs. TEMPERATURE 1 0.99 0.98 14 12 60VIN 10 8 34VIN 6 -25 0 25 50 75 100 125 150 12VIN SWITCH TURN-ON TIME vs. TEMPERATURE 180 25 50 75 100 125 80 60 50 75 100 125 75 100 125 150 toc12 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (°C) POWER-UP RESPONSE POWER-UP RESPONSE REVERSE-BLOCKING RESPONSE toc13 toc13 VIN 20V/div VOUT 20V/div CLL==33mF C 33mF = 2.9A IILIM LIM = 2.9A 1A/div 200ms/div 50 3 0 150 TEMPERATURE (°C) IOUT 25 4 1 www.maximintegrated.com 0 5 2 25 -25 6 20 0 -50 VIN = +24V RL = 240Ω CL = 4.7μF 7 40 -25 0.2 SWITCH TURN-OFF TIME vs. TEMPERATURE 10 8 100 -50 VIN = +12V 0.3 TEMPERATURE (°C) 9 120 0 0.4 0 150 TURN-OFF TIME (μs) TURN-ON TIME (μs) 140 0 toc11 MAX17525 VIN = +24V RL = 240Ω CL = 4.7μF 160 -25 VIN = +24V 0.5 0.1 5.5VIN -50 0.6 TEMPERATURE (°C) TEMPERATURE (°C) 200 24VIN 4 2 -50 toc10 0.7 16 0 FET LEAKAGE CURRENT vs. TEMPERATURE 0.8 18 1.01 0.97 toc09 FET LEAKAGE CURRENT (µA) 1.02 SHUTDOWN IN CURRENT vs. TEMPERATURE 20 NORMALIZED TO TA = +25oC VIN = 24V RILIM = 37.5kΩ SHUTDOWN IN CURRENT (µA) NORMALIZED CURRENT LIMIT 1.03 toc08 VIN 20V/div VOUT 20V/div IOUT 5A/div 10µs/div Maxim Integrated │ 7 MAX17525 High-Accuracy, Adjustable Power Limiter Typical Operating Characteristics (VIN = 12V, CIN = 1µF, COUT = 4.7µF, TA = +25°C, unless otherwise noted.) FLAG RESPONSE CURRENT-LIMIT RESPONSE toc15 VIN toc16 VIN 20V/div 20V/div 0V 0V VOUT VOUT 20V/div 0V 5V/div VFLAG\ 20V/div 0V 1A/div IOUT ILIM = 1A IL = 100mA TO SUDDEN SHORT APPLIED 10ms/div 4µs/div CURRENT-LIMIT RESPONSE VIN BLANKING TIME toc17 toc18 AUTO-RETRY MODE 20V/div 0V VOUT VOUT 20V/div 0V 1A/div IOUT 20V/div IOUT 1A/div ILIM = 1A IL = 100mA TO SHORT ON OUT WITH 1A/s 10ms/div 10ms/div AUTORETRY TIME AUTORETRY TIME toc19 toc19 AUTORETRY MODE MODE VOUT 20V/div IOUT 1A/div 200ms/div 200ms/div www.maximintegrated.com Maxim Integrated │ 8 MAX17525 High-Accuracy, Adjustable Power Limiter OUT OUT OUT OUT TOP VIEW OUT Pin Configurations 15 14 13 12 11 RIPEN 16 HVEN 17 MAX17525 CLTS2 18 CLTS1 19 GND/EP 3 4 UVLO 9 OVLO 8 FLAG 7 SETI 6 GP 5 IN 2 IN IN 1 IN + IN EN 20 10 TQFN (5mm x 5mm) Pin Description PIN NAME FUNCTION 1–5 IN Switch Input. Bypass IN to ground with a 1µF ceramic capacitor. In applications in which an external pFET is used, a 4.7µF capacitor should be placed at the drain of the pFET and a reduced capacitor of 10nF to 100nF should be placed at IN. The maximum slew rate allowed at IN is 30V/µs. IN serves as the undervoltage/overvoltage sensed input when preprogrammed UVLO/OVLO is used. 6 GP Gate Driver Output for External pFET. 7 SETI 8 FLAG 9 OVLO 10 UVLO 11–15 OUT 16 RIPEN Overload Current-Limit Adjust. Connect a resistor from SETI to GND to program the overcurrent limit. SETI must be connected to a resistor. If SETI is connected to GND during startup, then the switch does not turn on. Do not connect more than 30pF to SETI. Open-Drain Fault Indicator Output. FLAG asserts low when the VIN - VOUT voltage exceeds VFA, reverse current is detected, thermal shutdown mode is active, OVLO or UVLO threshold is reached, or SETI is connected to GND. Externally-Programmable Overvoltage-Lockout Threshold. Connect OVLO to GND to use the default internal OVLO threshold. Connect OVLO to an external resistor-divider to define a threshold externally and override the preset internal OVLO threshold. 17 HVEN Externally Programmable Undervoltage-Lockout Threshold. Connect UVLO to GND to use the default internal UVLO threshold. Connect UVLO to an external resistor-divider to define a threshold externally and override the preset internal UVLO threshold. Switch Output. Bypass OUT to GND with a 4.7µF ceramic capacitor placed as close as possible to the device. Reverse-Current Protection Enable. Connect RIPEN to GND with 10kΩ pulldown resistor to disable the reverse-current flow protection. Leave RIPEN open or connect RIPEN to logic-high to activate the reverse-current flow protection. 60V Capable Active-Low Enable Input. See Table 1. 18 CLTS2 Current-Limit Type Select 2. See Table 2. 19 CLTS1 Current-Limit Type Select 1. See Table 2. 20 EN — GND/EP www.maximintegrated.com Active-High Enable Input. See Table 1. Ground/Exposed Pad. Connect to a large copper ground plane to maximize thermal performance. Maxim Integrated │ 9 MAX17525 High-Accuracy, Adjustable Power Limiter Functional Diagram GP IN IN IN IN IN OUT OUT MAX17525 OUT OUT RIPEN OUT 5V SETI 150kΩ REVERSE CURRENT FLOW CONTROL CURRENT LIMIT CONTROL CHARGE PUMP CONTROL VSET UVLO VUVLO_SEL FLAG CONTROL LOGIC VSET OVLO VOVLO_SEL 5V EN 150 kΩ HVEN 150kΩ CLTS1 www.maximintegrated.com CLTS2 GND Maxim Integrated │ 10 MAX17525 Detailed Description The MAX17525 adjustable overvoltage, undervoltage, and overcurrent protection devices guard systems against overcurrent faults in addition to positive overvoltage and reverse-voltage faults. When used with an optional external pMOSFET, the devices also protect downstream circuitry from voltage faults up to +60V, -60V (for -(60 + VOUT) external pFET rating). The devices feature a low, 31mΩ, on-resistance integrated FET. During startup, the devices are designed to charge large capacitances on the output in a continuous mode for applications where large reservoir capacitors are used on the inputs to downstream devices. Additionally, the device features a dual-stage current-limit mode in which the current is continuously limited to 1x, 1.5x, and 2x the programmed limit, respectively, for a short time after startup. This enables faster charging of large loads during startup. The devices feature the option to set the overvoltagelockout (OVLO) and undervoltage-lockout (UVLO) thresholds manually using external voltage-dividers or to use the factory-preset internal thresholds by connecting the OVLO and/or UVLO pin(s) to GND. The permitted external overvoltage setting range of the devices is 6V to 40V. Therefore, the pFET and internal nFET must be kept off in the 40V to 60V range by appropriate OVLO resistordivider. The devices’ programmable current-limit threshold can be set for currents up to 6A in autoretry, latchoff, or continuous-fault-response mode. When the device is set to autoretry mode and the current exceeds the threshold for more than 24ms (typ), both FETs are turned off for 720ms (typ), then turned back on. If the fault is still present, the cycle repeats. In latchoff mode, if a fault is present for more than 24ms (typ), both FETs are turned off until enable is toggled or the power is cycled. In continuous mode, the current is limited continuously to the programmed current-limit value. In all modes, FLAG asserts if VIN - VOUT is greater than the FLAG assertion drop voltage threshold (VFA). Startup Control The devices feature a dual-stage startup sequence that continuously limits the current to 1x/1.5x/2x the set current limit during the startup initial time (tSTI), allowing large capacitors present on the output of the switch to be rapidly charged. The MAX17525 limits the current to 1x the set limit during this period. If the temperature of any device rises to the thermal-foldback threshold www.maximintegrated.com High-Accuracy, Adjustable Power Limiter (TJ_FB), the device enters power-limiting mode (Figure 1). In this mode, the device thermally regulates the current through the switch to protect itself while still delivering as much current as possible to the output regardless of the current-limit type selected. If the output is not charged within the startup timeout period (tSTO), the switch turns off and IN, EN, or HVEN must be toggled to resume normal operation. The tSTO timout period is also applied when there is a restart after a turn-off event caused by UVLO, OVLO, or reverse-current block event. If the output is not charged to (VIN - VFA) level during this time, the device turns off and IN, EN, or HVEN must be toggled to resume normal operation. Overvoltage Lockout (OVLO) The devices feature two methods for determining the OVLO threshold. By connecting the OVLO pin to GND, the preset internal OVLO threshold of 36V (typ) is selected. If the voltage at OVLO rises above the OVLO select threshold (VOVLO_SEL), the device enters adjustable OVLO mode. Connect an external voltage-divider to the OVLO pin, as shown in the Typical Application Circuit to adjust the OVLO threshold. R3 = 2.2MΩ is a good starting value for minimum current consumption. Since VSET is known, R3 has been chosen, and VOVLO is the target OVLO value, R4 can then be calculated by the following equation: R4 = R3 × VSET VOVLO − VSET Undervoltage Lockout (UVLO) The devices feature two methods for determining the UVLO threshold. By connecting the UVLO pin to GND, the preset, internal UVLO threshold of 12V (typ) is selected. If the voltage at UVLO rises above the UVLO select threshold (VUVLO_SEL), the device enters adjustable UVLO mode. Connect an external voltage-divider to the UVLO pin, as shown in the Typical Application Circuit to adjust the UVLO threshold. R1 = 2.2MΩ is a good starting value for minimum current consumption. Since VSET is known, R1 has been chosen, and VUVLO is the target value, R2 can then be calculated by the following equation: R1× VSET R2 = VUVLO − VSET Maxim Integrated │ 11 MAX17525 High-Accuracy, Adjustable Power Limiter Table 1. Enable Inputs Table 2. Current-Limit Type Select HVEN EN SWITCH STATUS CLTS2 CLTS1 CURRENT-LIMIT TYPE 0 0 ON 0 0 LATCHOFF MODE 0 1 ON 0 1 AUTORETRY MODE 1 0 OFF 1 0 CONTINUOUS MODE 1 1 ON 1 1 CONTINUOUS MODE Switch Control There are two independent enable inputs on the devices: HVEN and EN. HVEN is a high-voltage-capable input, accepting signals up to 60V. EN is a low-voltage input, accepting a maximum voltage of 5V. In case of a fault condition, toggling HVEN or EN resets the fault. The enable inputs control the state of the switch based on the truth table (Table 1). Input Debounce The devices feature a built-in input debounce time (tDEB). The debounce time is a delay between a POR event and the switch being turned on. If the input voltage rises above the UVLO threshold voltage or if, with a voltage greater than VUVLO present on IN, the enable pins toggle to the on state, the switch turns on after tDEB. In cases where the voltage at IN falls below VUVLO before tDEB has passed, the switch remains off (Figure 2). If the voltage at OUT is already above VUVLO_OUT when the device is turned on through either enable pin or coming out of OVLO, there is no debounce interval. This is due to the device already being out of the POR condition with OUT above VUVLO_OUT. Current-Limit Type Select The MAX17525 feature three selectable current-limiting modes. During power-up, all devices default to continuous mode and follow the procedure defined in the Startup Control section. Once the part has been successfully powered on and tSTO has expired, the device senses the condition of CLTS1 and CLTS2. The condition of CLTS1 and CLTS2 sets the current-limit mode type according to Table 2. CLTS1,2 are internally pulled up to an internal 5V supply. Therefore, the device is in continuous current-limit mode when CLTS1 and 2 are open. To set CLTS_ state to low, connect a 10kΩ resistor or below to ground. In addition to the selectable current-limiting modes, the device has a protection feature against a severe over load condition. If the output current exceeds 2 times the set current limit, the device will turn off the internal nFET and external pFET immediately and will attempt to restart to allow the overcurrent to last for tBLANK time. The off duration depends on fault condition occurred after the FETs turn www.maximintegrated.com off, with the shortest duration of 420us (tON_FET) if there is no fault. In lacthoff mode, the device will latch off if the overcurrent fault last longer than tBLANK. Autoretry Mode (Figure 3) In autoretry current-limit mode, when current through the device reaches the threshold, the tBLANK timer begins counting. The FLAG output asserts low when the voltage drop across the switch rises above VFA. If the overcurrent condition is present for tBLANK, the switch is turned off. The timer resets if the overcurrent condition disappears before tBLANK has elapsed. A retry time delay (tRETRY) starts immediately once tBLANK has elapsed. During the retry time, the switch remains off and, once tRETRY has elapsed, the switch is turned back on. If the fault still exists, the cycle is repeated and FLAG remains low. If the fault has been removed, the switch stays on. The autoretry feature reduces system power in case of overcurrent or short-circuit conditions. When the switch is on during tBLANK time, the supply current is held at the current limit. When the switch is off during tRETRY time, there is no current through the switch. Thus, the output current is much less than the programmed current limit. Calculate the average output current using the following equation: t BLANK + t STI × K ILOAD = ILIM t BLANK + t RETRY + t STI where K is the multiplication factor of the initial current limit (1x, 1.5x or 2x). With a 24ms (typ) tBLANK, 24ms tSTI, K = 1 and 720ms (typ) tRETRY, the duty cycle is 3.1%, resulting in 97% power saving when compared to the switch being on the entire time. Latchoff Mode (Figure 4) In latchoff current-limit mode, when current through the device reaches the threshold, the tBLANK timer begins counting. FLAG asserts when the voltage drop across the switch rises above VFA. The timer resets if the overcurrent condition disappears before tBLANK has elapsed. The switch turns off if the overcurrent condition remains for the blanking time. The switch remains off until the control logic (EN or HVEN) is toggled or the input voltage is cycled. Maxim Integrated │ 12 MAX17525 High-Accuracy, Adjustable Power Limiter tBLANK IOUT tBLANK tRETRY tDEB + tON_NFET tSTI tBLANK tON_NFET tRETRY 1x/1.5x/2x I LIMIT ILIMIT tSTI 1x/1.5x/2x I LIMIT 0 VOUT VIN VFB VUVLO_OUT FLAG NOT DRAWN TO SCALE VUVLO < VIN < VOVLO, HVEN = LOW, EN = HIGH Figure 3. Autoretry Fault Diagram tBLANK IOUT tBLANK tON_NFET ILIMIT tSTI 1x/1.5x/2x I LIMIT tBLANK tDEB + tON_NFET tSTI 1x/1.5x/2x I LIMIT 0 VOUT VIN VFB VUVLO _OUT EN HVEN FLAG NOT DRAWN TO SCALE VUVLO < VIN < VOVLO Figure 4. Latchoff Fault Diagram www.maximintegrated.com Maxim Integrated │ 13 MAX17525 High-Accuracy, Adjustable Power Limiter Continuous Mode (Figure 5) In continuous current-limit mode, when current through the device reaches the threshold, the device limits the current to the programmed limit. FLAG asserts when the voltage drop across the switch rises above VFA, and deasserts when it falls below VFA. Reverse-Current Blocking (Figure 6, Figure 7) The devices feature current-blocking functionality to be used with external pFET. To enable the reverse-current blocking feature, pull RIPEN high or leave RIPEN unconnected as it is internally pulled high. With RIPEN high, if a reversecurrent condition is detected (VIN - VOUT < VRIB_), the internal nFET and the external pFET are turned off for 450µs (tREV_REC). During and after this time, the device monitors the voltage difference between OUT and IN pins to determine whether the reverse current is still present. Once tREV_REC expired and the reverse-current condition tDEB + tON_NFET tSTI tSTO has been removed, the nFET and pFET are turned back on after an additional time delay followed by the dual-stage startup control mechanism, defined in the Startup Control section above, is applied. The additional time delay will be 200µs (tON_NFET) for nFET and 1.2ms (tON_PFET) for pFET if voltage at OUT is greater than or equal to VUVLO_ OUT falling at the end of tREV_REC delay, otherwise the delay will be 1.4ms (tDEB + tON_NFET) for nFET and 2.4ms (tDEB + tON_PFET) for pFET. After a reverse-current event, the device will attempt a restart regardless of the currenttype select. The device contains two reverse-current thresholds with slow (< 30µs) and fast (< 1µs) response time for reverse current protection. This feature results in robust operation in a noisy environment, while still delivering fast protection for severe fault, such as input short circuit. tON_NFET tSTI OVLO IN IOUT UVLO ILIMIT 1x/1.5x/2x I LIMIT 1x/1.5x/2x I LIMIT THERMAL CURRENT LIMIT THERMAL CURRENT LIMIT 0 VIN VFA VOUT VOUT_UVLO TJMAX TJ HVEN EN FLAG NOT DRAWN TO SCALE Figure 5. Continuous Fault Diagram www.maximintegrated.com Maxim Integrated │ 14 MAX17525 High-Accuracy, Adjustable Power Limiter Fault Indicator (FLAG) Output FLAG is an open-drain fault-indicator output. It requires an external pullup resistor to a DC supply. FLAG asserts when any of the following conditions occur: ●● VIN - VOUT > VFA ●● Reverse-current protection is tripped ●● Die temperature exceeds +170°C ●● SETI is connected to ground ●● UVLO threshold has not been reached ●● OVLO threshold is reached Thermal Shutdown Protection The thermal shutdown technology built into the devices behave in accordance with the selected current-limit mode. While the devices are in autoretry mode, the thermal limit uses the autoretry timing when coming out of a fault condition. When the devices detect an overtemperature fault, the switch turns off. Once the temperature of the junction falls below the falling thermal threshold, the device turns on after the time interval tRETRY. In latchoff mode, the device latches off until the input is cycled or one of the enable pins is toggled. In continuous currentlimiting mode, the device turns off while the temperature is over the limit, then turns back on after tDEB when the temperature reaches the falling threshold. There is no retry time for thermal protection. Thermal-shutdown circuitry protects the devices from overheating. The switch turns off and FLAG asserts when the junction temperature exceeds +170°C (typ). The devices exit thermal shutdown and resume normal operation once the junction temperature cools by 20°C (typ) when the device is in autoretry or continuous current-limiting mode. When in latchoff mode, the device remains latched off until the input voltage is cycled or one of the enable pins is toggled. tON_PFET tON_PFET tRIB_SLOW tRIB_SLOW tREV_REC tRIB_SLOW tREV_REC tON_NFET tDEB tON_NFET (VIN-VOUT) 0V VRIB_SLOW VD_PFET VOUT VUVLO_OUT VIN-VGP 0V IOUT ILOAD 1x/1.5x/2x ILIMIT 1x/1.5x/2x ILIMIT 0A -(VRIB_SLOW/RON) NMOS_OFF Figure 6. Slow Reverse-Current Fault Timing Diagram www.maximintegrated.com Maxim Integrated │ 15 MAX17525 High-Accuracy, Adjustable Power Limiter tON_PFET tRIB_SLOW tRIB_FAST tREV_REC tON_PFET tON_NFET tRIB_FAST tREV_REC tDEB tON_NFET (VIN - VOUT) 0V VRIB_SLOW VRIB_FAST VD_PFET VOUT VUVLO_OUT VIN-VGP 0V 1x/1.5x/2x IOUT ILIMIT ILOAD 0A -(VRIB_SLOW/RON) -(VRIB_FAST/RON) 1x/1.5x/2x ILIMIT NMOS_OFF Figure 7. Fast Reverse-Current Fault Timing Diagram tON_PFET tDEB tON_NFET OVLO VIN VOUT VUVLO_OUT VIN - VGP 0V IOUT ILOAD 0A 1x/1.5x/2x ILIMIT 1x/1.5x/2x ILIMIT NMOS_OFF Figure 8. Overvoltage Fault Timing Diagram www.maximintegrated.com Maxim Integrated │ 16 MAX17525 High-Accuracy, Adjustable Power Limiter Applications Information Setting the Current-Limit Threshold Connect a resistor between SETI and ground to program the current-limit threshold for the devices. Leaving SETI unconnected sets the current-limit threshold to 0A and, since connecting SETI to ground is a fault condition, this causes the switch to remain off and FLAG to assert. Use the following formula to calculate the current-limit threshold: R SETI = (kΩ ) VRI(Ω × A) × C IRATIO ILIM(mA) Do not use a RSETI smaller than 6kΩ. Table 3 shows currentlimit thresholds for different resistor values at SETI. A current mirror with a ratio of CIRATIO is implemented with a current-sense auto-zero operational amplifier. The mirrored current of the IN-OUT FET is provided on the SETI pin. Therefore, the voltage (VSETI) read on the SETI pin should be interpreted as the current through the IN-OUT FET, as shown below: V (V) IIN−OUT = I SETI × C IRATIO =SETI R SETI(kΩ ) × C IRATIO = VSETI(V) × ILIM VRI(V) IN Bypass Capacitor In application in which an external pFET is not used, connect a minimum of 1µF capacitor from IN to GND to limit the input voltage drop during momentary output short-circuit conditions. Larger capacitor values further reduce the voltage droop at the input caused by load transients. In applications in which an external pFET is used a 4.7µF capacitor is placed at the drain of the pFET, and capacitor at IN is reduced to 10nF (100nF, max). Hot Plug-In In many power applications, an input filtering capacitor is required to lower the radiated emission and enhance the ESD capability, etc. In hot-plug applications, parasitic cable inductance, along with the input capacitor, causes overshoot and ringing when a powered cable is suddenly connected to the input terminal. This effect causes the protection device to see almost twice the applied voltage. An input voltage of 24V can easily exceed 40V due to ringing. The devices contain internal protection against hot-plug input transient. on the IN pins,with slew rate up to 30V/µs. However, in the case where the harsh industrial EMC test is required, use a transient voltage suppressor (TVS) placed close to the input terminal that is capable of limiting the input surge to 60V. www.maximintegrated.com OUT Capacitance For stable operation over the full temperature range and over the entire programmable current-limit range, connect a 4.7µF ceramic capacitor from OUT to ground. Other circuits connected to the output of the device may introduce additional capacitance, but it should be noted that excessive output capacitance on the devices can cause faults. If the capacitance is too high, the devices may not be able to charge the capacitor before the startup timeout. Calculate the maximum capacitive load (CMAX) value that can be connected to OUT using the following formula: (MM− x1)t×STI (ms) + t+STO (ms) t STI (ms) t STO (ms) CMAX(mF) = ILIM(A) VIN_MAX(V) where M is the multiplier (1x/1.5x/2x) applied to the current limit during startup. For example, when using MAX17525, if VIN_MAX = 30V, tSTO (min) = 1090ms, tSTI (min) = 22ms, and ILIM = 3A, CMAX results in the theoretical maximum of 111mF. In this case, any capacitance larger than 111mF will cause a fault condition because the capacitor cannot be charged to a sufficient voltage before tSTO has expired. In practical applications, the output capacitor size is limited by the thermal performance of the PCB. Poor thermal design can cause the thermal-foldback current-limiting function of the device to kick in too early, which may further limit the maximum capacitance that can be charged. Therefore, good thermal PCB design is imperative to charge large capacitor banks. Table 3. Current-Limit Threshold vs. Resistor Values RSETI (kΩ) CURRENT LIMIT (A) 62.5 0.6 37.5 1.0 25.0 1.5 18.75 2.0 15.0 2.5 12.5 3.0 10.7 3.5 9.375 4.0 8.3 4.5 7.5 5.0 6.82 5.5 6.25 6.0 Maxim Integrated │ 17 MAX17525 High-Accuracy, Adjustable Power Limiter OUT Freewheeling Diode for Inductive Hard Short to Ground Current Path Requirements PCB Layout Recommendations Use extreme caution when placing the decoupling capacitors to the IN and OUT pins. The tendency to go as close as possible to the IC pins might interfere with the minimum requirement of the trace width above. In applications with a highly inductive load, a freewheeling diode is required between the OUT terminal and GND. This protects the device from inductive kickback that occurs during short-to-ground events. To optimize the switch response to output short-circuit conditions, it is important to reduce the effect of undesirable parasitic inductance by keeping all traces as short as possible. Place input and output capacitors as close as possible to the device (no more than 5mm). IN and OUT must be connected with wide short traces to the power bus. During steady-state operation, the power dissipation is typically low and the package temperature change is usually minimal. PCB layout designs need to meet two challenges: high-current input and output paths and important heat dissipation. Heat Dissipation Maxim recommends the use of 2oz copper on FR4 isolator in a four-layer configuration. The layer stack needs to be Top (routing), GND (plane), Power (plane, connected to VOUT) and Bottom (routing), in this order, from top to bottom. Install the IC on an exposed pad landing of minimum 100 x 100 mils, with at least five through vias to the GND plane. The vias should be 32mils in diameter, with a 16mils plated hole. The hole plating needs to be at least 0.5oz copper. Connect all five IN pins to a copper area that is at least 150mils wide. Using 2oz copper may reduce this requirement to 100mils. Remember to provide the same copper trace width on the source connection, when using the external pMOS pass FET (with the source connected to the IN pins). It is important to note that the return load current does not flow through the IC; therefore, it is important to provide an external ground trace of at least the same width as the input/output one. Maxim recommends the use of a GND plane. Connect the input and output grounds to this plane using at least four plated vias each. The vias should be 84mils in diameter (or 60mils x 60mils, if square), with a 35mils plated hole. Additional Information For more information on heat dissipation, see the IC Application Section on http://www.maximintegrated.com. HBM ESD Protection Figure 9 shows the Human Body Model and Figure 10 shows the current waveform it generates when discharged into low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the device through a 1.5kΩ resistor. Provide a minimum of 1in x 1in area of copper plane on all four layers. It is important to remember that the inner planes do not contribute much to heat dissipation, due to FR4 isolation, but are important from an electrical point of view. If possible, keep the top and bottom copper areas clear of solder mask, as this will greatly improve heat dissipation. Use a similarly large copper area connected directly to the OUT pins. A dimension of 1in x 1in is also recommended. This might look oversized for current path requirements, but is essential for heat dissipation. Keep in mind that heat is generated at the drain junction of the internal nMOS pass FET, which is then eliminated through the five OUT pins and needs to be dissipated on this same copper area. www.maximintegrated.com Maxim Integrated │ 18 MAX17525 High-Accuracy, Adjustable Power Limiter RC 1mΩ CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE RD 1.5kΩ IP 100% 90% DISCHARGE RESISTANCE AMPERES DEVICE UNDER TEST STORAGE CAPACITOR IR 36.8% 10% 0 tRL TIME tDL CURRENT WAVEFORM Figure 10. Human Body Current Waveform Figure 9. Human Body ESD Test Model Ordering Information PART INITIAL CURRENT LIMIT TEMP RANGE PIN-PACKAGE 1.0x -40°C to +125°C 20 TQFN-EP* MAX17525ATP+T +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. *EP = Exposed pad. Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 20 TQFN-EP T2055+5C 21-0140 90-0010 www.maximintegrated.com Maxim Integrated │ 19 MAX17525 High-Accuracy, Adjustable Power Limiter Revision History REVISION NUMBER REVISION DATE 0 6/16 DESCRIPTION Initial release PAGES CHANGED — For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2016 Maxim Integrated Products, Inc. │ 20