STS1DN45K3 Dual N-channel 450 V, 3.2 Ω, 0.5 A SuperMESH3™ Power MOSFET in SO-8 Preliminary data Features Type VDSS RDS(on) max ID Pw STS1DN45K3 450 V < 3.8 Ω 0.5 A 1.7 W ■ 100% avalanche tested ■ Low input capacitances and gate charge ■ Low gate input resistance ) s ( ct u d o SO-8 r P e Application ■ t e l o Switching applications Description ) (s SuperMESH3™ is a new Power MOSFET technology that is obtained via improvements applied to STMicroelectronics’ SuperMESH™ technology combined with a new optimized vertical structure. The resulting product has an extremely low on resistance, superior dynamic performance and high avalanche capability, making it especially suitable for the most demanding applications. s b O Figure 1. Internal schematic diagram t c u d o r P e t e l o s b O Table 1. Device summary Order codes Marking Packages Packaging STS1DN45K3 1ll45 SO-8 Tape and reel April 2010 Doc ID 17338 Rev 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/10 www.st.com 10 Contents STS1DN45K3 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 .............................................. 6 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 2/10 Doc ID 17338 Rev 1 STS1DN45K3 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage (VGS = 0) 450 V VGS Gate-source voltage ± 30 V ID Drain current (continuous) at TC = 25 °C 0.5 A ID Drain current (continuous) at TC = 100 °C 0.32 A 2 A IDM (1) PTOT Drain current (pulsed) Total dissipation at TC = 25 °C (dual operation) 1.7 Total dissipation at TC = 25 °C (single operation) 1.3 IAR Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) EAS Single pulse avalanche energy (starting Tj = 25°C, ID = IAR, VDD = 50 V) dv/dt (2) Tstg Tj u d o ) s ( ct W W 0.5 A TBD mJ TBD V/ns - 55 to 150 °C 150 °C Value Unit Thermal resistance junction-amb max (single operation) 62.5 °C/W Thermal resistance junction-amb max (dual operation) 78 °C/W Peak diode recovery voltage slope t e l o Storage temperature s b O Max. operating junction temperature ) (s 1. Pulse width limited by safe operating area r P e 2. ISD ≤ 0.5 A, di/dt ≤ TBD A/µs, VPeak < V(BR)DSS Table 3. od Symbol r P e Rthj-amb(1) let o s b t c u Thermal data Parameter 1. When mounted on FR4 board (steady state) O Doc ID 17338 Rev 1 3/10 Electrical characteristics 2 STS1DN45K3 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4. On /off states Symbol V(BR)DSS Parameter Drain-source breakdown voltage VDS = Max rating Zero gate voltage drain current (VGS = 0) VDS = Max rating, TC=125 °C IGSS Gate-body leakage current (VDS = 0) Gate threshold voltage VDS = VGS, ID = 50 µA RDS(on) Static drain-source on resistance Co(tr)(1) ete e t e ol Parameter u d o s b O Test conditions )- s ( t c VDS =25 V, f = 1 MHz, VGS = 0 Equivalent capacitance time related Pr Co(er)(2) VGS = 10 V, ID = 0.5 A Dynamic Input capacitance Output capacitance Reverse transfer capacitance Ciss Coss Crss Equivalent capacitance energy related Min. Typ. Max. Unit 450 V 1 50 µA µA ±10 µA 4.5 V 3.2 3.8 Ω Min. Typ. Max. Unit - 150 30 6 - pF pF pF - TBD - pF - TBD - pF - TBD - Ω - 6 TBD TBD - nC nC nC ) s ( ct VGS = ± 20 V VGS(th) Symbol b O ID = 1 mA, VGS = 0 IDSS Table 5. l o s Test conditions u d o 3 Pr 3.75 VDS = 0 to 360 V, VGS = 0 RG Intrinsic gate resistance f = 1 MHz open drain Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD = 360 V, ID = 0.5 A, VGS = 10 V (see Figure 3) 1. Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 2. Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 4/10 Doc ID 17338 Rev 1 STS1DN45K3 Electrical characteristics Table 6. Switching times Symbol td(on) tr td(off) tf Parameter Test conditions Turn-on delay time Rise time Turn-off-delay time Fall time Table 7. ISD Source-drain current Source-drain current (pulsed) VSD (2) trr Qrr IRRM trr Qrr IRRM - TBD TBD TBD TBD Min. Typ. Max Unit - ns ns ns ns Source drain diode Parameter ISDM Typ. VDD = 225 V, ID = 0.5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 4) Symbol (1) Min. Test conditions ISD = 0.5 A, VGS = 0 Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 0.5 A, di/dt = 100 A/µs VDD = 100 V (see Figure 7) Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 0.5 A, di/dt = 100 A/µs VDD = 100 V, Tj = 150 °C (see Figure 7) 1. Pulse width limited by safe operating area ) (s ) s ( ct - Forward on voltage e t e ol s b O u d o - Pr Max. Unit 0.5 2 A A 1.6 V - TBD TBD TBD ns nC A - TBD TBD TBD ns nC A 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% t c u Table 8. Gate-source Zener diode d o r Symbol Parameter P e BVGSO s b O t e l o Test conditions Gate-source breakdown voltage Igs=± 1 mA (open drain) Min. 30 Typ. Max. Unit V The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components Doc ID 17338 Rev 1 5/10 Test circuits STS1DN45K3 3 Test circuits Figure 2. Switching times test circuit for resistive load Figure 3. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 µF 2200 RL µF IG=CONST VDD VGS 100Ω Vi=20V=VGMAX VD RG 2200 µF D.U.T. VG c u d 47kΩ 1kΩ AM01468v1 e t e ol Figure 4. Test circuit for inductive load Figure 5. switching and diode recovery times A A D.U.T. FAST DIODE B B A D G S D RG S r P e AM01469v1 L VD VDD 2200 µF 3.3 µF VDD ID Vi D.U.T. Pw let so 1000 µF o r P Unclamped inductive load test circuit s b O u d o G b O s ( t c 3.3 µF B 25 Ω Figure 6. )- L=100µH ) s ( t 2.7kΩ PW PW D.U.T. AM01470v1 Unclamped inductive waveform AM01471v1 Figure 7. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 6/10 0 Doc ID 17338 Rev 1 10% AM01473v1 STS1DN45K3 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Doc ID 17338 Rev 1 7/10 Package mechanical data STS1DN45K3 SO-8 mechanical data mm Dim. Min. A A1 A2 b c D E E1 e h L L1 k ccc Typ. 1.75 0.25 0.10 1.25 0.28 0.17 4.80 5.80 3.80 0.48 0.23 5.00 6.20 4.00 4.90 6.00 3.90 1.27 0.25 0.40 t e l o ) s ( ct u d o r P e 1.04 0° ) (s Max. 0.50 1.27 8° 0.10 s b O t c u d o r P e t e l o s b O 0016023_D 8/10 Doc ID 17338 Rev 1 STS1DN45K3 5 Revision history Revision history Table 9. Document revision history Date Revision 07-Apr-2010 1 Changes First release ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Doc ID 17338 Rev 1 9/10 STS1DN45K3 ) s ( ct Please Read Carefully: u d o Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. r P e All ST products are sold pursuant to ST’s terms and conditions of sale. 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