ETC NT5SV4M16DT 64mb synchronous dram Datasheet

NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
Features
• High Performance:
-6K
-7K
-7
Units
fCK
Clock
Frequency
166
133
143
133
143
MHz
tCK
Clock Cycle
6
7.5
7
7.5
7
ns
CL=2
CL=3
CKs
CL
CAS Latency
tAC
Clock Access
Time1
CL=3 CL=2 CL=3
---
—
---
—
—
ns
tAC
Clock Access
Time2
5.4
5.4
5.4
5.4
5.4
ns
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1. Terminated load. See AC Characteristics on page 16.
2. Unterminated load. See AC Characteristics on page 16.
• Single Pulsed RAS Interface
• Fully Synchronous to Positive Clock Edge
• Four Banks controlled by BS0/BS1 (Bank Select)
Programmable CAS Latency: 2, 3
Programmable Burst Length: 1, 2, 4, 8, Full page
Programmable Wrap: Sequential or Interleave
Multiple Burst Read with Single Write Option
Automatic and Controlled Precharge Command
Data Mask for Read/Write control (x4, x8)
Dual Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
Standard Power operation
4096 refresh cycles/64ms
Random Column Address every CK (1-N Rule)
Single 3.3V ± 0.3V Power Supply
LVTTL compatible
Package: 54-pin 400 mil TSOP-Type II
Description
tiplexing style. Twelve row addresses (A0-A11) and two bank
select addresses (BS0, BS1) are strobed with RAS. Eleven
column addresses (A0-A9) plus bank select addresses and
A10 are strobed with CAS. Column address A9 is dropped on
the x8 device, and column addresses A8 and A9 are dropped
on the x16 device.
The NT5SV16M4DT, NT5SV8M8DT, and NT5SV4M16DT
are four-bank Synchronous DRAMs organized as 4Mbit x 4
I/O x 4 Bank, 2Mbit x 8 I/O x 4 Bank, and 1Mbit x 16 I/O x 4
Bank, respectively. These synchronous devices achieve
high-speed data transfer rates of up to 200MHz by employing
a pipeline chip architecture that synchronizes the output data
to a system clock. The chip is fabricated with NTC’s
advanced 64Mbit single transistor CMOS DRAM process
technology.
Prior to any access operation, the CAS latency, burst length,
and burst sequence must be programmed into the device by
address inputs A0-A11, BS0, BS1 during a mode register set
cycle. In addition, it is possible to program a multiple burst
sequence with single write cycle for write through cache operation.
The device is designed to comply with all JEDEC standards
set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive
edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion
allows random access operation to occur at a higher rate
than is possible with standard DRAMs. A sequential and gapless data rate of up to 200MHz is possible depending on
burst length, CAS latency, and speed grade of the device.
Simultaneous operation of both decks of a stacked device is
allowed, depending on the operation being done. Auto
Refresh (CBR) and Self Refresh operation are supported.
RAS, CAS, WE, and CS are pulsed signals which are examined at the positive edge of each externally applied clock
(CK). Internal chip operating modes are defined by combinations of these signals and a command decoder initiates the
necessary timings for each operation. A fourteen bit address
bus accepts address data in the conventional RAS/CAS mul-
REV 1.1
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© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
Pin Assignments for Planar Components (Top View)
VDD
VDD
VDD
1
54
VSS
VSS
VSS
DQ0
VDDQ
DQ1
DQ0
VDDQ
NC
NC
VDDQ
NC
2
3
4
53
52
51
NC
VSSQ
NC
DQ7
VSSQ
NC
DQ15
VSSQ
DQ14
DQ2
DQ1
DQ0
5
50
DQ3
DQ6
DQ13
VSSQ
DQ3
DQ4
VDDQ
DQ5
VSSQ
NC
NC
VDDQ
NC
6
7
8
9
10
49
48
47
46
45
VDDQ
NC
NC
VSSQ
NC
VDDQ
NC
DQ5
VSSQ
NC
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ6
VSSQ
NC
DQ2
VDDQ
NC
DQ3
DQ1
11
44
DQ2
DQ4
DQ9
VSSQ
VSSQ
VSSQ
12
43
VDDQ
VDDQ
VDDQ
DQ7
VDD
NC
VDD
NC
VDD
LDQM
WE
NC
WE
NC
WE
13
14
15
16
42
41
40
39
NC
VSS
NC
DQM
NC
VSS
NC
DQM
DQ8
VSS
NC
UDQM
CAS
RAS
CS
CAS
RAS
CS
CAS
RAS
CS
17
18
19
38
37
36
CK
CKE
NC
CK
CKE
NC
CK
CKE
NC
BS0
BS0
BS0
20
35
A11
A11
A11
BS1
A10/AP
A0
BS1
A10/AP
A0
BS1
A10/AP
A0
21
22
23
34
33
32
A9
A8
A7
A9
A8
A7
A9
A8
A7
A1
A2
A1
A2
A1
A2
24
25
31
30
A6
A5
A6
A5
A6
A5
A3
VDD
A3
VDD
A3
VDD
26
27
29
28
A4
VSS
A4
VSS
A4
VSS
54-pin Plastic TSOP(II) 400 mil
4Mbit x 4 I/O x 4 Bank
NT5SV16M4DT
2Mbit x 8 I/O x 4 Bank
NT5SV8M8DT
1Mbit x 16 I/O x 4 Bank
NT5SV4M16DT
REV 1.1
10/01
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© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
Pin Description
CK
Clock Input
DQ0-DQ15
Data Input/Output
CKE
Clock Enable
DQM, LDQM, UDQM
Data Mask
CS
Chip Select
VDD
Power (+3.3V)
RAS
Row Address Strobe
VSS
Ground
CAS
Column Address Strobe
VDDQ
Power for DQs (+3.3V)
WE
Write Enable
VSSQ
Ground for DQs
BS1, BS0
Bank Select
NC
No Connection
A0 - A11
Address Inputs
—
—
Input/Output Functional Description
Symbol
Type
Polarity
Function
CLK
Input
Positive
Edge
CKE
Input
Active High
Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
CS
Input
Active Low
CS enables the command decoder when low and disables the command decoder when high. When the
command decoder is disabled, new commands are ignored but previous operations continue.
RAS, CAS,
WE
Input
Active Low
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be
executed by the SDRAM.
BS0, BS1
Input
—
Selects which bank is to be active.
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
A0 - A11
Input
—
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at
the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when sampled
at the rising clock edge.
A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is
high, auto-precharge is selected and BS0, BS1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with BS0, BS1 to control which bank(s)
to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10 is low,
then BS0 and BS1 are used to define which bank to precharge.
DQ0 - DQ15
InputOutput
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In
x16 products, LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In Read
mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable.
Active High
DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has a latency
of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write
operation if DQM is high.
DQM
LDQM
UDQM
Input
VDD, VSS
Supply
—
Power and ground for the input buffers and the core logic.
VDDQ VSSQ
Supply
—
Isolated power supply and ground for the output buffers to provide improved noise immunity.
REV 1.1
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© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
Ordering Information
Speed Grade
Organization
Clock Frequency@CAS Latency
16M x 4
8M x 8
4M x 16
REV 1.1
10/01
Power
Supply
Package
Note
PC133 , PC100
3.3 V
400mil 54-PIN
TSOP II
Part Number
NT5SV16M4DT-6K
166MHz@CL3
133MHz@CL2
NT5SV16M4DT-7K
143MHz@CL3
133MHz@CL2
NT5SV16M4DT-7
143MHz@CL3
100MHz@CL2
NT5SV8M8DT-6K
166MHz@CL3
133MHz@CL2
NT5SV8M8DT-7K
143MHz@CL3
133MHz@CL2
NT5SV8M8DT-7
143MHz@CL3
100MHz@CL2
NT5SV4M16DT-6K
166MHz@CL3
133MHz@CL2
NT5SV4M16DT-7K
143MHz@CL3
133MHz@CL2
NT5SV4M16DT-7
143MHz@CL3
100MHz@CL2
4
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
Block Diagram
Column Decoder
CKE Buffer
CKE
Row Decoder
Row Decoder
Cell Array
Memory Bank 0
Cell Array
Memory Bank 1
CLK Buffer
Sense Amplifiers
Data Control Circuitry
Control Signal
Generator
Sense Amplifiers
Mode Register
Column
Address
Counter
Refresh
Counter
Address Buffers (14)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
BS0
BS1
A10
Data Input/Output Buffers
CLK
Column Decoder
Command Decoder
WE
Column Decoder
Row Decoder
CAS
Row Decoder
CS
DQX
DQM
Column Decoder
RAS
DQ0
Cell Array
Memory Bank 2
Cell Array
Memory Bank 3
Sense Amplifiers
Sense Amplifiers
Cell Array, per bank, for 4Mb x 4 DQ: 4096 Row x 1024 Col x 4 DQ (DQ0-DQ3).
Cell Array, per bank, for 2Mb x 8 DQ: 4096 Row x 512 Col x 8 DQ (DQ0-DQ7).
Cell Array, per bank, for 1Mb x 16 DQ: 4096 Row x 256 Col x 16 DQ (DQ0-DQ15).
REV 1.1
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
Mode Register Operation (Address Input For Mode Set)
BS0
BS1
A11
A10
A9
A8
A7
A6
Operation Mode
A5
A4
CAS Latency
A3
A2
BT
A1
Address
Bus (Ax)
A0
Burst Length
Mode
Register(Mx)
Burst Type
M3
Type
0
Sequential
1
Interleave
Operation Mode
M13 M12 M11 M10 M9
M8
M7
Mode
Burst Length
Length
0
0
0
0
0
0
0
Normal
0
0
0
0
1
0
0
Multiple Burst with
Single Write
M2
10/01
M0
Sequential Interleave
CAS Latency
REV 1.1
M1
0
0
0
1
1
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
M6
M5
M4
Latency
1
0
0
Reserved
Reserved
0
0
0
Reserved
1
0
1
Reserved
Reserved
0
0
1
Reserved
1
1
0
Reserved
Reserved
0
1
0
2
1
1
1
Full Page
Reserved
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
6
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations
(read cycle). There are three parameters that define how the burst mode will operate. These parameters include burst
sequence, burst length, and operation mode. The burst sequence and burst length are programmable, and are determined by
address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is set by address bits
A7 - A11, BS0, and BS1.
The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM. Two types of burst
sequences are supported, sequential and interleaved. See the table below.
The burst length controls the number of bits that will be output after a Read Command, or the number of bits to be input after a
Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 or full page(actual page length is dependent
on organization: x4, x8, or x16).Full page burst operation is only posible using the sequential burst type.
Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation implies that the
device will perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple burst with
single write operation was added to support Write Through Cache operation. Here, the programmed burst length only applies to
read cycles. All write cycles are single write operations when this mode is selected.
Burst Length and Sequence
Burst Length
2
4
8
Full Page(Note)
Starting Address (A2 A1 A0)
Sequential Addressing (decimal)
Interleave Addressing (decimal)
xx0
0, 1
0, 1
xx1
1, 0
1, 0
x00
0, 1, 2, 3
0, 1, 2, 3
x01
1, 2, 3, 0
1, 0, 3, 2
x10
2, 3, 0, 1
2, 3, 0, 1
x11
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
111
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
nnn
Cn, Cn+1, Cn+2, .....
Not Supported
Note: Page length is a function of I/O organization and column addressing.
x4 organization (CA0-CA9); Page Length = 1024 bits
x8 organization (CA0-CA8); Page Length = 512 bits
x16 organization (CA0-CA7); Page Length = 256 bits
REV 1.1
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© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
Command Truth Table (See note 1)
CKE
Function
Device State
Previous
Cycle
Current
Cycle
CS
RAS
CAS
WE
DQM
BS0,
BS1
A11,
A11,
A9-A0
A10
Mode Register Set
Idle
H
X
L
L
L
L
X
Auto (CBR) Refresh
Idle
H
H
L
L
L
H
X
X
X
X
Entry Self Refresh
Idle
H
L
X
X
X
X
X
X
X
X
L
L
L
H
H
X
X
X
L
H
H
H
Notes
OP Code
Exit Self Refresh
Idle (SelfRefresh)
L
H
Single Bank Precharge
See Current
State Table
H
X
L
L
H
L
X
BS
L
X
Precharge all Banks
See Current
State Table
H
X
L
L
H
L
X
X
H
X
Row Address
2
Bank Activate
Idle
H
X
L
L
H
H
X
BS
Write
Active
H
X
L
H
L
L
X
BS
L
Column
2
Write with Auto-Precharge
Active
H
X
L
H
L
L
X
BS
H
Column
2
Read
Active
H
X
L
H
L
H
X
BS
L
Column
2
Read with Auto-Precharge
Active
H
X
L
H
L
H
X
BS
H
Column
2
Burst Termination
Active
H
X
L
H
H
L
X
X
X
X
3,8
No Operation
Any
H
X
L
H
H
H
X
X
X
X
Device Deselect
Any
H
X
H
X
X
X
X
X
X
X
2
Clock Suspend Mode Entry
Active
H
L
X
X
X
X
X
X
X
X
Clock Suspend Mode Exit
Active
L
H
X
X
X
X
X
X
X
X
Data Write/Output Enable
Active
H
X
X
X
X
X
L
X
X
X
Data Mask/Output Disable
Active
H
X
X
X
X
X
H
X
X
X
Power Down Mode Entry
Idle/Active
H
L
X
X
X
X
6, 7
Power Down Mode Exit
Any (Power
Down)
L
H
X
X
X
X
6, 7
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
4
5
1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock.Operation of
both decks of a stacked device at the same time is allowed, depending on the operation being performed on the other deck. Refer to the
Current State Truth Table.
2. Bank Select (BS0, BS1): BS0, BS1 = 0,0 selects bank 0; BS0, BS1 = 1,0 selects bank 1; BS0, BS1 = 0,1 selects bank 2; BS0, BS1 = 1,1
selects bank 3.
3. During a Burst Write cycle there is a zero clock delay; for a Burst Read cycle the delay is equal to the CAS latency.
4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and
Write operations. One clock delay is required for mode entry and exit.
5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the
data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for Write cycles.
When it activates, the Write operation at the clock is prohibited (zero clock latency).
6. All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the device
state will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device can’t remain in
this mode longer than the Refresh period (t REF) of the device. One clock delay is required for mode entry and exit.
7. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high.
8. Device state is full page burst operation. Use of this command to terminate other burst length operations is illegal.
REV 1.1
10/01
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© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
Clock Enable (CKE) Truth Table
CKE
Current State
Self Refresh
Previous
Cycle
Command
Current
Cycle
CS
RAS
Action
CAS
WE
BS0,
BS1
A11 - A0
Notes
H
X
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
X
Exit Self Refresh with Device Deselect
2
L
H
L
H
H
H
X
X
Exit Self Refresh with No Operation
2
L
H
L
H
H
L
X
X
ILLEGAL
2
L
H
L
H
L
X
X
X
ILLEGAL
2
L
H
L
L
X
X
X
X
ILLEGAL
2
L
L
X
X
X
X
X
X
Maintain Self Refresh
H
X
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
X
Power Down mode exit, all banks idle
2
L
H
L
X
X
X
X
X
ILLEGAL
2
L
L
X
X
X
X
X
X
Maintain Power Down Mode
H
H
H
X
X
X
Power Down
All Banks Idle
Any State
other than
listed above
H
H
L
H
X
X
H
H
L
L
H
X
H
H
L
L
L
H
H
H
L
L
L
L
H
L
H
X
X
X
H
L
L
H
X
X
H
L
L
L
H
X
H
L
L
L
L
H
3
Refer to the Idle State section of the
Current State Truth Table
3
3
X
X
OP Code
CBR Refresh
Mode Register Set
4
3
Refer to the Idle State section of the
Current State Truth Table
3
3
X
X
OP Code
Entry Self Refresh
H
L
L
L
L
L
L
X
X
X
X
X
X
X
Power Down
H
H
X
X
X
X
X
X
Refer to operations in the Current State
Truth Table
H
L
X
X
X
X
X
X
Begin Clock Suspend next cycle
L
H
X
X
X
X
X
X
Exit Clock Suspend next cycle
L
L
X
X
X
X
X
X
Maintain Clock Suspend
4
Mode Register Set
4
5
1. For the given Current State CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE
(tCES) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on the first rising
clock after CKE goes high (see page 26).
3. The address inputs depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information.
4. The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state.
5. Must be a legal command as defined in the Current State Truth Table.
REV 1.1
10/01
9
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
Current State Truth Table
Current State
Idle
Row Active
Read
Write
(Part 1 of 3)(See note 1)
Command
CS
RAS CAS WE BS0,BS1
A11 - A0
OP Code
Action
Description
Mode Register Set
Set the Mode Register
X
Auto or Self Refresh
Start Auto or Self Refresh
X
Precharge
No Operation
Notes
L
L
L
L
L
L
L
H
X
L
L
H
L
BS
L
L
H
H
BS
L
H
L
L
BS
Column
Write w/o Precharge
ILLEGAL
4
L
H
L
H
BS
Column
Read w/o Precharge
ILLEGAL
4
L
H
H
L
X
X
Burst Termination
No Operation
Row Address Bank Activate
2
2, 3
Activate the specified bank and row
L
H
H
H
X
X
No Operation
No Operation
H
X
X
X
X
X
Device Deselect
No Operation or Power Down
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
BS
X
Precharge
L
L
H
H
BS
L
H
L
L
BS
Column
Write
Start Write; Determine if Auto Precharge
7, 8
L
H
L
H
BS
Column
Read
Start Read; Determine if Auto Precharge
7, 8
L
H
H
L
X
X
Burst Termination
No Operation
L
H
H
H
X
X
No Operation
No Operation
H
X
X
X
X
X
Device Deselect
No Operation
OP Code
Row Address Bank Activate
OP Code
Precharge
ILLEGAL
5
6
4
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
BS
X
Precharge
Terminate Burst; Start the Precharge
L
L
H
H
BS
L
H
L
L
BS
Column
Write
Terminate Burst; Start the Write cycle
8, 9
L
H
L
H
BS
Column
Read
Terminate Burst; Start a new Read cycle
8, 9
L
H
H
L
X
X
Burst Termination
Terminate the Burst
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
Row Address Bank Activate
OP Code
ILLEGAL
4
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
BS
X
Precharge
Terminate Burst; Start the Precharge
L
L
H
H
BS
L
H
L
L
BS
Column
Write
Terminate Burst; Start a new Write cycle
8, 9
L
H
L
H
BS
Column
Read
Terminate Burst; Start the Read cycle
8, 9
L
H
H
L
X
X
Burst Termination
Terminate the Burst
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
Row Address Bank Activate
ILLEGAL
4
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is
being applied to.
2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is
entered.
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS to CAS Delay (tRCD) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (t RRD) is not satisfied.
REV 1.1
10/01
10
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
Current State Truth Table
Current State
Read with
Auto Precharge
Write with Auto
Precharge
Precharging
Row
Activating
(Part 2 of 3)(See note 1)
Command
CS
RAS CAS WE BS0,BS1
A11 - A0
OP Code
Action
Description
Notes
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
BS
X
Precharge
ILLEGAL
4
L
L
H
H
BS
ILLEGAL
4
L
H
L
L
BS
Column
Write
ILLEGAL
4
L
H
L
H
BS
Column
Read
ILLEGAL
4
L
H
H
L
X
X
Burst Termination
ILLEGAL
Row Address Bank Activate
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
BS
X
Precharge
L
L
H
H
BS
L
H
L
L
BS
Column
L
H
L
H
BS
Column
L
H
H
L
X
X
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
OP Code
ILLEGAL
4
ILLEGAL
4
Write
ILLEGAL
4
Read
ILLEGAL
4
Burst Termination
ILLEGAL
Row Address Bank Activate
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
OP Code
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
BS
X
Precharge
L
L
H
H
BS
L
H
L
L
BS
Column
L
H
L
H
BS
Column
L
H
H
L
X
X
Row Address Bank Activate
No Operation; Bank(s) idle after tRP
ILLEGAL
4
Write
ILLEGAL
4
Read
ILLEGAL
4
Burst Termination
No Operation; Bank(s) idle after tRP
L
H
H
H
X
X
No Operation
No Operation; Bank(s) idle after tRP
H
X
X
X
X
X
Device Deselect
No Operation; Bank(s) idle after tRP
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
BS
X
Precharge
L
L
H
H
BS
OP Code
Row Address Bank Activate
ILLEGAL
4
ILLEGAL
4, 10
L
H
L
L
BS
Column
Write
ILLEGAL
4
L
H
L
H
BS
Column
Read
ILLEGAL
4
L
H
H
L
X
X
Burst Termination
No Operation; Row Active after tRCD
L
H
H
H
X
X
No Operation
No Operation; Row Active after tRCD
H
X
X
X
X
X
Device Deselect
No Operation; Row Active after tRCD
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is
being applied to.
2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is
entered.
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS to CAS Delay (tRCD) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (t RRD) is not satisfied.
REV 1.1
10/01
11
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
Current State Truth Table
Current State
Write
Recovering
Write
Recovering
with
Auto Precharge
Refreshing
Mode
Register
Accessing
(Part 3 of 3)(See note 1)
Command
CS
RAS CAS WE BS0,BS1
A11 - A0
OP Code
Action
Description
Notes
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
BS
X
Precharge
ILLEGAL
4
L
L
H
H
BS
ILLEGAL
4
L
H
L
L
BS
Column
Write
Start Write; Determine if Auto Precharge
9
L
H
L
H
BS
Column
Read
Start Read; Determine if Auto Precharge
9
L
H
H
L
X
X
Burst Termination
No Operation; Row Active after tDPL
Row Address Bank Activate
L
H
H
H
X
X
No Operation
No Operation; Row Active after tDPL
H
X
X
X
X
X
Device Deselect
No Operation; Row Active after tDPL
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
BS
X
Precharge
ILLEGAL
L
L
H
H
BS
L
H
L
L
BS
Column
L
H
L
H
BS
Column
L
H
H
L
X
X
OP Code
Row Address Bank Activate
4
Write
ILLEGAL
4, 9
Read
ILLEGAL
4, 9
Burst Termination
No Operation; Precharge after tDPL
L
H
H
H
X
X
No Operation
No Operation; Precharge after tDPL
H
X
X
X
X
X
Device Deselect
No Operation; Precharge after tDPL
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
BS
X
Precharge
ILLEGAL
L
L
H
H
BS
L
H
L
L
BS
Column
Write
ILLEGAL
L
H
L
H
BS
Column
Read
ILLEGAL
L
H
H
L
X
X
Burst Termination
No Operation; Idle after tRC
L
H
H
H
X
X
No Operation
No Operation; Idle after tRC
H
X
X
X
X
X
Device Deselect
No Operation; Idle after tRC
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
BS
X
Precharge
ILLEGAL
L
L
H
H
BS
L
H
L
L
BS
Column
Write
ILLEGAL
L
H
L
H
BS
Column
Read
ILLEGAL
L
H
H
L
X
X
Burst Termination
ILLEGAL
L
H
H
H
X
X
No Operation
No Operation; Idle after two clock cycles
H
X
X
X
X
X
Device Deselect
No Operation; Idle after two clock cycles
OP Code
Row Address Bank Activate
OP Code
4
ILLEGAL
Row Address Bank Activate
ILLEGAL
ILLEGAL
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is
being applied to.
2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is
entered.
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS to CAS Delay (tRCD) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (t RRD) is not satisfied.
REV 1.1
10/01
12
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
Absolute Maximum Ratings
Symbol
VDD
VDDQ
VIN
VOUT
TA
TSTG
PD
IOUT
Parameter
Rating
Units
Notes
Power Supply Voltage
-0.3 to +4.6
V
1
Power Supply Voltage for Output
-0.3 to +4.6
V
1
Input Voltage
-0.3 to VDD +0.3
V
1
Output Voltage
-0.3 to VDD +0.3
V
1
0 to +70
°C
1
-55 to +125
°C
1
Power Dissipation
1.0
W
1
Short Circuit Output Current
50
mA
1
Operating Temperature (ambient)
Storage Temperature
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended DC Operating Conditions (TA = 0°C to 70°C)
Rating
Symbol
Parameter
Units
Notes
3.6
V
1
3.3
3.6
V
1
2.0
—
VDD + 0.3
V
1, 2
-0.3
—
0.8
V
1, 3
Min.
Typ.
Max.
Supply Voltage
3.0
3.3
Supply Voltage for Output
3.0
VIH
Input High Voltage
VIL
Input Low Voltage
VDD
VDDQ
1. All voltages referenced to V SS and V SSQ.
2. VIH (max) = VDD + 1.2V for pulse width ≤ 5ns.
3. VIL (min) = VSS - 1.2V for pulse width ≤ 5ns.
Capacitance (TA = 25°C, f = 1MHz, VDD = 3.3V ± 0.3V)
Symbol
CI
CO
REV 1.1
10/01
Parameter
Min.
Typ
Max.
Units
Input Capacitance (A0-A11, BS0, BS1, CS, RAS, CAS, WE, CKE, DQM)
2.5
3.0
3.8
pF
Input Capacitance (CK)
2.5
2.8
3.5
pF
Output Capacitance (DQ0 - DQ15)
4.0
4.5
6.5
pF
13
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
DC Electrical Characteristics (TA = 0 to +70°C, VDD = 3.3V ±0.3V)
Symbol
Parameter
Min.
Max.
Units
II(L)
Input Leakage Current, any input
(0.0V ≤ VIN ≤ VDD ), All Other Pins Not Under Test = 0V
-1
+1
µA
IO(L)
Output Leakage Current
(DOUT is disabled, 0.0V ≤ VOUT ≤ VDDQ)
-1
+1
µA
VOH
Output Level (LVTTL)
Output “H” Level Voltage (IOUT = -2.0mA)
2.4
—
V
VOL
Output Level (LVTTL)
Output “L” Level Voltage (I OUT = +2.0mA)
—
0.4
V
DC Output Load Circuit
3.3 V
1200Ω
VOH (DC) = 2.4V, I OH = -2mA
Output
VOL (DC) = 0.4V, IOL = 2mA
50pF
REV 1.1
10/01
870Ω
14
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
Operating, Standby, and Refresh Currents
Parameter
Symbol
(TA = 0 to +70°C, VDD = 3.3V ±0.3V)
-6K
-7K
-7
(6ns)
(7ns)
(7ns)
Test Condition
Units
Notes
mA
1, 2, 3
ICC1
1 bank operation
tRC = tRC(min), t CK = min
Active-Precharge command cycling
without burst operation
ICC2P
CKE ≤ VIL(max), tCK = min,
CS = V IH(min)
1
mA
1
ICC2PS
CKE ≤ VIL(max), tCK = Infinity,
CS = V IH(min)
1
mA
1
ICC2N
CKE ≥ VIH(min), t CK = min,
CS = VIH (min)
10
mA
1, 5
ICC2NS
CKE ≥ VIH(min), t CK = Infinity,
5
mA
1, 7
ICC3N
CKE ≥ VIH(min), t CK = min,
CS = VIH (min)
30
mA
1, 5
ICC3P
CKE ≤ VIL(max), tCK = min,
9
mA
1, 6
Operating Current (Burst
Mode)
ICC4
tCK = min,
Read/ Write command cycling,
Multiple banks active, gapless data,
BL = 4
75
70
mA
1, 3, 4
Auto (CBR) Refresh Current
ICC5
tCK = min, t RC = tRC(min)
CBR command cycling
120
110
mA
1
Self Refresh Current
ICC6
mA
1
Operating Current
Precharge Standby Current
in Power Down Mode
Precharge Standby Current
in Non-Power Down Mode
No Operating Current
(Active state: 4 bank)
CKE ≤ 0.2V
60
55
1
1. Currents given are valid for a single device. The total current for a stacked device depends on the operation being performed
on the other deck.
2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC.
Input signals are changed up to three times during tRC(min).
3. The specified values are obtained with the output open.
4. Input signals are changed once during tCK(min).
5. Input signals are changed once during three clock cycles.
6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).
7. Input signals are stable.
REV 1.1
10/01
15
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
AC Characteristics (TA = 0 to +70°C, VDD = 3.3V ± 0.3V)
1. An initial pause of 200µs, with DQM and CKE held high, is required after power-up. A Precharge All Banks command must
be given followed by a minimum of two Auto (CBR) Refresh cycles before or after the Mode Register Set operation.
2. The Transition time is measured between V IH and V IL (or between VIL and V IH)
3. In addition to meeting the transition rate specification, the clock and CKE must transit between V IH and VIL (or between V IL
and VIH) in a monotonic manner.
4. Load Circuit A: AC timing tests have VIL = 0.4 V and V IH = 2.4 V with the timing referenced to the 1.40V crossover point
5. Load Circuit A: AC measurements assume tT = 1.0ns.
6. Load Circuit B: AC timing tests have VIL = 0.8 V and V IH = 2.0 V with the timing referenced to the 1.40V crossover point
7. Load Circuit B: AC measurements assume tT = 1.2ns.
.
AC Characteristics Diagrams
tT
tCKL
Clock
tSETUP
tCKH
Vtt = 1.4V
VIH
1.4V
VIL
50Ω
Output
Z o = 50Ω
50pF
AC Output Load Circuit (A)
tHOLD
1.4V
Input
Output
tAC
Z o = 50Ω
tOH
50pF
tLZ
Output
REV 1.1
10/01
AC Output Load Circuit (B)
1.4V
16
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
Clock and Clock Enable Parameters
Symbol
tCK3
tCK2
Parameter
-6K
-7K
-7
Units
Min.
Max.
Min.
Max.
Min.
Max.
Clock Cycle Time, CAS Latency = 3
6
1000
7
1000
7
1000
ns
Notes
Clock Cycle Time, CAS Latency = 2
7.5
1000
7.5
1000
10
1000
ns
tAC3 (A)
Clock Access Time, CAS Latency = 3
—
—
—
—
—
—
ns
1
tAC2 (A)
Clock Access Time, CAS Latency = 2
—
—
—
—
—
—
ns
1
tAC3 (B)
Clock Access Time, CAS Latency = 3
—
5.4
—
5.4
—
5.4
ns
2
tAC2 (B)
2
Clock Access Time, CAS Latency = 2
—
5.4
—
5.4
—
6
ns
tCKH
Clock High Pulse Width
2.5
—
2.5
—
3
—
ns
tCKL
Clock Low Pulse Width
2.5
—
2.5
—
3
—
ns
tCES
Clock Enable Set-up Time
1.5
—
1.5
—
2
—
ns
Clock Enable Hold Time
ns
tCEH
0.8
—
0.8
—
1
—
tSB
Power down mode Entry Time
0
6
0
7
0
7.5
ns
tT
Transition Time (Rise and Fall)
0.5
10
0.5
10
0.5
10
ns
1. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 4, 5 and load circuit A.
2. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 6, 7 and load circuit B.
Common Parameters
-6K
Symbol
-7K
-7
Parameter
Units
Min.
Max.
Min.
Max.
Min.
Max.
Notes
tCS
Command Setup Time
1.5
—
1.5
—
1.5
—
ns
tCH
Command Hold Time
0.8
—
0.8
—
0.8
—
ns
tAS
Address and Bank Select Set-up Time
1.5
—
1.5
—
1.5
—
ns
tAH
Address and Bank Select Hold Time
0.8
—
0.8
—
0.8
—
ns
tRCD
RAS to CAS Delay
15
—
15
—
20
—
ns
1
tRC
Bank Cycle Time
48
—
52
—
63
—
ns
1
tRAS
Active Command Period
36
100K
37
100K
42
100K
ns
1
tRP
Precharge Time
15
—
15
—
20
—
ns
1
Bank to Bank Delay Time
12
—
14
—
14
—
ns
1
tRRD
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Mode Register Set Cycle
-6K
Symbol
tRSC
Mode Register Set Cycle Time
REV 1.1
10/01
-7K
-7
Parameter
Units
Min.
Max.
Min.
Max.
Min.
Max.
12
—
14
—
14
—
ns
17
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
Read Cycle
-6K
Symbol
-7K
-7
Parameter
Min.
Units
Notes
—
ns
1
3
—
ns
2, 4
—
0
—
ns
Max.
Min.
Max.
Min.
Max.
—
—
—
—
—
3
—
—
0
tOH
Data Out Hold Time
tLZ
Data Out to Low Impedance Time
tHZ3
Data Out to High Impedance Time
2.7
5.4
2.7
5.4
2.7
5.4
ns
3
tHZ2
Data Out to High Impedance Time
2.7
5.4
2.7
5.4
3
6
ns
3
tDQZ
DQM Data Out Disable Latency
2
—
2
—
2
—
CK
1.
2.
3.
4.
3
AC Output Load Circuit A.
AC Output Load Circuit B.
Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Data Out Hold Time with no load must meet 1.8ns (-5K, -7K, -75B).
Refresh Cycle
-6K
Symbol
tREF
tSREX
-7K
-7
Parameter
Units
Notes
64
ms
1
—
ns
Min.
Max.
Min.
Max.
Min.
Max.
Refresh Period
—
64
—
64
—
Self Refresh Exit Time
10
—
10
—
10
1. 4096 auto refresh cycles.
Write Cycle
-6K
Symbol
-7K
-7
Parameter
Units
Min.
Max.
Min.
Max.
Min.
Max.
tDS
Data In Set-up Time
1.5
—
1.5
—
1.5
—
ns
tDH
Data In Hold Time
0.8
—
0.8
—
0.8
—
ns
tDPL
Data input to Precharge
12
—
14
—
14
—
ns
tWR
Write Recovery Time
12
—
14
—
14
—
ns
tDAL3
Data In to Active Delay
CAS Latency = 3
5
—
5
—
5
—
CK
tDAL2
Data In to Active Delay
CAS Latency = 2
4
—
4
—
4
—
CK
tDQW
DQM Write Mask Latency
0
—
0
—
—
CK
REV 1.1
10/01
18
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
Clock Frequency and Latency
Symbol
-6K
-7K
-7
Units
fCK
Clock Frequency
166
133
143
133
143
100
MHz
tCK
Clock Cycle Time
6
7.5
7
7.5
7
10
ns
tAA
CAS Latency
3
2
3
2
3
2
CK
tRP
Precharge Time
3
2
3
2
3
2
CK
RAS to CAS Delay
3
2
3
2
3
2
CK
tRC
Bank Cycle Time
9
7
9
7
9
7
CK
tRAS
Minimum Bank Active Time
6
5
6
5
6
5
CK
tDPL
Data In to Precharge
2
2
2
2
2
2
CK
tDAL
Data In to Active/Refresh
5
4
5
4
5
4
CK
tRRD
Bank to Bank Delay Time
2
2
2
2
2
2
CK
tWL
Write Latency
0
0
0
0
0
0
CK
tDQW
DQM Write Mask Latency
0
0
0
0
0
0
CK
tDQZ
DQM Data Disable Latency
2
2
2
2
2
2
CK
tCSL
Clock Suspend Latency
1
1
1
1
1
1
CK
tRCD
REV 1.1
10/01
Parameter
19
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
Package Dimensions (400mil; 54 lead; Thin Small Outline Package)
22.22 ± 0.13
11.76 ± 0.20
10.16 ± 0.13
Detail A
Lead #1
Seating Plane
0.10
0.80 Basic
0.35
+ 0.10
- 0.05
0.71REF
1.20 Max
Detail A
0.25 Basic
0.5
±
Gage Plane
0.1
0.05 Min
REV 1.1
10/01
20
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
Revision Log
Rev
05/01
Contents of Modification
Preliminary
Changed to Revision 1.0
Removed -75B speed grade
09/01
Added -7 speed grade.
Removed Icc6 low power product grade.
Changed to Revision 1.1
10/01
Changed tOH from 2.7ns to 3ns for all speed sort.
REV 1.1
10/01
21
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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