TI1 LMZM23600SILT 36-v, 0.5-a step-down dc-dc power module in 3.8-mm x 3-mm package Datasheet

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LMZM23600
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1 Features
3 Description
•
•
•
•
The LMZM23600 integrated-inductor module is
specifically designed for space-constrained industrial
applications and is available in fixed output voltage
options of 5-V and 3.3-V and an adjustable (ADJ)
output voltage option with 2.5-V to 15-V range. The
LMZM23600 supports an input voltage range of 4-V
to 36-V and can deliver up to 500-mA of output
current. This power module is extremely easy to use,
requiring only 2 external components for a 5-V or 3.3V output design. All aspects of the LMZM23600 are
optimized for performance driven and low EMI
industrial applications with space-constrained needs.
An open-drain, Power-Good output provides a true
indication of the system status and negates the
requirement for an additional supervisory component,
saving cost and board space. Seamless transition
between PWM and PFM modes along with a no-load
supply current of only 30 µA ensures high efficiency
and superior transient response for the entire loadcurrent range.
4-V to 36-V Wide Operating Input Voltage
Adjustable, 3.3-V, or 5-V Output Voltage Options
0.5-A Output Current
Only Input and Output Capacitors Needed for 5-V
and 3.3-V Output Designs
27-mm2 Solution Size With Single Sided Layout
30-µA Supply Current at No Load
2-µA Shutdown Current
Power-Good Flag
External Frequency Synchronization
MODE Selection Pin
– Forced PWM Mode for Constant Frequency
Operation
– Auto PFM Mode for High Efficiency at Light
Load
Built-in Control Loop Compensation, Soft Start,
Current Limit, and UVLO
Miniature 3.8-mm × 3-mm × 1.6-mm Package
1
•
•
•
•
•
•
•
•
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
MicroSiP™ (10)
3.80 mm × 3.00 mm
2 Applications
LMZM23600
•
•
•
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Factory Automation, Test and Measurement
Space Constrained Applications
LDO Replacement
space
space
space
Single-Sided Layout Solution Size
24-V to 5-V, 0.5-A DC-DC Converter
Schematic for Fixed Output Option
24-V to 5-V, 0.5-A DC-DC Converter
3.8 mm x 3.0 mm package
GND
GND
CIN
VIN
MODE/
SYNC
CIN
VIN
EN
PGOOD
COUT
FB
VOUT
VOUT
COUT
GND
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
LMZM23600 36-V, 0.5-A Step-Down DC-DC Power Module in 3.8-mm × 3-mm Package
LMZM23600
SNVSB53 – FEBRUARY 2018
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison ...............................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
5
5
5
5
6
9
10 Power Supply Recommendations ..................... 26
10.1 Supply Voltage Range .......................................... 26
10.2 Supply Current Capability ..................................... 26
10.3 Supply Input Connections ..................................... 26
11 Layout................................................................... 27
11.1 Layout Guidelines ................................................ 27
11.2 Layout Examples................................................... 28
12 Device and Documentation Support ................. 29
ADVANCE INFORMATION
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Detailed Description ............................................ 10
8.1
8.2
8.3
8.4
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
System Characteristics .............................................
9.1 Application Information............................................ 16
9.2 Typical Applications ................................................ 16
9.3 Do's and Don't's ...................................................... 25
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
15
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
29
30
13 Mechanical, Packaging, and Orderable
Information ........................................................... 30
Applications and Implementation ...................... 16
4 Revision History
2
DATE
REVISION
NOTES
February 2018
*
Initial release
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5 Device Comparison
Table 1. LMZM23600 Device Options
PART NUMBER
LMZM23600SILR
LMZM23600V3SILR
LMZM23600V5SILR
OUTPUT VOLTAGE
PACKAGE QTY
Adjustable
3000
3.3 V
3000
5V
3000
Adjustable
250
LMZM23600V3SILT
3.3 V
250
LMZM23600V5SILT
5V
250
ADVANCE INFORMATION
LMZM23600SILT
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LMZM23600
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6 Pin Configuration and Functions
SIL Package
10-Pin MicroSiP
Top View
ADVANCE INFORMATION
GND
1
10
DNC
MODE
/SYNC
2
9
DNC
VIN
3
8
DNC
EN
4
7
FB
5
6
VOUT
PGOOD
Thermal
Pad
Pin Functions
PIN
NO.
NAME
1
GND
TYPE (1)
DESCRIPTION
G
Ground for all circuitry. Reference point for all voltages.
2
MODE/SYNC
I
This is a multifunction mode control input which is tolerant of voltages up to the input voltage.
With this input tied LOW, the device is in Auto PFM mode with automatic transition between PFM
and PWM with diode emulation at light load. This mode is recommended when the application
requires high efficiency at light load.
With this input tied HIGH, the device is in forced PWM mode. The device switches at the internal
clock frequency. This mode is recommended when the application requires constant switching
frequency across the entire load current.
With a valid synchronization signal at this pin, the device switches in forced PWM mode at the
external clock frequency and synchronized with it at the rising edge of the clock.
Do not float this pin.
3
VIN
P
Input supply to the regulator. Connect a high-quality bypass capacitor(s) directly to this pin and the
GND pin (pin 1).
4
EN
I
Enable input to the regulator. HIGH = ON, LOW = OFF. This pin can be connected to VIN. Do not
float.
5
PGOOD
O
Open-drain, power-good output. Connect to a suitable voltage supply through a current limiting
resistor. HIGH = power is good, LOW = fault. This output terminal is LOW when EN is LOW.
6
VOUT
O
Output voltage terminal. It is internally connected to one terminal of the integrated inductor. Connect
an output filter capacitor from VOUT to GND and place the capacitor as close as possible to the
VOUT pin.
7
FB
I
Feedback input to the regulator.
If using the fixed 3.3-V or 5-V options of the device, connect this pin to the positive end of the output
filter capacitor (the VOUT node).
If using the adjustable output option of the device connect this to the feedback voltage divider and
keep this node as small as possible on the board layout.
8
DNC
O
Do not connect. Leave floating. This pin provides access to the internal VCC voltage of the device.
9
DNC
O
Do not connect. Leave floating. This pin provides access to the internal BOOT voltage for the high
side MOSFET driver.
10
DNC
O
Do not connect. Leave floating. This pin provides access to the internal SW voltage of the device.
G
This terminal is internally connected to GND and provides a wide thermal connection from the IC to
the PCB. Connect to electrical ground plane for adequate heat sinking.
Thermal Pad
(1)
4
G = Ground, I = Input, O = Output, P = Power
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7 Specifications
7.1 Absolute Maximum Ratings
MIN
MAX
UNIT
VIN to GND
–0.3
42
V
SW to GND
–0.3
VIN + 0.3
V
BOOT to SW
–0.3
3.6
V
EN to GND
–0.3
42
V
FB to GND (3.3-V and 5-V options)
–0.3
16
V
FB to GND (ADJ option)
–0.3
5.5
V
PGOOD to GND
–0.3
16
V
8
mA
MODE/SYNC to GND
–0.3
42
V
VCC to GND
-0.3
3.6
V
Operating junction temperature, TJ
–40
125
°C
Storage temperature, Tstg
–65
150
°C
PGOOD sink current
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
VOUT
NOM
MAX
UNIT
Input voltage
4
36
V
Output voltage (5 V)
0
5
V
Output voltage (3.3 V)
Output voltage (ADJ)
IOUT
Output current (0.5 A)
TJ
Operating junction temperature
0
3.3
V
2.5
15
V
0
0.5
A
–40
125
°C
7.4 Thermal Information
LMZM23601
THERMAL METRIC
(1)
SIL (USIP)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
ΨJT
ΨJB
(1)
45
°C/W
Junction-to-top characterization parameter
3
°C/W
Junction-to-board characterization parameter
20
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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ADVANCE INFORMATION
over operating free-air temperature range (unless otherwise noted) (1)
LMZM23600
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7.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature range of -40°C to +125°C, unless otherwise stated.
Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FEEDBACK
VFB
Initial output voltage accuracy
(3.3-V and 5-V fixed output)
VIN = 4 V to 36 V, open loop
–1.5%
VFB
Reference voltage (ADJ option)
VIN = 4 V to 36 V, open loop
0.985
IFB
Input current from FB to GND
(ADJ option)
FB = 1 V
1.5%
1
1.015
V
20
nA
7
µA
CURRENT
VIN = 12 V, VFB = +10%, VOUT = 5 V
ADVANCE INFORMATION
Operating quiescent current;
measured at VIN pin
IQ
IB
Bias current into the VOUT pin
Shutdown quiescent current;
measured at VIN pin
ISD
VIN = 12 V, VFB = +10%, VOUT = 5 V, TJ
= 85°C
16
VIN = 12 V, VFB = +10%, VOUT = 5 V, TJ
= 125°C
18
VIN = 24 V, VFB = +10%, VOUT = 5 V
12
µA
VIN = 24 V, VFB = +10%, VOUT = 5 V, TJ
= 85°C
24
VIN = 24 V, VFB = +10%, VOUT = 5 V, TJ
= 125°C
26
VIN = 24 V, VFB = +10%, VOUT = 5 V,
Mode = 0 V
48
EN = 0 V, VIN = 12 V, TJ = 25°C
1.8
EN = 0 V, VIN = 12 V, TJ = 85°C
80
3
EN = 0 V, VIN = 24 V, TJ = 25°C
5
EN = 0 V, VIN = 24 V, TJ = 85°C
µA
µA
10
UNDERVOLTAGE LOCKOUT (UVLO)
VIN_UVLO
Minimum input voltage to operate Rising
3.1
3.5
3.85
V
VIN_UVLO_HYST
UVLO hysteresis
0.2
0.25
0.3
V
6
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Electrical Characteristics (continued)
Limits apply over the recommended operating junction temperature range of -40°C to +125°C, unless otherwise stated.
Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER GOOD FLAG (PGOOD)
VPGOOD_OV
PGOOD upper threshold voltage
Rising, % of Vout
104%
106.7%
109%
VPGOOD_UV
PGOOD lower threshold voltage
Falling, % of Vout
92%
94.7%
97%
VPGOOD_GUARD
Magnitude of PGOOD lower
threshold difference from steady
state output voltage.
Steady state output voltage PGOOD
threshold read at the same TJ and VIN
4.5%
VPGOOD_HYST
PGOOD hysteresis as a percent
of output voltage set point
VPGOOD_VALID
Minimum input voltage for proper
PGOOD function
tRESET_FILTER
Glitch filter time constant for
PGOOD function
RPGOOD_RDSON
Low-level PGOOD function
output voltage
50-µA pullup to PGOOD pin, EN = 0 V, TJ
= 25°C
1.0
1.5
V
190
µs
50-µA pullup to PGOOD pin, VIN = 1.5 V,
EN = 0 V
0.4
0.5-mA pullup to PGOOD pin, VIN = 12 V,
EN = 0 V
0.4
1-mA pullup to PGOOD pin, VIN = 12 V,
EN = 3.3 V
0.4
RDSON of the PGOOD output
pull down
50
110
ADVANCE INFORMATION
VOL
1.4%
V
Ω
SWITCHING FREQUENCY
fSW
Switching frequency
VIN = 24 V, 5-V and 3.3-V fixed output
options
675
750
825
VIN = 24 V, ADJ output options
890
1000
1090
VIN = 36 V, 5-V and 3.3-V fixed output
options
750
VIN = 36 V, ADJ output options
800
kHz
FREQUENCY SYNCHRONIZATION AND MODE
fSYNC
Sync frequency range
DSYNC
Sync input duty cycle range
VMODE_HIGH
MODE/SYNC input logic HIGH
voltage to enter FPWM mode
VMODE_LOW
MODE/SYNC input logic LOW
voltage to enter AUTO PFM
mode
IMODE
MODE/SYNC leakage current
tMODE
5-V and 3.3-V fixed output options VOUT +
VDROPOUT < VIN < 36 V
500
825
ADJ output options VOUT + VDROPOUT<
VIN < 28 V
700
1100
25%
75%
2.3 V < HIGH state input < 5.5 V
kHz
1.5
V
0.4
VIN = 12 V, VMODE/SYNC = 3.3 V
1
VIN = 12 V, VMODE/SYNC = 12V
5
MODE transition time to FPWM
VIN = 12 V, VOUT = 5 V, IOUT= 20 mA
300
MODE transition time to AUTO
PFM
VIN = 12 V, VOUT = 5 V, IOUT = 20 mA
300
V
µA
µs
CURRENT LIMIT PROTECTION
IL-HS
0.5-A option high-side switch
current limit
IL-LS
0.5-A option low-side switch
current limit
IL-ZC
Zero-cross current limit
Duty cycle approaches 0%
MODE/SYNC = logic LOW
0.94
1.35
1.6
A
0.5
0.625
0.75
A
–0.01
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LMZM23600
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Electrical Characteristics (continued)
Limits apply over the recommended operating junction temperature range of -40°C to +125°C, unless otherwise stated.
Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V.
PARAMETER
Low-side reverse current limit
(positive current ino the SW pin
to GND)
IL-NEG
TEST CONDITIONS
MODE/SYNC = logic HIGH
MIN
TYP
MAX
UNIT
0.5
0.8
A
POWER STAGE CHARACTERISTICS
HS RDS-ON
High-side MOSFET on-resistance
220
mΩ
LS RDS-ON
Low-side MOSFET on-resistance
200
mΩ
tON-MIN
Minimum high-side on-time
IOUT = 500 mA
50
80
ns
tOFF-MIN
Minimum high-side off-time
IOUT = 500 mA
62
100
ns
ADVANCE INFORMATION
DMAX
Maximum switch duty cycle
L
Integrated inductor - inductance
LDCR
Integrated inductor - DCR
5-V and 3.3-V fixed output options
93%
ADJ option
91%
While in frequency foldback
97%
10
µH
390
mΩ
ENABLE
VEN
Enable input threshold voltage
VEN_HYST
Enable input threshold hysteresis
VEN_WAKE
Enable input wake-up threshold
IEN
Enable pin input current
Rising
1.7
1.92
V
0.42
0.52
V
0.4
VIN = VEN = 12 V
V
2.7
µA
VCC REGULATOR
VIN = 12 V, VOUT < 3.3 V
3.05
VIN = 12 V, VOUT ≥ 3.3V
3.15
VCC
Internal VCC voltage
VCC_UVLO
Internal VCC voltage input UVLO
VIN rising
2.27
VCC_UVLO_HYST
Internal VCC voltage input UVLO
hysteresis
Hysteresis below VCC_UVLO
150
tSS
Soft-start time
Time for VREF to ramp from 0% to 90%
1.8
tEN_LV
Turnon delay with low VIN
VIN < 4.2 V
4
ms
tEN
Turnon delay
VIN = 12 V
0.7
ms
tW
Short circuit wait time (hiccup
time)
8.0
ms
155
°C
15
°C
2.73
V
3.2
V
240
mV
5.5
ms
SOFT START
3.5
THERMAL PROTECTION
TSD
Thermal shutdown
TSD_HYST
Thermal shutdown hysteresis
8
Rising threshold
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7.6 System Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
xxx
5
xxx
UNIT
OUTPUT VOLTAGE REGULATION 5-V OPTION
VIN = 24 V, IOUT = 0 A, AUTO PFM
mode
VOUT
5-V option no load accuracy
AUTO PFM mode, IOUT = 0 A to xx A
xxx
AUTO PFM mode, IOUT > xx A
xxx
VIN = 24 V, IOUT = 0 A, FPWM mode
xxx
5
V
%/A
xxx
V
FPWM mode, IOUT > xx A
xxx
%/A
VIN = 6 V to 36 V
xxx
%/V
xxx
V
OUTPUT VOLTAGE REGULATION 3.3-V OPTION
VOUT
3.3-V option no load accuracy
xxx
3.3
AUTO PFM mode, IOUT = 0 A to xx A
xxx
AUTO PFM mode, IOUT > xx A
xxx
VIN = 24 V, IOUT = 0 A, FPWM mode
xxx
3.3
%/A
xxx
V
FPWM mode, IOUT > xx A
xxx
%/A
VIN = 4.5 V to 36 V
xxx
%/V
ADVANCE INFORMATION
VIN = 24 V, FPWM mode, IOUT = 0 A,
AUTO PFM mode
SUPPLY CURRENT
IQ-VIN
Input current to the VIN node of the
DC-DC converter while in regulation
VIN =12 V, VOUT = 3.3 V, IOUT = 0 A
23
VIN =12 V, VOUT = 5 V, IOUT = 0 A
30
VIN =24 V, VOUT = 3.3 V, IOUT = 0 A
30
VIN = 24 V, VOUT = 5 V, IOUT = 0 A
32
µA
EFFICIENCY
Efficiency
Typical efficiency 12-V input
VIN = 12 V, VOUT = 5 V, IOUT = 0.5 A
90%
Efficiency
Typical efficiency 12-V input
VIN = 12 V, VOUT = 3.3 V, IOUT = 0.5 A
87%
Efficiency
Typical efficiency 24-V input
VIN = 24 V, VOUT = 5 V, IOUT = 0.5 A
87%
Efficiency
Typical efficiency 24-V input
VIN = 24 V, VOUT = 3.3 V, IOUT = 0.5 A
83%
Efficiency
Typical efficiency 24-V input
VIN = 24 V, VOUT = 12 V, IOUT = 0.5 A
93%
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LMZM23600
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8 Detailed Description
8.1 Overview
The LMZM23600 is a 4-V to 36-V wide-input voltage range, low quiescent current, high-performance DC-DC
module designed specifically for space constrained industrial applications. The device is available in an
adjustable output voltage option with 2.5-V to 15-V output range, as well as fixed 5-V and 3.3-V output options.
The high level of integration and innovative packaging technology utilized in this nano module makes it possible
to design a 5-V or 3.3-V 0.5-A switching converter solution with only an input capacitor, an output capacitor, and
27 mm² of available board space.
8.2 Functional Block Diagram
VIN
ENABLE
LOGIC
EN
VCC
THERMAL
PROTECTION
ADVANCE INFORMATION
MODE/SYNC
OSCILLATOR
INT. REG.
BIAS
UVLO
HS CURRENT
SENSE
BOOT
1-V
REFERENCE
ERROR
AMPLIFIER
ADJ VOUT OPTION
FB
+
+
-
PWM
COMP.
CONTROL
LOGIC
-
MOSFET
DRIVER
VCC
MOSFET
DRIVER
OR
HS
SW
VOUT
LS
PFM MODE
CONTROL
FIXED VOUT OPTION
LS CURRENT
SENSE
PGOOD
POWER
GOOD
CONTROL
GND
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8.3 Feature Description
8.3.1 Control Scheme
The LMZM23600 nano module utilizes peak-current-mode-control architecture. This enables the use of wide
range of input voltages while maintaining constant switching frequency and good input and output transient
response. The device can be used with 5-V, 12-V, or 24-V typical industrial input voltage rail. The short minimum
on- and off-times ensure constant frequency regulation over a wide range of input to output voltage conversion
ratios. The adjustable (ADJ) output voltage option operates at 1000-kHz switching frequency. The minimum onand off- times allow for a duty factor window of 5% to 91% at 1000-kHz switching frequency. If the input voltage
exceeds approximately 28 V on the ADJ version, the frequency is smoothly reduced from 1000 kHz as a function
of input voltage. The switching frequency reduction allows output voltage regulation and the current mode control
to operate with a duty factor below 5%. The fixed 5-V and 3.3-V output options operate at 750 kHz nominal
switching frequency and the frequency fold back at high input voltage is not active or needed.
10
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Feature Description (continued)
The control architecture also uses frequency foldback at low input voltage in order to achieve low dropout
voltage, maintaining output regulation as the input voltage falls close to output voltage. The frequency foldback at
low input voltage is active for the ADJ as well as the 5-V and 3.3-V output options. The reduction in frequency is
smooth and continuous and is activated as the off-time approaches the minimum value. Under these conditions,
the LMZM23600 device operates much like a constant off-time converter allowing the maximum duty cycle to
reach 97%. This feature allows output voltage regulation with very low dropout.
The LMZM23600 features exceptional conversion efficiency at light load. As the load current is reduced, the
LMZM23600 transitions to light-load mode if the MODE/SYNC terminal is pulled low. In light-load mode the
device uses diode emulation to reduce the RMS inductor current and the switching frequency is reduced. The
fixed voltage versions (3.3-V and 5-V) do not need an external voltage divider connected to FB, which results in
saving two components and lower standby current when the load is in standby. As a result, the consumed supply
current is only 21 µA (typical) with 24-V to 3.3-V conversion and 24 µA (typical) with 24-V to 5-V conversion,
while the output is regulated with no load.
The LMZM23600 features an internally programmed soft-start time. The soft-start time is fixed internally at about
4 ms and is achieved by ramping the internal reference. The device starts up properly even if there is a voltage
present on output before the activation of the LMZM23600. In such cases, there is no switching until the output
voltage value programmed by the ramping reference voltage is above the pre-biased output value. Once the prebiased voltage level is reached by the reference ramp, the switching starts, and the output ramps up smoothly
from the pre-biased value up to the final output voltage.
8.3.3 Enable and External UVLO Function
Some applications may require a precision enable or custom input voltage lock-out (UVLO) functionality. Setting
up external UVLO based on the application needs would prevent the converter from trying to regulate the output
voltage until after the input voltage has reached a desired minimum level. Such function can be used to lower the
current demand from the input supply as the supply is still starting up.
The LMZM23600 features a precision enable (EN) input terminal. The EN input logic has two internal thresholds.
The first rising threshold is at 0.9V typical. Its purpose is to wake up the internal VCC regulator to bias the
internal circuitry. The EN rising threshold to start switching is 1.8V (typical) with 0.5V (typical) hysteresis. A
voltage divider from VIN to EN can be used to set the VIN voltage at which the regulator starts the voltage
conversion. The EN terminal is rated for up to the input voltage and can be connected directly to VIN for an
always-on operation. Pulling the EN pin below 0.4 V puts the LMZM23600 in shutdown mode. In shutdown mode
and 12-V input voltage the LMZM23600 only consumes 1.8 µA (typical) of input current.
8.3.4 Current Limit
The LMZM23600 devices features two current limits inside the IC. A coarse high side or peak current limit is
provided to protect against faults. The high-side current limit limits the duration of the on-period of the high-side
power MOSFET during a given clock cycle. A precision cycle-by-cycle valley current limit prevents excessive
average output current. A new switching cycle is not initiated until the inductor current drops below the valley
current limit.
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8.3.2 Soft-Start Function
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Feature Description (continued)
Vout
Peak
Valley
ADVANCE INFORMATION
Figure 1. Current Limit Operation During Output Short Circuit
Figure 1 shows the response of the LMZM23600 device to a short circuit on the output: The peak current limit
prevents excessive peak current while the valley current limit prevents excessive average inductor current. After
a small number of cycles, hiccup mode is activated.
8.3.5 Hiccup Mode
In order to prevent excessive heating and power consumption under sustained output short circuit conditions, a
hiccup mode operation is included in the control logic. If an over current condition is maintained on the output,
the LMZM23600 device shuts off both power MOSFETs and waits for a hiccup interval, tW, of approximately 8
ms. After the wait period, the device restarts operation beginning with a soft-start time interval.
Vout
Figure 2. Hiccup Operation
Figure 2 shows hiccup mode operation: The LMZM23600 attempts to restart periodically, following a hiccup wait
interval. If the fault at the output is still present, another hiccup wait interval is initiated, followed by another
restart attempt. This sequence continues until the output short circuit is removed. When the output short circuit is
removed, the output ramps up during the next restart sequence.
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Feature Description (continued)
8.3.6 Power Good (PGOOD) Function
The LMZM23600 has a built-in power-good signal presented at the PGOOD terminal. This signal indicates
whether the output voltage is within the regulation window. The PGOOD terminal is an open-drain output that
requires a pullup resistor to a nominal voltage source of 15 V or less. The absolute maximum PGOOD sink
current is 8 mA. Typically, TI recommends a pullup resistor value between 10 kΩ and 100 kΩ. Refer to Electrical
Characteristics for the power-good thresholds and hysteresis for undervoltage and overvoltage detection.
8.3.7 MODE/SYNC Function
8.3.7.1 Forced PWM Mode
This feature may be activated and deactivated while the part is regulating without removing the load. This feature
activates and deactivates gradually, preventing perturbation of output voltage. When in FPWM mode, a limited
reverse current is allowed through the inductor allowing power to pass from the regulators output to its input.
8.3.7.2 Auto PFM Mode
If the MODE/SYNC terminal is held low the LMZM23600 device enables automatic power-saving-mode transition
at light load. With high load the LMZM23600 regulates the output using normal PWM operation. When the load is
light, the control logic smoothly transitions to PFM operation and diode emulation. In this mode, the high side
MOSFET is turned on for one or more pulses to provide energy to the load. The on-time of the high side in this
mode depends on the input voltage level and a pre-programmed internal IPEAK-MIN current level. The higher the
input voltage is, the shorter the on-time is. At this point, there is a longer off-time during which the output would
still be in the regulation window because the load is light, and the output is not getting discharged as quickly. The
duration of the off-time depends on the load current level. Lighter load results in longer off-time. This mode of
operation results in excellent conversion efficiency at very light load. When auto-PFM mode is used, the output
voltage at no load is approximately 1% higher than FPWM operation.
8.3.7.3 Dropout Mode
When the input voltage level decreases and approaches the output voltage level, the buck regulator reaches its
maximum duty cycle or minimum off-time requirement for each switching cycle. At this point the output is no
longer regulated and follows the input voltage minus the voltage drops from VIN to VOUT.
In order to maximize the input voltage range for which the output is still regulated, the LMZM23600 features
frequency foldback at low input voltage. This operation extends the switching period and, for a given fixed
minimum off-time, it prolongs the maximum duty cycle of the regulator. As a result, the output voltage can still be
well regulated even as the input voltage level is very close to the output voltage. This feature can be useful for
battery applications (maximizing the useful battery range) or in applications where large input voltage variations
can be expected.
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ADVANCE INFORMATION
When constant frequency operation is more important than light load efficiency, the MODE/SYNC input of the
LMZM23600 device must be pulled high or a valid synchronization input must be provided. This activates forcedPWM-mode operation. Once activated, this feature ensures that the switching frequency stays constant across
the entire load current range, while operating between the minimum and maximum duty cycle limits. The diode
emulation feature is turned off in this mode. This means that the device remains in CCM under light loads. The
switching frequency in forced PWM mode is only reduced when the input voltage-to-output voltage ratio results in
minimum on-time limitation (ADJ version only) or minimum off-time limitation near dropout.
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Feature Description (continued)
8.3.7.4 SYNC Operation
It is often desirable to synchronize the switching frequency of multiple regulators in a single system. This
technique results in better defined EMI behavior and can reduce the need for capacitance on some power rails.
The LMZM23600 MODE/SYNC input allows synchronization to an external clock. The LMZM23600 implements
an in-phase locking scheme – the rising edge of the clock signal provided to the input of the LMZM23600 device
corresponds to turning on the high-side MOSFET device. This function is implemented using phase locking over
a limited frequency range eliminating large glitches upon initial application of an external clock. The clock fed into
the LMZM23600 device replaces the internal free-running clock but does not affect frequency foldback operation.
The output voltage continues to be well regulated using frequency reduction when duty factors outside of the
normal duty cycle range are reached.
The device remains in FPWM mode and operates in CCM for light loads when synchronization input is provided.
The MODE/SYNC function logic always prioritizes the proper regulation of the output voltage. Table 2
summarizes the MODE/SYNC function and the operating switching frequency with various conditions.
Table 2. Switching Frequency and MODE/SYNC Function
ADVANCE INFORMATION
DEVICE
ADJ Output
Fixed
3.3-V
Output
or 5-V
Output
SWITCHING FREQUENCY
MODE/SYNC
LIGHT LOAD
FULL LOAD
VIN > 28 V
IN DROPOUT MODE
Logic LOW = Auto PFM
Reduced
(save power)
Fixed
1000 kHz
Reduced
(maintain regulation)
Reduced
(maintain regulation)
Logic HIGH = FPWM
Fixed
1000 kHz
Fixed
1000 kHz
Reduced
(maintain regulation)
Reduced
(maintain regulation)
Valid FSYNC Input
FSYNC
FSYNC
Reduced
(maintain regulation)
Reduced
(maintain regulation)
Logic LOW = Auto PFM
Reduced
(save power)
Fixed
750 kHz
Fixed
750 kHz
Reduced
(maintain regulation)
Logic HIGH = FPWM
Fixed
750 kHz
Fixed
750 kHz
Fixed
750 kHz
Reduced
(maintain regulation)
Valid FSYNC Input
FSYNC
FSYNC
FSYNC
Reduced
(maintain regulation)
8.3.8 Thermal Protection
The LMZM23600 monitors its junction temperature (TJ) and shuts off if the it gets too hot. The thermal shutdown
threshold for the junction is typically 155°C. Both, high-side and low-side power MOSFETs are turned off until the
junction temperature has decreased under the hysteresis level, typically 15°C below the shutdown temperature.
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8.4 Device Functional Modes
8.4.1
Shutdown
The LMZM23600 device shuts down most internal circuitry and high-side and low-side power MOSFETs under
any of the following conditions:
1. EN is low
2. VIN is below the falling UVLO threshold
3. Junction temperature exceeds TSD threshold
The PGOOD flag remains operational with input voltage as low as 1.5 V.
8.4.2 FPWM Operation
8.4.3 Auto PFM Mode Operation
If MODE/SYNC is below the VMODE/SYNC low threshold, reverse current in the inductor is not allowed. This feature
is called diode emulation. While the load is heavy, the regulator uses PWM mode to control the output. If the load
is light, the control logic transitions to PFM mode. The switching frequency is reduced, resulting in excellent
energy savings while regulation is maintained. Because the frequency is reduced and switching pulses can come
in groups, the output voltage ripple can increase slightly. Under this condition, the output ripple can be reduced
by increasing the output capacitance.
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ADVANCE INFORMATION
If MODE/SYNC is above the VMODE/SYNC high threshold or a valid synchronizing is applied to MODE/SYNC,
constant frequency operation is maintained across load. The ADJ option of the device folds back the frequency
when VIN exceeds 28 V typical so that the output voltage can be properly regulated. See Table 2 for all use
cases and options. FPWM mode requires negative current be allowed in the inductor if the load is light. If a large
negative load is present, operation is halted by a reverse current limit, IL-NEG.
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMZM23600 device is a step-down nano module, typically used to efficiently convert a high DC input voltage
to a lower DC output voltage with a maximum output current of up to 1 A. The following sections describe a
simple design procedure for creating a DC-DC converter design with these modules.
9.2 Typical Applications
ADVANCE INFORMATION
The LMZM23600 module requires very few external components for a complete DC-DC converter design. If the
output voltage for the application is 3.3 V or 5 V, the fixed output voltage option of the LMZM23600 device can
be used. In such cases, the design is as simple as adding only an input and an output capacitor. The adjustable
output voltage version of the device allows the user to set the output voltage between 2.5 V and 15 V with the
addition of two feedback resistors to the bill of materials.
GND
GND
CIN
VIN
MODE/
SYNC
VIN
EN
PGOOD
FB
VOUT
VOUT
COUT
GND
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Figure 3. Fixed 5-V or 3.3-V Typical Application Circuit
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Typical Applications (continued)
GND
GND
CIN
VIN
MODE/
SYNC
VIN
RFBT
EN
FB
RFBB
VOUT
VOUT
PGOOD
COUT
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Figure 4. Adjustable 2.5-V to 15-V Output Typical Application Circuit
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 3 as the input parameters.
Table 3. Design Parameters
DESIGN PARAMETER
VALUE
Input voltage range
8 V to 36 V
Output voltage
5V
Output current range
No load to 0.5 A
COMMENT
This range covers a typical 12-V or 24-V industrial supply
Fixed or adjustable output voltage can be used
9.2.2 Detailed Design Procedure
9.2.2.1 Input Capacitor Selection
The input capacitor selection and placement on the board layout is very important for any buck converter design.
This component provides the pulsing high di/dt current every switching cycle and reduces the input voltage ripple
seen by the buck converter. Use a good-quality 10-µF, 1210 (3225) case size, X5R or X7R ceramic capacitor
with sufficient voltage rating on the input of the device. Alternatively, in applications with strict size constraints
and more stable input voltage it is possible to use a 10-µF 1206 (3216) case size or a parallel combination of 2 ×
4.7 µF, 0805 (2012), X5R or X7R capacitors. Ceramic capacitors have a DC bias dependence on their effective
capacitance and can de-rate their value significantly when used at higher bias voltage. TI recommends ceramic
capacitors with ≥ 50-V rating when using the device with a 24-V input supply. Ceramic capacitors with ≥ 25-V
rating are recommended when using the device with a 12-V input supply.
Just like with any buck converter, place the input capacitor as close as possible and next to the LMZM23600.
Connect the capacitor directly to the VIN (pin 3) and GND (pin 1) terminals of the device. This placement
ensures that the area of the high di/dt current loop in the buck converter is kept to a minimum, resulting in the
lowest possible inductance in the switching current path. The proper placement of the input capacitor in any
buck converter helps to keep the output noise of the converter to a minimum. See Table 4 for several input
capacitor choices.
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ADVANCE INFORMATION
GND
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Table 4. Input Capacitor Selection
VALUE
VOLTAGE
RATING
CASE
SIZE
DIELECTRIC
QUANTITY
VENDOR
PART NUMBER
10 µF
50 V
1210
(3225)
X7R
1
TDK
C3225X7R1H106M250AC
10 µF
50 V
1210
(3225)
X7R
1
MuRata
GRJ32ER71H106KE11
10 µF
50 V
1206
(3216)
X5R
1
TDK
C3216X5R1H106K160AB
4.7 µF
50 V
0805
(2012)
X5R
2
TDK
C2012X5R1H475K125AB
For this design example a single 10-µF, 50-V 1210 X7R capacitor is used.
9.2.2.2 Output Capacitor Selection
ADVANCE INFORMATION
TI recommends low-ESR ceramic capacitors for output capacitors. There is a requirement for minimum
capacitance on the output of the LMZM23600 in order to ensure stable operation. The minimum output
capacitance requirement depends on the output voltage setting. There is also a maximum capacitance value for
stability and in order to limit the in-rush supply current. Excessive output capacitance can result in excessive
current to be drawn from the input supply during startup. If the overcurrent condition is persistent during start-up,
the over current protection of the LMZM23600 can activate and affect the normal output voltage ramp up. In
extreme cases, the Hiccup Mode operation can be activated during start-up if the maximum output capacitance is
exceeded.
Refer to Table 5 for the minimum, recommended, and maximum output capacitance values for each output
voltage. For this example with a 5-V output a 22-µF capacitor can be used.
Table 5. Output Capacitor
OUTPUT VOLTAGE
MINIMUM
OUTPUT CAPACITANCE
RECOMMENDED
OUTPUT CAPACITANCE
MAXIMUM
OUTPUT CAPACITANCE
2.5 V
47 µF
68 µF
390 µF
3.3 V
22 µF
33 µF
330 µF
5V
15 µF
22 µF
220 µF
12 V
10 µF
15 µF
200 µF
15 V
10 µF
15 µF
200 µF
9.2.2.3 Feedback Voltage Divider for Adjustable Output Voltage Versions
GND
GND
CIN
VIN
MODE/
SYNC
VIN
RFBT
EN
FB
RFBB
PGOOD
VOUT
VOUT
COUT
GND
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Figure 5. Adjustable 2.5 V to 15 V Output Typical Application Circuit
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The adjustable version of the LMZM23600 regulates the output voltage such that the FB node voltage is equal to
the internal VREF voltage of 1 V. The output voltage is then set by a feedback voltage divider formed by two
external resistors, RFBT and RFBB.
VOUT = VREF u
RFBB + RFBT
RFBB
(1)
The range of adjustable output voltage is 2.5 V to 15 V.
Choose a value for RFBT in the kΩ range, and calculate the bottom resistor RFBB using Equation 2:
RFBT
RFBB =
VOUT
1
VREF
(2)
For this design example the output voltage is set to 5 V. The fixed 5-V output voltage option of the LMZM23600
can be used without any feedback resistors. If the adjustable output option is used for this design condition, the
top feedback resistor RFBT can be set to 102 kΩ. The RFBB value results in 25.5 kΩ.
The PGOOD terminal of the LMZM23600 is an open-drain output. If the application requires a power-good flag,
use a 100-kΩ pullup resistor from the PGOOD terminal to an external voltage rail. If a power-good function is not
necessary, the PGOOD terminal can be left floating.
9.2.2.5 VIN Divider and Enable
If the application requires custom input UVLO level higher than the internal UVLO, a voltage divider can be
connected from VIN to the EN terminal to set the turnon threshold.
VIN
RENT
EN
RENB
GND
Figure 6. Enable Divider to Set External UVLO Threshold
Choose the top resistor RENB between 10 kΩ and 50 kΩ and calculate the RENT according to Equation 3.
§ VSTART ·
¨¨
1¸¸ u RENB
© VEN
¹
RENT
VSTOP
§ VEN _ HYST ·
¸
VSTART u ¨¨1
VEN ¸¹
©
where
•
•
•
•
VSTART is the rising input voltage level at which switching starts. Choose this value based on the application
requirements.
VSTOP is the input voltage at which switching stops
VEN is the rising threshold on EN; see Electrical Characteristics
VEN_HYST is the hysteresis on the EN threshold; see Electrical Characteristics
(3)
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ADVANCE INFORMATION
9.2.2.4 RPU - PGOOD Pull Up Resistor
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9.2.3 Application Curves
Unless otherwise stated, the following conditions apply: VIN = 24 V, TA = 25°C.
9.2.3.1 VOUT = 5 V
100
90
80
Efficiency (%)
70
IOUT
(200 mA/DIV)
60
50
VIN = 6.5V PFM
VIN = 6.5V FPWM
VIN = 12 V PFM
VIN = 12 V FPWM
VIN = 24 V PFM
VIN = 24 V FPWM
VIN = 36 V PFM
VIN = 36 V FPWM
40
30
20
10
0
0.0001
0.001
0.01
0.1 0.2 0.5 1
Output Current (A)
ADVANCE INFORMATION
MODE = Low for Auto PFM Mode
MODE = High for FPWM Mode
VOUT
(20 mV/DIV)
Time (500 µs/DIV)
2 3 5 710
D002
5-V Adjustable Output
5-V Adjustable Output
10% to 100% Load Step
Figure 7. Efficiency
MODE = High
Figure 8. Load Transient
VOUT Ripple
(5 mV/DIV)
VOUT Ripple
(20 mV/DIV)
20MHz BW
Time (1 µs/DIV)
5-V Adjustable Output
IOUT = 0.5 A
Time (1 µs/DIV)
5-V Adjustable Output
Figure 9. Output Ripple 20 MHz BW
250MHz BW
IOUT = 0.5 A
Figure 10. Output Ripple 250-MHz BW
5.1
Output Voltage (V)
5.05
EN
(2 V/DIV)
5
VOUT
(2 V/DIV)
4.95
VIN = 5 V PFM
VIN = 5 V FPWM
VIN = 12 V PFM
VIN = 12 V FPWM
VIN = 24 V PFM
VIN = 24 V FPWM
VIN = 36 V PFM
VIN = 36 V FPWM
4.9
4.85
IOUT
(200 mA/DIV)
PGOOD
(2 V/DIV)
4.8
0
0.05
0.1
0.15
0.2 0.25 0.3 0.35
Output Current (A)
0.4
0.45
Time (2 ms/DIV)
0.5
D008
Figure 11. Line and Load Regulation
Figure 12. Start-up With 24-V Input
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9.2.3.2 VOUT = 3.3 V
100
90
80
IOUT
(200 mA/DIV)
60
50
VIN = 6.5V PFM
VIN = 6.5V FPWM
VIN = 12 V PFM
VIN = 12 V FPWM
VIN = 24 V PFM
VIN = 24 V FPWM
VIN = 36 V PFM
VIN = 36 V FPWM
40
30
20
10
0
0.0001
0.001
0.01
0.1 0.2 0.5 1
Output Current (A)
MODE = High for FPWM Mode
MODE = Low for Auto PFM Mode
VOUT
(20 mV/DIV)
Time (500 µs/DIV)
2 3 5 710
D003
3.3-V Adjustable Output
3.3-V Adjustable Output
10% to 100% Load Step
Figure 13. Efficiency
MODE = High
Figure 14. Load Transient
VOUT Ripple
(5 mV/DIV)
ADVANCE INFORMATION
Efficiency (%)
70
VOUT Ripple
(20 mV/DIV)
3.3-V Adjustable Output
Time (1 µs/DIV)
20MHz BW
Time (1 µs/DIV)
IOUT = 0.5 A
3.3-V Adjustable Output
Figure 15. Output Ripple 20-MHz BW
250MHz
20MHz BW
IOUT = 0.5 A
Figure 16. Output Ripple 250 MHz BW
3.36
3.34
EN
(2 V/DIV)
Output Voltage (V)
3.32
VOUT
(2 V/DIV)
3.3
3.28
VIN = 5 V PFM
VIN = 5 V FPWM
VIN = 12 V PFM
VIN = 12 V FPWM
VIN = 24 V PFM
VIN = 24 V FPWM
VIN = 36 V PFM
VIN = 36 V FPWM
3.26
3.24
3.22
IOUT
(200 mA/DIV)
PGOOD
(2 V/DIV)
Time (2 ms/DIV)
3.2
0
0.05
0.1
0.15
0.2 0.25 0.3 0.35
Output Current (A)
MODE = High for FPWM Mode
MODE = Low for Auto PFM Mode
0.4
0.45
0.5
D009
3.3-V Adjustable Output
3.3-V Adjustable Output
Figure 17. Line and Load Regulation
Toggle Enable
Figure 18. Start-up With 24-V Input
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9.2.3.3 VOUT = 12 V
100
90
80
Efficiency (%)
70
IOUT
(200 mA/DIV)
60
50
VIN = 15V PFM
VIN = 15V FPWM
VIN = 18 V PFM
VIN = 18 V FPWM
VIN = 24 V PFM
VIN = 24 V FPWM
VIN = 36 V PFM
VIN = 36 V FPWM
40
30
20
10
0
0.0001
0.001
0.01
0.1 0.2 0.5 1
Output Current (A)
MODE = High for FPWM Mode
MODE = Low for Auto PFM Mode
VOUT
(50 mV/DIV)
Time (500 µs/DIV)
2 3 5 710
D004
12-V Adjustable Output
12-V Adjustable Output
10% to 100% Load Step
MODE = High
Figure 19. Efficiency
ADVANCE INFORMATION
Figure 20. Load Transient
VOUT Ripple
(5 mV/DIV)
VOUT Ripple
(20 mV/DIV)
20MHz BW
Time (1 µs/DIV)
12-V Adjustable Output
IOUT = 0.5 A
Time (1 µs/DIV)
12-V Adjustable Output
Figure 21. Output Ripple 20-MHz BW
250MHz BW
IOUT = 0.5 A
Figure 22. Output Ripple 250-MHz BW
12.2
12.15
Output Voltage (V)
12.1
EN
(2 V/DIV)
12.05
12
VOUT
(5 V/DIV)
11.95
VIN = 5 V PFM
VIN = 5 V FPWM
VIN = 12 V PFM
VIN = 12 V FPWM
VIN = 24 V PFM
VIN = 24 V FPWM
VIN = 36 V PFM
VIN = 36 V FPWM
11.9
11.85
11.8
11.75
11.7
IOUT
(200 mA/DIV)
PGOOD
(2 V/DIV)
Time (2 ms/DIV)
11.65
0
0.05
0.1
0.15
0.2 0.25 0.3 0.35
Output Current (A)
MODE = High for FPWM Mode
MODE = Low for Auto PFM Mode
0.4
0.45
0.5
D010
12-V Adjustable Output
12-V Adjustable Output
Figure 23. Line and Load Regulation
22
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Toggle Enable
Figure 24. Start-up With 24-V Input
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9.2.3.4 VOUT = 15 V
100
90
80
IOUT
(200 mA/DIV)
Efficiency (%)
70
60
50
VIN = 18V PFM
VIN = 18V FPWM
VIN = 22 V PFM
VIN = 22 V FPWM
VIN = 24 V PFM
VIN = 24 V FPWM
VIN = 36 V PFM
VIN = 36 V FPWM
40
30
20
10
0
0.0001
0.001
0.01
0.1 0.2 0.5 1
Output Current (A)
MODE = High for FPWM Mode
MODE = Low for Auto PFM Mode
VOUT
(50 mV/DIV)
Time (500 µs/DIV)
2 3 5 710
D006
15-V Adjustable Output
15-V Adjustable Output
10% to 100% Load Step
MODE = High
Figure 26. Load Transient
VOUT Ripple
(5 mV/DIV)
ADVANCE INFORMATION
Figure 25. Efficiency
VOUT Ripple
(20 mV/DIV)
20MHz BW
Time (1 µs/DIV)
15-V Adjustable Output
IOUT = 0.5 A
Time (1 µs/DIV)
15-V Adjustable Output
Figure 27. Output Ripple 20-MHz BW
250MHz BW
IOUT = 0.5 A
Figure 28. Output Ripple 250-MHz BW
15.3
15.2
EN
(2 V/DIV)
Output Voltage (V)
15.1
15
VOUT
(10 V/DIV)
14.9
VIN = 5 V PFM
VIN = 5 V FPWM
VIN = 12 V PFM
VIN = 12 V FPWM
VIN = 24 V PFM
VIN = 24 V FPWM
VIN = 36 V PFM
VIN = 36 V FPWM
14.8
14.7
14.6
IOUT
(200 mA/DIV)
PGOOD
(2 V/DIV)
Time (2 ms/DIV)
14.5
0
0.05
0.1
0.15
0.2 0.25 0.3 0.35
Output Current (A)
MODE = High for FPWM Mode
MODE = Low for Auto PFM Mode
0.4
0.45
0.5
D011
15-V Adjustable Output
15-V Adjustable Output
Figure 29. Line and Load Regulation
Toggle Enable
Figure 30. Start-up with 24-V Input
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SNVSB53 – FEBRUARY 2018
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9.2.3.5 VOUT = 2.5 V
100
90
80
IOUT
(200 mA/DIV)
Efficiency (%)
70
60
50
VIN = 5 V PFM
VIN = 5 V FPWM
VIN = 12 V PFM
VIN = 12 V FPWM
VIN = 24 V PFM
VIN = 24 V FPWM
VIN = 36 V PFM
VIN = 36 V FPWM
40
30
20
10
0
0.0001
0.001
0.01
0.1 0.2 0.5 1
Output Current (A)
MODE = High for FPWM Mode
MODE = Low for Auto PFM Mode
VOUT
(20 mV/DIV)
Time (500 µs/DIV)
2 3 5 710
D005
2.5-V Adjustable Output
2.5-V Adjustable Output
10% to 100% Load Step
ADVANCE INFORMATION
Figure 31. Efficiency
MODE = High
Figure 32. Load Transient
VOUT Ripple
(5 mV/DIV)
VOUT Ripple
(20 mV/DIV)
20MHz BW
Time (1 µs/DIV)
2.5-V Adjustable Output
IOUT = 0.5 A
Time (1 µs/DIV)
2.5-V Adjustable Output
Figure 33. Output Ripple 20-MHz BW
250MHz BW
IOUT = 0.5 A
Figure 34. Output Ripple 250-MHz BW
2.6
Output Voltage (V)
2.55
EN
(2 V/DIV)
2.5
VOUT
(2 V/DIV)
2.45
VIN = 5 V PFM
VIN = 5 V FPWM
VIN = 12 V PFM
VIN = 12 V FPWM
VIN = 24 V PFM
VIN = 24 V FPWM
VIN = 36 V PFM
VIN = 36 V FPWM
2.4
2.35
IOUT
(200 mA/DIV)
PGOOD
(2 V/DIV)
Time (2 ms/DIV)
2.3
0
0.05
0.1
0.15
0.2 0.25 0.3 0.35
Output Current (A)
0.4
0.45
0.5
D007
Figure 35. Line and Load Regulation
24
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Figure 36. Start-up with 24-V Input
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SNVSB53 – FEBRUARY 2018
9.3 Do's and Don't's
•
•
•
•
•
•
ADVANCE INFORMATION
•
Don't: Exceed the absolute maximum ratings of the device.
Don't: Exceed the ESD ratings of the device.
Don't: Exceed the recommended operating conditions.
Don't: Allow the EN or MODE/SYNC terminals to float.
Don't: Allow the output voltage to exceed the input voltage, nor go below ground.
Do: Follow all of the guidelines and/or suggestions found in this data sheet, before committing your design to
production.
Do: Review your designs with TI Application Engineers on the E2E forum.
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SNVSB53 – FEBRUARY 2018
www.ti.com
10 Power Supply Recommendations
10.1 Supply Voltage Range
The voltage of the input supply must not exceed the absolute maximum ratings and the recommended operating
conditions of the LMZM23600.
10.2 Supply Current Capability
The input supply must be able to supply the required input current to the LMZM23600 converter. The required
input current depends on the application's minimum input voltage, the required maximum output current, the
output voltage, and the converter efficiency η for this condition.
IIN t
VOUT u IOUTMAX
VINMIN u K
(4)
As an example, assuming that the adjustable output voltage version of the LMZM23600 is used for a 5-V, 0.5-A
output converter design with 12-V minimum input voltage. The conversion efficiency for this condition is about
85 %. The required input current from the supply would be 0.49 A, so an input power supply with ≥ 0.5 A current
capability would be recommended.
ADVANCE INFORMATION
10.3 Supply Input Connections
Long input connection cables can cause issues with the normal operation of any buck converter. Some of the
issues could be a voltage drop in the input voltage or stability probes because of the added series input
inductance.
10.3.1 Voltage Drops
Using long input wires to connect the supply to the input of any converter adds impedance in series with the
input supply. This impedance can cause a voltage drop at the VIN pin of the converter when the output of the
converter is loaded. If the input voltage is near the minimum input operating voltage for the design, this added
voltage drop can cause the converter to drop out or reset. If long wires are used during testing, it is
recommended to add some bulk (for example, electrolytic) capacitance at the input of the converter.
10.3.2 Stability
The added inductance of long input cables together with the ceramic (and low ESR) input capacitor can result in
an underdamped RLC network at the input of the buck converter. This circuit may cause instability, or overvoltage transients at the VIN pin each time the input supply is cycled on and off. If long wires are used, TI
recommends adding some electrolytic bulk capacitance in parallel with the ceramic input capacitor. The ESR of
the bulk capacitor improves the damping. Use an electrolytic capacitor with a capacitance at least four times
larger than the ceramic input capacitance.
CBULK t 4 u CCER
(5)
The required ESR from the bulk capacitor depends on the cable inductance.
ESRBULK t
LCABLE
CCER
(6)
For example, two cables (one for VIN and one for GND), each 1 meter (approximately 3 feet) long with ~1 mm
diameter (18 AWG), placed 1 cm (approximately 0.4 inch) apart forms a rectangular loop resulting in about 1.2
µH of inductance. The inductance in this example can be decreased to almost half if the input wires are twisted.
Based on a 10-µF ceramic input capacitor, the recommended parallel CBULK is ≥ 40 µF. Using a 47-µF capacitor
is sufficient. Based on about 1.2 µH of inductance and 10 µF of ceramic input capacitance, the recommended
ESR of the bulk capacitor is 0.35 Ω or larger. See TI User Guide, Simple Success with Conducted EMI for DCDC Converters for more details on input filter design.
26
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SNVSB53 – FEBRUARY 2018
11 Layout
11.1 Layout Guidelines
1. Minimize the inductance in the switching current path of the converter. The switching current path in the buck
converter is formed by the input capacitor and the power switches (for example, MOSFETs). A common
mistake in many buck converter layouts is placing the input capacitor far from the IC. This introduces
inductance in the switching current path, which leads to high frequency ringing on the switching node, which
results in high frequency noise coupled all the way to the output voltage. The input capacitor placement
affects the amount of noise on the output in a buck converter. Place the input capacitor as close as
possible, right next to the LMZM23600 ensures that the switching current path area is kept to a minimum.
This results in the lowest possible inductance in the path of high di/dt current.
2. Protect any sensitive nodes in the converter design. The feedback node is usually a sensitive area of the
converter and needs to be away from any noise sources. The fixed 5-V and 3.3-V output voltage versions of
the LMZM23600 have the feedback resistors internal to the device, and the sensitive node is inside the
module. However, if the adjustable option is used, then two feedback resistors are required to set the output
voltage. A common mistake in many layouts is placing the divider close to the load, far from the device, and
then using a long feedback trace back to the regulator. A long feedback trace can potentially pick up noise
from other nearby circuits. TI recommends placing the feedback divider as close as possible to the
LMZM23600 device so that the feedback node is as small as possible.
3. Provide enough copper for heat dissipation. The board copper provides a thermal resistance path for the
heat to flow out of the package and dissipate into the environment. Place a dog-bone shape of ground (GND)
copper under the module for proper heat sinking. Also, place thermal vias to provide a heat path to the other
board layers. TI recommends an unbroken GND plane or GND area of copper on the top and bottom layers.
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Product Folder Links: LMZM23600
27
ADVANCE INFORMATION
Good board layout is essential for the proper operation of any switching regulator. A poor layout can ruin an
otherwise perfect schematic design. The good news is that it is relatively easy to achieve an optimized layout
when using a module because some of the critical nodes for the board layout are internal to the device. To have
a good layout with this module, the designer should follow these main objectives:
LMZM23600
SNVSB53 – FEBRUARY 2018
www.ti.com
11.2 Layout Examples
INPUT CAPACITOR
PLACED NEXT TO
THE MODULE
OUTPUT
CAPACITOR
MODULE
GND
GND
GND
EN
VIN
FB
MODE
PG
VIN
VOUT
VOUT
ADVANCE INFORMATION
FEEDBACK
CONNECTION
GND COPPER FOR
HEAT SINKING
=THERMAL VIAS
Figure 37. Layout Example With Fixed Output Version
INPUT CAPACITOR
PLACED NEXT TO
THE MODULE
BOTTOM FB
RESISTOR
TOP FB
OUTPUT
RESISTOR CAPACITOR
MODULE
GND
GND
GND
EN
VIN
MODE
VIN
PG
GND COPPER FOR
HEAT SINKING
FB
VOUT
MINIMIZE FB
NODE
VOUT
=THERMAL VIAS
Figure 38. Layout Example With Adjustable Output Version
28
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation request the following:
AN-1149 Layout Guidelines for Switching Power Supplies
AN-1229 Simple Switcher PCB Layout Guidelines (SNVA054)
Using New Thermal Metrics
PowerPAD Made Easy
PowerPAD™ Thermally Enhanced Package
Semiconductor and IC Package Thermal Metrics
AN-2020 Thermal Design By Insight, Not Hindsight
AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
TI User Guide, Simple Success with Conducted EMI for DC-DC Converters
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
MicroSiP, PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Product Folder Links: LMZM23600
29
ADVANCE INFORMATION
Constructing Your Power Supply – Layout Considerations
LMZM23600
SNVSB53 – FEBRUARY 2018
www.ti.com
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
ADVANCE INFORMATION
30
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Mar-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMZM23600SILR
PREVIEW
uSiP
SIL
10
3000
TBD
Call TI
Call TI
-40 to 125
TXN6300EC
4J
A
A 4J
LMZM23600SILT
PREVIEW
uSiP
SIL
10
250
TBD
Call TI
Call TI
-40 to 125
TXN6300EC
4J
A
A 4J
LMZM23600V3SILR
PREVIEW
uSiP
SIL
10
3000
TBD
Call TI
Call TI
-40 to 125
TXN6500EC
4L
A
A 4L
LMZM23600V3SILT
PREVIEW
uSiP
SIL
10
250
TBD
Call TI
Call TI
-40 to 125
TXN6500EC
4L
A
A 4L
LMZM23600V5SILR
PREVIEW
uSiP
SIL
10
3000
TBD
Call TI
Call TI
-40 to 125
TXN6400EC
4K
A
A 4K
LMZM23600V5SILT
PREVIEW
uSiP
SIL
10
250
TBD
Call TI
Call TI
-40 to 125
TXN6400EC
4K
A
A 4K
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
29-Mar-2018
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
SIL0010A
MicroSiP TM - 1.578 mm max height
SCALE 3.500
MICRO SYSTEM IN PACKAGE
3.9
3.7
B
A
PIN 1 ID
3.1
2.9
PICK AREA
NOTE 3
NOTE 4
TYP
1.578 MAX
C
0.08 C
SEATING PLANE
3.05 TYP
EXPOSED
THERMAL PAD
0.7 0.1
(0.05) TYP
11
5
6
6X 0.6
2.9 0.1
SYMM
2X
2.4
10X
10
1
PIN 1 ID
0.175
10X
PKG
0.4
0.2
0.1
0.05
C A B
C
0.75
0.55
4222635/C 01/2018
MicroSiP is a trademark of Texas Instruments
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Pick and place nozzle 1.1 mm or smaller recommended.
4. Location, size and quantity of components are for reference only and could vary.
5. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
SIL0010A
MicroSiP TM - 1.578 mm max height
MICRO SYSTEM IN PACKAGE
(0.7)
10X (0.65)
11
1
10
10X (0.3)
SYMM
(2.9)
8X (0.6)
(1.03)
6
5
( 0.2) VIA
TYP
(0.175)
PKG
(3.05)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PACKAGE SOLDER PADS
SOLDER MASK DEFINED
SCALE:20X
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
(R0.05) TYP
DETAIL
NOT TO SCALE
4222635/C 01/2018
NOTES: (continued)
6. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
7. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
SIL0010A
MicroSiP TM - 1.578 mm max height
MICRO SYSTEM IN PACKAGE
3X (0.7)
(R0.05) TYP
10X (0.65)
11
1
10X (0.3)
10
3X
(0.833)
SYMM
8X (0.6)
(1.03)
SOLDER MASK EDGE
5
6
EXPOSED
METAL
2X
(0.175)
PKG
(3.05)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PAD 11:
86% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4222635/C 01/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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