TI1 OPA2354AIDGKRG4 250-mhz, rail-to-rail i/o, cmos operational amplifier Datasheet

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OPA354, OPA2354, OPA4354
SBOS233F – MARCH 2002 – REVISED JUNE 2016
OPAx354 250-MHz, Rail-to-Rail I/O, CMOS Operational Amplifiers
1 Features
3 Description
•
•
•
•
•
•
•
The OPA354 series of high-speed, voltage-feedback
CMOS operational amplifiers are designed for video
and other applications requiring wide bandwidth.
They are unity-gain stable and can drive large output
currents. Differential gain is 0.02% and differential
phase is 0.09°. Quiescent current is only 4.9 mA per
channel.
1
•
•
•
•
•
Unity-Gain Bandwidth: 250 MHz
Wide Bandwidth: 100-MHz GBW
High Slew Rate: 150 V/µs
Low Noise: 6.5 nV√Hz
Rail-to-Rail I/O
High Output Current: > 100 mA
Excellent Video Performance:
– Diff Gain: 0.02%, Diff Phase: 0.09°
– 0.1-dB Gain Flatness: 40 MHz
Low Input Bias Current: 3 pA
Quiescent Current: 4.9 mA
Thermal Shutdown
Supply Range: 2.5 V to 5.5 V
MicroSIZE and PowerPAD™ Packages
The OPA354 series op amps are optimized for
operation on single or dual supplies as low as 2.5 V
(±1.25 V) and up to 5.5 V (±2.75 V). Common-mode
input range extends beyond the supplies. The output
swing is within 100 mV of the rails, supporting wide
dynamic range.
For applications requiring the full 100-mA continuous
output current, single and dual 8-pin HSOP
PowerPAD versions are available.
The single version (OPA354) is available in the tiny
5‑pin SOT-23 and 8-pin HSOP PowerPAD packages.
The dual version (OPA2354) comes in the miniature
8-pin VSSOP and 8-pin HSOP PowerPAD packages.
The quad version (OPA4354) is offered in 14-pin
TSSOP and 14-pin SOIC packages.
2 Applications
•
•
•
•
•
•
•
•
•
•
Video Processing
Ultrasound
Optical Networking, Tunable Lasers
Photodiode Transimpedance Amps
Active Filters
High-Speed Integrators
Analog-to-Digital (A/D) Converter Input Buffers
Digital-to-Analog (D/A) Converter Output
Amplifiers
Barcode Scanners
Communications
Multichannel version feature completely independent
circuitry for lowest crosstalk and freedom from
interaction. All are specified over the extended –40°C
to 125°C temperature range.
Device Information(1)
PART NUMBER
OPA354
OPA2354
OPA4354
PACKAGE
BODY SIZE (NOM)
HSOP (8)
4.89 mm × 3.90 mm
SOT-23 (5)
2.90 mm × 1.60 mm
VSSOP (8)
3.00 mm × 3.00 mm
HSOP (8)
4.89 mm × 3.90 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
V+
-In
OPA354
VOUT
+In
VCopyright © 2016,
Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA354, OPA2354, OPA4354
SBOS233F – MARCH 2002 – REVISED JUNE 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information: OPA354 .................................. 7
Thermal Information: OPA2354 ................................ 7
Thermal Information: OPA4354 ................................ 7
Electrical Characteristics: VS = 2.7 V to 5.5 V SingleSupply ........................................................................ 8
7.8 Typical Characteristics ............................................ 10
8
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 20
9
Application and Implementation ........................ 21
9.1 Application Information............................................ 21
9.2 Typical Application ................................................. 21
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 23
11.1
11.2
11.3
11.4
11.5
Layout Guidelines .................................................
Layout Example ....................................................
Power Dissipation .................................................
PowerPAD Thermally-Enhanced Package ...........
PowerPAD Assembly Process ..............................
23
23
23
24
24
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
Changes from Revision E (March 2002) to Revision F
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Deleted Package/Ordering Information table, see POA at the end of the data sheet............................................................ 1
•
Renamed OPAx354 Related Products table to Device Comparison Table ........................................................................... 3
2
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SBOS233F – MARCH 2002 – REVISED JUNE 2016
5 Device Comparison Table
FEATURES
PRODUCT
Shutdown Version of OPA354 Family
OPAx357
200-MHz GBW, Rail-to-Rail Output, CMOS, Shutdown
OPAx355
200-MHz GBW, Rail-to-Rail Output, CMOS
OPAx356
38-MHz GBW, Rail-to-Rail Input/Output, CMOS
OPAx350/OPAx353
75-MHz BW G = 2, Rail-to-Rail Output
OPA2631
150-MHz BW G = 2, Rail-to-Rail Output
OPA2634
100-MHz BW, Differential Input/Output, 3.3-V Supply
THS412x
6 Pin Configuration and Functions
OPA354: DBV Package
5-Pin SOT-23
Top View
Out
1
V-
2
+In
3
5
4
OPA354: DDA Package
8-Pin HSOP(2)
Top View
V+
-In
(1)
(1)
(1)
1
8
NC
-In
2
7
V+
+In
3
6
Out
V-
4
5
NC
NC
(1)
NC means no internal connection.
PowerPAD must be connected to V− or left
floating.
Pin Functions: OPA354
PIN
NAME
–In
SOT-23
HSOP
4
2
I/O
DESCRIPTION
I
Inverting input
Noninverting input
+In
3
3
I
NC
—
1, 5, 8
—
No internal connection (can be left floating)
Out
1
6
O
Output
V–
2
4
—
Negative (lowest) supply
V+
5
7
—
Positive (highest) supply
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OPA2354: DGK and DDA Packages
8-Pin VSSOP, HSOP(1)
Top View
Out A
1
-In A
2
8
V+
7
Out B
6
-In B
5
+In B
A
+In A
3
B
V-
(1)
4
PowerPAD must be connected to V− or left floating.
Pin Functions: OPA2354
PIN
I/O
DESCRIPTION
NAME
VSSOP
HSOP
–In A
2
2
I
Inverting input, channel A
+In A
3
3
I
Noninverting input, channel A
–In B
6
6
I
Inverting input, channel B
+In B
5
5
I
Noninverting input, channel B
Out A
1
1
O
Output, channel A
Out B
7
7
O
Output, channel B
V–
4
4
—
Negative (lowest) supply
V+
8
8
—
Positive (highest) supply
4
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SBOS233F – MARCH 2002 – REVISED JUNE 2016
OPA4354: D and PW Packages
14-Pin SOIC, TSSOP
Top View
Out A
1
14
Out D
-In A
2
13
-In D
+In A
3
12
+In D
V+
4
11
V-
+In B
5
10
+In C
A
B
D
C
-In B
6
9
-In C
Out B
7
8
Out C
Pin Functions: OPA4354
PIN
I/O
DESCRIPTION
NAME
SOIC
TSSOP
–In A
2
2
I
Inverting input, channel A
+In A
3
3
I
Noninverting input, channel A
–In B
6
6
I
Inverting input, channel B
+In B
5
5
I
Noninverting input, channel B
–In C
9
9
I
Inverting input, channel C
+In C
10
10
I
Noninverting input, channel C
–In D
13
13
I
Inverting input, channel D
+In D
12
12
I
Noninverting input, channel D
Out A
1
1
O
Output, channel A
Out B
7
7
O
Output, channel B
Out C
8
8
O
Output, channel C
Out D
14
14
O
Output, channel D
V–
11
11
—
Negative (lowest) supply
V+
4
4
—
Positive (highest) supply
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Product Folder Links: OPA354 OPA2354 OPA4354
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Voltage
Current
Signal input terminals (2)
(V−) − (0.5)
(V+) + 0.5
Signal input terminals (2)
–10
10
Operating, TA
(3)
V
mA
Continuous
–55
Junction, TJ
150
150
Storage, Tstg
(2)
UNIT
7.5
Output short circuit (3)
Temperature
(1)
MAX
Supply voltage, V+ to V−
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
6
MAX
UNIT
Supply voltage, V– to V+
2.5
5.5
V
Specified temperature
–40
125
°C
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SBOS233F – MARCH 2002 – REVISED JUNE 2016
7.4 Thermal Information: OPA354
OPA354
THERMAL METRIC (1)
DBV (SOT-23)
DDA (HSOP)
5 PINS
8 PINS
UNIT
42.5
°C/W
RθJA
Junction-to-ambient thermal resistance
216.3
RθJC(top)
Junction-to-case (top) thermal resistance
84.3
54
°C/W
RθJB
Junction-to-board thermal resistance
43.1
26.5
°C/W
ψJT
Junction-to-top characterization parameter
3.8
8
°C/W
ψJB
Junction-to-board characterization parameter
42.3
26.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
3.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Thermal Information: OPA2354
OPA2354
THERMAL METRIC
(1)
DDA (HSOP)
DGK (VSSOP)
8 PINS
8 PINS
UNIT
40.6
175.9
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
46
67.8
°C/W
RθJB
Junction-to-board thermal resistance
20.7
97.1
°C/W
ψJT
Junction-to-top characterization parameter
5.6
9.3
°C/W
ψJB
Junction-to-board characterization parameter
20.6
95.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.5
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Thermal Information: OPA4354
OPA4354
THERMAL METRIC
(1)
D (SOIC)
PW (TSSOP)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
83.8
92.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
70.7
27.5
°C/W
RθJB
Junction-to-board thermal resistance
59.5
33.6
°C/W
ψJT
Junction-to-top characterization parameter
11.6
1.9
°C/W
ψJB
Junction-to-board characterization parameter
37.7
33.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2002–2016, Texas Instruments Incorporated
Product Folder Links: OPA354 OPA2354 OPA4354
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7.7 Electrical Characteristics: VS = 2.7 V to 5.5 V Single-Supply
At TA = 25°C, RF = 0 Ω, RL = 1 kΩ, and connected to VS/2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VS = 5 V, at TA = 25°C
VOS
Input offset voltage
dVOS/dT
Input offset voltage vs temperature
±2
VS = 5 V, at TA = −40°C to 125°C
VS = 5 V, at TA = −40°C to 125°C
±4
VS = 2.7 V to 5.5 V,
VCM = (VS/2) − 0.55 V
PSRR
Input offset voltage vs power supply
±8
±10
±200
mV
µV/°C
±800
µV/V
VS = 2.7 V to 5.5 V,
VCM = (VS/2) − 0.55 V,
at TA = −40°C to 125°C
±900
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
3
±50
pA
±1
±50
pA
NOISE
en
Input voltage noise density
f = 1 MHz
6.5
nV/√Hz
in
Current noise density
f = 1 MHz
50
fA/√Hz
INPUT VOLTAGE RANGE
VCM
CMRR
(V−) − 0.1
Common-mode voltage
Common-mode rejection ratio
VS = 5.5 V, –0.1 V < VCM < 3.5 V,
at TA = 25°C
66
VS = 5.5 V, –0.1 V < VCM < 3.5 V,
at TA = −40°C to 125°C
64
VS = 5.5 V, –0.1 V < VCM < 5.6 V,
at TA = 25°C
56
VS = 5.5 V, –0.1 V < VCM < 5.6 V,
at TA = −40°C to 125°C
55
(V+) + 0.1
V
80
dB
68
INPUT IMPEDANCE
Differential
1013 || 2
Ω || pF
Common-mode
1013 || 2
Ω || pF
OPEN-LOOP GAIN
AOL
Open-loop gain
VS = 5.5 V, 0.3 V < VO < 4.7 V,
at TA = 25°C
94
VS = 5 V, 0.4 V < VO < 4.6 V,
at TA = −40°C to 125°C
90
110
dB
FREQUENCY RESPONSE
f−3dB
Small-signal bandwidth
At G = +1, VO = 100 mVPP,
RF = 25 Ω
250
At G = +2, VO = 100 mVPP
90
MHz
GBW
Gain-bandwidth product
G = +10
100
MHz
f0.1dB
Bandwidth for 0.1-dB gain flatness
At G = +2, VO = 100 mVPP
40
MHz
VS = 5 V, G = +1, 4-V step
150
SR
Slew rate
VS = 5 V, G = +1, 2-V step
130
VS = 3 V, G = +1, 2-V step
110
At G = +1, VO = 200 mVPP,
10% to 90%
2
Rise-and-fall time
Settling time
Overload recovery time
8
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At G = +1, VO = 2 VPP, 10% to 90%
11
0.1%, VS = 5 V, G = +1,
2-V output step
30
0.01%, VS = 5 V, G = +1,
2-V output step
60
V/µs
ns
ns
VIN × Gain = VS
5
ns
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Electrical Characteristics: VS = 2.7 V to 5.5 V Single-Supply (continued)
At TA = 25°C, RF = 0 Ω, RL = 1 kΩ, and connected to VS/2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE, continued
Harmonic distortion
Second
harmonic
At G = +1, f = 1 MHz, VO = 2 VPP,
RL = 200 Ω, VCM = 1.5 V
–75
Third harmonic
At G = +1, f = 1 MHz, VO = 2 VPP,
RL = 200 Ω, VCM = 1.5 V
–83
dBc
Differential gain error
NTSC, RL = 150 Ω
0.02%
Differential phase error
NTSC, RL = 150 Ω
0.09
f = 5 MHz
–100
Channel-to-channel
crosstalk
OPA2354
OPA4354
°
dB
–84
OUTPUT
VS = 5 V, RL = 1 kΩ, AOL > 94 dB,
at TA = 25°C
Voltage output swing from rail
IO
0.1
V
VS = 5 V, RL = 1 kΩ, AOL > 90 dB,
at TA = −40°C to 125°C
Output current, single, dual, quad (1) (2)
VS = 5 V
0.4
100
VS = 3 V
Closed-loop output impedance
RO
0.3
mA
50
f < 100 kHz
Open-loop output resistance
mA
0.05
Ω
35
Ω
POWER SUPPLY
VS
IQ
Specified voltage
2.7
5
Operating voltage
2.5
5.5
Quiescent current (per amplifier)
At TA = 25°C, VS = 5 V, enabled,
IO = 0
4.9
At TA = –40°C to 125°C
6
V
mA
7.5
THERMAL SHUTDOWN – JUNCTION TEMPERATURE
Shutdown
160
°C
Reset from shutdown
140
°C
THERMAL RANGE
(1)
(2)
Specified
–40
125
°C
Operating
–55
150
°C
Storage
–65
150
°C
See typical characteristic curves, Output Voltage Swing vs Output Current (Figure 20 and Figure 22).
Specified by design.
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7.8 Typical Characteristics
At TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS/2, unless otherwise noted.
3
VO = 0.1VPP, RF = 604W
0
Normalized Gain (dB)
0
Normalized Gain (dB)
3
G = +1
RF = 25W
VO = 0.1VPP
G = +2, RF = 604W
-3
G = +5, RF = 604W
-6
G = +10, RF = 604W
-9
-12
-3
G = -1
-6
G = -5
G = -10
-12
-15
100k
1M
10M
Frequency (Hz)
100M
-15
100k
1G
1M
100M
1G
Figure 2. Inverting Small-Signal Frequency Response
Output Voltage (40mV/div)
Time (20ns/div)
Time (20ns/div)
Figure 3. Noninverting Small-Signal Step Response
0.5
0.4
Figure 4. Noninverting Large-Signal Step Response
-50
VO = 0.1VPP
Harmonic Distortion (dBc)
0.3
Normalized Gain (dB)
10M
Frequency (Hz)
Output Voltage (500mV/div)
Figure 1. Noninverting Small-Signal Frequency Response
G = +1
RF = 25W
0.2
0.1
0
-0.1
-0.2
G = +2
RF = 604W
-0.3
G = -1
f = 1MHz
RL = 200W
-60
-70
2nd Harmonic
-80
-90
-0.4
-0.5
100k
3rd Harmonic
-100
1M
10M
Frequency (Hz)
100M
Figure 5. 0.1-dB Gain Flatness
10
G = -2
-9
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1G
0
1
2
Output Voltage (VPP)
3
4
Figure 6. Harmonic Distortion vs Output Voltage
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Typical Characteristics (continued)
At TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS/2, unless otherwise noted.
-50
-50
Harmonic Distortion (dBc)
-60
-70
2nd Harmonic
-80
-90
VO = 2VPP
f = 1MHz
RL = 200W
-60
Harmonic Distortion (dBc)
VO = 2VPP
f = 1MHz
RL = 200W
-70
2nd Harmonic
-80
3rd Harmonic
-90
3rd Harmonic
-100
-100
1
10
1
10
Gain (V/V)
Gain (V/V)
Figure 7. Harmonic Distortion vs Noninverting Gain
-60
Figure 8. Harmonic Distortion vs Inverting Gain
-50
G = +1
VO = 2VPP
RL = 200W
VCM = 1.5V
-70
2nd Harmonic
-80
3rd Harmonic
-90
G = +1
VO = 2VPP
f = 1MHz
VCM = 1.5V
-60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-50
-70
2nd Harmonic
-80
3rd Harmonic
-90
-100
-100
100k
1M
Frequency (Hz)
100
10M
1k
RL (W)
Figure 9. Harmonic Distortion vs Frequency
Figure 10. Harmonic Distortion vs Load Resistance
3
10k
RL = 10kW
1k
Voltage Noise
Normalized Gain (dB)
Voltage Noise (nV/ÖHz),
Current Noise (fA/ÖHz)
0
Current Noise
100
10
-3
-6
G = +1
R F = 0W
VO = 0.1VPP
CL = 0pF
RL = 1kW
RL = 100W
-9
RL = 50W
-12
1
10
100
1k
10k
100k
1M
10M
100M
-15
100k
1M
Frequency (Hz)
Figure 11. Input Voltage and Current Noise
Spectral Density vs Frequency
10M
Frequency (Hz)
100M
1G
Figure 12. Frequency Response for Various RL
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Typical Characteristics (continued)
At TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS/2, unless otherwise noted.
160
9
G = +1
VO = 0.1VPP
RS = 0W
6
Normalized Gain (dB)
3
120
100
-3
RS (W)
0
CL = 47pF
80
-6
60
-9
40
VIN
1kW
0
1M
10M
Frequency (Hz)
100M
1
1G
Figure 13. Frequency Response for Various CL
1k
10
100
Capacitive Load (pF)
Figure 14. Recommended RS vs Capacitive Load
100
3
G = +1,
VO = 0.1VPP
0
CL = 5.6pF, RS = 0W
CMRR
80
CL = 47pF, RS = 140W
-3
CMRR, PSRR (dB)
Normalized Gain (dB)
VO
CL
20
-15
100k
CL = 100pF, RS = 120W
-6
-9
VIN
RS
VO
OPA354
CL
-12
PSRR+
60
PSRR40
20
1kW
0
-15
100k
1M
10M
Frequency (Hz)
1G
100M
10k
Figure 15. Frequency Response vs Capacitive Load
100k
1M
10M
Frequency (Hz)
100M
1G
Figure 16. Common-Mode Rejection Ratio and
Power-Supply Rejection Ratio vs Frequency
180
0.8
160
0.7
120
dG/dP (%/degrees)
140
Phase
100
80
60
40
Gain
20
0.6
0.5
dP
0.4
0.3
0.2
0
0.1
dG
-20
0
-40
10
100
1k
10k 100k
1M
Frequency (Hz)
10M
100M
Figure 17. Open-Loop Gain and Phase
12
RS
OPA354
CL = 5.6pF
-12
Open-Loop Phase (degrees)
Open-Loop Gain (dB)
For 0.1dB
Flatness
140
CL = 100pF
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1G
1
2
3
Number of 150W Loads
4
Figure 18. Composite Video Differential Gain and Phase
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Typical Characteristics (continued)
At TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS/2, unless otherwise noted.
3
1k
Output Voltage (V)
Input Bias Current (pA)
10k
100
10
1
2
+125°C
+25°C
-55°C
1
0
-55
-35
-15
5
25
45
65
Temperature (°C)
85
105 125 135
0
Figure 19. Input Bias Current vs Temperature
20
40
60
80
Output Current (mA)
100
120
Figure 20. Output Voltage Swing vs Output Current for
VS = 3 V
5
7
4
VS = 5V
5
Output Voltage (V)
Supply Current (mA)
6
4
VS = 2.5V
3
2
3
+125°C
+25°C
-55°C
2
1
1
0
0
-55
-35
-15
5
25
45
65
Temperature (°C)
85
0
105 125 135
Figure 21. Supply Current vs Temperature
25
50
75
100
125
Output Current (mA)
150
175
200
Figure 22. Output Voltage Swing vs Output Current for
VS = 5 V
6
100
VS = 5.5V
10
Output Voltage (VPP)
Output Impedance (W)
5
1
0.1
Maximum Output
Voltage without
Slew RateInduced Distortion
4
3
VS = 2.7V
2
OPA354
1
ZO
0.01
100k
0
1M
10M
Frequency (Hz)
100M
1G
Figure 23. Closed-Loop Output Impedance vs Frequency
1
10
Frequency (MHz)
100
Figure 24. Maximum Output Voltage vs Frequency
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Typical Characteristics (continued)
At TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS/2, unless otherwise noted.
120
0.5
0.4
110
Open-Loop Gain (dB)
Output Error (%)
RL = 1kW
VO = 2VPP
0.3
0.2
0.1
0
-0.1
-0.2
100
90
80
-0.3
-0.4
70
-0.5
0
10
20
30
40
50
60
Time (ns)
70
80
90
100
-55
Figure 25. Output Settling Time to 0.1%
-35
5
-15
25
45
65
Temperature (°C)
85
105 125 135
Figure 26. Open-Loop Gain vs Temperature
100
Population
CMRR, PSRR (dB)
90
Common-Mode Rejection Ratio
80
Power-Supply Rejection Ratio
70
60
50
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3
Offset Voltage (mV)
4 5 6
7 8
-55
Figure 27. Offset Voltage Production Distribution
-35
-15
5
25
45
65
Temperature (°C)
85
105 125 135
Figure 28. Common-Mode Rejection Ratio and
Power-Supply Rejection Ratio vs Temperature
Crosstalk, Input-Referred (dB)
0
-20
-40
OPA4354
-60
OPA2354
-80
-100
-120
100k
1M
10M
100M
1G
Frequency (Hz)
Figure 29. Channel-to-Channel Crosstalk
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8 Detailed Description
8.1 Overview
The OPA354 is a CMOS, rail-to-rail I/O, high-speed, voltage-feedback operational amplifier designed for video,
high-speed, and other applications. It is available as a single, dual, or quad op amp.
The amplifier features a 100-MHz gain bandwidth, and 150-V/µs slew rate, but it is unity-gain stable and can be
operated as a +1-V/V voltage follower.
8.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINVBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V(Ground)
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8.3 Feature Description
8.3.1 Operating Voltage
The OPA354 is specified over a power-supply range of 2.7 V to 5.5 V (±1.35 V to ±2.75 V). However, the supply
voltage may range from 2.5 V to 5.5 V (±1.25 V to ±2.75 V). Supply voltages higher than 7.5 V (absolute
maximum) can permanently damage the amplifier.
Parameters that vary over supply voltage or temperature are shown in Typical Characteristics of this data sheet.
8.3.2 Rail-to-Rail Input
The specified input common-mode voltage range of the OPA354 extends 100 mV beyond the supply rails. This
extended range is achieved with a complementary input stage—an N-channel input differential pair in parallel
with a P-channel differential pair, as shown in the Functional Block Diagram. The N-channel pair is active for
input voltages close to the positive rail, typically (V+) − 1.2 V to 100 mV above the positive supply, while the Pchannel pair is on for inputs from 100 mV below the negative supply to approximately (V+) − 1.2 V. There is a
small transition region, typically (V+) − 1.5 V to (V+) − 0.9 V, in which both pairs are on. This 600-mV transition
region can vary ±500 mV with process variation. Thus, the transition region (both input stages on) can range
from (V+) − 2 V to (V+) − 1.5 V on the low end, up to (V+) − 0.9 V to (V+) − 0.4 V on the high end.
A double-folded cascode adds the signal from the two input pairs and presents a differential signal to the class
AB output stage.
8.3.3 Rail-to-Rail Output
A class AB output stage with common-source transistors is used to achieve rail-to-rail output. For highimpedance loads (> 200 Ω), the output voltage swing is typically 100 mV from the supply rails. With 10-Ω loads,
a useful output swing can be achieved while maintaining high open-loop gain. See the typical characteristic
curves, Output Voltage Swing vs Output Current (Figure 20 and Figure 22).
8.3.4 Output Drive
The OPA354 output stage can supply a continuous output current of ±100 mA and yet provide approximately
2.7 V of output swing on a 5-V supply, as shown in Figure 30. For maximum reliability, TI does not recommend
running a continuous DC current in excess of ±100 mA. Refer to the typical characteristic curves, Output Voltage
Swing vs Output Current (Figure 20 and Figure 22). For supplying continuous output currents greater than ±100
mA, the OPA354 may be operated in parallel, as shown in Figure 31.
R2
1kW
+
-
C1
50pF
V1
5V
1mF
R1
10kW
V+
OPA354
+
R3
VIN 10kW
V-
-
1V In = 100mA
Out, as Shown
R4
1kW
RSHUNT
1W
Laser Diode
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Figure 30. Laser Diode Driver
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Feature Description (continued)
The OPA354 provides peak currents up to 200 mA, which corresponds to the typical short-circuit current.
Therefore, an on-chip thermal shutdown circuit is provided to protect the OPA354 from dangerously high junction
temperatures. At 160°C, the protection circuit shuts down the amplifier. Normal operation resumes when the
junction temperature cools to below 140°C.
R2
10kW
C1
200pF
+5V
1mF
R1
100kW
R5
1W
OPA2354
R3
100kW
+
-
R6
1W
2V In = 200mA
Out, as Shown
RSHUNT
1W
OPA2354
R4
10kW
Laser Diode
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Figure 31. Parallel Operation
8.3.5 Video
The OPA354 output stage is capable of driving standard back-terminated 75-Ω video cables, as shown in
Figure 32. By back-terminating a transmission line, it does not exhibit a capacitive load to its driver. A properly
back-terminated 75-Ω cable does not appear as capacitance; it presents only a 150-Ω resistive load to the
OPA354 output.
+5V
Video
In
75W
75W
OPA354
Video
Output
+2.5V
604W
604W
+2.5V
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Figure 32. Single-Supply Video Line Driver
The OPA354 can be used as an amplifier for RGB graphic signals, which have a voltage of zero at the video
black level, by offsetting and AC-coupling the signal. See Figure 33.
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Feature Description (continued)
604W
+3V
+
V+
Red
10nF
604W
75W
1/2
OPA2354
R1
(1)
1mF
Red
75W
R2
V+
Green
R1
(1)
R2
604W
75W
1/2
OPA2354
Green
75W
604W
604W
+3V
+
V+
Blue
(1)
1 mF
10nF
604W
R1
75W
Blue
OPA354
75W
R2
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(1)
Source video signal offset 300 mV above ground to accommodate op amp swing−to−ground capability.
Figure 33. RGB Cable Driver
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Feature Description (continued)
8.3.6 Driving Analog-to-Digital converters
The OPA354 series op amps offer 60 ns of settling time to 0.01%, making them a good choice for driving highand medium-speed sampling A/D converters and reference circuits. The OPA354 series provide an effective
means of buffering the A/D converter input capacitance and resulting charge injection while providing signal gain.
For applications requiring high DC accuracy, the OPA350 series is recommended.
Figure 34 illustrates the OPA354 driving an A/D converter. With the OPA354 in an inverting configuration, a
capacitor across the feedback resistor can be used to filter high-frequency noise in the signal.
+5V
330pF
5kW
5kW
VIN
VREF
V+
ADS7816, ADS7861,
or ADS7864
12-Bit A/D Converter
+In
OPA354
+2.5V
-In
GND
VIN = 0V to -5V for 0V to 5V output.
NOTE: A/D converter input = 0V to VREF
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Figure 34. The OPA354 in Inverting Configuration Driving the ADS7816
8.3.7 Capacitive Load and Stability
The OPA354 series op amps can drive a wide range of capacitive loads. However, all op amps under certain
conditions may become unstable. Op amp configuration, gain, and load value are just a few of the factors to
consider when determining stability. An op amp in unity-gain configuration is most susceptible to the effects of
capacitive loading. The capacitive load reacts with the device output resistance, along with any additional load
resistance, to create a pole in the small-signal response that degrades the phase margin. Refer to the typical
characteristic curve, Frequency Response for Various CL (Figure 13) for details.
The OPA354 topology enhances its ability to drive capacitive loads. In unity gain, these op amps perform well
with large capacitive loads. Refer to the typical characteristic curves, Recommended RS vs Capacitive Load
(Figure 14) and Frequency Response vs Capacitive Load (Figure 15) for details.
One method of improving capacitive load drive in the unity-gain configuration is to insert a 10-Ω to 20-Ω resistor
in series with the output, as shown in Figure 35. This configuration significantly reduces ringing with large
capacitive loads—see the typical characteristic curve, Frequency Response vs Capacitive Load (Figure 15).
However, if there is a resistive load in parallel with the capacitive load, RS creates a voltage divider. This voltage
division introduces a DC error at the output and slightly reduces output swing. This error may be insignificant. For
instance, with RL = 10 kΩ and RS = 20 Ω, there is approximately a 0.2% error at the output.
V+
RS
VOUT
OPA354
VIN
RL
CL
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Figure 35. Series Resistor in Unity-Gain Configuration Improves Capacitive Load Drive
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Feature Description (continued)
8.3.8 Wideband Transimpedance Amplifier
Wide bandwidth, low input bias current, low input voltage, and current noise make the OPA354 an ideal
wideband photodiode transimpedance amplifier for low-voltage single-supply applications. Low-voltage noise is
important because photodiode capacitance causes the effective noise gain of the circuit to increase at high
frequency.
The key elements to a transimpedance design, as shown in Figure 36, are the expected diode capacitance
[including the parasitic input common-mode and differential-mode input capacitance (2 + 2) pF for the OPA354],
the desired transimpedance gain (RF), and the Gain-Bandwidth Product (GBW) for the OPA354 (100 MHz
typical). With these three variables set, the feedback capacitor value (CF) may be set to control the frequency
response.
CF
< 1pF
(prevents gain peaking)
RF
10MW
+V
l
CD OPA354
VOUT
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Figure 36. Transimpedance Amplifier
To achieve a maximally flat, second-order, Butterworth frequency response, the feedback pole must be set as
shown in Equation 1:
1 =
2pRFCF
GBP
4pRFCD
(1)
Typical surface-mount resistors have a parasitic capacitance of approximately 0.2 pF that must be deducted from
the calculated feedback capacitance value. Bandwidth is calculated by Equation 2:
f-3dB =
GBP Hz
2pRFCD
(2)
For even higher transimpedance bandwidth, the high-speed CMOS OPA355 (200-MHz GBW) or the OPA655
(400-MHz GBW) may be used.
8.4 Device Functional Modes
The OPAx354 family of devices is powered on when the supply is connected. The devices can be operated as
single-supply operational amplifiers or dual-supply amplifiers depending on the application. The devices can also
be used with asymmetrical supplies as long as the differential voltage (V– to V+) is at least 1.8 V and no greater
than 5.5 V (example: V– set to –3.5 V and V+ set to 1.5 V).
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The OPAx354 family of devices is a CMOS, rail-to-rail I/O, high-speed, voltage-feedback operational amplifier
designed for video, high-speed, and other applications. The OPAx354 family of devices is available as a single,
dual, or quad op amp. The amplifier features a 100-MHz gain bandwidth, and 150-V/µs slew rate, but it is unitygain stable and can be operated as a 1-V/V voltage follower.
9.2 Typical Application
Wide gain bandwidth, low input bias current, low input voltage, and current noise make the OPAx354 family of
devices an ideal wideband photodiode transimpedance amplifier. Low-voltage noise is important because
photodiode capacitance causes the effective noise gain of the circuit to increase at high frequency. The key
elements to a transimpedance design, as shown in Figure 37, are the expected diode capacitance, which include
the parasitic input common-mode and differential-mode input capacitance; the desired transimpedance gain; and
the gain-bandwidth (GBW) for the OPAx354 family of devices (20 MHz). With these three variables set, the
feedback capacitor value can be set to control the frequency response. Feedback capacitance includes the stray
capacitance of, which is 0.2 pF for a typical surface-mount resistor.
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Figure 37. Dual-Supply Transimpedance Amplifier
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
PARAMETER
EXAMPLE VALUE
Supply voltage, V(V+)
2.5 V
Supply voltage, V(V-)
–2.5 V
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C(F) is optional to prevent gain peaking. C(F) includes the stray capacitance of R(F).
9.2.2 Detailed Design Procedure
To achieve a maximally-flat, second-order Butterworth frequency response, set the feedback pole using
Equation 3.
(3)
Calculate the bandwidth using Equation 4.
(4)
9.2.2.1 Optimizing the Transimpedance Circuit
To achieve the best performance, components must be selected according to the following guidelines:
1. For lowest noise, select R(F) to create the total required gain. Using a lower value for R(F) and adding gain after
the transimpedance amplifier generally produces poorer noise performance. The noise produced by R(F)
increases with the square-root of R(F), whereas the signal increases linearly. Therefore, signal-to-noise ratio
improves when all the required gain is placed in the transimpedance stage.
2. Minimize photodiode capacitance and stray capacitance at the summing junction (inverting input). This
capacitance causes the voltage noise of the op amp to be amplified (increasing amplification at high frequency).
Using a low-noise voltage source to reverse-bias a photodiode can significantly reduce the capacitance. Smaller
photodiodes have lower capacitance. Use optics to concentrate light on a small photodiode.
3. Noise increases with increased bandwidth. Limit the circuit bandwidth to only that required. Use a capacitor
across the R(F) to limit bandwidth, even if not required for stability.
4. Circuit board leakage can degrade the performance of an otherwise well-designed amplifier. Clean the circuit
board carefully. A circuit board guard trace that encircles the summing junction and is driven at the same voltage
can help control leakage.
9.2.3 Application Curve
Figure 38. AC Transfer Function
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10 Power Supply Recommendations
The OPAx354 family of devices is specified for operation from 2.5 V to 5.5 V (±1.25 to ±2.75 V); many
specifications apply from –40°C to 125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are shown Typical Characteristics.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, see Layout
Guidelines.
11 Layout
11.1 Layout Guidelines
Good high-frequency printed-circuit board (PCB) layout techniques must be employed for the OPA354. Generous
use of ground planes, short and direct signal traces, and a suitable bypass capacitor located at the V+ pin assure
clean, stable operation. Large areas of copper also provides a means of dissipating heat that is generated in
normal operation.
TI does not recommend using sockets with any high-speed amplifier.
A 10-nF ceramic bypass capacitor is the minimum recommended value; adding a 1-µF or larger tantalum
capacitor in parallel can be beneficial when driving a low-resistance load. Providing adequate bypass
capacitance is essential to achieving very low harmonic and intermodulation distortion.
11.2 Layout Example
Figure 39. Operational Amplifier Board Layout for Noninverting Configuration
11.3 Power Dissipation
Power dissipation depends on power-supply voltage, signal and load conditions. With DC signals, power
dissipation is equal to the product of output current times the voltage across the conducting output transistor,
VS − VO. Power dissipation can be minimized by using the lowest possible power-supply voltage necessary to
assure the required output voltage swing.
For resistive loads, the maximum power dissipation occurs at a DC output voltage of one-half the power-supply
voltage. Dissipation with AC signals is lower. AB-039 Power Amplifier Stress and Power Handling Limitations
explains how to calculate or measure power dissipation with unusual signals and loads, and can be found at
www.ti.com.
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Power Dissipation (continued)
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature must be limited to 150°C, maximum. To estimate the
margin of safety in a complete design, increase the ambient temperature until the thermal protection is triggered
at 160°C. The thermal protection should trigger more than 35°C above the maximum expected ambient condition
of the application.
11.4 PowerPAD Thermally-Enhanced Package
In addition to the regular 5-pin SOT-23 and 9-pin VSSOP packages, the single and dual versions of the OPA354
also come in an 8-pin SOIC PowerPAD package. The 98-pin SO with PowerPAD is a standard size 8-pin SOIC
package where the exposed leadframe on the bottom of the package can be soldered directly to the PCB to
create an extremely low thermal resistance. This direct attachment enhances the OPA354 power dissipation
capability significantly, and eliminates the use of bulky heatsinks and slugs traditionally used in thermal
packages. This package can be easily mounted using standard PCB assembly techniques.
NOTE
Because the 8-pin HSOP PowerPAD is pin-compatible with standard 8-pin SOIC
packages, the OPA354 and OPA2354 can directly replace operational amplifiers in
existing sockets. Soldering the PowerPAD to the PCB is always required, even with
applications that have low power dissipation. This configuration provides the necessary
thermal and mechanical connection between the leadframe die pad and the PCB.
The PowerPAD package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of
the IC, as shown in Figure 40. This exposed die provides an extremely low thermal resistance (RθJC) path
between the die and the exterior of the package. The thermal pad on the bottom of the IC can then be soldered
directly to the PCB, using the PCB as a heatsink. In addition, plated-through holes (vias) provide a low thermal
resistance heat flow path to the back side of the PCB.
Leadframe (Copper Alloy)
IC (Silicon)
Mold Compound (Plastic)
Die Attach (Epoxy)
Leadframe Die Pad
Exposed at Base of the Package
(Copper Alloy)
Figure 40. Section View of a PowerPAD Package
11.5 PowerPAD Assembly Process
The PowerPAD must be connected to the most negative supply voltage for the device, which is ground in singlesupply applications and V− in split-supply applications.
Prepare the PCB with a top-side etch pattern, as shown in Figure 41. The exact land design may vary based on
the specific assembly process requirements. There must be etch for the leads as well as etch for the thermal
land.
Place the recommended number of plated-through holes (or thermal vias) in the area of the thermal pad. These
holes must be 13 mils (.013 in) in diameter. They are kept small so that solder wicking through the holes is not a
problem during reflow. TI recommends a minimum of 5 holes for the 8-pin HSOP PowerPAD package, as shown
in Figure 41.
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Product Folder Links: OPA354 OPA2354 OPA4354
OPA354, OPA2354, OPA4354
www.ti.com
SBOS233F – MARCH 2002 – REVISED JUNE 2016
PowerPAD Assembly Process (continued)
Thermal Land
(Copper)
Minimum Size
4.8mm x 3.8mm
(189 mils x 150 mils)
OPTIONAL:
Additional 4 vias outside
of thermal pad area but
under the package.
REQUIRED:
Thermal pad area 2.286mm x 2.286mm
(90 mils x 90 mils) with 5 vias
(via diameter = 13 mils)
Figure 41. 8-Pin PowerPAD PCB Etch and Via Pattern
TI recommends, but does not require, placing a small number of additional holes under the package and outside
the thermal pad area. These holes provide additional heat paths between the copper thermal land and the
ground plane. They may be larger because they are not in the area to be soldered, so wicking is not a problem.
This technique is illustrated in Figure 41.
Connect all holes, including those within the thermal pad area and outside the pad area, to the internal ground
plane or other internal copper plane for single-supply applications, and to V− for split-supply applications.
When laying out these holes, do not use the typical web or spoke via connection methodology, as shown in
Figure 42. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer
during soldering operations. This feature makes soldering the vias that have ground plane connections easier.
However, in this application, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the PowerPAD package must make connection to the internal ground plane with a complete
connection around the entire circumference of the plated-through hole.
Solid Via
RECOMMENDED
Web or Spoke Via
NOT RECOMMENDED
(due to poor heat conduction)
Figure 42. Via Connection
The top-side solder mask must leave the pad connections and the thermal pad area exposed. The thermal pad
area must leave the 13-mil holes exposed. The larger holes outside the thermal pad area may be covered with
solder mask.
Apply solder paste to the exposed thermal pad area and all of the package terminals.
With these preparatory steps in place, the PowerPAD IC is simply placed in position and run through the solder
reflow operation as any standard surface-mount component. This preparation and processing results in a part
that is properly installed.
For detailed information on the PowerPAD package including thermal modeling considerations and repair
procedures, please see PowerPAD Thermally Enhanced Package located at www.ti.com.
Copyright © 2002–2016, Texas Instruments Incorporated
Product Folder Links: OPA354 OPA2354 OPA4354
Submit Documentation Feedback
25
OPA354, OPA2354, OPA4354
SBOS233F – MARCH 2002 – REVISED JUNE 2016
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
For related documentation see the following:
• ADS8326 16-Bit, High-Speed, 2.7V to 5.5V microPower Sampling ANALOG-TO-DIGITAL CONVERTER
(SBAS343)
• Circuit Board Layout Techniques (SLOA089)
• Compensate Transimpedance Amplifiers Intuitively (SBOA055)
• FilterPro™ User's Guide (SBFA001)
• Noise Analysis for High-Speed Op Amps
• OPA380 and OPA2380 Precision, High-Speed Transimpedance Amplifier (SBOS291)
• OPA355, OPA2355, and OPA3355 200MHz, CMOS OPERATIONAL AMPLIFIER WITH SHUTDOWN
(SBOS195)
• OPA656 Wideband, Unity-Gain Stable, FET-Input OPERATIONAL AMPLIFIER (SBOS196)
• POWER AMPLIFIER STRESS AND POWER HANDLING LIMITATIONS (SBOA022)
• PowerPAD Thermally Enhanced Package (SLMA002)
12.2 Related Links
Table 2 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA354
Click here
Click here
Click here
Click here
Click here
OPA2354
Click here
Click here
Click here
Click here
Click here
OPA4354
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
26
Submit Documentation Feedback
Copyright © 2002–2016, Texas Instruments Incorporated
Product Folder Links: OPA354 OPA2354 OPA4354
OPA354, OPA2354, OPA4354
www.ti.com
SBOS233F – MARCH 2002 – REVISED JUNE 2016
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2002–2016, Texas Instruments Incorporated
Product Folder Links: OPA354 OPA2354 OPA4354
Submit Documentation Feedback
27
PACKAGE OPTION ADDENDUM
www.ti.com
2-Feb-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2354AIDDA
ACTIVE SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
OPA
2354A
OPA2354AIDDAG3
ACTIVE SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
OPA
2354A
OPA2354AIDDAR
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
OPA
2354A
OPA2354AIDDARG3
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
OPA
2354A
OPA2354AIDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
OACI
OPA2354AIDGKRG4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
OACI
OPA2354AIDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
OACI
OPA2354AIDGKTG4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
OACI
OPA354AIDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OABI
OPA354AIDBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OABI
OPA354AIDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OABI
OPA354AIDBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OABI
OPA354AIDDA
ACTIVE SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
OPA
354A
OPA354AIDDAG3
ACTIVE SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
OPA
354A
OPA354AIDDAR
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
OPA
354A
OPA4354AID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4354A
OPA4354AIDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4354A
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
2-Feb-2016
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA4354AIDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4354A
OPA4354AIDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4354A
OPA4354AIPWR
ACTIVE
TSSOP
PW
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
4354A
OPA4354AIPWRG4
ACTIVE
TSSOP
PW
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
4354A
OPA4354AIPWT
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
4354A
OPA4354AIPWTG4
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
4354A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Feb-2016
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA4354 :
• Automotive: OPA4354-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Feb-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA2354AIDDAR
SO
Power
PAD
DDA
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA2354AIDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2354AIDGKT
VSSOP
DGK
8
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA354AIDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
OPA354AIDBVT
SOT-23
DBV
5
250
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
OPA354AIDDAR
SO
Power
PAD
DDA
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA4354AIDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
OPA4354AIPWR
TSSOP
PW
14
2500
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
OPA4354AIPWT
TSSOP
PW
14
250
180.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Feb-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2354AIDDAR
OPA2354AIDGKR
SO PowerPAD
DDA
8
2500
367.0
367.0
35.0
VSSOP
DGK
8
2500
366.0
364.0
50.0
OPA2354AIDGKT
VSSOP
DGK
8
250
366.0
364.0
50.0
OPA354AIDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
OPA354AIDBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
OPA354AIDDAR
SO PowerPAD
DDA
8
2500
367.0
367.0
35.0
OPA4354AIDR
SOIC
D
14
2500
367.0
367.0
38.0
OPA4354AIPWR
TSSOP
PW
14
2500
367.0
367.0
35.0
OPA4354AIPWT
TSSOP
PW
14
250
210.0
185.0
35.0
Pack Materials-Page 2
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