TI1 LMK05028 Low-jitter dual channel clock synchronizer with eight outputs and integrated eeprom Datasheet

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LMK05028
SNAS724 – FEBRUARY 2018
LMK05028 Low-Jitter Dual Channel Clock Synchronizer With Eight Outputs and Integrated
EEPROM
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
Two Independent PLL Cores, Each Featuring:
– Jitter: 150-fs RMS for Outputs ≥ 100 MHz
– Phase Noise: –102 dBc/Hz at 100-Hz Offset
for 122.88 MHz
– Hitless Switching: 50-ps Phase Transient With
Phase Cancellation
– Programmable Loop Bandwidth With Fastlock
– Standards-Compliant Synchronization and
Holdover Using a Low-Cost TCXO/OCXO
– Any Input to Any Output Frequency Translation
Four Reference Clock Inputs
– Priority-Based Input Selection (Auto or
Manual)
– Digital Holdover on Loss of Reference
Eight Clock Outputs With Programmable Drivers
– Up to Six Different Output Frequencies
– AC-LVDS, AC-CML, AC-LVPECL, HCSL, and
1.8-V or 2.5-V LVCMOS Output Formats
EEPROM/ROM for Custom Startup Clock
Profiles(2)
Flexible Configuration Options
– 1 Hz (1 PPS) to 750 MHz on Input and Output
– XO: 10 to 100 MHz, TCXO: 10 to 54 MHz
– DCO Mode: < 1 ppt/Step for Fine Frequency
and Phase Steering (IEEE 1588 Slave
Operation)
– Zero Delay for Deterministic Phase Offset
– Robust Clock Monitoring and Status
– I2C or SPI Interface
Excellent Power Supply Noise Rejection
Supply: 3.3-V Core With 1.8-V, 2.5-V, or 3.3-V
Output
Industrial Temperature Range: –40°C to +85°C
SyncE (G.8262), SONET/SDH (Stratum 3/3E,
G.813, GR-1244, GR-253), IEEE 1588 (PTP)
Slave Clock, or Optical Transport Network (G.709)
Synchronization
Telecom and Enterprise Line Cards
Wireless Base Station (BTS)
Test and Measurement, Broadcast Video, and
Medical Ultrasound
Jitter and Wander Attenuation, Precise Frequency
Translation, and Low-Jitter Clock Generation for
FPGA, DSP, ASIC, and CPU Devices.
•
•
•
•
3 Description
The LMK05028 device is a high-performance clock
generator, jitter cleaner, and clock synchronizer with
advanced reference clock selection and hitless
switching to meet the stringent requirements of
communications infrastructure applications. The ultralow jitter reduces bit error rates (BER) in high-speed
serial links.
The device has two independent PLL cores that can
each synchronize or lock to one of four reference
clock inputs, and the LMK05028 can generate up to
eight output clocks with up to six different
frequencies.
Device Information(1)
PART NUMBER
PACKAGE
LMK05028
VQFN (64)
BODY SIZE (NOM)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Contact TI Field Sales to inquire about custom factory preprogrammed devices.
LMK05028 Simplified Block Diagram
TCXO/OCXO
(Optional)
VDD,VDDO
LMK05028
High-performance Network Synchronizer
Power
Conditioning
Hitless Switching
with priority
4
PLL Core 1
Output
Dividers
PLL Core 2
6
Output
Buffers
8
Device Control
I2C/SPI/Pin mode
EEPROM/ROM
Logic I/O
XO
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
1
LMK05028
SNAS724 – FEBRUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.20 SPI Timing Requirements (SDA, SCL, GPIO1/SCS,
GPIO2/SDO) ............................................................ 13
7.21 Other Characteristics ............................................ 14
7.22 PLL Clock Output Performance Characteristics ... 14
7.23 Timing Diagrams ................................................... 15
1
1
1
2
3
4
7
8
Parameter Measurement Information ................ 17
9
Detailed Description ............................................ 20
8.1 Test Configuration................................................... 17
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
ADVANCE INFORMATION
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 8
Thermal Information .................................................. 8
Power Supply Characteristics ................................... 8
Clock Input Characteristics (INx_P/N) ...................... 9
XO Input Characteristics (XO_P/N) .......................... 9
TCXO/OCXO Input Characteristics (TCXO_IN)...... 10
APLL/VCO Characteristics...................................... 10
2.5-V LVCMOS Output Characteristics
(OUTx_P/N) ............................................................. 10
7.11 1.8-V LVCMOS Output Characteristics
(OUTx_P/N) ............................................................. 10
7.12 AC-LVDS Output Characteristics (OUTx_P/N) ..... 11
7.13 AC-CML Output Characteristics (OUTx_P/N)....... 11
7.14 AC-LVPECL Output Characteristics (OUTx_P/N). 12
7.15 HCSL Output Characteristics (OUTx_P/N) ........... 12
7.16 2-Level Logic Input Characteristics (PDN,
GPIO[6:0], INSELx_[1:0])......................................... 12
7.17 3-Level Logic Input Characteristics
(HW_SW_CTRL, STATUS[1:0]) .............................. 12
7.18 Logic Output Characteristics (STATUS[1:0],
GPIO[6:5], GPIO2/SDO) .......................................... 13
7.19 I2C Interface Characteristics (SDA, SCL) ............. 13
9.1
9.2
9.3
9.4
9.5
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
20
21
21
36
38
10 Application and Implementation........................ 44
10.1 Application Information.......................................... 44
10.2 Typical Application ............................................... 47
10.3 Do's and Don'ts ..................................................... 51
11 Power Supply Recommendations ..................... 52
11.1 Power Supply Bypassing ...................................... 52
12 Layout................................................................... 52
12.1 Layout Guidelines ................................................. 52
12.2 Layout Example .................................................... 53
12.3 Thermal Reliability................................................. 53
13 Device and Documentation Support ................. 54
13.1
13.2
13.3
13.4
13.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
54
54
54
54
54
14 Mechanical, Packaging, and Orderable
Information ........................................................... 54
4 Revision History
2
DATE
REVISION
NOTES
February 2018
*
Initial release.
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5 Description (continued)
The flexible PLL cores provide programmable loop bandwidth for input jitter and wander attenuation and
fractional frequency translation to generate any output frequency from any input frequency. Each PLL core has
up to 3 feedback loops with two digital PLLs (DPLLs) and one analog PLL (APLL) with integrated VCO. Each
core supports 3 loop or 2 loop mode configurations to optimize clock performance and solution cost for different
use cases.
The reference input muxes supports automatic input selection or manual input selection through software or pin
control. The reference switchover event will be hitless with superior phase transient performance (50 ps typical).
The reference clock input monitoring block monitors the clock inputs and will perform a switchover or holdover
when a loss of reference (LOR) is detected. A LOR can be detected upon any violation of the threshold limits set
for the input clock amplitude, frequency, missing pulse, and runt pulse monitors. The threshold limits for each
input monitor can be set and enabled independently per clock input. The holdover output frequency accuracy can
be determined by the historical average frequency to minimize frequency and phase disturbance during LOR.
The device has eight outputs with programmable drivers, allowing up to eight differential clocks, eight LVCMOS
pairs (two per pair), or a combination of both. The output clocks can be derived from either PLL/VCO domain
through the output channel muxes. A 1-PPS output can be supported on outputs 0 and 7. The output dividers
have a SYNC feature to allow multiple outputs to be phase-aligned. If needed, zero delay can be enabled to
achieve a deterministic phase offset between any specified PLL output clock and its selected input clock.
To support IEEE 1588 PTP slave clock or other clock steering applications, each PLL core also supports DCO
mode with <1-ppt (part per trillion) frequency resolution for precise frequency and phase adjustment through
external software or pin control.
The device is fully programmable through I2C or SPI interface and features custom start-up clock configuration
with the internal EEPROM, which is factory-set and in-system programmable. Internal LDO regulators provide
excellent power supply noise rejection (PSNR) to reduce the cost and complexity of the power delivery network.
The clock input and PLL monitors can be observed through the interrupt registers and status pins for full
diagnostic capability.
Table 1. Clock Output Phase Jitter for 156.25 MHz
INTEGRATION BANDWIDTH
TYPICAL JITTER
MAXIMUM JITTER
12 kHz – 20 MHz
150-fs RMS
225-fs RMS
-80
Phase Noise (dBc/Hz)
-90
-100
-110
-120
-130
-140
-150
-160
-170
100
1000
10000
100000
1000000
Offset Frequency (Hz)
10000000
D001
AC-LVPECL output, IN = 19.44 MHz, XO = 48 MHz, TCXO = 10 MHz
Figure 1. Clock Output Phase Noise for 156.25 MHz
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3
ADVANCE INFORMATION
In three-loop mode, the TCXO/OCXO source determines the free-run and holdover frequency stability and
accuracy, and the XO source determines the output phase noise and jitter performance over the 12-kHz to 20MHz band. Three-loop mode allows the use of a cost-effective, low-frequency TCXO/OCXO (10 or 12.8 MHz) to
support standards-compliant frequency stability and low loop bandwidth (≤10 Hz) required in synchronization
applications like SyncE and SONET/SDH. Two-loop mode allows for either higher loop bandwidth, relaxed
holdover operation where the XO determines the free-run and holdover frequency stability and accuracy, or both.
LMK05028
SNAS724 – FEBRUARY 2018
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6 Pin Configuration and Functions
HW_SW_CTRL
VDDO_7
OUT7_P
OUT7_N
GPIO2/SDO
VDDO_6
OUT6_N
OUT6_P
STATUS1
STATUS0
OUT5_P
OUT5_N
OUT4_N
OUT4_P
VDDO_45
VDD_APLL1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RGC Package
64-Pin VQFN
Top View
1
48
CAP_APLL1
IN0_N
2
47
LF1
VDD_IN0
3
46
PDN
VDD_IN3
4
45
GPIO0/SYNCN
IN3_P
5
44
XO_N
IN3_N
6
43
XO_P
CAP_DIG
7
42
VDD_XO
VDD_DIG
8
41
GPIO4/FDEC1
VDD_IN2
9
40
GPIO3/FINC1
IN2_P
10
39
LF2
IN2_N
11
38
CAP_APLL2
GPIO5/FINC2
12
37
VDD_APLL2
GPIO6/FDEC2
13
36
SCL/SCK
IN1_P
14
35
SDA/SDI
IN1_N
15
34
OUT3_P
VDD_IN1
16
33
OUT3_N
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
TCXO_IN
VDD_TCXO
INSEL0_0
VDDO_0
OUT0_P
OUT0_N
GPIO1/SCS
VDDO_1
OUT1_N
OUT1_P
INSEL1_0
INSEL1_1
VDDO_23
OUT2_P
OUT2_N
GND
INSEL0_1
ADVANCE INFORMATION
IN0_P
Not to scale
Pin Functions
PIN
NAME
NO.
TYPE
(1)
DESCRIPTION
POWER
GND
PAD
G
VDD_IN0
3
P
VDD_IN1
16
P
VDD_IN2
9
P
VDD_IN3
4
P
(1)
4
Ground / Thermal Pad.
The exposed pad must be connected to PCB ground for proper electrical and thermal performance.
A 7x7 via pattern is recommended to connect the IC ground pad to the PCB ground layers.
Core Supply (3.3 V) for Reference Inputs 0 to 3.
Place a nearby 0.1-µF bypass capacitor on each pin.
G = Ground, P = Power, I = Input, O = Output, I/O = Input or Output, A = Analog.
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Pin Functions (continued)
PIN
NAME
NO.
TYPE
VDD_XO
42
P
VDD_TCXO
19
P
VDD_APLL1
49
P
VDD_APLL2
37
P
VDD_DIG
8
P
VDDO_0
21
P
VDDO_1
25
P
VDDO_23
30
P
VDDO_45
50
P
VDDO_6
59
P
VDDO_7
63
P
LF1
47
A
LF2
39
A
CAP_APLL1
48
A
CAP_APLL2
38
A
CAP_DIG
7
A
IN0_P
1
I
IN0_N
2
I
IN1_P
14
I
IN1_N
15
I
IN2_P
10
I
IN2_N
11
I
IN3_P
5
I
IN3_N
6
I
XO_P
43
I
XO_N
44
I
(1)
DESCRIPTION
Core Supply (3.3 V) for XO and TCXO Inputs.
Place a nearby 0.1-µF bypass capacitor on each pin.
Core Supply (3.3 V) for PLL1, PLL2, and Digital Blocks.
Place a nearby 0.1-µF bypass capacitor on each pin.
Output Supply (1.8, 2.5, or 3.3 V) for Clock Outputs 0 to 7.
Place a nearby 0.1-µF bypass capacitor on each pin.
CORE BLOCKS
ADVANCE INFORMATION
External Loop Filter Capacitor for APLL1 and APLL2.
Place a nearby 0.1-µF capacitor on each pin.
External Bypass Capacitors for APLL1, APLL2, and Digital Blocks.
Place a nearby 10-µF bypass capacitor on each pin.
INPUT BLOCKS
TCXO_IN
18
I
OUT0_P
22
O
OUT0_N
23
O
OUT1_P
27
O
OUT1_N
26
O
OUT2_P
31
O
OUT2_N
32
O
OUT3_P
34
O
OUT3_N
33
O
DPLL Reference Clock Inputs 0 to 3.
Each input pair can accept a differential or single-ended clock signal for synchronizing the DPLLs.
Each pair has programmable input type with internal termination to support AC- or DC-coupled
clocks. A single-ended LVCMOS clock can applied to the P input with the N input pulled down to
ground. An unused input pair can be left floating. LVCMOS input mode is recommended for input
frequencies below 1 MHz.
XO Input.
This input pair can accept a differential or single-ended clock signal from a low-jitter local oscillator
to lock the APLLs. This input has programmable input type with internal termination to support ACor DC-coupled clocks. A single-ended LVCMOS clock can applied to the P input with the N input
pulled down to ground.
TCXO Input.
This input can accept an AC-coupled sinewave, clipped-sinewave, or single-ended clock signal from
a stable oscillator (TCXO/OCXO) to lock the TCXO-DPLL if used by a DPLL configuration. The
input swing must be less than 1.2 Vpp before AC-coupling to the input pin, which a weak internal
biasing to about 0.6 V and no internal termination. Leave pin floating if unused.
OUTPUT BLOCKS
Clock Outputs 0 to 3 Bank.
Each programmable output driver pair can support AC-LVDS, AC-CML, AC-LVPECL, HCSL, or
1.8/2.5-V LVCMOS clocks (one or two per pair). Unused differential outputs should be terminated if
active or left floating if disabled through registers.
The OUT[0:3] bank requires at least one clock from PLL2 domain if enabled. This bank is preferred
for PLL2 clocks to minimize output crosstalk.
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Pin Functions (continued)
PIN
NAME
NO.
TYPE
OUT4_P
51
O
OUT4_N
52
O
OUT5_P
54
O
OUT5_N
53
O
OUT6_P
57
O
OUT6_N
58
O
OUT7_P
62
O
OUT7_N
61
LOGIC CONTROL / STATUS
HW_SW_CTRL
ADVANCE INFORMATION
PDN
64
46
I
Device Start-Up Mode Select (3-level, 1.8-V compatible).
This input selects the device start-up mode that determines the memory page used to initialize the
registers, serial interface, and logic pin functions. The input level is sampled only at device poweron reset (POR).
See Table 2 for start-up mode descriptions and logic pin functions.
I
Device Power-Down (active low).
When PDN is pulled low, the device is in hard reset and all blocks including the serial interface are
powered-down. When PDN is pulled high, the device is started according to device mode selected
by HW_SW_CTRL and begins normal operation with all internal circuits reset to their initial state.
I2C Serial Data I/O (SDA) or SPI Serial Data Input (SDI). See Table 2.
The default 7-bit I2C address is 11000xxb, where the MSB bits (11000b) are initialized from on-chip
EEPROM and the LSB bits (xxb) are determined by the logic input pins. When HW_SW_CTRL is 0,
the LSBs are determined by the GPIO[2:1] input levels during POR. When HW_SW_CTRL is 1, the
LSBs are fixed to 00b.
I/O
SCL/SCK
36
I
GPIO0/SYNCN
45
I
GPIO1/SCS
24
I
GPIO2/SDO
60
I/O
GPIO3/FINC1
40
I
GPIO4/FDEC1
41
I
GPIO5/FINC2
12
I/O
GPIO6/FDEC2
13
I/O
STATUS1
56
I/O
STATUS0
55
I/O
INSEL0_1
17
I
INSEL0_0
20
I
INSEL1_1
29
I
INSEL1_0
28
I
6
Clock Outputs 4 to 7 Bank.
Each programmable output driver pair can support AC-LVDS, AC-CML, AC-LVPECL, HCSL, or
1.8/2.5-V LVCMOS clocks (one or two per pair). Unused differential outputs should be terminated if
active or left floating if disabled through registers.
The OUT[4:7] bank requires at least one clock from PLL1 domain. This bank is preferred for PLL1
clocks to minimize output crosstalk.
O
35
(3)
DESCRIPTION
(2) (3)
SDA/SDI
(2)
(1)
I2C Serial Clock Input (SCL) or SPI Serial Clock Input (SCK). See Table 2.
Multifunction Inputs or Outputs.
See Table 2.
Status Outputs [1:0].
Each output has programmable status signal selection, driver type (3.3-V LVCMOS or open-drain),
and status polarity. Open-drain requires an external pullup resistor. Leave pin floating if unused.
Manual Reference Input Selection for DPLL1.
INSEL0_[1:0] = 00b (IN0), 01b (IN1), 10b (IN2), or 11b (IN3). Leave pin floating if unused.
Manual Reference Input Selection for DPLL2.
INSEL1_[1:0] = 00b (IN0), 01b (IN1), 10b (IN2), or 11b (IN3). Leave pin floating if unused.
Internal resistors: PDN pin has 200-kΩ pullup to VDD. Each HW_SW_CTRL, GPIO, and STATUS pin has a 150-kΩ bias to VIM (~0.9 V)
when PDN = 0 or 400-kΩ pulldown when PDN = 1. Each INSEL pin has a 85-kΩ pullup to 1.8 V when PDN = 0 or 400-kΩ pulldown
when PDN = 1.
Unless otherwise noted: Logic inputs are 2-level, 1.8-V compatible inputs. Logic outputs are 3.3-V LVCMOS levels.
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Table 2. Device Start-Up Modes With Logic Pin Functions
0
Float
(VIM)
1
START-UP
MODE
MODE DESCRIPTION
EEPROM + I2C
(Soft pin mode)
Registers are initialized from EEPROM, and I2C interface is enabled. Logic pins:
•
SDA, SCL: I2C Data, I2C Clock (open-drain). Pins require external pullups > 1 kΩ.
•
GPIO0: Output SYNC Input (active low). Tie pin high externally if not used.
•
GPIO[2:1] (1): I2C Address LSB Select Input (00, 01, 10, 11b)
•
GPIO[4:3] (2): DPLL1 DCO Frequency Decrement and Increment Inputs (active high)
•
GPIO[6:5] (2) (3): DPLL2 DCO Frequency Decrement and Increment Inputs (active high), or
Status Outputs
EEPROM + SPI
(4)
(Soft pin mode)
ROM + I2C
(Hard pin mode)
Registers are initialized from EEPROM, and SPI interface is enabled. Logic pins:
•
SDA, SCL: SPI Data Input (SDI), SPI Clock (SCK)
•
GPIO1: SPI Chip Select (SCS)
•
GPIO2: SPI Data Output (SDO)
•
GPIO[6:3, 0]: Same as for HW_SW_CTRL = 0
Registers are initialized from the ROM page selected by GPIO pins, and I2C interface is enabled.
Logic pins:
•
SDA, SCL: I2C Data, I2C Clock (open-drain). Pins require external pullups > 1 kΩ.
•
GPIO[3:0] (1): ROM Page Select Input (0000 to 1111b)
•
GPIO[6:5] (3): Status Outputs
•
GPIO4: Not used during POR
ADVANCE INFORMATION
HW_SW_CTRL
INPUT LEVEL (1)
After POR, GPIO[6:3] can function the same as for HW_SW_CTRL = 0 if enabled by registers.
(1)
(2)
(3)
(4)
The input levels on these pins are sampled only during POR.
These GPIO pins are only functional when the DCO feature and FINC/FDEC pin controls are enabled by registers.
As status outputs, the GPIO[6:5] pins have the same capabilities as the STATUS[1:0] pins described in .
When HW_SW_CTRL = Float (VIM), the STATUS[1:0] pins momentarily function as 3-level inputs and both pins must be biased to VIM
(internally or externally) during device POR to ensure proper start-up. If either STATUS pin is connected to an external host device
(MCU, FPGA), the external device must be configured with high-impedance inputs (no pullup or pulldown) to avoid conflict with the
internal bias to VIM. If needed, external biasing resistors (10-kΩ pullup to 3.3 V and 3.75-kΩ pulldown) can be connected on each
STATUS pin to bias the inputs to VIM during POR.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VDD
(2)
VDDO
(3)
MIN
MAX
UNIT
Core Supply Voltages
–0.3
3.6
V
Output Supply Voltages
–0.3
3.6
V
Vin
Input Voltage for Clock and Logic Inputs
–0.3
VDD + 0.3
V
Vout
Output Voltage for Clock and Logic Outputs
–0.3
VDD + 0.3
V
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
VDD refers to all core supply pins or voltages. All VDD core supplies should be powered-on before internal power-on reset (POR).
VDDO refers to all output supply pins or voltages. VDDO_x refers to the output supply for a specific output channel, where x denotes
the channel index.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±750
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
VDD
(1)
VDDO
Core Supply Voltages
AC-LVDS/CML/LVPECL, HCSL
(1)
Output Supply Voltages
TA
Ambient Temperature
TJ
Junction Temperature
tVDD
Power Supply Ramp Time
nEEcyc
EEPROM Programming Cycles
(1)
(2)
(3)
1.8-V or 2.5-V LVCMOS
(2)
(3)
MIN
NOM
MAX
UNIT
3.135
3.3
3.465
V
1.71
1.8, 2.5, 3.3
3.465
V
1.71
1.8, 2.5
2.625
V
–40
25
85
°C
0.01
135
°C
100
ms
100
cycles
VDD refers to all core supply pins or voltages. All VDD core supplies should be powered-on before internal power-on reset (POR).
The LVCMOS driver supports full rail-to-rail swing when VDDO_x is 1.8 V or 2.5 V ± 5%. When VDDO_x is 3.3 V, the LVCMOS driver
cannot swing fully to the positive rail due to the dropout voltage of the output channel's internal LDO regulator.
Time for VDD to ramp monotonically above 2.7 V for proper internal POR. For slower or non-monotonic VDD ramp, hold PDN low until
after VDD voltages are valid.
7.4 Thermal Information
LMK05028
ADVANCE INFORMATION
THERMAL METRIC (1)
RGC (VQFN)
(2) (3)
UNIT
64 PINS
0-LFM AIRFLOW
RθJA
Junction-to-ambient thermal resistance
20.5
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
6.3
°C/W
RθJB
4.9
°C/W
0.3
°C/W
Junction-to-board thermal resistance
RθJC(bot) Junction-to-case (bottom) thermal resistance
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
4.8
°C/W
(1)
(2)
(3)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The thermal information is based on a 10-layer 200 mm x 250 mm board with 49 thermal vias (7 x 7 pattern, 0.3 mm holes)
ψJB can allow the system designer to measure the board temperature (TPCB) with a fine-gauge thermocouple and back-calculate the
device junction temperature, TJ = TPCB + (ψJB x Power). Measurement of ψJB is defined by JESD51-6.
7.5 Power Supply Characteristics (1)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40ºC to 85ºC. Specification applies to both
Configuration A (2) and Configuration B (3) unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IDD_IN[0,1,
3]
Core Supply Current
(VDD_INx)
3.5
mA
IDD_IN2
Core Supply Current
(VDD_INx)
6
mA
Core Supply Current
(VDD_PLL1)
Configuration A
(2)
IDD_PLL1
160
mA
Configuration B
(3)
185
mA
IDD_PLL2
Core Supply Current
(VDD_PLL2)
Configuration A
138
mA
Configuration B
160
mA
IDD_DIG
Core Supply Current
(VDD_DIG)
Configuration A
34
mA
Configuration B
42
mA
IDD_XO
Core Supply Current
(VDD_XO)
25
mA
(1)
(2)
(3)
8
Total device current can be estimated by summing the individual IDD_x and IDDO_x per pin for all blocks enabled in a given
configuration.
Configuration A (All blocks on except TCXO_IN and both TCXO-DPLLs): IN[0:3] = 25 MHz, XO = 48.0048 MHz, TCXO_IN disabled.
Both DPLLs in 2 loop mode, DPLL[1:2] REF-TDC ~ 0.4 MHz, VCO1 = 5 GHz, PLL1_P1 = 8, VCO2 = 5.5296 GHz, PLL2_P1 = 9.
Configuration B (All blocks on): IN[0:3] = 25 MHz, XO = 48.0048 MHz, TCXO_IN = 10 MHz. Both DPLLs in 3 loop mode, DPLL[1:2]
REF-TDC ~ 0.4 MHz, TCXO-TDC = 10 MHz, VCO1 = 5 GHz, PLL1_P1 = 8, VCO2 = 5.5296 GHz, PLL2_P1 = 9.
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Power Supply Characteristics(1) (continued)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40ºC to 85ºC. Specification applies to both
Configuration A (2) and Configuration B (3) unless otherwise noted.
IDD_TCXO
IDDO_x
IDD_PD
TEST CONDITIONS
Core Supply Current
(VDD_TCXO)
Output Supply Current
(VDDO_x = 3.3 V ± 5%)
Total Supply Current in
Power-down (all VDD and
VDDO pins)
MIN
Configuration A
Configuration B
TYP
MAX
UNIT
1
mA
6
mA
AC-LVDS (one pair), 156.25 MHz
22
mA
AC-CML (one pair), 156.25 MHz
24
mA
AC-LVPECL (one pair), 156.25 MHz
27
mA
HCSL (one pair), 156.25 MHz
33
mA
2.5-V LVCMOS (two outputs), 156.25 MHz,
5-pF load
40
mA
1.8-V LVCMOS (two outputs), 156.25 MHz,
5-pF load
33
mA
Device powered-down (PDN pin = 0)
40
mA
ADVANCE INFORMATION
PARAMETER
7.6 Clock Input Characteristics (INx_P/N)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40ºC to 85ºC
PARAMETER
TEST CONDITIONS
fCLK
Input frequency (1)
VIH
Input high voltage
VIL
Input low voltage
VIN_DIFF
Differential input voltage
swing, peak-peak (VP – VN)
dV/dt
Input slew rate
IIN
Input leakage current
CIN
Input capacitance
(1)
(2)
LVCMOS input
Differential input
(2)
LVCMOS input
Differential input
(1)
MIN
TYP
MAX
1E-6
250
1
750
UNIT
MHz
1.4
V
0
0.8
V
0.2
2
V
0.2
V/ns
–100
Single-ended, each pin
100
µA
2
pF
Parameter is specified by characterization and is not tested in production.
For inputs less than 1 MHz, use LVCMOS input or else disable the amplitude monitor.
7.7 XO Input Characteristics (XO_P/N)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40ºC to 85ºC
PARAMETER
TEST CONDITIONS
(1)
fCLK
Input frequency
VIH
Input high voltage
VIL
Input low voltage
VIN_DIFF
Differential input voltage
swing, peak-peak (VP – VN)
dV/dt
Input slew rate
IDC
Input duty cycle
IIN
Input leakage current
CIN
Input capacitance
(1)
LVCMOS input
Differential input
(1)
MIN
MAX
UNIT
10
TYP
100
MHz
1.4
2.6
V
0
0.8
V
0.2
2
V
0.2
Single-ended, each pin
V/ns
40
60
%
–100
100
uA
1
pF
Parameter is specified by characterization and is not tested in production.
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7.8 TCXO/OCXO Input Characteristics (TCXO_IN)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40ºC to 85ºC
PARAMETER
TEST CONDITIONS
(1)
fCLK
Input frequency
VIN
Input voltage swing
VBIAS
Input bias voltage
dV/dt
Input slew rate
IDC
Input duty cycle
CIN
Input capacitance
(1)
Biased internally
(1)
MIN
MAX
UNIT
10
54
MHz
0.8
1.3
V
TBD
TYP
0.6
TBD
0.2
V
V/ns
40
60
10
%
pF
Parameter is specified by characterization and is not tested in production.
7.9 APLL/VCO Characteristics
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40ºC to 85ºC
PARAMETER
ADVANCE INFORMATION
MAX
UNIT
fVCO1
VCO1 Frequency range
(1)
4.8
5.4
GHz
fVCO2
VCO2 Frequency range
(1)
5.5
6.2
GHz
MAX
UNIT
200
MHz
(1)
TEST CONDITIONS
MIN
TYP
Parameter is specified by characterization and is not tested in production.
7.10 2.5-V LVCMOS Output Characteristics (OUTx_P/N)
VDD = 3.3 V ± 5%, VDDO = 2.5 V ± 5%, TA = –40ºC to 85ºC, Fast slew rate
PARAMETER
TEST CONDITIONS
(1)
fOUT
Output frequency
VOH
Output high voltage
IOH = 1 mA
VOL
Output low voltage
IOL = 1 mA
IOH
Output high current
IOL
Output low current
tR/tF
Output rise/fall time
1.9
-48
20% to 80%
250
(1)
tSKEW
Output-to-output skew
(1)
Same post divider and output divide values,
LVCMOS-to-DIFF
PN-Floor
Output phase noise floor
(fOFFSET = 10 MHz) (1)
(1)
Output impedance
(1)
66.66 MHz
mA
TBD
ps
100
ps
1.5
ns
–155
Not PLL bypass output
45
V
mA
55
(1)
Output-to-output skew
Output duty cycle
V
0.525
tSKEW
ROUT
TYP
1E-6
Same post divider, output divide values, and
output type
ODC
MIN
dBc/Hz
55
50
%
Ω
Parameter is specified by characterization and is not tested in production.
7.11 1.8-V LVCMOS Output Characteristics (OUTx_P/N)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, TA = –40ºC to 85ºC, Fast slew rate
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
fOUT
Output frequency
1E-6
VOH
Output high voltage
IOH = 1 mA
VOL
Output low voltage
IOL = 1 mA
IOH
Output high current
-23
IOL
Output low current
24
tR/tF
Output rise/fall time
(1)
20% to 80%
tSKEW
Output-to-output skew
(1)
tSKEW
Output-to-output skew
(1)
Same post divider and output divide values,
LVCMOS-to-DIFF
10
UNIT
200
MHz
1.2
V
0.4
Same post divider, output divide values, and
output type
(1)
MAX
250
V
mA
TBD
ps
100
ps
1.5
ns
Parameter is specified by characterization and is not tested in production.
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1.8-V LVCMOS Output Characteristics (OUTx_P/N) (continued)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, TA = –40ºC to 85ºC, Fast slew rate
PARAMETER
PN-Floor
TEST CONDITIONS
Output phase noise floor
(fOFFSET = 10 MHz) (1)
(1)
ODC
Output duty cycle
ROUT
Output impedance
MIN
66.66 MHz
TYP
MAX
–155
Not PLL bypass output
45
UNIT
dBc/Hz
55
%
50
Ω
7.12 AC-LVDS Output Characteristics (OUTx_P/N)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40ºC to 85ºC, Output pair AC-coupled to 100-Ω
differential load, Fast slew rate
TEST CONDITIONS
Output frequency (1)
VOD
Output voltage swing (VOHVOL)
VODpp
Differential output voltage
swing, peak-to-peak
VOS
Output common mode
tSKEW
Output-to-output skew
tR/tF
Output rise/fall time
PN-Floor
Output phase noise floor
(fOFFSET = 10 MHz)
ODC
Output duty cycle
(1)
(2)
MIN
TYP
(2)
fOUT ≥ 25 MHz
250
400
Same post divider, output divide values, and
output type
20% to 80%, < 300 MHz
(1)
150
±100 mV around center point, > 300 MHz
(1)
UNIT
750
MHz
450
mV
2 × |VOD|
100
(1)
MAX
V
430
mV
100
ps
300
–160
Not PLL bypass output
ps
200
156.25 MHz
45
ADVANCE INFORMATION
PARAMETER
fOUT
dBc/Hz
55
%
Parameter is specified by characterization and is not tested in production.
An output frequency over the fOUT max spec is possible, but the output swing may be less than the VOD min spec.
7.13 AC-CML Output Characteristics (OUTx_P/N)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40ºC to 85ºC, Output pair AC-coupled to 100-Ω
differential load, Fast slew rate
PARAMETER
TEST CONDITIONS
fOUT
Output frequency
VOD
Output voltage swing (VOHVOL)
VODpp
Differential output voltage
swing, peak-to-peak
VOS
Output common mode
(1)
Output-to-output skew
tR/tF
Output rise/fall time
PN-Floor
Output phase noise floor
(fOFFSET = 10 MHz)
(1)
(2)
Output duty cycle
TYP
(1)
(1)
fOUT ≥ 25 MHz
400
600
MAX
UNIT
750
MHz
800
mV
2 x |VOD|
150
tSKEW
ODC
MIN
(1) (2)
Same post divider, output divide values, and
output type
20% to 80%, < 300 MHz
150
±100 mV around center point, > 300 MHz
550
mV
100
ps
300
ps
200
156.25 MHz
Not PLL bypass output
V
–160
45
dBc/Hz
55
%
Parameter is specified by characterization and is not tested in production.
An output frequency over the fOUT max spec is possible, but the output swing may be less than the VOD min spec.
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7.14 AC-LVPECL Output Characteristics (OUTx_P/N)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40ºC to 85ºC, Output pair AC-coupled to 100-Ω
differential load, Fast slew rate
PARAMETER
TEST CONDITIONS
fOUT
Output frequency (1)
VOD
Output voltage swing (VOHVOL)
VODpp
Differential output voltage
swing, peak-to-peak
VOS
Output common mode
TYP
fOUT ≥ 25 MHz
500
800
Output-to-output skew
tR/tF
Output rise/fall time
PN-Floor
Output phase noise floor
(fOFFSET = 10 MHz)
ODC
Output duty cycle
Same post divider, output divide values, and
output type
20% to 80%, < 300 MHz
(1)
150
±100 mV around center point, > 300 MHz
(1)
MAX
UNIT
750
MHz
1000
mV
2 × |VOD|
300
(1)
tSKEW
ADVANCE INFORMATION
(1)
(2)
MIN
(2)
V
700
mV
100
ps
300
200
156.25 MHz
–162
Not PLL bypass output
45
ps
dBc/Hz
55
%
Parameter is specified by characterization and is not tested in production.
An output frequency over the fOUT max spec is possible, but the output swing may be less than the VOD min spec.
7.15 HCSL Output Characteristics (OUTx_P/N)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40ºC to 85ºC, Output pair terminated with 50 Ω to
GND, Fast slew rate
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fOUT
Output frequency
400
MHz
VOH
Output high voltage
600
880
mV
VOL
Output low voltage
–150
150
mV
tSKEW
Output-to-output skew
100
ps
dV/dt
Output slew rate (1)
Measured from -150 mV to +150 mV on the
differential waveform
PN-Floor
Output phase noise floor
(fOFFSET = 10 MHz)
100 MHz
ODC
Output duty cycle
(1)
(1)
(1)
Same post divider, output divide values, and
output type
2.5
8
–158
Not PLL bypass output
45
V/ns
dBc/Hz
55
%
Parameter is specified by characterization and is not tested in production.
7.16 2-Level Logic Input Characteristics (PDN, GPIO[6:0], INSELx_[1:0])
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40ºC to 85ºC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.2
UNIT
VIH
Input high voltage
V
VIL
Input low voltage
0.6
V
IIH
Input high current
VIH = VDD
–40
40
uA
IIL
Input low current
VIL = GND
–40
40
uA
tWIDTH
Input pulse width
Monotonic edges
CIN
Input capacitance
10
ns
2
pF
7.17 3-Level Logic Input Characteristics (HW_SW_CTRL, STATUS[1:0])
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40ºC to 85ºC
PARAMETER
VIH
Input high voltage
VIM
Input mid voltage
VIL
Input low voltage
12
TEST CONDITIONS
MIN
TYP
MAX
1.4
Input floating with internal bias
V
0.9
V
0.4
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UNIT
V
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3-Level Logic Input Characteristics (HW_SW_CTRL, STATUS[1:0]) (continued)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40ºC to 85ºC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIH
Input high current
VIH = VDD
–40
40
uA
IIL
Input low current
VIL = GND
–40
40
uA
CIN
Input capacitance
2
pF
7.18 Logic Output Characteristics (STATUS[1:0], GPIO[6:5], GPIO2/SDO)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40ºC to 85ºC
PARAMETER
TEST CONDITIONS
VOH
Output high voltage
IOH = 3 mA, LVCMOS mode
VOL
Output low voltage
IOL = 3 mA
tR/tF
Output rise/fall time
20% to 80%, LVCMOS mode, 1 kΩ to GND
MIN
TYP
MAX
UNIT
TBD
V
0.6
V
500
ps
7.19 I2C Interface Characteristics (SDA, SCL)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VIH
Input high voltage
VIL
Input low voltage
1.2
IIH
Input leakage
V
CIN
Input capacitance
VOL
Output low voltage
IOL = 3 mA
0.3
V
fSCL
SCL clock rate
Standard
100
kHz
fSCL
SCL clock rate
Fast mode
400
kHz
tSU_STA
START condition setup
time
SCL high before SDA low
0.6
us
tH_STA
START condition hold time
SCL low after SDA low
0.6
us
tPH_STA
SCL pulse width high
0.6
us
tPL_STA
SCL pulse width low
1.3
tSU_SDA
SDA hold time
tH_SDA
SDA setup time
tR_IN
SCL/SDA input rise time
300
ns
tF_IN
SCL/SDA input fall time
300
ns
tF_OUT
SDA output fall time
300
ns
tSU_STOP
STOP condition setup time
0.6
us
tBUS
Bus free time between
STOP and START
1.3
us
tVD-DAT
Data valid time
0.9
us
tVD-ACK
Data valid acknowledge
time
0.9
us
–15
0.5
V
15
uA
1
SDA valid after SCL low
ADVANCE INFORMATION
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40ºC to 85ºC
pF
us
0
0.9
us
100
ns
CBUS ≤ 400 pF
7.20 SPI Timing Requirements (SDA, SCL, GPIO1/SCS, GPIO2/SDO)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40ºC to 85ºC
PARAMETER
MIN
NOM
MAX
UNIT
20
MHz
fClock
SCL clock rate
t1
SCS to SCL setup time
10
ns
t2
SDI to SCL setup time
10
ns
t3
SDI to SCL hold time
10
ns
t4
SCL high time
25
ns
t5
SCL low time
25
ns
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SPI Timing Requirements (SDA, SCL, GPIO1/SCS, GPIO2/SDO) (continued)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40ºC to 85ºC
PARAMETER
MIN
NOM
MAX
UNIT
TBD
ns
t6
SCL to SDO valid read-back data
10
t7
SCS pulse width
20
ns
t8
SCS to CLK hold time
10
ns
7.21 Other Characteristics
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40ºC to 85ºC, OUTx = 156.25 MHz, Differential
output pair AC-coupled to 100-Ω differential load, HCSL output pair terminated with 50 Ω to GND, LVCMOS output terminated
with 50 Ω to VDDO / 2.
PARAMETER
tPHO,CMO
TEST CONDITIONS
MIN
NOM
MAX
UNIT
IN-to-OUT Phase Offset,
LVCMOS outputs (1)
Zero delay enabled
TBD
ns
tPHO,DIFF
IN-to-OUT Phase Offset, DIFF
outputs (1)
Zero delay enabled
TBD
ns
PSNR
Spur level induced by power
supply noise (VN = 50 mVpp)
VDDO_x = 2.5 V or 3.3 V, AC-Diff or
HCSL output
–70
dBc
VDDO_x = 2.5 V, LVCMOS output
–55
dBc
VDDO_x = 1.8 V, AC-Diff or HCSL output
–70
dBc
VDDO_x = 1.8 V, LVCMOS output
–45
dBc
OUTx = 156.25 MHz, OUTy = 155.52
MHz, AC-Diff or HCSL (same output type
for both channels)
–75
dBc
S
ADVANCE INFORMATION
Spur level induced by power
supply noise (VN = 25 mVpp)
PSNR
Spur level due to isolation/cross
coupling (adjacent outputs)
SPUR
(1)
Parameter is specified by characterization and is not tested in production.
7.22 PLL Clock Output Performance Characteristics
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40ºC to 85ºC, OUTx = 156.25 MHz, Differential
output pair AC-coupled to 100-Ω differential load, HCSL output pair terminated with 50 Ω to GND, LVCMOS output terminated
with 50 Ω to VDDO / 2.
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
150
225
fs RMS
RJ
RMS Phase Jitter (1) (12
kHz – 20 MHz)
OUT = 156.25 MHz AC-Diff or HCSL, XO =
48.0048 MHz
PN-TDC
Output Close-in Phase
Noise (fOFFSET = 100 Hz)
OUT = 122.88 MHz AC-Diff or HCSL, IN = 10
MHz, XO = 48.0048 MHz, LBW = 100 Hz
LBW
DPLL Loop Bandwidth
Range (1) (2)
Programmed bandwidth setting
JPK
Jitter Peaking (1)
IN = 25 MHz, OUT = 25 MHz, DPLL BW = TBD
Hz
JTOL
Jitter tolerance (1)
Jitter Modulation = 10 Hz, 10.3125 Gbps
2488
UI p-p
PHTR
Maximum phase transient
during Hitless Switch (1)
Valid for a single switchover event between two
clock inputs at the same frequency
±100
ps
fERROR
Maximum additive
frequency error (1)
Valid for a single switchover event between two
clock inputs at the same frequency
100
ppb
Initial Clock Start-up Time
From rising edge of PDN to free-running output
clocks from first PLL domain
20
ms
tSTART-XO
STD
(1)
(2)
(3)
14
(3)
–102
dBc/Hz
0.01 to
4000
Hz
0.1
dB
G.813 Opt. 1
G.8262 Opt. 1 and 2
G.709
GR-253-CORE
GR-1244 CORE
Standards Compliance
Parameter is specified by characterization and is not tested in production.
Actual loop bandwidth may be lower. Applies to REF-DPLL and TCXO-DPLL. The valid loop bandwidth range may be constrained by
the DPLL loop mode and REF and/or TCXO input frequencies used in a given configuration.
First PLL domain to start-up is selected by PLLSTRTMODE bit. Assumes XO input clock is stable before rising edge of PDN, PLL/VCO
wait timers set to 3 ms/0.4 ms, and output channels auto-muted during APLL lock only.
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7.23 Timing Diagrams
OUTx_P
VOD
OUTx_N
80%
VOUT,DIFF,PP = 2 x VOD
0V
20%
tR
tF
Figure 2. Differential Output Voltage and Rise/Fall Time
ADVANCE INFORMATION
80%
VOUT,SE
OUT_REFx/2
20%
tR
tF
Figure 3. Single-Ended Output Voltage and Rise/Fall Time
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Timing Diagrams (continued)
INx_P
Single Ended
INx_P
Differential
INx_N
tPHO,DIFF
OUTx_P
Differential, PLL
OUTx_N
tSK,DIFF,INT
OUTx_P
ADVANCE INFORMATION
Differential, PLL
OUTx_N
tSK,SE-DIFF,INT
Single Ended, PLL
OUTx_P/N
tPHO, SE
tSK,SE,INT
OUTx_P/N
Single Ended, PLL
Figure 4. Differential and Single-Ended Output Skew and Phase Offset
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8 Parameter Measurement Information
8.1 Test Configuration
This section describes the test configuration for several electrical characteristics.
High impedance probe
LVCMOS
LMK05028
Oscilloscope
2pF
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LMK05028
ADVANCE INFORMATION
Figure 5. LVCMOS Output DC Configuration During Device Test
Phase Noise/
Spectrum
Analyzer
LVCMOS
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Figure 6. LVCMOS Output AC Configuration During Device Test
High impedance differential probe
AC-LVPECL,
AC-LVDS,
AC-CML
LMK05028
Oscilloscope
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Figure 7. AC-LVPECL, AC-LVDS, AC-CML Output DC Configuration During Device Test
High impedance differential probe
Opt ± 33
LMK05028
HCSL
Opt ± 33
Oscilloscope
HCSL
50
50
Copyright © 2018, Texas Instruments Incorporated
Figure 8. HCSL Output Driving 100-Ω Differential Trace Impedance DC Configuration During Device Test
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Test Configuration (continued)
AC-LVPECL, AC-LVDS, AC-CML
LMK05028
Phase Noise/
Spectrum
Analyzer
Balun
AC-LVPECL, AC-LVDS, AC-CML
Copyright © 2018, Texas Instruments Incorporated
Figure 9. AC-LVPECL, AC-LVDS, AC-CML Output AC Configuration During Device Test
Opt ± 33
LMK05028
Opt ± 33
HCSL
Balun
HCSL
ADVANCE INFORMATION
50
Phase Noise/
Spectrum
Analyzer
50
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Figure 10. HCSL Output Driving 100-Ω Differential Trance Impedance AC Configuration During Device
Test
LVCMOS
LMK05028
Signal Generator
Offset = VDD_IN/2
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Figure 11. LVCMOS Reference Input DC Configuration During Device Test
125
Signal Generator
LMK05028
375
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Figure 12. LVCMOS XO Input DC Configuration During Device Test
Signal Generator
LVDS
LMK05028
100
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Figure 13. LVDS Input DC Configuration During Device Test
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Test Configuration (continued)
Signal Generator
LMK05028
LVPECL
50
50
VDD_IN - 2
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Figure 14. LVPECL Input DC Configuration During Device Test
Signal Generator
HCSL
ADVANCE INFORMATION
50
LMK05028
50
Copyright © 2018, Texas Instruments Incorporated
Figure 15. HCSL Input DC Configuration During Device Test
Differential
Signal Generator
LMK05028
Copyright © 2018, Texas Instruments Incorporated
100-Ω differential input termination with AC biasing enabled internally (not shown)
Figure 16. Differential Input AC Configuration During Device Test
Sine wave
Modulator
Power Supply
Signal Generator
LMK05028
Device Output
Balun
Reference
Input
Phase Noise/
Spectrum
Analyzer
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Figure 17. PSNR Test Setup
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9 Detailed Description
9.1 Overview
The LMK05028 is a high-performance clock generator and jitter cleaner with advanced clock synchronization
capabilities to meet the stringent timing requirements of communications infrastructure and other industrial
applications. The device features four reference inputs, two independent PLL domains, and eight output clocks
with RMS phase jitter of 150 fs typical. Each PLL core supports programmable loop bandwidth for jitter or wander
attenuation, and fractional frequency translation for flexible frequency planning. The advanced synchronization
options in each PLL core include superior hitless switching, digital holdover, DCO mode with <1 ppt/step for
precise clock steering (IEEE 1588 PTP slave operation), and zero delay for deterministic input-to-output phase
offset. The device can use a low-frequency TCXO/OCXO to determine the free-run or holdover frequency
stability for standards-compliant operation, or a standard XO when long-term stability and wander are non-critical.
The device is programmable through I2C or SPI registers and supports custom start-up clock configuration with
internal EEPROM, which can be programmed in-system or factory pre-programmed.
ADVANCE INFORMATION
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9.2 Functional Block Diagrams
VDD (x9)
3.3 V
TCXO/OCXO
10-54 MHz
(Optional)
VDDO (x6)
3.3/2.5/1.8 V
XO
10-100 MHz
Power Conditioning
(all blocks)
M Div
5-b
SYNC
x2
System
Clocks (3.3 V)
2
1
0
INSEL0[1:0]
0
1
2
3
4
5
OUT Divs
11-b * 20-b
OUT0
0
1
2
3
4
5
OUT Div
20-b
OUT1
0
1
2
3
OUT Div
20-b
IN2
To APLL
R Div
16-b
VCO1
PLL Core 1
To REF TDC
P1 Div
VCO1 Freq = 4.8 - 5.4 GHz
P2 Div
IN3
OUT2
FB Div
5-b
/48
FB Div
5-b
/48
OUT4
0
1
2
3
TCXO
Hitless Switching
with Priority
To TCXO TDC
R Div
16-b
OUT3
TCXO
PLL1
FB CLK
IN4 (PLL1
FB CLK)
PLL2
FB CLK
To TCXO TDC
IN5 (PLL2
FB CLK)
To APLL
PLL Core 2
To REF TDC
OUT Div
20-b
OUT5
P1 Div
VCO2
VCO2 Freq = 5.5 - 6.2 GHz
P2 Div
P Div range:
/4-/9, /11, /13
Synthesizers (3.3 V)
INSEL1[1:0]
0
1
2
3
OUT Div
20-b
OUT6
0
1
2
3
OUT Divs
11-b * 20-b
OUT7
Inputs (3.3 V)
SDA
Output (3.3/2.5/1.8 V)
Registers EEPROM
ROM
SCL
HW_SW_CTRL
GPIO[6:0]
STATUS[1:0]
PDN
Device Control
and Status
1.5-V to 3.3-V
Logic I/O Levels
Control (3.3 V)
CAP (x3) LF1
LF2
Copyright © 2018, Texas Instruments Incorporated
Figure 18. LMK05028 Block Diagram
9.3 Feature Description
The following section describes the features of the device functional blocks.
9.3.1 Oscillator Input (XO_P/N)
The XO input is the reference clock for the Fractional-N APLLs. The combination of XO and APLL determine the
jitter and phase noise performance of the output clocks. For optimal performance, the XO frequency should be
between 48 to 54 MHz and have a non-integer frequency relationship with the VCO frequencies so the APLLs
operate in Fractional mode.
The XO input buffer has programmable input on-chip termination and biasing controls to support any oscillator
interface type.
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Hitless Switching
with Priority
IN1
AC-LVDS/CML/LVPECL, HCSL, and 2.5/1.8-V LVCMOS (x2)
IN0
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Feature Description (continued)
9.3.2 TCXO Input (TCXO_IN)
The TCXO input is the reference clock to the TCXO-DPLL loop in each PLL core. When the PLL core uses the
TCXO-DPLL in 3-loop mode (typically), the TCXO input determines the wander and close-in phase noise
performance when the DPLL is locked, and the frequency accuracy and stability during holdover mode. A TCXO
input with high phase noise floor should have minimal or no impact on the output jitter performance, provided the
TCXO loop bandwidth is designed low enough to attenuate its noise contribution. When the TCXO input is not
used, the XO determines the frequency accuracy and stability during free-run or holdover modes.
The TCXO input accepts an AC-coupled single-ended clock (sine, clipped-sine, or square wave) and has a
internal weak bias of about 0.6 V. The input voltage swing should be less than 1.2 Vpp and attenuated or
terminated before AC-coupling to the pin. This input can be driven from a low-frequency TCXO, OCXO, or
external timing reference that conforms to the frequency accuracy and holdover stability requirements required
by the application. TCXO and OCXO frequencies of 10 to 12.8 MHz are widely available and cost-effective
options.
9.3.3 Reference Inputs (INx_P/N)
ADVANCE INFORMATION
The reference inputs (IN0 to IN3) can accept differential or LVCMOS clocks to lock either or both DPLLs. Each
DPLL has an input mux to select one of the four inputs. Each DPLL can support switching between two or more
inputs with different frequencies provided each input can be divided down by DPLL reference dividers
(DPLLy_REFx_RDIV) to a single common frequency.
Each input has programmable input type, on-chip termination, and biasing controls to support any clock interface
type.
Figure 19 shows the input termination and biasing options implemented on the reference and XO inputs. The
internal switch options are register configurable. Table 3 shows the typical input buffer configurations to interface
with LVDS, CML, LVPECL HCSL, and LVCMOS drivers.
LMK05028
Differential Input Control
7pF
IN_P/
XO_P/
TCXO_P
SWHCSL
SWLVDS
SWAC
50
100
7pF
IN_N/XO_N
SWHCSL
SWAC
50
Copyright © 2018, Texas Instruments Incorporated
Figure 19. Input Buffer Termination Options for Reference, XO, and TCXO Inputs
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Feature Description (continued)
Table 3. Input Buffer Configurations for Reference and XO Inputs
MODE
INTERNAL COUPLING
HCSL
AC
TERMINATION
Internal (50 Ω)
LVDS (DC-coupled)
AC
Internal (100 Ω)
LVDS, CML, LVPECL (AC-coupled)
AC
Internal (100 Ω)
CML or LVPECL (DC-coupled)
AC
External
LVCMOS
DC
External
Figure 20 through Figure 24 show recommendations for interfacing LMK05028’s clock inputs with LVCMOS,
LVPECL, LVDS, CML, and HCSL drivers, respectively.
3.3V LVCMOS
Driver
LVCMOS
Rs
LMK05028
ADVANCE INFORMATION
Copyright © 2018, Texas Instruments Incorporated
Figure 20. Interfacing LMK05028 Input With LVCMOS Driver (3.3 V, 2.5 V, 1.8 V)
LVPECL Driver
LMK05028
LVPECL
50
50
VDD_IN - 2
Copyright © 2018, Texas Instruments Incorporated
Figure 21. Interfacing LMK05028 Inputs With DC-Coupled LVPECL Driver
LMK05028
LVDS Driver
LVDS
100
Copyright © 2018, Texas Instruments Incorporated
Figure 22. Interfacing LMK05028 Inputs With DC-Coupled LVDS Driver
CML
Driver
CML
LMK05028
Copyright © 2018, Texas Instruments Incorporated
Figure 23. Interfacing LMK05028 Inputs With DC-Coupled CML Driver (Source Terminated)
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50
HCSL
Driver
HCSL
LMK05028
50
Copyright © 2018, Texas Instruments Incorporated
Figure 24. Interfacing LMK05028 Inputs With HCSL Driver (Load Terminated)
9.3.4 Reference Input Mux Selection
ADVANCE INFORMATION
For each DPLL, the reference input mux selection can be done automatically using an internal state machine
with a configurable input priority scheme manually through register control or hardware pin controls. The input
mux can select from IN0 to IN3. Additionally, DPLL1 can select IN5 as an internal loopback clock divided from
PLL2 VCO (VCO2), and DPLL2 can select IN4 as an internal loopback clock from PLL1 VCO (VCO2).
The priority for all inputs can be assigned for each DPLL through registers. The priority ranges from 0 to 6, where
0 means Ignored (never select) and 1 to 6 are highest (1st) to lowest (6th) priority. When two or more inputs are
configured with the same priority setting, the reference input with lower index (INx) will be given higher priority.
The currently selected reference input for each DPLL can be read through a status pin or register.
9.3.4.1 Automatic Input Selection
There are two automatic input selection modes that can be set by a register: Auto Revertive and Auto NonRevertive.
• Auto Revertive: In this mode, the DPLL automatically selects the valid input with the highest configured
priority. If a clock with higher priority becomes valid, the DPLL will automatically switch over to that clock
immediately.
• Auto Non-Revertive: In this mode, the DPLL automatically selects the highest priority input that is valid. If a
higher priority input because valid, the DPLL will not switch-over until the currently selected input becomes
invalid.
9.3.4.2 Manual Input Selection
There are two manual input selection modes that can be set by a register: Manual with Auto-Fallback and
Manual with Auto-Holdover. In either manual mode, the input selection can be done through register control
(Table 4) or hardware pin control (Table 5).
• Manual with Auto-Fallback: In this mode, the manually selected reference is the active reference until it
becomes invalid. If the reference becomes invalid, the DPLL will automatically fallback to the highest priority
input that is valid or qualified. If no prioritized inputs are valid, the DPLL will enter holdover mode (if tuning
word history is valid) or free-run mode. The DPLL will exit holdover mode when the selected input becomes
valid.
• Manual with Auto-Holdover: In this mode, the manually selected reference is the active reference until it
becomes invalid. If the reference becomes invalid, the DPLL will automatically enter holdover mode (if tuning
word history is valid) or free-run mode. The DPLL will exit holdover mode when the selected input becomes
valid.
Table 4. Manual Input Selection by Register Bits
DPLLx_REF_MAN_REG_SEL[2
:0] BITS
DPLLx_REF_MAN_SEL BIT
SELECTED INPUT
00b
0
IN0
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Table 4. Manual Input Selection by Register Bits (continued)
DPLLx_REF_MAN_REG_SEL[2
:0] BITS
DPLLx_REF_MAN_SEL BIT
SELECTED INPUT
01b
0
IN1
10b
0
IN2
11b
0
IN3
Table 5. Manual Input Selection by Hardware Pins
INSELx_[1:0] PINS
DPLLx_REF_MAN_SEL BIT
SELECTED INPUT
00b
1
IN0
01b
1
IN1
10b
1
IN2
11b
1
IN3
Each DPLL supports hitless switching through phase cancellation which restricts the rate of change of output
phase during a reference switchover event in accordance with Stratum 3/4E, Stratum 2/3E, and Synchronous
Ethernet EEC Option 1.
During hitless switching, the phase cancellation filter averages the input to find a common position and is
necessary to reduce the noise of input to obtain the true center. The switching scheme involves an inbuilt
interpolation algorithm that allows interpolation below 1-ps step size on the output phase perturbation. This
implementation allows minimal phase hit on the outputs when all inputs are synchronous to the same source. In
the case of the inputs derived in an asynchronous manner, the output phase smoothly tracks the new frequency
and phase with reduced transient. The hitless switching specification is valid for reference inputs that are
wander-free.
The hitless switching flowchart is shown in Figure 25.
Locked State
No
Lock Acquisition (Fastlock,
Phase Cancellation)
Reference Switching
= Manual?
Yes : Auto
Holdover
Reference Switching
= Automatic?
Yes : Auto
Revertive
Is LOS (frequency,
missing pulse or amplitude monitor)
of higher priority input = 1?
Yes : Auto
Non-revertive
Yes : Auto
Fallback
Yes
Is LOS (frequency,
missing pulse or amplitude monitor)
of current input = 1?
No
Is LOS (frequency,
missing pulse or amplitude monitor)
of current input = 1?
No
Yes
No
Holdover
(Refer to holdover flowchart)
Auto switch to higher
priority reference
Yes
Holdover
(Refer to holdover flowchart)
Exit Holdover
Lock Acquisition (Fastlock,
Phase Cancellation)
Figure 25. Hitless Switching Flowchart
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9.3.5 Hitless Switching
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9.3.6 Gapped Clock Support on Reference Inputs (INx_P/N)
Each DPLL supports locking to an input clock that has missing periods and is referred to as a gapped clock.
Gapping a clock severely increases its jitter, so the device provides the high input jitter tolerance and low loop
bandwidth necessary to generate a low-jitter periodic output clock. The resulting output will be a periodic nongapped clock with an average frequency of the input with its missing cycles. A valid gapped clock input must
have a minimum frequency of 10 MHz with a maximum of two missing cycles out of every 8. The fault monitors
can be configured to avoid triggering on any flags and achieve phase lock. Reference switchover between
gapped clocks may violate the hitless switching specification if the switch occurs during a gap in either input
clock.
9.3.7 Clock Monitoring, Status, and Interrupts
The following section describes the clock monitoring, status, and interrupt features.
9.3.7.1 Reference Monitoring
ADVANCE INFORMATION
All reference clock inputs are monitored for input qualification or validation for DPLL input selection. An input can
be selected if it is qualified or if it falls within the valid threshold for all enabled input monitoring blocks. The input
monitoring blocks include amplitude, a missing pulse, a runt pulse, or both, and frequency monitors. Additionally,
a validation timer sets the minimum time for all enabled input monitors to be clear of flags before an input is
qualified.
The enablement and valid threshold for all input monitors and validation timers are configurable per input through
the registers. The monitors and validation timers are optional to enable, but can be very useful to avoid selection
of an unreliable clock input. If a given monitor is not enabled, it will not trigger a flag and will be ignored. The
status flag of an enabled input monitor can be observed through status pin for any input (selected or nonselected), or through the corresponding interrupt register bit for the selected input of each DPLL. The valid status
of all inputs can also be read through a status register.
9.3.7.1.1 Amplitude Monitor
The amplitude monitor detects if the input meets or violates the amplitude-related thresholds for differential or
LVCMOS input modes. The differential input detector clears its flag when the input voltage swing is above the
minimum setting selected by the registers (200, 300, or 400 mVpp nominal). The LVCMOS input slew rate
detector clears its flag when its slew rate is faster than the fixed threshold on the clock edge selected by the
registers (rising edge only, falling edge only, or both edges). If either the differential or LVCMOS clock does not
meet the specified thresholds, the detector will set its flag to disqualify the input.
Below about 1 MHz, the differential input detector may signal a false flag; in that case, the input detector should
be disabled or bypassed. The LVCMOS input detector can be used for low-frequency clocks down to 1 Hz or 1
PPS.
9.3.7.1.2 Missing Pulse Monitor
The missing pulse monitor uses a window detector to validate input clock pulses that arrive within the nominal
clock period plus a programmable late window threshold (TLATE). When an input pulse arrives before TLATE, the
pulse is considered valid and the missing pulse flag will be cleared. When an input pulse does not arrive before
TLATE (due to missing or late pulse), the flag will be set immediately to disqualify the input.
TLATE should be typically set higher than the input's longest clock period (including periodic jitter), or higher than
the gap width for a gapped clock. The missing pulse monitor can act as a coarse frequency detector with faster
fault detection than the precision frequency monitor. The missing pulse monitor is supported for input frequencies
between 2 kHz and TBD MHz and should be disabled for any input outside this range.
9.3.7.1.3 Runt Pulse Monitor
The runt pulse monitor uses a window detector to validate input clock pulses that arrive within the nominal clock
period minus a programmable early window threshold (TEARLY). When an input pulse arrives after TEARLY, the
pulse is considered valid and the runt pulse flag will be cleared. When an early or runt input pulse arrives before
TEARLY, the monitor will set the flag immediately to disqualify the input.
26
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TEARLY should be typically set higher than the input's shortest clock period (including periodic jitter). The early
pulse monitor can act as a coarse frequency detector with faster fault detection than the precision frequency
monitor. The early pulse monitor is supported for input frequencies between 2 kHz and TBD MHz and should be
disabled for any input outside this range.
The missing pulse and runt pulse monitors operate from the same window detector block, and the status flags for
both monitors are logically OR-ed together. The OR-ed output flag can be observed through status pin for any
input, or through the MISSCLK interrupt register bit for the selected input of each DPLL.
The frequency monitor measures the frequency ppm offset for all input clocks relative to a "0-ppm" reference
clock, which can be selected from either the XO or TCXO input. The valid and invalid ppm frequency thresholds
are configurable through the registers. The monitor will clear the LOR_FREQ flag when the relative input
frequency error is less than the valid ppm threshold. Otherwise, it will set its flag when the relative input
frequency error is greater than the invalid ppm threshold. The ppm delta between the valid and invalid thresholds
provides hysteresis to prevent the LOR_FREQ flag from toggling when the input frequency offset is crossing
these thresholds or has high wander. A measurement averaging factor is also used in computing the frequency
threshold register settings. A higher averaging factor increases the delay to set or clear the LOR_FREQ flag to
allow more time for the input frequency to settle and can provide better frequency measurement resolution for an
input with high wander. Higher averaging also reduces the maximum frequency detector thresholds that can be
configured.
9.3.7.1.5 Reference Validation Timer
Each reference input has a dedicated validation timer. The validation timer sets the amount of time that a
reference must be clear of flags from all enabled input monitors before it is qualified and valid for selection. The
validation timer count and enable settings are register-configurable.
9.3.7.2 XO Input Monitoring
The XO input has an amplitude and frequency monitor for input qualification before it can be used to lock the
APLLs. The XO input amplitude monitor can be configured and operates the same as the reference input
amplitude detector. The XO loss-of-signal (LOS) status flags can be observed through status pin or interrupt
register bits. The XO detectors can be bypassed or ignored through register bits, so the input is always
considered to be valid by the PLL control state machines.
9.3.7.3 TCXO Input Monitoring
The TCXO input has an amplitude and frequency monitor for input qualification before it can be used to lock the
TCXO-DPLLs. The TCXO input amplitude monitor can be configured and operates the same as the reference
input's LVCMOS input slew rate detector. The TCXO loss-of-signal (LOS) status flags can be observed through
status pin or interrupt register bits. The TCXO detectors can be bypassed or ignored through register bits, so the
input is always considered to be valid by the PLL control state machines.
9.3.7.4 Loss of Lock (LOL)
The loss-of-lock (LOL) status is available for each APLL and DPLL. The APLLs are monitored for loss-offrequency lock only, and the REF-DPLLs are monitored for both loss-of-phase lock (LOPL) and loss-of-frequency
lock (LOFL). The DPLL lock and loss-of-lock thresholds for both LOPF and LOFL detectors are configurable
through the registers.
Each DPLL LOFL monitor will clear its flag when the DPLL frequency error relative the selected reference input
is less than the lock ppm threshold. Otherwise, it will set its flag when the DPLL frequency error is greater than
the unlock ppm threshold. The ppm delta between the lock and unlock thresholds provides hysteresis to prevent
the LOFL flag from toggling when the DPLL frequency error is crossing these thresholds. A measurement
averaging factor is also used in computing the lock and unlock threshold register settings. A higher averaging
factor increases the delay to set or clear the LOFL flag to allow more time for the DPLL frequency to acquire
lock. Higher averaging may be useful when locking to an input with high wander or when the DPLL is configured
with a narrow loop bandwidth. Note that higher averaging reduces the maximum frequency thresholds that can
be measured.
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9.3.7.1.4 Frequency Monitoring
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The LOL flags can be observed through status pins for all APLLs and DPLLs, as well as through the
corresponding interrupt register bits.
9.3.7.5 Tuning Word History
Each REF-DPLL domain has a tuning word history monitor block that determines the initial output frequency
accuracy upon entry into holdover. The tuning word can be updated from one of three sources depending on the
DPLL operating mode:
a. Locked Mode: From the output of the digital loop filter when locked
b. Holdover Mode: From the final output of the history monitor
c. Free Run Mode: From the free-run tuning word register (user defined)
When the history monitor is enabled and the DPLL is locked, it effectively averages the reference input frequency
by accumulating history from the digital loop filter output during a programmable averaging time (Tavg). Once the
input becomes invalid, the final tuning word value is stored to determine the initial holdover frequency accuracy.
Generally, a longer the Tavg time will produce a more accurate initial holdover frequency. The stability of 0-ppm
reference clock (XO or TCXO input) determines the long-term stability and accuracy of the holdover output
frequency.
ADVANCE INFORMATION
There is also a separate programmable delay timer (Tign) that can be set to ignore the history data that is
corrupted just prior to entry into holdover. The history data could be corrupted if a tuning word update occurs
while the input clock is failing and before it is detected by the input monitors. Both Tavg and Tign times are
programmable through HISTCNT and HISTDLY bits, respectively, and are related to the REF-TDC rate.
The tuning word history is initial cleared after a device hard reset or soft reset. The history monitor begins to
accumulate history once the DPLL locks to a new reference. The previous history will be cleared when a
switchover to a new reference occurs assuming the history persistence bit (HIST_HOLD) is not set. The history
can be manually cleared by asserting the history soft reset bit (HIST_SW_RST). If the history persistence bit is
set, the history monitor will not clear the previous history value during reference switchover, holdover exit, or
history soft reset. Whenever the tuning word is cleared, the history monitor waits for the first Tavg timer to expire
before storing the first tuning word value.
If the Tavg period is set very long (minutes or hours) to a more precise historical average frequency, it is possible
for a switchover or holdover event to occur before the first tuning word is stored and available for use. To
overcome this, there is an intermediate history update option (HIST_INTMD). If the history is reset, then the
intermediate average can be updated at intervals of Tavg/2K , where K = HIST_INTMD to 0, during the first Tavg
period only. If HIST_INTMD = 0, there is no intermediate updates and the first average is stored after the first
Tavg period. However, if HIST_INTMD = 4, then four intermediate averages are taken at Tavg/16, Tavg/8,
Tavg/4, and Tavg/2, as well as at Tavg. After the first Tavg period, all subsequent history updates occur at the
Tavg period.
When the history monitor is disabled, the user-programmable, free-run tuning word value (TUNING_FREE_RUN)
determines the initial holdover output frequency accuracy.
9.3.7.6 Status Outputs
STATUS[1:0] and GPIO[6:5] pins can be used to output various internal status signals or interrupt flag for device
diagnostic or debug purposes. The status signal, output driver type, and output polarity settings are configurable
by registers.
The following lists the available status outputs (active high):
• XO Input Loss of Signal (LOS)
• TCXO Input Loss of Signal (LOS)
• PLLy Lock Detected (LOLb)
• PLLy VCO Calibration Active
• PLLy N Divider, div-by-2
• EEPROM Active
• Interrupt (INTR)
• PLLy VCO div-by-96
• REFx monitor divider output, div-by-2
28
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•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
SNAS724 – FEBRUARY 2018
REFx amplitude monitor fault
REFx frequency monitor fault
REFx missing clock monitor fault
REFx ppm timer active
REFx validation timer active
REFx phase validation monitor fault
DPLLy R Divider, div-by-2
DPLLy REF N Divider, div-by-2
DPLL TCXO M Divider, div-by-2
DPLLy TCXO N Divider, div-by-2
DPLLy REF HS Clock, div-by-2
DPLLy TCXO HS Clock, div-by-2
DPLLy REFx selected
DPLLy Holdover active
DPLLy Reference switchover event
DPLLy R Divider Reset
DPLLy Tuning history update
DPLLy Fast lock active
DPLLy Fast lock done
DPLLy Loss of Lock
DPLLy Phase Cancellation done
DPLLy Loop filter saturation
DPLLy lock ppm timer active
DPLLy REF N Divider Reset
9.3.7.7 Interrupt
Any of the 4 status pins can be configured as a device interrupt output pin. The interrupt configuration is set
through registers. When the interrupt is enabled, the interrupt flag can be triggered from any combination of
interrupt status indicators, including LOS for the XO, TCXO, and DPLL-selected inputs, LOL for each DPLL and
APLL, and holdover and switchover events for each DPLL. Any status indicator can be masked so it will not
trigger the interrupt pin. Any unmasked status indicator can have its polarity inverted before it is combined at the
interrupt OR/AND gate and output to the status pin.
9.3.8 PLL Core
9.3.8.1 PLL Core Block Diagram
Figure 26 shows a functional block diagram of a single PLL core. The LMK05028 has two independent PLL
cores implemented identically, except for the VCO frequency ranges (shown below). The VCO frequency ranges
do not overlap to help minimize cross-coupling between the two PLL domains.
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VCO1 Freq = 4.8 - 5.4 GHz
VCO2 Freq = 5.5 - 6.2 GHz
1x, 2x
From XO
P1 Div
PFD
To OUT
Divs
APLL BW
~ 400 kHz
P2 Div
/48
FB Div
PLL N Div
™û fractional
Feedback CLK to
other DPLL REF/
TCXO input muxes
APLL
From TCXO Mux
TCXO
TDC
TCXO Loop BW
ADVANCE INFORMATION
TCXO FB Div
™û fractional
TCXO FB
Pre Div
TCXO-DPLL
From Input Mux
REF
TDC
REF Loop BW
REF FB Div
™û fractional
REF FB
Pre Div
REF-DPLL
Figure 26. PLL Core Block Diagram
9.3.8.2 PLL Frequency Relationships
The following equations provide the frequency relationships for closed-loop operation according to the loop mode
configured on each PLL core.
• To operate in free-run mode (APLL only), the condition in Equation 1 must be met.
• To operate in 3-loop mode (REF-DPLL, TCXO-DPLL, and APLL), the conditions in Equation 1, Equation 2,
Equation 3, and Equation 4 must be met.
• To operate in 2-loop mode (REF-DPLL and APLL), the conditions in Equation 1, Equation 3, and Equation 4
must be met.
• To operate in 2-loop mode (TCXO-DPLL and APLL), the conditions in Equation 1 and Equation 2 must be
met.
Equation 1 relates to the APLL.
FVCO = FXO × DXO × (INTAPLL + NUMAPLL/ DENAPLL)
where
•
•
•
•
•
30
FVCO: APLL/VCO frequency
FXO: Crystal Oscillator (XO) input frequency
DXO: APLL input doubler, 1 = disabled and 2 = enabled
INTAPLL: APLL feedback N divider integer value (9 bits, 1 to 29-1)
NUMAPLL: APLL feedback N divider numerator value (40 bits, 0 to 240-1)
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•
DENAPLL: APLL feedback N divider denominator value (40 bits, 1 to 240)
(1)
Equation 2 relates to the TCXO-DPLL.
FVCO = (FTCXO × DTCXO / MDIV) × P1 × PRTCXO-DPLL × (INTTCXO-DPLL + NUMTCXO-DPLL/ DENTCXO-DPLL)
where
•
•
•
•
•
•
•
•
•
FVCO: APLL/VCO frequency
FTCXO: TCXO/OCXO input frequency
DTCXO: TCXO input doubler, 1 = disabled and 2 = enabled
M: TCXO input divider (5 bits, 1 to 32)
P1 = PLL primary post-divider (4 to 9, 11, 13)
PRTCXO-DPLL: TCXO-DPLL feedback prescaler divider (2 to 17)
INTTCXO-DPLL: TCXO-DPLL feedback divider integer value (30 bits, 1 to 230-1)
NUMTCXO-DPLL: TCXO-DPLL feedback divider numerator value (40 bits, 0 to 240-1)
DENTCXO-DPLL: TCXO-DPLL feedback divider denominator value (fixed, 240)
(2)
Equation 3 relates to the REF-DPLL.
where
•
•
•
•
•
•
•
FVCO: APLL/VCO frequency
FINx: Reference input (0 to 3) or VCO loopback frequency (IN4 = VCO2, IN5 for VCO1)
Rx: Reference input divider (16 bits, 1 to 216-1) (x = 0 to 5)
PRREF-DPLL: REF-DPLL feedback prescaler divider (2 to 17)
INTREF-DPLL: REF-DPLL feedback divider integer value (30 bits, 1 to 230-1)
NUMREF-DPLL: TCXO-DPLL feedback divider numerator value (40 bits, 0 to 0 to 240-1)
DENREF-DPLL: REF-DPLL feedback divider denominator value (40 bits, 1 to 240)
(3)
Equation 4 relates to any reference inputs assigned to a DPLL to ensure a constant REF-TDC rate for proper
input switchover.
FREF-TDC = FIN0/R0 = FIN1/R1 = FIN2/R2 = FIN3/R3
(4)
Equation 5, Equation 6, and Equation 7 relate to the output frequency according to the source selected by the
output channel mux (CH_x_MUX).
FOUTx = FXO or FREF when XO or Ref Bypass is selected (OUT0 or OUT1 only)
FOUTx = FVCO / (Pn × DIVAOUTx) when PLL post-divider is selected
FOUTx = FVCO / (Pn × DIVAOUTx × DIVBOUTx) when PLL post-divider is selected (OUT0 or OUT7 only)
(5)
(6)
where
•
•
•
•
FREF: TCXO, DPLL1 Ref, or DPLL2 Ref input frequency selected by REF_BYPASS_MUX
Pn: P1 or P2 post divider value for PLL1 or PLL2
DIVAOUTx: Output divider value (20 bits, 1 to 220-1)
DIVBOUTx: Output divider MSB value (11 bits, 1 to 211-1)
(7)
9.3.8.3 APLL XO Doubler
Each APLL has a frequency doubler on the XO input that can be enabled (default) to double the APLL PFD rate
for improved phase noise and jitter performance within the APLL loop bandwidth.
9.3.8.4 APLL Phase Frequency Detector (PFD)
The PFD frequency of each APLL can operate from 10 MHz to 200 MHz, but the APLL performance is optimized
for PFD frequencies at 96 MHz or higher.
9.3.8.5 APLL Charge Pump
Each PLL has programmable charge pump settings of 1.6 mA, 3.2 mA, 4.8 mA, or 6.4 mA.
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FVCO = (FINx / Rx) × P1 × PRREF-DPLL × (INTREF-DPLL + NUMREF-DPLL/ DENREF-DPLL)
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9.3.8.6 APLL Loop Filter
Each APLL supports programmable loop bandwidth from 100 kHz to 1 MHz. The analog loop filter components,
R2, C1, R3, C3, R4, and C4 can be configured through registers. C2 for each APLL is an external 0.1-µF
capacitor on the LF1 or LF2 pins. Because each APLL operates in fractional mode during normal operation, the
charge pump non-linearity should be reduced by configuring the bleed resistor. Figure 27 shows the APLL loop
filter structure between the PFD/charge pump output and VCO input.
C2
LF1 / LF2
LMK05028
R2
R3
R4
From PFD /
>>
Charge Pump
>>
ADVANCE INFORMATION
C3
C1
C4
Copyright © 2018, Texas Instruments Incorporated
Figure 27. Loop Filter Structure of Each APLL
9.3.8.7 APLL Fractional Feedback Divider (NDIV)
The fractional feedback divider (NDIV) of each APLL includes a 9-b integer portion (INT), 40-b numerator portion
(NUM), and 40-b denominator portion (DEN). The total NDIV value is: NDIV = INT + NUM / DEN. The NDIV
output sets the APLL PFD frequency, which should be equal to the XO doubler output frequency.
9.3.8.8 REF-DPLL Reference Divider (RDIV)
The reference clock input paths to each REF-DPLL features a 16-b reference divider (RDIV) for each clock input
(IN0 to IN3). The output of each RDIV sets the frequencies to the reference input mux and the TDC rate of the
REF-DPLL. There are also two additional RDIV for the internal VCO loopback clocks (IN4 and IN5) which could
be used in cascaded DPLL configurations. IN4 refers to the VCO1 loopback clock to DPLL2 reference input, and
IN5 refers to the VCO2 loopback clock to DPLL1 reference input.
9.3.8.9 TCXO Input Doubler (D) and Divider (MDIV)
The TCXO input features a frequency doubler followed by a 5-b divider (MDIV). The MDIV output is sent to both
TCXO-DPLLs and sets the TDC rate for both TCXO-DPLLs if used in the configuration.
9.3.8.10 REF-DPLL and TCXO-DPLL Time-to-Digital Converter (TDC)
Each REF-DPLL and TCXO-DPLL TDC operates up 30 MHz. The TDC resolution is fine enough to achieve inband phase noise of –102 dBc/Hz at 100-Hz offset for a 122.88-MHz output. The REF-DPLL TDC rate is: REFTDC = FINx / RDIVx. . The TCXO-DPLL TDC rate is: TCXO-TDC = FTCXO × D / MDIV, where D = 1 (doubler
disabled) or 2 (enabled).
9.3.8.11 REF-DPLL and TCXO-DPLL Loop Filter
Each REF-DPLL and TCXO-DPLL supports programmable loop bandwidth from 10 mHz to 4 kHz and can
achieve jitter peaking below 0.1 dB. The jitter transfer characteristic of each DPLL attenuates the noise of its
respective input clock at –60 dB/decade slope above its configured loop bandwidth.
In 2-loop mode with the REF-DPLL , the TCXO-DPLL is bypassed and the REF-DPLL loop filter output directly
modulates the APLL NDIV MASH engine to steer the APLL VCO into lock with the selected REF-DPLL input.
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In 2-loop mode with the TCXO-DPLL, the REF-DPLL is not used and the TCXO-DPLL loop filter output directly
modulates the APLL NDIV MASH engine to steer the APLL VCO into lock with the TCXO input.
In 3-loop mode, the REF-DPLL loop filter output modulates the TCXO-DPLL FB_DIV MASH engine, and the
TCXO-DPLL loop filter output correspondingly modulates the APLL NDIV MASH engine to steer the APLL VCO
into lock with the selected REF-DPLL input.
9.3.8.12 REF-DPLL and TCXO-DPLL Feedback Dividers (FB_PRE_DIV, FB_DIV)
The feedback path of each REF-DPLL and TCXO-DPLL has an feedback prescaler (FB_PRE_DIV) followed by a
fractional feedback divider (FB_DIV). The FB_PRE_DIV divides its PLL primary post divider (P1) by a
programmable value from 2 to 17 and outputs the prescaler clock to the FB_DIV. The FB_DIV of each REFDPLL and TCXO-DPLL includes a 30-b integer portion (INT), 40-b numerator portion (NUM), and 40-b
denominator portion (DEN). The total FB_DIV value is: FB_DIV = INT + NUM / DEN. The FB_DIV output sets the
TDC rate to the respective DPLL.
Each PLL has a primary (P1) and secondary (P2) VCO post divider for more flexible clock frequency generation.
Each post divider supports divide by 4 to 9, 11, or 13 from the VCO frequency. Each post divider frequency for
PLL1 and PLL2 is distributed to the output block where it can be selected by any output channel mux. The P1
post divider output for each PLL is also fed-back to their respective REF-DPLL and TCXO-DPLL feedback divider
paths to close the loops.
Once the P1 divider and DPLL fractional feedback dividers have been configured for closed-loop operation, the
P1 divider should not be changed dynamically without also changing the DPLL feedback dividers to maintain the
original TDC rates. A software PLL reset is required after changing any PLL post divider value.
9.3.8.14 VCO Calibration
Each PLL's VCO must be calibrated to ensure that the clock outputs deliver optimal phase noise performance.
Fundamentally, a VCO calibration establishes an optimal operating point within the tuning range of the VCO.
While transparent to the user, the LMK05028 performs the following steps during a VCO calibration sequence:
1. Normal Operation – When the LMK05028 is in normal (operational) mode, the state of both the power-down
pin (PDN) is high.
2. Entering the reset state - If the user wishes to restore all device defaults and initiate a VCO calibration
sequence, then the host system must place the device in reset through the PDN pin, or through
programming, or by removing and restoring device power. Pulling the PDN pin low or through programming
places the device in the reset state.
3. Exiting the reset state – The device calibrates the VCO either by exiting the device reset state or through
the device reset command initiated through the host interface. Exiting the reset state occurs automatically
after power is applied, the system restores the state of the PDN, or both, or through programming from the
low to high state. Exiting the reset state using this method causes the device defaults to be loaded or
reloaded into the device register bank. Invoking a device reset through the register bit does not restore
device defaults; rather, the device retains settings related to the current clock frequency plan. Using this
method allows for a VCO calibration for a frequency plan other than the default state (that is, the device
calibrates the VCO based on the settings contained within the registers). The nominal state of this bit is low.
Writing this bit to a high state and then returning it to the low state invokes a device reset without restoring
device defaults.
4. Device stabilization – After exiting the reset state as described in Step 3, the device monitors internal
voltages and starts a reset timer. Only after internal voltages are at the correct level and the reset time has
expired will the device initiate a VCO calibration. This ensures that the device power supplies and phase
locked loops have stabilized prior to calibrating the VCO.
5. VCO Calibration – The LMK05028 calibrates the VCO. During the calibration routine, the device holds all
outputs in reset so that they generate no spurious clock signals.
9.3.9 Output Channel Muxes
Each of the 6 output channels has an output mux. The output muxes for outputs 2 to 7 can select between the
PLL1 and PLL2 post divider clocks. The output muxes for outputs 0 and 1 can select between PLL1 and PLL2
post divider clocks, XO input, or one of the reference bypass mux inputs.
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9.3.8.13 PLL VCO Post Dividers (P1, P2)
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9.3.9.1 Reference Bypass Mux
The reference bypass mux can select between the selected DPLL1 input, selected DPLL2 input, or TCXO input.
These PLL bypass paths are intended for diagnostic purposes, and are not optimized for lowest additive phase
noise or jitter.
9.3.10 Output Divider
Each of the 6 output channels has an output divider after the channel mux. Outputs 2 and 3 share an output
divider, as do outputs 4 and 5. Outputs 0, 1, 6, and 7 have their own individual output dividers. The output divider
is used to generate the final output clock frequency from the source selected by the output mux. Each output
divider is powered from the same VDDO supply used for the clock output drivers.
Outputs 1 to 6 have 20-bit dividers that can support output frequencies from 2 kHz to 750 MHz. It is possible to
configure the divider for higher clock frequencies, but the output voltage swing may fall out of specification due to
signal attenuation depending on the configured output driver.
Outputs 0 and 7 each have cascaded 11-bit and 20-bit output dividers that can support output frequencies from 1
Hz (1 PPS) to 750 MHz. In this case, the total output divide value is the product of the cascaded divider values.
9.3.11 Clock Outputs
ADVANCE INFORMATION
Each output can be configured through registers as Differential AC-coupled (AC-LVDS/CML/LVPECL), HCSL, or
2.5-V / 1.8-V LVCMOS clocks. Outputs 2 and 3 share an output supply (VDDO_23), as do outputs 4 and 5
(VDDO_45). Outputs 0, 1, 2, and 3 have individual output supplies (VDDO_0, VDDO_1, VDDO_6, and
VDDO_7). Each output supply can be independently set to 1.8 V, 2.5 V, or 3.3 V for Differential or HCSL driver
modes, or 1.8 V or 2.5 V for LVCMOS mode. Each channel has a dedicated LDO regulator to provide high power
supply noise rejection (PSNR) and minimize supply-noise induced jitter and spurs.
The differential output stage uses a switched-current mode driver shown in . A programmable tail current of 4, 6,
or 8 mA is used to achieve typical VOD swings of 400 mV (AC-LVDS), 600 mV (AC-CML), or 800 mV (ACLVPECL) across a 100-Ω differential load. Because this output driver is ground-referenced (VOL near GND) and
has low common-mode voltage, the output clock jitter performance or other AC or DC specifications are
insensitive of the VDDO voltage. The differential output can be externally AC-coupled to LVDS, CML, or LVPECL
receivers with internal or external termination and biasing. The differential drivers are internally biased and do not
need any external pullup or pulldown resistors.
1.8 V, 2.5 V, 3.3 V
LDO
4 mA
P
P
N
N
I1
Output Current can be programmed to
4 mA, 6 mA, or 8 mA
(I1+I2)
IN
OUT
INb
0, 2, or 4 mA
P
P
N
N
I2
OUTb
Figure 28. Structure of AC-LVDS, AC-CML, AC-LVPECL Differential Output Stage
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The HCSL output driver is open-drain type and can be DC coupled to HCSL receivers. The HCSL output has
programmable 50-Ω source termination to ground internally. If the internal termination is disabled, the HCSL
output should have external 50-Ω termination to ground at either the source or load side.
The LVCMOS outputs on each side (P and N) can be configured individually to be complementary or in-phase,
or can be disabled (HiZ or static low). 1.8-V or 2.5-V LVCMOS outputs can be configured using VDDO of 1.8 V
or 2.5 V, respectively.
Figure 29 and Figure 34 show recommendations for interfacing between clock outputs and LVCMOS, LVPECL,
LVDS, CML, and HCSL receivers, respectively.
NOTE
If interfacing 2.5-V LVCMOS high-speed clock outputs with a 3.3-V LVCMOS receiver is
desired, use a level-shifter like LSF0101 to convert the 2.5-V LVCMOS signal to a 3.3-V
LVCMOS signal.
LVCMOS
ADVANCE INFORMATION
2.5 V LVCMOS
Receiver
LMK05028
Copyright © 2018, Texas Instruments Incorporated
Figure 29. Interfacing LMK05028’s 2.5-V LVCMOS Output With 2.5-V LVCMOS Receiver
VrefB = 3.3 V
VrefA = 2.5 V
LVCMOS
3.3 V LVCMOS
Receiver
LSF0101
LMK05028
Copyright © 2018, Texas Instruments Incorporated
Figure 30. Interfacing LMK05028’s 2.5-V LVCMOS Output With 3.3-V LVCMOS Receiver
LMK05028
AC-LVDS
100
LVDS
Receiver
Copyright © 2018, Texas Instruments Incorporated
Figure 31. Interfacing LMK05028’s AC-LVDS Output With LVDS Receiver
50
LMK05028
AC-CML
CML
Receiver
50
Copyright © 2018, Texas Instruments Incorporated
Figure 32. Interfacing LMK05028’s AC-CML Output With CML Receiver
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LMK05028
AC-LVPECL
LVPECL Receiver
50
50
VDD_IN - 2
Copyright © 2018, Texas Instruments Incorporated
Figure 33. Interfacing LMK05028’s AC-LVPECL Output With LVPECL Receiver
33
LMK05028
(optional)
HCSL
Receiver
HCSL
ADVANCE INFORMATION
33
(optional)
50
50
Copyright © 2018, Texas Instruments Incorporated
Figure 34. Interfacing LMK05028’s Output With HCSL Receiver
9.3.12 Output Synchronization
Each output divider and PLL post divider bank can be synchronized using the SYNC assertion signal for any
divider that has their corresponding SYNC-enable bit set. The SYNC assertion signal can come from the external
GPIO0 pin (active low) or the SYNC_SW register bit (active high). When SYNC is asserted, the SYNC-enabled
dividers held are reset and clock outputs are muted. When SYNC is de-asserted, the clock outputs will start up
with their initial phases synchronized or aligned. SYNC can also be used to mute any SYNC-enabled outputs to
prevent output clocks from being distributed to down-stream devices, such as DSPs or FPGAs, until they are
configured and ready to accept the incoming clock.
Table 6. Output Channel Synchronization
GPIO0 PIN
OUTPUT DIVIDER AND DRIVER STATE
0
Output driver(s) muted and output divider(s) reset
1
Normal output driver/divider operation as configured
9.4 Device Functional Modes
After device POR and initialization, each PLL core operates in one of the following modes depending on the
clock input qualification and DPLL lock status:
9.4.1 Free-Run Mode
After device POR and initialization, the APLL in each PLL core locks to the qualified XO and no DPLL lock
acquisition or synchronization has been initiated. The accuracy of the output clock is equal to the accuracy of the
XO input clock. Neither the DPLL reference input nor TCXO/OCXO input are qualified yet. After the TCXO input
is qualified, the TCXO-DPLL in each PLL core locks to it so the accuracy of the output clock is equal to the
accuracy of the TCXO input clock. The reference input remains unqualified during free-run mode.
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Device Functional Modes (continued)
9.4.2 Lock Acquisition Mode
Each DPLL constantly monitors its assigned inputs for a valid clock. When at least one valid clock is detected,
the DPLL will exit free-run or holdover mode and initiate lock acquisition. The LMK05028 supports a fast lock
feature where the loop bandwidth is set to wider than the nominal setting the during lock acquisition to reduce the
lock time. Once lock acquisition is done, the loop bandwidth is set to its nominal loop bandwidth setting.
9.4.3 Locked Mode
When a DPLL has completed lock acquisition, the PLL output clocks will be frequency and phase locked to its
selected input clock. While the DPLL is locked, the output clocks will not be affected by frequency drift on the XO
input or the TCXO input if the TCXO-DPLL is configured. Each DPLL has a programmable frequency and phase
lock detector thresholds to indicate DPLL lock status, which can be observed through status pin or interrupt
register bits.
If a tuning word history exists, the holdover frequency is the average frequency just prior to entry of the holdover.
If no tuning word history exists, the holdover frequency is determined by the free-run tuning word register (user
programmable). The initial holdover frequency accuracy depends on the loop bandwidth of the REF-DPLL and
the time elapsed to compute a tuning word history. In general, the longer the historical average, the more
accurate the initial holdover frequency (assuming the 0-ppm reference clock is drift-free). The stability of 0-ppm
reference clock (XO or TCXO input) determines the long-term stability and accuracy of the holdover output
frequency. Holdover mode flow chart is shown in Figure 35.
Locked State
Is LOS (frequency,
missing pulse or amplitude monitor)
of selected input = 1?
No
Yes
Yes
No
Is holdover history valid?
Lock Acquisition (Fastlock, Phase
Cancellation)
No
Holdover mode (locked to average tuning
word from history)
Free-run mode
Is DCO mode enabled?
Is DCO mode enabled?
No
Yes
Follow increment/decrement as per control pin
settings for each TCXO-DPLL
Yes
Yes
Follow increment/decrement as per control pin
settings for each TCXO-DPLL
Is LOS (frequency,
missing pulse or amplitude monitor)
of selected input = 1?
Yes
Is LOS (frequency,
missing pulse or amplitude monitor)
of selected input = 1?
No
No
Figure 35. LMK05028 Holdover Flowchart
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9.4.4 Holdover Mode
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Device Functional Modes (continued)
9.4.5 Digitally-Controlled Oscillator (DCO) Mode
To support IEEE 1588 slave clock and other clock steering applications, each DPLL supports DCO mode to allow
precise output clock frequency adjustment of less than 1 ppt per step. DCO mode can be enabled by register
(DPLLy_FDEV_EN bit) on either REF-DPLL or TCXO-DPLL loop when operating in locked mode. The DCO
frequency step size can be programmed through the frequency deviation register (DPLLy_FDEV bits), and the
DCO frequency increment or decrement can be updated through software or pin control. DCO updates through
software control are always available through I2C or SPI register write command (DPLLy_FDEV_REG_UPDATE
bit). Pin control must be enabled through registers. When pin control is enabled (GPIO[3:6]_FDEV_EN bits), the
GPIO3 and GPIO4 pins allow DPLL1 DCO frequency increment (FINC) and decrement (FDEC) updates, and the
GPIO5 and GPIO6 pins allow DPLL2 DCO FINC and FDEC updates, respectively. A rising edge on the FINC pin
will increment the PLL output frequency by the programmed step size, while a rising edge on the FDEC pin will
decrement it. The DCO update rate should be limited to 1 MHz or less.
9.4.5.1 DCO Frequency Step Size
Equation 8 shows the formula to compute the DPLLy_FDEV register value required to meet the specified DCO
frequency step size (in ppb) when DCO mode is enabled for the REF-DPLL (when
DPLLy_DCO_SEL_REF_TCXOB = 1).
ADVANCE INFORMATION
DPLLy_FDEV = (Reqd_ppb / 1E9) × DENREF-DPLL / (FINx / Rx) × FVCO / (P1 × PRREF-DPLL)
where
•
•
•
•
•
•
•
•
DPLLy_FDEV: Frequency deviation value (38 bits, 0 to 238-1)
Reqd_ppb: Required DCO frequency step size (in ppb)
DENREF-DPLL: REF-DPLL feedback divider denominator value (40 bits, 1 to 1 to 240)
FINx: Reference input frequency (x = 0, 1, 2, 3)
Rx: Reference input divider (16 bits, 1 to 1 to 216-1) (x = 0, 1, 2, 3)
FVCO: APLL/VCO frequency
P1 = PLL primary post-divider (4 to 9, 11, 13)
PRREF-DPLL: REF-DPLL feedback prescaler divider (2 to 17)
(8)
Equation 9 shows the formula to compute the DPLLy_FDEV register value required to meet the specified DCO
frequency step size (in ppb) when DCO mode is enabled for the TCXO-DPLL (when
DPLLy_DCO_SEL_REF_TCXOB = 0).
DPLLy_FDEV = (Reqd_ppb / 1E9) x DENTCXO-DPLL) / (FTCXO / M) x FVCO / (P1 x PRTCXO-DPLL)
where
•
•
•
•
•
Reqd_ppb: Required DCO frequency step size (in ppb)
DENTCXO-DPLL: TCXO-DPLL feedback divider denominator value (fixed, 240)
FTCXO: TCXO/OCXO input frequency
M: TCXO/OCXO input divider (5 bits, 1 to 32)
PRTCXO-DPLL: TCXO-DPLL feedback prescaler divider (2 to 17)
(9)
9.4.5.2 Direct-Write DCO Mode
An alternate method to update the DCO frequency is by directly writing the REF-DPLL or TCXO-DPLL feedback
divider numerator (NUM) register for the corresponding DPLL through I2C or SPI write command.
9.5 Programming
The LMK05028 can
HW_SW_CTRL pin:
• HW_SW_CTRL =
• HW_SW_CTRL =
• HW_SW_CTRL =
start up in one of three modes depending on the 3-level input level sampled on the
0: EEPROM + I2C Mode (Soft pin mode)
F: EEPROM + SPI Mode (Soft pin mode)
1: ROM + I2C Mode (Hard pin mode)
The selected device start-up mode determines the following:
• The memory bank (EEPROM or ROM) used to initialize the registers to configure all device blocks.
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Programming (continued)
• The serial interface (I2C or SPI) used for register access.
• The logic pin functionality for control and status.
The I2C or SPI interface allows register access to configure the device after start-up and monitors its status. The
register map configurations are the same for I2C and SPI.
Figure 36 shows the device start-up mode configurations. Table 2 shows the logic pin functions used to enter
and operate in each device mode.
Power-on Internal Reset
Pulse or PDN Pin
0
1
Sample HW_SW_CTRL
Hard pin programming mode
I2C is still enabled, LSB of I2C
address is 00
GPIO[6:5] and GPIO[2:0] are
2-state; GPIO[4:3] are 3-state
Float
Soft pin programming mode
I2C Enabled. LSB of I2C address is set
by GPIO[2:1]. GPIO[0] is repurposed as
SYNCN pin for output synchronization.
Soft pin programming mode
SPI Enabled. GPIO[1] is repurposed as SCS.
GPIO[2] is repurposed as SDO for data
read and GPIO[0] is repurposed as SYNCN
pin for output synchronization.
Sample GPIO[4:0] for selecting 1 of 32
pre-defined ROM settings. GPIO[6:5]
are repurposed as devide status
outputs
GPIO[4:3] provides frequency increment/decrement for
DPLL1 and GPIO[6:5] can be programmed as STATUS
outputs or set as frequency increment/decrement for
DPLL2.
User can operate from EEPROM loaded configurations or
reprogram the device register via I2C
Save desired configuration
into the EEPROM page
Figure 36. LMK05028 Programming Flow
9.5.1 Interface and Control
The system host (MCU, FPGA,) can use either I2C or SPI to access the register, SRAM, and EEPROM maps.
The register and EEPROM map configurations are the same for I2C and SPI. The LMK05028 device blocks can
be initially configured, controlled, and monitored through registers during normal operation (not when the PDN is
low). The host can also control and monitor certain device parameters directly through the external logic control
and status pins.
In the absence of a host, the LMK05028 can self-start from its on-chip EEPROM or ROM page depending on the
state of HW_SW_CTRL pin. The EEPROM or ROM page is used to initialize the registers upon device POR. The
EEPROM can be programmed and read-back through the register interface using I2C or SPI. The contents of
ROM are fixed in hardware and cannot be modified.
Within the device registers, there are certain bits that have read or write access. Other bits are read-only (an
attempt to write to a read-only bit will not change the state of the bit). Certain device registers and bits are
reserved and should not be modified to avoid potential mis-operation of the device. Figure 37 shows the interface
and control blocks within LMK05028 and the arrows refer to read and write access for the different embedded
memories (SRAM, EEPROM, and ROM).
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ADVANCE INFORMATION
GPIO[4:0] are 2-state
GPIO[6:5] and GPIO[2:0] are
2-state; GPIO[4:3] are 3-state
LMK05028
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Programming (continued)
ROM (hard pin mode)
1 of 32 images
Reg89
Reg89
7
6
5
4
3
2
1
0
Reg89
7
6
5
4
3
2
1
0
Reg88Reg89
7 Reg896
5
4
3
2
1
0
Reg88
76Reg8965
54
43
32
21
10
0
7
Reg88
76
65
54
43
32
21
10
0
7 Reg88
7
6
5
4
3
2
1
0
Reg89
Reg87 7 Reg886Reg895
4
3
2
1
0
Reg87
7
6
5
4
3
2
10
0
76Reg886Reg89
54
43
32
21
10
7
5
7
6
5
4
3
2
10
0
7
6
5
4
3
2
1
Reg87
7
6Reg88Reg89
5
4
3
2
1
0
7
6
54
4
32
2
10
0
7 Reg88
6Reg89
5
3
1
Reg86Reg87
7
5
4
3
2
1
0
7Reg876
5 Reg896
4
3
2
1
0
Reg86
7
6
5
4
3
2
1
01
Reg88
7
6
5
4
3
2
1
0
7
6Reg87 5
74
63
52
41
30
21
0
76Reg88
6Reg89
56
45
34
23
01
Reg86
76
5
4
3
2
1
0
7Reg86
5
4
3
2
1
0
7
2
0
76
6Reg89
54
43
32
21
10
0
Reg87
7Reg87
5
Reg88
76
65
54
43
32
21
10
0
7
7Reg866
5 Reg88
4Reg89
3
2
1
0
7
5
4
3
2
1
0
76
65
56
43
34
21
12
01
7Reg86
4Reg896
2
0
Reg87
7
5
3
0
76
6Reg88
5
45
3
23
1
01
7
56Reg88
45
34
23
12
01
Reg87
76
6
54
4
32
2
10
0
7
Reg3
7
0
Reg86
7Reg866Reg87
5
45
23
01
76
63
54
41
32
210
10
0
76
54
32
Reg3
7Reg87
Reg88
7
6
3
7
6
5
4
3
2
1
0
75
64
56Reg88
452
341
230
12
01
Reg3
0
7 Reg3 6 Reg86
5 76
4
3
2
1
0
7Reg86
5
4
3
2
1
0
Reg87 76
654
543
432
321
210
10
0
Reg2 7
7 5 76Reg87
5
6
4
3
2
1
0
7
6
5
4
3
2
1
0
10
0
Reg2 Reg3
7Reg86
76Reg3 65 Reg86
54 76Reg87
43 65632 54521 43410 3230 212
7
7Reg87
1
0
Reg2
1
0
76
65 7 54 6 43 5 32 4 21 3 10 2 0
7
Reg3
10
0
7Reg86
7 Reg3 6 Reg86
5 76 4 65 3 54 2 43 1 32 0 21
Reg1 Reg2
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Reg2
7
6
5
4
3
2
1
0
Reg1 7
654 Reg86
543
43
32
21
10
0
7
6Reg276Reg3
5
1
0
76Reg3
654 7Reg86
53 6 2
432 5 1
321 4 0
210 3 10 2 0
Reg1
76
7
5
7
65 745
Reg2
0
7
67
4 6 434 5 323 4 212 3 101 2 0 0 1
Reg 0 Reg1
7 Reg1 6Reg2 Reg3
5 Reg3 6
4
3
75
6 2
5 1
4 0
3
2
1
0
Reg 0
7
6
5
4
3
2
1
0
76Reg1 6Reg2
54
43
3
21
1
0
7
5
7
6
52
4
30
2
10
0
76Reg2
6Reg3
56
45
34
23
12
Reg
0 76
54
45
32
23
10
01
7Reg
5
3
1
7
10
0
7
6Reg3
43
21
0 Reg1
7
67
56
45
23
01
7
6
54
4
32
2
10
0
7Reg 06Reg1 Reg2
5
4Reg3
36
25
14
03
7
2
1
0
76Reg1 6Reg2
5
4
3
2
1
0
7Reg 0
5
4
3
2
1
0
6Reg3
54
43
32
21
10
0
76Reg176Reg2
5
7
5
45
34
23
12
01
76
65
54
43
32
210
10
0
Reg
0 76Reg176Reg2
7Reg
56
45
23
01
76
63
54
41
32
210
10
0
7
54
32
07
Reg2
7
6
5
4
3
2
1
0
7Reg 06Reg1
45
34
23
12
01
76Reg156Reg2
0
7Reg 0
45
3
23
1
01
765
6
543
4
321
2
10
0
76Reg15
7
4
2
0
765
654
543
432
321
210
10
0
Reg
0 76
7Reg
0 Reg1
7
6
5
4
3
2
1
0
7Reg 06Reg1 5
4
3
2
1
0
76
65
54
43
32
21
10
0
7Reg 0
76
65
54
43
32
21
10
0
7
Reg
0 6
7Reg
5
4
3
2
1
0
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
STATUS0
ADVANCE INFORMATION
STATUS1
PDN
GPIO6
Control/
Status Pins
Device Registers
GPIO5
GPIO4
Reg200
7
Reg199
7
Reg29
7
Reg28
7
Device
Control
And
Status
GPIO3
GPIO2
GPIO1
I2C/SPI
Port
Reg3
7
Reg2
7
Reg1
7
Reg 0
7
GPIO0
SCL
SDA
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Device
Hardware
HW_SW_CTRL
Reg200
7
Reg199
7
Reg29
7
Reg28
7
Reg3
7
Reg2
7
Reg1
7
Reg 0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Reg200
7
Reg199
7
Reg29
7
Reg28
7
Reg3
7
Reg2
7
Reg1
7
Reg 0
7
SRAM (soft pin mode)
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
EEPROM (soft pin mode)
NOTE: The internal ROM has 16 pages selectable by GPIO[3:0] pins in Hard pin mode (not 32 pages as shown).
Figure 37. Device Control, Register, and Memory Interfaces
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Programming (continued)
9.5.2 I2C Serial Interface
When started in I2C mode (HW_SW_CTRL = 0 or 1), the LMK05028 operates as an I2C slave and supports bus
rates of 100 kHz (standard mode) and 400 kHz (fast mode). Slower bus rates can work as long as the other I2C
specifications are met. The I2C timing diagram is shown in Figure 38.
ACK
STOP
STOP
START
tW(SCLL)
tW(SCLH)
tr(SM)
tf(SM)
~
~
VIH(SM)
SCL
VIL(SM)
~
~
th(START)
tr(SM)
tSU(SDATA)
th(SDATA)
tSU(START)
tf(SM)
tSU(STOP)
~
~
~
~
VIH(SM)
SDA
VIL(SM)
~
~
Figure 38. I2C Timing Diagram
In EEPROM mode, the LMK05028 can support up 4 different I2C addresses depending on the GPIO[2:1] pins.
The 7-bit I2C address is 11000xxb, where the two LSBs are determined by the GPIO[2:1] input levels sampled at
device POR and the five MSBs (11000b) are initialized from EEPROM. In ROM mode, the two LSBs are fixed to
00b and the five MSB are initialized from ROM.
A generic transaction is shown in Figure 39.
Figure 39. I2C Generic Programming Sequence
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ADVANCE INFORMATION
tBUS
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Programming (continued)
9.5.3 SPI Serial Interface
When started in SPI mode (HW_SW_CTRL = float), the LMK05028 uses a 4-wire SPI interface with SDI, SCL,
SDO, and SCS signals. The host must present data to the device MSB first. A message includes a transfer
direction bit (W/R), a 15-bit address field (A14 to A0), and a 8-bit data field (D7 to D0) as shown in Figure 40.
The W/R bit is 0 for a SPI write and 1 for a SPI read.
First Out
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22
23
24
Order of Transmission
W
/R
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
1
D
0
Bit Definition
Register Address (15 bits)
D
2
Message Field Definition
Data Payload (8 bits)
Figure 40. SPI Message Format
The SPI timing diagram is shown in Figure 41.
t1
t4
t5
SCL
§
§
²
W/R
t3
§
A14
D1
D0
'21¶7 &$5(
§
t6
§
SDO
'21¶7 &$5(
D7
D1
D0
§
ADVANCE INFORMATION
t2
SDI
t7
SCS
t8
Figure 41. SPI Timing Parameters
9.5.4 EEPROM Programming Flow
After the configuration registers are programmed, the EEPROM can be programmed by the register writes in two
steps: Write SRAM and Program EEPROM.
9.5.4.1 Write SRAM
The SRAM array is volatile shadow memory mapped to a subset of the active configuration registers that
determine the device operation at POR or initialization. After the active registers have been programmed, they
can be committed to the SRAM through the following sequence:
1. Write a 0 to REGCOMMIT_PG bits.
2. Write a 1 to REGCOMMIT bit (self-clearing). This transfers the active register data to the SRAM internally.
If the SRAM/EEPROM map data is already known, the SRAM can also be written directly without modifying the
active configuration registers through the following sequence:
1. Write the 4 upper bits of the SRAM address to MEMADR[12:8] bits and write 8 lower bits of the SRAM
address to MEMADR[7:0] bits.
2. Write the desired SRAM data byte to RAMDAT bits in the same I2C or SPI transaction and this data byte will
be written at the SRAM address specified in the previous step. Any additional access that is part of the same
transaction will cause the SRAM address to be auto-incremented and a subsequent write will take place to
the next SRAM address. Access to SRAM will terminate at the end of current I2C or SPI transaction.
42
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Programming (continued)
9.5.4.2 Program EEPROM
The EEPROM array is non-volatile memory mapped directly from the SRAM array. After the register settings
have been committed to SRAM (see Write SRAM), the EEPROM can be programmed from SRAM through the
following sequence:
1. Write EAh to NVMUNLK bits. This unlocks the EEPROM from protected state to allow programming.
2. Write a 1 to NVM_ERASE_PROG bits. This programs EEPROM from the entire SRAM contents. The total
Erase/Program sequence takes about 230 ms.
3. Poll the NVMBUSY bit. The EEPROM programming is done when the NVMBUSY bit is cleared. The
NVMCNT register value will be auto-incremented by 1 to reflect total number of EEPROM programming
cycles completed.
4. (optional) Write 0h to NVMUNLK bits. This locks the EEPROM to protect against inadvertent programming.
ADVANCE INFORMATION
On the next power-up or POR cycle, the device will self-start in Soft Pin mode from the newly programmed
EEPROM configuration.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Device Start-Up Sequence
The device start-up sequence is shown in Figure 42. In the case when VDDO_x is delayed until after the POR,
the output channel is held in reset and its output(s) are muted when VDDO_x reaches acceptable value. Once
VDDO_x reaches is ramped, the output channel is released from reset and outputs are unmuted without glitches.
ADVANCE INFORMATION
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Application Information (continued)
Power on
Reset
no
PDN =1?
(all outputs are disabled)
1
0
HW_SW_CTRL
Float
Hard Pin Mode
(activate I2C IF)
Soft Pin Mode
(activate I2C IF)
Soft Pin Mode
(activate SPI IF)
Device setting from EEPROM image is loaded.
Registers programmable via I2C or SPI.
GPIO[4:3] can be used for DPLL1/2 FINC/
FDEC and GPIO[6:5] can also be repurposed
as device status outputs
Latch GPIO[4:0] to select 1 of 32 device
settings from ROM codes.GPIO[5:6] are
set as device status outputs
Enter pin mode specified by GPIO
ADVANCE INFORMATION
APLLs startup in free-run mode:
Disable outputs, Calibrate VCO
If VDDO_x is not stable, wait till reaches allowable range
(within a programmable timer) before unmuting outputs
For outputs with APLL mute enabled but DPLL mute
disabled, enable outputs after APLL is locked
Auto-synchronize these outputs
If input with highest priority is available, DPLL loads
appropriate loop parameters and locks with minimal output
phase shift using phase cancellation (fast lock, if enabled,
loads temporary loop parameters)
For outputs with DPLL mute enabled, enable outputs after
DPLL is locked. Auto synchronize these outputs
If reference is lost or higher priority
reference is available, refer to
Hitless Switching and Holdover
flowcharts
No
GPIO0 pin (soft pin mode only)
or SYNCN bit =1?
Yes
Synchronize outputs while
outputs are muted
Enable all outputs
Clear SYNCN_SW,
PLLx_SYNCN_SW
register bits
Disable
all
outputs
Normal device operation in Soft Pin
Mode. Host can reprogram device
via I2C or SPI and can be written to
on-chip EEPROM.
GPIO0 pin (soft pin mode
only) or SYNCN bit =1?
Yes
No
PDN=1?
Disable
all
outputs
Figure 42. Device Start-Up Sequence
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Application Information (continued)
10.1.2 Power Down (PDN) Pin
The PDN pin (active low) can be used for device power-down and used to initialize the POR sequence. When
PDN is pulled low, the entire device is powered down and the serial interface is disabled. When PDN is pulled
high, the device POR sequence is triggered to begin the device start-up sequence and normal operation as
depicted in Figure 42.
Table 7. PDN Control
PDN PIN STATE
DEVICE OPERATION
0
Device is disabled
1
Normal operation
10.1.3 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
10.1.3.1 Mixing Supplies
ADVANCE INFORMATION
The LMK05028 incorporates flexible power supply architecture. While all VDD core supplies should be powered
by the same 3.3-V rail, the individual output supplies can be powered from separate 1.8-V, 2.5-V or 3.3-V rails.
This can allow all output supplies at 1.8 V to minimize power consumption. It can also allow mixed output driver
levels simultaneously, for example, a 2.5-V LVCMOS clock from a 2.5-V rail and other differential clocks from a
1.8-V rail.
10.1.3.2 Power-On Reset (POR) Circuit
The LMK05028 integrates a built-in power-on reset (POR) circuit that holds the device in reset until all of the
following conditions have been met:
• All VDD core supplies have ramped above 2.72 V
• PDN pin has ramped above 1.2 V (VIH)
10.1.3.3 Powering Up From a Single-Supply Rail
As long as all VDD core supplies are driven by the same 3.3-V supply rail that ramp in a monotonic manner from
0 V to 3.135 V, irrespective of the ramp time, then there is no requirement to add a capacitor on the PDN pin to
externally delay the device power-up sequence. As shown in Figure 43, the PDN pin can be left floating or
otherwise driven by a host controller for meeting the clock sequencing requirements in the system.
VDD_PLLx, VDD_INx,
VDD_DIG, VDD_XO,
VDD_TCXO, PDN
3.135 V
VDD_DIG
Decision Point 2:
VDD_PLLx/VDD_INx/
VDD_DIG / VDD_XO /
VDD_7&;2 • 2.72 V
200 k
Decision Point 1:
3'1 • 1.2 V
PDN
0V
Figure 43. Recommendation for Power Up From a Single-Supply Rail
46
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10.1.3.4 Power Up From Split-Supply Rails
If some VDD core supplies are driven from different supply rails, TI recommends starting the PLL calibration after
all of the core supplies have settled at 3.135 V. This can be realized by delaying the PDN low-to-high transition.
The PDN input incorporates a 200-kΩ resistor to VDD_DIG and as shown in Figure 44, a capacitor from the PDN
pin to GND can be used to form a R-C time constant with the internal pullup resistor. This R-C time constant can
be designed to delay the low-to-high transition of PDN until all the core supplies have settled at 3.135 V.
VDD_PLLx, VDD_XO,
VDD_TCXO, VDD_INx,
VDD_DIG, PDN
3.135 V
Decision Point 2:
VDD_PLLx/VDD_INx/
VDD_XO/VDD_TCXO/
VDD_',* • 2.72 V
VDD_DIG
200 k
PDN
Decision Point 1:
3'1 • 1.2 V
CPDN
Figure 44. Recommendation for Power Up From Split-Supply Rails
10.1.3.5 Non-Monotonic or Slow Power-Up Supply Ramp
In case the VDD core supplies ramp with a non-monotonic manner or with a slow ramp time from 0 V to 3.135 V
of over 100 ms, TI recommends starting the PLL calibration after all of the core supplies have settled at 3.135 V.
This can be realized by delaying the PDN low-to-high transition in a manner similar to the condition shown in
Figure 44.
10.2 Typical Application
Figure 45 shows a reference schematic to help implement the LMK05028 and its peripheral circuitry. Power
filtering examples are given for the core supply pins and independent output supply pins. Single-ended
LVCMOS, AC-coupled differential, and HCSL clock interface examples are shown for the various clock input and
output pins. An external LVCMOS oscillator is driving a AC-coupled voltage divider network as an example to
interface a 3.3-V LVCMOS output to the XO or TCXO input pin. The required external capacitors with the
recommended values are shown. The logic I/O pins with external pullup or pulldown resistor options set the
default input states. The I2C or SPI pins and other logic pins can be connected to a host device (not shown) to
program and control the LMK05028 and monitor its status. This example assumes the device will start up from
EEPROM mode with an I2C interface (HW_SW_CTRL = 0).
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Delay
0V
LMK05028
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LMK05028
Internal pin states: Ibias = Internal Bias,
Ipu = Pullup, Ipd = Pulldown
POWER FILTERING
3.3V
3.3V
FB1
C1
0.1µF
3.3V
220 ohm
C2
0.1µF
C4
10µF
C6
0.1µF
3.3V
FB2
C5
10µF
C7
0.1µF
3.3V
1.8V/2.5V/3.3V
220 ohm
C11
10µF
C8
0.1µF
C15
0.1µF
C16
VDDIN
16
C17
VDDIN
9
0.1µF
4
C18
VDDIN
0.1µF
C19
VDDXO
C12
10µF
42
19
0.1µF
C20
VDDIN
0.1µF
C21
VDDDIG
0.1µF
C22
VDDPLL1
49
0.1µF
C23
VDDPLL2
37
ADVANCE INFORMATION
LVCMOS DRIVER
0.1µF
C9
0.1µF
C10 IN0_N
R1
C13
10µF
IN0_P
IN1_P
OUT
33
IN1_N
AC-DIFF
INT. TERM
LVCMOS
1.8V-3.3V
LOGIC I/O PINS
CONNECT ANY NEEDED LOGIC I/O PINS TO HOST MCU.
1.5V-3.3V
PIN DEFS. FOR EEPROM (SOFT PIN) START-UP MODE:
I2C MODE (HW_SW_CTRL = 0)
- SDA, SCL = I2C Data, I2C Clock
- GPIO0 = Output Sync (active low)
- GPIO[2:1] = I2C Address LSB Select (00,01,10,11b)
- GPIO[4:3] = DPLL1 DCO FDEC:FINC
- GPIO[6:5] = DPLL2 DCO FDEC:FINC (or Status Out)
SPI MODE (HW_SW_CTRL= FLOAT)
- STATUS[1:0] = Must be FLOAT (or connect to Hi-Z Input)
- SDA, SCL = SPI Data In (SDI), SPI Clock
- GPIO1 = SPI SCS
- GPIO2 = SPI Data Out (SDO)
- GPIO[0,3-6] = Same as for HW_SW_CTRL = 0
4.7k R9
4.7k R10
SDA(SDI)
SCL(SCK)
HW_SW_CTRL 10k R11
10k
10k
10k
10k
10k
10k
10k
GPIO0
GPIO1(SCS)
GPIO2(SDO)
GPIO3
GPIO4
GPIO5
GPIO6
R2
R3
R4
R5
R6
R7
R8
DNP
DNP
DNP
DNP
DNP
DNP
8
VDDOx
220 ohm
CLOCK INPUT EXAMPLES
OUT-
3
0.1µF
DIFF DRIVER
OUT+
VDDIN
VDDPLL2
220 ohm
PDN
TP2
TP1
10k
10k
10k
10k
10k
10k
DNP
R12
R13
R14
R15
R16
R17
C14
C35
C38
0.1µF
0.1µF
R22
XO_P (TCXO_IN)
0.1µF
FB5
VDDDIG
C3
1µF
LVCMOS OSC EXAMPLE (XO, TCXO)
U1
VDDPLL1
FB4
VDDXO
220 ohm
Place C near pins
FB3
VDDIN
IN0_P
IN0_N
1
2
IN1_P
IN1_N
14
15
IN2_P
IN2_N
10
11
IN3_P
IN3_N
5
6
INSEL0_0
INSEL0_1
20
17
INSEL1_0
INSEL1_1
28
29
SDA(SDI)
SCL(SCK)
HW_SW_CTRL
35
36
64
GPIO0
GPIO1(SCS)
GPIO2(SDO)
GPIO3
GPIO4
GPIO5
GPIO6
45
24
60
40
41
12
13
STATUS0
STATUS1
55
56
PDN
46
VDD_IN0
VDDO_0
VDD_IN1
VDDO_1
VDD_IN2
VDDO_23
VDD_IN3
VDDO_45
VDD_XO
VDDO_6
VDD_TCXO
VDDO_7
VDD_DIG
TCXO_IN
Ibias
VDD_APLL1
VDD_APLL2
XO_P
XO_N
IN0_P
IN0_N
OUT0_P
OUT0_N
IN1_P
IN1_N
OUT1_P
OUT1_N
Ibias
IN2_P
IN2_N
OUT2_P
OUT2_N
IN3_P
IN3_N
OUT3_P
OUT3_N
INSEL0_0
INSEL0_1
OUT4_P
OUT4_N
Ipu
INSEL1_0
INSEL1_1
OUT5_P
OUT5_N
SDA
SCL
HW_SW_CTRL Ipu/pd
OUT6_P
OUT6_N
OUT7_P
OUT7_N
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
Ipu/pd
LF1
LF2
STATUS0
STATUS1
PDN
CAP_APLL1
CAP_APLL2
CAP_DIG
Ipu
PAD
21
VDDO0
0.1µF
C25
XO_N
25
VDDO1
0.1µF
C26
30
VDDO23 0.1µF
C27
50
VDDO45 0.1µF
C28
59
VDDO6
0.1µF
C29
0.1µF
C30
63
VDDO7
18
TCXO_IN
43
XO_P
44
XO_N
22
23
OUT0_P
OUT0_N
27
26
OUT1_P
OUT1_N
31
32
OUT2_P
OUT2_N
34
33
OUT3_P
OUT3_N
51
52
OUT4_P
OUT4_N
54
53
OUT5_P
OUT5_N
57
58
OUT6_P
OUT6_N
62
61
OUT7_P
OUT7_N
48
38
7
CPLL1
CPLL2
CDIG
47
39
LF1
LF2
R18
49.9
Place C+R near XO_P
(or TCXO_IN) pin
100
2
E/C
VDD
GND
OUT
FB6
4
3
C39
0.1µF
C40
10µF
C41
0.1µF
CLOCK OUTPUT EXAMPLES
IN+
65
3.3V_LDO
Y1
1
0.1µF
C36
OUT0_N 0.1µF
C37
OUT0_P
AC-DIFF
AC-DIFF RECEIVER
50R
50R
Vbias
IN-
IN+
HCSL
EXT. TERM
OUT1_P
0
R19
OUT1_N
0
R20
HCSL RECEIVER
50R
50R
IN-
LVCMOS RECEIVER
LVCMOS
1.8V/2.5V
C32
10µF
C24
0.1µF
C31
0.1µF
C33
10µF
OUT7_P
0
R21
IN (Hi-Z)
C34
10µF
Place C near pins
LMK05028RGC
CONNECT E-PAD TO PCB GROUND
LAYERS WITH 6x6 VIA PATTERN.
Copyright © 2018, Texas Instruments Incorporated
Figure 45. Reference Schematic Example
48
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In a typical application, the following design parameters should be considered to implement the overall clock
solution:
1. Device initial configuration: Host programmed or factory pre-programmed.
2. Device start-up mode and serial interface. Typically, this will be EEPROM + I2C or SPI mode.
3. XO frequency, signal type, and phase noise or jitter
4. TCXO frequency and stability if any of the following is required:
– Standard-compliant frequency stability (such as SyncE, SONET/SDH, IEEE 1588)
– Lowest possible close-in phase noise at offsets ≤ 100 Hz
– Narrow DPLL bandwidth ≤ 10 Hz
5. For each PLL domain, determine the following:
– Input clocks: frequency, buffer mode, priority, and input selection mode
– Output clocks: frequency, buffer mode
– DPLL loop mode, loop bandwidth, and market segment
– DCO mode or Zero delay
6. Clock monitoring options
7. Status outputs and interrupt flag
8. Power supply rails
10.2.2 Detailed Design Procedure
In a typical application, TI recommends the following steps:
1. The LMK05028 GUI in TI's TICS Pro software has a step-by-step design flow to enter the design parameters,
calculate the frequency plan for each PLL domain, and generate the register settings for the desired
configuration. The register settings can be exported (as hex data) to enable host or factory programming.
– If using a generic (non-custom) device, a host device can program the register settings through the serial
interface after power-up and issue a soft-reset (by RESET_SW bit) to start the device. The host can also
store the settings to the EEPROM to allow self-startup with these register settings on subsequent poweron reset cycles.
– Alternatively, a LMK05028 setup file for TICS Pro (.tcs) can be sent to TI to request custom factory preprogrammed devices.
2. Tie the HW_SW_CTRL pin to 0 or float it (VIM) to select EEPROM mode with I2C or SPI respectively.
Determine the logic I/O pin assignments for control and status functions.
– Connect I2C/SPI and logic I/O pins (1.8-V compatible levels) to the host device pins with the proper I/O
direction and voltage levels.
3. Select a XO frequency by following Oscillator Input (XO_P/N).
– Choose a XO with target phase jitter performance < 300 fs RMS (12 kHz to 20 MHz).
– For a 3.3-V LVCMOS XO, follow the OSC clock interface example in Figure 45. Power the OSC from a
low-noise regulator.
– Configure the XO input buffer and termination options through the registers.
4. If a TCXO/OCXO is needed, select the frequency by following TCXO Input (TCXO_IN).
– Choose a TCXO/OCXO that meets the frequency stability (over operating conditions) and accuracy
requirements required for the output clocks during free-run or holdover.
– For a 3.3-V LVCMOS TCXO/OCXO, follow the OSC clock interface example in Figure 45.
– A (clipped) sinewave TCXO/OCXO with less than 1.2-Vpp swing can be simply AC-coupled to the input
pin.
5. For each PLL domain, wire the clock I/O in the schematic and configure the device settings as follows:
– Reference inputs: Follow the LVCMOS or differential clock input interface examples in Figure 45.
– Configure each reference input buffer mode through registers to match the driver interface
requirements.
– LVCMOS input mode should be used for input frequencies below 5 MHz.
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– Configure the DPLL input selection modes and input priorities through the registers.
– Output clock assignment guidelines to minimize crosstalk and spurs:
– OUT[4:7] bank requires at least one clock from the PLL1 domain. OUT[4:7] bank is preferred for PLL1
clocks.
– OUT[0:3] bank requires at least one clock from the PLL2 domain if enabled. OUT[0:3] bank is
preferred for PLL2 clocks.
– Group identical output frequencies (or harmonic frequencies) on adjacent channels. Use the output
pairs with a single divider (OUT2/3 or OUT4/5) if possible to minimize power.
– Separate clock outputs when the difference of the two frequencies, |FOUTx - FOUTy|, falls within the jitter
integration bandwidth (12 kHz to 20 MHz, for example). The two outputs should be separated by at
least 4 static pins (power or logic) to minimize potential coupling, or consider placing them on separate
output banks (which are on opposite sides of the chip).
– Avoid or isolate any LVCMOS output (strong aggressor) from other jitter-sensitive differential output
clocks. If a LVCMOS output is required, use dual complementary LVCMOS mode (+/- or -/+) with the
unused LVCMOS output left floating with no trace. Furthermore, the output slew rate could also be
slowed to Normal mode (CHx_SLEW_RATE bit) to reduce the coupling strength of an LVCMOS
output.
– If not all outputs pairs are used in the application, consider connecting OUT0 or OUT1 to a pair of RF
coaxial test structures for testing purposes (such as SMA, SMP). OUT0 and OUT1 are capable of
selecting a buffered copy of the XO clock or the Ref Bypass clock (either DPLL reference or TCXO
input) as well as any PLL post-divider clock.
– Clock outputs: Follow the single-ended or differential clock output interface examples in Figure 45.
– Configure each clock output buffer mode through registers to match the receiver interface
requirements.
– Differential outputs should be AC-coupled and terminated or biased at the receiver inputs.
– HCSL outputs should have 50-Ω termination to GND (at source or load side) unless the internal
source termination is enabled by registers.
– LVCMOS outputs have internal source termination to drive 50-Ω traces directly. LVCMOS VOH level is
determined by VDDO voltage (1.8 V and 2.5 V).
– Configure the DPLL loop mode.
– 3-loop mode supports standards-compliant synchronization using a low-cost holdover TCXO/OCXO,
very low loop bandwidths (≤10 Hz), or both. 3-loop mode also supports 1-PPS input synchronization.
– 2-loop mode with REF-DPLL supports higher loop bandwidth (>10 Hz) and relaxed holdover stability
without a TCXO/OCXO.
– 2-loop mode with TCXO-DPLL locks to a TCXO/OCXO input and typically used with DCO mode for
external clock steering (such as IEEE 1588 PTP).
– Configure the REF-DPLL loop bandwidth.
– The optimal bandwidth depends on the relative phase noise between the reference input and the XO
(or the TCXO for 3-loop mode).
– For 3-loop mode, the bandwidth is typically 10 mHz to 10 Hz to attenuate wander and support low
wander generation because of the TCXO/OCXO.
– For 2-loop mode, the bandwidth is typically 10 Hz or higher. Target a bandwidth below 300 Hz if the
PLL VCO frequency is an integer multiple of the reference input frequency.
– Below the loop bandwidth, the reference noise is added to the REF-TDC noise floor (and the XO
noise in 2-loop mode). Above the loop bandwidth, the reference noise will be attenuated at 20
dB/decade.
– Configure the TCXO-DPLL loop bandwidth.
– The optimal bandwidth depends on the relative phase noise between the TCXO/OCXO and the XO.
– For 3-loop mode, the bandwidth should be at least 200x higher than the REF-DPLL bandwidth for loop
stability.
– For 2-loop mode with TCXO-DPLL, target a bandwidth below 300 Hz if the PLL VCO frequency is an
integer multiple of the TCXO/OCXO frequency.
– Below the loop bandwidth, the TCXO/OCXO noise is added to the TCXO-TDC noise floor. Above the
loop bandwidth, the OCXO/TCXO noise will be attenuated at 20 dB/decade.
50
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– Configure the market segment parameter in TICS Pro to optimize the DPLL according to the use case.
– SyncE/SONET: TDC rate is targeted for approximately 400 kHz. Hitless switching is enabled.
Supports SyncE/SONET and other use cases using a narrow loop bandwidth (≤10 Hz) in 3-loop mode
with a TCXO/OCXO to set the frequency stability and wander performance.
– Wireless/BTS: TDC rate is maximized for lowest in-band TDC noise contribution. Hitless switching is
enabled. Supports wireless and other use cases where close-in phase noise is critical. This is used to
achieve –102 dBc/Hz at 100-Hz offset for a 122.88-MHz output.
– OTN/JitterAtten: TDC rate is targeted for approximately 1 MHz. Hitless switching is disabled. Supports
OTN/OTU and traditional jitter cleaning use cases with wider bandwidths (>10 Hz) in 2-loop mode and
relaxed holdover frequency accuracy (no TCXO/OCXO).
– If clock steering is needed (such as for IEEE 1588 PTP), configure DCO mode for the REF or TCXO loop
and compute the DCO FDEV step size register by following Digitally-Controlled Oscillator (DCO) Mode).
To allow DCO frequency updates using the external control pins, enable the FINC/FDEC functionality on
the needed GPIO pins by setting the appropriate register bits (GPIO[3:6]_FDEV_EN).
– If deterministic input-to-output clock phase is needed, configure zero delay mode and select the output
channel that needs to phase-aligned with the input. For DPLL1, any output from the OUT[4:7] bank can
be selected for zero-delay feedback. For DPLL2, any output from the OUT[0:3] bank can be selected for
zero-delay feedback.
6. Configure the clock monitoring features (per input or per DPLL):
– Amplitude monitor: Set the LVCMOS input slew rate detected edge or the Differential input minimum
amplitude to monitor input signal quality. Disable monitor for differential inputs below 5 MHz or else use
LVCMOS input mode.
– Frequency monitor: Set the valid and invalid thresholds (in ppm). Disable monitor for inputs < 2 kHz.
– Missing pulse monitor: Set the late window threshold (TLATE) to allow for the longest expected input clock
period, including jitter and gapped input clock (if applicable). Disable monitor for inputs < 2 kHz.
– Runt pulse monitor: Set the early window threshold (TEARLY) to allow for the shortest expected input clock
period, including jitter. Disable monitor for inputs < 2 kHz.
– Phase validation monitor: Set the phase validation threshold to account for worst-case input peak-to-peak
jitter, specified by number of periods of the 0-ppm reference clock (XO or TCXO input). Disable monitor
for inputs ≥ 2 kHz.
– Validation timer: Set the amount of time the reference input must be qualified by all enabled input
monitors before the input is valid for selection.
– DPLL frequency lock and phase lock detectors: Set the lock and unlock thresholds for each detector.
7. Configure each status output pin and interrupt flag, if needed.
– Select the desired status signal selection, driver mode (3.3-V LVCMOS or open-drain), and status
polarity. Open-drain requires an external pullup resistor.
– If the Interrupt is enabled and selected as a status output, set the mask for any interrupt flag to be
ignored, set the interrupt flag polarity, and select the combinational gate logic (OR/AND) as desired.
10.3 Do's and Don'ts
•
•
•
•
•
•
•
Power all VDD pins with proper supply decoupling and bypassing connect like shown in Figure 45.
Power down unused blocks through registers to minimize power consumption.
Leave unused clock outputs floating and powered down through register control.
Leave unused clock inputs floating.
For EEPROM+SPI Mode: Leave HW_SW_CTRL and STATUS[1:0] pins floating during POR to ensure proper
start-up. These pins has internal biasing to VIM internally.
– If HW_SW_CTRL or either STATUS pin is connected to an external device (MCU, FPGA), the external
device must be configured with high-impedance input (no pullup or pulldown resistors) to avoid conflict
with the internal bias to VIM. If needed, external biasing resistors (10-kΩ pullup to 3.3 V and 3.75-kΩ
pulldown) can be connected on each STATUS pin to bias the inputs to VIM during POR.
Use a low-noise, high-PSRR LDO regulator to power the external oscillators used to drive the XO and TCXO
inputs. Typically, oscillator jitter performance is typically impacted by switching noise on its power supply.
Include a dedicated serial port to the I2C or SPI pins of the LMK05028.
– This allows off-board programming for device bring-up, debug, and diagnostics using TI's USB hardware
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Do's and Don'ts (continued)
interface and software GUI tools.
11 Power Supply Recommendations
11.1 Power Supply Bypassing
Figure 46 shows two general placements of power supply bypass capacitors on either back side or component
side. If the capacitors are mounted on the back side, 0402 components can be employed. For component side
mounting, use 0201 body size capacitors to facilitate signal routing. A combination of component and back side
placement can be used. Keep the connections between the bypass capacitors and the power supply on the
device as short as possible. Ground the other side of the capacitor using a low impedance connection to the
ground plane.
ADVANCE INFORMATION
Back Side
Component Side
(Does not indicate actual location of LMK05028 supply pins)
Figure 46. Generalized Placement of Power Supply Bypass Capacitors
12 Layout
12.1 Layout Guidelines
•
•
•
•
•
•
52
Isolate input, XO, TCXO, and output clocks from adjacent clocks with different frequencies and other nearby
dynamic signals.
Avoid impedance discontinuities on controlled-impedance 50-Ω single-ended (or 100-Ω differential) traces for
clock and dynamic logic signals.
Place bypass capacitors close to the VDD and VDDO pins on the same side as the LMK05028, or directly
below the IC pins on the back side of the PCB. Larger decoupling capacitor values can be placed further
away.
Place external capacitors close to the CAP_x and LFx pins.
Preferably use multiple vias to connect wide supply traces to the respective power islands or planes.
Use at least 7x7 through-hole via pattern to connect the IC ground/thermal pad to the PCB ground planes.
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12.2 Layout Example
Figure 47. Recommended PCB Layout of LMK05028
12.3 Thermal Reliability
The LMK05028 is a high-performance device. To ensure good electrical and thermal performance, it is
recommended to design a thermally-enhanced interface between the IC ground/thermal pad and the PCB ground
using at least 7x7 through-hole via pattern connected to multiple PCB ground layers like shown in Figure 47.
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13 Device and Documentation Support
13.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
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13.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
54
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Product Folder Links: LMK05028
PACKAGE OPTION ADDENDUM
www.ti.com
24-Mar-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMK05028RGCR
PREVIEW
VQFN
RGC
64
2500
Green (RoHS
& no Sb/Br)
Call TI
Level-3-260C-168 HR
-40 to 85
K5028
LMK05028RGCRN1
PREVIEW
VQFN
RGC
64
2500
Green (RoHS
& no Sb/Br)
Call TI
Level-3-260C-168 HR
-40 to 85
K5028N1
LMK05028RGCT
PREVIEW
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
Call TI
Level-3-260C-168 HR
-40 to 85
K5028
LMK05028RGCTN1
PREVIEW
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
Call TI
Level-3-260C-168 HR
-40 to 85
K5028N1
P1LMK05028RGCT
ACTIVE
VQFN
RGC
64
250
TBD
Call TI
Call TI
-40 to 85
P1K5028
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Mar-2018
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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