MP38870 3A, 14V, 600KHz Step-Down Converter with Synchronizable Gate Driver The Future of Analog IC Technology DESCRIPTION FEATURES The MP38870 is a monolithic step-down switch mode converter with a built in internal high-side power MOSFET. It achieves 3A continuous output current over a wide input supply range with excellent load and line regulation. • • • • • Current mode operation provides fast transient response and reliable over current protection. Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown. The MP38870 requires a minimum number of readily available standard external components and is available in a space saving 3mm x 4mm 14-pin QFN package. • • • • • • • Wide 4.5V to 14V Operating Input Range 3A Continuous Output Current 80mΩ Internal Power MOSFET Switch Power Good Indicator Synchronous Gate Driver Delivers up to 95% Efficiency Fixed 600KHz Frequency External Synchronous Option: 250kHz1.5MHz Cycle-by-Cycle Over Current Protection Thermal Shutdown Output Adjustable from 0.8V Stable with Low ESR Output Ceramic Capacitors Available in a 3mm x 4mm 14-Pin QFN Package APPLICATIONS • • • • • Point of Load Regulator in Distributed Power System Digital Set Top Boxes Personal Video Recorders Broadband Communications Flat Panel Television and Monitors “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION VIN 4, 5, 6 IN BST Efficiency vs. Output Current 11 100 VIN=5V 12 2 OFF ON 3 SW VCC BG PG EN/SYNC GND 14 MP38870 Rev. 1.1 10/22/2009 FB 8, 9, 10 13 1 VOUT 3.3V @ 3A EFFICIENCY (%) 95 90 VIN=12V 85 80 75 70 65 60 VOUT=3.3V 0 1 2 3 OUTPUT CURRENT (A) www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 4 1 MP38870 – 3A, 14V, 600KHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER ABSOLUTE MAXIMUM RATINGS (1) PACKAGE REFERENCE Supply Voltage VIN ....................................... 16V VSW....................... –0.3V (-5V for < 10ns) to 17V VBS ....................................................... VSW + 6V All Other Pins................................. –0.3V to +6V Junction Temperature...............................150°C Lead Temperature ....................................260°C Storage Temperature ..............–65°C to +150°C TOP VIEW FB 1 14 GND PG 2 13 BG EN/SYNC 3 12 VCC IN 4 11 BST IN 5 10 SW IN 6 9 SW N/C 7 8 SW Recommended Operating Conditions Supply Voltage VIN ........................... 4.5V to 14V Output Voltage VOUT .................... 0.8V to VIN-3V Operating Temperature .............–40°C to +85°C EXPOSED PAD ON BACKSIDE CONNECT TO GROND * (2) Thermal Resistance Part Number* Package Temperature MP38870DL 3x4 QFN14 –40°C to +85°C For Tape & Reel, add suffix –Z (eg. MP38870DL–Z) For RoHS Compliant Packaging, add suffix –LF (eg. MP38870DL–LF–Z) (3) θJA θJC 3x4 QFN14 ............................. 48 ...... 11... °C/W Notes: 1) Exceeding these ratings may damage the device. 2) The device is not guaranteed to function outside of its operating conditions. 3) Measured on approximately 1” square of 1 oz copper. ELECTRICAL CHARACTERISTICS VIN = 12V, TA = +25°C, unless otherwise noted. Parameters Feedback Voltage Feedback Current Switch On Resistance (4) Switch Leakage Current Limit (4) Oscillator Frequency Fold-back Frequency Maximum Duty Cycle Minimum On Time (4) Under Voltage Lockout Threshold Rising Under Voltage Lockout Threshold Hysteresis EN Input Low Voltage En Input High Voltage Symbol Condition VFB 4.5V ≤ VIN ≤ 14V IFB VFB = 0.8V RDS(ON) VEN = 0V, VSW = 0V fSW 4 400 60 85 tON 3.9 Max 0.828 600 150 90 100 4.1 880 800 240 10 4.3 0.4 VEN = 2V VEN = 0V Synchronous Frequency Range (Low) Synchronous Frequency Range (High) Supply Current (Shutdown) Supply Current (Quiescent) Thermal Shutdown BG Driver Bias Supply Voltage Gate Driver Sink Impedance (4) Gate Driver Source Impedance (4) Gate Drive Current Sense Trip Threshold Typ 0.808 10 80 0 1.2 EN Input Current MP38870 Rev. 1.1 10/22/2009 VFB = 0.6V VFB = 0V VFB = 0.6V Min 0.788 FSYNC_L FSYNC_H 250 VEN = 0V VEN = 2V, VFB = 1V VCC RSINK RSOURCE 4.5 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 2 0 300 1.5 0 0.9 150 5 1 4 20 Units V nA mΩ μA A KHz KHz % ns V mV V V μA 10 1.1 2 5.5 kHz MHz μA mA °C V Ω Ω mV 2 MP38870 – 3A, 14V, 600KHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER ELECTRICAL CHARACTERISTICS(continued) VIN = 12V, TA = +25°C, unless otherwise noted. Parameters Power Good Threshold Power Good Threshold Hysteresis PG Pin Level Symbol Condition VPG Min 0.69 PG Sink 4mA Typ 0.74 40 Max 0.79 0.4 Units V mV V Note: 4) Guaranteed by design. PIN FUNCTIONS Pin # 1 2 3 4, 5, 6 7 8, 9, 10 11 12 13 14 Name Description Feedback. An external resistor divider from the output to GND, tapped to the FB pin sets the output voltage. To prevent current limit run away during a short circuit fault condition FB the frequency foldback comparator lowers the oscillator frequency when the FB voltage is below 250mV. Power Good Indicator. The output of this pin is low if the output voltage is 10% less than PG the nominal voltage, otherwise it is an open drain. EN/SYNC On/Off Control and External Frequency Synchronization Input. Supply Voltage. The MP38870 operates from a +4.5V to +14V unregulated input. C1 is IN needed to prevent large voltage spikes from appearing at the input. N/C No Connect. SW Switch Output. Bootstrap. This capacitor is needed to drive the power switch’s gate above the supply BST voltage. It is connected between SW and BST pins to form a floating supply across the power switch driver. VCC BG Driver Bias Supply. Decouple with a 1µF ceramic capacitor. BG Gate Driver Output. Connect this pin to the synchronous MOSFET Gate. Ground. This pin is the voltage reference for the regulated output voltage. For this reason GND care must be taken in its layout. This node should be placed outside of the M2 to C1 ground path to prevent switching current spikes from inducing voltage noise into the part. MP38870 Rev. 1.1 10/22/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 3 MP38870 – 3A, 14V, 600KHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VOUT = 3.3V, and TA = +28°C, unless otherwise noted. MP38870 Rev. 1.1 10/22/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 4 MP38870 – 3A, 14V, 600KHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, and TA = +28°C, unless otherwise noted. Latch Off with Output Short Circuit Power Up Power Up No Load Full Load VOUT 2V/div VSW 10V/div VOUT 2V/div VOUT 2V/div VSW 5V/div VSW 5V/div VIN 10V/div VIN 5V/div IINDUCTOR 2A/div IINDUCTOR 2A/div IINDUCTOR 2A/div 2ms/div 2ms/div Enable Startup Enable Startup Input Ripple Voltage No Load Full Load IOUT=3A VIN 50mV/div VOUT 2V/div VOUT 2V/div VSW 20V/div VSW 20V/div VEN 5V/div VEN 5V/div IINDUCTOR 5A/div IINDUCTOR 5A/div 4ms/div VSW 10V/div 4ms/div Output Ripple Voltage Load Transient Response IOUT=3A VSW 10V/div VSW 10V/div VOUT 20mV/div VOUT 50mV/div IINDUCTOR 2A/div IINDUCTOR 2A/div 400ns/div MP38870 Rev. 1.1 10/22/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 5 MP38870 – 3A, 14V, 600KHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER Operation IN CURRENT SENSE AMPLIFIER D + -- x40 REGULATOR BST EN/SYNC REGULATOR OSCILLATOR 600KHz S + -C1 1pF VCC REFERENCE C1 50pF VBG FB Q DRIVER R CURRENT LIMIT COMPARATOR R Q VCC VCC DRIVER + -- ERROR AMPLIFIER SW BG + -- PWM COMPARATOR PG VBG POWER GOOD GND Figure 1—Functional Block Diagram The MP38870 is a fixed frequency, synchronous, step-down switching regulator with an integrated high-side power MOSFET and a gate driver for a low-side external MOSFET. It achieves 3A continuous output current over a wide input supply range with excellent load and line regulation. It provides a single highly efficient solution with current mode control for fast loop response and easy compensation. The MP38870 operates in a fixed frequency, peak current control mode to regulate the output voltage. A PWM cycle is initiated by the internal clock. The integrated high-side power MOSFET is turned on and remains on until its current reaches the value set by the COMP voltage. When the power switch is off, it remains off until the next clock cycle starts. If, in 90% of one PWM period, the current in the power MOSFET does not reach the COMP set current value, the power MOSFET will be forced to turn off. MP38870 Rev. 1.1 10/22/2009 Error Amplifier The error amplifier compares the FB pin voltage with the internal 0.8V reference (REF) and outputs a current proportional to the difference between the two. This output current is then used to charge or discharge the internal compensation network to form the COMP voltage, which is used to control the power MOSFET current. The optimized internal compensation network minimizes the external component counts and simplifies the control loop design. Internal Regulator Most of the internal circuitries are powered from the 5V internal regulator. This regulator takes the VIN input and operates in the full VIN range. When VIN is greater than 5.0V, the output of the regulator is in full regulation. When VIN is lower than 5.0V, the output decreases. Since this internal regulator provides the bias current for the bottom gate driver that requires significant amount of current depending upon the external MOSFET selection, a 1uF ceramic capacitor for decoupling purpose is required. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 6 MP38870 – 3A, 14V, 600KHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER Enable/Synch Control The MP38870 has a dedicated Enable/Synch control pin (EN/SYNC). By pulling it high or low, the IC can be enabled and disabled by EN. Tie EN to VIN for automatic start up. To disable the part, EN must be pulled low for at least 5µs. The MP38870 can be synchronized to an external clock range from 250KHz up to 1.5MHz through the EN/SYNC pin. The internal clock rising edge is synchronized to the external clock rising edge. Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) is implemented to protect the chip from operating at insufficient supply voltage. The MP38870 UVLO comparator monitors the output voltage of the internal regulator, VCC. The UVLO rising threshold is about 4.1V while its falling threshold is a consistent 3.2V. Internal Soft-Start The soft-start is implemented to prevent the converter output voltage from overshooting during startup. When the chip starts, the internal circuitry generates a soft-start voltage (SS) ramping up from 0V to 1.2V. When it is lower than the internal reference (REF), SS overrides REF so the error amplifier uses SS as the reference. When SS is higher than REF, REF regains control. Over-Current-Protection (OCP) The MP38870 has cycle-by-cycle over current limit when the inductor current peak value exceeds the set current limit threshold. Meanwhile, output voltage starts to drop until FB is below the Under-Voltage (UV) threshold, typically 30% below the reference. Once a output UV is triggered, the MP38870 enters latch off mode. Mode is especially useful to ensure system safety under fault condition. The MP38870 exits the latch off mode once the EN or input power is re-cycled. MP38870 Rev. 1.1 10/22/2009 Thermal Shutdown Thermal shutdown is implemented to prevent the chip from operating at exceedingly high temperatures. When the silicon die temperature is higher than 150°C, it shuts down the whole chip. When the temperature is lower than its lower threshold, typically 140°C, the chip is enabled again. Floating Driver and Bootstrap Charging The floating power MOSFET driver is powered by an external bootstrap capacitor. This floating driver has its own UVLO protection. This UVLO’s rising threshold is 2.2V with a hysteresis of 150mV. The bootstrap capacitor voltage is regulated internally by VIN through D1, M3, C4, L1 and C2 (Figure 2). If (VIN-VSW) is more than 5V, U2 will regulate M3 to maintain a 5V BST voltage across C4. D1 VIN M3 + 5V + -- BST U2 -- C4 VOUT SW L1 C2 Figure 2—Internal Bootstrap Charging Circuit Startup and Shutdown If both VIN and EN are higher than their appropriate thresholds, the chip starts. The reference block starts first, generating stable reference voltage and currents, and then the internal regulator is enabled. The regulator provides stable supply for the remaining circuitries. Three events can shut down the chip: EN low, VIN low and thermal shutdown. In the shutdown procedure, the signaling path is first blocked to avoid any fault triggering. The COMP voltage and the internal supply rail are then pulled down. The floating driver is not subject to this shutdown command. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 7 MP38870 – 3A, 14V, 600KHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER APPLICATION INFORMATION Setting the Output Voltage The external resistor divider is used to set the output voltage (see the schematic on front page). The feedback resistor R1 also sets the feedback loop bandwidth with the internal compensation capacitor (see Figure 1). Choose R1 to be around 40.2kΩ for optimal transient response. R2 is then given by: R2 = R1 VOUT −1 0 .8 V VOUT (V) R1 (kΩ) R2 (kΩ) 1.8 2.5 3.3 5 40.2 (1%) 40.2 (1%) 40.2 (1%) 40.2 (1%) 32.4 (1%) 19.1 (1%) 13 (1%) 7.68 (1%) Selecting the Inductor A 1µH to 10µH inductor with a DC current rating of at least 25% percent higher than the maximum load current is recommended for most applications. For highest efficiency, the inductor DC resistance should be less than 15mΩ. For most designs, the inductance value can be derived from the following equation. VOUT × ( VIN − VOUT ) VIN × ΔIL × f OSC Where ΔIL is the inductor ripple current. Choose inductor current to be approximately 30% if the maximum load current, 3A. The maximum inductor peak current is: IL(MAX ) = ILOAD + ΔI L 2 Under light load conditions below 100mA, larger inductance is recommended for improved efficiency. MP38870 Rev. 1.1 10/22/2009 Table 2 lists example synchronous MOSFETs and manufacturers. Table 2—Synchronous MOSFET Selection Guide Table 1—Resistor Selection for Common Output Voltages L= Synchronous MOSFET The external synchronous MOSFET is used to supply current to the inductor when the internal high-side switch is off. It reduces the power loss significantly when compared to a Schottky rectifier. Part No. Manufacture Si7112 Si7114 AM4874 Vishay Vishay Analog Power Selecting the Input Capacitor The input current to the step-down converter is discontinuous, therefore a capacitor is required to supply the AC current to the step-down converter while maintaining the DC input voltage. Use low ESR capacitors for the best performance. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, a 10µF capacitor is sufficient. Since the input capacitor (C1) absorbs the input switching current it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated by: I C1 = ILOAD × VOUT ⎛⎜ VOUT × 1− VIN ⎜⎝ VIN ⎞ ⎟ ⎟ ⎠ The worse case condition occurs at VIN = 2VOUT, where: IC1 = ILOAD 2 For simplification, choose the input capacitor whose RMS current rating greater than half of the maximum load current. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 8 MP38870 – 3A, 14V, 600KHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER The input capacitor can be electrolytic, tantalum or ceramic. When using electrolytic or tantalum capacitors, a small, high quality ceramic capacitor, i.e. 0.1μF, should be placed as close to the IC as possible. When using ceramic capacitors, make sure that they have enough capacitance to provide sufficient charge to prevent excessive voltage ripple at input. The input voltage ripple caused by capacitance can be estimated by: ΔVIN = ⎛ ILOAD V V × OUT × ⎜1 − OUT fS × C1 VIN ⎜⎝ VIN ⎞ ⎟⎟ ⎠ Selecting the Output Capacitor The output capacitor (C2) is required to maintain the DC output voltage. Ceramic, tantalum, or low ESR electrolytic capacitors are recommended. Low ESR capacitors are preferred to keep the output voltage ripple low. The output voltage ripple can be estimated by: ΔVOUT = VOUT ⎛ V × ⎜⎜1 − OUT fS × L ⎝ VIN ⎞ ⎞ ⎛ 1 ⎟ ⎟⎟ × ⎜ R ESR + ⎜ 8 × f S × C2 ⎟⎠ ⎠ ⎝ Where L is the inductor value and RESR is the equivalent series resistance (ESR) value of the output capacitor. In the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. The output voltage ripple is mainly caused by the capacitance. For simplification, the output voltage ripple can be estimated by: ΔVOUT ⎛ ⎞ V = × ⎜⎜1 − OUT ⎟⎟ 2 VIN ⎠ 8 × fS × L × C2 ⎝ VOUT In the case of tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated to: ΔVOUT = VOUT ⎛ V × ⎜1 − OUT f S × L ⎜⎝ VIN ⎞ ⎟⎟ × R ESR ⎠ The characteristics of the output capacitor also affect the stability of the regulation system. The MP38870 can be optimized for a wide range of capacitance and ESR values. PC Board Layout The high current paths (GND, IN and SW) should be placed very to the device with short, direct and wide traces. The input capacitor needs to be as close as possible to the IN and GND pins. The external feedback resistors should be placed next to the FB pin. Keep the switching node SW short and away from the feedback network. External Bootstrap Diode An external bootstrap diode may enhance the efficiency of the regulator, the applicable conditions of external BST diode are: z VOUT=5V or 3.3V; and z Duty cycle is high: D= VOUT >65% VIN In these cases, an external BST diode is recommended from the output of the voltage regulator to BST pin, as shown in Fig.3 External BST Diode IN4148 BST MP38870 SW CBST L 5V or 3.3V COUT Figure 3—Add Optional External Bootstrap Diode to Enhance Efficiency The recommended external BST diode is IN4148, and the BST cap is 0.1~1µF. MP38870 Rev. 1.1 10/22/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 9 MP38870 – 3A, 14V, 600KHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER PACKAGE INFORMATION 3mm x 4mm QFN14 2.90 3.10 1.60 1.80 0.30 0.50 PIN 1 ID SEE DETAIL A PIN 1 ID MARKING 1 14 0.18 0.30 3.20 3.40 3.90 4.10 PIN 1 ID INDEX AREA 0.50 BSC 7 8 TOP VIEW BOTTOM VIEW 0.80 1.00 0.20 REF PIN 1 ID OPTION A 0.30x45º TYP. PIN 1 ID OPTION B R0.20 TYP. 0.00 0.05 SIDE VIEW DETAIL A 2.90 0.70 NOTE: 1.70 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX. 4) JEDEC REFERENCE IS MO-229, VARIATION VGED-3. 5) DRAWING IS NOT TO SCALE. 0.25 3.30 0.50 RECOMMENDED LAND PATTERN NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP38870 Rev. 1.1 10/22/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 10