PD - 97790
IRFI4510GPbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
l Halogen-Free
VDSS
RDS(on) typ.
max.
ID
100V
10.7m
13.5m
35A
D
D
G
G
S
D
S
TO-220AB Full-Pak
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS (Thermally limited)
TJ
TSTG
Parameter
Max.
Units
35
24
180
42
A
W
0.28
±20
206
-55 to + 175
W/°C
V
mJ
°C
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Maximum Power Dissipation
c
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
d
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
300
x
x
10lb in (1.1N m)
Thermal Resistance
Parameter
RJC
RJA
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f
Junction-to-Case
Junction-to-Ambient
f
Typ.
–––
–––
Max.
3.6
65
Units
°C/W
1
05/15/12
IRFI4510GPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max. Units
100
–––
–––
2.0
–––
–––
–––
–––
–––
–––
0.11
10.7
–––
–––
–––
–––
–––
0.6
–––
–––
13.5
4.0
20
250
100
-100
–––
Parameter
Min.
Typ.
Max. Units
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
55
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
54
13
16
16
33
54
37
2998
216
103
261
494
Min.
Typ.
–––
–––
V(BR)DSS
V(BR)DSS/TJ
RDS(on)
VGS(th)
IDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
RG(int)
V
V/°C
m
V
μA
nA
Conditions
VGS = 0V, ID = 250μA
Reference to 25°C, ID = 5mA
VGS = 10V, ID = 21A
VDS = VGS, ID = 100μA
VDS = 100V, VGS = 0V
VDS = 100V, VGS = 0V, TJ = 125°C
VGS = 20V
VGS = -20V
e
e
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Diode Characteristics
Symbol
IS
Parameter
VSD
trr
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
ISM
c
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.93mH
RG = 50, IAS = 21A, VGS =10V. Part not recommended for use
above this value.
Pulse width 400μs; duty cycle 2%.
R is measured at TJ approximately 90°C.
2
–––
81
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
nC
ns
pF
Max. Units
Conditions
VDS = 50V, ID = 21A
ID = 21A
VDS = 50V
VGS = 10V
VDD = 65V
ID = 21A
RG = 7.5
VGS = 10V
VGS = 0V
VDS = 50V
ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 80V
VGS = 0V, VDS = 0V to 80V
e
e
h, See Fig.11
g
Conditions
MOSFET symbol
showing the
G
–––
–––
180
A
integral reverse
p-n junction diode.
–––
–––
1.3
V
TJ = 25°C, IS = 21A, VGS = 0V
–––
39
59
ns
TJ = 25°C
VR = 85V
IF = 21A
–––
47
71
TJ = 125°C
di/dt = 100A/μs
–––
63
95
nC TJ = 25°C
–––
90
135
TJ = 125°C
–––
2.9
–––
A
TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
35
A
e
D
S
e
Coss eff. (TR) is a fixed capacitance that gives the same charging
time as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
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IRFI4510GPbF
1000
1000
100
BOTTOM
VGS
15V
10V
6.0V
5.5V
5.0V
4.75V
4.5V
4.25V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
6.0V
5.5V
5.0V
4.75V
4.5V
4.25V
100
10
4.25V
BOTTOM
4.25V
10
60μs PULSE WIDTH
60μs PULSE WIDTH
Tj = 175°C
Tj = 25°C
1
1
0.1
1
10
100
0.1
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
100
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
10
Fig 2. Typical Output Characteristics
1000
100
10
T J = 25°C
T J = 175°C
1
VDS = 50V
60μs PULSE WIDTH
0.1
ID = 21A
VGS = 10V
2.5
2.0
1.5
1.0
0.5
1
2
3
4
5
6
7
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
100000
14.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
VGS, Gate-to-Source Voltage (V)
ID= 21A
C oss = C ds + C gd
10000
C, Capacitance (pF)
1
V DS, Drain-to-Source Voltage (V)
Ciss
1000
Coss
Crss
100
12.0
VDS= 80V
VDS= 50V
10.0
VDS= 20V
8.0
6.0
4.0
2.0
0.0
10
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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0
10
20
30
40
50
60
70
QG, Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFI4510GPbF
1000
100
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
T J = 175°C
T J = 25°C
10
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100
100μsec
10
10msec
1
DC
0.1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
1.0
0.01
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0.1
VSD, Source-to-Drain Voltage (V)
20
10
0
75
100
125
150
175
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
ID, Drain Current (A)
30
50
100
1000
125
Id = 5mA
120
115
110
105
100
95
90
-60 -40 -20 0 20 40 60 80 100120140160180
T C , Case Temperature (°C)
T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Drain-to-Source Breakdown Voltage
1.4
EAS , Single Pulse Avalanche Energy (mJ)
900
1.2
1.0
Energy (μJ)
10
Fig 8. Maximum Safe Operating Area
40
25
1
VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
0.8
0.6
0.4
0.2
0.0
ID
TOP
6.7A
11A
BOTTOM 21A
800
700
600
500
400
300
200
100
0
-20
0
20
40
60
80
100
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
1msec
120
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRFI4510GPbF
Thermal Response ( Z thJC ) °C/W
10
D = 0.50
1
0.20
0.10
0.05
0.1
0.02
0.01
J
R1
R1
J
1
R2
R2
R3
R3
Ri (°C/W) i (sec)
R4
R4
C
1
2
3
2
3
4
4
Ci= iRi
Ci iRi
0.01
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
1.34312
0.470619
1.47895
0.072697
0.62114
0.006558
0.15442
0.000152
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
0.01
0.1
1
10
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
Avalanche Current (A)
Duty Cycle = Single Pulse
10
0.01
0.05
0.10
1
0.1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming j = 25°C and
Tstart = 150°C.
0.01
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
1.0E+01
1.0E+02
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
250
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 21A
200
150
100
50
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFI4510GPbF
25
3.5
IF = 14A
V R = 85V
20
TJ = 25°C
TJ = 125°C
3.0
2.5
IRRM (A)
VGS(th) , Gate threshold Voltage (V)
4.0
ID = 100μA
ID = 250μA
2.0
15
10
ID = 1.0mA
ID = 1.0A
5
1.5
1.0
0
-75 -50 -25
0
25 50 75 100 125 150 175
0
200
TJ , Temperature ( °C )
600
800
1000
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
500
25
IF = 21A
V R = 85V
20
IF = 14A
V R = 85V
400
TJ = 25°C
TJ = 125°C
15
QRR (nC)
IRRM (A)
400
diF /dt (A/μs)
10
TJ = 25°C
TJ = 125°C
300
200
100
5
0
0
0
200
400
600
800
0
1000
200
400
600
800
1000
diF /dt (A/μs)
diF /dt (A/μs)
Fig. 19 - Typical Stored Charge vs. dif/dt
Fig. 18 - Typical Recovery Current vs. dif/dt
500
IF = 21A
V R = 85V
QRR (nC)
400
TJ = 25°C
TJ = 125°C
300
200
100
0
0
200
400
600
800
1000
diF /dt (A/μs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFI4510GPbF
D.U.T
Driver Gate Drive
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
+
V
- DD
IAS
VGS
20V
tp
A
0.01
I AS
Fig 22a. Unclamped Inductive Test Circuit
LD
Fig 22b. Unclamped Inductive Waveforms
VDS
VDS
+
90%
VDD -
10%
D.U.T
VGS
VGS
Pulse Width < 1μs
Duty Factor < 0.1%
td(on)
Fig 23a. Switching Time Test Circuit
tr
td(off)
tf
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
DUT
0
1K
VCC
Vgs(th)
Qgs1 Qgs2
Fig 24a. Gate Charge Test Circuit
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Qgd
Qgodr
Fig 24b. Gate Charge Waveform
7
IRFI4510GPbF
TO-220AB Full-Pak Package Outline (Dimensions are shown in millimeters (inches))
TO-220AB Full-Pak Part Marking Information
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TO-220AB Full-Pak packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 101N Sepulveda Blvd, El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 05/2012
8
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