Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design OPA333, OPA2333 SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 OPAx333 1.8-V, microPower, CMOS Operational Amplifiers, Zero-Drift Series 1 Features • • • • • • • • 1 3 Description Low Offset Voltage: 10 μV (Maximum) Zero Drift: 0.05 μV/°C (Maximum) 0.01-Hz to 10-Hz Noise: 1.1 μVPP Quiescent Current: 17 μA Single-Supply Operation Supply Voltage: 1.8 V to 5.5 V Rail-to-Rail Input/Output microSize Packages: SC70 and SOT23 2 Applications • • • • • • Transducers Temperature Measurements Electronic Scales Medical Instrumentation Battery-Powered Instruments Handheld Test Equipment The OPAx333 series of CMOS operational amplifiers use a proprietary auto-calibration technique to simultaneously provide very low offset voltage (10 μV, maximum) and near-zero drift over time and temperature. These miniature, high-precision, low quiescent current amplifiers offer high-impedance inputs that have a common-mode range 100 mV beyond the rails, and rail-to-rail output that swings within 50 mV of the rails. Single or dual supplies as low as 1.8 V (±0.9 V) and up to 5.5 V (±2.75 V) can be used. These devices are optimized for lowvoltage, single-supply operation. The OPAx333 family offers excellent CMRR without the crossover associated with traditional complementary input stages. This design results in superior performance for driving analog-to-digital converters (ADCs) without degradation of differential linearity. The OPA333 (single version) is available in the 5-pin SOT-23, SOT, and 8-pin SOIC packages, while the OPA2333 (dual version) is available in the 8-pin VSON, SOIC, and VSSOP packages. All versions are specified for operation from –40°C to 125°C. Device Information(1) PART NUMBER PACKAGE OPA333 OPA2333 BODY SIZE (NOM) SOT-23 (5) 2.90 mm × 1.60 mm SOT (5) 2.00 mm x 1.25 mm SOIC (8) 4.90 mm × 3.90 mm VSON (8) 3.00 mm × 3.00 mm SOIC (8) 4.90 mm × 3.90 mm VSSOP (8) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 0.1-Hz to 10-Hz Noise OPAx333 Pinout Diagrams 500 nV/div OPA333 OUT 1 V- 2 +IN 3 OPA333 5 4 V+ -IN +IN 1 V- 2 -IN 3 SOT23-5 5 V+ 4 OUT SC70-5 OPA2333 1 s/div OUT A 1 -IN A 2 +IN A 3 V- 4 Exposed Thermal Die Pad on Underside 8 V+ 7 OUT B 6 -IN B 5 +IN B DFN-8 (SON-8) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. OPA333, OPA2333 SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 5 5 5 6 6 7 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information: OPA333 .................................. Thermal Information: OPA2333 ................................ Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 12 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 12 12 12 14 8 Application and Implementation ........................ 15 8.1 Application Information............................................ 15 8.2 Typical Applications ............................................... 15 8.3 System Examples ................................................... 20 9 Power Supply Recommendations...................... 22 10 Layout................................................................... 23 10.1 Layout Guidelines ................................................. 23 10.2 Layout Example .................................................... 23 11 Device and Documentation Support ................. 24 11.1 11.2 11.3 11.4 11.5 11.6 11.7 Device Support...................................................... Documentation Support ........................................ Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 24 24 24 24 24 24 25 12 Mechanical, Packaging, and Orderable Information ........................................................... 25 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (November 2013) to Revision E • Page Added Pin Configuration and Functions section, ESD Ratings and Thermal Information tables, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................................................................................ 1 Changes from Revision C (May 2007) to Revision D Page • Changed data sheet format to most current standard look and feel ...................................................................................... 1 • Added OPA2333 DFN-8 pinout to front page......................................................................................................................... 1 • Changed 2nd signal input terminals parameter in the Absolute Maximum Ratings from "voltage" to "current" (typo) .......... 5 • Added Table 1 ........................................................................................................................................................................ 8 2 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 OPA333, OPA2333 www.ti.com SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 5 Pin Configuration and Functions OPA333 DBV Package 5-Pin SOT Top View OUT 1 V- 2 +IN 3 5 4 OPA333 DCK Package 5-Pin SC70 Top View V+ +IN 1 V- 2 -IN 3 -IN 5 V+ 4 OUT OPA333 D Package 8-Pin SOIC Top View (1) (1) 1 8 NC -IN 2 7 V+ +IN 3 6 OUT V- 4 5 NC NC (1) Pin Functions: OPA333 PIN NAME I/O DESCRIPTION SOIC SOT SC70 +IN 3 3 1 I Noninverting input –IN 2 4 3 I Inverting input NC 1, 5, 8 — — — No internal connection (can be left floating) OUT 6 1 4 O Output V+ 7 5 5 — Positive (highest) power supply V– 4 2 2 — Negative (lowest) power supply Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 3 OPA333, OPA2333 SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 www.ti.com OPA2333 DRB Package 8-Pin VSON With Exposed Thermal Pad Top View OUT A 1 -IN A 2 +IN A 3 V- 4 Exposed Thermal Die Pad on (2) Underside OPA2333 D or DGK Package 8-Pin SOIC or VSSOP Top View OUT A 8 V+ 7 OUT B 6 -IN B 5 +IN B 1 8 V+ 7 OUT B A -IN A 2 B +IN A 3 6 -IN B V- 4 5 +IN B Pin Functions: OPA2333 PIN NAME I/O DESCRIPTION VSON SOIC, VSSOP +IN — — I Noninverting input +IN A 3 3 I Noninverting input, channel A +IN B 5 5 I Noninverting input, channel B –IN — — I Inverting input –IN A 2 2 I Inverting input, channel A –IN B 6 6 I Inverting input, channel B OUT — — O Output OUT A 1 1 O Output, channel A OUT B 7 7 O Output, channel B V+ 8 8 — Positive (highest) power supply V– 4 4 — Negative (lowest) power supply 4 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 OPA333, OPA2333 www.ti.com SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 6 Specifications 6.1 Absolute Maximum Ratings See (1) MIN Supply Voltage Current MAX Signal input terminals (2) –0.3 (V+) + 0.3 Signal input terminals (2) –1 1 Output short-circuit (3) 150 Operating temperature, TA –40 150 Storage temperature, Tstg –65 150 (2) (3) V mA Continuous Operating junction temperature, TJ (1) UNIT 7 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should be current limited to 10 mA or less. Short-circuit to ground, one amplifier per package. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Supply voltage, VS 1.8 5.5 V Specified temperature –40 125 °C Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 5 OPA333, OPA2333 SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 www.ti.com 6.4 Thermal Information: OPA333 OPA333 THERMAL METRIC (1) D (SOIC) DBV (SOT) DCK (SC70) 8 PINS 5 PINS 5 PINS 140.1 220.8 298.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 89.8 97.5 65.4 °C/W RθJB Junction-to-board thermal resistance 80.6 61.7 97.1 °C/W ψJT Junction-to-top characterization parameter 28.7 7.6 0.8 °C/W ψJB Junction-to-board characterization parameter 80.1 61.1 95.5 °C/W — — — °C/W RθJA Junction-to-ambient thermal resistance RθJC(bot) Junction-to-case (bottom) thermal resistance (1) UNIT For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Thermal Information: OPA2333 OPA2333 THERMAL METRIC RθJA (1) Junction-to-ambient thermal resistance D (SOIC) DGK (VSSOP) DRB (VSON) 8 PINS 8 PINS 8 PINS UNIT 124.0 180.3 46.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 73.7 48.1 26.3 °C/W RθJB Junction-to-board thermal resistance 64.4 100.9 22.2 °C/W ψJT Junction-to-top characterization parameter 18.0 2.4 1.6 °C/W ψJB Junction-to-board characterization parameter 63.9 99.3 22.3 °C/W — — 10.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 OPA333, OPA2333 www.ti.com SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 6.6 Electrical Characteristics At TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage VS = 5 V dVOS/dT Input offset voltage drift TA = –40°C to 125°C PSRR Power-supply rejection ratio VS = 1.8 V to 5.5 V, TA = –40°C to 125°C Long-term stability (1) 10 0.05 μV/°C 1 5 μV/V See note Channel separation, dc μV 2 0.02 (1) µV μV/V 0.1 INPUT BIAS CURRENT IB Input bias current IOS Input offset current TA= 25°C ±70 TA = –40°C to 125°C ±200 ±150 pA ±140 ±400 NOISE Input voltage noise in Input current noise f = 0.01 Hz to 1 Hz 0.3 f = 0.1 Hz to 10 Hz 1.1 f = 10 Hz 100 μVPP fA/√Hz INPUT VOLTAGE VCM Common-mode voltage range CMRR Common-mode rejection ratio (V–) – 0.1 (V–) – 0.1 V < VCM < (V+) + 0.1 V, TA = –40°C to 125°C 106 (V+) + 0.1 V 130 dB Differential 2 pF Common-mode 4 pF 130 dB INPUT CAPACITANCE OPEN-LOOP GAIN AOL Open-loop voltage gain (V–) + 100 mV < VO < (V+) – 100 mV, RL = 10 kΩ, TA = –40°C to 125°C 106 FREQUENCY RESPONSE GBW Gain-bandwidth product CL = 100 pF 350 kHz SR Slew rate G = +1 0.16 V/μs OUTPUT Voltage output swing from rail ISC Short-circuit current CL Capacitive load drive Open-loop output impedance RL = 10 kΩ 30 RL = 10 kΩ, TA = –40°C to 125°C 50 70 ±5 mV mA See Typical Characteristics f = 350 kHz, IO = 0 A 2 kΩ POWER SUPPLY VS IQ Specified voltage range Quiescent current per amplifier Turn-on time 1.8 IO = 0 A 5.5 17 TA = –40°C to 125°C 25 28 VS = +5 V V μA μs 100 TEMPERATURE TA Tstg (1) Specified range –40 125 °C Operating range –40 150 °C Storage range –65 150 °C 300-hour life test at 150°C demonstrated randomly distributed variation of approximately 1 μV. Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 7 OPA333, OPA2333 SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 www.ti.com 6.7 Typical Characteristics Table 1. List of Typical Characteristics TITLE FIGURE Offset Voltage Production Distribution Figure 1 Offset Voltage Drift Production Distribution Figure 2 Open-Loop Gain vs Frequency Figure 3 Common-Mode Rejection Ratio vs Frequency Figure 4 Power-Supply Rejection Ratio vs Frequency Figure 5 Output Voltage Swing vs Output Current Figure 6 Input Bias Current vs Common-Mode Voltage Figure 7 Input Bias Current vs Temperature Figure 8 Quiescent Current vs Temperature Figure 9 Large-Signal Step Response Figure 10 Small-Signal Step Response Figure 11 Positive Overvoltage Recovery Figure 12 Negative Overvoltage Recovery Figure 13 Settling Time vs Closed-Loop Gain Figure 14 Small-Signal Overshoot vs Load Capacitance Figure 15 0.1-Hz to 10-Hz Noise Figure 16 Current and Voltage Noise Spectral Density vs Frequency Figure 17 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 0 0.0025 0.0050 0.0075 0.0100 0.0125 0.0150 0.0175 0.0200 0.0225 0.0250 0.0275 0.0300 0.0325 0.0350 0.0375 0.0400 0.0425 0.0450 0.0475 0.0500 Population Population At TA = 25°C, VS = 5 V, and CL = 0 pF, unless otherwise noted. Offset Voltage (mV) Offset Voltage Drift (mV/°C) Figure 1. Offset Voltage Production Distribution 8 Figure 2. Offset Voltage Drift Production Distribution Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 OPA333, OPA2333 www.ti.com SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 At TA = 25°C, VS = 5 V, and CL = 0 pF, unless otherwise noted. 140 100 200 120 150 100 AOL (dB) 80 Phase 60 100 40 50 20 CMRR (dB) 250 Phase (°) 120 80 60 0 40 -50 20 -100 0 Gain 0 -20 10 100 1k 10k 100k 1 1M 10 100 1k 10k 100k Figure 4. Common-Mode Rejection Ratio vs Frequency Figure 3. Open-Loop Gain and Phase vs Frequency 120 3 VS = ±2.75 V VS = ±0.9 V +PSRR 2 -PSRR Output Swing (V) PSRR (dB) 100 80 60 40 20 0 10 100 1k 10k 100k +25°C +125°C 0 +25°C -40°C -1 +125°C +25°C -40°C -3 1M 0 1 2 3 4 5 6 7 8 9 10 Frequency (Hz) Output Current (mA) Figure 5. Power-Supply Rejection Ratio vs Frequency Figure 6. Output Voltage Swing vs Output Current 100 200 80 150 -IB 60 VS = 5.5 V VS = 1.8 V -IB 100 40 -IB 50 20 IB (pA) IB (pA) -40°C 1 -2 1 1M Frequency (Hz) Frequency (Hz) 0 -20 0 +IB -50 -40 -100 -60 +IB -100 0 1 +IB -150 -80 2 3 4 5 -200 -50 -25 Common-Mode Voltage (V) Figure 7. Input Bias Current vs Common-Mode Voltage 0 25 50 75 100 125 Temperature (°C) Figure 8. Input Bias Current vs Temperature Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 9 OPA333, OPA2333 SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 www.ti.com At TA = 25°C, VS = 5 V, and CL = 0 pF, unless otherwise noted. 25 G=1 RL = 10 kW Output Voltage (1 V/div) 20 VS = 5.5 V IQ (mA) 15 VS = 1.8 V 10 5 0 -50 -25 0 25 50 75 100 125 Time (50 ms/div) Temperature (°C) G = +1 RL = 10 kW Output Voltage (50 mV/div) Figure 10. Large-Signal Step Response 2 V/div Figure 9. Quiescent Current vs Temperature 0 Input Output 10 kW +2.5 V 1 V/div 1 kW 0 OPA333 -2.5 V Time (5 ms/div) Time (50 ms/div) Figure 11. Small-Signal Step Response Figure 12. Positive Overvoltage Recovery 600 Input 0 0 10 kW +2.5 V Settling Time (ms) 1 V/div 2 V/div 4-V Step 500 400 300 200 0.001% 1 kW Output OPA333 100 -2.5 V 0 0.01% 1 10 10 100 Time (50 ms/div) Gain (dB) Figure 13. Negative Overvoltage Recovery Figure 14. Settling Time vs Closed-Loop Gain Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 OPA333, OPA2333 www.ti.com SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 At TA = 25°C, VS = 5 V, and CL = 0 pF, unless otherwise noted. 40 35 25 500nV/div Overshoot (%) 30 20 15 10 5 0 100 1000 1s/div Load Capacitance (pF) Figure 16. 0.1-Hz to 10-Hz Noise Figure 15. Small-Signal Overshoot vs Load Capacitance 1000 Voltage Noise (nV/ÖHz) 1000 Continues with no 1/f (flicker) noise. Current Noise 100 100 Voltage Noise Current Noise (fA/ÖHz) 10 10 10 1 10 100 1k 10k Frequency (Hz) Figure 17. Current and Voltage Noise Spectral Density vs Frequency Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 11 OPA333, OPA2333 SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 www.ti.com 7 Detailed Description 7.1 Overview The OPAx333 is a family of Zero-Drift, low-power, rail-to-rail input and output operational amplifiers. These devices operate from 1.8 V to 5.5 V, are unity-gain stable, and are suitable for a wide range of general-purpose applications. The Zero-Drift architecture provides ultra low offset voltage and near-zero offset voltage drift. 7.2 Functional Block Diagram C2 CHOP1 GM1 CHOP2 Notch Filter GM2 GM3 +IN OUT -IN C1 GM_FF 7.3 Feature Description The OPA333 and OPA2333 are unity-gain stable and free from unexpected output phase reversal. These devices use a proprietary auto-calibration technique to provide low offset voltage and very low drift over time and temperature. For lowest offset voltage and precision performance, optimize circuit layout and mechanical conditions. Avoid temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed from connecting dissimilar conductors. Cancel these thermally-generated potentials by assuring they are equal on both input terminals. Other layout and design considerations include: • Use low thermoelectric-coefficient conditions (avoid dissimilar metals). • Thermally isolate components from power supplies or other heat sources. • Shield operational amplifier and input circuitry from air currents, such as cooling fans. Following these guidelines reduces the likelihood of junctions being at different temperatures, which can cause thermoelectric voltages of 0.1 μV/°C or higher, depending on materials used. 7.3.1 Operating Voltage The OPA333 and OPA2333 operational amplifiers operate over a power-supply range of 1.8 V to 5.5 V (±0.9 V to ±2.75 V). Parameters that vary over supply voltage or temperature are shown in the Typical Characteristics section. CAUTION Supply voltages higher than +7 V (absolute maximum) can permanently damage the device. 12 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 OPA333, OPA2333 www.ti.com SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 Feature Description (continued) 7.3.2 Input Voltage The OPA333 and OPA2333 input common-mode voltage range extends 0.1 V beyond the supply rails. The OPA333 is designed to cover the full range without the troublesome transition region found in some other rail-torail amplifiers. Typically, input bias current is approximately 70 pA; however, input voltages that exceed the power supplies can cause excessive current to flow into or out of the input pins. Momentary voltages greater than the power supply can be tolerated if the input current is limited to 10 mA. This limitation is easily accomplished with an input resistor, as shown in Figure 18. Current-limiting resistor required if input voltage exceeds supply rails by ³ 0.5 V. +5 V IOVERLOAD 10 mA max VOUT OPA333 VIN 5 kW Figure 18. Input Current Protection 7.3.3 Internal Offset Correction The OPA333 and OPA2333 operational amplifiers use an auto-calibration technique with a time-continuous 350-kHz operational amplifier in the signal path. This amplifier is zero-corrected every 8 μs using a proprietary technique. Upon power up, the amplifier requires approximately 100 μs to achieve specified VOS accuracy. This design has no aliasing or flicker noise. 7.3.4 Achieving Output Swing to the Op Amp Negative Rail Some applications require output voltage swings from 0 V to a positive full-scale voltage (such as 2.5 V) with excellent accuracy. With most single-supply operational amplifiers, problems arise when the output signal approaches 0 V, near the lower output swing limit of a single-supply operational amplifier. A good, single-supply operational amplifier may swing close to single-supply ground, but does not reach ground. The output of the OPA333 and OPA2333 can be made to swing to, or slightly below, ground on a single-supply power source. This swing is achieved with the use of the use of another resistor and an additional, more negative power supply than the operational amplifier negative supply. A pulldown resistor can be connected between the output and the additional negative supply to pull the output down below the value that the output would otherwise achieve, as shown in Figure 19. V+ = +5 V VOUT OPA333 VIN RP = 20 kW Op Amp V- = GND -5 V Additional Negative Supply Figure 19. VOUT Range to Ground Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 13 OPA333, OPA2333 SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 www.ti.com Feature Description (continued) The OPA333 and OPA2333 have an output stage that allows the output voltage to be pulled to the negative supply rail, or slightly below, using the technique previously described. This technique only works with some types of output stages. The OPA333 and OPA2333 are characterized to perform with this technique; the recommended resistor value is approximately 20 kΩ. NOTE This configuration increases the current consumption by several hundreds of microamps. Accuracy is excellent down to 0 V and as low as –2 mV. Limiting and nonlinearity occur below –2 mV, but excellent accuracy returns after the output is again driven above –2 mV. Lowering the resistance of the pulldown resistor allows the operational amplifier to swing even further below the negative rail. Resistances as low as 10 kΩ can be used to achieve excellent accuracy down to –10 mV. 7.3.5 DFN Package The OPA2333 is offered in an DFN-8 package (also known as SON). The DFN is a QFN package with lead contacts on only two sides of the bottom of the package. This leadless package maximizes board space and enhances thermal and electrical characteristics through an exposed pad. DFN packages are physically small, have a smaller routing area, improved thermal performance, and improved electrical parasitics. Additionally, the absence of external leads eliminates bent-lead issues. The DFN package can be easily mounted using standard PCB assembly techniques. See Application Reports SLUA271, QFN/SON PCB Attachment and SCBA017, Quad Flatpack No-Lead Logic Packages, both are available for download at www.ti.com. NOTE The exposed leadframe die pad on the bottom of the package should be connected to V– or left unconnected. 7.4 Device Functional Modes The OPAx333 device has a single functional mode. The device is powered on as long as the power supply voltage is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V). 14 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 OPA333, OPA2333 www.ti.com SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The OPAx333 family is a unity-gain stable, precision operational amplifier with very low offset voltage drift; these devices are also free from output phase reversal. Applications with noisy or high-impedance power supplies require decoupling capacitors close to the device power-supply pins. In most cases, 0.1-μF capacitors are adequate. 8.2 Typical Applications 8.2.1 High-Side Voltage-to-Current (V-I) Converter The circuit shown in Figure 20 is a high-side voltage-to-current (V-I) converter. It translates in input voltage of 0 V to 2 V to and output current of 0 mA to 100 mA. Figure 21 shows the measured transfer function for this circuit. The low offset voltage and offset drift of the OPA333 facilitate excellent dc accuracy for the circuit. V+ RS2 RS3 IRS2 470 VRS2 IRS3 4.7 10 k R4 VRS3 C7 2200 pF R5 A2 + V+ 200 + 330 Q2 Q1 A1 R3 VIN + ± 1000 pF C6 10 k VRS1 R2 RS1 2k IRS1 VLOAD RLOAD ILOAD Figure 20. High-Side Voltage-to-Current (V-I) Converter Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 15 OPA333, OPA2333 SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 www.ti.com Typical Applications (continued) 8.2.1.1 Design Requirements The design requirements are as follows: • Supply Voltage: 5 V DC • Input: 0 V to 2 V DC • Output: 0 mA to 100 mA DC 8.2.1.2 Detailed Design Procedure The V-I transfer function of the circuit is based on the relationship between the input voltage, VIN, and the three current sensing resistors, RS1, RS2, and RS3. The relationship between VIN and RS1 determines the current that flows through the first stage of the design. The current gain from the first stage to the second stage is based on the relationship between RS2 and RS3. For a successful design, pay close attention to the dc characteristics of the operational amplifier chosen for the application. To meet the performance goals, this application benefits from an operational amplifier with low offset voltage, low temperature drift, and rail-to-rail output. The OPA2333 CMOS operational amplifier is a highprecision, 5-uV offset, 0.05-μV/°C drift amplifier optimized for low-voltage, single-supply operation with an output swing to within 50 mV of the positive rail. The OPA2333 family uses chopping techniques to provide low initial offset voltage and near-zero drift over time and temperature. Low offset voltage and low drift reduce the offset error in the system, making these devices appropriate for precise dc control. The rail-to-rail output stage of the OPA2333 ensures that the output swing of the operational amplifier is able to fully control the gate of the MOSFET devices within the supply rails. A detailed error analysis, design procedure, and additional measured results are given in TIPD102. 8.2.1.3 Application Curve 0.1 Load Output Current (A) 0.075 0.05 0.025 0 0 0.5 1 Input Voltage (V) 1.5 2 D001 Figure 21. Measured Transfer Function for High-Side V-I Converter 16 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 OPA333, OPA2333 www.ti.com SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 Typical Applications (continued) 8.2.2 Precision, Low-Level Voltage-to-Current (V-I) Converter The circuit shown in Figure 22 is a precision, low-level voltage-to-current (V-I) converter. The converter translates in input voltage of 0 V to 5 V and output current of 0 µA to 5 µA. Figure 23 shows the measured transfer function for this circuit. The low offset voltage and offset drift of the OPA333 facilitate excellent dc accuracy for the circuit. Figure 24 shows the calibrated error for the entire range of the circuit. R3 100 k C1 10 nF R4 100 k 5V VOUT_OPA OPA333 +R1 + U2 INA326 R1 40.2 k Rset 100 k + 5V VOUT_INA R1 ± VIN RLOAD IOUT R2 R2 200 k C2 1 nF + A AM1 Figure 22. Low-Level, Precision V-I Converter 8.2.2.1 Design Requirements The design requirements are as follows: • Supply Voltage: 5 V DC • Input: 0 V to 5 V DC • Output: 0 μA to 5 μA DC 8.2.2.2 Detailed Design Procedure The V-I transfer function of the circuit is based on the relationship between the input voltage, VIN, RSET, and the instrumentation amplifier (INA) gain. During operation, the input voltage divided by the INA gain appears across the set resistor in Equation 1: VSET = VIN/GINA (1) The current through RSET must flow through the load, so IOUT is VSET / RSET. IOUT remains a well-regulated current as long as the total voltage across RSET and RLOAD does not violate the output limits of the operational amplifier or the input common-mode limits of the INA. The voltage across the set resistor (VSET) is the input voltage divided by the INA gain (that is, VSET = 1 V / 10 = 0.1 V). The current is determined by VSET and RSET shown in Equation 2: IOUT = VSET / RSET = 0.1 V / 100 kΩ = 1 μA (2) A detailed error analysis, design procedure, and additional measured results are given in TIPD107. Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 17 OPA333, OPA2333 SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 www.ti.com Typical Applications (continued) 8.2.2.3 Application Curves 100 Measured Output Current Error (pA) Output Current (µA) 0.1 0.075 0.05 0.025 0 0 80 60 40 20 0 –20 –40 –60 –80 –100 1 3 2 Input Voltage (V) 5 4 0 1 3 4 2 Desired Output Current, Iout_desired (µA) D002 Figure 23. Measured Transfer Function for Low-Level Precision V-I 5 D002 Figure 24. Calibrated Output Error for Low-Level V-I 8.2.3 Composite Amplifier The circuit shown in Figure 25 is a composite amplifier used to drive the reference on the ADS8881. The OPA333 provides excellent dc accuracy, and the THS4281 allows the output of the circuit to respond quickly to the transient current requirements of a typical SAR data converter reference input. The ADS8881 system was optimized for THD and achieved a measured performance of –110 dB. The linearity of the ADC is shown Figure 26. REFERENCE DRIVE CIRCUIT 20k 1µF THS4281 + - 1k AVDD + 0.2 1µF AVDD + OPA333 + Vout AVDD 10µF REF5045 1k Vin Temp 1µF Trim Gnd 1µF 1K 1K AVDD AVDD VIN+ THS4521 + + - VCM - 10 REFP AVDD AINP V+ 10nF + AINM 10 GND CONVST + VIN- CONVST ADS8881 1K 1K INPUT DRIVER 18-Bit 1MSPS SAR ADC Figure 25. Composite Amplifier Reference Driver Circuit 18 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 OPA333, OPA2333 www.ti.com SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 Typical Applications (continued) 8.2.3.1 Design Requirements The design requirements for this block design are: • System Supply Voltage: 5 V DC • ADC Supply Voltage: 3.3 V DC • ADC Sampling Rate: 1 MSPS • ADC Reference Voltage (VREF): 4.5 V DC • ADC Input Signal: A differential input signal with amplitude of Vpk = 4.315 V (–0.4 dBFS to avoid clipping) and frequency, fIN = 10 kHz are applied to each differential input of the ADC 8.2.3.2 Detailed Design Procedure The two primary design considerations to maximize the performance of a high-resolution SAR ADC are the input driver and the reference driver design. The circuit comprises the critical analog circuit blocks, the input driver, anti-aliasing filter, and the reference driver. Each analog circuit block should be carefully designed based on the ADC performance specifications in order to maximize the distortion and noise performance of the data acquisition system while consuming low power. The diagram includes the most important specifications for each individual analog block. This design systematically approaches the design of each analog circuit block to achieve a 16-bit, low-noise and low-distortion data acquisition system for a 10-kHz sinusoidal input signal. The first step in the design requires an understanding of the requirement of extremely low distortion input driver amplifier. This understanding helps in the decision of an appropriate input driver configuration and selection of an input amplifier to meet the system requirements. The next important step is the design of the anti-aliasing RC-filter to attenuate ADC kick-back noise while maintaining the amplifier stability. The final design challenge is to design a highprecision reference driver circuit, which would provide the required value VREF with low offset, drift, and noise contributions. In designing a very low distortion data acquisition block, it is important to understand the sources of nonlinearity. Both the ADC and the input driver introduce nonlinearity in a data acquisition block. To achieve the lowest distortion, the input driver for a high-performance SAR ADC must have a distortion that is negligible against the ADC distortion. This parameter requires the input driver distortion to be 10 dB lower than the ADC THD. This stringent requirement ensures that overall THD of the system is not degraded by more than –0.5 dB. THDAMP < THDADC – 10 dB (3) It is therefore important to choose an amplifier that meets the above criteria to avoid the system THD from being limited by the input driver. The amplifier nonlinearity in a feedback system depends on the available loop gain. A detailed error analysis, design procedure, and additional measured results are given in TIPD115. 8.2.3.3 Application Curve Integral Non-Linearity Error (LSB) 1.5 1 0.5 0 –0.5 –1 –1.5 –4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 ADC Differential Input 2.5 3.5 4.5 D002 Figure 26. Linearity of the ADC8881 System Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 19 OPA333, OPA2333 SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 www.ti.com 8.3 System Examples 8.3.1 Temperature Measurement Application Figure 27 shows a temperature measurement application. REF3140 +5 V 0.1 mF 4.096 V + R9 150 kW R1 6.04 kW R5 31.6 kW D1 +5 V 0.1 mF + - R2 2.94 kW - + + R2 549 W R4 6.04 kW VO OPA333 R6 200 W K-Type Thermocouple 40.7 mV/°C Zero Adjust R3 60.4 W Figure 27. Temperature Measurementf 8.3.2 Single Operational Amplifier Bridge Amplifier Application Figure 28 shows the basic configuration for a bridge amplifier. VEX R1 +5 V R R R R VOUT OPA333 R1 VREF Figure 28. Single Operational Amplifier Bridge Amplifier 8.3.3 Low-Side Current Monitor Application A low-side current shunt monitor is shown in Figure 29. RN are operational resistors used to isolate the ADS1100 from the noise of the digital I2C bus. The ADS1100 is a 16-bit converter; therefore, a precise reference is essential for maximum accuracy. If absolute accuracy is not required and the 5-V power supply is sufficiently stable, the REF3130 can be omitted. 3V +5 V REF3130 Load R1 4.99 kW R2 49.9 kW R6 71.5 kW V ILOAD RSHUNT 1W RN 56 W OPA333 R3 4.99 kW Stray Ground-Loop Resistance R4 48.7 kW ADS1100 R7 1.18 kW RN 56 W 2 IC (PGA Gain = 4) FS = 3.0 V NOTE: 1% resistors provide adequate common-mode rejection at small ground-loop errors. Figure 29. Low-Side Current Monitor 20 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 OPA333, OPA2333 www.ti.com SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 8.3.4 Other Applications Additional application ideas are shown in Figure 30 through Figure 33. RG zener RSHUNT (1) V+ (2) R1 10 kW MOSFET rated to stand-off supply voltage such as BSS84 for up to 50 V. OPA333 +5V V+ Two zener biasing methods (3) are shown. Output Load RBIAS RL (1) Zener rated for op amp supply capability (that is, 5.1 V for OPA333). (2) Current-limiting resistor. (3) Choose zener biasing resistor or dual N-MOSFETs (FDG6301N, NTJD4001N, or Si1034). Figure 30. High-Side Current Monitor 100 kW 1 MW 60 kW 3V NTC Thermistor 1 MW OPA333 Figure 31. Thermistor Measurement V1 -In INA152 OPA333 R2 R1 2 5 6 VO R2 3 1 OPA333 V2 +In VO = (1 + 2R2 / R1) (V2 - V1) Figure 32. Precision Instrumentation Amplifier Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 21 OPA333, OPA2333 SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 www.ti.com +VS R1 100 kW fLPF = 150 Hz C4 1.06 nF 1/2 OPA2333 RA +VS R2 100 kW R6 100 kW 1/2 OPA2333 +VS 3 2 LL 7 INA321 (1) 4 5 R8 100 kW +VS ac dc R3 100 kW 1/2 OPA2333 GINA = 5 R12 5 kW 6 +VS 1 C3 1 mF VOUT OPA333 R13 318 kW GOPA = 200 +VS 1/2 OPA2333 Wilson LA R14 1 MW GTOT = 1 kV/V R7 100 kW VCENTRAL C1 47 pF (RA + LA + LL) / 3 fHPF = 0.5 Hz (provides ac signal coupling) 1/2 VS R5 390 kW R9 20 kW +VS R4 100 kW RL 1/2 OPA2333 Inverted VCM +VS VS = +2.7 V to +5.5 V BW = 0.5 Hz to 150 Hz 1/2 OPA2333 +VS R10 1 MW 1/2 VS C2 0.64 mF R11 1 MW fO = 0.5 Hz (1) Other instrumentation amplifiers can be used, such as the INA326, which has lower noise, but higher quiescent current. Figure 33. Single-Supply, Very Low Power, ECG Circuit 9 Power Supply Recommendations The OPAx333 is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply from –40°C to 125°C. The Typical Characteristics presents parameters that can exhibit significant variance with regard to operating voltage or temperature. CAUTION Supply voltages larger than 7 V can permanently damage the device (see the Absolute Maximum Ratings). TI recommends placing 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout section. 22 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 OPA333, OPA2333 www.ti.com SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 10 Layout 10.1 Layout Guidelines 10.1.1 General Layout Guidelines Pay attention to good layout practices. Keep traces short and when possible, use a printed-circuit-board (PCB) ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1-μF capacitor closely across the supply pins. Apply these guidelines throughout the analog circuit to improve performance and provide benefits, such as reducing the electromagnetic interference (EMI) susceptibility. Operational amplifiers vary in susceptibility to radio frequency interference (RFI). RFI can generally be identified as a variation in offset voltage or DC signal levels with changes in the interfering RF signal. The OPA333 is specifically designed to minimize susceptibility to RFI and demonstrates remarkably low sensitivity compared to previous generation devices. Strong RF fields may still cause varying offset levels. 10.1.2 DFN Layout Guidelines Solder the exposed leadframe die pad on the DFN package to a thermal pad on the PCB. A mechanical drawing showing an example layout is attached at the end of this data sheet. Refinements to this layout may be necessary based on assembly process requirements. Mechanical drawings located at the end of this data sheet list the physical dimensions for the package and pad. The five holes in the landing pattern are optional, and are intended for use with thermal vias that connect the leadframe die pad to the heatsink area on the PCB. Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push, package shear, and similar board-level tests. Even with applications that have low-power dissipation, the exposed pad must be soldered to the PCB to provide structural integrity and long-term reliability. 10.2 Layout Example + VIN VOUT RG RF (Schematic Representation) Run the input traces as far away from the supply lines as possible Place components close to device and to each other to reduce parasitic errors VS+ RF N/C N/C GND ±IN V+ VIN +IN OUTPUT V± N/C RG Use low-ESR, ceramic bypass capacitor GND VS± GND Use low-ESR, ceramic bypass capacitor VOUT Ground (GND) plane on another layer Figure 34. Layout Example Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 23 OPA333, OPA2333 SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support For development support on this product, see the following: • High-Side V-I Converter, 0 V to 2 V to 0 mA to 100 mA, 1% Full-Scale Error, TIPD102 • Low-Level V-to-I Converter Reference Design, 0-V to 5-V Input to 0-µA to 5-µA Output, TIPD107 • 18-Bit, 1-MSPS, Serial Interface, microPower, Truly-Differential Input, SAR ADC, ADS8881 • Very Low-Power, High-Speed, Rail-To-Rail Input/Output, Voltage Feedback Operational Amplifier, THS4281 • Data Acquisition Optimized for Lowest Distortion, Lowest Noise, 18-bit, 1-MSPS Reference Design, TIPD115 • Self-Calibrating, 16-Bit Analog-to-Digital Converter, ADS1100 • 20-ppm/Degrees C Max, 100-µA, SOT23-3 Series Voltage Reference, REF3130 • Precision, Low Drift, CMOS Instrumentation Amplifier, INA326, INA326 11.2 Documentation Support 11.2.1 Related Documentation For related documentation, see the following: • QFN/SON PCB Attachment, SLUA271 • Quad Flatpack No-Lead Logic Packages, SCBA017 11.3 Related Links Table 2 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY OPA333 Click here Click here Click here Click here Click here OPA2333 Click here Click here Click here Click here Click here 11.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.5 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 24 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 OPA333, OPA2333 www.ti.com SBOS351E – MARCH 2006 – REVISED DECEMBER 2015 11.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: OPA333 OPA2333 25 PACKAGE OPTION ADDENDUM www.ti.com 7-Feb-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) OPA2333AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 O2333A OPA2333AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 O2333A OPA2333AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 OBAQ OPA2333AIDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 OBAQ OPA2333AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 OBAQ OPA2333AIDGKTG4 ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 OBAQ OPA2333AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 O2333A OPA2333AIDRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BQZ OPA2333AIDRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BQZ OPA2333AIDRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BQZ OPA2333AIDRBTG4 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BQZ OPA2333AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 O2333A OPA333AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 O333A OPA333AIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 OAXQ OPA333AIDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 OAXQ OPA333AIDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 OAXQ OPA333AIDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 OAXQ Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 7-Feb-2015 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) OPA333AIDCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BQY OPA333AIDCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BQY OPA333AIDCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BQY OPA333AIDCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BQY OPA333AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 O333A OPA333AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 O333A OPA333AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 O333A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 7-Feb-2015 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF OPA2333, OPA333 : • Automotive: OPA2333-Q1, OPA333-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing OPA2333AIDGKR VSSOP DGK 8 OPA2333AIDGKT VSSOP DGK OPA2333AIDR SOIC D OPA2333AIDRBR SON OPA2333AIDRBT SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 OPA333AIDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 OPA333AIDBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 OPA333AIDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 OPA333AIDCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 OPA333AIDCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 OPA333AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA2333AIDGKR VSSOP DGK 8 2500 364.0 364.0 27.0 OPA2333AIDGKT VSSOP DGK 8 250 364.0 364.0 27.0 OPA2333AIDR SOIC D 8 2500 367.0 367.0 35.0 OPA2333AIDRBR SON DRB 8 3000 367.0 367.0 35.0 OPA2333AIDRBT SON DRB 8 250 210.0 185.0 35.0 OPA333AIDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 OPA333AIDBVR SOT-23 DBV 5 3000 203.0 203.0 35.0 OPA333AIDBVT SOT-23 DBV 5 250 180.0 180.0 18.0 OPA333AIDCKR SC70 DCK 5 3000 203.0 203.0 35.0 OPA333AIDCKT SC70 DCK 5 250 203.0 203.0 35.0 OPA333AIDR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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