Infineon IFX1763XEJV50 Wide input range low noise 500ma 5v ldo Datasheet

IFX1763 V50
Wide Input Range Low Noise 500mA 5V LDO
IFX1763XEJV50
IFX1763LDV50
Data Sheet
Rev. 1.11, 2015-01-30
Standard Power
Wide Input Range Low Noise 500mA 5V LDO
1
IFX1763XEJV50
IFX1763LDV50
Overview
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low Noise down to 42 µVRMS (BW = 10 Hz to 100 kHz)
500mA Current Capability
Low Quiescent Current: 30 µA
Wide Input Voltage Range up to 20 V
Internal circuitry working down to 1.8 V
2.5% Output Voltage Accuracy (over full temperature and load range)
Low Dropout Voltage: 350 mV
Very low Shutdown Current: < 1 µA
No Protection Diodes Needed
Fixed Output Voltage: 5.0 V
Stable with ≥ 3.3 µF Output Capacitor
Stable with Aluminium, Tantalum or Ceramic Capacitors
Reverse Battery Protection
No Reverse Current
Overcurrent and Overtemperature Protected
PG-DSO-8 Exposed Pad and TSON-10 Exposed Pad Packages
Green Product (RoHS compliant)
PG-DSO-8 Exposed Pad
PG-TSON-10
Applications
•
•
•
•
•
Microcontroller Supply
Battery-Powered Systems
Noise Sensitive Instruments
Radar Applications
Image Sensors
The IFX1763 V50 is not qualified and manufactured according to the requirements of Infineon Technologies with
regards to automotive and/or transportation applications. For automotive applications please refer to the Infineon
TLx (TLE, TLS, TLF.....) voltage regulator products.
Type
Package
Marking
IFX1763XEJV50
PG-DSO-8 Exposed Pad
1763EV50
IFX1763LDV50
PG-TSON-10
176LV50
Data Sheet
2
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
Overview
The IFX1763 V50 is a micropower, low noise, low dropout 5 V voltage regulator. The device is capable of
supplying an output current of 500 mA with a dropout voltage of 350 mV. Designed for use in battery-powered
systems, the low quiescent current of 30 µA makes it an ideal choice.
One feature of the IFX1763 V50 is its low output noise: by adding an external 0.01 µF bypass capacitor output
noise values down to 42 µVRMS over a 10 Hz to 100 kHz bandwidth can be reached. The IFX1763 V50 voltage
regulator is stable with output capacitors as small as 3.3 µF. Small ceramic capacitors can be used without the
series resistance required by many other regulators. Its internal protection circuitry includes reverse battery
protection, current limiting and reverse current protection. The IFX1763 V50 is available in a PG-DSO-8 Exposed
Pad and as well as in a TSON10 exposed pad package.
Data Sheet
3
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
Block Diagram
2
Block Diagram
Note: Pin numbers in the block diagram refer to the DSO-8 EP package type.
Saturation
Control
IFX1763
IN 8
1 OUT
EN 5
Bias
BYP 4
Voltage
reference
Over Current
Protection
Temperature
Protection
Error
Amplifier
2
SENSE
6
GND
Figure 1
Data Sheet
Block Diagram IFX1763 V50
4
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
OUT
1
8
IN
SENSE
2
7
NC
NC
3
6
GND
5
EN
9
BYP
4
IFX1763 XEJ V50
Figure 2
Pin Configuration of IFX1763XEJV50 in PG-DSO-8 Exposed Pad
OUT
OUT
NC
SENSE
BYP
1
2
3
4
5
11
10
9
8
7
6
IN
IN
NC
EN
GND
IFX1763LD V50
Figure 3
Data Sheet
Pin Configuration of IFX1763LDV50 in PG-TSON10
5
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
Pin Configuration
3.2
Pin Definitions and Functions
Pin
Symbol
Function
1 (DSO-8 EP)
1,2 (TSON-10)
OUT
Output. Supplies power to the load. For this pin a minimum output capacitor of
3.3 µF is required to prevent oscillations. Larger output capacitors may be
required for applications with large transient loads in order to limit peak voltage
transients or when the regulator is applied in conjunction with a bypass capacitor.
For more details please refer to the section “Application Information” on
Page 19.
2 (DSO-8 EP)
4 (TSON-10)
SENSE
Output Sense. The SENSE pin is the input to the error amplifier. This allows to
achieve an optimized regulation performance in case of small voltage drops Rp
that occur between regulator and load. In applications where such drops are
relevant they can be eliminated by connecting the SENSE pin directly at the load.
In standard configurations the SENSE pin can be connected directly to the OUT
pin. For further details please refer to the section “Kelvin Sense Connection”
on Page 19.
3, 7 (DSO-8 EP) NC
3, 8 (TSON-10)
No Connect. The NC Pins have no connection to any internal circuitry. Connect
either to GND or leave open.
4 (DSO-8)
5 (TSON-10)
BYP
Bypass. The BYP pin is used to bypass the reference of the IFX1763 V50 to
achieve low noise performance. The BYP-pin is clamped internally to ±0.6 V (i.e.
one VBE). A small capacitor from the output to the BYP pin will bypass the
reference to lower the output voltage noise1). If not used this pin must be left
unconnected.
5 (DSO-8 EP)
7 (TSON-10)
EN
Enable. With the EN pin the IFX1763 V50 can be put into a low power shutdown
state. The output will be off when the EN is pulled low. The EN pin can be driven
by 5V logic or open-collector logic with pull-up resistor. The pull-up resistor is
required to supply the pull-up current of the open-collector gate2) and the EN pin
current3). Please note that if the EN pin is not used it must be connected to VIN. It
must not be left floating.
6 (DSO-8 EP)
6,(TSON-10)
GND
Ground.
8 (DSO-8 EP)
IN
9, 10 (TSON-10)
Input. Via the input pin IN the power is supplied to the device. A capacitor at the
input pin is required if the device is more than 6 inches away from the main input
filter capacitor or if bigger inductance is present at the IN pin4). The IFX1763 V50
is designed to withstand reverse voltages on the Input pin with respect to GND
and Output. In the case of reverse input (e.g. due to a wrongly attached battery)
the device will act as if there is a diode in series with its input. In this way there will
be no reverse current flowing into the regulator and no reverse voltage will appear
at the load. Hence, the device will protect both - the device itself and the load.
9 (DSO-8 EP)
11 (TSON-10)
Exposed Pad. To ensure proper thermal performance, solder Pin 11 (exposed
pad) of TSON10 to the PCB ground and tie directly to Pin 6. In the case of DSO8 EP as well solder Pin 9 (exposed pad) to the PCB ground and tie directly to Pin
6.
1)
2)
3)
4)
Tab
A maximum value of 10 nF can be used for reducing output voltage noise over the bandwidth from 10 Hz to 100 kHz.
Normally several microamperes.
Typical value is 1 µA.
In general the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in batterypowered circuits. Depending on actual conditions an input capacitor in the range of 1 to 10 µF is sufficient.
Data Sheet
6
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Table 1
Absolute Maximum Ratings1)
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter
Symbol
Values
Unit
Note /
Number
Test Condition
Min.
Typ.
Max.
-20
–
20
V
–
P_4.1.1
VOUT
-20
VIN - VOUT -20
–
20
V
–
P_4.1.2
–
20
V
–
P_4.1.3
VSENSE
-20
–
20
V
–
P_4.1.4
VBYP
-0.6
–
0.6
V
VEN
-20
–
20
V
–
P_4.1.6
Tj
Tstg
-40
–
150
°C
–
P_4.1.7
-55
–
150
°C
–
P_4.1.8
VESD
VESD
-2
–
2
kV
HBM2)
P_4.1.9
-1
–
1
kV
CDM3)
P_4.1.10
Input Voltage
Voltage
VIN
Output Voltage
Voltage
Input to Output Differential
Voltage
Sense Pin
Voltage
BYP Pin
Voltage
P_4.1.5
Enable Pin
Voltage
Temperatures
Junction Temperature
Storage Temperature
ESD Susceptibility
All Pins
All Pins
1) Not subject to production test, specified by design.
2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5k Ω, 100 pF)
3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not
designed for continuous repetitive operation.
Data Sheet
7
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
General Product Characteristics
4.2
Functional Range
Table 2
Functional Range
Parameter
Symbol
Input Voltage Range
VIN
Tj
Operating Junction Temperature
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
5.5
–
20
V
–
P_4.2.1
-40
–
125
°C
–
P_4.2.2
Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the Electrical Characteristics table.
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Table 3
Thermal Resistance1)
Parameter
Symbol
Values
Min.
Typ.
Max.
–
7.0
–
Junction to Ambient
RthJC
RthJA
RthJA
RthJA
Junction to Ambient
Unit
Note /
Test Condition
Number
K/W
–
P_4.3.1
IFX1763X EJ (PG-DSO-8 Exposed Pad)
Junction to Case
Junction to Ambient
Junction to Ambient
–
39
–
K/W
–
2)
P_4.3.2
3)
–
155
–
K/W
Footprint only
–
66
–
K/W
300 mm2 heatsink
area on PCB3)
P_4.3.3
P_4.3.4
RthJA
–
52
–
K/W
600 mm2 heatsink
area on PCB3)
P_4.3.5
–
6.4
–
K/W
–
P_4.3.6
–
53
–
K/W
–2)
P_4.3.7
–
183
–
K/W
Footprint only3)
Junction to Ambient
RthJC
RthJA
RthJA
RthJA
–
69
–
K/W
300 mm heatsink
area on PCB3)
P_4.3.9
Junction to Ambient
RthJA
–
57
–
K/W
600 mm2 heatsink
area on PCB3)
P_4.3.10
IFX1763 LD (PG-TSON10)
Junction to Case
Junction to Ambient
Junction to Ambient
2
P_4.3.8
1) Not subject to production test, specified by design.
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).
Data Sheet
8
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
Electrical Characteristics
5
Electrical Characteristics
5.1
Electrical Characteristics Table
Table 4
Electrical Characteristics
-40 °C < Tj < 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless
otherwise specified.
Parameter
Symbol
Values
Unit
Note / Test Condition
Number
Min.
Typ.
Max.
VIN,min
–
1.8
2.3
V
IOUT = 500 mA
P_5.1.1
VOUT
4.875
5.00
5.125
V
1 mA < IOUT < 500 mA;
6 V < VIN < 20 V
P_5.1.2
∆VOUT
–
1
25
mV
∆VIN = 5.5 V to 20 V;
IOUT = 1 mA
P_5.1.3
Load Regulation
∆VOUT
–
16
32
mV
P_5.1.4
Load Regulation
∆VOUT
–
–
57
mV
TJ = 25°C; VIN= 6.0 V;
∆IOUT = 1 to 500 mA
VIN = 6.0V;
∆IOUT = 1 to 500 mA
Dropout Voltage
VDR
–
110
140
mV
P_5.1.6
Dropout Voltage
VDR
–
–
190
mV
Dropout Voltage
VDR
–
170
200
mV
Dropout Voltage
VDR
–
–
250
mV
Dropout Voltage
VDR
–
200
230
mV
Dropout Voltage
VDR
–
–
300
mV
Dropout Voltage
VDR
–
350
380
mV
Dropout Voltage
VDR
–
–
480
mV
IOUT = 10 mA;
VIN = VOUT,nom; TJ = 25°C
IOUT = 10 mA;
VIN = VOUT,nom
IOUT = 50 mA;
VIN = VOUT,nom; TJ = 25°C
IOUT = 50 mA;
VIN = VOUT,nom
IOUT = 100 mA;
VIN = VOUT,nom; TJ = 25°C
IOUT = 100 mA;
VIN = VOUT,nom
IOUT = 500 mA;
VIN = VOUT,nom; TJ = 25°C
IOUT = 500 mA;
VIN = VOUT,nom
GND Pin Current
IGND
–
30
60
µA
P_5.1.14
GND Pin Current
IGND
–
50
100
µA
VIN = VOUT,nom;
IOUT = 0 mA
VIN = VOUT,nom;
IOUT = 1 mA
1)
Minimum Operating Voltage
Minimum Operating Voltage
Output Voltage2)
Output Voltage
Line Regulation
Line Regulation
Load Regulation
P_5.1.5
Dropout Voltage3)
P_5.1.7
P_5.1.8
P_5.1.9
P_5.1.10
P_5.1.11
P_5.1.12
P_5.1.13
GND Pin Current4)
Data Sheet
9
P_5.1.15
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
Electrical Characteristics
Table 4
Electrical Characteristics (cont’d)
-40 °C < Tj < 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless
otherwise specified.
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note / Test Condition
Number
VIN = VOUT,nom;
P_5.1.16
IOUT = 50 mA
VIN = VOUT,nom;
P_5.1.17
IOUT = 100 mA
VIN = VOUT,nom;
P_5.1.18
IOUT = 250 mA
VIN = VOUT,nom;
P_5.1.19
IOUT = 500 mA; TJ ≥ 25°C
VIN = VOUT,nom;
P_5.1.20
IOUT = 500 mA; TJ < 25°C
GND Pin Current
IGND
–
300
850
µA
GND Pin Current
IGND
–
0.7
2.2
mA
GND Pin Current
IGND
–
3
8
mA
GND Pin Current
IGND
–
11
22
mA
GND Pin Current
IGND
–
11
31
mA
–
0.1
1
µA
VIN = 6 V; VEN = 0 V;
TJ = 25°C
P_5.1.21
Vth,EN
Vtl,EN
IEN
IEN
–
0.8
2.0
V
P_5.1.22
0.25
0.65
–
V
–
0.01
–
µA
–
1
–
µA
VOUT = Off to On
VOUT = On to Off
VEN = 0 V; TJ = 25°C
VEN = 20 V; TJ = 25°C
eno
–
55
–
µVRMS COUT = 10 µF ceramic;
CBYP = 10 nF;
IOUT = 500 mA;
P_5.1.26
Quiescent Current in Shutdown
Quiescent Current in Off-Mode Iq
(EN-pin low)
Enable
Enable Threshold High
Enable Threshold Low
EN Pin Current5)
EN Pin Current5)
P_5.1.23
P_5.1.24
P_5.1.25
6)
Output Voltage Noise
Output Voltage Noise
(BW = 10 Hz to100 kHz)
Output Voltage Noise
eno
–
44
–
µVRMS COUT = 10µF ceramic
P_5.1.27
+250mΩ resistor in series;
CBYP = 10 nF;
IOUT = 500 mA;
(BW = 10 Hz to100 kHz)
Output Voltage Noise
eno
–
42
–
µVRMS COUT = 22 µF ceramic;
CBYP = 10 nF;
IOUT = 500 mA;
P_5.1.28
(BW = 10 Hz to100 kHz)
Output Voltage Noise
eno
–
42
–
µVRMS COUT = 22 µF ceramic
P_5.1.29
+250mΩ resistor in series;
CBYP = 10 nF;
IOUT = 500 mA;
(BW = 10 Hz to100 kHz)
Power Supply Ripple Rejection6)
Power Supply Ripple Rejection PSRR
Data Sheet
50
65
–
10
dB
VIN - VOUT = 1.5 V (avg);
VRIPPLE = 0.5 Vpp;
fr = 120 Hz;
IOUT = 500mA
P_5.1.30
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
Electrical Characteristics
Table 4
Electrical Characteristics (cont’d)
-40 °C < Tj < 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless
otherwise specified.
Parameter
Symbol
Values
Unit
Note / Test Condition
Number
P_5.1.31
Min.
Typ.
Max.
520
–
–
mA
520
–
–
mA
VIN = 7 V; VOUT = 0 V
VIN = VOUT,nom + 1 V
∆VOUT = -0.1 V
Ileak,rev
–
–
1
mA
VIN = -20 V; VOUT = 0 V
P_5.1.33
IReverse
–
10
20
µA
VOUT = VOUT,nom;
VIN < VOUT,nom;
TJ = 25°C
P_5.1.34
COUT
ESR
3.3
–
–
µF
CBYP = 0 nF
P_5.1.35
8)
–
3
Ω
–
P_5.1.36
Output Current Limitation
IOUT,limit
IOUT,limit
Output Current Limit
Output Current Limit
P_5.1.32
Input Reverse Leakage Current
Input Reverse Leakage
Reverse Output Current
Reverse Output Current
7)
Output Capacitor6)
Output Capacitance
ESR
–
1) This parameter defines the minimum input voltage for which the device is powered up and provides the maximum nominal
output current of 500 mA. Under this minimum input voltage condition the IFX1763 V50 starts to be in tracking mode and
the output voltage will typically be in the range of around 1 V while providing the 500 mA.
2) The operation conditions are limited by the maximum junction temperature. The regulated output voltage specification will
only apply for conditions where the limit of the maximum junction temperature is fulfilled. It will therefore not apply for all
possible combinations of input voltage and output current. When operating at maximum input voltage, the output current
must be limited for thermal reasons. The same holds true when operating at maximum output current where the input
voltage range must be limited for thermal reasons.
3) The dropout voltage is the minimum input to output voltage differential needed to maintain regulation at a specified output
current. In dropout, the output voltage will be equal to VIN - VDR.
4) GND-pin current is tested with VIN = VOUT,nom and a current source load. This means that this parameter is tested while being
in dropout condition and thus reflects a worst case condition. The GND-pin current will in most cases decrease slightly at
higher input voltages - please also refer to the corresponding typical performance graphs.
5) The EN pin current flows into EN pin.
6) Not subject to production test, specified by design.
7) Reverse output current is tested with the IN pin grounded and the OUT pin forced to the rated output voltage. This current
flows into the OUT pin and out of the GND pin.
8) CBYP = 0 nF, COUT ≥ 3.3 µF; please note that for cases where a bypass capacitor at BYP is used - depending on the actual
applied capacitance of COUT and CBYP - a minimum requirement for ESR may apply. For further details please also refer to
the corresponding typical performance graph.
Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical
characteristics specified mean values expected over the production spread. If not otherwise specified,
typical characteristics apply at TA = 25°C and the given supply voltage.
Data Sheet
11
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
Typical Performance Characteristics
6
Typical Performance Characteristics
Guaranteed Dropout Voltage VDR versus
Output Current IOUT
500
500
450
450
400
400
350
350
300
300
Δ = Guaranteed Limits
VDR [mV]
VDR [mV]
Dropout Voltage VDR versus
Output Current IOUT
250
250
200
200
150
150
100
100
Tj = −40 °C
Tj = 25 °C
50
Tj ≤ 125 °C
Tj = 125 °C
0
0
100
200
300
IOUT [A]
400
Dropout Voltage VDR versus
Junction Temperature TJ
Tj ≤ 25 °C
50
0
500
0
100
200
300
IOUT [A]
400
500
Quiescent Current versus
Junction Temperature TJ
500
50
IOUT = 10 mA
450
IOUT = 100 mA
40
IOUT = 500 mA
350
35
300
30
Iq [µA]
VDR [mV]
400
45
IOUT = 50 mA
250
25
200
20
150
15
100
10
50
5
0
−50
Data Sheet
0
50
Tj [°C]
0
−50
100
12
VIN = 6 V
IOUT = 0 mA .
VEN = VIN
0
50
Tj [°C]
100
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
Typical Performance Characteristics
Output Voltage VOUT versus
Junction Temperature TJ
Quiescent Current Iq versus
Input Voltage VIN
800
5.08
700
5.06
600
5.04
500
IGND [µA]
VOUT [V]
5.02
5
4.98
400
300
4.96
VOUT,nom = 5.0 V
IOUT,nom = 0 mA
VEN = VIN
Tj = 25 °C
200
4.94
100
4.92
IOUT = 1 mA
4.9
−50
0
50
Tj [°C]
0
100
0
2
4
6
8
10
VIN [V]
GND Current IGND versus
Input Voltage VIN
GND Current IGND versus
Input Voltage VIN
1600
16
RLoad = 50.0 Ω / IOUT = 100 mA*
RLoad = 5.0 kΩ / IOUT = 1 mA*
RLoad = 100 Ω / IOUT = 50 mA*
1400
RLoad = 16.7 Ω / IOUT = 300 mA*
14
RLoad = 10.0 Ω / IOUT = 500 mA *.
[* for VOUT = 5.0 V]
Tj = 25°C
1200
10
IGND [mA]
IGND [µA]
1000
800
8
600
6
400
4
200
2
0
[* for VOUT = 5.0 V]
Tj = 25°C
12
0
2
4
6
8
0
10
VIN [V]
Data Sheet
0
2
4
6
8
10
VIN [V]
13
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
Typical Performance Characteristics
GND Current IGND versus
Output Current IOUT
EN Pin Threshold (On-to-Off) versus
Junction Temperature TJ
1.2
12
1 mA
500 mA
10
1
8
0.8
VEN,th [V]
IGND [mA]
VIN = 6 V
Tj = 25 ° C
6
0.6
4
0.4
2
0.2
0
0
100
200
300
IOUT [mA]
400
0
−50
500
0
50
Tj [°C]
100
EN Pin Current IEN versus
EN Pin Voltage VEN
EN Pin Threshold (Off-to-On) versus
Junction Temperature TJ
1.2
1.4
Tj = 25 °C
VIN = 20 V
1 mA
500 mA
1.2
1
1
IEN [µA]
VEN,th [V]
0.8
0.6
0.8
0.6
0.4
0.4
0.2
0
−50
Data Sheet
0.2
0
50
Tj [°C]
0
100
14
0
5
10
VEN [V]
15
20
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
Typical Performance Characteristics
Current Limit versus
Input Voltage VIN
EN Pin Current versus
Junction Temperature TJ
1.6
1
VEN = 20 V
VOUT = 0 V
Tj = 25 ° C
0.9
1.4
0.8
1.2
0.7
IOUT,max [A]
IEN [µA]
1
0.8
0.6
0.5
0.4
0.6
0.3
0.4
0.2
0.2
0
−50
0.1
0
50
Tj [°C]
0
100
Current Limit versus
Junction Temperature TJ
0
1
2
3
4
VIN [V]
5
6
7
Reverse Output Current versus
Output Voltage VOUT
1.2
90
VOUT.nom = 5.0 V (V50)
VIN = 7 V
VOUT = 0 V
80
1
70
VIN = 0 V
Tj = 25 °C
60
IOUT,rev [µA]
IOUT,max [A]
0.8
0.6
0.4
50
40
30
20
0.2
10
0
−50
Data Sheet
0
50
Tj [°C]
0
100
0
2
4
6
8
10
VOUT [V]
15
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
Typical Performance Characteristics
Minimum Input Voltage1) versus
Junction Temperature TJ
Reverse Output Current versus
Junction Temperature TJ
22
2.5
VOUT.nom = 5.0 V (V50)
20
18
16
2
VIN = 0 V
1.5
VIN,min [V]
IOUT,rev [µA]
14
12
10
1
8
6
0.5
4
IOUT = 100 mA
2
IOUT = 500 mA
0
−50
0
50
Tj [°C]
0
−50
100
0
50
Tj [°C]
100
Load Regulation versus
Junction Temperature TJ
0
VIN = 6.0 V; VOUT.nom = 5.0 V
−5
ΔVLoad [mV]
−10
−15
−20
−25
ΔILoad = 1 mA to 500 mA
−30
−50
1)
0
50
Tj [°C]
100
VIN,min is referred here as the minimum input voltage for which the requested current is provided and VOUT reaches 1 V.
Data Sheet
16
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
Typical Performance Characteristics
ESR(COUT) with CBYP = 10 nF versus
Output Capacitance COUT
ESR Stability versus
Output Current IOUT (for COUT = 3.3µF)
3
1
10
CByp = 10 nF
measurement limit
2.5
ESR(COUT) [Ω]
ESR(COUT) [Ω]
2
ESRmax CByp = 0 nF
0
10
ESRmin CByp = 0 nF
ESRmax CByp = 10 nF
ESRmin CByp = 10 nF
stable region above blue line
1.5
1
COUT = 3.3 µF
(0.06 Ω is measurement limit)
0.5
−1
10
0
100
200
300
IOUT [mA]
400
0
500
Input Ripple Rejection PSRR versus
Frequency f
2
3
4
5
COUT [µF]
6
7
Input Ripple Rejection PSRR versus
Junction Temperature TJ
68
100
VIN = VOUTnom + 1.5 V
Vripple = 0.5 Vpp
COUT = 10 µF
90
66
80
64
70
62
PSRR [dB]
PSRR [dB]
60
50
60
58
40
56
30
20
54
IOUT =500mA CBYP =0 nF
IOUT =500mA CBYP =10nF
10
52
IOUT =50mA CBYP =0 nF
Data Sheet
100
1k
f [Hz]
IOUT =500mA CBYP =0 nF
IOUT =500mA CBYP =10nF
IOUT =50mA CBYP =10nF
0
10
VIN = VOUTnom + 1.5 V
Vripple = 0.5 Vpp
fripple = 120 Hz
COUT = 10 µF
10k
50
−50
100k
17
0
50
Tj [°C]
100
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
Typical Performance Characteristics
Output Noise Spectral Density versus
Frequency (COUT = 10µF, IOUT = 50mA1))
Output Noise Spectral Density versus
Frequency (COUT = 22µF, IOUT = 50mA1))
1
1
10
10
COUT = 22 µF
IOUT = 50 mA
√
Output Spectral Noise Density μV/ Hz
√
Output Spectral Noise Density μV/ Hz
COUT = 10 µF
IOUT = 50 mA
0
10
−1
10
CByp = 0 nF; ESR(COUT)=0
CByp = 10 nF; ESR(COUT)=0
CByp = 10 nF; ESR(COUT)=250mΩ
−2
10
1
2
10
3
10
CByp = 0 nF; ESR(COUT)=0
CByp = 10 nF; ESR(COUT)=0
10
5
10
10
Transient Response CBYP = 0nF
1
2
10
3
10
4
10
f [Hz]
5
10
10
0,2
COUT = 10 µF
CBYP = 0 nF
VIN = 6V
0,3
COUT = 10 µF
CBYP = 10 nF
VIN = 6V
0,15
VOUT Deviation / [V]
0,2
0,1
0
0,1
0,05
0
-0,05
-0,1
-0,2
-0,1
-0,3
-0,15
-0,2
-0,4
0
100
200
300
400
500
Time (μs)
600
700
800
900
0
1000
20
40
60
80
60
80
100
120
140
160
180
200
100
120
140
160
180
200
Time / [μs]
600
600
IOUT : 100 to 500mA
IOUT : 100 to 500mA
500
500
400
400
Load Step / [mA]
Load Step / [mA]
CByp = 10 nF; ESR(COUT)=250mΩ
Transient Response CBYP = 10nF
0,4
VOUT Deviation / [V]
−1
10
−2
4
10
f [Hz]
0
10
300
200
300
200
100
100
0
0
0
100
200
300
400
500
Time (μs)
600
700
800
900
0
1000
20
40
Time / [μs]
1) Load condition 50mA is representing a worst case condition with regard to output voltage noise performance.
Data Sheet
18
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
Application Information
7
Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
IFX1763
VIN
IN
V OUT
OUT
CIN
SENSE
1µF
EN
CBYP
COUT
10nF
10µF
R Load
BYP
GND
GND
Figure 4
Typical Application Circuit IFX1763 V50
Note: This is a very simplified example of an application circuit. The function must be verified in the real
application1)2).
The IFX1763 V50 is a 500 mA low dropout regulator with very low quiescent current and Enable-functionality. The
device is capable of supplying 500 mA at a dropout voltage of 350 mV. Output voltage noise numbers down to
42 µVRMS can be achieved over a 10 Hz to 100 kHz bandwidth with the addition of a 10 nF reference bypass
capacitor. The usage of a reference bypass capacitor will additionally improve transient response of the regulator,
lowering the settling time for transient load conditions. The device has a low operating quiescent current of typical
30 µA that drops to less than 1 µA in shutdown (EN-pin pulled to low level). The device also incorporates several
protection features which makes it ideal for battery-powered systems. It is protected against both reverse input
and reverse output voltages. In battery backup applications where the output can be held up by a backup battery
when the input is pulled to ground the device behaves like it has a diode in series with its output and prevents
reverse current flow.
7.1
Kelvin Sense Connection
The SENSE pin of the IFX1763 V50 is the input to the error amplifier. An optimum regulation will be obtained at
the point where the SENSE pin is connected to the OUT pin of the regulator. In critical applications however small
voltage drops can be caused by the resistance Rp of the PC-traces and thus may lower the resulting voltage at the
load. This effect may be eliminated by connecting the SENSE pin to the output as close as possible at the load
1) Please note that in case a non-negligible inductance at IN pin is present, e.g. due to long cables, traces, parasitics, etc, a
bigger input capacitor CIN may be required to filter its influence. As a rule of thumb if the IN pin is more than six inches away
from the main input filter capacitor an input capacitor value of CIN = 10 µF is recommended.
2) For specific needs a small optional resistor may be placed in series to very low ESR output capacitors COUT for enhanced
noise performance (for details please see “Bypass Capacitance and Low Noise Performance” on Page 20).
Data Sheet
19
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
Application Information
(see Figure 5). Please note that the voltage drop across the external PC trace will add up to the dropout voltage
of the regulator.
IFX1763
IN
VIN
CIN
RP
OUT
SENSE
EN
COUT
R Load
BYP
GND
RP
Figure 5
Kelvin Sense Connection
7.2
Bypass Capacitance and Low Noise Performance
The IFX1763 V50 regulator may be used in combination with a bypass capacitor connecting the OUT pin to the
BYP pin in order to minimize output voltage noise1).This capacitor will bypass the reference of the regulator,
providing a low frequency noise pole. The noise pole provided by such a bypass capacitor will lower the output
voltage noise in the considered bandwidth. For a given output voltage actual numbers of the output voltage noise
will - next to the bypass capacitor itself - be dependent on the capacitance of the applied output capacitor and its
ESR: In case of applying the IFX1763 V50 with a bypass capacitor of 10 nF in combination with a (low ESR)
ceramic COUT of 10 µF will result in output voltage noise numbers of typical 55 µVRMS. This Output Noise level can
be reduced to typical 44 µVRMS under the same conditions by adding a small resistance of ~250 mΩ in series to
the 10 µF ceramic output capacitor acting as additional ESR. A reduction of the output voltage noise can also be
achieved by increasing capacitance of the output capacitor. For COUT = 22 µF (ceramic low ESR) the output
voltage noise will be typical 42 µVRMS. For output capacitor values of 22 µF or bigger adding resistance in series
to COUT does not further lower output noise numbers significantly anymore. For further details please also see
“Output Voltage Noise6)” on Page 10,, of the Electrical Characteristics. Please note that next to reducing the
output voltage noise level the usage of a bypass capacitor has the additional benefit of improving transient
response which will be also explained in the next chapter. However one needs to take into consideration that on
the other hand the regulator start-up time is proportional to the size of the bypass capacitor and slows down to
values around 15 ms when using a 10 nF bypass capacitor in combination with a 10 µF COUT output capacitor.
7.3
Output Capacitance Requirements and Transient Response
The IFX1763 V50 is designed to be stable with a wide range of output capacitors. The ESR of the output capacitor
is an essential parameter with regard to stability, most notably with small capacitors. A minimum output capacitor
of 3.3 µF with an ESR of 3 Ω or less is recommended to prevent oscillations. Like in general for LDO’s the output
transient response of the IFX1763 V50 will be a function of the output capacitance. Larger values of output
capacitance decrease peak deviations and thus improve transient response for larger load current changes.
1) a good quality low leakage capacitor is recommended.
Data Sheet
20
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
Application Information
Bypass capacitors, used to decouple individual components powered by the IFX1763 V50 will increase the
effective output capacitor value. Please note that with the usage of larger bypass capacitors for low noise
operation either larger values of output capacitors are needed or a minimum ESR requirement of COUT may have
to be considered (see also Figure “ESR(COUT) with CBYP = 10 nF versus Output Capacitance COUT” on
Page 17 as example). In conjunction with the usage of a 10 nF bypass capacitor an output capacitor COUT ≥
6.8 µF is recommended. The benefit of a bypass capacitor to the transient response performance is impressive
and illustrated as one example in Figure 6 where the transient response of the IFX1763 V50 to one and the same
load step from 100 mA to 500 mA is shown with and without a 10 nF bypass capacitor: for the given configuration
of COUT = 10 µF with no bypass capacitor the load step will settle in the range of less than 200 µs while for
COUT = 10 µF in conjunction with a 10 nF bypass capacitor the same load step will settle in the range of 20 µs. Due
to the shorter reaction time of the regulator by adding the bypass capacitor not only the settling time improves but
also output voltage deviations due to load steps are sharply reduced.
0,4
VOUT Deviation / [V]
C_BYP = 0nF
C_BYP = 10nF
COUT = 10 µF
CBYP = 0 vs 10nF
VIN = 6 V
0,3
0,2
0,1
0
-0,1
-0,2
-0,3
-0,4
0
100
200
300
400
500
Time (μs)
600
700
800
900
1000
Figure 6
Influence of CBYP: example of transient response to one and the same load step with and
without CBYP of 10 nF (IOUT 100 mA to 500 mA)
7.4
Protection Features
The IFX1763 V50 regulators incorporate several protection features which make them ideal for usage in batterypowered circuits. In addition to normal protection features associated with monolithic regulators like current limiting
and thermal limiting the device is protected against reverse input voltage, reverse output voltage and reverse
voltages from output to input.
Current limit protection and thermal overload protection are intended to protect the device against current overload
conditions at the output of the device. For normal operation the junction temperature must not exceed 125°C.
The input of the device will withstand reverse voltages of 20 V. Current flowing into the device will be limited to
less than 1 mA (typically less than 100 µA) and no negative voltage will appear at the output. The device will
protect both itself and the load. This provides protection against batteries being plugged backwards.
The output of the IFX1763 V50 can be pulled below ground without damaging the device. If the input is left opencircuit or grounded, the output can be pulled below ground by 20 V. Under such conditions the OUT pin by itself
will act like an open circuit with practically no current flowing out of the pin1). In more application relevant cases
where the output pin OUT is connected to the SENSE pin there will be a small current of typically less than 100 µA
present from this origin. If the input is powered by a voltage source the output will source the short-circuit current
of the device and will protect itself by thermal limiting. In this case grounding the EN pin will turn off the device and
stop the output from sourcing the short-circuit current.
In circuits where a backup battery is required, several different input/output conditions can occur. The output
voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left
open-circuit. Current flow back into the output will follow the curve as shown in Figure 7 below.
1) typically < 1 µA for the mentioned conditions, VOUT being pulled below ground with other pins either grounded or open.
Data Sheet
21
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
Application Information
When the IN pin of the IFX1763 V50 is forced below the OUT pin, or the OUT pin is pulled above the IN pin, the
input current will typically drop to less than 2 µA. This can happen if the input of the device is connected to a
discharged battery and the output is held up by either a backup battery or a second regulator circuit. The state of
the EN pin will have no effect on the reverse output current when the output is pulled above the input.
90
VOUT.nom = 5.0 V (V50)
80
70
VIN = 0 V
Tj = 25 °C
IOUT,rev [µA]
60
50
40
30
20
10
0
0
2
4
6
8
10
VOUT [V]
Figure 7
Data Sheet
Reverse Output Current
22
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
Package Outlines
8
Package Outlines
0.35 x 45˚
0.41±0.09 2)
0.2
M
C A-B D 8x
8˚ MAX.
0.19 +0.06
0.08 C
Seating Plane
C
1.27
0.1 C D 2x
1.7 MAX.
Stand Off
(1.45)
0.1+0
-0.1
3.9 ±0.11)
0.64 ±0.25
D
0.2
6 ±0.2
M
D 8x
Bottom View
8
1
5
1
4
4
8
5
2.65 ±0.2
3 ±0.2
A
B
4.9 ±0.11)
0.1 C A-B 2x
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Dambar protrusion shall be maximum 0.1 mm total in excess of lead width
3) JEDEC reference MS-012 variation BA
1.63 ±0.1
Z
0.71 ±0.1
Pin 1 Marking
0.25 ±0.1
3.3 ±0.1
0.05
0.5 ±0.1
0.53 ±0.1
1.48 ±0.1
0.36 ±0.1
0.55 ±0.1
0.1 ±0.1
3.3 ±0.1
2.58 ±0.1
0.96 ±0.1
1±0.1
0 +0.05
PG-DSO-8 Exposed Pad package outlines
0.2 ±0.1
Figure 8
PG-DSO-8-27-PO V01
Pin 1 Marking
0.25 ±0.1
PG-TSON-10-2-PO V02
Z (4:1)
0.07 MIN.
Figure 9
PG-TSON-10 Package Outlines
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Data Sheet
23
Dimensions in mm
Rev. 1.11, 2015-01-30
IFX1763XEJV50
IFX1763LDV50
Revision History
9
Revision History
Revision
Date
Changes
1.11
2015-01-30
•
1.1
2014-10-30
Updated Data Sheet including additional package type PG-TSON-10:
• PG-TSON-10 package variants added: Product Overview, Pin Configuration
Thermal Resistance, Wording, etc added / updated accordingly.
• Editorial changes throughout the document.
1.0
2014-05-16
Data Sheet - Initial Release
Data Sheet
Editorial changes - figure title of TSON-10 package figure in Product Overview
corrected.
24
Rev. 1.11, 2015-01-30
Edition 2015-01-30
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2015 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
The Infineon Technologies component described in this Data Sheet may be used in life-support devices or systems
and/or automotive, aviation and aerospace applications or systems only with the express written approval of
Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that lifesupport automotive, aviation and aerospace device or system or to affect the safety or effectiveness of that device
or system. Life support devices or systems are intended to be implanted in the human body or to support and/or
maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user
or other persons may be endangered.