MOTOROLA MC5474F74 Dual d-type positive edge-triggered flip-flop Datasheet

MC54/74F74
DUAL D-TYPE POSITIVE
EDGE-TRIGGERED FLIP-FLOP
The MC54/74F74 is a dual D-type flip-flop with Direct Clear and Set inputs
and complementary (Q, Q) outputs. Information at the input is transferred to
the outputs on the positive edge of the clock pulse. Clock triggering occurs at
a voltage level of the clock pulse and is not directly related to the transition time
of the positive-going pulse. After the Clock Pulse input threshold voltage has
been passed, the Data input is locked out and information present will not be
transferred to the outputs until the next rising edge of the Clock Pulse input.
DUAL D-TYPE POSITIVE
EDGE-TRIGGERED FLIP-FLOP
FAST SCHOTTKY TTL
• ESD > 4000 Volts
J SUFFIX
CERAMIC
CASE 632-08
CONNECTION DIAGRAM
VCC
CD2
D2
CP2
SD2
Q2
Q2
14
13
12
11
10
9
8
14
1
CP2 SD2 Q2
D2 CD2 Q2
D1 CD1 Q1
CP1 SD1 Q1
N SUFFIX
PLASTIC
CASE 646-06
14
1
1
2
3
4
5
6
7
CD1
D1
CP1
SD1
Q1
Q1
GND
D SUFFIX
SOIC
CASE 751A-02
14
1
FUNCTION TABLE (Each Half)
Input
Outputs
@ tn
@ tn + 1
D
Q
Q
L
L
H
H
H
L
ORDERING INFORMATION
MC54FXXJ
MC74FXXN
MC74FXXD
Ceramic
Plastic
SOIC
Asynchronous Inputs:
LOGIC SYMBOL
LOW Input to SD sets Q to HIGH level
LOW Input to CD sets Q to LOW level
Clear and Set are independent of clock
4
Simultaneous LOW on CD and SD makes both Q and Q HIGH
H = HIGH Voltage Level
L = LOW Voltage Level
tn = Bit time before clock pulse
tn + 1 = Bit time after clock pulse
2
SD1
D1 Q1
3
CP1
Q1
CD1
10
5
12
SD2
D2 Q2
11
CP2
6
1
13
VCC = PIN 14
GND = PIN 7
FAST AND LS TTL DATA
4-33
Q2
CD2
9
8
MC54/74F74
LOGIC DIAGRAM
Q
Q
D
CP
SD
CD
NOTE:
This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA
Operating Ambient Temperature Range
Min
Typ
Max
Unit
54, 74
4.50
5.0
5.50
V
54
–55
25
125
°C
74
0
25
70
IOH
Output Current — High
54, 74
–1.0
mA
IOL
Output Current — Low
54, 74
20
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIK
Input Clamp Diode Voltage
Min
Typ
Max
2.0
Unit
Test Conditions
V
Guaranteed Input HIGH Voltage
0.8
V
Guaranteed Input LOW Voltage
–1.2
V
IIN = –18 mA
VCC = MIN
54, 74
2.5
3.4
V
IOH = –1.0 mA
VCC = 4.50 V
74
2.7
3.4
V
IOH = –1.0 mA
VCC = 4.75 V
0.5
V
IOL = 20mA
VCC = MIN
20
µA
VIN = 2.7 V
VCC = MAX
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IIH
Input HIGH Current
100
µA
VIN = 7.0 V
IIL
Input LOW Current
(CP and D Inputs)
–0.6
mA
VIN = 0.5V
VCC = MAX
(CD and SD Inputs)
–1.8
mA
–150
mA
VOUT = 0 V
VCC = MAX
16
mA
VCP = 0 V
VCC = MAX
IOS
Output Short Circuit Current (Note 2)
ICC
Power Supply Current
0.35
–60
10.5
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2. Not more then one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
4-34
MC54/74F74
AC CHARACTERISTICS
54/74F
54F
74F
TA = +25°C
TA = –55°C to +125°C
TA = 0°C to 70°C
VCC = +5.0 V
VCC = 5.0 V ± 10%
VCC = 5.0 V ± 10%
CL = 50 pF
Symbol
Parameter
Min
CL = 50 pF
Max
Min
CL = 50 pF
Max
100
Min
Max
fmax
Maximum Clock Frequency
100
100
tPLH
Propagation Delay
3.8
6.8
3.8
8.5
3.8
7.8
tPHL
CPn to Qn or Qn
4.4
8.0
4.4
10.5
4.4
9.2
tPLH
Propagation Delay
2.5
6.1
2.5
8.0
2.5
7.1
tPHL
CDn or SDn to Qn or Qn
3.5
9.0
3.5
11.5
3.5
10.5
Unit
MHz
ns
ns
AC OPERATING REQUIREMENTS
Symbol
Parameter
Min
54/74F
54F
74F
TA = +25°C
TA = –55°C to +125°C
TA = 0°C to +70°C
VCC = +5.0 V
VCC = 5.0 V ± 10%
VCC = 5.0V ± 10%
Typ
Max
Min
Max
Min
ts(H)
Setup Time, HIGH or LOW
2.0
3.0
2.0
ts(L)
Dn to CPn
3.0
4.0
3.0
th(H)
Hold Time, HIGH or LOW
1.0
2.0
1.0
th(L)
Dn to CPn
1.0
2.0
1.0
tw(H)
CPn Pulse Width, HIGH
4.0
4.0
4.0
5.0
6.0
5.0
tw(L)
or LOW
Max
Unit
ns
ns
tw(L)
CDn or SDn Pulse Width, LOW
4.0
4.0
4.0
ns
trec
Recovery Time
CDn or SDn to CP
2.0
3.0
2.0
ns
FAST AND LS TTL DATA
4-35
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