TI ADS8881IDGSR 18-bit, 1-msps, serial interface, micropower, miniature, true-differential input, sar analog-to-digital converter Datasheet

ADS8881
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SBAS547A – MAY 2013 – REVISED JULY 2013
18-Bit, 1-MSPS, Serial Interface, microPower, Miniature,
True-Differential Input, SAR Analog-to-Digital Converter
Check for Samples: ADS8881
FEATURES
APPLICATIONS
• Sample Rate: 1 MHz
• No Latency Output
• Unipolar, True-Differential Input Range:
–VREF to +VREF
• Wide Common-Mode Voltage Range:
0 V to VREF with 90-dB CMRR (min)
• SPI™-Compatible Serial Interface with
Daisy-Chain Option
• Excellent AC and DC Performance:
– SNR: 100 dB, THD: –115 dB
– INL: ±1.5 LSB (typ), ±3.0 LSB (max)
– DNL: +1.5 and –1 LSB (max), 18-Bit NMC
• Wide Operating Range:
– AVDD: 2.7 V to 3.6 V
– DVDD: 2.7 V to 3.6 V
(Independent of AVDD)
– REF: 2.5 V to 5 V (Independent of AVDD)
– Operating Temperature: –40°C to +85°C
• Low-Power Dissipation:
– 5.5 mW at 1 MSPS
– 0.55 mW at 100 kSPS
– 55 µW at 10 kSPS
• Power-Down Current (AVDD): 50 nA
• Full-Scale Step Settling to 18 Bits: 290 ns
• Packages: MSOP-10 and SON-10
•
•
•
•
1
234
Traditional Input Range
ADS8881 Input Range
VDIFF
Automatic Test Equipment (ATE)
Instrumentation and Process Controls
Precision Medical Equipment
Low-Power, Battery-Operated Instruments
DESCRIPTION
The ADS8881 is an 18-bit, 1-MSPS, true-differential
input, analog-to-digital converter (ADC). The device
operates with a 2.5-V to 5-V external reference,
offering a wide selection of signal ranges without
additional input signal scaling. The reference voltage
setting is independent of, and can exceed, the analog
supply voltage (AVDD).
The device
that also
cascading
indicator bit
easy.
The device supports unipolar, true-differential analog
input signals with a differential input swing of –VREF to
+VREF. This true-differential analog input structure
allows for a common-mode voltage of any value in
the range of 0 V to +VREF (when both inputs are
within the operating input range of –0.1 V to VREF
+ 0.1 V).
Device operation is optimized for very low-power
operation. Power consumption directly scales with
speed. This feature makes the ADS8881 excellent for
lower-speed applications.
True-Differential Input Range
+VREF
VREF
VCM
0V
offers an SPI-compatible serial interface
supports daisy-chain operation for
multiple devices. An optional busymakes synchronizing with the digital host
2.5 V to 5 V
2.7 V to 3.6 V
REF
AVDD
0 V - VREF
DVDD
AINP
VCM
DIN
ADS8881
VREF
SCLK
DOUT
0V
AINM
CONVST
0 V - VREF
VREF/2
GND
-VREF
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TINA is a trademark of Texas Instruments Inc..
SPI is a trademark of Motorola Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
ADS8881
SBAS547A – MAY 2013 – REVISED JULY 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FAMILY AND ORDERING INFORMATION (1)
(1)
DISSIPATION
18-BIT, TRUE-DIFFERENTIAL
16-BIT, SINGLE-ENDED
16-BIT, TRUE-DIFFERENTIAL
100 kSPS
ADS8887
ADS8866
ADS8867
250 kSPS
—
—
—
400 kSPS
ADS8885
ADS8864
ADS8865
500 kSPS
—
ADS8319
ADS8318
680 kSPS
ADS8883
ADS8862
ADS8863
1 MSPS
ADS8881
ADS8860
ADS8861
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
MIN
MAX
AINP to GND or AINN to GND
–0.3
REF + 0.3
V
AVDD to GND or DVDD to GND
–0.3
4
V
REF to GND
–0.3
5.7
V
Digital input voltage to GND
–0.3
DVDD + 0.3
V
Digital output to GND
–0.3
DVDD + 0.3
V
Operating temperature range, TA
–40
+85
°C
Storage temperature range, Tstg
–65
+150
°C
(1)
UNIT
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under electrical characteristics is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
ADS8881
THERMAL METRIC (1)
DGS
DRC
10 PINS
10 PINS
θJA
Junction-to-ambient thermal resistance
151.9
111.1
θJCtop
Junction-to-case (top) thermal resistance
45.4
46.4
θJB
Junction-to-board thermal resistance
72.2
45.9
ψJT
Junction-to-top characterization parameter
3.3
3.5
ψJB
Junction-to-board characterization parameter
70.9
45.5
θJCbot
Junction-to-case (bottom) thermal resistance
N/A
N/A
(1)
2
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SBAS547A – MAY 2013 – REVISED JULY 2013
ELECTRICAL CHARACTERISTICS
All minimum and maximum specifications are at TA = –40°C to +85°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, VCM = VREF /
2 V, and fSAMPLE = 1 MSPS, unless otherwise noted. Typical specifications are at TA = +25°C, AVDD = 3 V, and DVDD = 3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input span (1) (2)
Operating input range (1) (2)
AINP – AINN
–VREF
VREF
V
AINP
–0.1
VREF + 0.1
V
AINN
–0.1
VREF + 0.1
V
VCM
Input common-mode range
0
Ci
Input capacitance
AINP and AINN terminal to GND
Input leakage current
During acquisition for dc input
VREF / 2
VREF
V
59
pF
5
nA
18
Bits
SYSTEM PERFORMANCE
Resolution
NMC
No missing codes
DNL
Differential linearity
INL
EO
18
±0.7
1.5
LSB (3)
Integral linearity (4)
–3
±1.5
3
LSB (3)
Offset error (5)
–4
±1
4
Offset error drift with temperature
EG
Bits
–0.99
mV
±1.5
Gain error
–0.01
Gain error drift with temperature
±0.005
µV/°C
0.01
±0.15
CMRR
Common-mode rejection ratio
With common-mode input signal = 5 VPP at dc
PSRR
Power-supply rejection ratio
At mid-code
90
Transition noise
%FSR
ppm/°C
100
dB
80
dB
0.7
LSB
SAMPLING DYNAMICS
tconv
Conversion time
500
tACQ
Acquisition time
290
710
ns
Maximum throughput rate
with or without latency
(1)
(2)
(3)
(4)
(5)
ns
1000
kHz
Aperture delay
4
ns
Aperture jitter, RMS
5
ps
Step response
Settling to 18-bit accuracy
290
ns
Overvoltage recovery
Settling to 18-bit accuracy
290
ns
Ideal input span, does not include gain or offset error.
Specified for VCM = VREF / 2. Refer to the Analog Input section for the effect of VCM on the full-scale input range.
LSB = least significant bit.
This parameter is the endpoint INL, not best-fit.
Measured relative to actual measured reference.
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ELECTRICAL CHARACTERISTICS (continued)
All minimum and maximum specifications are at TA = –40°C to +85°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, VCM = VREF /
2 V, and fSAMPLE = 1 MSPS, unless otherwise noted. Typical specifications are at TA = +25°C, AVDD = 3 V, and DVDD = 3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
98
MAX
UNIT
DYNAMIC CHARACTERISTICS
At 1 kHz, VREF = 5 V
SINAD
Signal-to-noise + distortion (6)
99.9
dB
At 10 kHz, VREF = 5 V
98.7
dB
At 100 kHz, VREF = 5 V
93.3
dB
100
dB
At 10 kHz, VREF = 5 V
99.5
dB
At 100 kHz, VREF = 5 V
93.5
dB
At 1 kHz, VREF = 5 V
–115
dB
At 10 kHz, VREF = 5 V
–112
dB
At 100 kHz, VREF = 5 V
–102
dB
At 1 kHz, VREF = 5 V
115
dB
At 10 kHz, VREF = 5 V
112
dB
At 100 kHz, VREF = 5 V
102
dB
30
MHz
At 1 kHz, VREF = 5 V
Signal-to-noise ratio (6)
SNR
Total harmonic distortion (6) (7)
THD
SFDR
BW-3dB
Spurious-free dynamic range (6)
98.5
–3-dB small-signal bandwidth
EXTERNAL REFERENCE INPUT
VREF
Input range
2.5
Reference input current
CREF
Decoupling capacitor at the REF
input
5
V
350
μA
10
22
µF
During conversion, 1-MHz sample rate, mid-code
POWER-SUPPLY REQUIREMENTS
AVDD
Power-supply
voltage
Supply current
DVDD
AVDD
Analog supply
Digital supply range
Digital supply range for specified performance
2.7
3
3.6
V
1.65
3
3.6
V
2.7
3
3.6
V
1.8
2.4
mA
5.5
7.2
mW
1-MHz sample rate, AVDD = 3 V
1-MHz sample rate, AVDD = 3 V
PVA
Power dissipation
100-kHz sample rate, AVDD = 3 V
10-kHz sample rate, AVDD = 3 V
IAPD
Device power-down current (8)
0.55
mW
55
μW
50
nA
LOGIC FAMILY (CMOS)
VIH
VIL
VOH
VOL
Logic level (digital inputs)
Logic level (digital outputs)
IO = 500-μA source, CLOAD = 20 pF
IO = 500-μA sink, CLOAD = 20 pF
0.7 × DVDD
DVDD + 0.3
V
–0.3
0.3 × DVDD
V
0.8 × DVDD
DVDD
V
0
0.2 × DVDD
V
–40
+85
°C
TEMPERATURE RANGE
TA
(6)
(7)
(8)
4
Operating free-air temperature
All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale,
unless otherwise specified.
Calculated on the first nine harmonics of the input frequency.
The device automatically enters a power-down state at the end of every conversion, and remains in power-down during the acquisition
phase.
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TIMING CHARACTERISTICS
3-WIRE OPERATION
1/fsample
DIN = HIGH
tconv-max
tACQ
tclkh
th-CK-DO
CONVST
tclkl
tquiet
SCLK
1
2
18
D1
D0
œœ
D17
twh-CNV-min
17
tSCLK
td-CNV-DO
DOUT
œœ
3
16
D16
D15
D2
œœ
td-CK-DOhz
td-CK-DO
Figure 1. 3-Wire Operation: CONVST Functions as Chip Select
NOTE
Figure 1 shows the timing diagram for the 3-Wire CS Mode Without a Busy Indicator
interface option. However, the timing parameters specified in Table 1 are also applicable
for the 3-Wire CS Mode With a Busy Indicator interface option, unless otherwise specified.
Refer to the Digital Interface section for specific details for each interface option.
Table 1. TIMING REQUIREMENTS: 3-Wire Operation (1)
PARAMETER
MIN
TYP
MAX
UNIT
tACQ
Acquisition time
290
tconv
Conversion time
500
1/fsample
Time between conversions
twh-CNV
Pulse duration: CONVST high
fSCLK
SCLK frequency
tSCLK
SCLK period
tclkl
SCLK low time
0.45
0.55
tSCLK
tclkh
SCLK high time
0.45
0.55
tSCLK
th-CK-DO
SCLK falling edge to current data invalid
td-CK-DO
SCLK falling edge to next data valid delay
13.4
ns
td-CNV-DO
Enable time: CONVST low to MSB valid
12.3
ns
td-CNV-DOhz
Disable time: CONVST high or last SCLK falling edge to DOUT 3-state (CS mode)
13.2
ns
tquiet
Quiet time
(1)
ns
710
1000
ns
ns
10
ns
66.6
15
MHz
ns
3
ns
20
ns
All specifications are at TA = –40°C to +85°C, AVDD = 3 V, and DVDD = 3 V, unless otherwise noted.
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4-WIRE OPERATION
1/fsample
tACQ
tconv-max
CONVST
tsu-DI-CNV
twl-CNV
DIN
SCLK
1
DOUT
D17
2
3
D16
D15
œœ
16
17
18
D1
D0
œœ
twh-DI-min
td-DI-DO
D2
œœ
td-DI-DOhz
Figure 2. 4-Wire Operation: DIN Functions as Chip Select
NOTE
Figure 2 shows the timing diagram for the 4-Wire CS Mode Without a Busy Indicator
interface option. However, the timing parameters specified in Table 2 are also applicable
for the 4-Wire CS Mode With a Busy Indicator interface option, unless otherwise specified.
Refer to the Digital Interface section for specific details for each interface option.
Table 2. TIMING REQUIREMENTS: 4-Wire Operation (1)
PARAMETER
tACQ
Acquisition time
tconv
Conversion time
1/fsample
Time between conversions
twh-DI
MIN
TYP
MAX
290
500
UNIT
ns
710
ns
1000
ns
Pulse duration: DIN high
10
ns
twl-CNV
Pulse width: CONVST low
20
td-DI-DO
Delay time: DIN low to MSB valid
12.3
ns
td-DI-DOhz
Delay time: DIN high or last SCLK falling edge to DOUT 3-state
13.2
ns
tsu-DI-CNV
Setup time: DIN high to CONVST rising edge
th-DI-CNV
Hold time: DIN high from CONVST rising edge (see Figure 62)
(1)
6
ns
7.5
ns
0
ns
All specifications are at TA = –40°C to +85°C, AVDD = 3 V, and DVDD = 3 V, unless otherwise noted.
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DAISY-CHAIN OPERATION
1/fsample
tconv-
tACQ
max
CONVST
th-CK-CNV
SCLK
DIN 1 = LOW
1
2
17
18
19
20
35
36
D17
D16
D1
D0
tsu-DI-CK
tsu-CK-CNV
DOUT 1
DIN 2
D17
D16
D1
D0
DOUT 2
D17
D16
D1
D0
Device 2 Data
Device 1 Data
Figure 3. Daisy-Chain Operation - 2 devices
NOTE
Figure 3 shows the timing diagram for the Daisy-Chain Mode Without a Busy Indicator
interface option. However, the timing parameters specified in Table 3 are also applicable
for the Daisy-Chain Mode With a Busy Indicator interface option, unless otherwise
specified. Refer to the Digital Interface section for specific details for each interface option.
Table 3. TIMING REQUIREMENTS: Daisy-Chain (1)
PARAMETER
MIN
tACQ
Acquisition time
290
tconv
Conversion time
500
1/fsample
Time between conversions
tsu-CK-CNV
Setup time: SCLK valid to CONVST rising edge
th-CK-CNV
Hold time: SCLK valid from CONVST rising edge
tsu-DI-CNV
Setup time: DIN low to CONVST rising edge (see Figure 2)
th-DI-CNV
Hold time: DIN low from CONVST rising edge (see Figure 62)
tsu-DI-CK
Setup time: DIN valid to SCLK falling edge
(1)
TYP
MAX
UNIT
ns
710
ns
1000
ns
5
ns
5
ns
7.5
ns
0
ns
1.5
ns
All specifications are at TA = –40°C to +85°C, AVDD = 3 V, and DVDD = 3 V, unless otherwise noted.
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EQUIVALENT CIRCUITS
500 µA
IOL
1.4 V
DOUT
20 pF
500 µA
IOH
Figure 4. Load Circuit for Digital Interface Timing
DIN
CONVST
SCLK
VIH
VIL
VOH
VOH
VOL
VOL
SDO
Figure 5. Voltage Levels for Timing
8
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PIN CONFIGURATIONS
DGS PACKAGE
VSSOP-10
(TOP VIEW, Not to Scale)
DRC PACKAGE
SON-10
(TOP VIEW, Not to Scale)
REF
1
10
DVDD
AVDD
2
9
DIN
AINP
3
8
SCLK
AINN
4
7
DOUT
GND
5
6
CONVST
REF
1
10
DVDD
AVDD
2
9
DIN
AINP
3
8
SCLK
AINN
4
7
DOUT
GND
5
6
CONVST
Thermal
PAD
PIN ASSIGNMENTS
PIN NAME
PIN
NUMBER
FUNCTION
AINN
4
Analog input
Inverting analog signal input
AINP
3
Analog input
Noninverting analog signal input
AVDD
2
Analog
CONVST
6
Digital input
Convert input.
This pin also functions as the CS input in 3-wire interface mode. Refer to the
Description and Timing Characteristics sections for more details.
Serial data input.
The DIN level at the start of a conversion selects the mode of operation (such as CS
or daisy-chain mode). This pin also serves as the CS input in 4-wire interface mode.
Refer to the Description and Timing Characteristics sections for more details.
DESCRIPTION
Analog power supply.
This pin must be decoupled to GND with a 1-μF capacitor.
DIN
9
Digital input
DOUT
7
Digital output
Serial data output
DVDD
10
Power supply
Digital interface power supply.
This pin must be decoupled to GND with a 1-μF capacitor.
Device ground.
Note that this pin is a common ground pin for both the analog power supply (AVDD)
and digital I/O supply (DVDD). The reference return line is also internally connected to
this pin.
GND
5
Analog, digital
REF
1
Analog
SCLK
8
Digital input
Clock input for serial interface.
Data output (on DOUT) are synchronized with this clock.
Thermal pad
—
Thermal pad
Exposed thermal pad.
Texas Instruments recommends connecting the thermal pad to the printed circuit
board (PCB) ground.
Positive reference input.
This pin must be decoupled with a 10-μF or larger capacitor.
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TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
1
Typical Differential Nonlinearity (LSB)
Typical Integral Nonlinearity (LSB)
3
AVDD = 3 V
REF = 2.5 V
TA = 25oC
2
1
0
-1
-2
-3
-131072
0.5
0.25
0
-0.25
-0.5
-0.75
-1
-131072
131071
ADC Output Code
1
Typical Differential Nonlinearity (LSB)
Typical Integral Nonlinearity (LSB)
C00
Figure 7. TYPICAL DNL (VREF = 2.5 V)
3
AVDD = 3 V
REF = 5 V
TA = 25oC
2
1
0
-1
-2
-3
-131072
131071
ADC Output Code
AVDD = 3 V
REF = 5 V
TA = 25oC
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
-131072
131071
ADC Output Code
C00
Figure 8. TYPICAL INL (VREF = 5 V)
C00
Figure 9. TYPICAL DNL (VREF = 5 V)
2
3
AVDD = 3 V
REF = 5 V
2
Differential Nonlinearity (LSB)
Integral Nonlinearity (LSB)
131071
ADC Output Code
C00
Figure 6. TYPICAL INL (VREF = 2.5 V)
1
0
-1
-2
-3
AVDD = 3 V
REF = 5 V
1.5
1
0.5
0
-0.5
-1
-40
-15
10
35
Free-Air Temperature (oC)
60
85
-40
C00
Figure 10. INL vs TEMPERATURE
10
AVDD = 3 V
REF = 2.5 V
TA = 25oC
0.75
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-15
10
35
60
Free-Air Temperature (oC)
85
C00
Figure 11. DNL vs TEMPERATURE
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
2
AVDD = 3 V
TA = 25oC
2
Differential Nonlinearity (LSB)
Integral Nonlinearity (LSB)
3
1
0
-1
-2
AVDD = 3 V
TA = 25oC
1.5
1
0.5
0
-0.5
-1
-3
2.5
3
3.5
4
Reference Voltage (V)
4.5
2.5
5
3
C00
Figure 12. INL vs REFERENCE VOLTAGE
4.5
5
C00
Figure 13. DNL vs REFERENCE VOLTAGE
60
40
AVDD = 3 V
REF = 2.5 V
TA = 25oC
AVDD = 3 V
REF = 5 V
TA = 25oC
50
Hits per Code (%)
30
Hits per Code (%)
3.5
4
Reference Voltage (V)
20
40
30
20
10
10
0
0
10
12
14
16
ADC Output Code
18
4
20
Figure 14. DC INPUT HISTOGRAM (VREF = 2.5 V)
8
ADC Output Code
10
C01
Figure 15. DC INPUT HISTOGRAM (VREF = 5 V)
0
0
AVDD = 3 V
REF = 2.5 V
TA = 25oC
fIN = 1kHz
SNR = 95.4 dB
THD = -119dB
-40
-60
-80
AVDD = 3 V
REF = 5 V
TA = 25oC
fIN = 1kHz
SNR = 100 dB
THD = -115dB
-20
-40
-60
Power (dB)
-20
Power (dB)
6
C00
-100
-120
-80
-100
-120
-140
-140
-160
-160
-180
-180
-200
-200
0
100
200
300
Input Frequency (kHz)
400
500
0
C01
Figure 16. TYPICAL FFT (VREF = 2.5 V)
100
200
300
Input Frequency (kHz)
400
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C01
Figure 17. TYPICAL FFT (VREF = 5 V)
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
102
Signal-to-Noise and Distortion (dBFS)
Signal-to-Noise Ratio (dBFS)
102
101
100
99
98
97
96
95
94
101
100
99
98
97
96
95
94
2.5
3
3.5
4
Reference Voltage (V)
4.5
5
2.5
Figure 18. SNR vs REFERENCE VOLTAGE
Total Harmonic Distortion (dBFS)
Effective Number of Bits
4.5
5
C01
-109
17.5
17
16.5
16
15.5
15
14.5
-111
-113
-115
-117
-119
-121
-123
-125
14
2.5
3
3.5
4
Reference Voltage (V)
4.5
2.5
5
3
C01
Figure 20. ENOB vs REFERENCE VOLTAGE
3.5
4
Reference Voltage (V)
4.5
5
C01
Figure 21. THD vs REFERENCE VOLTAGE
126
102
124
101
Signal-to-Noise Ratio (dBFS)
Spurious-Free Dynamic Range (dBFS)
3.5
4
Reference Voltage (V)
Figure 19. SINAD vs REFERENCE VOLTAGE
18
122
120
118
116
114
112
100
99
98
97
96
95
94
110
2.5
3
3.5
4
Reference Voltage (V)
4.5
5
-40
C01
Figure 22. SFDR vs REFERENCE VOLTAGE
12
3
C01
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-15
10
35
Free-Air Temperature (oC)
60
85
C01
Figure 23. SNR vs TEMPERATURE
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TYPICAL CHARACTERISTICS (continued)
102
18
101
17.5
Effective Number of Bits
Signal-to-Noise and Distortion (dBFS)
At TA = +25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
100
99
98
97
96
95
17
16.5
16
15.5
15
14.5
94
14
-40
-15
10
35
Free-Air Temperature (oC)
60
85
-40
Figure 24. SINAD vs TEMPERATURE
Spurious-Free Dynamic Range (dBFS)
Total Harmonic Distortion (dBFS)
10
35
Free-Air Temperature (oC)
60
85
C02
Figure 25. ENOB vs TEMPERATURE
-109
-111
-113
-115
-117
-119
-121
-123
-125
126
124
122
120
118
116
114
112
110
-40
-15
10
35
Free-Air Temperature (oC)
60
85
-40
-15
C02
Figure 26. THD vs TEMPERATURE
10
35
Free-Air Temperature (oC)
60
85
C02
Figure 27. SFDR vs TEMPERATURE
101
Signal-to-Noise and Distortion (dBFS)
106
Signal-toNoise Ratio (dBFS)
-15
C01
104
102
100
98
96
94
92
100
99
98
97
96
95
94
93
90
0
20
40
60
Input Frequency (kHz)
80
100
0
C02
Figure 28. SNR vs INPUT FREQUENCY
20
40
60
Input Frequency (kHz)
80
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C02
Figure 29. SINAD vs INPUT FREQUENCY
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
18
-100
Total Harmonic Distortion (dBFS)
Effective Number of Bits
17.5
17
16.5
16
15.5
15
14.5
14
-103
-106
-109
-112
-115
-118
-121
-124
0
20
40
60
Input Frequency (kHz)
80
100
0
124
2.4
121
2.3
118
115
112
109
106
80
100
C02
2.2
2.1
2
1.9
1.8
1.7
103
1.6
100
0
20
40
60
Input Frequency (kHz)
80
-40
100
-15
C02
Figure 32. SFDR vs INPUT FREQUENCY
10
35
Free-Air Temperature (oC)
60
85
C02
Figure 33. SUPPLY CURRENT vs TEMPERATURE
6
2
5.9
1.8
Analog Supply Current (mA)
Power Consumption (mW)
40
60
Input Frequency (kHz)
Figure 31. THD vs INPUT FREQUENCY
Analog Supply Current (mA)
Spurious-Free Dynamic Range (dBFS)
Figure 30. ENOB vs INPUT FREQUENCY
5.8
5.7
5.6
5.5
5.4
5.3
5.2
5.1
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
5
0
-40
-15
10
35
Free-Air Temperature (oC)
60
85
0
200
C02
Figure 34. POWER CONSUMPTION vs TEMPERATURE
14
20
C02
400
600
Throughput (kSPS)
800
1000
C03
Figure 35. SUPPLY CURRENT vs THROUGHPUT
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
200
175
5
Power-Down Current (mA)
Power Consumption (mW)
6
4
3
2
1
150
125
100
75
50
25
0
0
0
200
400
600
Throughput (kSPS)
800
1000
-40
-15
C03
Figure 36. POWER CONSUMPTION vs THROUGHPUT
10
35
Free-Air Temperature (oC)
60
85
C03
Figure 37. POWER-DOWN CURRENT vs TEMPERATURE
0.01
4
3
0.006
Gain Error (%FS)
Offset (mV)
2
1
0
-1
-2
0.002
-0.002
-0.006
-3
-4
-0.01
-40
-15
10
35
Free-Air Temperature (oC)
60
-40
85
10
35
Free-Air Temperature (oC)
60
85
C03
Figure 39. GAIN ERROR vs TEMPERATURE
105
18000
103
16000
101
14000
99
12000
Frequency
Common-Mode Rejection Ratio (dB)
Figure 38. OFFSET vs TEMPERATURE
97
95
93
AVDD = 3 V
REF = 5 V
TA = 25oC
15000 Devices
10000
8000
6000
91
4000
89
2000
87
85
0.001
-15
C03
0
0.01
0.1
1
Input Frequency (kHz)
10
100
-0.01
Figure 40. CMRR vs INPUT FREQUENCY
-0.005
0
0.005
0.01
Gain Error (% FS)
C03
C03
Figure 41. TYPICAL DISTRIBUTION OF GAIN ERROR
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
8000
16000
AVDD = 3 V
REF = 5 V
TA = 25oC
15000 Devices
7000
12000
5000
Frequency
Frequency
6000
AVDD = 3 V
REF = 5 V
TA = 25oC
15000 Devices
14000
4000
3000
10000
8000
6000
2000
4000
1000
2000
0
0
-4
-3
-2
-1
0
1
Offset (mV)
2
3
4
-1
C03
Figure 42. TYPICAL DISTRIBUTION OF OFFSET ERROR
-0.5
0
0.5
1
Differential Nonlinearity Min & Max (LSB)
1.5
C03
Figure 43. TYPICAL DISTRIBUTION OF DIFFERENTIAL
NONLINEARITY (Minimum and Maximum)
14000
12000
Frequency
10000
AVDD = 3 V
REF = 5 V
TA = 25oC
15000 Devices
8000
6000
4000
2000
0
-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2
Integral Nonlinearity Min & Max (LSB)
2.5
3
C03
Figure 44. TYPICAL DISTRIBUTION OF INTEGRAL
NONLINEARITY (Minimum and Maximum)
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OVERVIEW
The ADS8881 is a high-speed, successive approximation register (SAR), analog-to-digital converter (ADC) from
a 16- and 18-bit product family. This compact device features high performance. Power consumption is
inherently low and scales linearly with sampling speed. The architecture is based on charge redistribution, which
inherently includes a sample-and-hold (S/H) function.
The ADS8881 supports a true-differential analog input across two pins (INP and INN). When a conversion is
initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in
progress, both the INP and INN inputs are disconnected from the internal circuit.
The ADS8881 uses an internal clock to perform conversions. The device reconnects the sampling capacitors to
the INP and INN pins after conversion and then enters an acquisition phase. During the acquisition phase, the
device is powered down and the conversion result can be read.
The device digital output is available in SPI-compatible format, which makes interfacing with microprocessors,
digital signal processors (DSPs), or field-programmable gate arrays (FPGAs) easy.
ANALOG INPUT
As shown in Figure 45, the device features a differential analog input. Both positive and negative inputs are
individually sampled on 55-pF sampling capacitors and the device converts for the voltage difference between
the two sampled values: VINP – VINN. Most differential input SAR ADCs prohibit the input common-mode voltage,
VCM, (that is, the average voltage between the inputs) at AINP or AINM from varying more than approximately
10% beyond the mid-scale input value. The ADS8881 has a unique, high CMRR input structure that does not
have this restriction and allows VCM to be set to any value between 0 V and VREF without degrading device
performance. As shown in Table 4, the full-scale input range of the device changes with the value of VCM. The
device offers a maximum dynamic range for VCM = VREF / 2. The differential input with wide common-mode range
allows connecting differential signals from sensors without any signal conditioning.
AVDD
REF
DVDD
REF
CONVST
AINP
Sample
and
Hold
AINN
SCLK
SAR
ADC
ADC
SPI
DOUT
DIN
AGND
REFM
DGND
GND
GND
Figure 45. Detailed Block Diagram
Table 4. Full-Scale Input Range
VCM
ABSOLUTE INPUT RANGE
FULL SCALE INPUT RANGE (VFS)
VAINP
VAINN
VCM < VREF / 2
0 V to 2 x VCM
0 V to 2 x VCM
VCM = VREF / 2
0 V to VREF
0 V to VREF
–VREF to VREF
VCM > VREF / 2
2 × VCM – VREF to VREF
2 × VCM – VREF to VREF
–2 × (VCM – VREF) to 2 × (VCM – VREF)
–2 x VCM to 2 x VCM
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Figure 46 shows an equivalent circuit of the input sampling stage. The sampling switch is represented by a 96-Ω
resistance in series with the ideal switch. Refer to the ADC Input Driver section for more details on the
recommended driving circuits.
96
Device in Hold Mode
AINP
4 pF
55 pF
REF
4 pF
55 pF
96
GND
GND
AINN
Figure 46. Input Sampling Stage Equivalent Circuit
Figure 45 and Figure 46 show electrostatic discharge (ESD) protection diodes to REF and GND from both analog
inputs. Make sure that these diodes do not turn on by keeping the analog inputs within the specified range.
REFERENCE
The device operates with an external reference voltage and switches binary-weighted capacitors onto the
reference terminal (REF pin) during the conversion process. The switching frequency is proportional to the
internal conversion clock frequency but the dynamic charge requirements are a function of the absolute value of
the input voltage and reference voltage. This dynamic load must be supported by a reference driver circuit
without degrading the noise and linearity performance of the device. The basic circuit diagram for such a
reference driver circuit for precision ADCs is shown in Figure 47. Refer to the ADC Reference Driver section for
more details on the application circuits.
RREF_FLT
Buffer
CREF_FLT
RBUF_FLT
Voltage
Reference
REF
CBUF_FLT
ADC
Figure 47. Reference Driver Schematic
CLOCK
The device uses an internal clock for conversion. Conversion duration may vary but is bounded by the minimum
and maximum value of tconv, as specified in the Timing Characteristics section. An external SCLK is only used for
a serial data read operation. Data are read after a conversion completes and when the device is in acquisition
phase for the next sample.
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ADC TRANSFER FUNCTION
The ADS8881 is a unipolar, differential input device. The device output is in twos compliment format.
Figure 48 shows ideal characteristics for the device. The full-scale range for the ADC input (AINP – AINN) is
equal to twice the reference input voltage to the ADC (2 × VREF). The LSB for the ADC is given by Equation 1.
1 LSB = [2 × (VREF / 218)]
(1)
ADC Code (Hex)
1FFFF
00000
3FFFF
20001
20000
±VREF
+ 1 LSB
±1 LSB
0
VREF
± 1 LSB
VIN
Differential Analog Input
(AINP AINN)
Figure 48. Differential Transfer Characteristics
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DIGITAL INTERFACE
The ADS8881 is a low pin-count device. However, the device offers six different options for interfacing with the
digital host.
These options can be broadly classified as being either CS mode (in either a 3- or 4-wire interface) or daisychain mode. The device operates in CS mode if DIN is high at the CONVST rising edge. If DIN is low at the
CONVST rising edge, or if DIN and CONVST are connected together, the device operates in daisy-chain mode.
In both modes, the device can either operate with or without a busy indicator, where the busy indicator is a bit
preceding the output data bits that can be used to interrupt the digital host and trigger the data transfer.
The 3-wire interface in CS mode is useful for applications that need galvanic isolation on-board. The 4-wire
interface in CS mode allows the user to sample the analog input independent of the serial interface timing and,
therefore, allows easier control of an individual device while having multiple, similar devices on-board. The daisychain mode is provided to hook multiple devices in a chain similar to a shift register and is useful in reducing
component count and the number of signal traces on the board.
CS Mode
CS mode is selected if DIN is high at the CONVST rising edge. There are four different interface options
available in this mode: 3-wire CS mode without a busy indicator, 3-wire CS mode with a busy indicator, 4-wire
CS mode without a busy indicator, and 4-wire CS mode with a busy indicator. The following sections discuss
these interface options in detail.
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3-Wire CS Mode Without a Busy Indicator
This interface option is most useful when a single ADC is connected to an SPI-compatible digital host. In this
interface option, DIN can be connected to DVDD and CONVST functions as CS (as shown in Figure 49). As
shown in Figure 50, a CONVST rising edge forces DOUT to 3-state, samples the input signal, and causes the
device to enter a conversion phase. Conversion is done with the internal clock and continues regardless of the
state of CONVST. As a result, CONVST (functioning as CS) can be pulled low after the start of the conversion to
select other devices on the board. However, CONVST must return high before the minimum conversion time
(tconv-min) elapses and is held high until the maximum possible conversion time (tconv-max) elapses. A high level on
CONVST at the end of the conversion ensures the device does not generate a busy indicator.
DVDD
DIN
CONVST
CNV
SCLK
CLK
DOUT
SDI
ADC
Digital Host
Figure 49. Connection Diagram: 3-Wire CS Mode Without a Busy Indicator (DIN = 1)
1/fsample
DIN = HIGH
CONVST = 1
CONVST
SCLK
1
DOUT
D17
2
3
D16
D15
œœ
16
17
18
D1
D0
œœ
tACQ
tconv-max
tconv-min
ADC
STATE
D2
œœ
Acquiring
Sample N
Conversion Result of Sample N Clocked-out
while Acquiring Sample N+1
Converting
Sample N
End-of-Conversion
Figure 50. Interface Timing Diagram: 3-Wire CS Mode Without a Busy Indicator (DIN = 1)
When conversion is complete, the device enters an acquisition phase and powers down. CONVST (functioning
as CS) can be brought low after the maximum conversion time (tconv-max) has elapsed. On the CONVST falling
edge, DOUT comes out of 3-state and the device outputs the MSB of the data. The lower data bits are output on
subsequent SCLK falling edges. Data are valid on both SCLK edges. Data are valid on both edges of SCLK and
can be captured on either edge. However, a digital host capturing data on the SCLK falling edge can achieve a
faster reading rate (provided th_CK_DO is acceptable). DOUT goes to 3-state after the 18th SCLK falling edge or
when CONVST goes high, whichever occurs first.
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3-Wire CS Mode With a Busy Indicator
This interface option is most useful when a single ADC is connected to an SPI-compatible digital host and an
interrupt-driven data transfer is desired. In this interface option, DIN can be connected to DVDD and CONVST
functions as CS (as shown in Figure 51). The pull-up resistor on the DOUT pin ensures that the IRQ pin of the
digital host is held high when DOUT goes to 3-state. As shown in Figure 52, a CONVST rising edge forces
DOUT to 3-state, samples the input signal, and causes the device to enter a conversion phase. Conversion is
done with the internal clock and continues regardless of the state of CONVST. As a result, CONVST (functioning
as CS) can be pulled low after the start of the conversion to select other devices on the board. However,
CONVST must be pulled low before the minimum conversion time (tconv-min) elapses and must remain low until
the maximum possible conversion time (tconv-max) elapses. A low level on the CONVST input at the end of a
conversion ensures the device generates a busy indicator.
DVDD
CNV
CONVST
CLK
SCLK
DIN
DVDD
DOUT
SDI
ADC
IRQ
Digital Host
Figure 51. Connection Diagram: 3-Wire CS Mode With a Busy Indicator
1/fsample
DIN = DVDD
CONVST
CONVST = 0
SCLK
1
2
3
D17
D16
œœ
17
18
19
D1
D0
œœ
SDO Pulled-up
DOUT
BUSY
D2
œœ
tACQ
tconv-max
tconv-min
ADC
STATE
Acquiring
Sample N
Conversion Result of Sample N Clocked-out
while Acquiring Sample N+1
Converting
Sample N
End-of-Conversion
Figure 52. Interface Timing Diagram: 3-Wire CS Mode With a Busy Indicator (DIN = 1)
When conversion is complete, the device enters an acquisition phase and powers down, DOUT comes out of 3state, and the device outputs a busy indicator bit (low level) on the DOUT pin. This configuration provides a highto-low transition on the IRQ pin of the digital host. The data bits are clocked out, MSB first, on the subsequent
SCLK falling edges. Data are valid on both SCLK edges. Data are valid on both edges of SCLK and can be
captured on either edge. However, a digital host capturing data on the SCLK falling edge can achieve a faster
reading rate (provided th_CK_DO is acceptable). DOUT goes to 3-state after the 19th SCLK falling edge or when
CONVST goes high, whichever occurs first.
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4-Wire CS Mode Without a Busy Indicator
This interface option is useful when one or more ADCs are connected to an SPI-compatible digital host.
Figure 53 shows the connection diagram for single ADC, Figure 55 shows the connection diagram for two ADCs.
CS
CNV
DIN
CONVST
DOUT
SDI
SCLK
CLK
ADC
Digital Host
Figure 53. Connection Diagram: Single ADC with 4-Wire CS Mode Without a Busy Indicator
In this interface option, DIN is controlled by the digital host and functions as CS. As shown in Figure 54, with DIN
high, a CONVST rising edge selects CS mode, forces DOUT to 3-state, samples the input signal, and causes the
device to enter a conversion phase. In this interface option, CONVST must be held at a high level from the start
of the conversion until all data bits are read. Conversion is done with the internal clock and continues regardless
of the state of DIN. As a result, DIN (functioning as CS) can be pulled low to select other devices on the board.
However, DIN must be pulled high before the minimum conversion time (tconv-min) elapses and remains high until
the maximum possible conversion time (tconv-max) elapses. A high level on DIN at the end of the conversion
ensures the device does not generate a busy indicator.
1/fsample
tconv-max
tACQ
tconv-min
CONVST
DIN = 1
DIN
SCLK
1
2
DOUT
D17
D16
œœ
17
18
œœ
ADC
STATE
End-ofConversion
Acquiring
Sample N
D1
D0
œœ
Read Sample N
Converting
Sample N
Acquiring Sample N+1
Figure 54. Interface Timing Diagram: Single ADC with 4-Wire CS Mode
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When conversion is complete, the device enters acquisition phase and powers down. DIN (functioning as CS)
can be brought low after the maximum conversion time (tconv-max) has elapsed. On the DIN falling edge, DOUT
comes out of 3-state and the device outputs the MSB of the data. The lower data bits are output on subsequent
SCLK falling edges. Data are valid on both SCLK edges. Data are valid on both edges of SCLK and can be
captured on either edge. However, a digital host capturing data on the SCLK falling edge can achieve a faster
reading rate (provided th_CK_DO is acceptable). DOUT goes to 3-state after the 18th SCLK falling edge or when
DIN goes high, whichever occurs first.
As shown in Figure 55, multiple devices can be hooked together on the same data bus. In this case, as shown in
Figure 56, the DIN of the second device (functioning as CS for the second device) can go low after the first
device data are read and the DOUT of the first device is in 3-state.
Care must be taken so that CONVST and DIN are not both low together at any time during the cycle.
CS1
CS2
CNV
CONVST
DIN
CONVST
DIN
DOUT
DOUT
SCLK
SDI
SCLK
CLK
ADC #1
ADC #2
Digital Host
Figure 55. Connection Diagram: Two ADCs with 4-Wire CS Mode Without a Busy Indicator
1/fsample
tconv-max
tACQ
tconv-min
CONVST
DIN = 1
DIN
(ADC 1)
DIN = 1
DIN
(ADC 2)
SCLK
1
2
DOUT
D17
D16
œœ
17
18
19
20
D0
D17
D16
ADC
STATE
Acquiring
Sample N
Converting
Sample N
36
œœ
œœ
End-ofConversion
œœ
35
D1
D1
D0
œœ
œœ
Read Sample N
ADC 1
Read Sample N
ADC 2
Acquiring Sample N+1
Figure 56. Interface Timing Diagram: Two ADCs with 4-Wire CS Mode Without a Busy Indicator
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4-Wire CS Mode With a Busy Indicator
This interface option is most useful when a single ADC is connected to an SPI-compatible digital host and an
interrupt-driven data transfer is desired. In this interface option, the analog sample is least affected by clock jitter
because the CONVST signal (used to sample the input) is independent of the data read operation. In this
interface option, DIN is controlled by the digital host and functions as CS (as shown in Figure 57). The pull-up
resistor on the DOUT pin ensures that the IRQ pin of the digital host is held high when DOUT goes to 3-state. As
shown in Figure 58, when DIN is high, a CONVST rising edge selects CS mode, forces DOUT to 3-state,
samples the input signal, and causes the device to enter a conversion phase. In this interface option, CONVST
must be held high from the start of the conversion until all data bits are read. Conversion is done with the internal
clock and continues regardless of the state of DIN. As a result, DIN (acting as CS) can be pulled low to select
other devices on the board. However, DIN must be pulled low before the minimum conversion time (tconv-min)
elapses and remains low until the maximum possible conversion time (tconv-max) elapses. A low level on the DIN
input at the end of a conversion ensures the device generates a busy indicator.
CS
DIN
CNV
CONVST
CLK
SCLK
DVDD
DOUT
SDI
IRQ
ADC
Digital Host
Figure 57. Connection Diagram: 4-Wire CS Mode With a Busy Indicator
1/fsample
tACQ
tconv-max
tconv-min
CONVST
DIN =0
DIN
SCLK
1
2
3
D17
D16
œœ
17
18
19
D1
D0
œœ
DOUT
ADC
STATE
SDO Pulled-up
Acquiring
Sample N
Converting
Sample N
BUSY
D2
œœ
Conversion Result of Sample N Clocked-out
while Acquiring Sample N+1
Figure 58. Interface Timing Diagram: 4-Wire CS Mode With a Busy Indicator
When conversion is complete, the device enters an acquisition phase and powers down, DOUT comes out of 3state, and the device outputs a busy indicator bit (low level) on the DOUT pin. This configuration provides a highto-low transition on the IRQ pin of the digital host. The data bits are clocked out, MSB first, on the subsequent
SCLK falling edges. Data are valid on both SCLK edges. Data are valid on both edges of SCLK and can be
captured on either edge. However, a digital host capturing data on the SCLK falling edge can achieve a faster
reading rate (provided th_CK_DO is acceptable). DOUT goes to 3-state after the 19th SCLK falling edge or when
DIN goes high, whichever occurs first.
Care must be taken so that CONVST and DIN are not both low together at any time during the cycle.
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DAISY-CHAIN MODE
Daisy-chain mode is selected if DIN is low at the time of a CONVST rising edge or if DIN and CONVST are
connected together. Similar to CS mode, this mode features operation with or without a busy indicator. The
following sections discuss these interface modes in detail.
Daisy-Chain Mode Without a Busy Indicator
This interface option is most useful in applications where multiple ADC devices are used but the digital host has
limited interfacing capability. Figure 59 shows a connection diagram with N ADCs connected in the daisy-chain.
The CONVST pins of all ADCs in the chain are connected together and are controlled by a single pin of the
digital host. Similarly, the SCLK pins of all ADCs in the chain are connected together and are controlled by a
single pin of the digital host. The DIN pin for ADC 1 is connected to GND. The DOUT pin of ADC 1 is connected
to the DIN pin of ADC 2, and so on. The DOUT pin of the last ADC in the chain (ADC N) is connected to the SDI
pin of the digital host.
CNV
CONVST
DIN
DOUT
SCLK
CONVST
DIN
CONVST
DOUT
}
DIN
SCLK
CONVST
DOUT
DIN
SCLK
SDI
DOUT
SCLK
CLK
ADC 1
ADC 2
}
ADC N
ADC N1
Digital Host
Figure 59. Connection Diagram: Daisy-Chain Mode Without a Busy Indicator (DIN = 0)
As shown in Figure 60, the device DOUT pin is driven low when DIN and CONVST are low together. With DIN
low, a CONVST rising edge selects daisy-chain mode, samples the analog input, and causes the device to enter
a conversion phase. In this interface option, CONVST must remain high from the start of the conversion until all
data bits are read. When started, the conversion continues regardless of the state of SCLK, however SCLK must
be low at the CONVST rising edge so that the device does not generate a busy indicator at the end of the
conversion.
tconv-min
1/fsample
tconv-max
tACQ
CONVST
SCLK
1
2
œœ
17
18
19
20
D17
D16
œœ
35
36
DIN 1 = LOW
œœ
DOUT 1
DIN 2
D17
D16
D1
D0
D1
D0
œœ
œœ
D17
DOUT 2
œœ
œœ
End-ofConversion
ADC
STATE
D16
Acquiring
Sample N
Converting
Sample N
D1
D0
œœ
Read Sample N
ADC 2
Read Sample N
ADC 1
Acquiring Sample N+1
Figure 60. Interface Timing Diagram: For Two devices in Daisy-Chain Mode Without a Busy Indicator
26
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At the end of conversion, every ADC in the chain loads its own conversion result into the internal, 18-bit, shift
register and also outputs the MSB bit of this conversion result on its own DOUT pin. All ADCs enter an
acquisition phase and power-down. On every subsequent SCLK falling edge, the internal shift register of each
ADC latches the data available on its DIN pin and shifts out the next bit of data on its DOUT pin. Therefore, the
digital host receives the data of ADC N, followed by the data of ADC N-1, and so on (in MSB-first fashion). A
total of 18 x N SCLK falling edges are required to capture the outputs of all N devices in the chain. Data are valid
on both SCLK edges. Data are valid on both edges of SCLK and can be captured on either edge. However, a
digital host capturing data on the SCLK falling edge can achieve a faster reading rate (provided th_CK_DO is
acceptable).
Daisy-Chain Mode With a Busy Indicator
This interface option is most useful in applications where multiple ADC devices are used but the digital host has
limited interfacing capability and an interrupt-driven data transfer is desired. Figure 61 shows a connection
diagram with N ADCs connected in the daisy-chain. The CONVST pins of all ADCs in the chain are connected
together and are controlled by a single pin of the digital host. Similarly, the SCLK pins of all ADCs in the chain
are connected together and are controlled by a single pin of the digital host. The DIN pin for ADC 1 is connected
to its CONVST. The DOUT pin of ADC 1 is connected to the DIN pin of ADC 2, and so on. The DOUT pin of the
last ADC in the chain (ADC N) is connected to the SDI and IRQ pins of the digital host.
CNV
CONVST
DIN
DOUT
CONVST
DIN
DOUT
SCLK
SCLK
ADC 1
ADC 2
CONVST
}
DIN
DOUT
CONVST
DIN
DOUT
SCLK
SCLK
ADC N1
ADC N
IRQ
SDI
CLK
}
Digital Host
Figure 61. Connection Diagram: Daisy-Chain Mode With a Busy Indicator (DIN = 0)
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As shown in Figure 62, the device DOUT pin is driven low when DIN and CONVST are low together. A CONVST
rising edge selects daisy-chain mode, samples the analog input, and causes the device to enter a conversion
phase. In this interface option, CONVST must remain high from the start of the conversion until all data bits are
read. When started, the conversion continues regardless of the state of SCLK, however SCLK must be high at
the CONVST rising edge so that the device generates a busy indicator at the end of the conversion.
tconv-min
1/fsample
tconv-max
tACQ
CONVST
SCLK
1
th-DI-CNV
2
œœ
18
19
20
21
D17
D16
œœ
36
37
DIN 1 =
CONVST
œœ
DOUT 1
DIN 2
BUSY
D17
D1
D0
D1
D0
œœ
œœ
BUSY
DOUT 2
œœ
œœ
End-ofConversion
ADC
STATE
D17
Acquiring
Sample N
Converting
Sample N
D1
D0
œœ
Read Sample N
ADC 2
Read Sample N
ADC 1
Acquiring Sample N+1
Figure 62. Interface Timing Diagram: For Two Devices in Daisy-Chain Mode With a Busy Indicator
At the end of conversion, every ADC in the chain loads its own conversion result into the internal, 18-bit, shift
register and also forces its DOUT pin high, thereby providing a low-to-high transition on the IRQ pin of the digital
host. All ADCs enter an acquisition phase and power-down. On every subsequent SCLK falling edge, the internal
shift register of each ADC latches the data available on its DIN pin and shifts out the next bit of data on its DOUT
pin. Therefore, the digital host receives the interrupt signal followed by the data of ADC N followed by the data of
ADC N-1, and so on (in MSB-first fashion). A total of (18 x N) + 1 SCLK falling edges are required to capture the
outputs of all N devices in the chain. Data are valid on both edges of SCLK and can be captured on either edge.
However, a digital host capturing data on the SCLK falling edge can achieve a faster reading rate (provided
th_CK_DO is acceptable). Note that the busy indicator bits of ADC 1 to ADC N-1 do not propagate to the next
device in the chain.
28
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POWER SUPPLY
The device has two separate power supplies: AVDD and DVDD. The internal circuits of the device operate on
AVDD; DVDD is used for the digital interface. AVDD and DVDD can be independently set to any value within the
permissible range.
Decouple the AVDD and DVDD pins with GND, using individual 1-µF decoupling capacitors placed in close
proximity to the pin, as shown in Figure 63.
Digital
Supply
REF
Analog
Supply
AVDD
1 µF
DVDD
DIN
AINP
SCLK
AINN
DOUT
GND
CONVST
1 µF
Figure 63. Supply Decoupling
POWER SAVING
The device has an auto power-down feature that powers down the internal circuitry at the end of every
conversion. The input signal is acquired on the sampling capacitors while the device is in power-down state; at
the same time, the result for the previous conversion is available for reading. The device powers up on the start
of the next conversion. The conversion time, tconv, is independent of the SCLK frequency. As a result, device
power consumption is directly proportional to the speed of operation.
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APPLICATION INFORMATION
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This
section details some general principles for designing these circuits, followed by some application circuits
designed using the ADS8881.
ADC REFERENCE DRIVER
The external reference source to the device must provide low-drift and very accurate voltages for ADC reference
input and support the dynamic charge requirements without affecting the noise and linearity performance of the
device. The output broadband noise of most references can be in the order of a few 100 μVRMS. Therefore, in
order to prevent any degradation in the noise performance of the ADC, the output of the voltage reference must
be appropriately filtered by using a low-pass filter with a cutoff frequency of few hundred Hertz.
After band-limiting the noise of the reference circuit, the next important step is to design a reference buffer that
can drive the dynamic load posed by the reference input of the ADC. The reference buffer must regulate the
voltage at the reference pin such that the value of VREF stays within 1-LSB error at the start of each conversion.
This condition necessitates the use of a large capacitor, CBUF_FLT (Refer to Figure 47) for regulating the voltage
at the reference input of the ADC. The amplifier selected to drive the reference pin should have an extremely low
offset and temperature drift with a low output impedance to drive the capacitor at the ADC reference pin without
any stability issues.
Reference Driver Circuit for VREF = 4.5 V DC
The application circuit in Figure 64 shows the schematic of a complete reference driver circuit that generates a
voltage of 4.5 V dc using a single 5-V supply. This circuit is suitable to drive the reference of the ADS8881 at
higher sampling rates up to 1 MSPS. The reference voltage of 4.5 V in this design is generated by the highprecision and low-noise REF5045 circuit. The output broadband noise of the reference is heavily filtered by a
low-pass filter with a 3-dB cutoff frequency of 160 Hz.
20k
1µF
-
AVDD
REF5045
Vin
1k
+
Vout
THS4281
1k
+
OPA333
+
AVDD
+
0.2
1µF
AVDD
Temp
1µF
AVDD
REF AVDD
10µF
AINP
V+
CONVST
ADS8881
Gnd Trim
AINM
GND
1µF
Figure 64. Schematic of Reference Driver Circuit with VREF = 4.5 V DC
The reference buffer is designed using the THS4281 and OPA333 in a composite architecture to achieve
superior dc and ac performance at a reduced power consumption, compared to using a single high-performance
amplifier. The THS4281 is a high-bandwidth amplifier with a very low output impedance of 1 Ω at a frequency of
1 MHz. The low output impedance makes the THS4281 a good choice for driving a high capacitive load to
regulate the voltage at the reference input of the ADC. The high offset and drift specifications of the THS4281
are corrected by using a dc-correcting amplifer (OPA333) inside the feedback loop. The composite scheme
inherits the extremely low offset and temperature drift specifications of the OPA333.
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to 18-Bit Data Acquisition (DAQ) Block Optimized for 1-μs Full-Scale Step Response (SLAU512).
30
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Reference Driver Circuit for VREF = 2.5 V DC in Ultralow Power, Lower Throughput Applications
The application circuit in Figure 65 shows the schematic of a complete reference driver circuit that generates a
voltage of 2.5 V dc using a single 3.3-V supply. This ultralow power reference block is suitable to drive the
ADS8881 for power-sensitive applications at a relatively lower throughput. This design uses the high-precision
REF3325 circuit that provides an accurate 2.5-V reference voltage at an extremely low quiescent current of 5 µA.
The output broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of
16 Hz.
1k 1µF
REF3325
IN
AVDD
10k OUT
AVDD
4.7 OPA313
+ +
REF AVDD
22µF
GND
1µF
AVDD
AINP
V+
CONVST
ADS8881
AINM
GND
Figure 65. Schematic of Reference Driver Circuit with VREF = 2.5 V DC
The reference buffer is designed using the low-power OPA313 that can operate from a 3.3-V supply at an
extremely low quiescent current of 50 µA. The wideband noise contribution from the amplifier is limited by a lowpass filter of a cutoff frequency equal to 1.5 kHz, formed by a 4.7-Ω resistor in combination with a 22-µF
capacitor. The series resistor of 4.7 Ω creates an additional drop in the reference voltage, which is corrected by a
dual-feedback configuration.
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to 18-Bit, 10kSPS Data Acquisition (DAQ) Block Optimized for Ultra Low Power < 1mW
(SLAU514).
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ADC INPUT DRIVER
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a fly-wheel
RC filter. The amplifier is used for signal conditioning of the input voltage and its low output impedance provides
a buffer between the signal source and the switched capacitor inputs of the ADC. The RC filter helps to attenuate
the sampling charge injection from the switched-capacitor input stage of the ADC as well as acts as an
antialiasing filter to band-limit the wideband noise contributed by the front-end circuit. A careful design of the
front-end circuit is critical to meet the linearity and noise performance of a high-precision, 18-bit ADC such as the
ADS8881.
Input Amplifier Selection
Selection criteria for the input amplifiers is highly dependent on the input signal type as well as the performance
goals of the data acquisition system. Some key amplifier specifications to consider while selecting an appropriate
amplifier to drive the inputs of the ADS8881 are:
• Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible
after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance
of the amplifier, thus allowing the amplifier to more easily drive the low cutoff frequency RC filter (refer to the
Antialiasing Filter section) at the inputs of the ADC. Higher bandwidth also minimizes the harmonic distortion
at higher input frequencies. In order to maintain the overall stability of the input driver circuit, the amplifier
bandwidth should be selected as described in Equation 2:
•
§
·
1
¸¸
Unity Gain Bandwidth t 4 u ¨¨
© 2S u RFLT u CFLT ¹
(2)
Noise. Noise contribution of the front-end amplifiers should be as low as possible to prevent any degradation
in SNR performance of the system. As a rule of thumb, to ensure that the noise performance of the data
acquisition system is not limited by the front-end circuit, the total noise contribution from the front-end circuit
should be kept below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is bandlimited by designing a low cutoff frequency RC filter, as explained in Antialiasing Filter.
2
§ V 1 _ AM P_ PP ·
S
¨
¸
2
NG u 2 u ¨ f
¸¸ en _ RM S u 2 u f3dB
6.6
¨
©
¹
d
§ SNR dB ·
¸
20
¹
¨
1 VREF
u
u 10 ©
5
2
where:
•
•
•
•
•
V1 / f_AMP_PP is the peak-to-peak flicker noise in µVRMS,
en_RMS is the amplifier broadband noise density in nV/√Hz,
f–3dB is the 3-dB bandwidth of the RC filter, and
NG is the noise gain of the front-end circuit, which is equal to '1' in a buffer configuration.
THD AMP d THD ADC 10 dB
•
32
(3)
Distortion. Both the ADC and the input driver introduce nonlinearity in a data acquisition block. As a rule of
thumb, to ensure that the distortion performance of the data acquisition system is not limited by the front-end
circuit, the distortion of the input driver should be at least 10 dB lower than the distortion of the ADC, as
shown in Equation 4.
(4)
Settling Time. For dc signals with fast transients that are common in a multiplexed application, the input signal
must settle within an 18-bit accuracy (4 ppm) at the inputs of the ADS8881, during the acquisition time
window. This condition is critical to maintain the overall linearity performance of the ADC. Typically, the
amplifier data sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be
sufficient for the desired 18-bit accuracy. Therefore, the settling behavior of the input driver should always be
verified by TINA™-SPICE simulations before selecting the amplifier.
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Antialiasing Filter
Converting analog-to-digital signals requires sampling an input signal at a constant rate. Any higher frequency
content in the input signal beyond half the sampling frequency is digitized and folded back into the low-frequency
spectrum. This process is called aliasing. Therefore, an analog, antialiasing filter must be used to remove the
harmonic content from the input signal before being sampled by the ADC. An antialiasing filter is designed as a
low-pass, RC filter, for which the 3-dB bandwidth is optimized based on specific application requirements. For dc
signals with fast transients (including multiplexed input signals), a high-bandwidth filter is designed to allow
accurately settling the signal at the inputs of the ADC during the small acquisition time window. For ac signals,
the filter bandwidth should be kept low to band-limit the noise fed into the input of the ADC, thereby increasing
the signal-to-noise ratio (SNR) of the system.
Besides filtering the noise from the front-end drive circuitry, the RC filter also helps attenuate the sampling
charge injection from the switched-capacitor input stage of the ADC. A differential capacitor, CFLT, is connected
across the inputs of the ADC (as shown in Figure 66). This capacitor helps reduce the sampling charge injection
as well as provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the
acquisition process. As a rule of thumb, the value of this capacitor should be at least 10 times the specified value
of the ADC sampling capacitance. For the ADS8881, the input sampling capacitance is equal to 59 pF, thus the
value of CFLT should be greater than 590 pF. The capacitor should be a COG- or NPO-type because these
capacitor types have a high-Q, low-temperature coefficient, and stable electrical characteristics under varying
voltages, frequency, and time.
RFLT ” 22
f 3 dB
2S u R FLT
1
R FLT u C FLT
AINP
V+
CFLT • 590 pF
ADS8881
AINM
GND
RFLT ” 22
Figure 66. Antialiasing Filter
Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a
result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance,
input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability
and distortion of the design. For the ADS8881, TI recommends limiting the value of RFLT to a maximum of 22 Ω
in order to avoid any significant degradation in linearity performance. The tolerance of the selected resistors can
be chosen as 1% because the use of a differential capacitor at the input balances the effects resulting from any
resistor mismatch.
The input amplifier bandwidth should be much higher than the cutoff frequency of the antialiasing filter. TI
strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase
margin with the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some amplifiers
might require more bandwidth than others to drive similar filters. If an amplifier has less than a 40° phase margin
with 22-Ω resistors, using a different amplifier with higher bandwidth or reducing the filter cutoff frequency with a
larger differential capacitor is advisable.
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APPLICATION CIRCUIT EXAMPLES
This section describes some common application circuits using the ADS8881. These data acquisition (DAQ)
blocks are optimized for specific input types and performance requirements of the system. For simplicity, powersupply decoupling capacitors are not shown in these circuit diagrams; refer to the Power Supply section for
suggested guidelines.
DAQ Circuit for 1-µs, Full-Scale Step Response
The application circuit shown in Figure 67 is optimized for using the ADS8881 at the maximum-specified
throughput of 1 MSPS for a full-scale step input voltage. Such step input signals are common in a multiplexed
application when switching between different channels. In a worst-case scenario, one channel is at the negative
full-scale (NFS) and the other channel is at the positive full-scale (PFS) voltage, in which case the step size is
the full-scale range (FSR) of the ADC when the MUX channel is switched.
In such applications, the primary design requirement is to ensure that the full-scale step input signal settles to 18bit accuracy at the inputs of the ADC. This condition is critical to achieve the excellent linearity specifications of
the ADC. Therefore, the bandwidth of the antialiasing RC filter should be large enough to allow optimal settling of
the input signal during the ADC acquisition time. The filter capacitor helps reduce the sampling charge injection
at the inputs of the ADC, but degrades the phase margin of the driving amplifier, thereby leading to stability
issues. Amplifier stability is maintained by the series isolation resistor. Therefore, the component values of the
antialiasing filter should be carefully selected to meet the settling requirements of the system as well as to
maintain the stability of the input driving amplifiers.
For the input driving amplifiers, key specifications include rail-to-rail input and output swing, high bandwidth, high
slew-rate, and fast settling time. The OPA350 CMOS amplifier meets all these specification requirements for this
circuit with a single-supply and low quiescent current.
REFERENCE DRIVE CIRCUIT
20k
1µF
-
THS4281
+
0.2
-
1k
+
AVDD
OPA333
1µF
+
1k
+
REF5045
Vout
Vin
AVDD
AVDD
10µF
Temp
1µF
Trim Gnd
1µF
+
AVDD
VIN+
+
AVDD
+
OPA350
10
REF AVDD
VCM
AINP
V+
1nF
CONVST
ADS8881
AINM
GND
+
VIN-
-
CONVST
10
OPA350
+
+
AVDD
INPUT DRIVER
18-Bit 1MSPS
SAR ADC
Figure 67. DAQ Circuit for 1-µs, Full-Scale Step Response
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to 18-Bit Data Acquisition (DAQ) Block Optimized for 1-μs Full-Scale Step Response (SLAU512).
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Low-Power DAQ Circuit for Excellent Dynamic Performance at 1 MSPS
The application circuit shown in Figure 68 is optimized for using the ADS8881 at the maximum specified
throughput of 1 MSPS for a full-scale sinusoidal signal of 10-kHz frequency. This circuit achieves excellent
dynamic performance for the lowest power consumption. The differential ac input signal is processed through
low-noise and low-power amplifiers configured as unity-gain buffers and a low-pass, RC filter before being fed
into the ADC.
In such applications, the input driver must be low in power and noise as well as able to support rail-to-rail input
and output swing with a single supply. A high amplifier bandwidth is also preferred because it helps attenuate
high-frequency distortion, but oftentimes bandwidth and noise are traded off with the power consumption of the
amplifier. This circuit uses the OPA320 as the front-end driving amplifier because this device has a relatively low
noise density of 7 nV/√Hz for a maximum-specified quiescent current of 1.85 mA per channel.
The noise contribution from the front-end amplifier is band-limited by the 3-dB bandwidth of the RC filter, which is
designed to be 1.65 MHz in this application. Again, the component values of the antialiasing filter are carefully
selected to maintain the stability of the input driving amplifiers.
REFERENCE DRIVE CIRCUIT
20k
1µF
-
THS4281
+
0.2
-
1k
AVDD
OPA333
+
1µF
+
1k
+
REF5045
Vout
Vin
AVDD
AVDD
10µF
Temp
1µF
Trim Gnd
1µF
+
AVDD
VIN+
+
AVDD
+
OPA320
22
REF AVDD
VCM
AINP
V+
2.2nF
CONVST
ADS8881
AINM
GND
+
VIN-
-
CONVST
22
OPA320
+
+
AVDD
INPUT DRIVER
18-Bit 1MSPS
SAR ADC
Figure 68. DAQ Circuit for Lowest Power and Excellent Dynamic Performance at 1 MSPS
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to 18-Bit, 1-MSPS Data Acquisition (DAQ) Block Optimized for Lowest Power (SLAU513).
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DAQ Circuit for Lowest Distortion and Noise Performance at 1 MSPS
This section describes two application circuits (Figure 69 and Figure 70) that are optimized for using the
ADS8881 with lowest distortion and noise performance at a throughput of 1 MSPS. In both applications, the input
signal is processed through a high-bandwidth and low-distortion, fully-differential amplifier (FDA) designed in an
inverting gain configuration and a low-pass RC filter before being fed into the ADC.
As a rule of thumb, the distortion from the input driver should be at least 10 dB less than the ADC distortion. The
distortion resulting from variation in the common-mode signal is eliminated by using the FDA in an inverting gain
configuration that establishes a fixed common-mode level for the circuit. This configuration also eliminates the
requirement of rail-to-rail swing at the input of the amplifier. Therefore, these circuits use the low-power THS4521
as an input driver, which provides exceptional ac performance because of its extremely low-distortion and highbandwidth specifications.
In addition, the components of the antialiasing filter are such that the noise from the front-end circuit is kept low
without adding distortion to the input signal.
Differential Input Configuration
The circuit in Figure 69 shows a fully-differential DAQ block optimized for low distortion and noise using the
THS4521 and ADS8881. This front-end circuit configuration requires a differential signal at the input of the FDA
and provides a differential output to the drive the inputs of the ADC. The common-mode of the input signal
provided to the ADC is set by the VOCM pin of the THS4521 (not shown in the schematic). To use the complete
dynamic range of the ADC, VOCM can be set to VREF / 2 by using a simple resistive divider. However, note that
the ADS8881 allows the common-mode input voltage (VCM) to be set to any value in the range of 0 V to VREF.
REFERENCE DRIVE CIRCUIT
20k
1µF
-
THS4281
+
0.2
-
1k
+
AVDD
OPA333
1µF
+
1k
+
REF5045
Vout
Vin
AVDD
AVDD
10µF
Temp
1µF
Trim Gnd
1µF
1K
1K
AVDD
AVDD
VIN+
10
+ + -
VCM
THS4521
-
REF AVDD
AINP
V+
10nF
+
AINM
10
GND
CONVST
+
VIN-
CONVST
ADS8881
1K
1K
INPUT DRIVER
18-Bit 1MSPS
SAR ADC
Figure 69. Differential Input DAQ Circuit for Lowest Distortion and Noise at 1 MSPS
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to 18-Bit, 1-MSPS Data Acquisition (DAQ) Block Optimized for Lowest Distortion and Noise
(SLAU515).
36
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Product Folder Links: ADS8881
ADS8881
www.ti.com
SBAS547A – MAY 2013 – REVISED JULY 2013
Single-Ended to Differential Configuration
The circuit in Figure 70 shows a single-ended to differential DAQ block optimized for low distortion and noise
using the THS4521 and the ADS8881. This front-end circuit configuration requires a single-ended ac signal at
the input of the FDA and provides a fully-differential output to drive the inputs of the ADC. The common-mode of
the input signal provided to the ADC is set by the VOCM pin of the THS4521 (not shown in the schematic). To use
the complete dynamic range of the ADC, VOCM can be set to VREF / 2 by using a simple resistive divider.
However, note that the ADS8881 allows the common-mode input voltage (VCM) to be set to any value in the
range of 0 V to VREF.
REFERENCE DRIVE CIRCUIT
20k
1µF
-
THS4281
+
0.2
-
1k
+
AVDD
OPA333
1µF
+
1k
+
REF5045
Vout
Vin
AVDD
AVDD
10µF
Temp
1µF
Trim Gnd
1µF
1K
1K
AVDD
AVDD
VIN+
10
+ + THS4521
-
REF AVDD
AINP
V+
10nF
+
AINM
10
1K
CONVST
ADS8881
GND
1K
INPUT DRIVER
CONVST
18-Bit 1MSPS
SAR ADC
Figure 70. Single-Ended to Differential DAQ Circuit for Lowest Distortion and Noise at 1 MSPS
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Product Folder Links: ADS8881
37
ADS8881
SBAS547A – MAY 2013 – REVISED JULY 2013
www.ti.com
Ultralow-Power DAQ Circuit at 10 kSPS
The data acquisition circuit shown in Figure 71 is optimized for using the ADS8881 at a reduced throughput of 10
kSPS with ultralow-power consumption (< 1 mW) targeted at portable and battery-powered applications.
In order to save power, this circuit is operated on a single 3.3-V supply. The circuit uses extremely low-power,
dual amplifiers (such as the OPA2333) with a maximum quiescent current of 28 µA per channel to drive the
inputs of the ADC. The input amplifiers are configured in a modified unity-gain buffer configuration. The filter
capacitor at the inputs of the ADC attenuates the sampling charge-injection noise from the ADC but effects the
stability of the input amplifiers by degrading the phase margin. This attenuation requires a series isolation resistor
to maintain amplifier stability. The value of the series resistor is directly proportional to the open-loop output
impedance of the driving amplifier to maintain stability, which is high (in the order of kΩ) in the case of low-power
amplifiers such as the OPA333. Therefore, a high value of 1 kΩ is selected for the series resistor at the inputs of
the ADC. However, this series resistor creates an additional voltage drop in the signal path, thereby leading to
linearity and distortion issues. The dual-feedback configuration used in Figure 71 corrects for this additional
voltage drop and maintains system performance at ultralow-power consumption.
1k REFERENCE DRIVE CIRCUIT
1µF
REF3325
IN
OUT
AVDD
4.7 OPA313
+ +
10k 22µF
GND
1µF
AVDD
10k AVDD
10nF
REF AVDD
AINP
CONVST
ADS8881
AINM
-
1k CONVST
GND
+
OPA333
+
+
VIN+
VCM
AVDD
4.7nF
VIN-
+
+
+
OPA333
1k 18-Bit 10kSPS
SAR ADC
-
10nF
INPUT DRIVER
10k Figure 71. Ultralow-Power DAQ Circuit at 10 kSPS
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to 18-Bit, 10kSPS Data Acquisition (DAQ) Block Optimized for Ultra Low Power < 1mW
(SLAU514).
38
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Product Folder Links: ADS8881
ADS8881
www.ti.com
SBAS547A – MAY 2013 – REVISED JULY 2013
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (May 2013) to Revision A
•
Page
Changed document status to Production Data; pre-RTM changes made throughout document ......................................... 1
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Product Folder Links: ADS8881
39
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jul-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
ADS8881IDGS
ACTIVE
VSSOP
DGS
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
8881
ADS8881IDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
8881
ADS8881IDRCR
PREVIEW
SON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
8881
ADS8881IDRCT
PREVIEW
SON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
8881
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jul-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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