Cypress CY7C375IL-83AC Ultralogic 128-macrocell flash cpld Datasheet

USE ULTRA37000™
FOR ALL NEW DESIGNS
CY7C375i
UltraLogic™ 128-Macrocell Flash CPLD
Features
• 3.3V or 5.0V I/O operation
• Available in 160-pin TQFP, CQFP, and PGA packages
• 128 macrocells in eight logic blocks
• 128 I/O pins
Functional Description
• Five dedicated inputs including 4 clock pins
The CY7C375i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
FLASH370i™ family of high-density, high-speed CPLDs. Like
all members of the FLASH370i family, the CY7C375i is
designed to bring the ease of use and high performance of the
22V10 to high-density PLDs.
• In-System Reprogrammable (ISR™) Flash technology
— JTAG Interface
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
Like all of the UltraLogic™ FLASH370i devices, the CY7C375i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins. The ISR interface is enabled
using the programming voltage pin (ISREN). Additionally,
because of the superior routability of the FLASH370i devices,
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
• High speed
— fMAX = 125 MHz
— tPD = 10 ns
— tS = 5.5 ns
— tCO = 6.5 ns
• Fully PCI compliant
Logic Block Diagram
Inputs
1
4
INPUT/CLOCK
MACROCELLS
4
INPUT
MACROCELL
4
I/O0–I/O15
16 I/Os
LOGIC
BLOCK
36
A
16 I/Os
I/O16–I/O31
16
LOGIC
BLOCK
B
16 I/Os
I/O32–I/O47
LOGIC
BLOCK
C
16 I/Os
I/O48–I/O63
LOGIC
BLOCK
D
Clock
Inputs
LOGIC
BLOCK
36
PIM
36
16
16
36
36
16
16
36
36
16
16
I/O112–I/O127
H
16
36
16 I/Os
LOGIC
BLOCK
16 I/Os
I/O96–I/O111
G
16 I/Os
LOGIC
BLOCK
I/O80–I/O95
F
16 I/Os
LOGIC
BLOCK
I/O64–I/O79
E
64
64
Selection Guide
7C375i–125 7C375i–100 7C375i–83
7C375iL–83
7C375i–66 7C375iL–66 Unit
Maximum Propagation Delay[1], tPD
10
12
15
15
20
20
ns
Minimum Set-Up, tS
5.5
6
8
8
10
10
ns
Maximum Clock to Output[1], tCO
6.5
7
8
8
10
10
ns
Typical Supply Current, ICC
125
125
125
75
125
75
mA
Note:
1. The 3.3V I/O mode timing adder, t3.3IO, must be added to this specification when VCCIO = 3.3V
Cypress Semiconductor Corporation
Document #: 38-03029 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised May 10, 2004
USE ULTRA37000™
FOR ALL NEW DESIGNS
CY7C375i
Pin Configurations
GND
I/O16
I/O17
I/O18
I/O19
I/O20 /SCLK
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
CLK0/I0
VCCIO
GND
CLK1/I1
I/O 116
I/O 115
I/O 114
I/O 113
I/O 112
GND
I/O 120
GND
I/O 119
I/O 118
I/O 117
GND
VCCINT
ISREN
I/O 127
I/O 126
I/O 125
I/O 124
I/O 123
I/O 122
I/O 121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
83
82
81
VCCIO
I/O111
I/O110
I/O109
I/O108 /SDI
I/O107
I/O106
I/O105
I/O104
GND
I/O103
I/O102
I/O101
I/O100
I/O99
I/O98
I/O97
I/O96
CLK3/I4
GND
VCCIO
CLK2/I3
I/O95
I/O94
I/O93
I/O92
I/O91
I/O90
I/O89
I/O88
GND
I/O87
I/O86
I/O85
I/O84
I/O83
I/O82
I/O81
I/O80
GND
Document #: 38-03029 Rev. *A
I/O78
I/O79
VCCIO
VCCINT
I/O64
I/O65
I/O66
I/O67
I/O68
I/O69
I/O70
I/O71
GND
I/O72
I/O73
I/O74
I/O75
I/O76 /SDO
I/O77
GND
I/O52 /SMODE
I/O53
I/O54
I/O55
GND
I/O56
I/O57
I/O58
I/O59
I/O60
I/O61
I/O62
I/O63
I2
VCCIO
GND
I/O48
I/O49
I/O50
I/O51
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
GND
I/O40
I/O41
I/O42
I/O43
I/O44
I/O45
I/O46
I/O47
VCCIO
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
VCCIO
I/O 13
I/O 12
I/O 11
I/O 10
I/O 9
I/O 8
GND
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
VCCIO
I/O 15
I/O 14
Top View
TQFP
Page 2 of 17
USE ULTRA37000™
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CY7C375i
Pin Configurations (continued)
GND
I/O16
I/O17
I/O18
I/O19
I/O20 /SCLK
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
CLK0/I0
VCC
GND
CLK1/I1
I/O 116
I/O 115
I/O 114
I/O 113
I/O 112
GND
I/O 120
GND
I/O 119
I/O 118
I/O 117
GND
VCC
ISREN
I/O 127
I/O 126
I/O 125
I/O 124
I/O 123
I/O 122
I/O 121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
83
82
81
VCC
I/O111
I/O110
I/O109
I/O108 /SDI
I/O107
I/O106
I/O105
I/O104
GND
I/O103
I/O102
I/O101
I/O100
I/O99
I/O98
I/O97
I/O96
CLK3/I4
GND
VCC
CLK2/I3
I/O95
I/O94
I/O93
I/O92
I/O91
I/O90
I/O89
I/O88
GND
I/O87
I/O86
I/O85
I/O84
I/O83
I/O82
I/O81
I/O80
GND
Document #: 38-03029 Rev. *A
I/O78
I/O79
VCC
I/O64
I/O65
I/O66
I/O67
I/O68
I/O69
I/O70
I/O71
GND
I/O72
I/O73
I/O74
I/O75
I/O76 /SDO
I/O77
GND
VCC
I/O52 /SMODE
I/O53
I/O54
I/O55
GND
I/O56
I/O57
I/O58
I/O59
I/O60
I/O61
I/O62
I/O63
I2
VCC
GND
I/O48
I/O49
I/O50
I/O51
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
GND
I/O40
I/O41
I/O42
I/O43
I/O44
I/O45
I/O46
I/O47
VCC
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
VCC
I/O 13
I/O 12
I/O 11
I/O 10
I/O 9
I/O 8
GND
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
VCC
I/O 15
I/O 14
Top View
CQFP
Page 3 of 17
USE ULTRA37000™
FOR ALL NEW DESIGNS
CY7C375i
Pin Configurations (continued)
PGA
Bottom View
R
I/O109
I/O112 I/O115
I/O118
I/O121 I/O123
I/O126
I/O127
I/O0
I/O3
I/O5
I/O7
I/O10
I/O11
I/O14
P
I/O106
I/O110 I/O113
I/O116
I/O119 I/O122
I/O125
GND
I/O1
I/O4
I/O6
I/O9
I/O13
I/O15
I/O16
N
I/O105
I/O108
I/O111
/SDI
I/O114
I/O117 I/O120
I/O124
ISREN
I/O2
GND
I/O8
I/O12
GND
I/O17
I/O19
M
I/O102
I/O104 I/O107
VCC
VCC
GND
VCC
GND
I/O18
I/O20
/SCLK
I/O22
L
I/O100
I/O101 I/O103
I/O21
I/O23
I/O25
K
I/O98
I/O99
GND
I/O24
I/O26
I/O27
J
I/O96
I/O97
CLK3
/I4
VCC
VCC
CLK28
I/O29
I/O30
H
I/O95
GND
CLK2
/I3
GND
GND
CLK0
/I0
GND
I/O31
G
I/O94
I/O93
I/O92
VCC
VCC
CLK1
/I1
I/O33
I/O32
F
I/O91
I/O90
I/O88
GND
I/O35
I/O34
E
I/O89
I/O87
I/O85
I/O39
I/O37
I/O36
D
I/O86
I/O84
I/O82
GND
VCC
I/O43
I/O40
I/O38
C
I/O83
I/O81
GND
I/O76
/SDO
I/O72
I/O50
I/O47
I/O44
I/O41
B
I/O80
I/O79
I/O77
I/O73
I/O52/
I/O49
SMODE
I/O46
I/O42
A
I/O78
I/O75
I/O74
I/O71
I/O51
I/O48
I/O45
1
2
3
13
14
4
VCC
GND
VCC
GND
I/O66
I2
I/O60
I/O56
I/O53
I/O70
I/O68
I/O65
GND
I/O61
I/O58
I/O55
I/O69
I/O67
I/O64
I/O63
I/O62
I/O59
I/O57
7
8
9
5
6
Functional Description
The 128 macrocells in the CY7C375i are divided between
eight logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
The logic blocks in the FLASH370i architecture are connected
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings
flexibility, routability, speed, and a uniform delay to the interconnect.
Like all members of the FLASH370i family, the CY7C375i is rich
in I/O resources. Every macrocell in the device features an
associated I/O pin, resulting in 128 I/O pins on the CY7C375i.
In addition, there is one dedicated input and four input/clock
pins.
Finally, the CY7C375i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect
delays, or expander delays. Regardless of the number of
resources used or the type of application, the timing parameters on the CY7C375i remain the same.
Document #: 38-03029 Rev. *A
10
11
I/O71
12
15
Logic Block
The number of logic blocks distinguishes the members of the
FLASH370i family. The CY7C375i includes eight logic blocks.
Each logic block is constructed of a product term array, a
product term allocator, and 16 macrocells.
Product Term Array
The product term array in the FLASH370i logic block includes
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are
available in both positive and negative polarity, making the
overall array size 72 x 86. This large array in each logic block
allows for very complex functions to be implemented in single
passes through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macrocells (this is called
product term steering). Furthermore, product terms can be
shared among multiple macrocells. This means that product
terms that are common to more than one output can be implemented in a single product term. Product term steering and
Page 4 of 17
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product term sharing help to increase the effective density of
the FLASH370i PLDs. Note that product term allocation is
handled by software and is invisible to the user.
I/O Macrocell
Each of the macrocells on the CY7C375i has a separate I/O
pin associated with it. The input to the macrocell is the sum of
between 0 and 16 product terms from the product term
allocator. The macrocell includes a register that can be
optionally bypassed, polarity control over the input sum-term,
and four global clocks to trigger the register. The macrocell
also features a separate feedback path to the PIM so that the
register can be buried if the I/O pin is used as an input.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
eight logic blocks on the CY7C375i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Programming
For an overview of ISR programming, refer to the FLASH370i
Family data sheet and for ISR cable and software specifications, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An
Introduction to In System Reprogramming with FLASH370i.”
PCI Compliance
The FLASH370i family of CMOS CPLDs are fully compliant with
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
FLASH370i ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term
distribution.
Document #: 38-03029 Rev. *A
CY7C375i
3.3V or 5.0V I/O Operation
The FLASH370i family can be configured to operate in both
3.3V and 5.0V systems. All devices have two sets of VCC pins:
one set, VCCINT, for internal operation and input buffers, and
another set, VCCIO, for I/O output drivers. VCCINT pins must
always be connected to a 5.0V power supply. However, the
VCCIO pins may be connected to either a 3.3V or 5.0V power
supply, depending on the output requirements. When VCCIO
pins are connected to a 5.0V source, the I/O voltage levels are
compatible with 5.0V systems. When VCCIO pins are
connected to a 3.3V source, the input voltage levels are
compatible with both 5.0V and 3.3V systems, while the output
voltage levels are compatible with 3.3V systems. There will be
an additional timing delay on all output buffers when operating
in 3.3V I/O mode. The added flexibility of 3.3V I/O capability is
available in commercial and industrial temperature ranges.
Bus Hold Capabilities on all I/Os and Dedicated Inputs
In addition to ISR capability, a new feature called bus-hold has
been added to all FLASH370i I/Os and dedicated input pins.
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
recalls the last state of a pin when it is three-stated, thus
reducing system noise in bus-interface applications. Bus-hold
additionally allows unused device pins to remain unconnected
on the board, which is particularly useful during prototyping as
designers can route new signals to the device without cutting
trace connections to VCC or GND.
Design Tools
Development software for the CY7C375i is available from
Cypress’s Warp®, Warp Professional™, and Warp Enterprise™ software packages. Please refer to the data sheets on
these products for more details. Cypress also actively
supports almost all third-party design tools. Please refer to
third-party tool support for further information.
Page 5 of 17
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Maximum Ratings
CY7C375i
Output Current into Outputs ........................................ 16 mA
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-up Current..................................................... > 200 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Range
Commercial
DC Voltage Applied to Outputs
in High-Z State ............................................... –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
Industrial
DC Program Voltage .....................................................12.5V
Military[2]
Ambient
Temperature
0°C to +70°C
VCC VCCINT
VCCIO
5V ± 0.25V 5V ± 0.25V or
3.3V ± 0.3V
−40°C to +85°C 5V ± 0.5V 5V ± 0.5V or
3.3V ± 0.3V
–55°C to +125°C 5V ± 0.5V
Electrical Characteristics Over the Operating Range[3, 4]
Parameter
Description
Test Conditions
Min.
Typ.
Max. Unit
VOH
Output HIGH Voltage
VCC = Min. IOH = –3.2 mA (Com’l/Ind)[5]
VOHZ
Output HIGH Voltage with Output
Disabled[9]
VCC = Max. IOH = 0 µA (Com’l/Ind)[5, 6]
4.0
V
IOH = –50 µA
3.6
V
VOL
Output LOW Voltage
VCC = Min. IOL = 16 mA (Com’l/Ind)[5]
0.5
V
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH voltage for all
inputs[7]
2.0
7.0
V
VIL
Input LOW Voltage
Guaranteed Input Logical LOW voltage for all
inputs[7]
–0.5
0.8
V
IIX
Input Load Current
VI = Internal GND, VI = VCC
–10
+10
µA
IOZ
Output Leakage Current
+50
µA
–125
µA
2.4
V
IOH = –2.0 mA (Mil)
V
(Com’l/Ind)[5, 6]
IOL = 12 mA (Mil)
V
VCC = Max., VO = GND or VO = VCC, Output Disabled –50
VCC = Max., VO = 3.3V, Output Disabled[6]
Current[8, 9]
IOS
Output Short Circuit
ICC
Power Supply Current[10]
VCC = Max., VOUT = 0.5V
VCC = Max., IOUT = 0 mA,
f = 1 MHz, VIN = GND, VCC
0
–70
–30
Com’l/Ind.
–160 mA
125
200
mA
Com’l “L” –66
75
125
mA
Military
125
250
mA
IBHL
Input Bus Hold LOW Sustaining Current VCC = Min., VIL = 0.8V
+75
µA
IBHH
Input Bus Hold HIGH Sustaining Current VCC = Min., VIH = 2.0V
–75
µA
IBHLO
Input Bus Hold LOW Overdrive Current VCC = Max.
+500
µA
IBHHO
Input Bus Hold HIGH Overdrive Current VCC = Max.
–500
µA
Capacitance[9]
Parameter
CI/O[11]
CCLK
Description
Input/Output Capacitance
Clock Signal Capacitance
Test Conditions
VIN = 5.0V at f=1 MHz
VIN = 5.0V at f = 1 MHz
Min.
5
Max.
8
12
Unit
pF
pF
Notes:
2. TA is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. If VCCIO is not specified, the device can be operating in either 3.3V or 5V I/O mode; VCC=VCCINT.
5. IOH = –2 mA, IOL = 2 mA for SDO.
6. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly by
a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note “Understanding Bus Hold” for additional information.
7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
9. Tested initially and after any design or process changes that may affect these parameters.
10. Measured with 16-bit counter programmed into each logic block.
11. CI/O for dedicated inputs, and for I/O pins with JTAG functionality is 12 pF,and for the ISREN pin is 15 pF Max.
Document #: 38-03029 Rev. *A
Page 6 of 17
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FOR ALL NEW DESIGNS
CY7C375i
Inductance[9]
Parameter
L
Test Conditions
160-Lead
TQFP
160-Pin
CQFP
160-Pin
CPGA
Unit
VIN = 5.0V at 5 = 1 MHz
9
6
10
nH
Description
Maximum Pin Inductance
Endurance Characteristics[9]
Parameter
Description
N
Maximum Reprogramming Cycles
Test Conditions
Max.
Unit
Normal Programming Conditions
100
Cycles
AC Test Loads and Waveforms
238Ω (COM'L)
319Ω (MIL)
238Ω (COM'L)
319Ω (MIL)
5V
5V
OUTPUT
OUTPUT
35 pF
INCLUDING
JIG AND
(a)
SCOPE
170Ω (COM'L)
236Ω (MIL)
5 pF
170Ω (COM'L)
236Ω (MIL)
ALL INPUT PULSES
3.0V
90%
GND
90%
10%
10%
<2ns
<2ns
INCLUDING
JIG AND
(b)
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
99Ω (COM'L)
136Ω (MIL) 2.08V(COM'L)
OUTPUT
2.13V(MIL)
Parameter[12]
VX
tER(–)
1.5V
Output Waveforms--Measurement Level
VOH
tER(+)
0.5V
VX
0.5V
VOH
0.5V
VOL
1.5V
VX
tEA(–)
VX
2.6V
VOL
tEA(+)
0.5V
Vthe
VX
(d) Test Waveforms
Note:
12. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
Document #: 38-03029 Rev. *A
Page 7 of 17
USE ULTRA37000™
FOR ALL NEW DESIGNS
CY7C375i
Switching Characteristics Over the Operating Range [13]
Parameter
Description
7C375i–125
7C375i–100
7C375i–83
7C374iL–83
7C375i–66
7C375iL–66
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Unit
Combinatorial Mode Parameters
tPD
Input to Combinatorial Output[1]
10
12
15
20
ns
tPDL
Input to Output Through Transparent Input
or Output Latch[1]
13
15
18
22
ns
tPDLL
Input to Output Through Transparent Input
and Output Latches[1]
15
16
19
24
ns
tEA
Input to Output Enable[1]
14
16
19
24
ns
tER
Input to Output Disable
14
16
19
24
ns
Input Registered/Latched Mode Parameters
tWL
Clock or Latch Enable Input LOW Time[9]
tWH
Clock or Latch Enable Input HIGH
Time[9]
3
3
4
5
ns
tIS
Input Register or Latch Set-Up Time
2
2
3
4
ns
tIH
Input Register or Latch Hold Time
2
tICO
Input Register Clock or Latch Enable to
Combinatorial Output[1]
14
16
19
24
ns
tICOL
Input Register Clock or Latch Enable to
Output Through Transparent Output Latch[1]
16
18
21
26
ns
10
ns
3
3
4
2
5
3
ns
4
ns
Ouptut Registered/Latched Mode Parameters
tCO
Clock or Latch Enable to Output[1]
tS
Set-Up Time from Input to Clock or Latch
Enable
tH
Register or Latch Data Hold Time
tCO2
Output Clock or Latch Enable to Output
Delay (Through Memory Array)[1]
tSCS
Output Clock or Latch Enable to Output
Clock or Latch Enable (Through Memory
Array)
8
10
12
15
ns
tSL
Set-Up Time from Input Through Transparent Latch to Output Register Clock or
Latch Enable
10
12
15
20
ns
tHL
Hold Time for Input Through Transparent
Latch from Output Register Clock or Latch
Enable
0
0
0
0
ns
fMAX1
Maximum Frequency with Internal
Feedback (Least of 1/tSCS, 1/(tS + tH), or
1/tCO)[9]
125
100
83
66
MHz
fMAX2
158.3
Maximum Frequency Data Path in Output
Registered/Latched Mode (Lesser of 1/(tWL
+ tWH), 1/(tS + tH), or 1/tCO)
143
125
100
MHz
fMAX3
Maximum Frequency with External
Feedback (Lesser of 1/(tCO + tS) and 1/(tWL
+ tWH,
83.3
76.9
62.5
50
MHz
tOH–tIH
37x
Output Data Stable from Output Clock
Minus Input Register Hold Time for 7C37x[9,
0
0
0
0
ns
6.5
7
8
5.5
6
8
10
ns
0
0
0
0
ns
14
16
19
24
ns
14]
Notes:
13. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
14. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C375i. This specification is met for
the devices operating at the same ambient temperature and at the same power supply voltage.
Document #: 38-03029 Rev. *A
Page 8 of 17
USE ULTRA37000™
FOR ALL NEW DESIGNS
CY7C375i
Switching Characteristics Over the Operating Range (continued)[13]
Parameter
Description
7C375i–125
7C375i–100
7C375i–83
7C374iL–83
7C375i–66
7C375iL–66
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Unit
Pipelined Mode Parameters
tICS
Input Register Clock to Output Register
Clock
fMAX4
Maximum Frequency in Pipelined Mode
(Least of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH),
1/(tIS + tIH), or 1/tSCS)
8
10
12
15
ns
125
100
83.3
66.6
MHz
Reset/Preset Parameters
tRW
Asynchronous Reset Width[9]
10
12
15
20
ns
tRR
Asynchronous Reset Recovery Time[9]
12
14
17
22
ns
tRO
Asynchronous Reset to Output
tPW
Asynchronous Preset Width[9]
[1]
16
10
Time[9]
tPR
Asynchronous Preset Recovery
tPO
Asynchronous Preset to Output[1]
18
12
12
14
16
21
15
17
18
26
20
ns
22
21
ns
ns
26
ns
Tap Controller Parameter
fTAP
Tap Controller Frequency
500
500
500
500
kHz
3.3V I/O Mode Parameters
t3.3IO
3.3V I/O mode timing adder
1
1
1
1
ns
Switching Waveforms
Combinatorial Output
INPUT
tPD
COMBINATORIAL
OUTPUT
Registered Output
INPUT
tS
tH
CLOCK
tCO
REGISTERED
OUTPUT
tWH
tWL
CLOCK
Document #: 38-03029 Rev. *A
Page 9 of 17
USE ULTRA37000™
FOR ALL NEW DESIGNS
CY7C375i
Switching Waveforms (continued)
Latched Output
INPUT
tH
tS
LATCH ENABLE
tCO
tPDL
LATCHED
OUTPUT
Registered Input
REGISTERED
INPUT
tIH
tIS
INPUT REGISTER
CLOCK
tICO
COMBINATORIAL
OUTPUT
tWH
tWL
CLOCK
Clock to Clock
REGISTERED
INPUT
INPUT REGISTER
CLOCK
tICS
tSCS
OUTPUT
REGISTER CLOCK
Document #: 38-03029 Rev. *A
Page 10 of 17
USE ULTRA37000™
FOR ALL NEW DESIGNS
CY7C375i
Switching Waveforms (continued)
Latched Input
LATCHED INPUT
tIH
tIS
LATCH ENABLE
tICO
tPDL
COMBINATORIAL
OUTPUT
tWH
tWL
LATCH ENABLE
Latched Input and Output
LATCHED INPUT
tPDLL
LATCHED
OUTPUT
tICOL
tSL
tHL
INPUT LATCH
ENABLE
tICS
OUTPUT LATCH
ENABLE
tWH
tWL
LATCH ENABLE
Document #: 38-03029 Rev. *A
Page 11 of 17
USE ULTRA37000™
FOR ALL NEW DESIGNS
CY7C375i
Switching Waveforms (continued)
Asynchronous Reset
tRW
INPUT
tRO
REGISTERED
OUTPUT
tRR
CLOCK
Asynchronous Preset
tPW
INPUT
tPO
REGISTERED
OUTPUT
tPR
CLOCK
Output Enable/Disable
INPUT
tER
tEA
OUTPUTS
Ordering Information
Speed
(MHz)
Ordering Code
Package
Name
Package Type
Operating
Range
125
CY7C375i–125AC
A160
160-Lead Thin Quad Flatpack
Commercial
100
CY7C375i–100AC
A160
160-Lead Thin Quad Flatpack
Commercial
CY7C375i–100AI
A160
160-Lead Thin Quad Flatpack
Industrial
CY7C375i–83AC
A160
160-Lead Thin Quad Flatpack
Commercial
CY7C375i–83AI
A160
160-Lead Thin Quad Flatpack
Industrial
CY7C375i–83GMB
G160
160-Pin Grid Array
Military
83
Flatpack[15]
CY7C375i–83UMB
U162
160-Pin Ceramic Quad
CY7C375iL–83AC
A160
160-Lead Thin Quad Flatpack
Document #: 38-03029 Rev. *A
Commercial
Page 12 of 17
USE ULTRA37000™
FOR ALL NEW DESIGNS
CY7C375i
Ordering Information (continued)
Speed
(MHz)
66
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C375i–66AC
A160
160-Lead Thin Quad Flatpack
Commercial
CY7C375i–66AI
A160
160-Lead Thin Quad Flatpack
Industrial
CY7C375i–66GMB
G160
160-Pin Grid Array
Military
CY7C375i–66UMB
U162
160-Pin Ceramic Quad Flatpack[15]
CY7C375iL–66AC
A160
160-Lead Thin Quad Flatpack
Commercial
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1, 2, 3
VOL
1, 2, 3
VIH
1, 2, 3
VIL
1, 2, 3
IIX
1, 2, 3
IOZ
1, 2, 3
ICC
1, 2, 3
Switching Characteristics
Parameter
Subgroups
tPD
9, 10, 11
tCO
9, 10, 11
tICO
9, 10, 11
tS
9, 10, 11
tH
9, 10, 11
tIS
9, 10, 11
tIH
9, 10, 11
tICS
9, 10, 11
Note:
15. Standard product ships trim and formed in a carrier. This product is also available in a molded carrier ring. Contact local Cypress office for package information.
Document #: 38-03029 Rev. *A
Page 13 of 17
USE ULTRA37000™
FOR ALL NEW DESIGNS
CY7C375i
Package Diagrams
160-Pin Thin Plastic Quad Flat Pack (24 x 24 x 1.4 mm)(TQFP) A160
51-85049-*B
Document #: 38-03029 Rev. *A
Page 14 of 17
USE ULTRA37000™
FOR ALL NEW DESIGNS
CY7C375i
Package Diagrams (continued)
160-Pin PGA G160
51-80012-*A
Document #: 38-03029 Rev. *A
Page 15 of 17
USE ULTRA37000™
FOR ALL NEW DESIGNS
CY7C375i
Package Diagrams (continued)
160-Lead Ceramic Quad Flatpack (Cavity Up) U162
25.35±0.10
(.998±.004)
TYP.
DIMENSION IN MM (INCH)
REFERENCE JEDEC: N/A
PKG. WEIGHT: 6-7gms
PIN 1
0.650(.0256)
TYP.
0.300(.012)
TYP.
R 0.13(.005)
MIN.
0°-7°
28.00 ±0.10
(1.102 ±.004)
SQ.
0.20 MIN.
(.008 MIN.)
0° MIN.
31.20 ±0.25
(1.228 ±.010)
SQ.
SEATING PLANE
DETAIL A
SEE DETAIL A
2.03(.080)
2.79(.110)
0.15 ±0.02
(.006 ±.001)
0.050(.002)
0.500(.020)
0.51 ±0.20
(.020 ±.008)
51-80106-*A
Warp is a registered trademark and Ultra37000, Warp Professional, Warp Enterprise, ISR, UltraLogic, FLASH370 and FLASH370i
are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document are trademarks of their respective holders.
Document #: 38-03029 Rev. *A
Page 16 of 17
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
USE ULTRA37000™
FOR ALL NEW DESIGNS
CY7C375i
Document History Page
Document Title: CY7C375i UltraLogic™ 128-Macrocell Flash CPLD
Document Number: 38-03029
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
106374
09/15/01
SZV
Change from Spec number: 38-00494 to 38-03029
*A
213375
See ECN
FSG
Added note to title page: “Use Ultra37000 For All New Designs”
Document #: 38-03029 Rev. *A
Page 17 of 17
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