Mitsubishi MH8S64BALD-7 536870912-bit (8388608 - word by 64-bit)synchronousdram Datasheet

Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH8S64BALD is 8388608 - word by 64-bit
Synchronous DRAM module. This consists of eight
industry standard 8Mx8 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
-7
CLK Access Time
1pin
94pin
10pin
95pin
11pin
124pin
40pin
125pin
41pin
168pin
84pin
(Component SDRAM)
6.0ns(CL=3)
-8
100MHz
100MHz
-10
100MHz
8.0ns(CL=3)
6.0ns(CL=3)
Utilizes industry standard 8M x 8 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
Front side
Back side
Frequency
85pin
single 3.3V±0.3V power supply
Clock frequency 100MHz
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
Discrete IC and module design conform to
PC100 specification.
(module Spec. Rev. 1.0 and
SPD 1.2A(-7,-8), SPD 1.0(-10))
APPLICATION
PC main memory
MIT-DS-0224-0.5
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
PIN NO.
PIN NAME
PIN NO.
PIN NAME
PIN NO.
PIN NO.
PIN NAME
1
VSS
43
VSS
85
PIN NAME
VSS
127
VSS
2
DQ0
44
NC
86
DQ32
128
CKE0
3
DQ1
45
/S2
87
DQ33
129
4
DQ2
46
DQMB2
88
DQ34
130
NC
DQMB6
5
DQ3
47
DQMB3
89
DQ35
131
DQMB7
6
VDD
48
NC
90
VDD
132
7
DQ4
49
VDD
91
DQ36
133
NC
VDD
8
DQ5
50
NC
92
DQ37
134
NC
9
DQ6
51
NC
93
DQ38
135
NC
10
DQ7
52
NC
94
DQ39
136
NC
11
53
DQ40
137
54
NC
VSS
95
12
DQ8
VSS
96
VSS
138
NC
VSS
13
DQ9
55
DQ16
97
DQ41
139
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
VDD
101
DQ45
143
VDD
18
VDD
60
DQ20
102
VDD
144
DQ52
19
DQ14
61
NC
103
DQ46
145
NC
20
NC
104
DQ47
146
NC
105
NC
147
NC
106
DQ15
62
21
NC
63
22
64
VSS
65
DQ21
107
NC
VSS
148
23
NC
VSS
NC
VSS
149
DQ53
24
NC
66
DQ22
108
NC
150
DQ54
25
NC
67
109
NC
151
DQ55
26
68
110
VDD
152
VSS
27
VDD
/WE0
DQ23
VSS
69
DQ24
111
/CAS
153
DQ56
28
DQMB0
70
DQ25
112
DQMB4
154
DQ57
29
DQMB1
71
DQ26
113
DQMB5
155
DQ58
30
/S0
72
DQ27
114
DQ59
NC
73
VDD
115
NC
/RAS
156
31
157
VDD
32
VSS
74
DQ28
116
VSS
158
DQ60
33
A0
75
DQ29
117
A1
159
DQ61
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
36
A6
78
VSS
120
A7
162
VSS
37
A8
79
A9
163
38
A10
80
CK2
NC
121
122
BA0
164
CK3
NC
39
81
SA0
124
A11
VDD
165
82
WP
SDA
123
40
BA1
VDD
166
SA1
41
42
VDD
CK0
83
84
SCL
VDD
125
126
CK1
NC
167
168
SA2
VDD
NC = No Connection
MIT-DS-0224-0.5
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Block Diagram
/S0
DQMB0
DQMB4
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB1
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB5
D0
DQM /CS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
DQM /CS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
/S2
DQMB2
DQMB6
DQM /CS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM /CS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB7
D2
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM /CS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
DQM /CS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D7
10Ω
10Ω
10Ω
CK0
4SDRAMs+3.3pF
4SDRAMs+3.3pF
/RAS
D0 - D7
CK2
/CAS
/WE
BA0,BA1,A<11:0>
Vcc
D0 - D7
D0 - D7
D0 - D7
D0 - D7
CK1
Vss
D0 - D7
10Ω
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ELECTRIC
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CK3
CKE0
10Ω
10pF
D0 - D7
SERIAL PD
SCL
WP
47K
MIT-DS-0224-0.5
10pF
A0 A1 A2
SDA
SA0 SA1 SA2
12.Nov.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
PIN FUNCTION
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
CKE0
Input
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
/S
(/S0,2)
Input
Chip Select: When /S is high,any command means
No Operation.
/RAS,/CAS,/WE
Input
Combination of /RAS,/CAS,/WE defines basic commands.
A0-11
Input
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-8.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
BA0,1
Input
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
CK
(CK0 ~ CK3)
DQ0-63
DQMB0-7
Vdd,Vss
Input/Output Data In and Data out are referenced to the rising edge of
CK
Input
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is high
in burst read,Dout is disabled at the next but one cycle.
Power Supply Power Supply for the memory mounted module.
SCL
Input
Serial clock for serial PD
SDA
Output
Serial data for serial PD
SA0-3
Input
MIT-DS-0224-0.5
Address input for serial PD
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH8S64BALD provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
/WE
Command
CKE
Refresh Option @refresh command
A10
Precharge Option @precharge or read/write command
define basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks are
deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
MIT-DS-0224-0.5
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
COMMAND TRUTH TABLE
CKE CKE
n-1
n
/RAS /CAS
A11
A10
A0-9
X
X
X
X
X
X
X
X
H
V
V
V
V
H
H
L
L
V
X
X
X
L
H
X
X
H
L
L
V
X
L
V
L
H
L
L
V
X
H
V
X
L
H
L
H
V
X
L
V
H
X
L
H
L
H
V
X
H
V
H
H
L
L
H
H
H
L
H
H
X
X
L
L
H
L
L
L
L
L
X
H
H
L
L
L
X
H
H
L
H
H
X
H
L
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
V*1
COMMAND
MNEMONIC
Deselect
No Operation
DESEL
NOP
H
H
X
X
H
L
X
H
X
H
X
H
Row Adress Entry &
Bank Activate
ACT
H
X
L
L
H
Single Bank Precharge
Precharge All Bank
PRE
PREA
H
H
X
X
L
L
L
L
Column Address Entry
& Write
WRITE
H
X
L
Column Address Entry
& Write with AutoPrecharge
WRITEA
H
X
Column Address Entry
& Read
READ
H
Column Address Entry
& Read with Auto
Precharge
READA
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
REFA
REFS
REFSX
Burst Terminate
Mode Register Set
TERM
MRS
/S
/WE BA0,1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE
/S
IDLE
H
L
X
H
X
H
X
H
X
X
L
H
H
L
BA
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
L
L
H
L
L
L
L
H
BA,A10
X
PRE/PREA
REFA
ROW ACTIVE
READ
/RAS /CAS
/WE
Address
Command
Current State
DESEL
NOP
Op-Code,
TBST
Action
NOP
NOP
ILLEGAL*2
READ/WRITE ILLEGAL*2
NOP*4
Auto-Refresh*5
L
L
L
L
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TBST
NOP
L
H
L
H
BA,CA,A10
L
H
L
L
BA,CA,A10
L
L
H
H
BA,RA
ACT
Bank Active/ILLEGAL*2
L
L
H
L
BA,A10
PRE/PREA
Precharge/Precharge All
L
L
L
H
X
L
L
L
L
H
X
X
X
X
DESEL
NOP(Continue Burst to END)
L
H
H
H
X
NOP
NOP(Continue Burst to END)
L
H
H
L
BA
TBST
Terminate Burst
Mode-Add
Op-Code,
Mode-Add
MRS
Bank Active,Latch RA
READ/READA
Mode Register Set*5
Begin Read,Latch CA,
Determine Auto-Precharge
WRITE/
Begin Write,Latch CA,
WRITEA
Determine Auto-Precharge
REFA
ILLEGAL
MRS
ILLEGAL
Terminate Burst,Latch CA,
L
H
L
H
BA,CA,A10
READ/READA Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
L
H
L
L
BA,CA,A10
WRITE/WRITEA Begin Write,Determine AutoPrecharge*3
MIT-DS-0224-0.5
L
L
H
H
BA,RA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
L
L
L
L
Op-Code,
Mode-Add
Bank Active/ILLEGAL*2
Terminate Burst,Precharge
REFA
ILLEGAL
MRS
ILLEGAL
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Preliminary Spec.
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MITSUBISHI LSIs
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State
WRITE
READ with
AUTO
PRECHARGE
WRITE with
AUTO
PRECHARGE
MIT-DS-0224-0.5
/S
H
L
L
/RAS /CAS
X
X
H
H
H
H
/WE
Address
X
X
H X
L
BA
L
H
L
H
BA,CA,A10
L
H
L
L
BA,CA,A10
L
L
H
H
BA,RA
L
L
L
L
H
L
L
H
BA,A10
X
L
L
L
L
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
H
Op-Code,
Mode-Add
X
X
BA
BA,CA,A10
L
H
L
L
BA,CA,A10
L
L
H
H
BA,RA
L
L
L
L
H
L
L
H
L
L
L
L
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
H
BA,A10
X
Op-Code,
Mode-Add
X
X
L
H
L
L
BA,CA,A10
L
L
L
L
L
L
H
H
L
H
L
H
BA,RA
L
L
L
L
BA
BA,CA,A10
BA,A10
X
Op-Code,
Mode-Add
Command
Action
DESEL
NOP(Continue Burst to END)
NOP
NOP(Continue Burst to END)
TBST
Terminate Burst
Terminate Burst,Latch CA,
READ/READA Begin Read,Determine AutoPrecharge*3
Terminate Burst,Latch CA,
WRITE/
Begin Write,Determine AutoWRITEA
Precharge*3
ACT
Bank Active/ILLEGAL*2
PRE/PREA
REFA
MRS
DESEL
NOP
TBST
READ/READA
WRITE/
WRITEA
ACT
PRE/PREA
REFA
MRS
DESEL
NOP
TBST
READ/READA
WRITE/
WRITEA
ACT
PRE/PREA
REFA
MRS
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Terminate Burst,Precharge
ILLEGAL
ILLEGAL
NOP(Continue Burst to END)
NOP(Continue Burst to END)
ILLEGAL
ILLEGAL
ILLEGAL
Bank Active/ILLEGAL*2
ILLEGAL*2
ILLEGAL
ILLEGAL
NOP(Continue Burst to END)
NOP(Continue Burst to END)
ILLEGAL
ILLEGAL
ILLEGAL
Bank Active/ILLEGAL*2
ILLEGAL*2
ILLEGAL
ILLEGAL
12.Nov.1998
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
/S
PRE -
H
X
X
X
X
DESEL
NOP(Idle after tRP)
CHARGING
L
H
H
H
X
NOP
NOP(Idle after tRP)
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
L
L
L
L
ROW
H
X
X
X
X
DESEL
NOP(Row Active after tRCD
ACTIVATING
L
H
H
H
X
NOP
NOP(Row Active after tRCD
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL*2
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL*2
L
L
L
H
X
L
L
L
L
WRITE RE-
H
X
X
X
X
DESEL
NOP
COVERING
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL*2
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL*2
L
L
L
H
X
L
L
L
L
MIT-DS-0224-0.5
/RAS /CAS
/WE
Address
Command
Current State
Action
READ/WRITE ILLEGAL*2
ILLEGAL*2
NOP*4(Idle after tRP)
REFA
ILLEGAL
MRS
ILLEGAL
Op-Code,
Mode-Add
READ/WRITE ILLEGAL*2
REFA
ILLEGAL
MRS
ILLEGAL
Op-Code,
Mode-Add
READ/WRITE ILLEGAL*2
REFA
ILLEGAL
MRS
ILLEGAL
Op-Code,
Mode-Add
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12.Nov.1998
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State
/S
/RAS /CAS
/WE
Address
RE-
H
X
X
X
X
DESEL
NOP(Idle after tRC)
FRESHING
L
H
H
H
X
NOP
NOP(Idle after tRC)
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
MODE
H
X
X
X
X
DESEL
NOP(Idle after tRSC)
REGISTER
L
H
H
H
X
NOP
NOP(Idle after tRSC)
SETTING
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
Op-Code,
Mode-Add
Op-Code,
Mode-Add
Command
Action
READ/WRITE ILLEGAL
READ/WRITE ILLEGAL
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
MIT-DS-0224-0.5
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Preliminary Spec.
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE FOR CKE
Current State
CKE
n-1
CKE
n
/S
SELF -
H
X
X
X
REFRESH*1
L
H
H
L
H
L
/RAS /CAS
Action
/WE
Add
X
X
X
INVALID
X
X
X
X
Exit Self-Refresh(Idle after tRC)
L
H
H
H
X
Exit Self-Refresh(Idle after tRC)
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP(Maintain Self-Refresh)
POWER
H
X
X
X
X
X
X
INVALID
DOWN
L
H
X
X
X
X
X
Exit Power Down to Idle
L
L
X
X
X
X
X
NOP(Maintain Self-Refresh)
ALL BANKS
H
H
X
X
X
X
X
Refer to Function Truth Table
IDLE*2
H
L
L
L
L
H
X
Enter Self-Refresh
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Refer to Current State = Power Down
ANY STATE
H
H
X
X
X
X
X
Refer to Function Truth Table
other than
H
L
X
X
X
X
X
Begin CK0 Suspend at Next Cycle*3
listed above
L
H
X
X
X
X
X
Exit CK0 Suspend at Next Cycle*3
L
L
X
X
X
X
X
Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All banks idle State.
3. Must be legal command.
MIT-DS-0224-0.5
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
REFS
REFSX
MRS
MODE
REGISTER
SET
REFA
AUTO
REFRESH
IDLE
CKEL
CKEH
CLK
SUSPEND
ACT
POWER
DOWN
CKEL
CKEH
TBST(for Full Page)
TBST(for Full Page)
ROW
ACTIVE
READ
WRITE
WRITE
SUSPEND
READA
WRITEA
CKEL
READ
WRITE
WRITE
CKEL
READ
CKEH
CKEH
WRITEA
READA
WRITEA
READA
CKEL
WRITEA
SUSPEND
POWER
APPLIED
READ
SUSPEND
CKEL
PRE
WRITEA
CKEH
POWER
ON
PRE
PRE
READA
PRE
CKEH
READA
SUSPEND
PRE
CHARGE
Automatic Sequence
Command Sequence
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP
condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 500us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which may
be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is
ready for new command.
CK
/S
BA0 BA1 A11 A10 A9
A8
A7 A6
0
0
A5
A4 A3
A2
A1 A0
/RAS
/CAS
0
0
0
0
WM
LTMODE
BT
BL
/WE
V
BA0,1 A11-0
LATENCY
MODE
WRITE
MODE
MIT-DS-0224-0.5
CL
000
001
010
011
100
101
110
111
0
1
/CAS LATENCY
R
R
2
3
R
R
R
R
BURST
SINGLE BIT
BURST
LENGTH
BURST
TYPE
BL
BT= 0
BT= 1
000
001
010
011
100
101
110
111
1
2
4
8
R
R
R
FP
1
2
4
8
R
R
R
R
0
1
SEQUENTIAL
INTERLEAVED
R:Reserved for Future Use
FP: Full Page
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ /CAS LATENCY]
/CAS latency,CL,is used to synchronize the first output data with the CLK frequency,i.e.,the
speed of CLK determines which CL should be used.First output data is available after CL
cycles from READ command.
/CAS Latency Timing(BL=4)
CK
ACT
Command
READ
tRCD
Address
X
Y
CL=2
DQ
Q0
CL=3
DQ
Q1
Q2
Q3
Q0
Q1
Q2
CL=2
Q3
CL=3
[ BURST LENGTH ]
The burst length,BL,determines the number of consecutive wrutes or reads that will be
automatically performed after the initial write or read command.For BL=1,2,4,8,full page the
output data is tristated(Hi-Z) after the last read.For BL=FP (Full Page),the TBST (Burst
Terminate) command should be issued to stop the output of data.
Burst Length Timing(CL=2)
tRCD
CK
Command
Address
ACT
READ
X
Y
DQ
Q0
DQ
Q0
Q1
DQ
Q0
Q1 Q2
Q3
DQ
Q0
Q1 Q2
Q3 Q4 Q5 Q6
Q7
DQ
Q0
Q1 Q2
Q3 Q4 Q5 Q6
Q7
BL=1
BL=2
BL=4
m=511
MIT-DS-0224-0.5
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BL=8
Q8
Qm Q0 Q1
BL=FP
Full Page counter rolls over
and continues to count.
12.Nov.1998
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
CK
Command
Read
Write
Y
Y
Address
Q0
DQ
CL= 3
BL= 4
/CAS Latency
Q1
Q2
Q3
D0
Burst Length
D1
D2
D3
Burst Length
Burst Type
Initial Address BL
Column Addressing
A2
A1
A0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
Sequential
Interleaved
8
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
-
0
0
0
1
2
3
0
1
2
3
-
0
1
1
2
3
0
1
0
3
2
4
-
1
0
2
3
0
1
2
3
0
1
-
1
1
3
0
1
2
3
2
1
0
-
-
0
0
1
0
1
1
0
1
0
2
-
-
1
MIT-DS-0224-0.5
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
OPERATION DESCRIPTION
BANK ACTIVATE
The SDRAM has four independent banks. Each bank is activated by the ACT command with
the bank address(BA0,1). A row is indicated by the row address A11-0. The minimum
activation interval between one bank and the other bank is tRRD.The number of banks which
are active concurrently is not limited.
PRECHARGE
The PRE command deactivates indicated by BA. When both banks are active, the precharge
all command(PREA,PRE + A10=H) is available to deactivate them at the same time. After tRP
from the precharge, an ACT command can be issued.
Bank Activation and Precharge All (BL=4, CL=3)
CLK
2ACT command/tRCmin
Command
ACT
tRCmin
ACT READ
tRRD
Y
Xa
Xb
0
Xa
Xb
00
01
Xa
A10
A11
ACT
tRP
tRAS
Xb
A0-9
PRE
Xb
tRCD
BA0,1
DQ
1
Xb
Xb
00
01
Qa0
Qa1
Qa2
Qa3
Precharge all
READ
After tRCD from the bank activation, a READ command can be issued. 1st output date is
available after the /CAS Latency from the READ, followed by (BL-1) consecutive date when
the Burst Length is BL. The start address is specified by A8-0, and the address sequence of
burst data is defined by the Burst Type. A READ command may be applied to any active bank,
so the row precharge time(tRP) can be hidden behind continuous output data(in case of BL=8)
by interleaving the dual banks. When A10 is high at a READ command, the
auto-precharge(READA) is performed. Any command (READ, WRITE, PRE, ACT) to the
same bank is inhibited till the internal precharge is complete. The internal precharge start at
BL after READA. The next ACT command can be issued after (BL + tRP) from the previous
READA.
MIT-DS-0224-0.5
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Multi Bank Interleaving READ (BL=4, CL=3)
CK
Command
ACT
A0-9
Xa
Y
Xb
Y
A10
Xa
0
Xb
0
0
A11
Xa
10
00
Qa1
Qa2
READ ACT
READ PRE
tRCD
BA0,1
Xb
00
00
10
DQ
Qa0
/CAS latency
Qa3
Qb0
Qb1
Qb2
Burst Length
READ with Auto-Precharge (BL=4, CL=3)
CK
BL + tRP
Command
ACT
A0-9
Xa
Y
Xa
A10
Xa
1
Xa
A11
Xa
BA0,1
00
READ
tRCD
ACT
tRP
BL
Xa
00
00
DQ
Qa0
Qa1
Qa2
Qa3
Internal precharge begins
READ Auto-Precharge Timing (BL=4)
CK
Command
ACT
READ
BL
CL=3
DQ
CL=2
DQ
Qa0
Qa0
Qa1
Qa2
Qa1
Qa2
Qa3
Qa3
Internal Precharge Start Timing
MIT-DS-0224-0.5
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set
at the same cycle as the WRITE. Following(BL-1) data are written into the RAM, when the
Burst Length is BL. The start address is specified by A8-0, and the address sequence of burst
data is defined by the Burst Type. A WRITE command may be applied to any active bank, so
the row precharge time(tRP) can be hidden behind continuous input data by interleaving the
multiple banks. From the last input data to the PRE command, the write recovery time (tWR) is
required. When A10 is high at a WRITE command, the auto-precharge(WRITEA) is
performed. Any command(READ, WRITE, PRE, ACT) to the same bank is inhibited till the
internal precharge is complete. The internal precharge begins at tWR after the last input data
cycle. The next ACT command can be issued after tRP from the internal precharge timing.
The Mode Register can be WRITE command is issued and the remaining burst length is
ignored.The read data burst length os unaffected while in this mode.
Multi Bank Interleaving WRITE (BL=4)
CK
Command
ACT
Write
ACT
tRCD
Write
PRE
PRE
0
0
0
0
10
00
10
Db0
Db1
tRCD
A0-9
Xa
Y
Xb
Y
A10
Xa
0
Xb
0
A11
Xa
BA0,1
00
Xb
DQ
00
10
Da0
Da1
Da2
Da3
Db2
Db3
WRITE with Auto-Precharge (BL=4)
CK
Command
ACT
Write
ACT
tRCD
tWR
tRP
A0-9
Xa
Y
Xa
A10
Xa
1
Xa
A11
Xa
BA0,1
DQ
00
Xa
00
Da0
00
Da1
Da2
Da3
Internal precharge begins
MIT-DS-0224-0.5
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ BURST WRITE ]
A burst write operation is enabled by setting A9=0 at MRS.A burst write stats in
the same cycle as a write command set.(The latency of data input is 0.) The
burst length can be set to 1,2,4,8,and full-page,like burst read operations.
tRCD
CK
Command
Address
ACT
READ
X
Y
DQ
Q0
DQ
Q0
Q1
DQ
Q0
Q1 Q2
Q3
DQ
Q0
Q1 Q2
Q3 Q4 Q5 Q6
Q7
DQ
Q0
Q1 Q2
Q3 Q4 Q5 Q6
Q7
BL=1
BL=2
BL=4
m=511
BL=8
Q8
BL=FP
Qm Q0 Q1
Full Page counter rolls over
and continues to count.
[ SINGLE WRITE ]
A single write operation is enabled by setting A9=1 at MRS.In a single write
operation,data is written only to the column address specified by the write
command set cycle without regard to the burst length setting.(The latency of data
input is 0.)
CK
Command
READ
ACT
tRCD
Address
DQ
MIT-DS-0224-0.5
X
Y
Q0
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read option can be interrupted by new read of any bank. Random column access is
allowed. READ to READ interval is minimum 1 CK
Read Interrupted by Read (BL=4, CL=3)
CK
Command
READ READ
READ
READ
A0-9
Yi
Yj
Yk
Yl
A10
0
0
0
0
00
00
10
01
A11
BA0,1
DQ
Qai0
Qaj0
Qaj1 Qbk0 Qbk1 Qbk2
Qal0 Qal1
Qal2
Qal3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of the same or the other bank. Random
column access is allowed. In this case, the DQ should be controlled adequately by using the
DQMB0-7 to prevent the bus contention. The output is disabled automatically 1 cycle after
WRITE assertion.
Read Interrupted by Write (BL=4, CL=3)
CK
Command
READ
Write
A0-9
Yi
Yj
A10
0
0
0
0
A11
BA0,1
DQMB0-7
Q
D
Qai0
Daj0
Daj1
Daj2
Daj3
DQM control Write control
MIT-DS-0224-0.5
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of the same or the other bank. Read
to PRE interval is minimum 1 CK. A PRE command output disable latency is equivalent to
the /CAS Latency.As a result, READ to PRE interval determines valid data length to be
output.The figure below shows examples of BL=4.
Read Interrupted by Precharge (BL=4)
CK
Command
READ
PRE
DQ
Q0
Q1
Q0
Q1
Q2
CL=3
Command
READ
PRE
DQ
Command
READ PRE
DQ
Command
Q0
PRE
READ
DQ
Q0
Q1
Q2
CL=2
Command
READ
DQ
Command
DQ
MIT-DS-0224-0.5
PRE
Q0
Q1
READ PRE
Q0
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Burst Terminate ]
Similarly to the precharge, burst terminate command,TBST, can interrupt burst read
operation and disable the data output. READ to TBST interval is minimum of 1 CK. TBST is
mainly used to interrupt FP bursts.The figure below show examples, of how the output data
is terminated with TBST.
Read Interrupted by Burst Terminate (BL=4)
CK
Command
READ
TBST
DQ
Command
Q0
READ
Q1
Q2
Q1
Q2
Q3
TBST
CL=3
DQ
Command
Q0
READ TBST
DQ
Command
Q0
DQ
Command
TBST
READ
Q0
Q1
Q2
Q3
TBST
READ
CL=2
DQ
Command
DQ
MIT-DS-0224-0.5
Q0
Q1
Q2
READ TBST
Q0
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of the same or the other bank.
Random column access is allowed. WRITE to WRITE interval is minimum 1 CK.
Write Interrupted by Write (BL=4)
CK
Command
Write Write
Write
Write
A0-9
Yi
Yj
Yk
Yl
A10
0
0
0
0
BA0,1
00
00
10
00
DQ
Dai0
Daj0
A11
Daj1
Dbk0 Dbk1 Dbk2 Dal0
Dal1
Dal2
Dal3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank.
Random column access is allowed. WRITE to READ interval is minimum 1 CK. The
input data on DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=3)
CK
Command
A0-9,11
A10
Write READ
Write
READ
Yi
Yj
Yk
Yl
0
0
0
0
00
00
10
00
A11
BA0,1
DQMB0-7
DQ
MIT-DS-0224-0.5
Dai0
Qaj0
Qaj1
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Dbk0 Dbk1
Qbl0
12.Nov.1998
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank. Random
column access is allowed. Because the write recovery time(tWR) is required from the
last data to PRE command.
Write Interrupted by Precharge (BL=4)
CK
Command
Write
PRE
tWR
A0-9,11
A10
Yi
Xb
0
0
Xb
A11
BA0,1
ACT
tRP
Xb
00
00
00
DQMB0-7
DQ
Dai0
Dai1
Dai2
[ Write Interrupted by Burst Terminate ]
A burst terminate command TBST can terminate burst write operation. In this case,
the write recovery time is not required and the bank remains active (Please see the
waveforms below).The WRITE to TBST minimum interval is 1CK.
Write Interrupted by Burst Terminate (BL=4)
CK
Command
Write
A0-9
Yi
A10
0
BA0,1
0
TBST
DQMB0-7
DQ
MIT-DS-0224-0.5
Dai0
Dai1
Dai2
MITSUBISHI
ELECTRIC
( 24 / 55 )
12.Nov.1998
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,
/WE=/CKE=H) command. The refresh address is generated internally. 4096 REFA
cycles within 64ms refresh 64Mbit memory cells. The auto-refresh is performed on
4bank concurrentry. Before performing an auto-refresh, all banks must be in the idle
state. Auto-refresh to Auto-refresh interval is minimum tRC.Any command must not be
supplied to the device before tRC from the REFA command.
Auto-Refresh
CK
/S
NOP or DESLECT
/RAS
/CAS
/WE
CKE
minimum tRC
A0-11
BA0,1
Auto Refresh on All Banks
MIT-DS-0224-0.5
Auto Refresh on All Banks
MITSUBISHI
ELECTRIC
( 25 / 55 )
12.Nov.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,
/WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is
kept low.During the self-refresh mode, CKE is asynchronous and the only enabled
input , all other inputs including CK are disabled and ignored, so that power
consumption due to synchronous inputs is saved. To exit the self-refresh, supplying
stable CK inputs, asserting DESEL or NOP command and then asserting
CKE(REFSX) for longer than tSRX. After tRC from REFSX all banks are in the idle
state and a new command can be issued after tRC, but DESEL or NOP commands
must be asserted till then.
Self-Refresh
CK
Stable CK
/S
NOP
/RAS
/CAS
/WE
CKE
tSRX
new command
A0-11
X
BA0,1
00
Self Refresh Entry
MIT-DS-0224-0.5
Self Refresh Exit
MITSUBISHI
ELECTRIC
( 26 / 55 )
minimum tRC
+1 CLOCK
for recovery
12.Nov.1998
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
CLK SUSPEND
CKE controls the internal CLK at the following cycle. Figure below shows how CKE
works. By negating CKE, the next internal CLK is suspended. The purpose of CLK
suspend is power down, output suspend or input suspend. CKE is a synchronous
input except during the self-refresh mode. CLK suspend can be performed either
when the banks are active or idle, A command at the following cycle is ignored.
ext.CLK
CKE
int.CLK
Power Down by CKE
CK
Standby Power Down
CKE
Command
PRE
NOP NOP NOP NOP NOP NOP NOP
Active Power Down
CKE
Command
NOP NOP NOP NOP NOP NOP NOP
ACT
DQ Suspend by CKE
CK
CKE
Command
DQ
MIT-DS-0224-0.5
Write
D0
READ
D1
D2
D3
MITSUBISHI
ELECTRIC
( 27 / 55 )
Q0
Q1
Q2
Q3
12.Nov.1998
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
DQM CONTROL
DQMB0-7 is a dual function signal defined as the data mask for writes and the output
disable for reads. During writes, DQMB0-7 masks input data word by word. DQMB0-7
to write mask latency is 0.
During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z
latency is 2.
DQM Function
CK
Command
READ
Write
DQMB0-7
DQ
D0
D2
D3
Q0
masked by DQM=H
MIT-DS-0224-0.5
Q1
Q3
disabled by DQM=H
MITSUBISHI
ELECTRIC
( 28 / 55 )
12.Nov.1998
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Condition
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 ~ 4.6
V
VI
Input Voltage
with respect to Vss
-0.5 ~ Vdd+0.5
V
VO
Output Voltage
with respect to Vss
-0.5 ~ Vdd+0.5
V
IO
Output Current
50
mA
Pd
Power Dissipation
8
W
Topr
Operating Temperature
0 ~ 70
°C
Tstg
Storage Temperature
-40 ~ 100
°C
Ta=25°C
RECOMMENDED OPERATING CONDITION
(Ta=0 ~ 70°C, unless otherwise noted)
Limits
Parameter
Symbol
Min.
Typ.
Max.
Unit
Vdd
Supply Voltage
3.0
3.3
3.6
V
Vss
Supply Voltage
0
0
0
V
VIH
High-Level Input Voltage all inputs
Low-Level Input Voltage all inputs
2.0
Vdd+0.3
V
-0.3
0.8
V
VIL
Note:* VIH (max) = Vdd+2.0V AC for pulse width<=3ns acceptable.
VIL (min) = -2V AC for pulse width< =3ns acceptable.
CAPACITANCE
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol
Parameter
Test Condition
CI(A)
Input Capacitance, address pin
CI(C)
Input Capacitance, /RAS,/CAS,/WE
VI = Vss
Limits(max.)
Unit
60
pF
60
pF
40
pF
CI(K)
Input Capacitance, CK pin
CI(S)
Input Capacitance, /CS pin
f=1MHz
40
pF
CI(E)
Input Capacitance, CKE pin
Vi=25mVrms
60
pF
CI(M) Input Capacitance, DQM pin
22
pF
CI/O
22
pF
MIT-DS-0224-0.5
Input Capacitance, I/O pin
MITSUBISHI
ELECTRIC
( 29 / 55 )
12.Nov.1998
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Parameter
Symbol
operating current
one bank active (discrete)
Icc1
precharge stanby current
in power-down mode
precharge stanby current
in non power-down mode
active stanby current
in power-down mode
active stanby current
in non power-down mode
one bank active (discrete)
burst current
auto-refresh current
self-refresh current
Limits
(max)
Test Condition
tRC=min.tCLK=min, BL=1, IOL=min
Icc2P
CKE=VILmax,tCLK=15ns
Icc2PS CKE=CLK=VILmax(fixed)
Icc2N CKE=/CS=VIHmin,tCLK=15ns(Note)
Icc2NS CKE=VIHmin,CLK=VILmax(fixed)
Icc3P CKE=VILmax,tCLK=15ns
Icc3PS CKE=CLK=VILmax(fixed)
Icc3N CKE=/CS=VIHmin,tCLK=15ns
Icc3NS CKE=VIHmin,CLK=VILmax(fixed)
Icc4 tCLK=min, BL=4, CL=3,IOL=0mAall banks active(discerte)
tRC=min, tCLK=min
Icc5
Icc6
CKE <0.2V
Unit
-7, -8
-10
880
680
mA
16
16
8
176
160
16
8
8
176
160
16
8
mA
mA
mA
mA
mA
mA
440
320
920
1200
360
320
920
920
8
8
mA
mA
mA
mA
mA
Note:Input signals are changed one time during 30ns.
Note:All other pins not under test are 0V.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol
VOH(DC)
VOL(DC)
VOH(AC
IOZ
)VOL(AC)
Ii
Parameter
High-Level Output Voltage(DC)
Low-Level Output Voltage(DC)
High-Level
Off-stare
Output
Output
Current
Voltage(AC)
Input
Current
Low-Level Output Voltage(AC)
MIT-DS-0224-0.5
Test Condition
IOH=-2mA
IOL=2mA
CL=50pF,
Q
floating VO=0 ~ Vdd
IOH=-2mA
CL=50pF,
VIH=0
~ Vdd+0.3V
IOL=2mA
MITSUBISHI
ELECTRIC
( 30 / 55 )
Limits
Unit
Min. Max.
2.4
V
0.4
V
2
-5
5 uA
V
0.8 uA
V
-40
40
12.Nov.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
AC TIMING REQUIREMENTS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
Input Timing Measurement Level: 1.4V
Symbol Parameter
tCLK
CK cycle time
CL=2
CL=3
tCH
CK High pulse width
tCL
CK Low pilse width
tT
Transition time of CK
tIS
Input Setup time(all inputs)
tIH
Input Hold time(all inputs)
tRC
Row cycle time
tRCD Row to Column Delay
tRAS Row Active time
tRP
Row Precharge time
tWR Write Recovery time
tRRD Act to Act Deley time
tCCD Col to Col Delay time
tRSC Mode Register Set Cycle time
tSRX Self Refresh Exit time
tREF Refresh Interval time
-7
Min. Max.
Limits
-8
Min. Max.
10
10
3
3
1
10
2
1
70
20
50 100K
20
10
20
10
20
10
64
13
10
3
3
1
10
2
1
70
20
50 100K
20
10
20
10
20
10
64
-10
Unit
Min. Max.
15
10
4
4
1
3
1
90
30
60
30
10
20
10
20
10
ns
ns
ns
ns
10 ns
ns
ns
ns
ns
100K ns
ns
ns
ns
ns
ns
ns
64 ms
Note
1
1
1
1
Note:1 The timing requirements are assumed tT=1ns.If tT is longer than 1ns,(tT-1)ns should
be added to the parameter.
CK
1.4V
Any AC timing is
referenced to the input
Signal
1.4V
signal crossing through
1.4V.
MIT-DS-0224-0.5
MITSUBISHI
ELECTRIC
( 31 / 55 )
12.Nov.1998
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
SWITCHING CHARACTERISTICS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise note3)
Limits
-7
-8
-10
Unit
Min. Max. Min. Max. Min. Max.
Symbol Parameter
tAC
tOH
tOLZ
tOHZ
Access time from CK
CL=2
6
7
8
ns
CL=3
6
6
8
ns
Output Hold time
from CK
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
3
3
3
ns
0
0
0
ns
3
6
3
6
3
8
ns
Note:3 If tr(clock rising time) is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
Output Load
Condition
VTT=1.4V
CK
1.4V
50Ω
VREF=1.4V
DQ
1.4V
VOUT
50pF
Output Timing
Measurement
Reference Point
CK
1.4V
DQ
1.4V
tAC
MIT-DS-0224-0.5
tOH
tOHZ
MITSUBISHI
ELECTRIC
( 32 / 55 )
12.Nov.1998
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Burst Write (single bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
tWR
CKE
DQM
A0-8
X
Y
A10
X
X
A9,11
X
X
BA0,1
0
0
D0
DQ
ACT#0
X
0
D0
WRITE#0
D0
0
D0
Y
0
D0
PRE#0
ACT#0
D0
D0
D0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0224-0.5
MITSUBISHI
ELECTRIC
( 33 / 55 )
12.Nov.1998
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Burst Write (multi bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
tWR
tWR
CKE
DQM
A0-8
X
X
A10
X
A9,11
BA0,1
Y
X
X
X
X
X
X
X
X
X
0
1
0
D0
DQ
ACT#0
Y
D0
WRITE#0
ACT#1
D0
D0
1
0
D1
D1
0
D1
D1
PRE#0
WRITE#1
1
2
Y
0
D0
ACT#0
D0
D0
D0
ACT#2 WRITE#0
PRE#1
Italic parameter indicates minimum case
MIT-DS-0224-0.5
MITSUBISHI
ELECTRIC
( 34 / 55 )
12.Nov.1998
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Burst Read (single bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency =2
A0-8
X
A10
X
X
A9,11
X
X
BA0,1
0
Y
X
0
0
0
Y
0
CL=3
Q0
DQ
ACT#0
READ#0
Q0
Q0
PRE#0
Q0
Q0
ACT#0
Q0
READ#0
READ to PRE ≥BL allows full data out
Italic parameter indicates minimum case
MIT-DS-0224-0.5
MITSUBISHI
ELECTRIC
( 35 / 55 )
12.Nov.1998
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Burst Read (multiple bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency =2
A0-8
X
X
A10
X
A9,11
BA0,1
Y
Y
X
X
X
X
X
X
X
X
X
0
1
0
1
CL=3
ACT#0
READ#0
ACT#1
0
1
2
Q1
Q1
Q1
0
CL=3
Q0
DQ
0
Y
Q0
Q0
Q0
PRE#0
READ#1
Q1
ACT#0
PRE#1
Q0
READ#0
ACT#2
Italic parameter indicates minimum case
MIT-DS-0224-0.5
MITSUBISHI
ELECTRIC
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12.Nov.1998
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Burst Write (multi bank) with Auto-Precharge @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
/RAS
tRCD
tRCD
tRCD
/CAS
BL-1+ tWR + tRP
BL-1+ tWR + tRP
/WE
CKE
DQM
A0-8
X
X
A10
X
X
X
X
A9,11
X
X
X
X
BA0,1
0
1
Y
0
D0
DQ
ACT#0
ACT#1
Y
X
1
D0
D0
WRITE#0 with
AutoPrecharge
D0
D1
D1
D1
Y
X
0
0
1
D1
D0
D0
ACT#0
WRITE#1 with
AutoPrecharge
Y
1
D0
WRITE#0
ACT#1
D0
D1
WRITE#1
Italic parameter indicates minimum case
MIT-DS-0224-0.5
MITSUBISHI
ELECTRIC
( 37 / 55 )
12.Nov.1998
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
/RAS
tRCD
tRCD
tRCD
/CAS
BL+tRP
BL+tRP
/WE
CKE
DQM
DQM read latency =2
A0-8
X
X
A10
X
X
X
X
A9,11
X
X
X
X
0
1
BA0,1
Y
Y
0
1
CL=3
ACT#0
ACT#1
Y
0
0
CL=3
Q0
DQ
X
READ#0 with
Auto-Precharge
Q0
Q0
X
Y
1
1
CL=3
Q0
Q1
Q1
ACT#0
READ#1 with
Auto-Precharge
Q1
Q1
Q0
Q0
READ#0
ACT#1
Italic parameter indicates minimum case
MIT-DS-0224-0.5
MITSUBISHI
ELECTRIC
( 38 / 55 )
12.Nov.1998
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Page Mode Burst Write (multi bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
X
A10
X
X
A9,11
X
X
BA0,1
0
1
Y
Y
Y
Y
0
0
1
0
D0
DQ
ACT#0
D0
WRITE#0
ACT#1
D0
D0
D0
D0
D0
D0
D1
D1
WRITE#0
D1
D1
D0
D0
D0
WRITE#0
WRITE#1
Italic parameter indicates minimum case
MIT-DS-0224-0.5
MITSUBISHI
ELECTRIC
( 39 / 55 )
12.Nov.1998
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Page Mode Burst Read (multi bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=2
A0-8
X
X
A10
X
X
A9,11
X
X
0
1
BA0,1
Y
Y
Y
Y
0
0
1
0
CL=3
CL=3
Q0
DQ
ACT#0
READ#0
ACT#1
Q0
Q0
Q0
CL=3
Q0
Q0
Q0
READ#0
Q0
Q1
Q1
Q1
Q1
READ#0
READ#1
Italic parameter indicates minimum case
MIT-DS-0224-0.5
MITSUBISHI
ELECTRIC
( 40 / 55 )
12.Nov.1998
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Write Interrupted by Write / Read @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
tCCD
/CAS
/WE
CKE
DQM
A0-8
X
X
A10
X
X
A9,11
X
X
0
1
BA0,1
Y
Y
Y
Y
Y
0
0
0
1
0
CL=3
D0
DQ
D0
D0
D0
D0
D0
D1
D1
Q0
Q0
Q0
Q0
ACT#0
WRITE#0 WRITE#0 WRITE#0
READ#0
ACT#1
WRITE#1
Burst Write can be interrupted by Write or Read of any active bank.
Italic parameter indicates minimum case
MIT-DS-0224-0.5
MITSUBISHI
ELECTRIC
( 41 / 55 )
12.Nov.1998
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Read Interrupted by Read / Write @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=2
A0-8
X
X
A10
X
X
A9,11
X
X
BA0,1
0
1
DQ
ACT#0
Y
Y
Y
Y
Y
Y
0
0
0
1
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q1
Q1
Q0
D0
D0
READ#0 READ#0 READ#0
READ#0
WRITE#0
ACT#1
READ#1
blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
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Preliminary Spec.
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Write Interrupted by Precharge @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
X
A10
X
X
X
A9,11
X
X
X
BA0,1
0
1
DQ
Y
Y
0
D0
D0
ACT#0
WRITE#0
ACT#1
D0
D0
X
1
0
D1
D1
1
1
1
D1
PRE#0
WRITE#1
PRE#1
Burst Write is not interrupted by
Precharge of the other bank.
Y
ACT#1
D1
D1
WRITE#1
Burst Write is interrupted by
Precharge of the same bank.
Italic parameter indicates minimum case
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Preliminary Spec.
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Read Interrupted by Precharge @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=2
A0-8
X
X
A10
X
X
X
A9,11
X
X
X
0
1
BA0,1
Y
Y
0
Q0
DQ
ACT#0
READ#0
ACT#1
X
1
0
1
Q0
Q0
Q0
1
Q1
PRE#0
READ#1
PRE#1
Burst Read is not interrupted
by Precharge of the other bank.
Y
1
Q1
ACT#1
READ#1
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
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Preliminary Spec.
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Mode Register Setting
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRSC
tRC
/RAS
tRCD
/CAS
/WE
CKE
DQM
M
A0-8
X
A10
X
A9,11
X
BA0,1
0
0
Y
0
D0
DQ
Auto-Ref (last of 8 cycles)
Mode
Register
Setting
ACT#0
D0
D0
D0
WRITE#0
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Auto-Refresh @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRC
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
Y
0
D0
DQ
D0
D0
Auto-Refresh
ACT#0
Before Auto-Refresh,
all banks must be idle state.
After tRC from Auto-Refresh,
all banks are idle state.
D0
WRITE#0
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Self-Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
CLK can be stopped
tRC
/CS
/RAS
/CAS
/WE
tSRX
CKE
CKE must be low to maintain Self-Refresh
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
DQ
Self-Refresh Entry
Before Self-Refresh Entry,
all banks must be idle state.
Self-Refresh Exit
ACT#0
After tRC from Self-Refresh Exit,
all banks are idle state.
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
DQM Write Mask @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
Y
Y
Y
0
0
0
masked
D0
DQ
ACT#0
D0
WRITE#0
D0
D0
masked
D0
WRITE#0
D0
D0
WRITE#0
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
DQM Read Mask @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM read latency=2
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
Y
Y
Y
0
0
0
masked
Q0
DQ
ACT#0
READ#0
Q0
Q0
Q0
READ#0
masked
Q0
Q0
Q0
READ#0
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Power Down
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
/CAS
/WE
Standby Power Down
Active Power Down
CKE
CKE latency=1
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
DQ
Precharge All
ACT#0
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
CLK Suspend @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
CKE latency=1
CKE latency=1
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
Y
Y
0
0
D0
DQ
ACT#0
D0
D0
D0
Q0
WRITE#0
READ#0
CLK suspended
Q0
Q0
Q0
CLK suspended
Italic parameter indicates minimum case
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Preliminary Spec.
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table I
Byte
Function described
SPD enrty data
SPD DATA(hex)
0
Defines # bytes written into serial memory at module mfgr
128
80
1
Total # bytes of SPD memory device
256 Bytes
08
2
Fundamental memory type
SDRAM
04
3
# Row Addresses on this assembly
A0-A11
0C
4
# Column Addresses on this assembly
A0-A8
09
5
# Module Banks on this assembly
1BANK
01
6
Data Width of this assembly...
x64
40
7
... Data Width continuation
0
00
8
Voltage interface standard of this assembly
LVTTL
01
-7,-8,-10
10ns
A0
SDRAM Access from Clock
-7,-8
6ns
60
tAC for CL=3
-10
8ns
80
DIMM Configuration type (Non-parity,Parity,ECC)
Non-PARITY
00
12
Refresh Rate/Type
self refresh(15.625uS)
80
13
SDRAM width,Primary DRAM
x8
08
14
Error Checking SDRAM data width
N/A
00
1
01
9
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=3
10
11
15
Minimum Clock Delay,Back to Back Random Column Addresses
16
Burst Lengths Supported
1/2/4/8/Full page
8F
17
# Banks on Each SDRAM device
4bank
04
18
CAS# Latency
2/3
06
19
CS# Latency
0
01
20
Write Latency
0
01
21
SDRAM Module Attributes
non-buffered,non-registered
00
22
SDRAM Device Attributes:General
Precharge All,Auto precharge
0E
23
SDRAM Cycle time(2nd highest CAS latency)
-7
10ns
A0
Cycle time for CL=2
-8
-10
13ns
15ns
D0
F0
-7
6ns
60
-8
7ns
70
-10
8ns
80
N/A
00
-7,-8
N/A
20ns
00
14
-10
30ns
1E
-7,-8,-10
20ns
14
24
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
25
26
27
SDRAM Cycle time(3rd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
Precharge to Active Minimum
28
Row Active to Row Active Min.
29
RAS to CAS Delay Min
-7,-8
20ns
14
-10
30
Active to Precharge Min
-7,-8
30ns
50ns
1E
32
-10
60ns
3C
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table II
31
32
33
34
35
36-61
Density of each bank on module
Command and Address signal input setup time
Command and Address signal input hold time
Data signal input setup time
Data signal input hold time
10
2ns
20
-10
N/A
00
-7,-8
1ns
10
-10
N/A
00
-7,-8
2ns
20
-10
N/A
00
-7,-8
1ns
10
-10
N/A
00
option
00
-7,-8
rev 1.2A
12
-10
rev 1
01
Check sum for -7
05
Check sum for -8
Check sum for -10
45
42
Superset Information (may be used in future)
62
SPD Revision
63
64-71
64MByte
-7,-8
Checksum for bytes 0-62
Manufactures Jedec ID code per JEP-108E
72
Manufacturing location
73-90
Manufactures Part Number
MITSUBISHI
1CFFFFFFFFFFFFFF
Miyoshi,Japan
01
Tajima,Japan
02
NC,USA
03
Germany
04
MH8S64BALD-7
MH8S64BALD-8
4D483853363442414C442D37202020202020
4D483853363442414C442D38202020202020
MH8S64BALD-10
4D483853363442414C442D312302020202020
91-92
Revision Code
PCB revision
rrrr
93-94
Manufacturing date
year/week code
yyww
95-98
Assembly Serial Number
serial number
ssssssss
99-125
Manufacture Specific Data
option
00
100MHz
66MHz
64
66
126
Intetl specification frequency
-7,-8
-10
127
Intel specification CAS# Latency support
AF
AD
06
-7
-8
-10
128+
MIT-DS-0224-0.5
Unused storage locations
open
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
2-ø3±0.1
8.89±0.13
1
2±0.13
17.78±0.13
3±0.13
3±0.13
1±0.13
85
6.35±0.13
24.495±0.13
9x1.27=11.43±0.2
29x1.27=36.83±0.2
42.18±0.13
133.35±0.13
127.35±0.13
6.35±0.1
43x1.27=54.61±0.2
1.27±0.1
168
84
2-R2±0.13
17.78±0.13
1±0.13
1.27±0.1
3.9MAX
OUTLINE
34.925
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Preliminary Spec.
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MITSUBISHI LSIs
MH8S64BALD -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making
semiconductor products better and more reliable,but there is always the
possibility that trouble may occur with them. Trouble with semiconductors
consideration to safety when making your circuit designs,with appropriate
measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of
non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the
customer's application;they do not convey any license under any
intellectual property rights,or any other rights,belonging to Mitsubishi
Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage,
or infringement of any third-party's rights,originating in the use of any
product data,diagrams,charts or circuit application examples contained in
these materials.
3.All information contained in these materials,including product data,
diagrams and charts,represent information on products at the time of
publication of these materials,and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other
reasons. It is therefore recommended that customers contact Mitsubishi
Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product
listed herein.
4.Mitsubishi Electric Corporation semiconductors are not designed or
manufactured for use in a device or system that is used under
circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor when considering the use of a product contained herein
for special applications,such as apparatus or systems for transportation,
vehicular,medical,aerospace,nuclear,or undersea repeater use.
5.The prior written approval of Mitsubishi Electric Corporation is necessary to
reprint or reproduce in whole or in part these materials.
6.If these products or technologies are subject the Japanese export
control restrictions,they must be exported under a license from the
Japanese government and cannot be imported into a country other than
the approved destination.
Any diversion or reexport contrary to the export control laws and
regulations of Japan and/or the country of destination is prohibited.
7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
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