ETC2 M453LC3AE 32-bit microcontroller Datasheet

M451
ARM Cortex® -M4
32-bit Microcontroller
NuMicro® Family
M451 Series
Datasheet
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Mar. 04, 2016
Page 1 of 219
Rev.2.05
M451 SERIES DATASHEET
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
M451
TABLE OF CONTENTS
1
GENERAL DESCRIPTION ------------------------------------------------ 10
2
FEATURES -------------------------------------------------------------- 12
NuMicro® M451 Features .................................................................. 12
2.1
3
Abbreviations ------------------------------------------------------------- 18
4
PARTS INFORMATION LIST AND PIN CONFIGURATION ---------------- 20
NuMicro® M451 Selection Guide ......................................................... 20
4.1
4.1.1
NuMicro M451 Naming Rule ..................................................................... 20
4.1.2
NuMicro M451 Base Series Selection Guide ................................................. 21
4.1.3
NuMicro M451M Series (M051 Pin Compatible) Selection Guide ......................... 22
4.1.4
NuMicro M452 USB Series Selection Guide .................................................. 23
4.1.5
NuMicro M453 CAN Series (CAN+USB) Selection Guide .................................. 24
®
®
®
®
Pin Configuration............................................................................ 25
4.2
M451 SERIES DATASHEET
4.2.1
NuMicro M451 Base Series LQFP48 Pin Diagram .......................................... 25
4.2.2
NuMicro M451 Base Series LQFP64 Pin Diagram .......................................... 26
4.2.3
NuMicro M451 Base Series LQFP100 Pin Diagram ......................................... 27
4.2.4
NuMicro M451M Series (M051 Pin Compatible) LQFP48 Pin Diagram .................. 28
4.2.5
NuMicro M451M Series (M058S Pin Compatible) LQFP64 Pin Diagram ................ 29
4.2.6
NuMicro M452 USB Series LQFP48 Pin Diagram ........................................... 30
4.2.7
NuMicro M452 USB Series LQFP64 Pin Diagram ........................................... 32
4.2.8
NuMicro M453 CAN Series (CAN+USB) LQFP48 Pin Diagram ........................... 34
4.2.9
NuMicro M453 CAN Series (CAN+USB) LQFP64 Pin Diagram ........................... 36
4.2.10
NuMicro M453 CAN Series (CAN+USB) LQFP100 Pin Diagram .......................... 38
®
®
®
®
®
®
®
®
®
®
Pin Description .............................................................................. 40
4.3
5
®
4.3.1
M451 Base Series LQFP48 Pin Description .................................................... 40
4.3.2
M451 Base Series LQFP64 Pin Description .................................................... 48
4.3.3
M451 Base Series LQFP100 Pin Description .................................................. 58
4.3.4
M451M Series (M051 Pin Compatible) LQFP48 Pin Description ........................... 71
4.3.5
M452 USB Series LQFP48 Pin Description .................................................... 79
4.3.6
M452 USB Series LQFP64 Pin Description .................................................... 86
4.3.7
M453 CAN Series(CAN+USB) LQFP48 Pin Description ..................................... 95
4.3.8
M453 CAN Series(CAN+USB) LQFP64 Pin Description ................................... 103
4.3.9
M453 CAN Series(CAN+USB) LQFP100 Pin Description ................................. 112
4.3.10
GPIO Multi-function Pin Summary ............................................................. 125
BLOCK DIAGRAM ------------------------------------------------------- 135
Mar. 04, 2016
Page 2 of 219
Rev.2.05
M451
NuMicro® M451 Block Diagram .......................................................... 135
5.1
FUNCTIONAL DESCRIPTION ------------------------------------------- 137
6
6.1
ARM® Cortex® -M4 Core................................................................... 137
6.2
System Manager ........................................................................... 140
6.2.1
Overview ........................................................................................... 140
6.2.2
System Reset...................................................................................... 140
6.2.3
Power Modes and Wake-up Sources .......................................................... 147
6.2.4
System Power Distribution ...................................................................... 149
6.2.5
System Memory Map ............................................................................. 151
6.2.6
SRAM Memory Organization ................................................................... 154
6.2.7
System Timer (SysTick) ......................................................................... 157
6.2.8
Nested Vectored Interrupt Controller (NVIC) ................................................. 157
6.3
Clock Controller ............................................................................ 158
6.3.1
Overview ........................................................................................... 158
6.3.2
Clock Generator ................................................................................... 160
6.3.3
System Clock and SysTick Clock .............................................................. 161
6.3.4
Peripherals Clock ................................................................................. 162
6.3.5
Power-down Mode Clock ........................................................................ 163
6.3.6
Clock Output ....................................................................................... 163
6.4
Flash Memeory Controller (FMC) ....................................................... 165
Overview ........................................................................................... 165
6.4.2
Features ............................................................................................ 165
6.5
External Bus Interface (EBI) ............................................................. 166
6.5.1
Overview ........................................................................................... 166
6.5.2
Features ............................................................................................ 166
6.6
General Purpose I/O (GPIO) ............................................................. 167
6.6.1
Overview ........................................................................................... 167
6.6.2
Features ............................................................................................ 167
6.7
PDMA Controller (PDMA) ................................................................ 168
6.7.1
Overview ........................................................................................... 168
6.7.2
Features ............................................................................................ 168
6.8
Timer Controller (TMR) ................................................................... 169
6.8.1
Overview ........................................................................................... 169
6.8.2
Features ............................................................................................ 169
6.9
PWM Generator and Capture Timer (PWM) .......................................... 170
Mar. 04, 2016
Page 3 of 219
Rev.2.05
M451 SERIES DATASHEET
6.4.1
M451
6.9.1
Overview ........................................................................................... 170
6.9.2
Features ............................................................................................ 170
6.10
Watchdog Timer (WDT)................................................................... 172
6.10.1
Overview ........................................................................................ 172
6.10.2
Features ......................................................................................... 172
6.11
Window Watchdog Timer (WWDT) ..................................................... 173
6.11.1
Overview ........................................................................................ 173
6.11.2
Features ......................................................................................... 173
6.12
Real Time Clock (RTC) ................................................................... 174
6.12.1
Overview ........................................................................................ 174
6.12.2
Features ......................................................................................... 174
6.13
UART Interface Controller (UART) ...................................................... 175
6.13.1
Overview ........................................................................................ 175
6.13.2
Features ......................................................................................... 175
6.14
Smart Card Host Interface (SC) ......................................................... 177
Overview ........................................................................................ 177
6.14.1
Features ......................................................................................... 177
6.14.2
6.15
I C Serial Interface Controller (I2C) ..................................................... 178
2
6.15.1
Overview ........................................................................................ 178
6.15.2
Features ......................................................................................... 178
M451 SERIES DATASHEET
6.16
Serial Peripheral Interface (SPI) ......................................................... 179
6.16.1
Overview ........................................................................................ 179
6.16.2
Features ......................................................................................... 179
6.17
USB Device Controller (USBD) .......................................................... 180
6.17.1
Overview ........................................................................................ 180
6.17.2
Features ......................................................................................... 180
6.18
USB 1.1 Host Controller (USBH) ........................................................ 181
6.18.1
Overview ........................................................................................ 181
6.18.2
Features ......................................................................................... 181
6.19
USB On-The-Go (OTG) ................................................................... 182
6.19.1
Overview ........................................................................................ 182
6.19.2
Features ......................................................................................... 182
6.20
Controller Area Network (CAN) .......................................................... 183
6.20.1
Overview ........................................................................................ 183
6.20.2
Features ......................................................................................... 183
Mar. 04, 2016
Page 4 of 219
Rev.2.05
M451
6.21
CRC Controller (CRC) .................................................................... 184
6.21.1
Overview ........................................................................................ 184
6.21.2
Features ......................................................................................... 184
6.22
Enhanced 12-bit Analog-to-Digital Converter (EADC) ............................... 185
6.22.1
Overview ........................................................................................ 185
6.22.2
Features ......................................................................................... 185
6.23
Digital to Analog Converter (DAC) ...................................................... 186
6.23.1
Overview ........................................................................................ 186
6.23.2
Features ......................................................................................... 186
6.24
Analog Comparator Controller (ACMP) ................................................ 187
6.24.1
Overview ........................................................................................ 187
6.24.2
Features ......................................................................................... 187
7
APPLICATION CIRCUIT ------------------------------------------------- 188
8
ELECTRICAL CHARACTERISTICS -------------------------------------- 189
8.1
Absolute Maximum Ratings .............................................................. 189
8.2
DC Electrical Characteristics ............................................................. 190
8.3
AC Electrical Characteristics ............................................................. 196
External 4~24 MHz High Speed Crystal (HXT) Input Clock ................................ 196
8.3.2
External 4~20 MHz High Speed Crystal (HXT) Oscillator .................................. 196
8.3.3
22.1184 MHz Internal High Speed RC Oscillator (HIRC) .................................. 197
8.3.4
32.768 kHz External Low Speed Crystal (LXT) Input Clock ............................... 198
8.3.5
32.768 kHz External Low Speed Crystal (LXT) Oscillator .................................. 198
8.3.6
10 kHz Internal Low Speed RC Oscillator (LIRC) ........................................... 199
8.4
Analog Characteristics .................................................................... 200
8.4.1
12-bit SAR ADC ................................................................................... 200
8.4.2
LDO ................................................................................................. 202
8.4.3
Low Voltage Reset ............................................................................... 202
8.4.4
Brown-out Detector ............................................................................... 202
8.4.5
Power-on Reset ................................................................................... 203
8.4.6
Temperature Sensor ............................................................................. 203
8.4.7
Comparator ........................................................................................ 204
8.4.8
12-bit DAC ......................................................................................... 204
8.4.9
Internal Voltage Reference ...................................................................... 205
8.4.10
USB PHY ........................................................................................... 205
8.5
Flash DC Electrical Characteristics ..................................................... 207
Mar. 04, 2016
Page 5 of 219
Rev.2.05
M451 SERIES DATASHEET
8.3.1
M451
8.6
I2C Dynamic Characteristics ............................................................. 208
8.7
SPI Dynamic Characteristics ............................................................. 209
8.7.1
8.8
Dynamic Characteristics of Data Input and Output Pin ..................................... 209
I2S Dynamic Characteristics.............................................................. 212
PACKAGE DIMENSIONS ------------------------------------------------ 214
9
9.1
LQFP 100L (14x14x1.4 mm footprint 2.0 mm) ........................................ 214
9.2
LQFP 64L (10x10x1.4 mm footprint 2.0 mm) ......................................... 215
9.3
LQFP 64L (7x7x1.4 mm footprint 2.0 mm)............................................. 216
9.4
LQFP 48L (7x7x1.4mm2 Footprint 2.0mm) ............................................ 217
10
REVISION HISTORY ---------------------------------------------------- 218
M451 SERIES DATASHEET
Mar. 04, 2016
Page 6 of 219
Rev.2.05
M451
List of Figures
®
Figure 4.1-1 NuMicro M451 Selection Code ................................................................................ 20
®
Figure 4.2-1 NuMicro M451 Base Series LQFP 48-pin Diagram ................................................. 25
®
Figure 4.2-2 NuMicro M451 Base Series LQFP 64-pin Diagram ................................................. 26
®
Figure 4.2-3 NuMicro M451 Base Series LQFP 100-pin Diagram ............................................... 27
®
Figure 4.2-4 NuMicro M451M Base Series (Pin Compatible with M051) LQFP 48-pin Diagram 28
®
Figure 4.2-5 NuMicro M451M Base Series (Pin Compatible with M058S) LQFP 64-pin Diagram
................................................................................................................................................ 29
®
Figure 4.2-6 NuMicro M451 USB Series LQFP 48-pin Diagram (M452LG/M452LE Device Only)
................................................................................................................................................ 30
®
Figure 4.2-7 NuMicro M451 USB Series LQFP 48-pin Diagram (M452LD/M452LC Device Only)
................................................................................................................................................ 31
®
Figure 4.2-8 NuMicro M451 USB Series LQFP 64-pin Diagram (M452RG/M452RE Device Only)
................................................................................................................................................ 32
®
Figure 4.2-9 NuMicro M451 USB Series LQFP 64-pin Diagram (M452RD Device Only) ........... 33
®
Figure 4.2-10 NuMicro M451 CAN Series (CAN+USB) LQFP 48-pin Diagram (M453LG/M453LE
Device Only)............................................................................................................................ 34
®
Figure 4.2-11 NuMicro M451 CAN Series (CAN+USB) LQFP 48-pin Diagram (M453LD/M453LC
Device Only)............................................................................................................................ 35
®
Figure 4.2-12 NuMicro M451 CAN Series (CAN+USB) LQFP 64-pin Diagram (M453RG/M453RE
Device Only)............................................................................................................................ 36
®
Figure 4.2-13 NuMicro M451 CAN Series (CAN+USB) LQFP 64-pin Diagram (M453RD Device
Only) ........................................................................................................................................ 37
®
Figure 4.2-14 NuMicro M451 CAN Series (CAN+USB) LQFP 100-pin Diagram
(M453VG/M453VE Device Only) ............................................................................................ 38
®
Figure 5.1-1 NuMicro M45xG/M45xE Block Diagram ................................................................ 135
®
Figure 5.1-2 NuMicro M45xD/M45xC Block Diagram ................................................................ 136
®
Figure 6.1-1 Cortex -M4 Block Diagram ...................................................................................... 137
Figure 6.2-1 System Reset Sources ............................................................................................ 141
Figure 6.2-2 nRESET Reset Waveform ....................................................................................... 144
Figure 6.2-3 Power-on Reset (POR) Waveform .......................................................................... 144
Figure 6.2-4 Low Voltage Reset (LVR) Waveform ....................................................................... 145
Figure 6.2-5 Brown-out Detector (BOD) Waveform ..................................................................... 146
Figure 6.2-6 Power Mode State Machine .................................................................................... 147
Figure 6.2-7 NuMicro® M451 Power Distribution Diagram .......................................................... 150
Figure 6.2-8 SRAM Block Diagram .............................................................................................. 154
Figure 6.2-9 SRAM Memory Organization (M45xG/M45xE) ....................................................... 155
Figure 6.2-10 SRAM Memory Organization (M45xD/M45xC) ..................................................... 156
Figure 6.3-1 Clock Generator Global View Diagram .................................................................... 159
Mar. 04, 2016
Page 7 of 219
Rev.2.05
M451 SERIES DATASHEET
®
Figure 4.2-15 NuMicro M451 CAN Series (CAN+USB) LQFP 100-pin Diagram (M453VD Device
Only) ........................................................................................................................................ 39
M451
Figure 6.3-2 Clock Generator Block Diagram .............................................................................. 160
Figure 6.3-3 System Clock Block Diagram .................................................................................. 161
Figure 6.3-4 HXT Stop Protect Procedure ................................................................................... 162
Figure 6.3-5 SysTick Clock Control Block Diagram ..................................................................... 162
Figure 6.3-6 Clock Source of Clock Output ................................................................................. 163
Figure 6.3-7 Clock Output Block Diagram ................................................................................... 164
Figure 8.3-1 Typical Crystal Application Circuit ........................................................................... 197
Figure 8.3-2 HIRC Accuracy vs. Temperature ............................................................................. 197
Figure 8.3-3 Typical Crystal Application Circuit ........................................................................... 199
Figure 8.4-1 Typical connection diagram using the ADC ............................................................ 201
Figure 8.4-2 Power-up Ramp Condition ...................................................................................... 203
2
Figure 8.6-1 I C Timing Diagram ................................................................................................. 208
Figure 8.7-1 SPI Master Mode Timing Diagram .......................................................................... 209
Figure 8.7-2 SPI Slave Mode Timing Diagram ............................................................................ 211
2
Figure 8.8-1 I S Master Mode Timing Diagram............................................................................ 213
2
Figure 8.8-2 I S Slave Mode Timing Diagram.............................................................................. 213
M451 SERIES DATASHEET
Mar. 04, 2016
Page 8 of 219
Rev.2.05
M451
List of Tables
Table 1-1 Key Features Support Table .......................................................................................... 10
Table 3-1 List of Abbreviations ....................................................................................................... 19
Table 4-1 M451 GPIO Multi-function Table ................................................................................. 134
Table 6-1 Reset Value of Registers ............................................................................................. 143
Table 6-2 Power Mode Difference Table ..................................................................................... 147
Table 6-3 Clocks in Power Modes ............................................................................................... 148
Table 6-4 Condition of Entering Power-down Mode Again .......................................................... 149
Table 6-5 Address Space Assignments for On-Chip Controllers ................................................. 153
®
Table 6-6 NuMicro M451 Series UART Feature ........................................................................ 176
M451 SERIES DATASHEET
Mar. 04, 2016
Page 9 of 219
Rev.2.05
M451
1
GENERAL DESCRIPTION
®
®
The M451 series includes a total of 33 ARM Cortex -M4F based products, including the M451
Base Series, M452 USB Series, M453 CAN Series, and M451M Series which is pin compatible
with M051 LQFP48 and M058S LQFP64. By planning a complete product line, Nuvoton hopes to
®
®
fulfill the demand for the ARM Cortex -M4F core with products at all levels and realize its
customer commitment: total support for long-term competitiveness enhancement, and to fulfill
their current product development demand and future innovation imagination.
®
®
The M451 series embedded with the ARM Cortex -M4F core supports DSC (digital signal
controller) and FPU (float point unit) and features high performance computing capability running
up to 72 MHz, built-in 256/128/72/40 KB Flash ROM, 32/16 KB SRAM complying with IEC60730,
built-in boot ROM and independent 4 KB in-system programming Flash ROM for developing more
2
flexible online upgrade code that support external UART, SPI, I C, CAN and USB. It also supports
EBI to provide greater flexibility for external memory. The entire M451 series is provided with
outstanding specifications: four 32-bit timers, dual watchdogs, and integrates plenty of peripherals
such as PDMA and RTCs, five UARTs that support 16-byte FIFO, three sets of SPI controllers
2
that support quad mode, two I²C devices that support SMBus and PMBus, two sets of I S, two
LINs, CAN bus, ISO-7816-3 interface, full-speed USB OTG, full-speed USB devices, 16-channel
12-bit ADC with 1 MSPS conversion rate, built-in reference voltage (VREF) for circuit generation,
12-bit DAC, two analog comparators and temperature detectors.
The M451 series provides two special designs. One is high-resolution 144 MHz PWM with highspeed electromechanical control timer and resolution<7ns. In conjunction with a driver ADC, it
delivers hardware brake protection and pulse capture functions to save MCU computing burden
and effectively carry out advanced computing required by motor control, making it exceptionally
outstanding in industrial automation and motor control performance. The other is VAI (Voltage
Adjustment Interface) system to support voltage level adjustment with individual I/O (1.8V-5.5V)
for saving additional cost on adjusting the interface voltage difference of peripheral components.
M451 SERIES DATASHEET
The M451 series also provides the wide operating voltage (2.5V-5.5V) and 5V-tolerance input I/O
to significantly enhance system stability, industrial operating temperature (-40°C - 105°C),
22.1184 MHz internal RC oscillator (HIRC variation < ±2%) and 32.768 kHz external crystal
oscillator to trim HIRC (HIRC variation < ±0.25%) working at -40˚C- 105˚C to boost system
immunity and adequately fulfill the high precision demand of communications. The M451 series is
specifically suitable for high-performance and high-precision applications, such as industrial
control, system automation, security surveillance, autotronics and digital power control.
Product Line
USB
CAN
UART
I2C
I2S
SPI
PWM
ADC
DAC
RTC
M453
●
●
●
●
●
●
●
●
●
●
M452
●
--
●
●
●
●
●
●
●
●
M451
--
--
●
●
●
●
●
●
●
●
--
--
●
●
●
●
●
●
●
--
M451M
(M051 Pin Compatible)
Table 1-1 Key Features Support Table
®
The NuMicro M451 series is suitable for a wide range of applications such as:

Industrial Automation

PLCs

Inverters

Home Automation
Mar. 04, 2016
Page 10 of 219
Rev.2.05
M451

Security Alarm System

Power Metering

Portable Data Collector

Portable RFID Reader

System Supervisors

Smart Card Reader

Printer

Bar Code Scanner

Motor Control

Digital Power
M451 SERIES DATASHEET
Mar. 04, 2016
Page 11 of 219
Rev.2.05
M451
2
FEATURES
2.1 NuMicro® M451 Features
 Core
®
–
–
–
–
–
–
–
–
®
ARM Cortex -M4F core running up to 72 MHz
Supports DSP extension with hardware divider
Supports IEEE 754 compliant Floating-point Unit (FPU)
Supports Memory Protection Unit (MPU)
One 24-bit system timer
Supports Low Power Sleep mode by WFI and WFE instructions
Single-cycle 32-bit hardware multiplier
Supports programmable 16 level priorities of Nested Vectored Interrupt Controller
(NVIC)
– Supports programmable mask-able interrupts
 Built-in LDO for wide operating voltage ranged from 2.5V to 5.5V
 Flash Memory
–
–
–
–
Supports 40/72/128/256 KB application ROM (APROM)
Supports 4 KB Flash for loader (LDROM)
Supports Data Flash with configurable memory size
Supports In-System-Programming (ISP), In-Application-Programming (IAP) update
embedded flash memory
– Supports 2 KB page erase for all embedded flash
 Boot Loader
–
–
16 KB embedded ROM
2
*1
Supports Nuvoton native In-System-Programming (ISP) for UART0, SPI0, I C0, CAN
*2
and USB
–
Supports direct boot from Boot Loader by pin selection
 SRAM Memory
M451 SERIES DATASHEET
– 32/16 KB embedded SRAM
– 16/8 KB with hardware parity check
– Supports byte-, half-word- and word-access
– Supports exception (NMI) generated once a parity check error occurs
– Supports PDMA mode
 PDMA (Peripheral DMA)
–
Supports 12/8 independent configurable channels for automatic data transfer between
memories and peripherals
– Supports Normal and Scatter-Gather Transfer modes
– Supports two types of priorities modes: Fixed-priority and Round-robin modes
– Supports byte-, half-word- and word-access
– Auto increment of the source and destination address
– Supports single and burst transfer type
 Clock Control
–
–
–
–
–
Built-in 22.1184 MHz internal high speed RC oscillator (HIRC) for system operation
(variation < 2% at -40˚C ~ +105˚C)
Built-in 10 kHz internal low speed RC oscillator (LIRC) for Watchdog Timer and wakeup operation
Built-in 4~20 MHz external high speed crystal oscillator (HXT) for precise timing
operation
Built-in 32.768 kHz external low speed crystal oscillator (LXT) for RTC function and
low-power system operation
Supports one PLL up to 144 MHz for high performance system operation, sourced
Mar. 04, 2016
Page 12 of 219
Rev.2.05
M451
from HIRC and HXT
– Supports clock failure detection for high/low speed external crystal oscillator
– Supports exception (NMI) generated once a clock failure detected
–
Supports clock output
 GPIO
–
–
–
–
–
–
–
 Timer
Four I/O modes
TTL/Schmitt trigger input selectable
I/O pin configured as interrupt source with edge/level trigger setting
Supports high driver and high sink current I/O (up to 20 mA at 5V)
Supports software selectable slew rate control
Supports 5V-tolerance function
Supports up to 85/55/42 GPIOs for LQFP100/64/48 respectively
– Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter
– Independent clock source for each timer
– Provides One-shot, Periodic, Toggle and Continuous Counting operation modes
– Supports event counting function to count the event from external pin
– Supports input capture function to capture or reset counter value
 Watchdog Timer
– Supports multiple clock sources from LIRC (default selection), HCLK/2048 and LXT
– 8 selectable time-out period from 1.6ms ~ 26.0sec (depending on clock source)
– Able to wake up from Power-down or Idle mode
– Interrupt or reset selectable on watchdog time-out
 Window Watchdog Timer
–
–
–
–
 RTC
–
–
–
–
–
 PWM
–
–
–
–
–
–
–
–
–
Supports external power pin V BAT
Supports software compensation by setting frequency compensate register (FCR)
Supports RTC counter (second, minute, hour) and calendar counter (day, month, year)
Supports Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8,
1/4, 1/2 and 1 second
Supports wake-up function
Supports 80 bytes spare registers
Programmable spare register erase function
Supports 32KHz Oscillator gain control
Supports tamper detection function
Supports up to 12 independent PWM outputs with 16-bit resolution
Supports maximum clock frequency up to 144MHz
Supports 12-bit clock prescale
Supports one-shot or auto-reload counter operation mode
Supports up, down or up-down PWM counter type
Supports synchronous function
Supports dead time with maximum divided 12-bit prescale
Supports brake function source from pin, comparator output and system safety events
Supports PWM auto recovery function after brake condition removed
Mar. 04, 2016
Page 13 of 219
Rev.2.05
M451 SERIES DATASHEET
–
–
–
–
–
–
–
Supports multiple clock sources from HCLK/2048 (default selection) and LIRC
Window set by 6-bit counter with 11-bit prescale
Able to wake up from Power-down or Idle mode
Interrupt or reset selectable on time-out
M451
–
–
–
–
–
–
–
 UART
Supports mask function and tri-state output for each PWM pin
Supports PWM events interrupt
Supports trigger EADC/DAC start conversion
Supports up to 12 independent input capture channels with rising/falling capture and
with counter reload option
Supports capture counter with 16-bit resolution
Supports capture interrupt
Supports capture PDMA mode
– Supports up to four UARTs – UART0, UART1, UART2 and UART3
– Supports 16-byte FIFOs with programmable level trigger
– Supports auto flow control ( CTS and RTS)
– Supports IrDA (SIR) function
– Supports RS-485 9-bit mode and direction control
– UART0 and UART1 support LIN function
– Programmable baud-rate generator up to 1/16 system clock
–
Supports wake-up function
– Supports PDMA mode
 Smart Card Interface
–
–
–
–
–
–
–
M451 SERIES DATASHEET
–
–
–
–
–
–
–
 SPI
One set of ISO-7816-3 port
Compliant to ISO-7816-3 T=0, T=1
Separate receive / transmit 4 bytes entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 266 ETU)
A 24-bit and two 8 bit time-out counters for Answer to Request (ATR) and waiting times
processing
Supports auto inverse convention function
Supports stop clock level and clock stop (clock keep) function
Supports transmitter and receiver error retry and error limit function
Supports hardware activation/deactivation sequence process
Supports hardware warm reset sequence process
Supports hardware auto deactivation sequence when detect the card is removal
Supports UART function
–
Supports one set of SPI Quad controller – SPI0
–
Supports Master or Slave mode operation
–
Supports 2-bit Transfer mode
–
Supports Dual and Quad I/O Transfer mode
–
Configurable bit length of a transfer word from 8 to 32-bit
–
Provides separate 8-level depth transmit and receive FIFO buffers
–
Supports MSB first or LSB first transfer sequence
–
Supports the byte reorder function
–
Supports Byte or Word Suspend mode
–
Supports PDMA mode
–
Supports 3-wired, no slave select signal, bi-direction interface
–
Master up to 32 MHz, and Slave up to 16 MHz (when chip works at VDD = 5V)
2
 SPI/ I S
–
–
–
–
–
Supports up to two sets of SPI controllers – SPI1 and SPI2
Supports Master or Slave mode operation
Configurable bit length of a transfer word from 8 to 32-bit
Provides separate 4-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Mar. 04, 2016
Page 14 of 219
Rev.2.05
M451
–
–
–
–
–
–
–
–
–
–
–
–
–
2
I C
Supports the byte reorder function
Supports Byte or Word Suspend mode
Supports 3-wire, no slave select signal, bi-direction interface
Master mode up to 36 MHz and Slave mode up to 18 MHz (when chip works at VDD =
5V)
2
Supports up to two sets of I S by SPI controllers – SPI1 and SPI2
Interface with external audio CODEC
Supports Master and Slave mode
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Supports mono and stereo audio data
2
Supports PCM mode A, PCM mode B, I S and MSB justified data format
Each provides two 4-word FIFO data buffers, one for transmitting and the other for
receiving
Generates interrupt requests when buffer levels cross a programmable boundary
Each supports two PDMA requests, one for transmitting and the other for receiving
2
–
–
–
–
–
Supports up to two sets of I C devices
Supports Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
– Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
– Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
– Programmable clocks allow versatile rate control
– Supports multiple address recognition (four slave address with mask option)
– Supports SMBus and PMBus
– Supports speed up to 1Mbps
– Supports multi-address Power-down wake-up function
 CAN 2.0
–
–
–
–
–
–
–
–
–
–
–
 EBI
Supports one set of USB 2.0 FS OTG (M45xG/M45xE Only)
FS Host compatible with Open HCI 1.0 specification (M45xG/M45xE Only)
Compliant to USB specification version 2.0
OTG compliant with USB OTG Supplement 1.3 (M45xG/M45xE Only)
On-chip USB Transceiver
Supports Control, Bulk In/Out, Interrupt and Isochronous transfers
Auto suspend function when no bus signaling for 3 ms
Provides 8 programmable endpoints
Supports 512 Bytes internal SRAM as USB buffer
Provides remote wake-up capability
On-chip 5V to 3.3V LDO for USB PHY
Mar. 04, 2016
Page 15 of 219
Rev.2.05
M451 SERIES DATASHEET
– Supports up to one set of CAN controller
– Supports CAN protocol version 2.0 part A and B
– Bit rates up to 1M bit/s
– Each supports 32 Message Objects
– Each Message Object has its own identifier mask
– Programmable FIFO mode (concatenation of Message Object)
– Supports interrupts
– Disabled Automatic Re-transmission mode for Time Triggered CAN applications
– Supports power-down wake-up function
 USB 2.0 FS Controller
M451
–
–
–
–
–
–
–
 EADC
–
–
–
–
–
–
–
–
–
–
–
–
 DAC
Supports two dedicated external chip select pins for each memory block
Supports accessible space up to 1 Mbytes for each bank, actually external
addressable space is dependent on package pin out
Supports 8-/16-bit data width
Supports byte write in 16-bit data width mode
Supports PDMA mode
Supports Address/Data multiplexed Mode
Supports Timing parameters individual adjustment for each memory block
Analog input voltage range: 0~ VREF (Max to AVDD)
Supports single 12-bit SAR ADC conversion
12-bit resolution and 10-bit accuracy is guaranteed
Up to 1MSPS conversion rate at 5.0V
Up to 16 external single-ended analog input channels
Up to 8 differential analog input pairs
Supports single ADC interrupt
Supports external VREF pin
Support internal reference voltages from Band-gap and Voltage divider
An A/D conversion can be triggered by Software enable, External pin, Timer 0~3
overflow pulse trigger and PWM trigger
Supports 3 internal channels for VBAT, band-gap VBG input and Temperature sensor
input
Supports PDMA transfer
– Supports a 12-bit voltage type DAC
– Rail to rail settle time 8us
– External reference voltage VREF
– Max. output voltage AVDD -0.2V at buffer mode
– Conversion started by software enable or PDMA trigger
– Supports PDMA mode
 Analog Comparator
M451 SERIES DATASHEET
–
–
–
–
–
Up to two rail-to-rail analog comparators
Supports a multiplexed I/O pin at positive node.
Supports I/O pins, band-gap, Voltage divider and DAC output at negative node
Supports programmable speed and power consumption
Interrupts generated when compare results change (Interrupt event condition is
programmable)
–
Supports Power-down Wake-up
–
Supports triggers for break events and cycle-by-cycle control for PWM
 Cyclic Redundancy Calculation Unit
– Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
– Programmable initial value
– Supports programmable order reverse setting for input data and CRC checksum
– Supports programmable 1’s complement setting for input data and CRC checksum.
– Supports 8-/16-/32-bit of data width
– Interrupt generated once checksum error occurs
 Voltage Adjustable Interface
–
Supports user Configurable 1.8~5.5V I/O Interface with a dedicated power input (VDDIO)
2
2
–
Supports UART1, SPI0, SPI1, I C1 or I C0 interface
 Supports 96-bit Unique ID (UID)
 Supports 128-bit Unique Customer ID (UCID)
Mar. 04, 2016
Page 16 of 219
Rev.2.05
M451
 One built-in temperature sensor with 1℃ resolution
 Brown-out detector
– With 4 levels: 4.4 V/ 3.7 V/ 2.7 V/ 2.2 V
– Supports Brown-out Interrupt and Reset option
 Low Voltage Reset
– Threshold voltage levels: 2.0 V
 Operating Temperature: -40℃~105℃
 Packages
–
–
–
–
–
All Green package (RoHS)
LQFP 100-pin (14mm x 14mm)
LQFP 64-pin (10mm x 10mm)
LQFP 64-pin (7mm x 7mm)
LQFP 48-pin (7mm x 7mm)
Note:
*1: For optional part numbers which support CAN
*2: For optional part numbers which support USB
M451 SERIES DATASHEET
Mar. 04, 2016
Page 17 of 219
Rev.2.05
M451
3
ABBREVIATIONS
M451 SERIES DATASHEET
Acronym
Description
ACMP
Analog Comparator Controller
ADC
Analog-to-Digital Converter
AES
Advanced Encryption Standard
APB
Advanced Peripheral Bus
AHB
Advanced High-Performance Bus
BOD
Brown-out Detection
CAN
Controller Area Network
DAP
Debug Access Port
DES
Data Encryption Standard
EBI
External Bus Interface
EPWM
Enhanced Pulse Width Modulation
FIFO
First In, First Out
FMC
Flash Memory Controller
FPU
Floating-point Unit
GPIO
General-Purpose Input/Output
HCLK
The Clock of Advanced High-Performance Bus
HIRC
22.1184 MHz Internal High Speed RC Oscillator
HXT
4~20 MHz External High Speed Crystal Oscillator
IAP
In Application Programming
ICP
In Circuit Programming
ISP
In System Programming
LDO
Low Dropout Regulator
LIN
Local Interconnect Network
LIRC
10 kHz internal low speed RC oscillator (LIRC)
MPU
Memory Protection Unit
NVIC
Nested Vectored Interrupt Controller
PCLK
The Clock of Advanced Peripheral Bus
PDMA
Peripheral Direct Memory Access
PLL
Phase-Locked Loop
PWM
Pulse Width Modulation
QEI
Quadrature Encoder Interface
SD
Secure Digital
SPI
Serial Peripheral Interface
Mar. 04, 2016
Page 18 of 219
Rev.2.05
M451
SPS
Samples per Second
TDES
Triple Data Encryption Standard
TMR
Timer Controller
UART
Universal Asynchronous Receiver/Transmitter
UCID
Unique Customer ID
USB
Universal Serial Bus
WDT
Watchdog Timer
WWDT
Window Watchdog Timer
Table 3-1 List of Abbreviations
M451 SERIES DATASHEET
Mar. 04, 2016
Page 19 of 219
Rev.2.05
M451
4
PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 NuMicro® M451 Selection Guide
4.1.1 NuMicro® M451 Naming Rule
ARM–Based
32-bit Microcontroller
M45 X-X X X X X
CPU Core
Corte® -M4
Temperature
E: -40oC ~ +105oC
Function
1 : Base Series
1M : Series (M051 Pin Compatible)
2 : USB Series
3 : CAN (CAN + USB) Series
Reserved
SRAM Size
3: 16KB
6: 32KB
Package Type
Flash ROM
L: LQFP 48 7x7mm
S: LQFP 64 7x7mm
R: LQFP 64 10x10mm
V: LQFP 100 14x14mm
M451 SERIES DATASHEET
C: 40KB
D: 72KB
E: 128KB
G: 256KB
®
Figure 4.1-1 NuMicro M451 Selection Code
In this document, M45xG means the part numbers which include 256 KB Flash, M45xE means the
part numbers which include 128 KB Flash, M45xD means the part numbers which include 72 KB
Flash, M45xC means the part numbers which include 40 KB Flash.
Mar. 04, 2016
Page 20 of 219
Rev.2.05
M451
SRAM (KB)
ISP Loader ROM
(KB)
I/O
Timer
UART*
SC*
(ISO-7816 )
SPI
I2C
CAN
LIN
I2S
USB
PWM
Analog Comp.
DAC (12-Bit)
ADC (12-Bit)
RTC
ICP/ISPI/AP
Package
M451LG6AE 256
32
4
39
4
3+1
1
3
2
--
2
2
--
12
2
√
8-ch
√
√
LQFP
48
M451LE6AE 128
32
4
39
4
3+1
1
3
2
--
2
2
--
12
2
√
8-ch
√
√
LQFP
48
M451RG6AE 256
32
4
53
4
4+1
1
3
2
--
2
2
--
12
2
√
12-ch
√
√
LQFP
64
M451RE6AE 128
32
4
53
4
4+1
1
3
2
--
2
2
--
12
2
√
12-ch
√
√
LQFP
64
M451VG6AE 256
32
4
85
4
4+1
1
3
2
--
2
2
--
12
2
√
16-ch
√
√
LQFP
100
M451VE6AE 128
32
4
85
4
4+1
1
3
2
--
2
2
--
12
2
√
16-ch
√
√
LQFP
100
M451LD3AE
72
16
4
39
4
4+1
1
2
2
--
2
1
--
12
2
√
10-ch
√
√
LQFP
48
M451LC3AE
40
16
4
39
4
4+1
1
2
2
--
2
1
--
12
2
√
10-ch
√
√
LQFP
48
M451RD3AE 72
16
4
53
4
4+1
1
2
2
--
2
1
--
12
2
√
16-ch
√
√
LQFP
64
M451RC3AE 40
16
4
53
4
4+1
1
2
2
--
2
1
--
12
2
√
16-ch
√
√
LQFP
64
Part Number
Flash (KB)
4.1.2 NuMicro® M451 Base Series Selection Guide
Connectivity
*Marked in this table (4+1) means 4 UART + 1 SC UART
*SC (ISO-7816) supports full duplex UART mode
M451 SERIES DATASHEET
Mar. 04, 2016
Page 21 of 219
Rev.2.05
M451
SRAM (KB)
ISP Loader ROM
(KB)
I/O
Timer
UART*
SC*
(ISO-7816 )
SPI
I2C
CAN
LIN
I2S
USB
PWM
Analog Comp.
DAC (12-Bit)
ADC (12-Bit)
RTC
ICP/ISPI/AP
Package
M451MLG6AE 256
32
4
42
4
3+1
1
3
2
--
2
2
--
12
2
√
9-ch
--
√
LQFP
48
M451MLE6AE 128
32
4
42
4
3+1
1
3
2
--
2
2
--
12
2
√
9-ch
--
√
LQFP
48
M451MLD3AE 72
16
4
42
4
4+1
1
2
2
--
2
1
--
12
2
√
11-ch
--
√
LQFP
48
M451MLC3AE 40
16
4
42
4
4+1
1
2
2
--
2
1
--
12
2
√
11-ch
--
√
LQFP
48
M451MSD3AE 72
16
4
55
4
4+1
1
2
2
--
2
1
--
12
2
√
13-ch
--
√
LQFP
64
M451MSC3AE 40
16
4
55
4
4+1
1
2
2
--
2
1
--
12
2
√
13-ch
--
√
LQFP
64
Part Number
Flash (KB)
4.1.3 NuMicro® M451M Series (M051 Pin Compatible) Selection Guide
Connectivity
*Marked in this table (4+1) means 4 UART + 1 SC UART
*SC (ISO-7816) supports full duplex UART mode
M451 SERIES DATASHEET
Mar. 04, 2016
Page 22 of 219
Rev.2.05
M451
SRAM (KB)
ISP Loader ROM
(KB)
I/O
Timer
UART*
SC*
(ISO-7816 )
SPI
I2C
CAN
LIN
I2S
USB
PWM
Analog Comp.
DAC (12-Bit)
ADC (12-Bit)
RTC
ICP/ISPI/AP
Package
M452LG6AE 256
32
4
34
4
3+1
1
3
2
--
2
2
OTG
10
2
√
8-ch
√
√
LQFP
48
M452LE6AE 128
32
4
34
4
3+1
1
3
2
--
2
2
OTG
10
2
√
8-ch
√
√
LQFP
48
M452RG6AE 256
32
4
48
4
4+1
1
3
2
--
2
2
OTG
12
2
√
12-ch
√
√
LQFP
64
M452RE6AE 128
32
4
48
4
4+1
1
3
2
--
2
2
OTG
12
2
√
12-ch
√
√
LQFP
64
M452LD3AE
72
16
4
35
4
4+1
1
2
2
--
2
1
Device 10
2
√
10-ch
√
√
LQFP
48
M452LC3AE
40
16
4
35
4
4+1
1
2
2
--
2
1
Device 10
2
√
10-ch
√
√
LQFP
48
M452RD3AE 72
16
4
49
4
4+1
1
2
2
--
2
1
Device 12
2
√
16ch,
√
√
LQFP
64
Part Number
Flash (KB)
4.1.4 NuMicro® M452 USB Series Selection Guide
Connectivity
*Marked in this table (4+1) means 4 UART + 1 SC UART
*SC (ISO-7816) supports full duplex UART mode
M451 SERIES DATASHEET
Mar. 04, 2016
Page 23 of 219
Rev.2.05
M451
SRAM (KB)
ISP Loader ROM
(KB)
I/O
Timer
UART*
SC*
(ISO-7816 )
SPI
I2C
CAN
LIN
I2S
USB
PWM
Analog Comp.
DAC (12-Bit)
ADC (12-Bit)
RTC
ICP/ISPI/AP
Package
M453LG6AE 256
32
4
34
4
3+1
1
3
2
√
2
2
OTG
10
2
1
8-ch
√
√
LQFP
48
M453LE6AE 128
32
4
34
4
3+1
1
3
2
√
2
2
OTG
10
2
1
8-ch
√
√
LQFP
48
M453RG6AE 256
32
4
48
4
4+1
1
3
2
√
2
2
OTG
12
2
1
12-ch
√
√
LQFP
64
M453RE6AE 128
32
4
48
4
4+1
1
3
2
√
2
2
OTG
12
2
1
12-ch
√
√
LQFP
64
M453VG6AE 256
32
4
80
4
4+1
1
3
2
√
2
2
OTG
12
2
1
16-ch
√
√
LQFP
100
M453VE6AE 128
32
4
80
4
4+1
1
3
2
√
2
2
OTG
12
2
1
16-ch
√
√
LQFP
100
M453LD3AE
72
16
4
35
4
4+1
1
2
2
√
2
1
Device 10
2
1
10-ch
√
√
LQFP
48
M453LC3AE
40
16
4
35
4
4+1
1
2
2
√
2
1
Device 10
2
1
10-ch
√
√
LQFP
48
M453RD3AE 72
16
4
49
4
4+1
1
2
2
√
2
1
Device 12
2
1
16-ch
√
√
LQFP
64
M453VD3AE
16
4
72
4
4+1
1
2
2
√
2
1
Device 12
2
1
16-ch
√
√
LQFP
100
Part Number
Flash (KB)
4.1.5 NuMicro® M453 CAN Series (CAN+USB) Selection Guide
72
Connectivity
*Marked in this table (4+1) means 4 UART + 1 SC UART
M451 SERIES DATASHEET
*SC (ISO-7816) supports full duplex UART mode
Mar. 04, 2016
Page 24 of 219
Rev.2.05
M451
4.2 Pin Configuration
4.2.1 NuMicro® M451 Base Series LQFP48 Pin Diagram
VDDIO
PE.13(LVIO)
PE.12(LVIO)
PE.11(LVIO)
PE.10(LVIO)
PE.9(LVIO)
PE.8(LVIO)
PF.6/ICE_DAT
PF.5/ICE_CLK
PC.7
PC.6
PC.5
36
35
34
33
32
31
30
29
28
27
26
25
Corresponding Part Number: M451LG6AE, M451LE6AE, M451LD3AE, M451LC3AE
PA.3
37
24
PE.0
PA.2
38
23
PC.4
PA.1
39
22
PC.3
PA.0
40
21
PC.2
VDD
41
20
PC.1
AVDD
42
19
PC.0
VREF
43
18
LDO_CAP
PB.0
44
17
VSS
PB.1
45
16
PF.4/XT1_IN
PB.2
46
15
PF.3/XT1_OUT
PB.3
47
14
PD.7
PB.4
48
13
PF.2
1
2
3
4
5
6
7
8
9
10
11
12
PB.6
PB.7
nRESET
PD.0
AVSS
PD.1
PD.2
PD.3
VBAT
X32_OUT/PF.0
X32_IN/PF.1
M451 SERIES DATASHEET
PB.5
LQFP 48-pin
®
Figure 4.2-1 NuMicro M451 Base Series LQFP 48-pin Diagram
Mar. 04, 2016
Page 25 of 219
Rev.2.05
M451
4.2.2 NuMicro® M451 Base Series LQFP64 Pin Diagram
VDDIO
PE.13(LVIO)
PE.12(LVIO)
PE.11(LVIO)
PE.10(LVIO)
PE.9(LVIO)
PE.8(LVIO)
PA.4
PA.5
PA.6
PA.7
PF.6/ICE_DAT
PF.5/ICE_CLK
PC.7
PC.6
PC.5
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Corresponding Part Number: M451RG6AE, M451RE6AE, M451RD3AE, M451RC3AE
PA.3
49
32
PE.0
PA.2
50
31
PC.4
PA.1
51
30
PC.3
PA.0
52
29
PC.2
VSS
53
28
PC.1
VDD
54
27
PC.0
AVDD
55
26
LDO_CAP
VREF
56
25
VDD
PB.0
57
24
VSS
PB.1
58
23
PF.4/XT1_IN
PB.2
59
22
PF.3/XT1_OUT
PB.3
60
21
PD.7
PB.4
61
20
PD.15
PB.8
62
19
PD.14
PB.11
63
18
PD.13
PB.12
64
17
PD.12
5
6
7
8
9
10
11
12
13
14
15
16
PD.0
AVSS
PD.8
PD.9
PD.1
PD.2
PD.3
VBAT
X32_OUT/PF.0
X32_IN/PF.1
PF.2
M451 SERIES DATASHEET
nRESET
3
PB.6
4
2
PB.5
PB.7
1
PB.15
LQFP 64-pin
®
Figure 4.2-2 NuMicro M451 Base Series LQFP 64-pin Diagram
Mar. 04, 2016
Page 26 of 219
Rev.2.05
M451
4.2.3 NuMicro® M451 Base Series LQFP100 Pin Diagram
VDDIO
PE.13(LVIO)
PE.12(LVIO)
PE.11(LVIO)
PE.10(LVIO)
PE.9(LVIO)
PE.8(LVIO)
PE.1
VDD
VSS
PA.4
PA.5
PA.6
PA.7
PE.6
PA.11
PA.10
PA.9
PA.8
PF.6/ICE_DAT
PF.5/ICE_CLK
PE.5
PE.4
PC.7
PC.6
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Corresponding Part Number: M451VG6AE, M451VE6AE
PE.7
76
50
PC.5
PC.15
77
49
PE.0
PE.2
78
48
PC.4
PA.3
79
47
PC.3
PA.2
80
46
PC.2
PA.1
81
45
PC.1
PA.0
82
44
PC.0
PA.12
83
43
PC.14
PA.13
84
42
PC.13
PA.14
85
41
PC.12
PA.15
86
40
PC.11
VSS
87
39
PC.10
VDD
88
38
PC.9
AVDD
89
37
LDO_CAP
VREF
90
36
VDD
PB.0
91
35
VSS
PB.1
92
34
PF.4/XT1_IN
PB.2
93
33
PF.3/XT1_OUT
PB.3
94
32
PD.7
PB.4
95
31
PD.15
PB.8
96
30
PD.14
PB.9
97
29
PD.13
PB.10
98
28
PD.12
PB.11
99
27
PD.11
PB.12
100
26
PD.10
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDD
VSS
PC.8
PD.8
PD.9
PD.1
PD.2
PD.3
PD.4
PD.5
PE.3
PD.6
VBAT
X32_OUT/PF.0
X32_IN/PF.1
PF.2
6
PB.7
AVSS
5
PB.6
8
4
PB.5
PD.0
3
PB.15
7
2
nRESET
1
PB.14
M451 SERIES DATASHEET
PB.13
LQFP 100-pin
®
Figure 4.2-3 NuMicro M451 Base Series LQFP 100-pin Diagram
Mar. 04, 2016
Page 27 of 219
Rev.2.05
M451
4.2.4 NuMicro® M451M Series (M051 Pin Compatible) LQFP48 Pin Diagram
PE.1
PA.4
PA.5
PA.6
PA.7
PF.6/ICE_DAT
PF.5/ICE_CLK
PE.5
PE.4
PC.7
PC.6
PC.5
36
35
34
33
32
31
30
29
28
27
26
25
Corresponding Part Number: M451MLG6AE, M451MLE6AE, M451MLD3AE,
M451MLC3AE
PA.3
37
24
PE.0
PA.2
38
23
PC.4
PA.1
39
22
PC.3
PA.0
40
21
PC.2
VDD
41
20
PC.1
AVDD
42
19
PC.0
PB.0
43
18
LDO_CAP
PB.1
44
17
VSS
PB.2
45
16
PF.4/XT1_IN
PB.3
46
15
PF.3/XT1_OUT
PB.4
47
14
PD.7
PB.8
48
13
PD.6
3
4
5
6
7
8
9
10
11
12
nRESET
PD.0
AVSS
PD.1
PD.2
PD.3
PD.4
PD.5
PE.3
2
PB.6
PB.7
1
PB.5
LQFP 48-pin
M451 SERIES DATASHEET
®
Figure 4.2-4 NuMicro M451M Base Series (Pin Compatible with M051) LQFP 48-pin Diagram
Mar. 04, 2016
Page 28 of 219
Rev.2.05
M451
4.2.5 NuMicro® M451M Series (M058S Pin Compatible) LQFP64 Pin Diagram
PE.1
PA.4
PA.5
PA.6
PA.7
PA.11
PA.10
PA.9
PA.8
PF.6/ICE_DAT
PF.5/ICE_CLK
PE.5
PE.4
PC.7
PC.6
PC.5
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Corresponding Part Number: M451MSD3AE, M451MSC3AE
PA.3
49
32
PE.0
PA.2
50
31
PC.4
PA.1
51
30
PC.3
PA.0
52
29
PC.2
VSS
53
28
PC.1
VDD
54
27
PC.0
AVDD
55
26
PC.13
25
PC.12
24
PC.11
VREF
56
PB.14
57
PB.13
58
23
PC.10
PB.0
59
22
LDO_CAP
PB.1
60
21
VDD
PB.2
61
20
VSS
PB.3
62
19
PF.4/XT1_IN
PB.4
63
18
PF.3/XT1_OUT
PB.8
64
17
PD.7
7
8
9
10
11
12
13
14
PC.8
PD.8
PD.9
PD.1
PD.2
PD.3
PD.4
PD.5
16
6
15
5
PD.0
AVSS
PE.3
4
PD.6
3
PB.7
2
nRESET
1
PB.6
®
Figure 4.2-5 NuMicro M451M Base Series (Pin Compatible with M058S) LQFP 64-pin Diagram
Mar. 04, 2016
Page 29 of 219
Rev.2.05
M451 SERIES DATASHEET
PB.5
LQFP 64-pin
M451
4.2.6 NuMicro® M452 USB Series LQFP48 Pin Diagram
USB_VDD33_CAP
USB_ID
USB_D+
USB_D-
USB_VBUS
VDDIO
PE.13(LVIO)
PE.12(LVIO)
PE.11(LVIO)
PE.10(LVIO)
PF.6/ICE_DAT
PF.5/ICE_CLK
36
35
34
33
32
31
30
29
28
27
26
25
Corresponding Part Number: M452LG6AE, M452LE6AE
PA.3
37
24
PE.0
PA.2
38
23
PC.4
PA.1
39
22
PC.3
PA.0
40
21
PC.2
VDD
41
20
PC.1
AVDD
42
19
PC.0
VREF
43
18
LDO_CAP
PB.0
44
17
VSS
PB.1
45
16
PF.4/XT1_IN
PB.2
46
15
PF.3/XT1_OUT
PB.3
47
14
PD.7
PB.4
48
13
PF.2
1
2
3
4
5
6
7
8
9
10
11
12
PB.5
PB.6
PB.7
nRESET
PD.0
AVSS
PD.1
PD.2
PD.3
VBAT
X32_OUT/PF.0
X32_IN/PF.1
LQFP 48-pin
M451 SERIES DATASHEET
®
Figure 4.2-6 NuMicro M451 USB Series LQFP 48-pin Diagram (M452LG/M452LE Device Only)
Mar. 04, 2016
Page 30 of 219
Rev.2.05
M451
USB_VDD33_CAP
PF.7
USB_D+
USB_D-
USB_VBUS
VDDIO
PE.13(LVIO)
PE.12(LVIO)
PE.11(LVIO)
PE.10(LVIO)
PF.6/ICE_DAT
PF.5/ICE_CLK
36
35
34
33
32
31
30
29
28
27
26
25
Corresponding Part Number: M452LD3AE, M452LC3AE
PA.3
37
24
PE.0
PA.2
38
23
PC.4
PA.1
39
22
PC.3
PA.0
40
21
PC.2
VDD
41
20
PC.1
AVDD
42
19
PC.0
VREF
43
18
LDO_CAP
PB.0
44
17
VSS
PB.1
45
16
PF.4/XT1_IN
PB.2
46
15
PF.3/XT1_OUT
PB.3
47
14
PD.7
PB.4
48
13
PF.2
1
2
3
4
5
6
7
8
9
10
11
12
PB.5
PB.6
PB.7
nRESET
PD.0
AVSS
PD.1
PD.2
PD.3
VBAT
X32_OUT/PF.0
X32_IN/PF.1
LQFP 48-pin
Mar. 04, 2016
Page 31 of 219
Rev.2.05
M451 SERIES DATASHEET
®
Figure 4.2-7 NuMicro M451 USB Series LQFP 48-pin Diagram (M452LD/M452LC Device Only)
M451
4.2.7 NuMicro® M452 USB Series LQFP64 Pin Diagram
UAB_VDD33_CAP
USB_ID
USB_D+
USB_D-
USB_VBUS
VDDIO
PE.13(LVIO)
PE.12(LVIO)
PE.11(LVIO)
PE.10(LVIO)
PE.9(LVIO)
PE.8(LVIO)
PF.6/ICE_DAT
PF.5/ICE_CLK
PC.7
PC.6
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Corresponding Part Number: M452RG6AE, M452RE6AE
PA.3
49
32
PC.5
PA.2
50
31
PC.4
PA.1
51
30
PC.3
PA.0
52
29
PC.2
VSS
53
28
PC.1
VDD
54
27
PC.0
AVDD
55
26
LDO_CAP
VREF
56
25
VDD
PB.0
57
24
VSS
PB.1
58
23
PF.4/XT1_IN
PB.2
59
22
PF.3/XT1_OUT
PB.3
60
21
PD.7
PB.4
61
20
PD.15
PB.8
62
19
PD.14
PB.11
63
18
PD.13
PB.12
64
17
PD.12
7
8
9
10
11
12
13
14
15
16
AVSS
PD.8
PD.9
PD.1
PD.2
PD.3
VBAT
X32_OUT/PF.0
X32_IN/PF.1
PF.2
4
PB.7
6
3
PB.6
PD.0
2
PB.5
5
M451 SERIES DATASHEET
nRESET
1
PB.15
LQFP 64-pin
®
Figure 4.2-8 NuMicro M451 USB Series LQFP 64-pin Diagram (M452RG/M452RE Device Only)
Mar. 04, 2016
Page 32 of 219
Rev.2.05
M451
UAB_VDD33_CAP
PF.7
USB_D+
USB_D-
USB_VBUS
VDDIO
PE.13(LVIO)
PE.12(LVIO)
PE.11(LVIO)
PE.10(LVIO)
PE.9(LVIO)
PE.8(LVIO)
PF.6/ICE_DAT
PF.5/ICE_CLK
PC.7
PC.6
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Corresponding Part Number:M452RD3AE
PA.3
49
32
PC.5
PA.2
50
31
PC.4
PA.1
51
30
PC.3
PA.0
52
29
PC.2
VSS
53
28
PC.1
VDD
54
27
PC.0
AVDD
55
26
LDO_CAP
VREF
56
25
VDD
PB.0
57
24
VSS
PB.1
58
23
PF.4/XT1_IN
PB.2
59
22
PF.3/XT1_OUT
PB.3
60
21
PD.7
PB.4
61
20
PD.15
PB.8
62
19
PD.14
PB.11
63
18
PD.13
PB.12
64
17
PD.12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PB.5
PB.6
PB.7
nRESET
PD.0
AVSS
PD.8
PD.9
PD.1
PD.2
PD.3
VBAT
X32_OUT/PF.0
X32_IN/PF.1
PF.2
®
Figure 4.2-9 NuMicro M451 USB Series LQFP 64-pin Diagram (M452RD Device Only)
Mar. 04, 2016
Page 33 of 219
Rev.2.05
M451 SERIES DATASHEET
PB.15
LQFP 64-pin
M451
4.2.8 NuMicro® M453 CAN Series (CAN+USB) LQFP48 Pin Diagram
USB_VDD33_CAP
USB_ID
USB_D+
USB_D-
USB_VBUS
VDDIO
PE.13(LVIO)
PE.12(LVIO)
PE.11(LVIO)
PE.10(LVIO)
PF.6/ICE_DAT
PF.5/ICE_CLK
36
35
34
33
32
31
30
29
28
27
26
25
Corresponding Part Number: M453LG6AE, M453LE6AE
PA.3
37
24
PE.0
PA.2
38
23
PC.4
PA.1
39
22
PC.3
PA.0
40
21
PC.2
VDD
41
20
PC.1
AVDD
42
19
PC.0
VREF
43
18
LDO_CAP
PB.0
44
17
VSS
PB.1
45
16
PF.4/XT1_IN
PB.2
46
15
PF.3/XT1_OUT
PB.3
47
14
PD.7
PB.4
48
13
PF.2
1
2
3
4
5
6
7
8
9
10
11
12
PB.6
PB.7
nRESET
PD.0
AVSS
PD.1
PD.2
PD.3
VBAT
X32_OUT/PF.0
X32_IN/PF.1
M451 SERIES DATASHEET
PB.5
LQFP 48-pin
®
Figure 4.2-10 NuMicro M451 CAN Series (CAN+USB) LQFP 48-pin Diagram (M453LG/M453LE
Device Only)
Mar. 04, 2016
Page 34 of 219
Rev.2.05
M451
USB_VDD33_CAP
PF.7
USB_D+
USB_D-
USB_VBUS
VDDIO
PE.13(LVIO)
PE.12(LVIO)
PE.11(LVIO)
PE.10(LVIO)
PF.6/ICE_DAT
PF.5/ICE_CLK
36
35
34
33
32
31
30
29
28
27
26
25
Corresponding Part Number: M453LD3AE, M453LC3AE
PA.3
37
24
PE.0
PA.2
38
23
PC.4
PA.1
39
22
PC.3
PA.0
40
21
PC.2
VDD
41
20
PC.1
AVDD
42
19
PC.0
VREF
43
18
LDO_CAP
PB.0
44
17
VSS
PB.1
45
16
PF.4/XT1_IN
PB.2
46
15
PF.3/XT1_OUT
PB.3
47
14
PD.7
PB.4
48
13
PF.2
1
2
3
4
5
6
7
8
9
10
11
12
PB.5
PB.6
PB.7
nRESET
PD.0
AVSS
PD.1
PD.2
PD.3
VBAT
X32_OUT/PF.0
X32_IN/PF.1
LQFP 48-pin
Mar. 04, 2016
Page 35 of 219
Rev.2.05
M451 SERIES DATASHEET
®
Figure 4.2-11 NuMicro M451 CAN Series (CAN+USB) LQFP 48-pin Diagram (M453LD/M453LC
Device Only)
M451
4.2.9 NuMicro® M453 CAN Series (CAN+USB) LQFP64 Pin Diagram
USB_VDD33_CAP
USB_ID
USB_D+
USB_D-
USB_VBUS
VDDIO
PE.13(LVIO)
PE.12(LVIO)
PE.11(LVIO)
PE.10(LVIO)
PE.9(LVIO)
PE.8(LVIO)
PF.6/ICE_DAT
PF.5/ICE_CLK
PC.7
PC.6
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Corresponding Part Number: M453RG6AE, M453RE6AE
PA.3
49
32
PC.5
PA.2
50
31
PC.4
PA.1
51
30
PC.3
PA.0
52
29
PC.2
VSS
53
28
PC.1
VDD
54
27
PC.0
AVDD
55
26
LDO_CAP
VREF
56
25
VDD
PB.0
57
24
VSS
PB.1
58
23
PF.4/XT1_IN
PB.2
59
22
PF.3/XT1_OUT
PB.3
60
21
PD.7
PB.4
61
20
PD.15
PB.8
62
19
PD.14
PB.11
63
18
PD.13
PB.12
64
17
PD.12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PB.5
PB.6
PB.7
nRESET
PD.0
AVSS
PD.8
PD.9
PD.1
PD.2
PD.3
VBAT
X32_OUT/PF.0
X32_IN/PF.1
PF.2
M451 SERIES DATASHEET
PB.15
LQFP 64-pin
®
Figure 4.2-12 NuMicro M451 CAN Series (CAN+USB) LQFP 64-pin Diagram (M453RG/M453RE
Device Only)
Mar. 04, 2016
Page 36 of 219
Rev.2.05
M451
USB_VDD33_CAP
PF.7
USB_D+
USB_D-
USB_VBUS
VDDIO
PE.13(LVIO)
PE.12(LVIO)
PE.11(LVIO)
PE.10(LVIO)
PE.9(LVIO)
PE.8(LVIO)
PF.6/ICE_DAT
PF.5/ICE_CLK
PC.7
PC.6
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Corresponding Part Number: M453RD3AE
PA.3
49
32
PC.5
PA.2
50
31
PC.4
PA.1
51
30
PC.3
PA.0
52
29
PC.2
VSS
53
28
PC.1
VDD
54
27
PC.0
AVDD
55
26
LDO_CAP
VREF
56
25
VDD
PB.0
57
24
VSS
PB.1
58
23
PF.4/XT1_IN
PB.2
59
22
PF.3/XT1_OUT
PB.3
60
21
PD.7
PB.4
61
20
PD.15
PB.8
62
19
PD.14
PB.11
63
18
PD.13
PB.12
64
17
PD.12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PB.5
PB.6
PB.7
nRESET
PD.0
AVSS
PD.8
PD.9
PD.1
PD.2
PD.3
VBAT
X32_OUT/PF.0
X32_IN/PF.1
PF.2
®
Figure 4.2-13 NuMicro M451 CAN Series (CAN+USB) LQFP 64-pin Diagram (M453RD Device Only)
Mar. 04, 2016
Page 37 of 219
Rev.2.05
M451 SERIES DATASHEET
PB.15
LQFP 64-pin
M451
4.2.10 NuMicro® M453 CAN Series (CAN+USB) LQFP100 Pin Diagram
USB_D+
USB_D-
USB_VBUS
VDDIO
PE.13(LVIO)
PE.12(LVIO)
PE.11(LVIO)
PE.10(LVIO)
PE.9(LVIO)
PE.8(LVIO)
PE.1
VDD
VSS
PA.4
PA.5
PA.6
PA.7
PA.9
PA.8
PF.6/ICE_DAT
PF.5/ICE_CLK
PE.5
PE.4
PC.7
PC.6
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Corresponding Part Number: M453VG6AE, M453VE6AE
76
50
PC.5
77
49
PE.0
PE.2
78
48
PC.4
PA.3
79
47
PC.3
PA.2
80
46
PC.2
PA.1
81
45
PC.1
PA.0
82
44
PC.0
PA.12
83
43
PC.14
PA.13
84
42
PC.13
PA.14
85
41
PC.12
PA.15
86
40
PC.11
VSS
87
39
PC.10
VDD
88
38
PC.9
AVDD
89
37
LDO_CAP
VREF
90
36
VDD
PB.0
91
35
VSS
PB.1
92
34
PF.4/XT1_IN
PB.2
93
33
PF.3/XT1_OUT
PB.3
94
32
PD.7
PB.4
95
31
PD.15
PB.8
96
30
PD.14
PB.9
97
29
PD.13
PB.10
98
28
PD.12
PB.11
99
27
PD.11
PB.12
100
26
PD.10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PB.14
PB.15
PB.5
PB.6
PB.7
nRESET
PD.0
AVSS
VDD
VSS
PC.8
PD.8
PD.9
PD.1
PD.2
PD.3
PD.4
PD.5
PE.3
PD.6
VBAT
X32_OUT/PF.0
X32_IN/PF.1
PF.2
LQFP 100-pin
PB.13
M451 SERIES DATASHEET
USB_ID
USB_VDD33_CAP
®
Figure 4.2-14 NuMicro M451 CAN Series (CAN+USB) LQFP 100-pin Diagram (M453VG/M453VE
Device Only)
Mar. 04, 2016
Page 38 of 219
Rev.2.05
M451
USB_D+
USB_D-
USB_VBUS
VDDIO
PE.13(LVIO)
PE.12(LVIO)
PE.11(LVIO)
PE.10(LVIO)
PE.9(LVIO)
PE.8(LVIO)
PE.1
NC
VSS
PA.4
PA.5
PA.6
PA.7
PA.9
PA.8
PF.6/ICE_DAT
PF.5/ICE_CLK
PE.5
PE.4
PC.7
PC.6
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Corresponding Part Number: M453VD3AE
76
50
PC.5
77
49
PE.0
NC
78
48
PC.4
PA.3
79
47
PC.3
PA.2
80
46
PC.2
PA.1
81
45
PC.1
PA.0
82
44
PC.0
PA.12
83
43
NC
PA.13
84
42
PC.13
PA.14
85
41
PC.12
PA.15
86
40
PC.11
VSS
87
39
PC.10
VDD
88
38
NC
AVDD
89
37
LDO_CAP
VREF
90
36
VDD
PB.0
91
35
VSS
PB.1
92
34
PF.4/XT1_IN
PB.2
93
33
PF.3/XT1_OUT
PB.3
94
32
PD.7
PB.4
95
31
PD.15
PB.8
96
30
PD.14
NC
97
29
PD.13
NC
98
28
PD.12
PB.11
99
27
NC
PB.12
100
26
NC
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PC.8
PD.8
PD.9
PD.1
PD.2
PD.3
PD.4
PD.5
PE.3
PD.6
VBAT
X32_OUT/PF.0
X32_IN/PF.1
PF.2
8
PD.0
11
7
nRESET
NC
6
PB.7
10
5
PB.6
VDD
4
PB.5
9
3
PB.15
AVSS
2
1
NC
NC
LQFP 100-pin
®
Figure 4.2-15 NuMicro M451 CAN Series (CAN+USB) LQFP 100-pin Diagram (M453VD Device
Only)
Mar. 04, 2016
Page 39 of 219
Rev.2.05
M451 SERIES DATASHEET
PF.7
USB_VDD33_CAP
M451
4.3 Pin Description
4.3.1 M451 Base Series LQFP48 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0.
PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5.
Pin No.
Type
MFP*
Description
I/O
MFP0
General purpose digital I/O pin.
EADC_CH13
A
MFP1
EADC analog input channel 13.
SPI0_MOSI0
I/O
MFP2
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1_MOSI
I/O
MFP3
SPI1 MOSI (Master Out, Slave In) pin.
ACMP0_P2
A
MFP5
Comparator0 positive input pin.
EBI_AD6
I/O
MFP7
EBI address/data bus bit 6.
UART2_RXD
I/O
MFP9
Data receiver input pin for UART2. (M45xD/M45xC Only)
PB.6
I/O
MFP0
General purpose digital I/O pin.
EADC_CH14
A
MFP1
EADC analog input channel 14.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
ACMP0_P1
A
MFP5
Comparator0 positive input pin.
EBI_AD5
I/O
MFP7
EBI address/data bus bit 5.
PB.7
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 15.
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin
ACMP0_P0
A
MFP5
Comparator0 positive input pin.
EBI_AD4
I/O
MFP7
EBI address/data bus bit 4.
STADC
I/O
MFP10
ADC external trigger input. (M45xD/M45xC Only)
4
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
5
PD.0
I/O
MFP0
General purpose digital I/O pin.
EADC_CH6
A
MFP1
EADC analog input channel 6. (M45xD/M45xC Only)
SPI1_I2SMCLK
O
MFP2
I2S1 master clock output pin.
UART0_RXD
I
MFP3
Data receiver input pin for UART0.
ACMP1_N
A
MFP5
Comparator1 negative input pin.
INT3
I
MFP8
External interrupt3 input pin.
I/O
MFP11
Timer3 event counter input / toggle output.
(M45xD/M45xC Only)
1
2
3
Pin Name
PB.5
M451 SERIES DATASHEET
EADC_CH15
T3
Mar. 04, 2016
Page 40 of 219
Rev.2.05
M451
Pin No.
Pin Name
Type
MFP*
Description
AVSS
P
MFP0
Ground pin for analog circuit.
7
PD.1
I/O
MFP0
General purpose digital I/O pin.
EADC_CH11
A
MFP1
EADC analog input channel 11. (M45xD/M45xC Only)
PWM0_SYNC_IN
I
MFP2
PWM0 counter synchronous trigger input pin.
UART0_TXD
O
MFP3
Data transmitter output pin for UART0.
ACMP1_P2
A
MFP5
Comparator1 positive input pin.
T0
I/O
MFP6
Timer0event counter input / toggle output
EBI_nRD
O
MFP7
EBI read enable output pin.
PD.2
I/O
MFP0
General purpose digital I/O pin.
STADC
I
MFP1
ADC external trigger input.
T0_EXT
I
MFP3
Timer0 external counter input
ACMP1_P1
A
MFP5
Comparator1 positive input pin.
PWM0_BRAKE0
I
MFP6
PWM0 break input 0
EBI_nWR
O
MFP7
EBI write enable output pin.
INT0
I
MFP8
External interrupt0 input pin.
PD.3
I/O
MFP0
General purpose digital I/O pin.
T2
I/O
MFP1
Timer2 event counter input / toggle output
T1_EXT
I
MFP3
Timer1 external counter input
ACMP1_P0
A
MFP5
Comparator1 positive input pin.
PWM0_BRAKE1
I
MFP6
PWM0 break input 1
EBI_MCLK
O
MFP7
EBI external clock output pin
INT1
I
MFP8
External interrupt1 input pin.
MFP0
Power supply by batteries for RTC and PF.0~PF.2.
8
9
10
VBAT
11
PF.0
I/O
MFP0
General purpose digital I/O pin.
X32_OUT
O
MFP1
External 32.768 kHZ (low speed) crystal output pin.
INT5
I
MFP8
External interrupt5 input pin.
PF.1
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 32.768 kHZ (low speed) crystal input pin.
PF.2
I/O
MFP0
General purpose digital I/O pin.
TAMPER
I/O
MFP1
TAMPER detector loop pin
PD.7
I/O
MFP0
General purpose digital I/O pin.
I
MFP3
PWM0 counter synchronous trigger input pin.
T1
I/O
MFP4
Timer1 event counter input / toggle output
ACMP0_O
O
MFP5
Comparator0 output .
12
X32_IN
13
14
PWM0_SYNC_IN
Mar. 04, 2016
Page 41 of 219
Rev.2.05
M451 SERIES DATASHEET
6
M451
Pin No.
15
16
Pin Name
Type
MFP*
Description
PWM0_CH5
I/O
MFP6
PWM0 output/capture input.
EBI_nRD
O
MFP7
EBI read enable output pin.
PF.3
I/O
MFP0
General purpose digital I/O pin.
XT1_OUT
O
MFP1
External 4~20 MHz (high speed) crystal output pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
PF.4
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 4~20 MHz (high speed) crystal input pin.
I/O
MFP3
I2C1 data input/output pin.
XT1_IN
I2C1_SDA
17
VSS
A
MFP0
Ground pin for digital circuit.
18
LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with a 1uF
capacitor.
19
PC.0
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
I
MFP3
Clear to Send input pin for UART2.
PWM0_CH0
I/O
MFP6
PWM0 output/capture input.
EBI_AD8
I/O
MFP7
EBI address/data bus bit 8.
INT2
I
MFP8
External interrupt2 input pin.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
T3_EXT
I
MFP11
Timer3 external counter input. (M45xD/M45xC Only)
PC.1
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP1
Clock Out
STDAC
I
MFP2
DAC external trigger input.
UART2_nRTS
O
MFP3
Request to Send output pin for UART2.
PWM0_CH1
I/O
MFP6
PWM0 output/capture input.
EBI_AD9
I/O
MFP7
EBI address/data bus bit 9.
UART3_RXD
I/O
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
PC.2
I/O
MFP0
General purpose digital I/O pin.
SPI2_SS
I
MFP2
SPI2 slave select pin. (M45xG/M45xE Only)
UART2_TXD
O
MFP3
Data transmitter output pin for UART2.
ACMP1_O
O
MFP5
Comparator1 output .
PWM0_CH2
I/O
MFP6
PWM0 output/capture input.
EBI_AD10
I/O
MFP7
EBI address/data bus bit 10.
PC.3
I/O
MFP0
General purpose digital I/O pin.
SPI2_MOSI
I/O
MFP2
SPI2 MOSI (Master Out, Slave In) pin. (M45xG/M45xE
UART2_nCTS
M451 SERIES DATASHEET
20
21
22
Mar. 04, 2016
Page 42 of 219
Rev.2.05
M451
Pin No.
Pin Name
Type
MFP*
Description
Only)
23
24
25
27
I
MFP3
Data receiver input pin for UART2.
PWM0_CH3
I/O
MFP6
PWM0 output/capture input.
EBI_AD11
I/O
MFP7
EBI address/data bus bit 11.
PC.4
I/O
MFP0
General purpose digital I/O pin.
SPI2_MISO
I/O
MFP2
SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE
Only)
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
PWM0_CH4
I/O
MFP6
PWM0 output/capture input.
EBI_AD12
I/O
MFP7
EBI address/data bus bit 12.
PE.0
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
T2_EXT
I
MFP4
Timer2 external counter input
SC0_CD
I
MFP5
SmartCard card detect pin.
PWM0_CH0
I/O
MFP6
PWM0 output/capture input.
EBI_nCS1
O
MFP7
EBI chip select 1 enable output pin.
INT4
I
MFP8
External interrupt4 input pin.
PC.5
I/O
MFP0
General purpose digital I/O pin.
SPI2_I2SMCLK
O
MFP2
I2S2 master clock output pin. (M45xG/M45xE Only)
PWM0_CH5
I/O
MFP6
PWM0 output/capture input.
EBI_AD13
I/O
MFP7
EBI address/data bus bit 13.
PC.6
I/O
MFP0
General purpose digital I/O pin.
I2C1_SMBAL
O
MFP3
I2C1 SMBus SMBALTER# pin
ACMP1_O
O
MFP5
Comparator1 output .
PWM1_CH0
I/O
MFP6
PWM1 output/capture input.
EBI_AD14
I/O
MFP7
EBI address/data bus bit 14.
UART0_TXD
O
MFP9
Data transmitter output pin for UART0. (M45xD/M45xC
Only)
PC.7
I/O
MFP0
General purpose digital I/O pin.
I2C1_SMBSUS
O
MFP3
I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)
PWM1_CH1
I/O
MFP6
PWM1 output/capture input.
EBI_AD15
I/O
MFP7
EBI address/data bus bit 15.
I
MFP9
Data receiver input pin for UART0. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
Serial wired debugger clock pin
UART0_RXD
28
PF.5
ICE_CLK
Mar. 04, 2016
Page 43 of 219
Rev.2.05
M451 SERIES DATASHEET
26
UART2_RXD
M451
Pin No.
29
30
31
32
M451 SERIES DATASHEET
33
Pin Name
Type
MFP*
Description
PF.6
I/O
MFP0
General purpose digital I/O pin.
ICE_DAT
I/O
MFP1
Serial wired debugger data pin
PE.8
I/O
MFP0
General purpose digital I/O pin.
UART1_TXD
O
MFP1
Data transmitter output pin for UART1.
SPI0_MISO1
I/O
MFP2
SPI0 2nd MISO (Master In, Slave Out) pin.
I2C1_SCL
I/O
MFP4
I2C1 clock pin.
SC0_PWR
O
MFP5
SmartCard power pin.
CLKO
O
MFP9
Clock Out (M45xD/M45xC Only)
PWM0_BRAKE0
I
MFP10
PWM0 break input 0 (M45xD/M45xC Only)
T1
I/O
MFP11
Timer1 event counter input / toggle output
(M45xD/M45xC Only)
PE.9
I/O
MFP0
General purpose digital I/O pin.
UART1_RXD
I
MFP1
Data receiver input pin for UART1.
SPI0_MOSI1
I/O
MFP2
SPI0 2nd MOSI (Master Out, Slave In) pin.
I2C1_SDA
I/O
MFP4
I2C1 data input/output pin.
SC0_RST
O
MFP5
SmartCard reset pin.
SPI1_I2SMCLK
O
MFP9
I2S1 master clock output pin. (M45xD/M45xC Only)
PWM1_BRAKE1
I
MFP10
PWM1 break input 1 (M45xD/M45xC Only)
T2
I/O
MFP11
Timer2 event counter input / toggle output
(M45xD/M45xC Only)
PE.10
I/O
MFP0
General purpose digital I/O pin.
SPI1_MISO
I/O
MFP1
SPI1 MISO (Master In, Slave Out) pin.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
UART1_nCTS
I
MFP3
Clear to Send input pin for UART1.
I2C0_SMBAL
O
MFP4
I2C0 SMBus SMBALTER# pin
SC0_DAT
I/O
MFP5
SmartCard data pin.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
I2C1_SCL
I/O
MFP11
I2C1 clock pin. (M45xD/M45xC Only)
PE.11
I/O
MFP0
General purpose digital I/O pin.
SPI1_MOSI
I/O
MFP1
SPI1 MOSI (Master Out, Slave In) pin.
SPI0_MOSI0
I/O
MFP2
SPI0 1st MOSI (Master Out, Slave In) pin.
UART1_nRTS
O
MFP3
Request to Send output pin for UART1.
I2C0_SMBSUS
O
MFP4
I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)
SC0_CLK
O
MFP5
SmartCard clock pin.
UART3_RXD
I
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
Mar. 04, 2016
Page 44 of 219
Rev.2.05
M451
Pin No.
34
35
Pin Name
Type
MFP*
I2C1_SDA
I/O
MFP11
I2C1 data input/output pin. (M45xD/M45xC Only)
PE.12
I/O
MFP0
General purpose digital I/O pin.
SPI1_SS
I/O
MFP1
SPI1 slave select pin
SPI0_SS
I/O
MFP2
SPI0 slave select pin.
UART1_TXD
O
MFP3
Data transmitter output pin for UART1.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
PE.13
I/O
MFP0
General purpose digital I/O pin.
SPI1_CLK
I/O
MFP1
SPI1 serial clock pin
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
I
MFP3
Data receiver input pin for UART1.
I/O
MFP4
I2C0 data input/output pin.
UART1_RXD
I2C0_SDA
Description
VDDIO
A
MFP0
Power supply for PE.8~PE.13.
37
PA.3
I/O
MFP0
General purpose digital I/O pin.
UART0_RXD
I
MFP2
Data receiver input pin for UART0.
UART0_nRTS
O
MFP3
Request to Send output pin for UART0.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
SC0_PWR
O
MFP5
SmartCard power pin.
PWM1_CH2
I/O
MFP6
PWM1 output/capture input.
EBI_AD3
I/O
MFP7
EBI address/data bus bit 3.
PA.2
I/O
MFP0
General purpose digital I/O pin.
UART0_TXD
O
MFP2
Data transmitter output pin for UART0.
UART0_nCTS
I
MFP3
Clear to Send input pin for UART0.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
SC0_RST
O
MFP5
SmartCard reset pin.
PWM1_CH3
I/O
MFP6
PWM1 output/capture input.
EBI_AD2
I/O
MFP7
EBI address/data bus bit 2.
PA.1
I/O
MFP0
General purpose digital I/O pin.
UART1_nRTS
O
MFP1
Request to Send output pin for UART1.
UART1_RXD
I
MFP3
Data receiver input pin for UART1.
SC0_DAT
I/O
MFP5
SmartCard data pin.
PWM1_CH4
I/O
MFP6
PWM1 output/capture input.
EBI_AD1
I/O
MFP7
EBI address/data bus bit 1.
STADC
I/O
MFP10
ADC external trigger input. (M45xD/M45xC Only)
PA.0
I/O
MFP0
General purpose digital I/O pin.
38
39
40
Mar. 04, 2016
Page 45 of 219
M451 SERIES DATASHEET
36
Rev.2.05
M451
Pin No.
Pin Name
Type
MFP*
Description
UART1_nCTS
I
MFP1
Clear to Send input pin for UART1.
UART1_TXD
O
MFP3
Data transmitter output pin for UART1.
SC0_CLK
O
MFP5
SmartCard clock pin.
PWM1_CH5
I/O
MFP6
PWM1 output/capture input.
EBI_AD0
I/O
MFP7
EBI address/data bus bit 0.
INT0
I
MFP8
External interrupt0 input pin.
SPI1_I2SMCLK
O
MFP9
I2S1 master clock output pin. (M45xD/M45xC Only)
41
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
42
AVDD
A
MFP0
Power supply for internal analog circuit.
43
VREF
I
MFP0
Voltage reference input for ADC.
Note: This pin needs to be connected with a 1uF
capacitor.
44
PB.0
I/O
MFP0
General purpose digital I/O pin.
EADC_CH0
A
MFP1
EADC analog input.
SPI0_MOSI1
I/O
MFP2
SPI0 2nd MOSI (Master Out, Slave In) pin.
UART2_RXD
I
MFP3
Data receiver input pin for UART2.
I/O
MFP4
Timer2 event counter input / toggle output
DAC
A
MFP5
DAC analog output
EBI_nWRL
O
MFP7
EBI low byte write enable output pin.
INT1
I
MFP8
External interrupt1 input pin.
PB.1
I/O
MFP0
General purpose digital I/O pin.
EADC_CH1
A
MFP1
EADC analog input channel 1.
SPI0_MISO1
I/O
MFP2
SPI0 2nd MISO (Master In, Slave Out) pin.
UART2_TXD
O
MFP3
Data transmitter output pin for UART2.
T3
I/O
MFP4
Timer3 event counter input / toggle output
SC0_RST
O
MFP5
SmartCard reset pin.
PWM0_SYNC_OUT
O
MFP6
PWM0 counter synchronous trigger output pin.
EBI_nWRH
O
MFP7
EBI high byte write enable output pin
PB.2
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 2.
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin
UART1_RXD
I
MFP4
Data receiver input pin for UART1.
SC0_CD
I
MFP5
SmartCard card detect pin.
UART3_RXD
I
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
T2
M451 SERIES DATASHEET
45
46
EADC_CH2
Mar. 04, 2016
Page 46 of 219
Rev.2.05
M451
Pin No.
Pin Name
Type
MFP*
I
MFP11
Timer2 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
EADC_CH3
A
MFP1
EADC analog input channel 3.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
UART1_TXD
O
MFP4
Data transmitter output pin for UART1.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
T0_EXT
I
MFP11
Timer0 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 4.
SPI0_SS
I/O
MFP2
SPI0 slave select pin.
SPI1_SS
I/O
MFP3
SPI1 slave select pin
UART1_nCTS
I
MFP4
Clear to Send input pin for UART1.
ACMP0_N
A
MFP5
Comparator0 negative input pin.
EBI_AD7
I/O
MFP7
EBI address/data bus bit 7.
UART2_TXD
O
MFP9
Data transmitter output pin for UART2. (M45xD/M45xC
Only)
T1_EXT
I
MFP11
Timer1 external counter input. (M45xD/M45xC Only)
T2_EXT
47
48
PB.3
PB.4
EADC_CH4
Description
M451 SERIES DATASHEET
Mar. 04, 2016
Page 47 of 219
Rev.2.05
M451
4.3.2 M451 Base Series LQFP64 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0.
PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5.
Pin No.
Type
MFP*
Description
I/O
MFP0
General purpose digital I/O pin.
EADC_CH12
A
MFP1
EADC analog input channel 12.
ACMP0_P3
A
MFP5
Comparator0 positive input pin.
EBI_nCS1
O
MFP7
EBI chip select 1 enable output pin.
PB.5
I/O
MFP0
General purpose digital I/O pin.
EADC_CH13
A
MFP1
EADC analog input channel 13.
SPI0_MOSI0
I/O
MFP2
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1_MOSI
I/O
MFP3
SPI1 MOSI (Master Out, Slave In) pin.
ACMP0_P2
A
MFP5
Comparator0 positive input pin.
EBI_AD6
I/O
MFP7
EBI address/data bus bit 6.
UART2_RXD
I/O
MFP9
Data receiver input pin for UART2. (M45xD/M45xC Only)
PB.6
I/O
MFP0
General purpose digital I/O pin.
EADC_CH14
A
MFP1
EADC analog input channel 14.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
ACMP0_P1
A
MFP5
Comparator0 positive input pin.
EBI_AD5
I/O
MFP7
EBI address/data bus bit 5.
PB.7
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 15.
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin
ACMP0_P0
A
MFP5
Comparator0 positive input pin.
EBI_AD4
I/O
MFP7
EBI address/data bus bit 4.
STADC
I/O
MFP10
ADC external trigger input. (M45xD/M45xC Only)
5
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
6
PD.0
I/O
MFP0
General purpose digital I/O pin.
EADC_CH6
A
MFP1
EADC analog input channel 6. (M45xD/M45xC Only)
SPI1_I2SMCLK
O
MFP2
I2S1 master clock output pin.
UART0_RXD
I
MFP3
Data receiver input pin for UART0.
ACMP1_N
A
MFP5
Comparator1 negative input pin.
1
2
3
M451 SERIES DATASHEET
4
Pin Name
PB.15
EADC_CH15
Mar. 04, 2016
Page 48 of 219
Rev.2.05
M451
Pin No.
Pin Name
INT3
T3
Type
MFP*
Description
I
MFP8
External interrupt3 input pin.
I/O
MFP11
Timer3 event counter input / toggle output.
(M45xD/M45xC Only)
AVSS
P
MFP0
Ground pin for analog circuit.
8
PD.8
I/O
MFP0
General purpose digital I/O pin.
EADC_CH7
A
MFP1
EADC analog input channel 7. (M45xD/M45xC Only)
EBI_nCS0
O
MFP7
EBI chip select 0 enable output pin.
PD.9
I/O
MFP0
General purpose digital I/O pin.
EADC_CH10
A
MFP1
EADC analog input channel 10. (M45xD/M45xC Only)
ACMP1_P3
A
MFP5
Comparator1 positive input pin.
EBI_ALE
O
MFP7
EBI address latch enable output pin.
PD.1
I/O
MFP0
General purpose digital I/O pin.
EADC_CH11
A
MFP1
EADC analog input channel 11. (M45xD/M45xC Only)
PWM0_SYNC_IN
I
MFP2
PWM0 counter synchronous trigger input pin.
UART0_TXD
O
MFP3
Data transmitter output pin for UART0.
ACMP1_P2
A
MFP5
Comparator1 positive input pin.
T0
I/O
MFP6
Timer0event counter input / toggle output
EBI_nRD
O
MFP7
EBI read enable output pin.
PD.2
I/O
MFP0
General purpose digital I/O pin.
STADC
I
MFP1
ADC external trigger input.
T0_EXT
I
MFP3
Timer0 external counter input
ACMP1_P1
A
MFP5
Comparator1 positive input pin.
PWM0_BRAKE0
I
MFP6
PWM0 break input 0
EBI_nWR
O
MFP7
EBI write enable output pin.
INT0
I
MFP8
External interrupt0 input pin.
PD.3
I/O
MFP0
General purpose digital I/O pin.
T2
I/O
MFP1
Timer2 event counter input / toggle output
T1_EXT
I
MFP3
Timer1 external counter input
ACMP1_P0
A
MFP5
Comparator1 positive input pin.
PWM0_BRAKE1
I
MFP6
PWM0 break input 1
EBI_MCLK
O
MFP7
EBI external clock output pin
INT1
I
MFP8
External interrupt1 input pin.
MFP0
Power supply by batteries for RTC and PF.0~PF.2.
9
10
11
12
M451 SERIES DATASHEET
7
13
VBAT
14
PF.0
I/O
MFP0
General purpose digital I/O pin.
X32_OUT
O
MFP1
External 32.768 kHZ (low speed) crystal output pin.
Mar. 04, 2016
Page 49 of 219
Rev.2.05
M451
Pin No.
15
Pin Name
Type
MFP*
Description
INT5
I
MFP8
External interrupt5 input pin.
PF.1
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 32.768 kHZ (low speed) crystal input pin.
PF.2
I/O
MFP0
General purpose digital I/O pin.
TAMPER
I/O
MFP1
TAMPER detector loop pin
PD.12
I/O
MFP0
General purpose digital I/O pin.
SPI2_SS
I
MFP2
SPI2 slave select pin. (M45xG/M45xE Only)
UART3_TXD
O
MFP3
Data transmitter output pin for UART3.
PWM1_CH0
I/O
MFP6
PWM1 output/capture input.
EBI_ADR16
O
MFP7
EBI address bus bit 16.
PD.13
I/O
MFP0
General purpose digital I/O pin.
SPI2_MOSI
I/O
MFP2
SPI2 MOSI (Master Out, Slave In) pin. (M45xG/M45xE
Only)
UART3_RXD
I
MFP3
Data receiver input pin for UART3.
PWM1_CH1
I/O
MFP6
PWM1 output/capture input.
EBI_ADR17
O
MFP7
EBI address bus bit 17.
PD.14
I/O
MFP0
General purpose digital I/O pin.
SPI2_MISO
I/O
MFP2
SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE
Only)
I
MFP3
Clear to Send input pin for UART3.
PWM1_CH2
I/O
MFP6
PWM1 output/capture input.
EBI_ADR18
O
MFP7
EBI address bus bit 18.
PD.15
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
UART3_nRTS
O
MFP3
Request to Send output pin for UART3.
PWM1_CH3
I/O
MFP6
PWM1 output/capture input.
EBI_ADR19
O
MFP7
EBI address bus bit 19.
PD.7
I/O
MFP0
General purpose digital I/O pin.
I
MFP3
PWM0 counter synchronous trigger input pin.
T1
I/O
MFP4
Timer1 event counter input / toggle output
ACMP0_O
O
MFP5
Comparator0 output .
PWM0_CH5
I/O
MFP6
PWM0 output/capture input.
EBI_nRD
O
MFP7
EBI read enable output pin.
PF.3
I/O
MFP0
General purpose digital I/O pin.
XT1_OUT
O
MFP1
External 4~20 MHz (high speed) crystal output pin.
X32_IN
16
17
18
19
UART3_nCTS
M451 SERIES DATASHEET
20
21
PWM0_SYNC_IN
22
Mar. 04, 2016
Page 50 of 219
Rev.2.05
M451
Pin No.
23
Pin Name
Type
MFP*
Description
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
PF.4
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 4~20 MHz (high speed) crystal input pin.
I/O
MFP3
I2C1 data input/output pin.
XT1_IN
I2C1_SDA
24
VSS
A
MFP0
Ground pin for digital circuit.
25
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
26
LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with a 1uF
capacitor.
27
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
I
MFP3
Clear to Send input pin for UART2.
PWM0_CH0
I/O
MFP6
PWM0 output/capture input.
EBI_AD8
I/O
MFP7
EBI address/data bus bit 8.
INT2
I
MFP8
External interrupt2 input pin.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
T3_EXT
I
MFP11
Timer3 external counter input. (M45xD/M45xC Only)
PC.1
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP1
Clock Out
STDAC
I
MFP2
DAC external trigger input.
UART2_nRTS
O
MFP3
Request to Send output pin for UART2.
PWM0_CH1
I/O
MFP6
PWM0 output/capture input.
EBI_AD9
I/O
MFP7
EBI address/data bus bit 9.
UART3_RXD
I/O
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
PC.2
I/O
MFP0
General purpose digital I/O pin.
SPI2_SS
I
MFP2
SPI2 slave select pin. (M45xG/M45xE Only)
UART2_TXD
O
MFP3
Data transmitter output pin for UART2.
ACMP1_O
O
MFP5
Comparator1 output .
PWM0_CH2
I/O
MFP6
PWM0 output/capture input.
EBI_AD10
I/O
MFP7
EBI address/data bus bit 10.
PC.3
I/O
MFP0
General purpose digital I/O pin.
SPI2_MOSI
I/O
MFP2
SPI2 MOSI (Master Out, Slave In) pin. (M45xG/M45xE
Only)
UART2_RXD
I
MFP3
Data receiver input pin for UART2.
PWM0_CH3
I/O
MFP6
PWM0 output/capture input.
UART2_nCTS
28
29
30
Mar. 04, 2016
Page 51 of 219
Rev.2.05
M451 SERIES DATASHEET
PC.0
M451
Pin No.
31
32
33
34
M451 SERIES DATASHEET
35
Pin Name
Type
MFP*
Description
EBI_AD11
I/O
MFP7
EBI address/data bus bit 11.
PC.4
I/O
MFP0
General purpose digital I/O pin.
SPI2_MISO
I/O
MFP2
SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE
Only)
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
PWM0_CH4
I/O
MFP6
PWM0 output/capture input.
EBI_AD12
I/O
MFP7
EBI address/data bus bit 12.
PE.0
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
T2_EXT
I
MFP4
Timer2 external counter input
SC0_CD
I
MFP5
SmartCard card detect pin.
PWM0_CH0
I/O
MFP6
PWM0 output/capture input.
EBI_nCS1
O
MFP7
EBI chip select 1 enable output pin.
INT4
I
MFP8
External interrupt4 input pin.
PC.5
I/O
MFP0
General purpose digital I/O pin.
SPI2_I2SMCLK
O
MFP2
I2S2 master clock output pin. (M45xG/M45xE Only)
PWM0_CH5
I/O
MFP6
PWM0 output/capture input.
EBI_AD13
I/O
MFP7
EBI address/data bus bit 13.
PC.6
I/O
MFP0
General purpose digital I/O pin.
I2C1_SMBAL
O
MFP3
I2C1 SMBus SMBALTER# pin
ACMP1_O
O
MFP5
Comparator1 output .
PWM1_CH0
I/O
MFP6
PWM1 output/capture input.
EBI_AD14
I/O
MFP7
EBI address/data bus bit 14.
UART0_TXD
O
MFP9
Data transmitter output pin for UART0. (M45xD/M45xC
Only)
PC.7
I/O
MFP0
General purpose digital I/O pin.
I2C1_SMBSUS
O
MFP3
I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)
PWM1_CH1
I/O
MFP6
PWM1 output/capture input.
EBI_AD15
I/O
MFP7
EBI address/data bus bit 15.
I
MFP9
Data receiver input pin for UART0. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
Serial wired debugger clock pin
PF.6
I/O
MFP0
General purpose digital I/O pin.
ICE_DAT
I/O
MFP1
Serial wired debugger data pin
UART0_RXD
36
PF.5
ICE_CLK
37
Mar. 04, 2016
Page 52 of 219
Rev.2.05
M451
Pin No.
38
39
40
41
42
44
Type
MFP*
Description
PA.7
I/O
MFP0
General purpose digital I/O pin.
SPI1_CLK
I/O
MFP2
SPI1 serial clock pin
T0_EXT
I
MFP3
Timer0 external counter input
EBI_AD7
I/O
MFP7
EBI address/data bus bit 7.
PA.6
I/O
MFP0
General purpose digital I/O pin.
SPI1_MISO
I/O
MFP2
SPI1 MISO (Master In, Slave Out) pin.
T1_EXT
I
MFP3
Timer1 external counter input
EBI_AD6
I/O
MFP7
EBI address/data bus bit 6.
PA.5
I/O
MFP0
General purpose digital I/O pin.
SPI1_MOSI
I/O
MFP2
SPI1 MOSI (Master Out, Slave In) pin.
T2_EXT
I
MFP3
Timer2 external counter input
EBI_AD5
I/O
MFP7
EBI address/data bus bit 5.
PA.4
I/O
MFP0
General purpose digital I/O pin.
SPI1_SS
I/O
MFP2
SPI1 slave select pin
EBI_AD4
I/O
MFP7
EBI address/data bus bit 4.
PE.8
I/O
MFP0
General purpose digital I/O pin.
UART1_TXD
O
MFP1
Data transmitter output pin for UART1.
SPI0_MISO1
I/O
MFP2
SPI0 2nd MISO (Master In, Slave Out) pin.
I2C1_SCL
I/O
MFP4
I2C1 clock pin.
SC0_PWR
O
MFP5
SmartCard power pin.
CLKO
O
MFP9
Clock Out (M45xD/M45xC Only)
PWM0_BRAKE0
I
MFP10
PWM0 break input 0 (M45xD/M45xC Only)
T1
I/O
MFP11
Timer1 event counter input / toggle output
(M45xD/M45xC Only)
PE.9
I/O
MFP0
General purpose digital I/O pin.
UART1_RXD
I
MFP1
Data receiver input pin for UART1.
SPI0_MOSI1
I/O
MFP2
SPI0 2nd MOSI (Master Out, Slave In) pin.
I2C1_SDA
I/O
MFP4
I2C1 data input/output pin.
SC0_RST
O
MFP5
SmartCard reset pin.
SPI1_I2SMCLK
O
MFP9
I2S1 master clock output pin. (M45xD/M45xC Only)
PWM1_BRAKE1
I
MFP10
PWM1 break input 1 (M45xD/M45xC Only)
T2
I/O
MFP11
Timer2 event counter input / toggle output
(M45xD/M45xC Only)
PE.10
I/O
MFP0
General purpose digital I/O pin.
SPI1_MISO
I/O
MFP1
SPI1 MISO (Master In, Slave Out) pin.
Mar. 04, 2016
Page 53 of 219
M451 SERIES DATASHEET
43
Pin Name
Rev.2.05
M451
Pin No.
45
46
M451 SERIES DATASHEET
47
Pin Name
Type
MFP*
Description
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
UART1_nCTS
I
MFP3
Clear to Send input pin for UART1.
I2C0_SMBAL
O
MFP4
I2C0 SMBus SMBALTER# pin
SC0_DAT
I/O
MFP5
SmartCard data pin.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
I2C1_SCL
I/O
MFP11
I2C1 clock pin. (M45xD/M45xC Only)
PE.11
I/O
MFP0
General purpose digital I/O pin.
SPI1_MOSI
I/O
MFP1
SPI1 MOSI (Master Out, Slave In) pin.
SPI0_MOSI0
I/O
MFP2
SPI0 1st MOSI (Master Out, Slave In) pin.
UART1_nRTS
O
MFP3
Request to Send output pin for UART1.
I2C0_SMBSUS
O
MFP4
I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)
SC0_CLK
O
MFP5
SmartCard clock pin.
UART3_RXD
I
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
I2C1_SDA
I/O
MFP11
I2C1 data input/output pin. (M45xD/M45xC Only)
PE.12
I/O
MFP0
General purpose digital I/O pin.
SPI1_SS
I/O
MFP1
SPI1 slave select pin
SPI0_SS
I/O
MFP2
SPI0 slave select pin.
UART1_TXD
O
MFP3
Data transmitter output pin for UART1.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
PE.13
I/O
MFP0
General purpose digital I/O pin.
SPI1_CLK
I/O
MFP1
SPI1 serial clock pin
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
I
MFP3
Data receiver input pin for UART1.
I/O
MFP4
I2C0 data input/output pin.
UART1_RXD
I2C0_SDA
48
VDDIO
A
MFP0
Power supply for PE.8~PE.13.
49
PA.3
I/O
MFP0
General purpose digital I/O pin.
UART0_RXD
I
MFP2
Data receiver input pin for UART0.
UART0_nRTS
O
MFP3
Request to Send output pin for UART0.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
SC0_PWR
O
MFP5
SmartCard power pin.
PWM1_CH2
I/O
MFP6
PWM1 output/capture input.
EBI_AD3
I/O
MFP7
EBI address/data bus bit 3.
PA.2
I/O
MFP0
General purpose digital I/O pin.
UART0_TXD
O
MFP2
Data transmitter output pin for UART0.
50
Mar. 04, 2016
Page 54 of 219
Rev.2.05
M451
Pin No.
Pin Name
MFP*
Description
I
MFP3
Clear to Send input pin for UART0.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
SC0_RST
O
MFP5
SmartCard reset pin.
PWM1_CH3
I/O
MFP6
PWM1 output/capture input.
EBI_AD2
I/O
MFP7
EBI address/data bus bit 2.
PA.1
I/O
MFP0
General purpose digital I/O pin.
UART1_nRTS
O
MFP1
Request to Send output pin for UART1.
UART1_RXD
I
MFP3
Data receiver input pin for UART1.
SC0_DAT
I/O
MFP5
SmartCard data pin.
PWM1_CH4
I/O
MFP6
PWM1 output/capture input.
EBI_AD1
I/O
MFP7
EBI address/data bus bit 1.
STADC
I/O
MFP10
ADC external trigger input. (M45xD/M45xC Only)
PA.0
I/O
MFP0
General purpose digital I/O pin.
UART1_nCTS
I
MFP1
Clear to Send input pin for UART1.
UART1_TXD
O
MFP3
Data transmitter output pin for UART1.
SC0_CLK
O
MFP5
SmartCard clock pin.
PWM1_CH5
I/O
MFP6
PWM1 output/capture input.
EBI_AD0
I/O
MFP7
EBI address/data bus bit 0.
INT0
I
MFP8
External interrupt0 input pin.
SPI1_I2SMCLK
O
MFP9
I2S1 master clock output pin. (M45xD/M45xC Only)
53
VSS
A
MFP0
Ground pin for digital circuit.
54
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
55
AVDD
A
MFP0
Power supply for internal analog circuit.
56
VREF
I
MFP0
Voltage reference input for ADC.
UART0_nCTS
51
52
Note: This pin needs to be connected with a 1uF
capacitor.
57
PB.0
I/O
MFP0
General purpose digital I/O pin.
EADC_CH0
A
MFP1
EADC analog input.
SPI0_MOSI1
I/O
MFP2
SPI0 2nd MOSI (Master Out, Slave In) pin.
UART2_RXD
I
MFP3
Data receiver input pin for UART2.
I/O
MFP4
Timer2 event counter input / toggle output
DAC
A
MFP5
DAC analog output
EBI_nWRL
O
MFP7
EBI low byte write enable output pin.
INT1
I
MFP8
External interrupt1 input pin.
PB.1
I/O
MFP0
General purpose digital I/O pin.
T2
58
Mar. 04, 2016
Page 55 of 219
Rev.2.05
M451 SERIES DATASHEET
Type
M451
Pin No.
59
Pin Name
Type
MFP*
Description
EADC_CH1
A
MFP1
EADC analog input channel 1.
SPI0_MISO1
I/O
MFP2
SPI0 2nd MISO (Master In, Slave Out) pin.
UART2_TXD
O
MFP3
Data transmitter output pin for UART2.
T3
I/O
MFP4
Timer3 event counter input / toggle output
SC0_RST
O
MFP5
SmartCard reset pin.
PWM0_SYNC_OUT
O
MFP6
PWM0 counter synchronous trigger output pin.
EBI_nWRH
O
MFP7
EBI high byte write enable output pin
PB.2
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 2.
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin
UART1_RXD
I
MFP4
Data receiver input pin for UART1.
SC0_CD
I
MFP5
SmartCard card detect pin.
UART3_RXD
I
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
T2_EXT
I
MFP11
Timer2 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
EADC_CH3
A
MFP1
EADC analog input channel 3.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
UART1_TXD
O
MFP4
Data transmitter output pin for UART1.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
T0_EXT
I
MFP11
Timer0 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 4.
SPI0_SS
I/O
MFP2
SPI0 slave select pin.
SPI1_SS
I/O
MFP3
SPI1 slave select pin
UART1_nCTS
I
MFP4
Clear to Send input pin for UART1.
ACMP0_N
A
MFP5
Comparator0 negative input pin.
EBI_AD7
I/O
MFP7
EBI address/data bus bit 7.
UART2_TXD
O
MFP9
Data transmitter output pin for UART2. (M45xD/M45xC
Only)
T1_EXT
I
MFP11
Timer1 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 5.
EADC_CH2
60
M451 SERIES DATASHEET
61
PB.3
PB.4
EADC_CH4
62
PB.8
EADC_CH5
Mar. 04, 2016
Page 56 of 219
Rev.2.05
M451
Pin No.
63
Pin Name
Type
MFP*
Description
UART1_nRTS
O
MFP4
Request to Send output pin for UART1.
PWM0_CH2
I/O
MFP6
PWM0 output/capture input.
PB.11
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 8.
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 9.
EADC_CH8
64
PB.12
EADC_CH9
M451 SERIES DATASHEET
Mar. 04, 2016
Page 57 of 219
Rev.2.05
M451
4.3.3 M451 Base Series LQFP100 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[3:0] = 0x0.
PA.9 MFP5 means SYS_GPA_MFPH[7:4] = 0x5.
Pin No.
Type
MFP*
Description
I/O
MFP0
General purpose digital I/O pin. (M45xG/M45xE Only)
A
MFP1
EADC analog input channel 10. (M45xG/M45xE Only)
I/O
MFP0
General purpose digital I/O pin. (M45xG/M45xE Only)
A
MFP1
EADC analog input channel 11. (M45xG/M45xE Only)
I/O
MFP0
General purpose digital I/O pin.
EADC_CH12
A
MFP1
EADC analog input channel 12.
ACMP0_P3
A
MFP5
Comparator0 positive input pin.
EBI_nCS1
O
MFP7
EBI chip select 1 enable output pin.
PB.5
I/O
MFP0
General purpose digital I/O pin.
EADC_CH13
A
MFP1
EADC analog input channel 13.
SPI0_MOSI0
I/O
MFP2
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1_MOSI
I/O
MFP3
SPI1 MOSI (Master Out, Slave In) pin.
ACMP0_P2
A
MFP5
Comparator0 positive input pin.
EBI_AD6
I/O
MFP7
EBI address/data bus bit 6.
UART2_RXD
I/O
MFP9
Data receiver input pin for UART2. (M45xD/M45xC Only)
PB.6
I/O
MFP0
General purpose digital I/O pin.
EADC_CH14
A
MFP1
EADC analog input channel 14.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
ACMP0_P1
A
MFP5
Comparator0 positive input pin.
EBI_AD5
I/O
MFP7
EBI address/data bus bit 5.
PB.7
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 15.
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin
ACMP0_P0
A
MFP5
Comparator0 positive input pin.
EBI_AD4
I/O
MFP7
EBI address/data bus bit 4.
STADC
I/O
MFP10
ADC external trigger input. (M45xD/M45xC Only)
7
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
8
PD.0
I/O
MFP0
General purpose digital I/O pin.
1
Pin Name
PB.13
EADC_CH10
2
PB.14
EADC_CH11
3
4
5
M451 SERIES DATASHEET
6
PB.15
EADC_CH15
Mar. 04, 2016
Page 58 of 219
Rev.2.05
M451
Pin No.
Pin Name
Type
MFP*
Description
EADC_CH6
A
MFP1
EADC analog input channel 6. (M45xD/M45xC Only)
SPI1_I2SMCLK
O
MFP2
I2S1 master clock output pin.
UART0_RXD
I
MFP3
Data receiver input pin for UART0.
ACMP1_N
A
MFP5
Comparator1 negative input pin.
INT3
I
MFP8
External interrupt3 input pin.
I/O
MFP11
Timer3 event counter input / toggle output.
(M45xD/M45xC Only)
T3
AVSS
P
MFP0
Ground pin for analog circuit.
10
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
11
VSS
A
MFP0
Ground pin for digital circuit. (M45xG/M45xE Only)
12
PC.8
I/O
MFP0
General purpose digital I/O pin.
13
PD.8
I/O
MFP0
General purpose digital I/O pin.
EADC_CH7
A
MFP1
EADC analog input channel 7. (M45xD/M45xC Only)
EBI_nCS0
O
MFP7
EBI chip select 0 enable output pin.
PD.9
I/O
MFP0
General purpose digital I/O pin.
EADC_CH10
A
MFP1
EADC analog input channel 10. (M45xD/M45xC Only)
ACMP1_P3
A
MFP5
Comparator1 positive input pin.
EBI_ALE
O
MFP7
EBI address latch enable output pin.
PD.1
I/O
MFP0
General purpose digital I/O pin.
EADC_CH11
A
MFP1
EADC analog input channel 11. (M45xD/M45xC Only)
PWM0_SYNC_IN
I
MFP2
PWM0 counter synchronous trigger input pin.
UART0_TXD
O
MFP3
Data transmitter output pin for UART0.
ACMP1_P2
A
MFP5
Comparator1 positive input pin.
T0
I/O
MFP6
Timer0event counter input / toggle output
EBI_nRD
O
MFP7
EBI read enable output pin.
PD.2
I/O
MFP0
General purpose digital I/O pin.
STADC
I
MFP1
ADC external trigger input.
T0_EXT
I
MFP3
Timer0 external counter input
ACMP1_P1
A
MFP5
Comparator1 positive input pin.
PWM0_BRAKE0
I
MFP6
PWM0 break input 0
EBI_nWR
O
MFP7
EBI write enable output pin.
INT0
I
MFP8
External interrupt0 input pin.
PD.3
I/O
MFP0
General purpose digital I/O pin.
T2
I/O
MFP1
Timer2 event counter input / toggle output
14
15
16
17
Mar. 04, 2016
Page 59 of 219
M451 SERIES DATASHEET
9
Rev.2.05
M451
Pin No.
18
Pin Name
Type
MFP*
Description
T1_EXT
I
MFP3
Timer1 external counter input
ACMP1_P0
A
MFP5
Comparator1 positive input pin.
PWM0_BRAKE1
I
MFP6
PWM0 break input 1
EBI_MCLK
O
MFP7
EBI external clock output pin
INT1
I
MFP8
External interrupt1 input pin.
PD.4
I/O
MFP0
General purpose digital I/O pin.
SPI1_CLK
I/O
MFP2
SPI1 serial clock pin
I2C0_SDA
I/O
MFP3
I2C0 data input/output pin.
I
MFP5
PWM0 break input 0
T0
I/O
MFP6
Timer0event counter input / toggle output
PD.5
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP1
Clock Out
SPI1_MISO
I/O
MFP2
SPI1 MISO (Master In, Slave Out) pin.
I2C0_SCL
I/O
MFP3
I2C0 clock pin.
I
MFP5
PWM0 break input 1
T1
I/O
MFP6
Timer1 event counter input / toggle output
PE.3
I/O
MFP0
General purpose digital I/O pin.
SPI1_MOSI
I/O
MFP2
SPI1 MOSI (Master Out, Slave In) pin.
PWM0_CH3
I/O
MFP6
PWM0 output/capture input.
PD.6
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP1
Clock Out
SPI1_SS
I/O
MFP2
SPI1 slave select pin
UART0_RXD
I
MFP3
Data receiver input pin for UART0.
ACMP0_O
O
MFP5
Comparator0 output .
PWM0_CH5
I/O
MFP6
PWM0 output/capture input.
EBI_nWR
O
MFP7
EBI write enable output pin.
MFP0
Power supply by batteries for RTC and PF.0~PF.2.
PWM0_BRAKE0
19
PWM0_BRAKE1
20
21
M451 SERIES DATASHEET
22
VBAT
23
PF.0
I/O
MFP0
General purpose digital I/O pin.
X32_OUT
O
MFP1
External 32.768 kHZ (low speed) crystal output pin.
INT5
I
MFP8
External interrupt5 input pin.
PF.1
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 32.768 kHZ (low speed) crystal input pin.
PF.2
I/O
MFP0
General purpose digital I/O pin.
TAMPER
I/O
MFP1
TAMPER detector loop pin
24
X32_IN
25
Mar. 04, 2016
Page 60 of 219
Rev.2.05
M451
Pin No.
26
27
28
29
30
Pin Name
MFP*
Description
PD.10
I/O
MFP0
General purpose digital I/O pin.
T2
I/O
MFP4
Timer2 event counter input / toggle output
PD.11
I/O
MFP0
General purpose digital I/O pin.
T3
I/O
MFP4
Timer3 event counter input / toggle output
PD.12
I/O
MFP0
General purpose digital I/O pin.
SPI2_SS
I
MFP2
SPI2 slave select pin. (M45xG/M45xE Only)
UART3_TXD
O
MFP3
Data transmitter output pin for UART3.
PWM1_CH0
I/O
MFP6
PWM1 output/capture input.
EBI_ADR16
O
MFP7
EBI address bus bit 16.
PD.13
I/O
MFP0
General purpose digital I/O pin.
SPI2_MOSI
I/O
MFP2
SPI2 MOSI (Master Out, Slave In) pin. (M45xG/M45xE
Only)
UART3_RXD
I
MFP3
Data receiver input pin for UART3.
PWM1_CH1
I/O
MFP6
PWM1 output/capture input.
EBI_ADR17
O
MFP7
EBI address bus bit 17.
PD.14
I/O
MFP0
General purpose digital I/O pin.
SPI2_MISO
I/O
MFP2
SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE
Only)
I
MFP3
Clear to Send input pin for UART3.
PWM1_CH2
I/O
MFP6
PWM1 output/capture input.
EBI_ADR18
O
MFP7
EBI address bus bit 18.
PD.15
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
UART3_nRTS
O
MFP3
Request to Send output pin for UART3.
PWM1_CH3
I/O
MFP6
PWM1 output/capture input.
EBI_ADR19
O
MFP7
EBI address bus bit 19.
PD.7
I/O
MFP0
General purpose digital I/O pin.
I
MFP3
PWM0 counter synchronous trigger input pin.
T1
I/O
MFP4
Timer1 event counter input / toggle output
ACMP0_O
O
MFP5
Comparator0 output .
PWM0_CH5
I/O
MFP6
PWM0 output/capture input.
EBI_nRD
O
MFP7
EBI read enable output pin.
PF.3
I/O
MFP0
General purpose digital I/O pin.
XT1_OUT
O
MFP1
External 4~20 MHz (high speed) crystal output pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
UART3_nCTS
31
32
PWM0_SYNC_IN
33
Mar. 04, 2016
Page 61 of 219
M451 SERIES DATASHEET
Type
Rev.2.05
M451
Pin No.
34
Pin Name
PF.4
XT1_IN
I2C1_SDA
Type
MFP*
Description
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 4~20 MHz (high speed) crystal input pin.
I/O
MFP3
I2C1 data input/output pin.
35
VSS
A
MFP0
Ground pin for digital circuit.
36
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
37
LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with a 1uF
capacitor.
38
39
40
41
M451 SERIES DATASHEET
42
PC.9
I/O
MFP0
General purpose digital I/O pin.
SPI2_I2SMCLK
O
MFP2
I2S2 master clock output pin. (M45xG/M45xE Only)
PWM1_CH0
I/O
MFP6
PWM1 output/capture input.
PC.10
I/O
MFP0
General purpose digital I/O pin.
SPI2_MOSI
I/O
MFP2
SPI2 MOSI (Master Out, Slave In) pin. (M45xG/M45xE
Only)
PWM1_CH1
I/O
MFP6
PWM1 output/capture input.
PC.11
I/O
MFP0
General purpose digital I/O pin.
SPI2_MISO
I/O
MFP2
SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE
Only)
PWM1_CH2
I/O
MFP6
PWM1 output/capture input.
PC.12
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
PWM1_CH3
I/O
MFP6
PWM1 output/capture input.
PC.13
I/O
MFP0
General purpose digital I/O pin.
I
MFP2
SPI2 slave select pin. (M45xG/M45xE Only)
PWM1_CH4
I/O
MFP6
PWM1 output/capture input.
PC.14
I/O
MFP0
General purpose digital I/O pin.
PWM1_CH5
I/O
MFP6
PWM1 output/capture input.
PC.0
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
I
MFP3
Clear to Send input pin for UART2.
PWM0_CH0
I/O
MFP6
PWM0 output/capture input.
EBI_AD8
I/O
MFP7
EBI address/data bus bit 8.
INT2
I
MFP8
External interrupt2 input pin.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
T3_EXT
I
MFP11
Timer3 external counter input. (M45xD/M45xC Only)
SPI2_SS
43
44
UART2_nCTS
Mar. 04, 2016
Page 62 of 219
Rev.2.05
M451
Pin No.
45
46
47
48
50
Type
MFP*
Description
PC.1
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP1
Clock Out
STDAC
I
MFP2
DAC external trigger input.
UART2_nRTS
O
MFP3
Request to Send output pin for UART2.
PWM0_CH1
I/O
MFP6
PWM0 output/capture input.
EBI_AD9
I/O
MFP7
EBI address/data bus bit 9.
UART3_RXD
I/O
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
PC.2
I/O
MFP0
General purpose digital I/O pin.
SPI2_SS
I
MFP2
SPI2 slave select pin. (M45xG/M45xE Only)
UART2_TXD
O
MFP3
Data transmitter output pin for UART2.
ACMP1_O
O
MFP5
Comparator1 output .
PWM0_CH2
I/O
MFP6
PWM0 output/capture input.
EBI_AD10
I/O
MFP7
EBI address/data bus bit 10.
PC.3
I/O
MFP0
General purpose digital I/O pin.
SPI2_MOSI
I/O
MFP2
SPI2 MOSI (Master Out, Slave In) pin. (M45xG/M45xE
Only)
UART2_RXD
I
MFP3
Data receiver input pin for UART2.
PWM0_CH3
I/O
MFP6
PWM0 output/capture input.
EBI_AD11
I/O
MFP7
EBI address/data bus bit 11.
PC.4
I/O
MFP0
General purpose digital I/O pin.
SPI2_MISO
I/O
MFP2
SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE
Only)
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
PWM0_CH4
I/O
MFP6
PWM0 output/capture input.
EBI_AD12
I/O
MFP7
EBI address/data bus bit 12.
PE.0
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
T2_EXT
I
MFP4
Timer2 external counter input
SC0_CD
I
MFP5
SmartCard card detect pin.
PWM0_CH0
I/O
MFP6
PWM0 output/capture input.
EBI_nCS1
O
MFP7
EBI chip select 1 enable output pin.
INT4
I
MFP8
External interrupt4 input pin.
PC.5
I/O
MFP0
General purpose digital I/O pin.
SPI2_I2SMCLK
O
MFP2
I2S2 master clock output pin. (M45xG/M45xE Only)
Mar. 04, 2016
Page 63 of 219
Rev.2.05
M451 SERIES DATASHEET
49
Pin Name
M451
Pin No.
51
52
Pin Name
Type
MFP*
Description
PWM0_CH5
I/O
MFP6
PWM0 output/capture input.
EBI_AD13
I/O
MFP7
EBI address/data bus bit 13.
PC.6
I/O
MFP0
General purpose digital I/O pin.
I2C1_SMBAL
O
MFP3
I2C1 SMBus SMBALTER# pin
ACMP1_O
O
MFP5
Comparator1 output .
PWM1_CH0
I/O
MFP6
PWM1 output/capture input.
EBI_AD14
I/O
MFP7
EBI address/data bus bit 14.
UART0_TXD
O
MFP9
Data transmitter output pin for UART0. (M45xD/M45xC
Only)
PC.7
I/O
MFP0
General purpose digital I/O pin.
I2C1_SMBSUS
O
MFP3
I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)
PWM1_CH1
I/O
MFP6
PWM1 output/capture input.
EBI_AD15
I/O
MFP7
EBI address/data bus bit 15.
I
MFP9
Data receiver input pin for UART0. (M45xD/M45xC Only)
PE.4
I/O
MFP0
General purpose digital I/O pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
SC0_PWR
O
MFP5
SmartCard power pin.
PWM1_BRAKE0
I
MFP6
PWM1 break input 0
EBI_nCS0
O
MFP7
EBI chip select 0 enable output pin.
INT0
I
MFP8
External interrupt0 input pin.
PE.5
I/O
MFP0
General purpose digital I/O pin.
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
SC0_RST
O
MFP5
SmartCard reset pin.
PWM1_BRAKE1
I
MFP6
PWM1 break input 1
EBI_ALE
O
MFP7
EBI address latch enable output pin.
INT1
I
MFP8
External interrupt1 input pin.
PF.5
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
Serial wired debugger clock pin
PF.6
I/O
MFP0
General purpose digital I/O pin.
ICE_DAT
I/O
MFP1
Serial wired debugger data pin
PA.8
I/O
MFP0
General purpose digital I/O pin.
UART3_TXD
O
MFP3
Data transmitter output pin for UART3.
PA.9
I/O
MFP0
General purpose digital I/O pin.
I
MFP3
Data receiver input pin for UART3.
I/O
MFP0
General purpose digital I/O pin.
UART0_RXD
53
M451 SERIES DATASHEET
54
55
ICE_CLK
56
57
58
UART3_RXD
59
PA.10
Mar. 04, 2016
Page 64 of 219
Rev.2.05
M451
Pin No.
Pin Name
Type
MFP*
Description
I
MFP3
Clear to Send input pin for UART3.
PA.11
I/O
MFP0
General purpose digital I/O pin.
UART3_nRTS
O
MFP3
Request to Send output pin for UART3.
PE.6
I/O
MFP0
General purpose digital I/O pin.
I
MFP3
Timer3 external counter input
PA.7
I/O
MFP0
General purpose digital I/O pin.
SPI1_CLK
I/O
MFP2
SPI1 serial clock pin
T0_EXT
I
MFP3
Timer0 external counter input
EBI_AD7
I/O
MFP7
EBI address/data bus bit 7.
PA.6
I/O
MFP0
General purpose digital I/O pin.
SPI1_MISO
I/O
MFP2
SPI1 MISO (Master In, Slave Out) pin.
T1_EXT
I
MFP3
Timer1 external counter input
EBI_AD6
I/O
MFP7
EBI address/data bus bit 6.
PA.5
I/O
MFP0
General purpose digital I/O pin.
SPI1_MOSI
I/O
MFP2
SPI1 MOSI (Master Out, Slave In) pin.
T2_EXT
I
MFP3
Timer2 external counter input
EBI_AD5
I/O
MFP7
EBI address/data bus bit 5.
PA.4
I/O
MFP0
General purpose digital I/O pin.
SPI1_SS
I/O
MFP2
SPI1 slave select pin
EBI_AD4
I/O
MFP7
EBI address/data bus bit 4.
UART3_nCTS
60
61
T3_EXT
62
63
64
65
VSS
A
MFP0
Ground pin for digital circuit.
67
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
68
PE.1
I/O
MFP0
General purpose digital I/O pin.
T3_EXT
I
MFP3
Timer3 external counter input
SC0_CD
I
MFP5
SmartCard card detect pin.
PWM0_CH1
I/O
MFP6
PWM0 output/capture input.
PE.8
I/O
MFP0
General purpose digital I/O pin.
UART1_TXD
O
MFP1
Data transmitter output pin for UART1.
SPI0_MISO1
I/O
MFP2
SPI0 2nd MISO (Master In, Slave Out) pin.
I2C1_SCL
I/O
MFP4
I2C1 clock pin.
SC0_PWR
O
MFP5
SmartCard power pin.
CLKO
O
MFP9
Clock Out (M45xD/M45xC Only)
PWM0_BRAKE0
I
MFP10
PWM0 break input 0 (M45xD/M45xC Only)
I/O
MFP11
Timer1 event counter input / toggle output
69
T1
Mar. 04, 2016
Page 65 of 219
Rev.2.05
M451 SERIES DATASHEET
66
M451
Pin No.
Pin Name
Type
MFP*
Description
(M45xD/M45xC Only)
70
71
72
M451 SERIES DATASHEET
73
74
PE.9
I/O
MFP0
General purpose digital I/O pin.
UART1_RXD
I
MFP1
Data receiver input pin for UART1.
SPI0_MOSI1
I/O
MFP2
SPI0 2nd MOSI (Master Out, Slave In) pin.
I2C1_SDA
I/O
MFP4
I2C1 data input/output pin.
SC0_RST
O
MFP5
SmartCard reset pin.
SPI1_I2SMCLK
O
MFP9
I2S1 master clock output pin. (M45xD/M45xC Only)
PWM1_BRAKE1
I
MFP10
PWM1 break input 1 (M45xD/M45xC Only)
T2
I/O
MFP11
Timer2 event counter input / toggle output
(M45xD/M45xC Only)
PE.10
I/O
MFP0
General purpose digital I/O pin.
SPI1_MISO
I/O
MFP1
SPI1 MISO (Master In, Slave Out) pin.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
UART1_nCTS
I
MFP3
Clear to Send input pin for UART1.
I2C0_SMBAL
O
MFP4
I2C0 SMBus SMBALTER# pin
SC0_DAT
I/O
MFP5
SmartCard data pin.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
I2C1_SCL
I/O
MFP11
I2C1 clock pin. (M45xD/M45xC Only)
PE.11
I/O
MFP0
General purpose digital I/O pin.
SPI1_MOSI
I/O
MFP1
SPI1 MOSI (Master Out, Slave In) pin.
SPI0_MOSI0
I/O
MFP2
SPI0 1st MOSI (Master Out, Slave In) pin.
UART1_nRTS
O
MFP3
Request to Send output pin for UART1.
I2C0_SMBSUS
O
MFP4
I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)
SC0_CLK
O
MFP5
SmartCard clock pin.
UART3_RXD
I
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
I2C1_SDA
I/O
MFP11
I2C1 data input/output pin. (M45xD/M45xC Only)
PE.12
I/O
MFP0
General purpose digital I/O pin.
SPI1_SS
I/O
MFP1
SPI1 slave select pin
SPI0_SS
I/O
MFP2
SPI0 slave select pin.
UART1_TXD
O
MFP3
Data transmitter output pin for UART1.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
PE.13
I/O
MFP0
General purpose digital I/O pin.
SPI1_CLK
I/O
MFP1
SPI1 serial clock pin
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
I
MFP3
Data receiver input pin for UART1.
UART1_RXD
Mar. 04, 2016
Page 66 of 219
Rev.2.05
M451
Pin No.
Pin Name
Type
MFP*
Description
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
VDDIO
A
MFP0
Power supply for PE.8~PE.13.
76
PE.7
I/O
MFP0
General purpose digital I/O pin.
77
PC.15
I/O
MFP0
General purpose digital I/O pin.
PWM1_CH0
I/O
MFP6
PWM1 output/capture input.
PE.2
I/O
MFP0
General purpose digital I/O pin.
PWM1_CH1
I/O
MFP6
PWM1 output/capture input.
PA.3
I/O
MFP0
General purpose digital I/O pin.
UART0_RXD
I
MFP2
Data receiver input pin for UART0.
UART0_nRTS
O
MFP3
Request to Send output pin for UART0.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
SC0_PWR
O
MFP5
SmartCard power pin.
PWM1_CH2
I/O
MFP6
PWM1 output/capture input.
EBI_AD3
I/O
MFP7
EBI address/data bus bit 3.
PA.2
I/O
MFP0
General purpose digital I/O pin.
UART0_TXD
O
MFP2
Data transmitter output pin for UART0.
UART0_nCTS
I
MFP3
Clear to Send input pin for UART0.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
SC0_RST
O
MFP5
SmartCard reset pin.
PWM1_CH3
I/O
MFP6
PWM1 output/capture input.
EBI_AD2
I/O
MFP7
EBI address/data bus bit 2.
PA.1
I/O
MFP0
General purpose digital I/O pin.
UART1_nRTS
O
MFP1
Request to Send output pin for UART1.
UART1_RXD
I
MFP3
Data receiver input pin for UART1.
SC0_DAT
I/O
MFP5
SmartCard data pin.
PWM1_CH4
I/O
MFP6
PWM1 output/capture input.
EBI_AD1
I/O
MFP7
EBI address/data bus bit 1.
STADC
I/O
MFP10
ADC external trigger input. (M45xD/M45xC Only)
PA.0
I/O
MFP0
General purpose digital I/O pin.
UART1_nCTS
I
MFP1
Clear to Send input pin for UART1.
UART1_TXD
O
MFP3
Data transmitter output pin for UART1.
SC0_CLK
O
MFP5
SmartCard clock pin.
PWM1_CH5
I/O
MFP6
PWM1 output/capture input.
EBI_AD0
I/O
MFP7
EBI address/data bus bit 0.
78
79
80
81
82
Mar. 04, 2016
Page 67 of 219
M451 SERIES DATASHEET
75
Rev.2.05
M451
Pin No.
Type
MFP*
Description
INT0
I
MFP8
External interrupt0 input pin.
SPI1_I2SMCLK
O
MFP9
I2S1 master clock output pin. (M45xD/M45xC Only)
PA.12
I/O
MFP0
General purpose digital I/O pin.
SPI1_I2SMCLK
O
MFP2
I2S1 master clock output pin.
84
PA.13
I/O
MFP0
General purpose digital I/O pin.
85
PA.14
I/O
MFP0
General purpose digital I/O pin.
UART2_nCTS
I
MFP3
Clear to Send input pin for UART2.
I2C0_SMBAL
O
MFP4
I2C0 SMBus SMBALTER# pin
PA.15
I/O
MFP0
General purpose digital I/O pin.
UART2_nRTS
O
MFP3
Request to Send output pin for UART2.
I2C0_SMBSUS
O
MFP4
I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)
87
VSS
A
MFP0
Ground pin for digital circuit.
88
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
89
AVDD
A
MFP0
Power supply for internal analog circuit.
90
VREF
I
MFP0
Voltage reference input for ADC.
83
86
Pin Name
Note: This pin needs to be connected with a 1uF
capacitor.
91
PB.0
M451 SERIES DATASHEET
I/O
MFP0
General purpose digital I/O pin.
EADC_CH0
A
MFP1
EADC analog input.
SPI0_MOSI1
I/O
MFP2
SPI0 2nd MOSI (Master Out, Slave In) pin.
UART2_RXD
I
MFP3
Data receiver input pin for UART2.
I/O
MFP4
Timer2 event counter input / toggle output
DAC
A
MFP5
DAC analog output
EBI_nWRL
O
MFP7
EBI low byte write enable output pin.
INT1
I
MFP8
External interrupt1 input pin.
PB.1
I/O
MFP0
General purpose digital I/O pin.
EADC_CH1
A
MFP1
EADC analog input channel 1.
SPI0_MISO1
I/O
MFP2
SPI0 2nd MISO (Master In, Slave Out) pin.
UART2_TXD
O
MFP3
Data transmitter output pin for UART2.
T3
I/O
MFP4
Timer3 event counter input / toggle output
SC0_RST
O
MFP5
SmartCard reset pin.
PWM0_SYNC_OUT
O
MFP6
PWM0 counter synchronous trigger output pin.
EBI_nWRH
O
MFP7
EBI high byte write enable output pin
PB.2
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 2.
T2
92
93
EADC_CH2
Mar. 04, 2016
Page 68 of 219
Rev.2.05
M451
Pin No.
94
95
Type
MFP*
Description
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin
UART1_RXD
I
MFP4
Data receiver input pin for UART1.
SC0_CD
I
MFP5
SmartCard card detect pin.
UART3_RXD
I
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
T2_EXT
I
MFP11
Timer2 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
EADC_CH3
A
MFP1
EADC analog input channel 3.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
UART1_TXD
O
MFP4
Data transmitter output pin for UART1.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
T0_EXT
I
MFP11
Timer0 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 4.
SPI0_SS
I/O
MFP2
SPI0 slave select pin.
SPI1_SS
I/O
MFP3
SPI1 slave select pin
UART1_nCTS
I
MFP4
Clear to Send input pin for UART1.
ACMP0_N
A
MFP5
Comparator0 negative input pin.
EBI_AD7
I/O
MFP7
EBI address/data bus bit 7.
UART2_TXD
O
MFP9
Data transmitter output pin for UART2. (M45xD/M45xC
Only)
T1_EXT
I
MFP11
Timer1 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
EADC_CH5
A
MFP1
EADC analog input channel 5.
UART1_nRTS
O
MFP4
Request to Send output pin for UART1.
PWM0_CH2
I/O
MFP6
PWM0 output/capture input.
PB.9
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 6. (M45xG/M45xE Only)
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 7. (M45xG/M45xE Only)
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 8.
I/O
MFP0
General purpose digital I/O pin.
PB.3
PB.4
EADC_CH4
96
97
PB.8
EADC_CH6
98
PB.10
EADC_CH7
99
PB.11
EADC_CH8
100
PB.12
Mar. 04, 2016
Page 69 of 219
Rev.2.05
M451 SERIES DATASHEET
Pin Name
M451
Pin No.
Pin Name
EADC_CH9
Type
MFP*
Description
A
MFP1
EADC analog input channel 9.
M451 SERIES DATASHEET
Mar. 04, 2016
Page 70 of 219
Rev.2.05
M451
4.3.4 M451M Series (M051 Pin Compatible) LQFP48 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0.
PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5.
Pin No.
MFP*
Description
I/O
MFP0
General purpose digital I/O pin.
EADC_CH13
A
MFP1
EADC analog input channel 13.
SPI0_MOSI0
I/O
MFP2
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1_MOSI
I/O
MFP3
SPI1 MOSI (Master Out, Slave In) pin.
ACMP0_P2
A
MFP5
Comparator0 positive input pin.
EBI_AD6
I/O
MFP7
EBI address/data bus bit 6.
UART2_RXD
I/O
MFP9
Data receiver input pin for UART2. (M45xD/M45xC Only)
PB.6
I/O
MFP0
General purpose digital I/O pin.
EADC_CH14
A
MFP1
EADC analog input channel 14.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
ACMP0_P1
A
MFP5
Comparator0 positive input pin.
EBI_AD5
I/O
MFP7
EBI address/data bus bit 5.
PB.7
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 15.
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin
ACMP0_P0
A
MFP5
Comparator0 positive input pin.
EBI_AD4
I/O
MFP7
EBI address/data bus bit 4.
STADC
I/O
MFP10
ADC external trigger input. (M45xD/M45xC Only)
4
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
5
PD.0
I/O
MFP0
General purpose digital I/O pin.
SPI1_I2SMCLK
O
MFP2
I2S1 master clock output pin.
UART0_RXD
I
MFP3
Data receiver input pin for UART0.
ACMP1_N
A
MFP5
Comparator1 negative input pin.
INT3
I
MFP8
External interrupt3 input pin.
I/O
MFP11
Timer3 event counter input / toggle output.
(M45xD/M45xC Only)
2
3
PB.5
EADC_CH15
T3
6
AVSS
P
MFP0
Ground pin for analog circuit.
7
PD.1
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 11. (M45xD/M45xC Only)
EADC_CH11
Mar. 04, 2016
Page 71 of 219
Rev.2.05
M451 SERIES DATASHEET
Type
1
Pin Name
M451
Pin No.
8
9
10
Pin Name
M451 SERIES DATASHEET
Type
MFP*
Description
PWM0_SYNC_IN
I
MFP2
PWM0 counter synchronous trigger input pin.
UART0_TXD
O
MFP3
Data transmitter output pin for UART0.
ACMP1_P2
A
MFP5
Comparator1 positive input pin.
T0
I/O
MFP6
Timer0event counter input / toggle output
EBI_nRD
O
MFP7
EBI read enable output pin.
PD.2
I/O
MFP0
General purpose digital I/O pin.
STADC
I
MFP1
ADC external trigger input.
T0_EXT
I
MFP3
Timer0 external counter input
ACMP1_P1
A
MFP5
Comparator1 positive input pin.
PWM0_BRAKE0
I
MFP6
PWM0 break input 0
EBI_nWR
O
MFP7
EBI write enable output pin.
INT0
I
MFP8
External interrupt0 input pin.
PD.3
I/O
MFP0
General purpose digital I/O pin.
T2
I/O
MFP1
Timer2 event counter input / toggle output
T1_EXT
I
MFP3
Timer1 external counter input
ACMP1_P0
A
MFP5
Comparator1 positive input pin.
PWM0_BRAKE1
I
MFP6
PWM0 break input 1
EBI_MCLK
O
MFP7
EBI external clock output pin
INT1
I
MFP8
External interrupt1 input pin.
PD.4
I/O
MFP0
General purpose digital I/O pin.
SPI1_CLK
I/O
MFP2
SPI1 serial clock pin
I2C0_SDA
I/O
MFP3
I2C0 data input/output pin.
I
MFP5
PWM0 break input 0
T0
I/O
MFP6
Timer0event counter input / toggle output
PD.5
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP1
Clock Out
SPI1_MISO
I/O
MFP2
SPI1 MISO (Master In, Slave Out) pin.
I2C0_SCL
I/O
MFP3
I2C0 clock pin.
I
MFP5
PWM0 break input 1
T1
I/O
MFP6
Timer1 event counter input / toggle output
PE.3
I/O
MFP0
General purpose digital I/O pin.
SPI1_MOSI
I/O
MFP2
SPI1 MOSI (Master Out, Slave In) pin.
PWM0_CH3
I/O
MFP6
PWM0 output/capture input.
PD.6
I/O
MFP0
General purpose digital I/O pin.
PWM0_BRAKE0
11
PWM0_BRAKE1
12
13
Mar. 04, 2016
Page 72 of 219
Rev.2.05
M451
Pin No.
14
Pin Name
Type
MFP*
Description
CLKO
O
MFP1
Clock Out
SPI1_SS
I/O
MFP2
SPI1 slave select pin
UART0_RXD
I
MFP3
Data receiver input pin for UART0.
ACMP0_O
O
MFP5
Comparator0 output .
PWM0_CH5
I/O
MFP6
PWM0 output/capture input.
EBI_nWR
O
MFP7
EBI write enable output pin.
PD.7
I/O
MFP0
General purpose digital I/O pin.
I
MFP3
PWM0 counter synchronous trigger input pin.
T1
I/O
MFP4
Timer1 event counter input / toggle output
ACMP0_O
O
MFP5
Comparator0 output .
PWM0_CH5
I/O
MFP6
PWM0 output/capture input.
EBI_nRD
O
MFP7
EBI read enable output pin.
PF.3
I/O
MFP0
General purpose digital I/O pin.
XT1_OUT
O
MFP1
External 4~20 MHz (high speed) crystal output pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
PF.4
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 4~20 MHz (high speed) crystal input pin.
I/O
MFP3
I2C1 data input/output pin.
PWM0_SYNC_IN
15
16
XT1_IN
I2C1_SDA
17
VSS
A
MFP0
Ground pin for digital circuit.
18
LDO_CAP
A
MFP0
LDO output pin.
19
PC.0
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
I
MFP3
Clear to Send input pin for UART2.
PWM0_CH0
I/O
MFP6
PWM0 output/capture input.
EBI_AD8
I/O
MFP7
EBI address/data bus bit 8.
INT2
I
MFP8
External interrupt2 input pin.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
T3_EXT
I
MFP11
Timer3 external counter input. (M45xD/M45xC Only)
PC.1
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP1
Clock Out
STDAC
I
MFP2
DAC external trigger input.
UART2_nRTS
O
MFP3
Request to Send output pin for UART2.
PWM0_CH1
I/O
MFP6
PWM0 output/capture input.
UART2_nCTS
20
Mar. 04, 2016
Page 73 of 219
Rev.2.05
M451 SERIES DATASHEET
Note: This pin needs to be connected with a 1uF
capacitor.
M451
Pin No.
21
22
23
24
M451 SERIES DATASHEET
25
26
Pin Name
Type
MFP*
Description
EBI_AD9
I/O
MFP7
EBI address/data bus bit 9.
UART3_RXD
I/O
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
PC.2
I/O
MFP0
General purpose digital I/O pin.
SPI2_SS
I
MFP2
SPI2 slave select pin. (M45xG/M45xE Only)
UART2_TXD
O
MFP3
Data transmitter output pin for UART2.
ACMP1_O
O
MFP5
Comparator1 output .
PWM0_CH2
I/O
MFP6
PWM0 output/capture input.
EBI_AD10
I/O
MFP7
EBI address/data bus bit 10.
PC.3
I/O
MFP0
General purpose digital I/O pin.
SPI2_MOSI
I/O
MFP2
SPI2 MOSI (Master Out, Slave In) pin. (M45xG/M45xE
Only)
UART2_RXD
I
MFP3
Data receiver input pin for UART2.
PWM0_CH3
I/O
MFP6
PWM0 output/capture input.
EBI_AD11
I/O
MFP7
EBI address/data bus bit 11.
PC.4
I/O
MFP0
General purpose digital I/O pin.
SPI2_MISO
I/O
MFP2
SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE
Only)
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
PWM0_CH4
I/O
MFP6
PWM0 output/capture input.
EBI_AD12
I/O
MFP7
EBI address/data bus bit 12.
PE.0
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
T2_EXT
I
MFP4
Timer2 external counter input
SC0_CD
I
MFP5
SmartCard card detect pin.
PWM0_CH0
I/O
MFP6
PWM0 output/capture input.
EBI_nCS1
O
MFP7
EBI chip select 1 enable output pin.
INT4
I
MFP8
External interrupt4 input pin.
PC.5
I/O
MFP0
General purpose digital I/O pin.
SPI2_I2SMCLK
O
MFP2
I2S2 master clock output pin. (M45xG/M45xE Only)
PWM0_CH5
I/O
MFP6
PWM0 output/capture input.
EBI_AD13
I/O
MFP7
EBI address/data bus bit 13.
PC.6
I/O
MFP0
General purpose digital I/O pin.
I2C1_SMBAL
O
MFP3
I2C1 SMBus SMBALTER# pin
ACMP1_O
O
MFP5
Comparator1 output .
Mar. 04, 2016
Page 74 of 219
Rev.2.05
M451
Pin No.
27
Pin Name
MFP*
Description
PWM1_CH0
I/O
MFP6
PWM1 output/capture input.
EBI_AD14
I/O
MFP7
EBI address/data bus bit 14.
UART0_TXD
O
MFP9
Data transmitter output pin for UART0. (M45xD/M45xC
Only)
PC.7
I/O
MFP0
General purpose digital I/O pin.
I2C1_SMBSUS
O
MFP3
I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)
PWM1_CH1
I/O
MFP6
PWM1 output/capture input.
EBI_AD15
I/O
MFP7
EBI address/data bus bit 15.
I
MFP9
Data receiver input pin for UART0. (M45xD/M45xC Only)
PE.4
I/O
MFP0
General purpose digital I/O pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
SC0_PWR
O
MFP5
SmartCard power pin.
PWM1_BRAKE0
I
MFP6
PWM1 break input 0
EBI_nCS0
O
MFP7
EBI chip select 0 enable output pin.
INT0
I
MFP8
External interrupt0 input pin.
PE.5
I/O
MFP0
General purpose digital I/O pin.
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
SC0_RST
O
MFP5
SmartCard reset pin.
PWM1_BRAKE1
I
MFP6
PWM1 break input 1
EBI_ALE
O
MFP7
EBI address latch enable output pin.
INT1
I
MFP8
External interrupt1 input pin.
PF.5
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
Serial wired debugger clock pin
PF.6
I/O
MFP0
General purpose digital I/O pin.
ICE_DAT
I/O
MFP1
Serial wired debugger data pin
PA.7
I/O
MFP0
General purpose digital I/O pin.
SPI1_CLK
I/O
MFP2
SPI1 serial clock pin
T0_EXT
I
MFP3
Timer0 external counter input
EBI_AD7
I/O
MFP7
EBI address/data bus bit 7.
PA.6
I/O
MFP0
General purpose digital I/O pin.
SPI1_MISO
I/O
MFP2
SPI1 MISO (Master In, Slave Out) pin.
T1_EXT
I
MFP3
Timer1 external counter input
EBI_AD6
I/O
MFP7
EBI address/data bus bit 6.
PA.5
I/O
MFP0
General purpose digital I/O pin.
SPI1_MOSI
I/O
MFP2
SPI1 MOSI (Master Out, Slave In) pin.
UART0_RXD
28
29
30
ICE_CLK
31
32
33
34
Mar. 04, 2016
Page 75 of 219
M451 SERIES DATASHEET
Type
Rev.2.05
M451
Pin No.
35
36
37
38
M451 SERIES DATASHEET
39
40
Pin Name
Type
MFP*
Description
T2_EXT
I
MFP3
Timer2 external counter input
EBI_AD5
I/O
MFP7
EBI address/data bus bit 5.
PA.4
I/O
MFP0
General purpose digital I/O pin.
SPI1_SS
I/O
MFP2
SPI1 slave select pin
EBI_AD4
I/O
MFP7
EBI address/data bus bit 4.
PE.1
I/O
MFP0
General purpose digital I/O pin.
T3_EXT
I
MFP3
Timer3 external counter input
SC0_CD
I
MFP5
SmartCard card detect pin.
PWM0_CH1
I/O
MFP6
PWM0 output/capture input.
PA.3
I/O
MFP0
General purpose digital I/O pin.
UART0_RXD
I
MFP2
Data receiver input pin for UART0.
UART0_nRTS
O
MFP3
Request to Send output pin for UART0.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
SC0_PWR
O
MFP5
SmartCard power pin.
PWM1_CH2
I/O
MFP6
PWM1 output/capture input.
EBI_AD3
I/O
MFP7
EBI address/data bus bit 3.
PA.2
I/O
MFP0
General purpose digital I/O pin.
UART0_TXD
O
MFP2
Data transmitter output pin for UART0.
UART0_nCTS
I
MFP3
Clear to Send input pin for UART0.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
SC0_RST
O
MFP5
SmartCard reset pin.
PWM1_CH3
I/O
MFP6
PWM1 output/capture input.
EBI_AD2
I/O
MFP7
EBI address/data bus bit 2.
PA.1
I/O
MFP0
General purpose digital I/O pin.
UART1_nRTS
O
MFP1
Request to Send output pin for UART1.
UART1_RXD
I
MFP3
Data receiver input pin for UART1.
SC0_DAT
I/O
MFP5
SmartCard data pin.
PWM1_CH4
I/O
MFP6
PWM1 output/capture input.
EBI_AD1
I/O
MFP7
EBI address/data bus bit 1.
STADC
I/O
MFP10
ADC external trigger input. (M45xD/M45xC Only)
PA.0
I/O
MFP0
General purpose digital I/O pin.
UART1_nCTS
I
MFP1
Clear to Send input pin for UART1.
UART1_TXD
O
MFP3
Data transmitter output pin for UART1.
SC0_CLK
O
MFP5
SmartCard clock pin.
Mar. 04, 2016
Page 76 of 219
Rev.2.05
M451
Pin No.
Pin Name
MFP*
Description
PWM1_CH5
I/O
MFP6
PWM1 output/capture input.
EBI_AD0
I/O
MFP7
EBI address/data bus bit 0.
INT0
I
MFP8
External interrupt0 input pin.
SPI1_I2SMCLK
O
MFP9
I2S1 master clock output pin. (M45xD/M45xC Only)
41
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
42
AVDD
A
MFP0
Power supply for internal analog circuit.
43
PB.0
I/O
MFP0
General purpose digital I/O pin.
EADC_CH0
A
MFP1
EADC analog input.
SPI0_MOSI1
I/O
MFP2
SPI0 2nd MOSI (Master Out, Slave In) pin.
UART2_RXD
I
MFP3
Data receiver input pin for UART2.
I/O
MFP4
Timer2 event counter input / toggle output
DAC
A
MFP5
DAC analog output
EBI_nWRL
O
MFP7
EBI low byte write enable output pin.
INT1
I
MFP8
External interrupt1 input pin.
PB.1
I/O
MFP0
General purpose digital I/O pin.
EADC_CH1
A
MFP1
EADC analog input channel 1.
SPI0_MISO1
I/O
MFP2
SPI0 2nd MISO (Master In, Slave Out) pin.
UART2_TXD
O
MFP3
Data transmitter output pin for UART2.
T3
I/O
MFP4
Timer3 event counter input / toggle output
SC0_RST
O
MFP5
SmartCard reset pin.
PWM0_SYNC_OUT
O
MFP6
PWM0 counter synchronous trigger output pin.
EBI_nWRH
O
MFP7
EBI high byte write enable output pin
PB.2
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 2.
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin
UART1_RXD
I
MFP4
Data receiver input pin for UART1.
SC0_CD
I
MFP5
SmartCard card detect pin.
UART3_RXD
I
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
T2_EXT
I
MFP11
Timer2 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
EADC_CH3
A
MFP1
EADC analog input channel 3.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
T2
44
45
EADC_CH2
46
PB.3
Mar. 04, 2016
Page 77 of 219
Rev.2.05
M451 SERIES DATASHEET
Type
M451
Pin No.
47
Pin Name
Type
MFP*
Description
UART1_TXD
O
MFP4
Data transmitter output pin for UART1.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
T0_EXT
I
MFP11
Timer0 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 4.
SPI0_SS
I/O
MFP2
SPI0 slave select pin.
SPI1_SS
I/O
MFP3
SPI1 slave select pin
UART1_nCTS
I
MFP4
Clear to Send input pin for UART1.
ACMP0_N
A
MFP5
Comparator0 negative input pin.
EBI_AD7
I/O
MFP7
EBI address/data bus bit 7.
UART2_TXD
O
MFP9
Data transmitter output pin for UART2. (M45xD/M45xC
Only)
T1_EXT
I
MFP11
Timer1 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
EADC_CH5
A
MFP1
EADC analog input channel 5.
UART1_nRTS
O
MFP4
Request to Send output pin for UART1.
PWM0_CH2
I/O
MFP6
PWM0 output/capture input.
PB.4
EADC_CH4
48
PB.8
M451 SERIES DATASHEET
Mar. 04, 2016
Page 78 of 219
Rev.2.05
M451
4.3.5 M452 USB Series LQFP48 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0.
PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5.
Pin No.
MFP*
Description
I/O
MFP0
General purpose digital I/O pin.
EADC_CH13
A
MFP1
EADC analog input channel 13.
SPI0_MOSI0
I/O
MFP2
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1_MOSI
I/O
MFP3
SPI1 MOSI (Master Out, Slave In) pin.
ACMP0_P2
A
MFP5
Comparator0 positive input pin.
EBI_AD6
I/O
MFP7
EBI address/data bus bit 6.
UART2_RXD
I/O
MFP9
Data receiver input pin for UART2. (M45xD/M45xC Only)
PB.6
I/O
MFP0
General purpose digital I/O pin.
EADC_CH14
A
MFP1
EADC analog input channel 14.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
ACMP0_P1
A
MFP5
Comparator0 positive input pin.
EBI_AD5
I/O
MFP7
EBI address/data bus bit 5.
PB.7
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 15.
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin
ACMP0_P0
A
MFP5
Comparator0 positive input pin.
EBI_AD4
I/O
MFP7
EBI address/data bus bit 4.
STADC
I/O
MFP10
ADC external trigger input. (M45xD/M45xC Only)
4
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
5
PD.0
I/O
MFP0
General purpose digital I/O pin.
EADC_CH6
A
MFP1
EADC analog input channel 6. (M45xD/M45xC Only)
SPI1_I2SMCLK
O
MFP2
I2S1 master clock output pin.
UART0_RXD
I
MFP3
Data receiver input pin for UART0.
ACMP1_N
A
MFP5
Comparator1 negative input pin.
INT3
I
MFP8
External interrupt3 input pin.
I/O
MFP11
Timer3 event counter input / toggle output.
(M45xD/M45xC Only)
2
3
PB.5
EADC_CH15
T3
6
AVSS
P
MFP0
Ground pin for analog circuit.
7
PD.1
I/O
MFP0
General purpose digital I/O pin.
Mar. 04, 2016
Page 79 of 219
Rev.2.05
M451 SERIES DATASHEET
Type
1
Pin Name
M451
Pin No.
8
9
Pin Name
M451 SERIES DATASHEET
Type
MFP*
Description
EADC_CH11
A
MFP1
EADC analog input channel 11. (M45xD/M45xC Only)
PWM0_SYNC_IN
I
MFP2
PWM0 counter synchronous trigger input pin.
UART0_TXD
O
MFP3
Data transmitter output pin for UART0.
ACMP1_P2
A
MFP5
Comparator1 positive input pin.
T0
I/O
MFP6
Timer0event counter input / toggle output
EBI_nRD
O
MFP7
EBI read enable output pin.
PD.2
I/O
MFP0
General purpose digital I/O pin.
STADC
I
MFP1
ADC external trigger input.
T0_EXT
I
MFP3
Timer0 external counter input
ACMP1_P1
A
MFP5
Comparator1 positive input pin.
PWM0_BRAKE0
I
MFP6
PWM0 break input 0
EBI_nWR
O
MFP7
EBI write enable output pin.
INT0
I
MFP8
External interrupt0 input pin.
PD.3
I/O
MFP0
General purpose digital I/O pin.
T2
I/O
MFP1
Timer2 event counter input / toggle output
T1_EXT
I
MFP3
Timer1 external counter input
ACMP1_P0
A
MFP5
Comparator1 positive input pin.
PWM0_BRAKE1
I
MFP6
PWM0 break input 1
EBI_MCLK
O
MFP7
EBI external clock output pin
INT1
I
MFP8
External interrupt1 input pin.
MFP0
Power supply by batteries for RTC and PF.0~PF.2.
10
VBAT
11
PF.0
I/O
MFP0
General purpose digital I/O pin.
X32_OUT
O
MFP1
External 32.768 kHZ (low speed) crystal output pin.
INT5
I
MFP8
External interrupt5 input pin.
PF.1
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 32.768 kHZ (low speed) crystal input pin.
PF.2
I/O
MFP0
General purpose digital I/O pin.
TAMPER
I/O
MFP1
TAMPER detector loop pin
PD.7
I/O
MFP0
General purpose digital I/O pin.
I
MFP3
PWM0 counter synchronous trigger input pin.
T1
I/O
MFP4
Timer1 event counter input / toggle output
ACMP0_O
O
MFP5
Comparator0 output .
PWM0_CH5
I/O
MFP6
PWM0 output/capture input.
EBI_nRD
O
MFP7
EBI read enable output pin.
12
X32_IN
13
14
PWM0_SYNC_IN
Mar. 04, 2016
Page 80 of 219
Rev.2.05
M451
Pin No.
15
16
Pin Name
Type
MFP*
Description
PF.3
I/O
MFP0
General purpose digital I/O pin.
XT1_OUT
O
MFP1
External 4~20 MHz (high speed) crystal output pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
PF.4
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 4~20 MHz (high speed) crystal input pin.
I/O
MFP3
I2C1 data input/output pin.
XT1_IN
I2C1_SDA
17
VSS
A
MFP0
Ground pin for digital circuit.
18
LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with a 1uF
capacitor.
19
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
I
MFP3
Clear to Send input pin for UART2.
PWM0_CH0
I/O
MFP6
PWM0 output/capture input.
EBI_AD8
I/O
MFP7
EBI address/data bus bit 8.
INT2
I
MFP8
External interrupt2 input pin.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
T3_EXT
I
MFP11
Timer3 external counter input. (M45xD/M45xC Only)
PC.1
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP1
Clock Out
STDAC
I
MFP2
DAC external trigger input.
UART2_nRTS
O
MFP3
Request to Send output pin for UART2.
PWM0_CH1
I/O
MFP6
PWM0 output/capture input.
EBI_AD9
I/O
MFP7
EBI address/data bus bit 9.
UART3_RXD
I/O
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
PC.2
I/O
MFP0
General purpose digital I/O pin.
SPI2_SS
I
MFP2
SPI2 slave select pin. (M45xG/M45xE Only)
UART2_TXD
O
MFP3
Data transmitter output pin for UART2.
ACMP1_O
O
MFP5
Comparator1 output .
PWM0_CH2
I/O
MFP6
PWM0 output/capture input.
EBI_AD10
I/O
MFP7
EBI address/data bus bit 10.
PC.3
I/O
MFP0
General purpose digital I/O pin.
SPI2_MOSI
I/O
MFP2
SPI2 MOSI (Master Out, Slave In) pin. (M45xG/M45xE
Only)
I
MFP3
Data receiver input pin for UART2.
UART2_nCTS
20
21
22
UART2_RXD
Mar. 04, 2016
Page 81 of 219
Rev.2.05
M451 SERIES DATASHEET
PC.0
M451
Pin No.
Pin Name
Type
MFP*
Description
I
MFP4
USB external VBUS regulator status pin. (M45xG/M45xE
Only)
PWM0_CH3
I/O
MFP6
PWM0 output/capture input.
EBI_AD11
I/O
MFP7
EBI address/data bus bit 11.
PC.4
I/O
MFP0
General purpose digital I/O pin.
SPI2_MISO
I/O
MFP2
SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE
Only)
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
USB_VBUS_EN
O
MFP4
USB external VBUS regulator enable pin.
(M45xG/M45xE Only)
PWM0_CH4
I/O
MFP6
PWM0 output/capture input.
EBI_AD12
I/O
MFP7
EBI address/data bus bit 12.
PE.0
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
T2_EXT
I
MFP4
Timer2 external counter input
SC0_CD
I
MFP5
SmartCard card detect pin.
PWM0_CH0
I/O
MFP6
PWM0 output/capture input.
EBI_nCS1
O
MFP7
EBI chip select 1 enable output pin.
INT4
I
MFP8
External interrupt4 input pin.
PF.5
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
Serial wired debugger clock pin
PF.6
I/O
MFP0
General purpose digital I/O pin.
ICE_DAT
I/O
MFP1
Serial wired debugger data pin
PE.10
I/O
MFP0
General purpose digital I/O pin.
SPI1_MISO
I/O
MFP1
SPI1 MISO (Master In, Slave Out) pin.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
UART1_nCTS
I
MFP3
Clear to Send input pin for UART1.
I2C0_SMBAL
O
MFP4
I2C0 SMBus SMBALTER# pin
SC0_DAT
I/O
MFP5
SmartCard data pin.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
I2C1_SCL
I/O
MFP11
I2C1 clock pin. (M45xD/M45xC Only)
PE.11
I/O
MFP0
General purpose digital I/O pin.
SPI1_MOSI
I/O
MFP1
SPI1 MOSI (Master Out, Slave In) pin.
SPI0_MOSI0
I/O
MFP2
SPI0 1st MOSI (Master Out, Slave In) pin.
USB_VBUS_ST
23
24
25
M451 SERIES DATASHEET
ICE_CLK
26
27
28
Mar. 04, 2016
Page 82 of 219
Rev.2.05
M451
Pin No.
29
30
Pin Name
Type
MFP*
Description
UART1_nRTS
O
MFP3
Request to Send output pin for UART1.
I2C0_SMBSUS
O
MFP4
I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)
SC0_CLK
O
MFP5
SmartCard clock pin.
UART3_RXD
I
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
I2C1_SDA
I/O
MFP11
I2C1 data input/output pin. (M45xD/M45xC Only)
PE.12
I/O
MFP0
General purpose digital I/O pin.
SPI1_SS
I/O
MFP1
SPI1 slave select pin
SPI0_SS
I/O
MFP2
SPI0 slave select pin.
UART1_TXD
O
MFP3
Data transmitter output pin for UART1.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
PE.13
I/O
MFP0
General purpose digital I/O pin.
SPI1_CLK
I/O
MFP1
SPI1 serial clock pin
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
I
MFP3
Data receiver input pin for UART1.
I/O
MFP4
I2C0 data input/output pin.
UART1_RXD
I2C0_SDA
VDDIO
A
MFP0
Power supply for PE.10~PE.13.
32
USB_VBUS
A
MFP0
Power supply from USB* host or HUB.
33
USB_D-
I
MFP0
USB differential signal D-.
34
USB_D+
I
MFP0
USB differential signal D+.
35
PF.7
I/O
MFP0
General purpose digital I/O pin. (M45xD/M45xC Only)
USB_ID
I
MFP0
USB identification. (M45xG/M45xE Only)
USB_VDD33_CAP
A
MFP0
Internal power regulator output 3.3V decoupling pin.
36
Note: This pin needs to be connected with a 1uF
capacitor.
37
38
PA.3
I/O
MFP0
General purpose digital I/O pin.
USB_VBUS_ST
I
MFP1
USB external VBUS regulator status pin. (M45xG/M45xE
Only)
UART0_RXD
I
MFP2
Data receiver input pin for UART0.
UART0_nRTS
O
MFP3
Request to Send output pin for UART0.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
SC0_PWR
O
MFP5
SmartCard power pin.
PWM1_CH2
I/O
MFP6
PWM1 output/capture input.
EBI_AD3
I/O
MFP7
EBI address/data bus bit 3.
PA.2
I/O
MFP0
General purpose digital I/O pin.
USB_VBUS_EN
O
MFP1
USB external VBUS regulator enable pin.
(M45xG/M45xE Only)
Mar. 04, 2016
Page 83 of 219
Rev.2.05
M451 SERIES DATASHEET
31
M451
Pin No.
Type
MFP*
Description
UART0_TXD
O
MFP2
Data transmitter output pin for UART0.
UART0_nCTS
I
MFP3
Clear to Send input pin for UART0.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
SC0_RST
O
MFP5
SmartCard reset pin.
PWM1_CH3
I/O
MFP6
PWM1 output/capture input.
EBI_AD2
I/O
MFP7
EBI address/data bus bit 2.
PA.1
I/O
MFP0
General purpose digital I/O pin.
UART1_nRTS
O
MFP1
Request to Send output pin for UART1.
UART1_RXD
I
MFP3
Data receiver input pin for UART1.
SC0_DAT
I/O
MFP5
SmartCard data pin.
PWM1_CH4
I/O
MFP6
PWM1 output/capture input.
EBI_AD1
I/O
MFP7
EBI address/data bus bit 1.
STADC
I/O
MFP10
ADC external trigger input. (M45xD/M45xC Only)
PA.0
I/O
MFP0
General purpose digital I/O pin.
UART1_nCTS
I
MFP1
Clear to Send input pin for UART1.
UART1_TXD
O
MFP3
Data transmitter output pin for UART1.
SC0_CLK
O
MFP5
SmartCard clock pin.
PWM1_CH5
I/O
MFP6
PWM1 output/capture input.
EBI_AD0
I/O
MFP7
EBI address/data bus bit 0.
INT0
I
MFP8
External interrupt0 input pin.
SPI1_I2SMCLK
O
MFP9
I2S1 master clock output pin. (M45xD/M45xC Only)
41
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
42
AVDD
A
MFP0
Power supply for internal analog circuit.
43
VREF
I
MFP0
Voltage reference input for ADC.
39
40
Pin Name
M451 SERIES DATASHEET
Note: This pin needs to be connected with a 1uF
capacitor.
44
PB.0
I/O
MFP0
General purpose digital I/O pin.
EADC_CH0
A
MFP1
EADC analog input.
SPI0_MOSI1
I/O
MFP2
SPI0 2nd MOSI (Master Out, Slave In) pin.
UART2_RXD
I
MFP3
Data receiver input pin for UART2.
I/O
MFP4
Timer2 event counter input / toggle output
DAC
A
MFP5
DAC analog output
EBI_nWRL
O
MFP7
EBI low byte write enable output pin.
INT1
I
MFP8
External interrupt1 input pin.
PB.1
I/O
MFP0
General purpose digital I/O pin.
T2
45
Mar. 04, 2016
Page 84 of 219
Rev.2.05
M451
Pin No.
46
Pin Name
MFP*
Description
EADC_CH1
A
MFP1
EADC analog input channel 1.
SPI0_MISO1
I/O
MFP2
SPI0 2nd MISO (Master In, Slave Out) pin.
UART2_TXD
O
MFP3
Data transmitter output pin for UART2.
T3
I/O
MFP4
Timer3 event counter input / toggle output
SC0_RST
O
MFP5
SmartCard reset pin.
PWM0_SYNC_OUT
O
MFP6
PWM0 counter synchronous trigger output pin.
EBI_nWRH
O
MFP7
EBI high byte write enable output pin
PB.2
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 2.
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin
UART1_RXD
I
MFP4
Data receiver input pin for UART1.
SC0_CD
I
MFP5
SmartCard card detect pin.
UART3_RXD
I
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
T2_EXT
I
MFP11
Timer2 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
EADC_CH3
A
MFP1
EADC analog input channel 3.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
UART1_TXD
O
MFP4
Data transmitter output pin for UART1.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
T0_EXT
I
MFP11
Timer0 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 4.
SPI0_SS
I/O
MFP2
SPI0 slave select pin.
SPI1_SS
I/O
MFP3
SPI1 slave select pin
UART1_nCTS
I
MFP4
Clear to Send input pin for UART1.
ACMP0_N
A
MFP5
Comparator0 negative input pin.
EBI_AD7
I/O
MFP7
EBI address/data bus bit 7.
UART2_TXD
O
MFP9
Data transmitter output pin for UART2. (M45xD/M45xC
Only)
T1_EXT
I
MFP11
Timer1 external counter input. (M45xD/M45xC Only)
EADC_CH2
47
48
PB.3
PB.4
EADC_CH4
Mar. 04, 2016
Page 85 of 219
Rev.2.05
M451 SERIES DATASHEET
Type
M451
4.3.6 M452 USB Series LQFP64 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0.
PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5.
Pin No.
Type
MFP*
Description
I/O
MFP0
General purpose digital I/O pin.
EADC_CH12
A
MFP1
EADC analog input channel 12.
ACMP0_P3
A
MFP5
Comparator0 positive input pin.
EBI_nCS1
O
MFP7
EBI chip select 1 enable output pin.
PB.5
I/O
MFP0
General purpose digital I/O pin.
EADC_CH13
A
MFP1
EADC analog input channel 13.
SPI0_MOSI0
I/O
MFP2
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1_MOSI
I/O
MFP3
SPI1 MOSI (Master Out, Slave In) pin.
ACMP0_P2
A
MFP5
Comparator0 positive input pin.
EBI_AD6
I/O
MFP7
EBI address/data bus bit 6.
UART2_RXD
I/O
MFP9
Data receiver input pin for UART2. (M45xD/M45xC Only)
PB.6
I/O
MFP0
General purpose digital I/O pin.
EADC_CH14
A
MFP1
EADC analog input channel 14.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
ACMP0_P1
A
MFP5
Comparator0 positive input pin.
EBI_AD5
I/O
MFP7
EBI address/data bus bit 5.
PB.7
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 15.
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin
ACMP0_P0
A
MFP5
Comparator0 positive input pin.
EBI_AD4
I/O
MFP7
EBI address/data bus bit 4.
STADC
I/O
MFP10
ADC external trigger input. (M45xD/M45xC Only)
5
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
6
PD.0
I/O
MFP0
General purpose digital I/O pin.
EADC_CH6
A
MFP1
EADC analog input channel 6. (M45xD/M45xC Only)
SPI1_I2SMCLK
O
MFP2
I2S1 master clock output pin.
UART0_RXD
I
MFP3
Data receiver input pin for UART0.
ACMP1_N
A
MFP5
Comparator1 negative input pin.
1
2
3
M451 SERIES DATASHEET
4
Pin Name
PB.15
EADC_CH15
Mar. 04, 2016
Page 86 of 219
Rev.2.05
M451
Pin No.
Pin Name
INT3
T3
Type
MFP*
Description
I
MFP8
External interrupt3 input pin.
I/O
MFP11
Timer3 event counter input / toggle output.
(M45xD/M45xC Only)
AVSS
P
MFP0
Ground pin for analog circuit.
8
PD.8
I/O
MFP0
General purpose digital I/O pin.
EADC_CH7
A
MFP1
EADC analog input channel 7. (M45xD/M45xC Only)
EBI_nCS0
O
MFP7
EBI chip select 0 enable output pin.
PD.9
I/O
MFP0
General purpose digital I/O pin.
EADC_CH10
A
MFP1
EADC analog input channel 10. (M45xD/M45xC Only)
ACMP1_P3
A
MFP5
Comparator1 positive input pin.
EBI_ALE
O
MFP7
EBI address latch enable output pin.
PD.1
I/O
MFP0
General purpose digital I/O pin.
EADC_CH11
A
MFP1
EADC analog input channel 11. (M45xD/M45xC Only)
PWM0_SYNC_IN
I
MFP2
PWM0 counter synchronous trigger input pin.
UART0_TXD
O
MFP3
Data transmitter output pin for UART0.
ACMP1_P2
A
MFP5
Comparator1 positive input pin.
T0
I/O
MFP6
Timer0event counter input / toggle output
EBI_nRD
O
MFP7
EBI read enable output pin.
PD.2
I/O
MFP0
General purpose digital I/O pin.
STADC
I
MFP1
ADC external trigger input.
T0_EXT
I
MFP3
Timer0 external counter input
ACMP1_P1
A
MFP5
Comparator1 positive input pin.
PWM0_BRAKE0
I
MFP6
PWM0 break input 0
EBI_nWR
O
MFP7
EBI write enable output pin.
INT0
I
MFP8
External interrupt0 input pin.
PD.3
I/O
MFP0
General purpose digital I/O pin.
T2
I/O
MFP1
Timer2 event counter input / toggle output
T1_EXT
I
MFP3
Timer1 external counter input
ACMP1_P0
A
MFP5
Comparator1 positive input pin.
PWM0_BRAKE1
I
MFP6
PWM0 break input 1
EBI_MCLK
O
MFP7
EBI external clock output pin
INT1
I
MFP8
External interrupt1 input pin.
MFP0
Power supply by batteries for RTC and PF.0~PF.2.
9
10
11
12
M451 SERIES DATASHEET
7
13
VBAT
14
PF.0
I/O
MFP0
General purpose digital I/O pin.
X32_OUT
O
MFP1
External 32.768 kHZ (low speed) crystal output pin.
Mar. 04, 2016
Page 87 of 219
Rev.2.05
M451
Pin No.
15
Pin Name
Type
MFP*
Description
INT5
I
MFP8
External interrupt5 input pin.
PF.1
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 32.768 kHZ (low speed) crystal input pin.
PF.2
I/O
MFP0
General purpose digital I/O pin.
TAMPER
I/O
MFP1
TAMPER detector loop pin
PD.12
I/O
MFP0
General purpose digital I/O pin.
SPI2_SS
I
MFP2
SPI2 slave select pin. (M45xG/M45xE Only)
UART3_TXD
O
MFP3
Data transmitter output pin for UART3.
PWM1_CH0
I/O
MFP6
PWM1 output/capture input.
EBI_ADR16
O
MFP7
EBI address bus bit 16.
PD.13
I/O
MFP0
General purpose digital I/O pin.
SPI2_MOSI
I/O
MFP2
SPI2 MOSI (Master Out, Slave In) pin. (M45xG/M45xE
Only)
UART3_RXD
I
MFP3
Data receiver input pin for UART3.
PWM1_CH1
I/O
MFP6
PWM1 output/capture input.
EBI_ADR17
O
MFP7
EBI address bus bit 17.
PD.14
I/O
MFP0
General purpose digital I/O pin.
SPI2_MISO
I/O
MFP2
SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE
Only)
I
MFP3
Clear to Send input pin for UART3.
PWM1_CH2
I/O
MFP6
PWM1 output/capture input.
EBI_ADR18
O
MFP7
EBI address bus bit 18.
PD.15
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
UART3_nRTS
O
MFP3
Request to Send output pin for UART3.
PWM1_CH3
I/O
MFP6
PWM1 output/capture input.
EBI_ADR19
O
MFP7
EBI address bus bit 19.
PD.7
I/O
MFP0
General purpose digital I/O pin.
I
MFP3
PWM0 counter synchronous trigger input pin.
T1
I/O
MFP4
Timer1 event counter input / toggle output
ACMP0_O
O
MFP5
Comparator0 output .
PWM0_CH5
I/O
MFP6
PWM0 output/capture input.
EBI_nRD
O
MFP7
EBI read enable output pin.
PF.3
I/O
MFP0
General purpose digital I/O pin.
XT1_OUT
O
MFP1
External 4~20 MHz (high speed) crystal output pin.
X32_IN
16
17
18
19
UART3_nCTS
M451 SERIES DATASHEET
20
21
PWM0_SYNC_IN
22
Mar. 04, 2016
Page 88 of 219
Rev.2.05
M451
Pin No.
23
Pin Name
Type
MFP*
Description
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
PF.4
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 4~20 MHz (high speed) crystal input pin.
I/O
MFP3
I2C1 data input/output pin.
XT1_IN
I2C1_SDA
24
VSS
A
MFP0
Ground pin for digital circuit.
25
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
26
LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with a 1uF
capacitor.
27
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
I
MFP3
Clear to Send input pin for UART2.
PWM0_CH0
I/O
MFP6
PWM0 output/capture input.
EBI_AD8
I/O
MFP7
EBI address/data bus bit 8.
INT2
I
MFP8
External interrupt2 input pin.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
T3_EXT
I
MFP11
Timer3 external counter input. (M45xD/M45xC Only)
PC.1
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP1
Clock Out
STDAC
I
MFP2
DAC external trigger input.
UART2_nRTS
O
MFP3
Request to Send output pin for UART2.
PWM0_CH1
I/O
MFP6
PWM0 output/capture input.
EBI_AD9
I/O
MFP7
EBI address/data bus bit 9.
UART3_RXD
I/O
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
PC.2
I/O
MFP0
General purpose digital I/O pin.
SPI2_SS
I
MFP2
SPI2 slave select pin. (M45xG/M45xE Only)
UART2_TXD
O
MFP3
Data transmitter output pin for UART2.
ACMP1_O
O
MFP5
Comparator1 output .
PWM0_CH2
I/O
MFP6
PWM0 output/capture input.
EBI_AD10
I/O
MFP7
EBI address/data bus bit 10.
PC.3
I/O
MFP0
General purpose digital I/O pin.
SPI2_MOSI
I/O
MFP2
SPI2 MOSI (Master Out, Slave In) pin. (M45xG/M45xE
Only)
UART2_RXD
I
MFP3
Data receiver input pin for UART2.
USB_VBUS_ST
I
MFP4
USB external VBUS regulator status pin. (M45xG/M45xE
UART2_nCTS
28
29
30
Mar. 04, 2016
Page 89 of 219
Rev.2.05
M451 SERIES DATASHEET
PC.0
M451
Pin No.
Pin Name
Type
MFP*
Description
Only)
31
32
33
M451 SERIES DATASHEET
34
PWM0_CH3
I/O
MFP6
PWM0 output/capture input.
EBI_AD11
I/O
MFP7
EBI address/data bus bit 11.
PC.4
I/O
MFP0
General purpose digital I/O pin.
SPI2_MISO
I/O
MFP2
SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE
Only)
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
USB_VBUS_EN
O
MFP4
USB external VBUS regulator enable pin.
(M45xG/M45xE Only)
PWM0_CH4
I/O
MFP6
PWM0 output/capture input.
EBI_AD12
I/O
MFP7
EBI address/data bus bit 12.
PC.5
I/O
MFP0
General purpose digital I/O pin.
SPI2_I2SMCLK
O
MFP2
I2S2 master clock output pin. (M45xG/M45xE Only)
PWM0_CH5
I/O
MFP6
PWM0 output/capture input.
EBI_AD13
I/O
MFP7
EBI address/data bus bit 13.
PC.6
I/O
MFP0
General purpose digital I/O pin.
I2C1_SMBAL
O
MFP3
I2C1 SMBus SMBALTER# pin
ACMP1_O
O
MFP5
Comparator1 output .
PWM1_CH0
I/O
MFP6
PWM1 output/capture input.
EBI_AD14
I/O
MFP7
EBI address/data bus bit 14.
UART0_TXD
O
MFP9
Data transmitter output pin for UART0. (M45xD/M45xC
Only)
PC.7
I/O
MFP0
General purpose digital I/O pin.
I2C1_SMBSUS
O
MFP3
I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)
PWM1_CH1
I/O
MFP6
PWM1 output/capture input.
EBI_AD15
I/O
MFP7
EBI address/data bus bit 15.
I
MFP9
Data receiver input pin for UART0. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
Serial wired debugger clock pin
PF.6
I/O
MFP0
General purpose digital I/O pin.
ICE_DAT
I/O
MFP1
Serial wired debugger data pin
PE.8
I/O
MFP0
General purpose digital I/O pin.
UART1_TXD
O
MFP1
Data transmitter output pin for UART1.
SPI0_MISO1
I/O
MFP2
SPI0 2nd MISO (Master In, Slave Out) pin.
I2C1_SCL
I/O
MFP4
I2C1 clock pin.
SC0_PWR
O
MFP5
SmartCard power pin.
UART0_RXD
35
PF.5
ICE_CLK
36
37
Mar. 04, 2016
Page 90 of 219
Rev.2.05
M451
Pin No.
38
39
41
42
Type
MFP*
Description
CLKO
O
MFP9
Clock Out (M45xD/M45xC Only)
PWM0_BRAKE0
I
MFP10
PWM0 break input 0 (M45xD/M45xC Only)
T1
I/O
MFP11
Timer1 event counter input / toggle output
(M45xD/M45xC Only)
PE.9
I/O
MFP0
General purpose digital I/O pin.
UART1_RXD
I
MFP1
Data receiver input pin for UART1.
SPI0_MOSI1
I/O
MFP2
SPI0 2nd MOSI (Master Out, Slave In) pin.
I2C1_SDA
I/O
MFP4
I2C1 data input/output pin.
SC0_RST
O
MFP5
SmartCard reset pin.
SPI1_I2SMCLK
O
MFP9
I2S1 master clock output pin. (M45xD/M45xC Only)
PWM1_BRAKE1
I
MFP10
PWM1 break input 1 (M45xD/M45xC Only)
T2
I/O
MFP11
Timer2 event counter input / toggle output
(M45xD/M45xC Only)
PE.10
I/O
MFP0
General purpose digital I/O pin.
SPI1_MISO
I/O
MFP1
SPI1 MISO (Master In, Slave Out) pin.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
UART1_nCTS
I
MFP3
Clear to Send input pin for UART1.
I2C0_SMBAL
O
MFP4
I2C0 SMBus SMBALTER# pin
SC0_DAT
I/O
MFP5
SmartCard data pin.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
I2C1_SCL
I/O
MFP11
I2C1 clock pin. (M45xD/M45xC Only)
PE.11
I/O
MFP0
General purpose digital I/O pin.
SPI1_MOSI
I/O
MFP1
SPI1 MOSI (Master Out, Slave In) pin.
SPI0_MOSI0
I/O
MFP2
SPI0 1st MOSI (Master Out, Slave In) pin.
UART1_nRTS
O
MFP3
Request to Send output pin for UART1.
I2C0_SMBSUS
O
MFP4
I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)
SC0_CLK
O
MFP5
SmartCard clock pin.
UART3_RXD
I
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
I2C1_SDA
I/O
MFP11
I2C1 data input/output pin. (M45xD/M45xC Only)
PE.12
I/O
MFP0
General purpose digital I/O pin.
SPI1_SS
I/O
MFP1
SPI1 slave select pin
SPI0_SS
I/O
MFP2
SPI0 slave select pin.
UART1_TXD
O
MFP3
Data transmitter output pin for UART1.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
PE.13
I/O
MFP0
General purpose digital I/O pin.
Mar. 04, 2016
Page 91 of 219
Rev.2.05
M451 SERIES DATASHEET
40
Pin Name
M451
Pin No.
Pin Name
Type
MFP*
Description
SPI1_CLK
I/O
MFP1
SPI1 serial clock pin
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
I
MFP3
Data receiver input pin for UART1.
I/O
MFP4
I2C0 data input/output pin.
UART1_RXD
I2C0_SDA
43
VDDIO
A
MFP0
Power supply for PE.8~PE.13.
44
USB_VBUS
A
MFP0
Power supply from USB* host or HUB.
45
USB_D-
I
MFP0
USB differential signal D-.
46
USB_D+
I
MFP0
USB differential signal D+.
47
PF.7
I/O
MFP0
General purpose digital I/O pin. (M45xD/M45xC Only)
USB_ID
I
MFP0
USB identification. (M45xG/M45xE Only)
USB_VDD33_CAP
A
MFP0
Internal power regulator output 3.3V decoupling pin.
48
Note: This pin needs to be connected with a 1uF
capacitor.
49
M451 SERIES DATASHEET
50
51
PA.3
I/O
MFP0
General purpose digital I/O pin.
USB_VBUS_ST
I
MFP1
USB external VBUS regulator status pin. (M45xG/M45xE
Only)
UART0_RXD
I
MFP2
Data receiver input pin for UART0.
UART0_nRTS
O
MFP3
Request to Send output pin for UART0.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
SC0_PWR
O
MFP5
SmartCard power pin.
PWM1_CH2
I/O
MFP6
PWM1 output/capture input.
EBI_AD3
I/O
MFP7
EBI address/data bus bit 3.
PA.2
I/O
MFP0
General purpose digital I/O pin.
USB_VBUS_EN
O
MFP1
USB external VBUS regulator enable pin.
(M45xG/M45xE Only)
UART0_TXD
O
MFP2
Data transmitter output pin for UART0.
UART0_nCTS
I
MFP3
Clear to Send input pin for UART0.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
SC0_RST
O
MFP5
SmartCard reset pin.
PWM1_CH3
I/O
MFP6
PWM1 output/capture input.
EBI_AD2
I/O
MFP7
EBI address/data bus bit 2.
PA.1
I/O
MFP0
General purpose digital I/O pin.
UART1_nRTS
O
MFP1
Request to Send output pin for UART1.
UART1_RXD
I
MFP3
Data receiver input pin for UART1.
SC0_DAT
I/O
MFP5
SmartCard data pin.
PWM1_CH4
I/O
MFP6
PWM1 output/capture input.
Mar. 04, 2016
Page 92 of 219
Rev.2.05
M451
Pin No.
Pin Name
Type
MFP*
Description
EBI_AD1
I/O
MFP7
EBI address/data bus bit 1.
STADC
I/O
MFP10
ADC external trigger input. (M45xD/M45xC Only)
PA.0
I/O
MFP0
General purpose digital I/O pin.
UART1_nCTS
I
MFP1
Clear to Send input pin for UART1.
UART1_TXD
O
MFP3
Data transmitter output pin for UART1.
SC0_CLK
O
MFP5
SmartCard clock pin.
PWM1_CH5
I/O
MFP6
PWM1 output/capture input.
EBI_AD0
I/O
MFP7
EBI address/data bus bit 0.
INT0
I
MFP8
External interrupt0 input pin.
SPI1_I2SMCLK
O
MFP9
I2S1 master clock output pin. (M45xD/M45xC Only)
53
VSS
A
MFP0
Ground pin for digital circuit.
54
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
55
AVDD
A
MFP0
Power supply for internal analog circuit.
56
VREF
I
MFP0
Voltage reference input for ADC.
52
Note: This pin needs to be connected with a 1uF
capacitor.
57
PB.0
MFP0
General purpose digital I/O pin.
EADC_CH0
A
MFP1
EADC analog input.
SPI0_MOSI1
I/O
MFP2
SPI0 2nd MOSI (Master Out, Slave In) pin.
UART2_RXD
I
MFP3
Data receiver input pin for UART2.
I/O
MFP4
Timer2 event counter input / toggle output
DAC
A
MFP5
DAC analog output
EBI_nWRL
O
MFP7
EBI low byte write enable output pin.
INT1
I
MFP8
External interrupt1 input pin.
PB.1
I/O
MFP0
General purpose digital I/O pin.
EADC_CH1
A
MFP1
EADC analog input channel 1.
SPI0_MISO1
I/O
MFP2
SPI0 2nd MISO (Master In, Slave Out) pin.
UART2_TXD
O
MFP3
Data transmitter output pin for UART2.
T3
I/O
MFP4
Timer3 event counter input / toggle output
SC0_RST
O
MFP5
SmartCard reset pin.
PWM0_SYNC_OUT
O
MFP6
PWM0 counter synchronous trigger output pin.
EBI_nWRH
O
MFP7
EBI high byte write enable output pin
PB.2
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 2.
I/O
MFP2
SPI0 serial clock pin.
T2
58
59
EADC_CH2
SPI0_CLK
Mar. 04, 2016
Page 93 of 219
M451 SERIES DATASHEET
I/O
Rev.2.05
M451
Pin No.
60
61
Pin Name
Type
MFP*
Description
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin
UART1_RXD
I
MFP4
Data receiver input pin for UART1.
SC0_CD
I
MFP5
SmartCard card detect pin.
UART3_RXD
I
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
T2_EXT
I
MFP11
Timer2 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
EADC_CH3
A
MFP1
EADC analog input channel 3.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
UART1_TXD
O
MFP4
Data transmitter output pin for UART1.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
T0_EXT
I
MFP11
Timer0 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 4.
SPI0_SS
I/O
MFP2
SPI0 slave select pin.
SPI1_SS
I/O
MFP3
SPI1 slave select pin
UART1_nCTS
I
MFP4
Clear to Send input pin for UART1.
ACMP0_N
A
MFP5
Comparator0 negative input pin.
EBI_AD7
I/O
MFP7
EBI address/data bus bit 7.
UART2_TXD
O
MFP9
Data transmitter output pin for UART2. (M45xD/M45xC
Only)
T1_EXT
I
MFP11
Timer1 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
EADC_CH5
A
MFP1
EADC analog input channel 5.
UART1_nRTS
O
MFP4
Request to Send output pin for UART1.
PWM0_CH2
I/O
MFP6
PWM0 output/capture input.
PB.11
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 8.
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 9.
PB.3
PB.4
EADC_CH4
M451 SERIES DATASHEET
62
63
PB.8
EADC_CH8
64
PB.12
EADC_CH9
Mar. 04, 2016
Page 94 of 219
Rev.2.05
M451
4.3.7 M453 CAN Series(CAN+USB) LQFP48 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0.
PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5.
Pin No.
MFP*
Description
I/O
MFP0
General purpose digital I/O pin.
EADC_CH13
A
MFP1
EADC analog input channel 13.
SPI0_MOSI0
I/O
MFP2
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1_MOSI
I/O
MFP3
SPI1 MOSI (Master Out, Slave In) pin.
ACMP0_P2
A
MFP5
Comparator0 positive input pin.
EBI_AD6
I/O
MFP7
EBI address/data bus bit 6.
UART2_RXD
I/O
MFP9
Data receiver input pin for UART2. (M45xD/M45xC Only)
PB.6
I/O
MFP0
General purpose digital I/O pin.
EADC_CH14
A
MFP1
EADC analog input channel 14.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
ACMP0_P1
A
MFP5
Comparator0 positive input pin.
EBI_AD5
I/O
MFP7
EBI address/data bus bit 5.
PB.7
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 15.
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin
ACMP0_P0
A
MFP5
Comparator0 positive input pin.
EBI_AD4
I/O
MFP7
EBI address/data bus bit 4.
STADC
I/O
MFP10
ADC external trigger input. (M45xD/M45xC Only)
4
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
5
PD.0
I/O
MFP0
General purpose digital I/O pin.
EADC_CH6
A
MFP1
EADC analog input channel 6. (M45xD/M45xC Only)
SPI1_I2SMCLK
O
MFP2
I2S1 master clock output pin.
UART0_RXD
I
MFP3
Data receiver input pin for UART0.
ACMP1_N
A
MFP5
Comparator1 negative input pin.
INT3
I
MFP8
External interrupt3 input pin.
I/O
MFP11
Timer3 event counter input / toggle output.
(M45xD/M45xC Only)
2
3
PB.5
EADC_CH15
T3
6
AVSS
P
MFP0
Ground pin for analog circuit.
7
PD.1
I/O
MFP0
General purpose digital I/O pin.
Mar. 04, 2016
Page 95 of 219
Rev.2.05
M451 SERIES DATASHEET
Type
1
Pin Name
M451
Pin No.
8
9
Pin Name
M451 SERIES DATASHEET
Type
MFP*
Description
EADC_CH11
A
MFP1
EADC analog input channel 11. (M45xD/M45xC Only)
PWM0_SYNC_IN
I
MFP2
PWM0 counter synchronous trigger input pin.
UART0_TXD
O
MFP3
Data transmitter output pin for UART0.
ACMP1_P2
A
MFP5
Comparator1 positive input pin.
T0
I/O
MFP6
Timer0event counter input / toggle output
EBI_nRD
O
MFP7
EBI read enable output pin.
PD.2
I/O
MFP0
General purpose digital I/O pin.
STADC
I
MFP1
ADC external trigger input.
T0_EXT
I
MFP3
Timer0 external counter input
ACMP1_P1
A
MFP5
Comparator1 positive input pin.
PWM0_BRAKE0
I
MFP6
PWM0 break input 0
EBI_nWR
O
MFP7
EBI write enable output pin.
INT0
I
MFP8
External interrupt0 input pin.
PD.3
I/O
MFP0
General purpose digital I/O pin.
T2
I/O
MFP1
Timer2 event counter input / toggle output
T1_EXT
I
MFP3
Timer1 external counter input
ACMP1_P0
A
MFP5
Comparator1 positive input pin.
PWM0_BRAKE1
I
MFP6
PWM0 break input 1
EBI_MCLK
O
MFP7
EBI external clock output pin
INT1
I
MFP8
External interrupt1 input pin.
MFP0
Power supply by batteries for RTC and PF.0~PF.2.
10
VBAT
11
PF.0
I/O
MFP0
General purpose digital I/O pin.
X32_OUT
O
MFP1
External 32.768 kHZ (low speed) crystal output pin.
INT5
I
MFP8
External interrupt5 input pin.
PF.1
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 32.768 kHZ (low speed) crystal input pin.
PF.2
I/O
MFP0
General purpose digital I/O pin.
TAMPER
I/O
MFP1
TAMPER detector loop pin
PD.7
I/O
MFP0
General purpose digital I/O pin.
I
MFP3
PWM0 counter synchronous trigger input pin.
T1
I/O
MFP4
Timer1 event counter input / toggle output
ACMP0_O
O
MFP5
Comparator0 output .
PWM0_CH5
I/O
MFP6
PWM0 output/capture input.
EBI_nRD
O
MFP7
EBI read enable output pin.
12
X32_IN
13
14
PWM0_SYNC_IN
Mar. 04, 2016
Page 96 of 219
Rev.2.05
M451
Pin No.
15
16
Pin Name
Type
MFP*
Description
PF.3
I/O
MFP0
General purpose digital I/O pin.
XT1_OUT
O
MFP1
External 4~20 MHz (high speed) crystal output pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
PF.4
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 4~20 MHz (high speed) crystal input pin.
I/O
MFP3
I2C1 data input/output pin.
XT1_IN
I2C1_SDA
17
VSS
A
MFP0
Ground pin for digital circuit.
18
LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with a 1uF
capacitor.
19
20
22
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
UART2_nCTS
I
MFP3
Clear to Send input pin for UART2.
CAN0_TXD
I
MFP4
CAN bus transmitter input.
PWM0_CH0
I/O
MFP6
PWM0 output/capture input.
EBI_AD8
I/O
MFP7
EBI address/data bus bit 8.
INT2
I
MFP8
External interrupt2 input pin.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
T3_EXT
I
MFP11
Timer3 external counter input. (M45xD/M45xC Only)
PC.1
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP1
Clock Out
STDAC
I
MFP2
DAC external trigger input.
UART2_nRTS
O
MFP3
Request to Send output pin for UART2.
CAN0_RXD
I
MFP4
CAN bus receiver input.
PWM0_CH1
I/O
MFP6
PWM0 output/capture input.
EBI_AD9
I/O
MFP7
EBI address/data bus bit 9.
UART3_RXD
I/O
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
PC.2
I/O
MFP0
General purpose digital I/O pin.
SPI2_SS
I
MFP2
SPI2 slave select pin. (M45xG/M45xE Only)
UART2_TXD
O
MFP3
Data transmitter output pin for UART2.
ACMP1_O
O
MFP5
Comparator1 output .
PWM0_CH2
I/O
MFP6
PWM0 output/capture input.
EBI_AD10
I/O
MFP7
EBI address/data bus bit 10.
PC.3
I/O
MFP0
General purpose digital I/O pin.
SPI2_MOSI
I/O
MFP2
SPI2 MOSI (Master Out, Slave In) pin. (M45xG/M45xE
Mar. 04, 2016
Page 97 of 219
Rev.2.05
M451 SERIES DATASHEET
21
PC.0
M451
Pin No.
Pin Name
Type
MFP*
Description
Only)
23
24
M451 SERIES DATASHEET
25
UART2_RXD
I
MFP3
Data receiver input pin for UART2.
USB_VBUS_ST
I
MFP4
USB external VBUS regulator status pin. (M45xG/M45xE
Only)
PWM0_CH3
I/O
MFP6
PWM0 output/capture input.
EBI_AD11
I/O
MFP7
EBI address/data bus bit 11.
PC.4
I/O
MFP0
General purpose digital I/O pin.
SPI2_MISO
I/O
MFP2
SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE
Only)
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
USB_VBUS_EN
O
MFP4
USB external VBUS regulator enable pin.
(M45xG/M45xE Only)
PWM0_CH4
I/O
MFP6
PWM0 output/capture input.
EBI_AD12
I/O
MFP7
EBI address/data bus bit 12.
PE.0
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
T2_EXT
I
MFP4
Timer2 external counter input
SC0_CD
I
MFP5
SmartCard card detect pin.
PWM0_CH0
I/O
MFP6
PWM0 output/capture input.
EBI_nCS1
O
MFP7
EBI chip select 1 enable output pin.
INT4
I
MFP8
External interrupt4 input pin.
PF.5
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
Serial wired debugger clock pin
PF.6
I/O
MFP0
General purpose digital I/O pin.
ICE_DAT
I/O
MFP1
Serial wired debugger data pin
PE.10
I/O
MFP0
General purpose digital I/O pin.
SPI1_MISO
I/O
MFP1
SPI1 MISO (Master In, Slave Out) pin.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
UART1_nCTS
I
MFP3
Clear to Send input pin for UART1.
I2C0_SMBAL
O
MFP4
I2C0 SMBus SMBALTER# pin
SC0_DAT
I/O
MFP5
SmartCard data pin.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
I2C1_SCL
I/O
MFP11
I2C1 clock pin. (M45xD/M45xC Only)
PE.11
I/O
MFP0
General purpose digital I/O pin.
SPI1_MOSI
I/O
MFP1
SPI1 MOSI (Master Out, Slave In) pin.
ICE_CLK
26
27
28
Mar. 04, 2016
Page 98 of 219
Rev.2.05
M451
Pin No.
29
30
Pin Name
Type
MFP*
Description
SPI0_MOSI0
I/O
MFP2
SPI0 1st MOSI (Master Out, Slave In) pin.
UART1_nRTS
O
MFP3
Request to Send output pin for UART1.
I2C0_SMBSUS
O
MFP4
I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)
SC0_CLK
O
MFP5
SmartCard clock pin.
UART3_RXD
I
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
I2C1_SDA
I/O
MFP11
I2C1 data input/output pin. (M45xD/M45xC Only)
PE.12
I/O
MFP0
General purpose digital I/O pin.
SPI1_SS
I/O
MFP1
SPI1 slave select pin
SPI0_SS
I/O
MFP2
SPI0 slave select pin.
UART1_TXD
O
MFP3
Data transmitter output pin for UART1.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
PE.13
I/O
MFP0
General purpose digital I/O pin.
SPI1_CLK
I/O
MFP1
SPI1 serial clock pin
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
I
MFP3
Data receiver input pin for UART1.
I/O
MFP4
I2C0 data input/output pin.
UART1_RXD
I2C0_SDA
VDDIO
A
MFP0
Power supply for PE.10~PE.13.
32
USB_VBUS
A
MFP0
Power supply from USB* host or HUB.
33
USB_D-
I
MFP0
USB differential signal D-.
34
USB_D+
I
MFP0
USB differential signal D+.
35
PF.7
I/O
MFP0
General purpose digital I/O pin. (M45xD/M45xC Only)
USB_ID
I
MFP0
USB identification. (M45xG/M45xE Only)
USB_VDD33_CAP
A
MFP0
Internal power regulator output 3.3V decoupling pin.
36
Note: This pin needs to be connected with a 1uF
capacitor.
37
38
PA.3
I/O
MFP0
General purpose digital I/O pin.
USB_VBUS_ST
I
MFP1
USB external VBUS regulator status pin. (M45xG/M45xE
Only)
UART0_RXD
I
MFP2
Data receiver input pin for UART0.
UART0_nRTS
O
MFP3
Request to Send output pin for UART0.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
SC0_PWR
O
MFP5
SmartCard power pin.
PWM1_CH2
I/O
MFP6
PWM1 output/capture input.
EBI_AD3
I/O
MFP7
EBI address/data bus bit 3.
PA.2
I/O
MFP0
General purpose digital I/O pin.
USB_VBUS_EN
O
MFP1
USB external VBUS regulator enable pin.
Mar. 04, 2016
Page 99 of 219
Rev.2.05
M451 SERIES DATASHEET
31
M451
Pin No.
Pin Name
Type
MFP*
Description
(M45xG/M45xE Only)
UART0_TXD
O
MFP2
Data transmitter output pin for UART0.
UART0_nCTS
I
MFP3
Clear to Send input pin for UART0.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
SC0_RST
O
MFP5
SmartCard reset pin.
PWM1_CH3
I/O
MFP6
PWM1 output/capture input.
EBI_AD2
I/O
MFP7
EBI address/data bus bit 2.
PA.1
I/O
MFP0
General purpose digital I/O pin.
UART1_nRTS
O
MFP1
Request to Send output pin for UART1.
UART1_RXD
I
MFP3
Data receiver input pin for UART1.
CAN0_TXD
I
MFP4
CAN bus transmitter input.
SC0_DAT
I/O
MFP5
SmartCard data pin.
PWM1_CH4
I/O
MFP6
PWM1 output/capture input.
EBI_AD1
I/O
MFP7
EBI address/data bus bit 1.
STADC
I/O
MFP10
ADC external trigger input. (M45xD/M45xC Only)
PA.0
I/O
MFP0
General purpose digital I/O pin.
UART1_nCTS
I
MFP1
Clear to Send input pin for UART1.
UART1_TXD
O
MFP3
Data transmitter output pin for UART1.
CAN0_RXD
I
MFP4
CAN bus receiver input.
SC0_CLK
O
MFP5
SmartCard clock pin.
PWM1_CH5
I/O
MFP6
PWM1 output/capture input.
EBI_AD0
I/O
MFP7
EBI address/data bus bit 0.
INT0
I
MFP8
External interrupt0 input pin.
SPI1_I2SMCLK
O
MFP9
I2S1 master clock output pin. (M45xD/M45xC Only)
41
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
42
AVDD
A
MFP0
Power supply for internal analog circuit.
43
VREF
I
MFP0
Voltage reference input for ADC.
39
40
M451 SERIES DATASHEET
Note: This pin needs to be connected with a 1uF
capacitor.
44
PB.0
I/O
MFP0
General purpose digital I/O pin.
EADC_CH0
A
MFP1
EADC analog input.
SPI0_MOSI1
I/O
MFP2
SPI0 2nd MOSI (Master Out, Slave In) pin.
UART2_RXD
I
MFP3
Data receiver input pin for UART2.
I/O
MFP4
Timer2 event counter input / toggle output
A
MFP5
DAC analog output
T2
DAC
Mar. 04, 2016
Page 100 of 219
Rev.2.05
M451
Pin No.
45
46
Type
MFP*
Description
EBI_nWRL
O
MFP7
EBI low byte write enable output pin.
INT1
I
MFP8
External interrupt1 input pin.
PB.1
I/O
MFP0
General purpose digital I/O pin.
EADC_CH1
A
MFP1
EADC analog input channel 1.
SPI0_MISO1
I/O
MFP2
SPI0 2nd MISO (Master In, Slave Out) pin.
UART2_TXD
O
MFP3
Data transmitter output pin for UART2.
T3
I/O
MFP4
Timer3 event counter input / toggle output
SC0_RST
O
MFP5
SmartCard reset pin.
PWM0_SYNC_OUT
O
MFP6
PWM0 counter synchronous trigger output pin.
EBI_nWRH
O
MFP7
EBI high byte write enable output pin
PB.2
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 2.
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin
UART1_RXD
I
MFP4
Data receiver input pin for UART1.
SC0_CD
I
MFP5
SmartCard card detect pin.
UART3_RXD
I
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
T2_EXT
I
MFP11
Timer2 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
EADC_CH3
A
MFP1
EADC analog input channel 3.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
UART1_TXD
O
MFP4
Data transmitter output pin for UART1.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
T0_EXT
I
MFP11
Timer0 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 4.
SPI0_SS
I/O
MFP2
SPI0 slave select pin.
SPI1_SS
I/O
MFP3
SPI1 slave select pin
UART1_nCTS
I
MFP4
Clear to Send input pin for UART1.
ACMP0_N
A
MFP5
Comparator0 negative input pin.
EBI_AD7
I/O
MFP7
EBI address/data bus bit 7.
UART2_TXD
O
MFP9
Data transmitter output pin for UART2. (M45xD/M45xC
Only)
EADC_CH2
47
48
PB.3
PB.4
EADC_CH4
Mar. 04, 2016
Page 101 of 219
Rev.2.05
M451 SERIES DATASHEET
Pin Name
M451
Pin No.
Pin Name
T1_EXT
Type
MFP*
I
MFP11
Description
Timer1 external counter input. (M45xD/M45xC Only)
M451 SERIES DATASHEET
Mar. 04, 2016
Page 102 of 219
Rev.2.05
M451
4.3.8 M453 CAN Series(CAN+USB) LQFP64 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0.
PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5.
Pin No.
MFP*
Description
I/O
MFP0
General purpose digital I/O pin.
EADC_CH12
A
MFP1
EADC analog input channel 12.
ACMP0_P3
A
MFP5
Comparator0 positive input pin.
EBI_nCS1
O
MFP7
EBI chip select 1 enable output pin.
PB.5
I/O
MFP0
General purpose digital I/O pin.
EADC_CH13
A
MFP1
EADC analog input channel 13.
SPI0_MOSI0
I/O
MFP2
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1_MOSI
I/O
MFP3
SPI1 MOSI (Master Out, Slave In) pin.
ACMP0_P2
A
MFP5
Comparator0 positive input pin.
EBI_AD6
I/O
MFP7
EBI address/data bus bit 6.
UART2_RXD
I/O
MFP9
Data receiver input pin for UART2. (M45xD/M45xC Only)
PB.6
I/O
MFP0
General purpose digital I/O pin.
EADC_CH14
A
MFP1
EADC analog input channel 14.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
ACMP0_P1
A
MFP5
Comparator0 positive input pin.
EBI_AD5
I/O
MFP7
EBI address/data bus bit 5.
STADC
I/O
MFP10
ADC external trigger input. (M45xD/M45xC Only)
PB.7
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 15.
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin
ACMP0_P0
A
MFP5
Comparator0 positive input pin.
EBI_AD4
I/O
MFP7
EBI address/data bus bit 4.
5
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
6
PD.0
I/O
MFP0
General purpose digital I/O pin.
EADC_CH6
A
MFP1
EADC analog input channel 6. (M45xD/M45xC Only)
SPI1_I2SMCLK
O
MFP2
I2S1 master clock output pin.
UART0_RXD
I
MFP3
Data receiver input pin for UART0.
ACMP1_N
A
MFP5
Comparator1 negative input pin.
2
3
4
PB.15
EADC_CH15
Mar. 04, 2016
Page 103 of 219
Rev.2.05
M451 SERIES DATASHEET
Type
1
Pin Name
M451
Pin No.
Pin Name
INT3
T3
Type
MFP*
Description
I
MFP8
External interrupt3 input pin.
I/O
MFP11
Timer3 event counter input / toggle output.
(M45xD/M45xC Only)
7
AVSS
P
MFP0
Ground pin for analog circuit.
8
PD.8
I/O
MFP0
General purpose digital I/O pin.
EADC_CH7
A
MFP1
EADC analog input channel 7. (M45xD/M45xC Only)
EBI_nCS0
O
MFP7
EBI chip select 0 enable output pin.
PD.9
I/O
MFP0
General purpose digital I/O pin.
EADC_CH10
A
MFP1
EADC analog input channel 10. (M45xD/M45xC Only)
ACMP1_P3
A
MFP5
Comparator1 positive input pin.
EBI_ALE
O
MFP7
EBI address latch enable output pin.
PD.1
I/O
MFP0
General purpose digital I/O pin.
EADC_CH11
A
MFP1
EADC analog input channel 11. (M45xD/M45xC Only)
PWM0_SYNC_IN
I
MFP2
PWM0 counter synchronous trigger input pin.
UART0_TXD
O
MFP3
Data transmitter output pin for UART0.
ACMP1_P2
A
MFP5
Comparator1 positive input pin.
T0
I/O
MFP6
Timer0event counter input / toggle output
EBI_nRD
O
MFP7
EBI read enable output pin.
PD.2
I/O
MFP0
General purpose digital I/O pin.
STADC
I
MFP1
ADC external trigger input.
T0_EXT
I
MFP3
Timer0 external counter input
ACMP1_P1
A
MFP5
Comparator1 positive input pin.
PWM0_BRAKE0
I
MFP6
PWM0 break input 0
EBI_nWR
O
MFP7
EBI write enable output pin.
INT0
I
MFP8
External interrupt0 input pin.
PD.3
I/O
MFP0
General purpose digital I/O pin.
T2
I/O
MFP1
Timer2 event counter input / toggle output
T1_EXT
I
MFP3
Timer1 external counter input
ACMP1_P0
A
MFP5
Comparator1 positive input pin.
PWM0_BRAKE1
I
MFP6
PWM0 break input 1
EBI_MCLK
O
MFP7
EBI external clock output pin
INT1
I
MFP8
External interrupt1 input pin.
MFP0
Power supply by batteries for RTC and PF.0~PF.2.
9
10
11
M451 SERIES DATASHEET
12
13
VBAT
14
PF.0
I/O
MFP0
General purpose digital I/O pin.
X32_OUT
O
MFP1
External 32.768 kHZ (low speed) crystal output pin.
Mar. 04, 2016
Page 104 of 219
Rev.2.05
M451
Pin No.
15
Pin Name
MFP*
Description
INT5
I
MFP8
External interrupt5 input pin.
PF.1
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 32.768 kHZ (low speed) crystal input pin.
PF.2
I/O
MFP0
General purpose digital I/O pin.
TAMPER
I/O
MFP1
TAMPER detector loop pin
PD.12
I/O
MFP0
General purpose digital I/O pin.
SPI2_SS
I
MFP2
SPI2 slave select pin. (M45xG/M45xE Only)
UART3_TXD
O
MFP3
Data transmitter output pin for UART3.
PWM1_CH0
I/O
MFP6
PWM1 output/capture input.
EBI_ADR16
O
MFP7
EBI address bus bit 16.
PD.13
I/O
MFP0
General purpose digital I/O pin.
SPI2_MOSI
I/O
MFP2
SPI2 MOSI (Master Out, Slave In) pin. (M45xG/M45xE
Only)
UART3_RXD
I
MFP3
Data receiver input pin for UART3.
PWM1_CH1
I/O
MFP6
PWM1 output/capture input.
EBI_ADR17
O
MFP7
EBI address bus bit 17.
PD.14
I/O
MFP0
General purpose digital I/O pin.
SPI2_MISO
I/O
MFP2
SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE
Only)
I
MFP3
Clear to Send input pin for UART3.
PWM1_CH2
I/O
MFP6
PWM1 output/capture input.
EBI_ADR18
O
MFP7
EBI address bus bit 18.
PD.15
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
UART3_nRTS
O
MFP3
Request to Send output pin for UART3.
PWM1_CH3
I/O
MFP6
PWM1 output/capture input.
EBI_ADR19
O
MFP7
EBI address bus bit 19.
PD.7
I/O
MFP0
General purpose digital I/O pin.
I
MFP3
PWM0 counter synchronous trigger input pin.
T1
I/O
MFP4
Timer1 event counter input / toggle output
ACMP0_O
O
MFP5
Comparator0 output .
PWM0_CH5
I/O
MFP6
PWM0 output/capture input.
EBI_nRD
O
MFP7
EBI read enable output pin.
PF.3
I/O
MFP0
General purpose digital I/O pin.
XT1_OUT
O
MFP1
External 4~20 MHz (high speed) crystal output pin.
X32_IN
16
17
18
19
UART3_nCTS
20
21
PWM0_SYNC_IN
22
Mar. 04, 2016
Page 105 of 219
M451 SERIES DATASHEET
Type
Rev.2.05
M451
Pin No.
23
Pin Name
Type
MFP*
Description
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
PF.4
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 4~20 MHz (high speed) crystal input pin.
I/O
MFP3
I2C1 data input/output pin.
XT1_IN
I2C1_SDA
24
VSS
A
MFP0
Ground pin for digital circuit.
25
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
26
LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with a 1uF
capacitor.
27
28
M451 SERIES DATASHEET
29
30
PC.0
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
UART2_nCTS
I
MFP3
Clear to Send input pin for UART2.
CAN0_TXD
I
MFP4
CAN bus transmitter input.
PWM0_CH0
I/O
MFP6
PWM0 output/capture input.
EBI_AD8
I/O
MFP7
EBI address/data bus bit 8.
INT2
I
MFP8
External interrupt2 input pin.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
T3_EXT
I
MFP11
Timer3 external counter input. (M45xD/M45xC Only)
PC.1
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP1
Clock Out
STDAC
I
MFP2
DAC external trigger input.
UART2_nRTS
O
MFP3
Request to Send output pin for UART2.
CAN0_RXD
I
MFP4
CAN bus receiver input.
PWM0_CH1
I/O
MFP6
PWM0 output/capture input.
EBI_AD9
I/O
MFP7
EBI address/data bus bit 9.
UART3_RXD
I/O
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
PC.2
I/O
MFP0
General purpose digital I/O pin.
SPI2_SS
I
MFP2
SPI2 slave select pin. (M45xG/M45xE Only)
UART2_TXD
O
MFP3
Data transmitter output pin for UART2.
ACMP1_O
O
MFP5
Comparator1 output .
PWM0_CH2
I/O
MFP6
PWM0 output/capture input.
EBI_AD10
I/O
MFP7
EBI address/data bus bit 10.
PC.3
I/O
MFP0
General purpose digital I/O pin.
SPI2_MOSI
I/O
MFP2
SPI2 MOSI (Master Out, Slave In) pin. (M45xG/M45xE
Only)
Mar. 04, 2016
Page 106 of 219
Rev.2.05
M451
Pin No.
31
32
33
Type
MFP*
Description
UART2_RXD
I
MFP3
Data receiver input pin for UART2.
USB_VBUS_ST
I
MFP4
USB external VBUS regulator status pin. (M45xG/M45xE
Only)
PWM0_CH3
I/O
MFP6
PWM0 output/capture input.
EBI_AD11
I/O
MFP7
EBI address/data bus bit 11.
PC.4
I/O
MFP0
General purpose digital I/O pin.
SPI2_MISO
I/O
MFP2
SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE
Only)
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
USB_VBUS_EN
O
MFP4
USB external VBUS regulator enable pin.
(M45xG/M45xE Only)
PWM0_CH4
I/O
MFP6
PWM0 output/capture input.
EBI_AD12
I/O
MFP7
EBI address/data bus bit 12.
PC.5
I/O
MFP0
General purpose digital I/O pin.
SPI2_I2SMCLK
O
MFP2
I2S2 master clock output pin. (M45xG/M45xE Only)
PWM0_CH5
I/O
MFP6
PWM0 output/capture input.
EBI_AD13
I/O
MFP7
EBI address/data bus bit 13.
PC.6
I/O
MFP0
General purpose digital I/O pin.
I2C1_SMBAL
O
MFP3
I2C1 SMBus SMBALTER# pin
ACMP1_O
O
MFP5
Comparator1 output .
PWM1_CH0
I/O
MFP6
PWM1 output/capture input.
EBI_AD14
I/O
MFP7
EBI address/data bus bit 14.
UART0_TXD
O
MFP9
Data transmitter output pin for UART0. (M45xD/M45xC
Only)
PC.7
I/O
MFP0
General purpose digital I/O pin.
I2C1_SMBSUS
O
MFP3
I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)
PWM1_CH1
I/O
MFP6
PWM1 output/capture input.
EBI_AD15
I/O
MFP7
EBI address/data bus bit 15.
I
MFP9
Data receiver input pin for UART0. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
Serial wired debugger clock pin
PF.6
I/O
MFP0
General purpose digital I/O pin.
ICE_DAT
I/O
MFP1
Serial wired debugger data pin
PE.8
I/O
MFP0
General purpose digital I/O pin.
UART1_TXD
O
MFP1
Data transmitter output pin for UART1.
SPI0_MISO1
I/O
MFP2
SPI0 2nd MISO (Master In, Slave Out) pin.
UART0_RXD
35
PF.5
ICE_CLK
36
37
Mar. 04, 2016
Page 107 of 219
Rev.2.05
M451 SERIES DATASHEET
34
Pin Name
M451
Pin No.
38
39
M451 SERIES DATASHEET
40
41
Pin Name
Type
MFP*
Description
I2C1_SCL
I/O
MFP4
I2C1 clock pin.
SC0_PWR
O
MFP5
SmartCard power pin.
CLKO
O
MFP9
Clock Out (M45xD/M45xC Only)
PWM0_BRAKE0
I
MFP10
PWM0 break input 0 (M45xD/M45xC Only)
T1
I/O
MFP11
Timer1 event counter input / toggle output
(M45xD/M45xC Only)
PE.9
I/O
MFP0
General purpose digital I/O pin.
UART1_RXD
I
MFP1
Data receiver input pin for UART1.
SPI0_MOSI1
I/O
MFP2
SPI0 2nd MOSI (Master Out, Slave In) pin.
I2C1_SDA
I/O
MFP4
I2C1 data input/output pin.
SC0_RST
O
MFP5
SmartCard reset pin.
SPI1_I2SMCLK
O
MFP9
I2S1 master clock output pin. (M45xD/M45xC Only)
PWM1_BRAKE1
I
MFP10
PWM1 break input 1 (M45xD/M45xC Only)
T2
I/O
MFP11
Timer2 event counter input / toggle output
(M45xD/M45xC Only)
PE.10
I/O
MFP0
General purpose digital I/O pin.
SPI1_MISO
I/O
MFP1
SPI1 MISO (Master In, Slave Out) pin.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
UART1_nCTS
I
MFP3
Clear to Send input pin for UART1.
I2C0_SMBAL
O
MFP4
I2C0 SMBus SMBALTER# pin
SC0_DAT
I/O
MFP5
SmartCard data pin.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
I2C1_SCL
I/O
MFP11
I2C1 clock pin. (M45xD/M45xC Only)
PE.11
I/O
MFP0
General purpose digital I/O pin.
SPI1_MOSI
I/O
MFP1
SPI1 MOSI (Master Out, Slave In) pin.
SPI0_MOSI0
I/O
MFP2
SPI0 1st MOSI (Master Out, Slave In) pin.
UART1_nRTS
O
MFP3
Request to Send output pin for UART1.
I2C0_SMBSUS
O
MFP4
I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)
SC0_CLK
O
MFP5
SmartCard clock pin.
UART3_RXD
I
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
I2C1_SDA
I/O
MFP11
I2C1 data input/output pin. (M45xD/M45xC Only)
PE.12
I/O
MFP0
General purpose digital I/O pin.
SPI1_SS
I/O
MFP1
SPI1 slave select pin
SPI0_SS
I/O
MFP2
SPI0 slave select pin.
UART1_TXD
O
MFP3
Data transmitter output pin for UART1.
Mar. 04, 2016
Page 108 of 219
Rev.2.05
M451
Pin No.
42
Pin Name
Type
MFP*
Description
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
PE.13
I/O
MFP0
General purpose digital I/O pin.
SPI1_CLK
I/O
MFP1
SPI1 serial clock pin
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
I
MFP3
Data receiver input pin for UART1.
I/O
MFP4
I2C0 data input/output pin.
UART1_RXD
I2C0_SDA
43
VDDIO
A
MFP0
Power supply for PE.8~PE.13.
44
USB_VBUS
A
MFP0
Power supply from USB* host or HUB.
45
USB_D-
I
MFP0
USB differential signal D-.
46
USB_D+
I
MFP0
USB differential signal D+.
47
PF.7
I/O
MFP0
General purpose digital I/O pin. (M45xD/M45xC Only)
USB_ID
I
MFP0
USB identification. (M45xG/M45xE Only)
USB_VDD33_CAP
A
MFP0
Internal power regulator output 3.3V decoupling pin.
48
Note: This pin needs to be connected with a 1uF
capacitor.
49
51
I/O
MFP0
General purpose digital I/O pin.
USB_VBUS_ST
I
MFP1
USB external VBUS regulator status pin. (M45xG/M45xE
Only)
UART0_RXD
I
MFP2
Data receiver input pin for UART0.
UART0_nRTS
O
MFP3
Request to Send output pin for UART0.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
SC0_PWR
O
MFP5
SmartCard power pin.
PWM1_CH2
I/O
MFP6
PWM1 output/capture input.
EBI_AD3
I/O
MFP7
EBI address/data bus bit 3.
PA.2
I/O
MFP0
General purpose digital I/O pin.
USB_VBUS_EN
O
MFP1
USB external VBUS regulator enable pin.
(M45xG/M45xE Only)
UART0_TXD
O
MFP2
Data transmitter output pin for UART0.
UART0_nCTS
I
MFP3
Clear to Send input pin for UART0.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
SC0_RST
O
MFP5
SmartCard reset pin.
PWM1_CH3
I/O
MFP6
PWM1 output/capture input.
EBI_AD2
I/O
MFP7
EBI address/data bus bit 2.
PA.1
I/O
MFP0
General purpose digital I/O pin.
UART1_nRTS
O
MFP1
Request to Send output pin for UART1.
UART1_RXD
I
MFP3
Data receiver input pin for UART1.
Mar. 04, 2016
Page 109 of 219
M451 SERIES DATASHEET
50
PA.3
Rev.2.05
M451
Pin No.
Pin Name
Type
MFP*
Description
I
MFP4
CAN bus transmitter input.
SC0_DAT
I/O
MFP5
SmartCard data pin.
PWM1_CH4
I/O
MFP6
PWM1 output/capture input.
EBI_AD1
I/O
MFP7
EBI address/data bus bit 1.
STADC
I/O
MFP10
ADC external trigger input. (M45xD/M45xC Only)
PA.0
I/O
MFP0
General purpose digital I/O pin.
UART1_nCTS
I
MFP1
Clear to Send input pin for UART1.
UART1_TXD
O
MFP3
Data transmitter output pin for UART1.
CAN0_RXD
I
MFP4
CAN bus receiver input.
SC0_CLK
O
MFP5
SmartCard clock pin.
PWM1_CH5
I/O
MFP6
PWM1 output/capture input.
EBI_AD0
I/O
MFP7
EBI address/data bus bit 0.
INT0
I
MFP8
External interrupt0 input pin.
SPI1_I2SMCLK
O
MFP9
I2S1 master clock output pin. (M45xD/M45xC Only)
53
VSS
A
MFP0
Ground pin for digital circuit.
54
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
55
AVDD
A
MFP0
Power supply for internal analog circuit.
56
VREF
I
MFP0
Voltage reference input for ADC.
CAN0_TXD
52
Note: This pin needs to be connected with a 1uF
capacitor.
M451 SERIES DATASHEET
57
PB.0
I/O
MFP0
General purpose digital I/O pin.
EADC_CH0
A
MFP1
EADC analog input.
SPI0_MOSI1
I/O
MFP2
SPI0 2nd MOSI (Master Out, Slave In) pin.
UART2_RXD
I
MFP3
Data receiver input pin for UART2.
I/O
MFP4
Timer2 event counter input / toggle output
DAC
A
MFP5
DAC analog output
EBI_nWRL
O
MFP7
EBI low byte write enable output pin.
INT1
I
MFP8
External interrupt1 input pin.
PB.1
I/O
MFP0
General purpose digital I/O pin.
EADC_CH1
A
MFP1
EADC analog input channel 1.
SPI0_MISO1
I/O
MFP2
SPI0 2nd MISO (Master In, Slave Out) pin.
UART2_TXD
O
MFP3
Data transmitter output pin for UART2.
T3
I/O
MFP4
Timer3 event counter input / toggle output
SC0_RST
O
MFP5
SmartCard reset pin.
PWM0_SYNC_OUT
O
MFP6
PWM0 counter synchronous trigger output pin.
T2
58
Mar. 04, 2016
Page 110 of 219
Rev.2.05
M451
Pin No.
59
Type
MFP*
Description
EBI_nWRH
O
MFP7
EBI high byte write enable output pin
PB.2
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 2.
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin
UART1_RXD
I
MFP4
Data receiver input pin for UART1.
SC0_CD
I
MFP5
SmartCard card detect pin.
UART3_RXD
I
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
T2_EXT
I
MFP11
Timer2 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
EADC_CH3
A
MFP1
EADC analog input channel 3.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
UART1_TXD
O
MFP4
Data transmitter output pin for UART1.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
T0_EXT
I
MFP11
Timer0 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 4.
SPI0_SS
I/O
MFP2
SPI0 slave select pin.
SPI1_SS
I/O
MFP3
SPI1 slave select pin
UART1_nCTS
I
MFP4
Clear to Send input pin for UART1.
ACMP0_N
A
MFP5
Comparator0 negative input pin.
EBI_AD7
I/O
MFP7
EBI address/data bus bit 7.
UART2_TXD
O
MFP9
Data transmitter output pin for UART2. (M45xD/M45xC
Only)
T1_EXT
I
MFP11
Timer1 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
EADC_CH5
A
MFP1
EADC analog input channel 5.
UART1_nRTS
O
MFP4
Request to Send output pin for UART1.
PWM0_CH2
I/O
MFP6
PWM0 output/capture input.
PB.11
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 8.
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 9.
EADC_CH2
60
61
PB.3
PB.4
EADC_CH4
62
63
PB.8
EADC_CH8
64
PB.12
EADC_CH9
Mar. 04, 2016
Page 111 of 219
Rev.2.05
M451 SERIES DATASHEET
Pin Name
M451
4.3.9 M453 CAN Series(CAN+USB) LQFP100 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[3:0] = 0x0.
PA.9 MFP5 means SYS_GPA_MFPH[7:4] = 0x5.
Pin No.
1
Pin Name
PB.13
EADC_CH10
Type
MFP*
Description
I/O
MFP0
General purpose digital I/O pin. (M45xG/M45xE Only)
A
MFP1
EADC analog input channel 10. (M45xG/M45xE Only)
NC
2
PB.14
EADC_CH11
Not connected (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin. (M45xG/M45xE Only)
A
MFP1
EADC analog input channel 11. (M45xG/M45xE Only)
NC
3
4
M451 SERIES DATASHEET
5
6
PB.15
I/O
MFP0
General purpose digital I/O pin.
EADC_CH12
A
MFP1
EADC analog input channel 12.
ACMP0_P3
A
MFP5
Comparator0 positive input pin.
EBI_nCS1
O
MFP7
EBI chip select 1 enable output pin.
PB.5
I/O
MFP0
General purpose digital I/O pin.
EADC_CH13
A
MFP1
EADC analog input channel 13.
SPI0_MOSI0
I/O
MFP2
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1_MOSI
I/O
MFP3
SPI1 MOSI (Master Out, Slave In) pin.
ACMP0_P2
A
MFP5
Comparator0 positive input pin.
EBI_AD6
I/O
MFP7
EBI address/data bus bit 6.
UART2_RXD
I/O
MFP9
Data receiver input pin for UART2. (M45xD/M45xC Only)
PB.6
I/O
MFP0
General purpose digital I/O pin.
EADC_CH14
A
MFP1
EADC analog input channel 14.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
ACMP0_P1
A
MFP5
Comparator0 positive input pin.
EBI_AD5
I/O
MFP7
EBI address/data bus bit 5.
PB.7
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 15.
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin
ACMP0_P0
A
MFP5
Comparator0 positive input pin.
EBI_AD4
I/O
MFP7
EBI address/data bus bit 4.
STADC
I/O
MFP10
ADC external trigger input. (M45xD/M45xC Only)
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up.
EADC_CH15
7
Not connected (M45xD/M45xC Only)
Mar. 04, 2016
Page 112 of 219
Rev.2.05
M451
Pin No.
Pin Name
Type
MFP*
Description
Set this pin low reset to initial state.
8
PD.0
I/O
MFP0
General purpose digital I/O pin.
EADC_CH6
A
MFP1
EADC analog input channel 6. (M45xD/M45xC Only)
SPI1_I2SMCLK
O
MFP2
I2S1 master clock output pin.
UART0_RXD
I
MFP3
Data receiver input pin for UART0.
ACMP1_N
A
MFP5
Comparator1 negative input pin.
INT3
I
MFP8
External interrupt3 input pin.
I/O
MFP11
Timer3 event counter input / toggle output.
(M45xD/M45xC Only)
P
MFP0
Ground pin for analog circuit. (M45xG/M45xE Only)
T3
9
AVSS
NC
Not connected (M45xD/M45xC Only)
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
11
VSS
A
MFP0
Ground pin for digital circuit.
12
PC.8
I/O
MFP0
General purpose digital I/O pin.
13
PD.8
I/O
MFP0
General purpose digital I/O pin.
EADC_CH7
A
MFP1
EADC analog input channel 7. (M45xD/M45xC Only)
EBI_nCS0
O
MFP7
EBI chip select 0 enable output pin.
EADC_CH10
A
MFP1
EADC analog input channel 10. (M45xD/M45xC Only)
ACMP1_P3
A
MFP5
Comparator1 positive input pin.
EBI_ALE
O
MFP7
EBI address latch enable output pin.
PD.1
I/O
MFP0
General purpose digital I/O pin.
EADC_CH11
A
MFP1
EADC analog input channel 11. (M45xD/M45xC Only)
PWM0_SYNC_IN
I
MFP2
PWM0 counter synchronous trigger input pin.
UART0_TXD
O
MFP3
Data transmitter output pin for UART0.
ACMP1_P2
A
MFP5
Comparator1 positive input pin.
T0
I/O
MFP6
Timer0event counter input / toggle output
EBI_nRD
O
MFP7
EBI read enable output pin.
PD.2
I/O
MFP0
General purpose digital I/O pin.
STADC
I
MFP1
ADC external trigger input.
T0_EXT
I
MFP3
Timer0 external counter input
ACMP1_P1
A
MFP5
Comparator1 positive input pin.
PWM0_BRAKE0
I
MFP6
PWM0 break input 0
EBI_nWR
O
MFP7
EBI write enable output pin.
INT0
I
MFP8
External interrupt0 input pin.
PD.3
I/O
MFP0
General purpose digital I/O pin.
15
16
17
Mar. 04, 2016
Page 113 of 219
Rev.2.05
M451 SERIES DATASHEET
10
M451
Pin No.
Pin Name
Type
MFP*
Description
I/O
MFP1
Timer2 event counter input / toggle output
T1_EXT
I
MFP3
Timer1 external counter input
ACMP1_P0
A
MFP5
Comparator1 positive input pin.
PWM0_BRAKE1
I
MFP6
PWM0 break input 1
EBI_MCLK
O
MFP7
EBI external clock output pin
INT1
I
MFP8
External interrupt1 input pin.
PD.4
I/O
MFP0
General purpose digital I/O pin.
SPI1_CLK
I/O
MFP2
SPI1 serial clock pin
I2C0_SDA
I/O
MFP3
I2C0 data input/output pin.
I
MFP5
PWM0 break input 0
T0
I/O
MFP6
Timer0event counter input / toggle output
PD.5
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP1
Clock Out
SPI1_MISO
I/O
MFP2
SPI1 MISO (Master In, Slave Out) pin.
I2C0_SCL
I/O
MFP3
I2C0 clock pin.
I
MFP5
PWM0 break input 1
T1
I/O
MFP6
Timer1 event counter input / toggle output
PE.3
I/O
MFP0
General purpose digital I/O pin.
SPI1_MOSI
I/O
MFP2
SPI1 MOSI (Master Out, Slave In) pin.
PWM0_CH3
I/O
MFP6
PWM0 output/capture input.
PD.6
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP1
Clock Out
SPI1_SS
I/O
MFP2
SPI1 slave select pin
UART0_RXD
I
MFP3
Data receiver input pin for UART0.
ACMP0_O
O
MFP5
Comparator0 output .
PWM0_CH5
I/O
MFP6
PWM0 output/capture input.
EBI_nWR
O
MFP7
EBI write enable output pin.
22
VBAT
A
MFP0
Power supply by batteries for RTC and PF.0~PF.2.
23
PF.0
I/O
MFP0
General purpose digital I/O pin.
X32_OUT
O
MFP1
External 32.768 kHZ (low speed) crystal output pin.
INT5
I
MFP8
External interrupt5 input pin.
PF.1
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 32.768 kHZ (low speed) crystal input pin.
I/O
MFP0
General purpose digital I/O pin.
T2
18
PWM0_BRAKE0
19
PWM0_BRAKE1
20
M451 SERIES DATASHEET
21
24
X32_IN
25
PF.2
Mar. 04, 2016
Page 114 of 219
Rev.2.05
M451
Pin No.
26
Pin Name
Type
MFP*
Description
TAMPER
I/O
MFP1
TAMPER detector loop pin
PD.10
I/O
MFP0
General purpose digital I/O pin. (M45xG/M45xE Only)
T2
I/O
MFP4
Timer2 event counter input / toggle output
(M45xG/M45xE Only)
NC
27
Not connected (M45xD/M45xC Only)
PD.11
I/O
MFP0
General purpose digital I/O pin. (M45xG/M45xE Only)
T3
I/O
MFP4
Timer3 event counter input / toggle output
(M45xG/M45xE Only)
NC
28
29
30
PD.12
MFP0
General purpose digital I/O pin.
SPI2_SS
I
MFP2
SPI2 slave select pin. (M45xG/M45xE Only)
UART3_TXD
O
MFP3
Data transmitter output pin for UART3.
PWM1_CH0
I/O
MFP6
PWM1 output/capture input.
EBI_ADR16
O
MFP7
EBI address bus bit 16.
PD.13
I/O
MFP0
General purpose digital I/O pin.
SPI2_MOSI
I/O
MFP2
SPI2 MOSI (Master Out, Slave In) pin. (M45xG/M45xE
Only)
UART3_RXD
I
MFP3
Data receiver input pin for UART3.
PWM1_CH1
I/O
MFP6
PWM1 output/capture input.
EBI_ADR17
O
MFP7
EBI address bus bit 17.
PD.14
I/O
MFP0
General purpose digital I/O pin.
SPI2_MISO
I/O
MFP2
SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE
Only)
I
MFP3
Clear to Send input pin for UART3.
PWM1_CH2
I/O
MFP6
PWM1 output/capture input.
EBI_ADR18
O
MFP7
EBI address bus bit 18.
PD.15
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
UART3_nRTS
O
MFP3
Request to Send output pin for UART3.
PWM1_CH3
I/O
MFP6
PWM1 output/capture input.
EBI_ADR19
O
MFP7
EBI address bus bit 19.
32
PD.7
I/O
MFP0
General purpose digital I/O pin.
I
MFP3
PWM0 counter synchronous trigger input pin.
T1
I/O
MFP4
Timer1 event counter input / toggle output
ACMP0_O
O
MFP5
Comparator0 output.
PWM0_CH5
I/O
MFP6
PWM0 output/capture input.
PWM0_SYNC_IN
Mar. 04, 2016
Page 115 of 219
Rev.2.05
M451 SERIES DATASHEET
I/O
UART3_nCTS
31
Not connected (M45xD/M45xC Only)
M451
Pin No.
33
34
Pin Name
Type
MFP*
Description
EBI_nRD
O
MFP7
EBI read enable output pin.
PF.3
I/O
MFP0
General purpose digital I/O pin.
XT1_OUT
O
MFP1
External 4~20 MHz (high speed) crystal output pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
PF.4
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 4~20 MHz (high speed) crystal input pin.
I/O
MFP3
I2C1 data input/output pin.
XT1_IN
I2C1_SDA
35
VSS
A
MFP0
Ground pin for digital circuit.
36
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
37
LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with a 1uF
capacitor.
38
PC.9
I/O
MFP0
General purpose digital I/O pin. (M45xG/M45xE Only)
SPI2_I2SMCLK
O
MFP2
I2S2 master clock output pin. (M45xG/M45xE Only)
PWM1_CH0
I/O
MFP6
PWM1 output/capture input. (M45xG/M45xE Only)
NC
39
M451 SERIES DATASHEET
40
41
42
PC.10
I/O
MFP0
General purpose digital I/O pin.
SPI2_MOSI
I/O
MFP2
SPI2 MOSI (Master Out, Slave In) pin. (M45xG/M45xE
Only)
PWM1_CH1
I/O
MFP6
PWM1 output/capture input.
PC.11
I/O
MFP0
General purpose digital I/O pin.
SPI2_MISO
I/O
MFP2
SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE
Only)
PWM1_CH2
I/O
MFP6
PWM1 output/capture input.
PC.12
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
PWM1_CH3
I/O
MFP6
PWM1 output/capture input.
PC.13
I/O
MFP0
General purpose digital I/O pin.
I
MFP2
SPI2 slave select pin. (M45xG/M45xE Only)
PWM1_CH4
I/O
MFP6
PWM1 output/capture input.
PC.14
I/O
MFP0
General purpose digital I/O pin. (M45xG/M45xE Only)
PWM1_CH5
I/O
MFP6
PWM1 output/capture input. (M45xG/M45xE Only)
SPI2_SS
43
Not connected (M45xD/M45xC Only)
NC
44
Not connected (M45xD/M45xC Only)
PC.0
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
I
MFP3
Clear to Send input pin for UART2.
UART2_nCTS
Mar. 04, 2016
Page 116 of 219
Rev.2.05
M451
Pin No.
45
46
48
Type
MFP*
Description
CAN0_TXD
I
MFP4
CAN bus transmitter input.
PWM0_CH0
I/O
MFP6
PWM0 output/capture input.
EBI_AD8
I/O
MFP7
EBI address/data bus bit 8.
INT2
I
MFP8
External interrupt2 input pin.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
T3_EXT
I
MFP11
Timer3 external counter input. (M45xD/M45xC Only)
PC.1
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP1
Clock Out
STDAC
I
MFP2
DAC external trigger input.
UART2_nRTS
O
MFP3
Request to Send output pin for UART2.
CAN0_RXD
I
MFP4
CAN bus receiver input.
PWM0_CH1
I/O
MFP6
PWM0 output/capture input.
EBI_AD9
I/O
MFP7
EBI address/data bus bit 9.
UART3_RXD
I/O
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
PC.2
I/O
MFP0
General purpose digital I/O pin.
SPI2_SS
I
MFP2
SPI2 slave select pin. (M45xG/M45xE Only)
UART2_TXD
O
MFP3
Data transmitter output pin for UART2.
ACMP1_O
O
MFP5
Comparator1 output .
PWM0_CH2
I/O
MFP6
PWM0 output/capture input.
EBI_AD10
I/O
MFP7
EBI address/data bus bit 10.
PC.3
I/O
MFP0
General purpose digital I/O pin.
SPI2_MOSI
I/O
MFP2
SPI2 MOSI (Master Out, Slave In) pin. (M45xG/M45xE
Only)
UART2_RXD
I
MFP3
Data receiver input pin for UART2.
USB_VBUS_ST
I
MFP4
USB external VBUS regulator status pin. (M45xG/M45xE
Only)
PWM0_CH3
I/O
MFP6
PWM0 output/capture input.
EBI_AD11
I/O
MFP7
EBI address/data bus bit 11.
PC.4
I/O
MFP0
General purpose digital I/O pin.
SPI2_MISO
I/O
MFP2
SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE
Only)
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
USB_VBUS_EN
O
MFP4
USB external VBUS regulator enable pin.
(M45xG/M45xE Only)
PWM0_CH4
I/O
MFP6
PWM0 output/capture input.
EBI_AD12
I/O
MFP7
EBI address/data bus bit 12.
Mar. 04, 2016
Page 117 of 219
Rev.2.05
M451 SERIES DATASHEET
47
Pin Name
M451
Pin No.
49
50
51
52
Pin Name
M451 SERIES DATASHEET
Type
MFP*
Description
PE.0
I/O
MFP0
General purpose digital I/O pin.
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin. (M45xG/M45xE Only)
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
T2_EXT
I
MFP4
Timer2 external counter input
SC0_CD
I
MFP5
SmartCard card detect pin.
PWM0_CH0
I/O
MFP6
PWM0 output/capture input.
EBI_nCS1
O
MFP7
EBI chip select 1 enable output pin.
INT4
I
MFP8
External interrupt4 input pin.
PC.5
I/O
MFP0
General purpose digital I/O pin.
SPI2_I2SMCLK
O
MFP2
I2S2 master clock output pin. (M45xG/M45xE Only)
PWM0_CH5
I/O
MFP6
PWM0 output/capture input.
EBI_AD13
I/O
MFP7
EBI address/data bus bit 13.
PC.6
I/O
MFP0
General purpose digital I/O pin.
I2C1_SMBAL
O
MFP3
I2C1 SMBus SMBALTER# pin
ACMP1_O
O
MFP5
Comparator1 output .
PWM1_CH0
I/O
MFP6
PWM1 output/capture input.
EBI_AD14
I/O
MFP7
EBI address/data bus bit 14.
UART0_TXD
O
MFP9
Data transmitter output pin for UART0. (M45xD/M45xC
Only)
PC.7
I/O
MFP0
General purpose digital I/O pin.
I2C1_SMBSUS
O
MFP3
I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)
PWM1_CH1
I/O
MFP6
PWM1 output/capture input.
EBI_AD15
I/O
MFP7
EBI address/data bus bit 15.
I
MFP9
Data receiver input pin for UART0. (M45xD/M45xC Only)
PE.4
I/O
MFP0
General purpose digital I/O pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
SC0_PWR
O
MFP5
SmartCard power pin.
PWM1_BRAKE0
I
MFP6
PWM1 break input 0
EBI_nCS0
O
MFP7
EBI chip select 0 enable output pin.
INT0
I
MFP8
External interrupt0 input pin.
PE.5
I/O
MFP0
General purpose digital I/O pin.
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
SC0_RST
O
MFP5
SmartCard reset pin.
PWM1_BRAKE1
I
MFP6
PWM1 break input 1
EBI_ALE
O
MFP7
EBI address latch enable output pin.
UART0_RXD
53
54
Mar. 04, 2016
Page 118 of 219
Rev.2.05
M451
Pin No.
55
Pin Name
MFP*
Description
INT1
I
MFP8
External interrupt1 input pin.
PF.5
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
Serial wired debugger clock pin
PF.6
I/O
MFP0
General purpose digital I/O pin.
ICE_DAT
I/O
MFP1
Serial wired debugger data pin
PA.8
I/O
MFP0
General purpose digital I/O pin.
UART3_TXD
O
MFP3
Data transmitter output pin for UART3.
PA.9
I/O
MFP0
General purpose digital I/O pin.
I
MFP3
Data receiver input pin for UART3.
PA.7
I/O
MFP0
General purpose digital I/O pin.
SPI1_CLK
I/O
MFP2
SPI1 serial clock pin
T0_EXT
I
MFP3
Timer0 external counter input
EBI_AD7
I/O
MFP7
EBI address/data bus bit 7.
PA.6
I/O
MFP0
General purpose digital I/O pin.
SPI1_MISO
I/O
MFP2
SPI1 MISO (Master In, Slave Out) pin.
T1_EXT
I
MFP3
Timer1 external counter input
EBI_AD6
I/O
MFP7
EBI address/data bus bit 6.
PA.5
I/O
MFP0
General purpose digital I/O pin.
SPI1_MOSI
I/O
MFP2
SPI1 MOSI (Master Out, Slave In) pin.
T2_EXT
I
MFP3
Timer2 external counter input
EBI_AD5
I/O
MFP7
EBI address/data bus bit 5.
PA.4
I/O
MFP0
General purpose digital I/O pin.
SPI1_SS
I/O
MFP2
SPI1 slave select pin
EBI_AD4
I/O
MFP7
EBI address/data bus bit 4.
ICE_CLK
56
57
58
UART3_RXD
59
60
61
62
63
VSS
A
MFP0
Ground pin for digital circuit.
64
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function. (M45xG/M45xE Only)
NC
65
66
PE.1
Not connected (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
T3_EXT
I
MFP3
Timer3 external counter input
SC0_CD
I
MFP5
SmartCard card detect pin.
PWM0_CH1
I/O
MFP6
PWM0 output/capture input.
PE.8
I/O
MFP0
General purpose digital I/O pin.
UART1_TXD
O
MFP1
Data transmitter output pin for UART1.
SPI0_MISO1
I/O
MFP2
SPI0 2nd MISO (Master In, Slave Out) pin.
Mar. 04, 2016
Page 119 of 219
Rev.2.05
M451 SERIES DATASHEET
Type
M451
Pin No.
67
68
M451 SERIES DATASHEET
69
70
Pin Name
Type
MFP*
Description
I2C1_SCL
I/O
MFP4
I2C1 clock pin.
SC0_PWR
O
MFP5
SmartCard power pin.
CLKO
O
MFP9
Clock Out (M45xD/M45xC Only)
PWM0_BRAKE0
I
MFP10
PWM0 break input 0 (M45xD/M45xC Only)
T1
I/O
MFP11
Timer1 event counter input / toggle output
(M45xD/M45xC Only)
PE.9
I/O
MFP0
General purpose digital I/O pin.
UART1_RXD
I
MFP1
Data receiver input pin for UART1.
SPI0_MOSI1
I/O
MFP2
SPI0 2nd MOSI (Master Out, Slave In) pin.
I2C1_SDA
I/O
MFP4
I2C1 data input/output pin.
SC0_RST
O
MFP5
SmartCard reset pin.
SPI1_I2SMCLK
O
MFP9
I2S1 master clock output pin. (M45xD/M45xC Only)
PWM1_BRAKE1
I
MFP10
PWM1 break input 1 (M45xD/M45xC Only)
T2
I/O
MFP11
Timer2 event counter input / toggle output
(M45xD/M45xC Only)
PE.10
I/O
MFP0
General purpose digital I/O pin.
SPI1_MISO
I/O
MFP1
SPI1 MISO (Master In, Slave Out) pin.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
UART1_nCTS
I
MFP3
Clear to Send input pin for UART1.
I2C0_SMBAL
O
MFP4
I2C0 SMBus SMBALTER# pin
SC0_DAT
I/O
MFP5
SmartCard data pin.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
I2C1_SCL
I/O
MFP11
I2C1 clock pin. (M45xD/M45xC Only)
PE.11
I/O
MFP0
General purpose digital I/O pin.
SPI1_MOSI
I/O
MFP1
SPI1 MOSI (Master Out, Slave In) pin.
SPI0_MOSI0
I/O
MFP2
SPI0 1st MOSI (Master Out, Slave In) pin.
UART1_nRTS
O
MFP3
Request to Send output pin for UART1.
I2C0_SMBSUS
O
MFP4
I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)
SC0_CLK
O
MFP5
SmartCard clock pin.
UART3_RXD
I
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
I2C1_SDA
I/O
MFP11
I2C1 data input/output pin. (M45xD/M45xC Only)
PE.12
I/O
MFP0
General purpose digital I/O pin.
SPI1_SS
I/O
MFP1
SPI1 slave select pin
SPI0_SS
I/O
MFP2
SPI0 slave select pin.
UART1_TXD
O
MFP3
Data transmitter output pin for UART1.
Mar. 04, 2016
Page 120 of 219
Rev.2.05
M451
Pin No.
71
Pin Name
Type
MFP*
Description
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
PE.13
I/O
MFP0
General purpose digital I/O pin.
SPI1_CLK
I/O
MFP1
SPI1 serial clock pin
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
I
MFP3
Data receiver input pin for UART1.
I/O
MFP4
I2C0 data input/output pin.
UART1_RXD
I2C0_SDA
72
VDDIO
A
MFP0
Power supply for PE.8~PE.13.
73
USB_VBUS
A
MFP0
Power supply from USB* host or HUB.
74
USB_D-
I
MFP0
USB differential signal D-.
75
USB_D+
I
MFP0
USB differential signal D+.
76
PF.7
I/O
MFP0
General purpose digital I/O pin. (M45xD/M45xC Only)
USB_ID
I
MFP0
USB identification. (M45xG/M45xE Only)
USB_VDD33_CAP
A
MFP0
Internal power regulator output 3.3V decoupling pin.
77
Note: This pin needs to be connected with a 1uF
capacitor.
78
PE.2
I/O
MFP0
General purpose digital I/O pin. (M45xG/M45xE Only)
PWM1_CH1
I/O
MFP6
PWM1 output/capture input. (M45xG/M45xE Only)
NC
79
I/O
MFP0
General purpose digital I/O pin.
USB_VBUS_ST
I
MFP1
USB external VBUS regulator status pin. (M45xG/M45xE
Only)
UART0_RXD
I
MFP2
Data receiver input pin for UART0.
UART0_nRTS
O
MFP3
Request to Send output pin for UART0.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
SC0_PWR
O
MFP5
SmartCard power pin.
PWM1_CH2
I/O
MFP6
PWM1 output/capture input.
EBI_AD3
I/O
MFP7
EBI address/data bus bit 3.
PA.2
I/O
MFP0
General purpose digital I/O pin.
USB_VBUS_EN
O
MFP1
USB external VBUS regulator enable pin.
(M45xG/M45xE Only)
UART0_TXD
O
MFP2
Data transmitter output pin for UART0.
UART0_nCTS
I
MFP3
Clear to Send input pin for UART0.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
SC0_RST
O
MFP5
SmartCard reset pin.
PWM1_CH3
I/O
MFP6
PWM1 output/capture input.
EBI_AD2
I/O
MFP7
EBI address/data bus bit 2.
Mar. 04, 2016
Page 121 of 219
M451 SERIES DATASHEET
80
PA.3
Not connected (M45xD/M45xC Only)
Rev.2.05
M451
Pin No.
Type
MFP*
Description
PA.1
I/O
MFP0
General purpose digital I/O pin.
UART1_nRTS
O
MFP1
Request to Send output pin for UART1.
UART1_RXD
I
MFP3
Data receiver input pin for UART1.
CAN0_TXD
I
MFP4
CAN bus transmitter input.
SC0_DAT
I/O
MFP5
SmartCard data pin.
PWM1_CH4
I/O
MFP6
PWM1 output/capture input.
EBI_AD1
I/O
MFP7
EBI address/data bus bit 1.
STADC
I/O
MFP10
ADC external trigger input. (M45xD/M45xC Only)
PA.0
I/O
MFP0
General purpose digital I/O pin.
UART1_nCTS
I
MFP1
Clear to Send input pin for UART1.
UART1_TXD
O
MFP3
Data transmitter output pin for UART1.
CAN0_RXD
I
MFP4
CAN bus receiver input.
SC0_CLK
O
MFP5
SmartCard clock pin.
PWM1_CH5
I/O
MFP6
PWM1 output/capture input.
EBI_AD0
I/O
MFP7
EBI address/data bus bit 0.
INT0
I
MFP8
External interrupt0 input pin.
SPI1_I2SMCLK
O
MFP9
I2S1 master clock output pin. (M45xD/M45xC Only)
PA.12
I/O
MFP0
General purpose digital I/O pin.
SPI1_I2SMCLK
O
MFP2
I2S1 master clock output pin.
CAN0_TXD
I
MFP4
CAN bus transmitter input.
I/O
MFP0
General purpose digital I/O pin.
I
MFP4
CAN bus receiver input.
I/O
MFP0
General purpose digital I/O pin.
UART2_nCTS
I
MFP3
Clear to Send input pin for UART2.
I2C0_SMBAL
O
MFP4
I2C0 SMBus SMBALTER# pin
PA.15
I/O
MFP0
General purpose digital I/O pin.
UART2_nRTS
O
MFP3
Request to Send output pin for UART2.
I2C0_SMBSUS
O
MFP4
I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)
87
VSS
A
MFP0
Ground pin for digital circuit.
88
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
89
AVDD
A
MFP0
Power supply for internal analog circuit.
90
VREF
I
MFP0
Voltage reference input for ADC.
81
82
83
M451 SERIES DATASHEET
84
Pin Name
PA.13
CAN0_RXD
85
86
PA.14
Note: This pin needs to be connected with a 1uF
capacitor.
91
PB.0
Mar. 04, 2016
I/O
MFP0
General purpose digital I/O pin.
Page 122 of 219
Rev.2.05
M451
Pin No.
Pin Name
MFP*
Description
EADC_CH0
A
MFP1
EADC analog input.
SPI0_MOSI1
I/O
MFP2
SPI0 2nd MOSI (Master Out, Slave In) pin.
UART2_RXD
I
MFP3
Data receiver input pin for UART2.
I/O
MFP4
Timer2 event counter input / toggle output
DAC
A
MFP5
DAC analog output
EBI_nWRL
O
MFP7
EBI low byte write enable output pin.
INT1
I
MFP8
External interrupt1 input pin.
PB.1
I/O
MFP0
General purpose digital I/O pin.
EADC_CH1
A
MFP1
EADC analog input channel 1.
SPI0_MISO1
I/O
MFP2
SPI0 2nd MISO (Master In, Slave Out) pin.
UART2_TXD
O
MFP3
Data transmitter output pin for UART2.
T3
I/O
MFP4
Timer3 event counter input / toggle output
SC0_RST
O
MFP5
SmartCard reset pin.
PWM0_SYNC_OUT
O
MFP6
PWM0 counter synchronous trigger output pin.
EBI_nWRH
O
MFP7
EBI high byte write enable output pin
PB.2
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 2.
SPI0_CLK
I/O
MFP2
SPI0 serial clock pin.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin
UART1_RXD
I
MFP4
Data receiver input pin for UART1.
SC0_CD
I
MFP5
SmartCard card detect pin.
UART3_RXD
I
MFP9
Data receiver input pin for UART3. (M45xD/M45xC Only)
T2_EXT
I
MFP11
Timer2 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
EADC_CH3
A
MFP1
EADC analog input channel 3.
SPI0_MISO0
I/O
MFP2
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
UART1_TXD
O
MFP4
Data transmitter output pin for UART1.
UART3_TXD
O
MFP9
Data transmitter output pin for UART3. (M45xD/M45xC
Only)
T0_EXT
I
MFP11
Timer0 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 4.
SPI0_SS
I/O
MFP2
SPI0 slave select pin.
SPI1_SS
I/O
MFP3
SPI1 slave select pin
T2
92
93
EADC_CH2
94
95
PB.3
PB.4
EADC_CH4
Mar. 04, 2016
Page 123 of 219
Rev.2.05
M451 SERIES DATASHEET
Type
M451
Pin No.
96
97
Pin Name
Type
MFP*
Description
UART1_nCTS
I
MFP4
Clear to Send input pin for UART1.
ACMP0_N
A
MFP5
Comparator0 negative input pin.
EBI_AD7
I/O
MFP7
EBI address/data bus bit 7.
UART2_TXD
O
MFP9
Data transmitter output pin for UART2. (M45xD/M45xC
Only)
T1_EXT
I
MFP11
Timer1 external counter input. (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
EADC_CH5
A
MFP1
EADC analog input channel 5.
UART1_nRTS
O
MFP4
Request to Send output pin for UART1.
PWM0_CH2
I/O
MFP6
PWM0 output/capture input.
PB.9
I/O
MFP0
General purpose digital I/O pin. (M45xG/M45xE Only)
A
MFP1
EADC analog input channel 6. (M45xG/M45xE Only)
PB.8
EADC_CH6
NC
98
PB.10
EADC_CH7
Not connected (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin. (M45xG/M45xE Only)
A
MFP1
EADC analog input channel 7. (M45xG/M45xE Only)
NC
99
PB.11
EADC_CH8
100
PB.12
EADC_CH9
Not connected (M45xD/M45xC Only)
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 8.
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC analog input channel 9.
M451 SERIES DATASHEET
Mar. 04, 2016
Page 124 of 219
Rev.2.05
M451
4.3.10 GPIO Multi-function Pin Summary
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0.
PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5.
Group
ACMP0
ACMP1
GPIO
MFP*
Type
ACMP0_N
PB.4
MFP5
A
Comparator0 negative input pin.
ACMP0_O
PD.6
MFP5
O
Comparator0 output .
ACMP0_O
PD.7
MFP5
O
Comparator0 output .
ACMP0_P0
PB.7
MFP5
A
Comparator0 positive input pin.
ACMP0_P1
PB.6
MFP5
A
Comparator0 positive input pin.
ACMP0_P2
PB.5
MFP5
A
Comparator0 positive input pin.
ACMP0_P3
PB.15
MFP5
A
Comparator0 positive input pin.
ACMP1_N
PD.0
MFP5
A
Comparator1 negative input pin.
ACMP1_O
PC.2
MFP5
O
Comparator1 output .
ACMP1_O
PC.6
MFP5
O
Comparator1 output .
ACMP1_P0
PD.3
MFP5
A
Comparator1 positive input pin.
ACMP1_P1
PD.2
MFP5
A
Comparator1 positive input pin.
ACMP1_P2
PD.1
MFP5
A
Comparator1 positive input pin.
ACMP1_P3
PD.9
MFP5
A
Comparator1 positive input pin.
EADC_CH0
PB.0
MFP1
A
ADC0 analog input.
EADC_CH1
PB.1
MFP1
A
ADC1 analog input.
EADC_CH2
PB.2
MFP1
A
ADC2 analog input.
EADC_CH3
PB.3
MFP1
A
ADC3 analog input.
EADC_CH4
PB.4
MFP1
A
ADC4 analog input.
EADC_CH5
PB.8
MFP1
A
ADC5 analog input.
EADC_CH6
PB.9
MFP1
A
ADC6 analog input. (M45xG/M45xE Only)
EADC_CH6
PD.0
MFP1
A
ADC6 analog input. (M45xD/M45xC Only)
EADC_CH7
PB.10
MFP1
A
ADC7 analog input. (M45xG/M45xE Only)
EADC_CH7
PD.8
MFP1
A
ADC7 analog input. (M45xD/M45xC Only)
EADC_CH8
PB.11
MFP1
A
ADC8 analog input.
EADC_CH9
PB.12
MFP1
A
ADC9 analog input.
EADC_CH10
PB.13
MFP1
A
ADC10 analog input. (M45xG/M45xE Only)
EADC_CH10
PD.9
MFP1
A
ADC10 analog input. (M45xD/M45xC Only)
EADC_CH11
PB.14
MFP1
A
ADC11 analog input. (M45xG/M45xE Only)
EADC_CH11
PD.1
MFP1
A
ADC11 analog input. (M45xD/M45xC Only)
EADC_CH12
PB.15
MFP1
A
ADC12 analog input.
Mar. 04, 2016
Page 125 of 219
Description
Rev.2.05
M451 SERIES DATASHEET
EADC
Pin Name
M451
Group
Pin Name
GPIO
MFP*
Type
Description
EADC_CH13
PB.5
MFP1
A
ADC13 analog input.
EADC_CH14
PB.6
MFP1
A
ADC14 analog input.
EADC_CH15
PB.7
MFP1
A
ADC15 analog input.
STADC
PD.2
MFP1
I
ADC external trigger input.
STADC
PB.7
MFP10
I
ADC external trigger input. (M45xD/M45xC
Only)
STADC
PA.1
MFP10
I
ADC external trigger input. (M45xD/M45xC
Only)
CAN0_RXD
PC.1
MFP4
I
CAN bus receiver input.
CAN0_RXD
PA.0
MFP4
I
CAN bus receiver input.
CAN0_RXD
PA.13
MFP4
I
CAN bus receiver input.
CAN0_TXD
PC.0
MFP4
I
CAN bus transmitter input.
CAN0_TXD
PA.1
MFP4
I
CAN bus transmitter input.
CAN0_TXD
PA.12
MFP4
I
CAN bus transmitter input.
CLKO
PD.5
MFP1
O
Clock Out
CLKO
PD.6
MFP1
O
Clock Out
CLKO
PC.1
MFP1
O
Clock Out
CLKO
PE.8
MFP9
O
Clock Out (M45xD/M45xC Only)
DAC
PB.0
MFP5
A
DAC analog output
STDAC
PC.1
MFP2
I
DAC external trigger input.
EBI_AD0
PA.0
MFP7
I/O
EBI address/data bus bit 0.
EBI_AD1
PA.1
MFP7
I/O
EBI address/data bus bit 1.
EBI_AD2
PA.2
MFP7
I/O
EBI address/data bus bit 2.
EBI_AD3
PA.3
MFP7
I/O
EBI address/data bus bit 3.
EBI_AD4
PB.7
MFP7
I/O
EBI address/data bus bit 4.
EBI_AD4
PA.4
MFP7
I/O
EBI address/data bus bit 4.
EBI_AD5
PB.6
MFP7
I/O
EBI address/data bus bit 5.
EBI_AD5
PA.5
MFP7
I/O
EBI address/data bus bit 5.
EBI_AD6
PB.5
MFP7
I/O
EBI address/data bus bit 6.
EBI_AD6
PA.6
MFP7
I/O
EBI address/data bus bit 6.
EBI_AD7
PA.7
MFP7
I/O
EBI address/data bus bit 7.
EBI_AD7
PB.4
MFP7
I/O
EBI address/data bus bit 7.
EBI_AD8
PC.0
MFP7
I/O
EBI address/data bus bit 8.
EBI_AD9
PC.1
MFP7
I/O
EBI address/data bus bit 9.
EBI_AD10
PC.2
MFP7
I/O
EBI address/data bus bit 10.
CAN0
CLKO
DAC
M451 SERIES DATASHEET
EBI
Mar. 04, 2016
Page 126 of 219
Rev.2.05
M451
Group
I2C1
GPIO
MFP*
Type
EBI_AD11
PC.3
MFP7
I/O
EBI address/data bus bit 11.
EBI_AD12
PC.4
MFP7
I/O
EBI address/data bus bit 12.
EBI_AD13
PC.5
MFP7
I/O
EBI address/data bus bit 13.
EBI_AD14
PC.6
MFP7
I/O
EBI address/data bus bit 14.
EBI_AD15
PC.7
MFP7
I/O
EBI address/data bus bit 15.
EBI_ADR16
PD.12
MFP7
O
EBI address bus bit 16.
EBI_ADR17
PD.13
MFP7
O
EBI address bus bit 17.
EBI_ADR18
PD.14
MFP7
O
EBI address bus bit 18.
EBI_ADR19
PD.15
MFP7
O
EBI address bus bit 19.
EBI_ALE
PD.9
MFP7
O
EBI address latch enable output pin.
EBI_ALE
PE.5
MFP7
O
EBI address latch enable output pin.
EBI_MCLK
PD.3
MFP7
O
EBI external clock output pin
EBI_nCS0
PD.8
MFP7
O
EBI chip select 0 enable output pin.
EBI_nCS0
PE.4
MFP7
O
EBI chip select 0 enable output pin.
EBI_nCS1
PB.15
MFP7
O
EBI chip select 1 enable output pin.
EBI_nCS1
PE.0
MFP7
O
EBI chip select 1 enable output pin.
EBI_nRD
PD.1
MFP7
O
EBI read enable output pin.
EBI_nRD
PD.7
MFP7
O
EBI read enable output pin.
EBI_nWR
PD.2
MFP7
O
EBI write enable output pin.
EBI_nWR
PD.6
MFP7
O
EBI write enable output pin.
EBI_nWRH
PB.1
MFP7
O
EBI high byte write enable output pin
EBI_nWRL
PB.0
MFP7
O
EBI low byte write enable output pin.
I2C0_SCL
PD.5
MFP3
I/O
I2C0 clock pin.
I2C0_SCL
PE.12
MFP4
I/O
I2C0 clock pin.
I2C0_SCL
PA.3
MFP4
I/O
I2C0 clock pin.
I2C0_SDA
PD.4
MFP3
I/O
I2C0 data input/output pin.
I2C0_SDA
PE.13
MFP4
I/O
I2C0 data input/output pin.
I2C0_SDA
PA.2
MFP4
I/O
I2C0 data input/output pin.
I2C0_SMBAL
PE.10
MFP4
O
I2C0 SMBus SMBALTER# pin
I2C0_SMBAL
PA.14
MFP4
O
I2C0 SMBus SMBALTER# pin
I2C0_SMBSUS
PE.11
MFP4
O
I2C0 SMBus SMBSUS# pin (PMBus
CONTROL pin)
I2C0_SMBSUS
PA.15
MFP4
O
I2C0 SMBus SMBSUS# pin (PMBus
CONTROL pin)
I2C1_SCL
PF.3
MFP3
I/O
I2C1 clock pin.
Mar. 04, 2016
Page 127 of 219
Description
Rev.2.05
M451 SERIES DATASHEET
I2C0
Pin Name
M451
Group
Pin Name
GPIO
MFP*
Type
I2C1_SCL
PC.4
MFP3
I/O
I2C1 clock pin.
I2C1_SCL
PE.4
MFP3
I/O
I2C1 clock pin.
I2C1_SCL
PE.8
MFP4
I/O
I2C1 clock pin.
I2C1_SCL
PE.10
MFP11
I/O
I2C1 clock pin. (M45xD/M45xC Only)
I2C1_SDA
PF.4
MFP3
I/O
I2C1 data input/output pin.
I2C1_SDA
PE.0
MFP3
I/O
I2C1 data input/output pin.
I2C1_SDA
PE.5
MFP3
I/O
I2C1 data input/output pin.
I2C1_SDA
PE.9
MFP4
I/O
I2C1 data input/output pin.
I2C1_SDA
PE.11
MFP11
I/O
I2C1 data input/output pin. (M45xD/M45xC
Only)
I2C1_SMBAL
PC.6
MFP3
O
I2C1 SMBus SMBALTER# pin
I2C1_SMBSUS
PC.7
MFP3
O
I2C1 SMBus SMBSUS# pin (PMBus
CONTROL pin)
SPI1_I2SMCLK
PD.0
MFP2
O
I2S1 master clock output pin.
SPI1_I2SMCLK
PA.12
MFP2
O
I2S1 master clock output pin.
SPI1_I2SMCLK
PE.9
MFP9
O
I2S1 master clock output pin. (M45xD/M45xC
Only)
SPI1_I2SMCLK
PA.0
MFP9
O
I2S1 master clock output pin. (M45xD/M45xC
Only)
SPI2_I2SMCLK
PC.9
MFP2
O
I2S2 master clock output pin. (M45xG/M45xE
Only)
SPI2_I2SMCLK
PC.5
MFP2
O
I2S2 master clock output pin. (M45xG/M45xE
Only)
ICE_CLK
PF.5
MFP1
I
Serial wired debugger clock pin
ICE_DAT
PF.6
MFP1
I/O
Serial wired debugger data pin
INT0
PD.2
MFP8
I
External interrupt0 input pin.
INT0
PE.4
MFP8
I
External interrupt0 input pin.
INT0
PA.0
MFP8
I
External interrupt0 input pin.
INT1
PD.3
MFP8
I
External interrupt1 input pin.
INT1
PE.5
MFP8
I
External interrupt1 input pin.
INT1
PB.0
MFP8
I
External interrupt1 input pin.
INT2
INT2
PC.0
MFP8
I
External interrupt2 input pin.
INT3
INT3
PD.0
MFP8
I
External interrupt3 input pin.
INT4
INT4
PE.0
MFP8
I
External interrupt4 input pin.
INT5
INT5
PF.0
MFP8
I
External interrupt5 input pin.
PWM0_BRAKE0
PD.2
MFP6
I
PWM0 break input 0
PWM0_BRAKE0
PD.4
MFP5
I
PWM0 break input 0
I2S1
Description
I2S2
M451 SERIES DATASHEET
ICE
INT0
INT1
PWM0
Mar. 04, 2016
Page 128 of 219
Rev.2.05
M451
Group
GPIO
MFP*
Type
Description
PWM0_BRAKE0
PE.8
MFP10
I
PWM0 break input 0 (M45xD/M45xC Only)
PWM0_BRAKE1
PD.3
MFP6
I
PWM0 break input 1
PWM0_BRAKE1
PD.5
MFP5
I
PWM0 break input 1
PWM0_CH0
PC.0
MFP6
I/O
PWM0 output/capture input.
PWM0_CH0
PE.0
MFP6
I/O
PWM0 output/capture input.
PWM0_CH1
PC.1
MFP6
I/O
PWM0 output/capture input.
PWM0_CH1
PE.1
MFP6
I/O
PWM0 output/capture input.
PWM0_CH2
PC.2
MFP6
I/O
PWM0 output/capture input.
PWM0_CH2
PB.8
MFP6
I/O
PWM0 output/capture input.
PWM0_CH3
PE.3
MFP6
I/O
PWM0 output/capture input.
PWM0_CH3
PC.3
MFP6
I/O
PWM0 output/capture input.
PWM0_CH4
PC.4
MFP6
I/O
PWM0 output/capture input.
PWM0_CH5
PD.6
MFP6
I/O
PWM0 output/capture input.
PWM0_CH5
PD.7
MFP6
I/O
PWM0 output/capture input.
PWM0_CH5
PC.5
MFP6
I/O
PWM0 output/capture input.
PWM0_SYNC_IN
PD.1
MFP2
I
PWM0 counter synchronous trigger input pin.
PWM0_SYNC_IN
PD.7
MFP3
I
PWM0 counter synchronous trigger input pin.
PWM0_SYNC_OUT
PB.1
MFP6
O
PWM0 counter synchronous trigger output pin.
PWM1_BRAKE0
PE.4
MFP6
I
PWM1 break input 0
PWM1_BRAKE1
PE.5
MFP6
I
PWM1 break input 1
PWM1_BRAKE1
PE.9
MFP10
I
PWM1 break input 1 (M45xD/M45xC Only)
PWM1_CH0
PD.12
MFP6
I/O
PWM1 output/capture input.
PWM1_CH0
PC.9
MFP6
I/O
PWM1 output/capture input.
PWM1_CH0
PC.6
MFP6
I/O
PWM1 output/capture input.
PWM1_CH0
PC.15
MFP6
I/O
PWM1 output/capture input.
PWM1_CH1
PD.13
MFP6
I/O
PWM1 output/capture input.
PWM1_CH1
PC.10
MFP6
I/O
PWM1 output/capture input.
PWM1_CH1
PC.7
MFP6
I/O
PWM1 output/capture input.
PWM1_CH1
PE.2
MFP6
I/O
PWM1 output/capture input.
PWM1_CH2
PD.14
MFP6
I/O
PWM1 output/capture input.
PWM1_CH2
PC.11
MFP6
I/O
PWM1 output/capture input.
PWM1_CH2
PA.3
MFP6
I/O
PWM1 output/capture input.
PWM1_CH3
PD.15
MFP6
I/O
PWM1 output/capture input.
PWM1_CH3
PC.12
MFP6
I/O
PWM1 output/capture input.
PWM1
Mar. 04, 2016
Page 129 of 219
Rev.2.05
M451 SERIES DATASHEET
Pin Name
M451
Group
Pin Name
GPIO
MFP*
Type
Description
PWM1_CH3
PA.2
MFP6
I/O
PWM1 output/capture input.
PWM1_CH4
PC.13
MFP6
I/O
PWM1 output/capture input.
PWM1_CH4
PA.1
MFP6
I/O
PWM1 output/capture input.
PWM1_CH5
PC.14
MFP6
I/O
PWM1 output/capture input.
PWM1_CH5
PA.0
MFP6
I/O
PWM1 output/capture input.
SC0_CD
PE.0
MFP5
I
SmartCard card detect pin.
SC0_CD
PE.1
MFP5
I
SmartCard card detect pin.
SC0_CD
PB.2
MFP5
I
SmartCard card detect pin.
SC0_CLK
PE.11
MFP5
O
SmartCard clock pin.
SC0_CLK
PA.0
MFP5
O
SmartCard clock pin.
SC0_DAT
PE.10
MFP5
I/O
SmartCard data pin.
SC0_DAT
PA.1
MFP5
I/O
SmartCard data pin.
SC0_PWR
PE.4
MFP5
O
SmartCard power pin.
SC0_PWR
PE.8
MFP5
O
SmartCard power pin.
SC0_PWR
PA.3
MFP5
O
SmartCard power pin.
SC0_RST
PE.5
MFP5
O
SmartCard reset pin.
SC0_RST
PE.9
MFP5
O
SmartCard reset pin.
SC0_RST
PA.2
MFP5
O
SmartCard reset pin.
SC0_RST
PB.1
MFP5
O
SmartCard reset pin.
SPI0_CLK
PB.7
MFP2
I/O
SPI0 serial clock pin.
SPI0_CLK
PE.13
MFP2
I/O
SPI0 serial clock pin.
SPI0_CLK
PB.2
MFP2
I/O
SPI0 serial clock pin.
SPI0_MISO0
PB.6
MFP2
I/O
SPI0 1st MISO (Master In, Slave Out) pin.
SPI0_MISO0
PE.10
MFP2
I/O
SPI0 1st MISO (Master In, Slave Out) pin.
SPI0_MISO0
PB.3
MFP2
I/O
SPI0 1st MISO (Master In, Slave Out) pin.
SPI0_MISO1
PE.8
MFP2
I/O
SPI0 2nd MISO (Master In, Slave Out) pin.
SPI0_MISO1
PB.1
MFP2
I/O
SPI0 2nd MISO (Master In, Slave Out) pin.
SPI0_MOSI0
PB.5
MFP2
I/O
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI0_MOSI0
PE.11
MFP2
I/O
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI0_MOSI1
PE.9
MFP2
I/O
SPI0 2nd MOSI (Master Out, Slave In) pin.
SPI0_MOSI1
PB.0
MFP2
I/O
SPI0 2nd MOSI (Master Out, Slave In) pin.
SPI0_SS
PE.12
MFP2
I/O
SPI0 slave select pin.
SPI0_SS
PB.4
MFP2
I/O
SPI0 slave select pin.
SPI1_CLK
PB.7
MFP3
I/O
SPI1 serial clock pin
SC0
M451 SERIES DATASHEET
SPI0
SPI1
Mar. 04, 2016
Page 130 of 219
Rev.2.05
M451
Group
GPIO
MFP*
Type
SPI1_CLK
PD.4
MFP2
I/O
SPI1 serial clock pin
SPI1_CLK
PA.7
MFP2
I/O
SPI1 serial clock pin
SPI1_CLK
PE.13
MFP1
I/O
SPI1 serial clock pin
SPI1_CLK
PB.2
MFP3
I/O
SPI1 serial clock pin
SPI1_MISO
PB.6
MFP3
I/O
SPI1 MISO (Master In, Slave Out) pin.
SPI1_MISO
PD.5
MFP2
I/O
SPI1 MISO (Master In, Slave Out) pin.
SPI1_MISO
PA.6
MFP2
I/O
SPI1 MISO (Master In, Slave Out) pin.
SPI1_MISO
PE.10
MFP1
I/O
SPI1 MISO (Master In, Slave Out) pin.
SPI1_MISO
PB.3
MFP3
I/O
SPI1 MISO (Master In, Slave Out) pin.
SPI1_MOSI
PB.5
MFP3
I/O
SPI1 MOSI (Master Out, Slave In) pin.
SPI1_MOSI
PE.3
MFP2
I/O
SPI1 MOSI (Master Out, Slave In) pin.
SPI1_MOSI
PA.5
MFP2
I/O
SPI1 MOSI (Master Out, Slave In) pin.
SPI1_MOSI
PE.11
MFP1
I/O
SPI1 MOSI (Master Out, Slave In) pin.
SPI1_SS
PD.6
MFP2
I/O
SPI1 slave select pin
SPI1_SS
PA.4
MFP2
I/O
SPI1 slave select pin
SPI1_SS
PE.12
MFP1
I/O
SPI1 slave select pin
SPI1_SS
PB.4
MFP3
I/O
SPI1 slave select pin
SPI2_CLK
PD.15
MFP2
I/O
SPI2 serial clock pin. (M45xG/M45xE Only)
SPI2_CLK
PC.12
MFP2
I/O
SPI2 serial clock pin. (M45xG/M45xE Only)
SPI2_CLK
PC.0
MFP2
I/O
SPI2 serial clock pin. (M45xG/M45xE Only)
SPI2_CLK
PE.0
MFP2
I/O
SPI2 serial clock pin. (M45xG/M45xE Only)
SPI2_MISO
PD.14
MFP2
I/O
SPI2 MISO (Master In, Slave Out) pin.
(M45xG/M45xE Only)
SPI2_MISO
PC.11
MFP2
I/O
SPI2 MISO (Master In, Slave Out) pin.
(M45xG/M45xE Only)
SPI2_MISO
PC.4
MFP2
I/O
SPI2 MISO (Master In, Slave Out) pin.
(M45xG/M45xE Only)
SPI2_MOSI
PD.13
MFP2
I/O
SPI2 MOSI (Master Out, Slave In) pin.
(M45xG/M45xE Only)
SPI2_MOSI
PC.10
MFP2
I/O
SPI2 MOSI (Master Out, Slave In) pin.
(M45xG/M45xE Only)
SPI2_MOSI
PC.3
MFP2
I/O
SPI2 MOSI (Master Out, Slave In) pin.
(M45xG/M45xE Only)
SPI2_SS
PD.12
MFP2
I
SPI2 slave select pin. (M45xG/M45xE Only)
SPI2_SS
PC.13
MFP2
I
SPI2 slave select pin. (M45xG/M45xE Only)
SPI2_SS
PC.2
MFP2
I
SPI2 slave select pin. (M45xG/M45xE Only)
TAMPER
PF.2
MFP1
I/O
SPI2
TAMPER
Mar. 04, 2016
Page 131 of 219
Description
TAMPER detector loop pin
Rev.2.05
M451 SERIES DATASHEET
Pin Name
M451
Group
TMR0
Pin Name
GPIO
MFP*
Type
Description
T0
PD.1
MFP6
I/O
Timer0event counter input / toggle output
T0
PD.4
MFP6
I/O
Timer0event counter input / toggle output
T0_EXT
PD.2
MFP3
I
Timer0 external counter input
T0_EXT
PA.7
MFP3
I
Timer0 external counter input
T0_EXT
PB.3
MFP11
I
Timer0 external counter input (M45xD/M45xC
Only)
T1
PD.5
MFP6
I/O
Timer1 event counter input / toggle output
T1
PD.7
MFP4
I/O
Timer1 event counter input / toggle output
T1
PE.8
MFP11
I/O
Timer1 event counter input / toggle output
(M45xD/M45xC Only)
T1_EXT
PD.3
MFP3
I
Timer1 external counter input
T1_EXT
PA.6
MFP3
I
Timer1 external counter input
T1_EXT
PB.4
MFP11
I
Timer1 external counter input (M45xD/M45xC
Only)
T2
PD.3
MFP1
I/O
Timer2 event counter input / toggle output
T2
PD.10
MFP4
I/O
Timer2 event counter input / toggle output
T2
PB.0
MFP4
I/O
Timer2 event counter input / toggle output
T2
PE.9
MFP11
I/O
Timer2 event counter input / toggle output
(M45xD/M45xC Only)
T2_EXT
PE.0
MFP4
I
Timer2 external counter input
T2_EXT
PA.5
MFP3
I
Timer2 external counter input
T2_EXT
PB.2
MFP11
I
Timer2 external counter input (M45xD/M45xC
Only)
T3
PD.11
MFP4
I/O
Timer3 event counter input / toggle output
T3
PB.1
MFP4
I/O
Timer3 event counter input / toggle output
T3
PD.0
MFP11
I/O
Timer3 event counter input / toggle output
(M45xD/M45xC Only)
T3_EXT
PE.6
MFP3
I
Timer3 external counter input
T3_EXT
PE.1
MFP3
I
Timer3 external counter input
T3_EXT
PC.0
MFP11
I
Timer3 external counter input (M45xD/M45xC
Only)
UART0_RXD
PD.0
MFP3
I
Data receiver input pin for UART0.
UART0_RXD
PD.6
MFP3
I
Data receiver input pin for UART0.
UART0_RXD
PA.3
MFP2
I
Data receiver input pin for UART0.
UART0_RXD
PC.7
MFP9
I
Data receiver input pin for UART0.
(M45xD/M45xC Only)
UART0_TXD
PD.1
MFP3
O
Data transmitter output pin for UART0.
UART0_TXD
PA.2
MFP2
O
Data transmitter output pin for UART0.
TMR1
TMR2
M451 SERIES DATASHEET
TMR3
UART0
Mar. 04, 2016
Page 132 of 219
Rev.2.05
M451
Group
Pin Name
GPIO
MFP*
Type
Description
UART0_TXD
PC.6
MFP9
O
Data transmitter output pin for UART0.
(M45xD/M45xC Only)
UART0_nCTS
PA.2
MFP3
I
Clear to Send input pin for UART0.
UART0_nRTS
PA.3
MFP3
O
Request to Send output pin for UART0.
UART1_RXD
PE.9
MFP1
I
Data receiver input pin for UART1.
UART1_RXD
PE.13
MFP3
I
Data receiver input pin for UART1.
UART1_RXD
PA.1
MFP3
I
Data receiver input pin for UART1.
UART1_RXD
PB.2
MFP4
I
Data receiver input pin for UART1.
UART1_TXD
PE.8
MFP1
O
Data transmitter output pin for UART1.
UART1_TXD
PE.12
MFP3
O
Data transmitter output pin for UART1.
UART1_TXD
PA.0
MFP3
O
Data transmitter output pin for UART1.
UART1_TXD
PB.3
MFP4
O
Data transmitter output pin for UART1.
UART1_nCTS
PE.10
MFP3
I
Clear to Send input pin for UART1.
UART1_nCTS
PA.0
MFP1
I
Clear to Send input pin for UART1.
UART1_nCTS
PB.4
MFP4
I
Clear to Send input pin for UART1.
UART1_nRTS
PE.11
MFP3
O
Request to Send output pin for UART1.
UART1_nRTS
PA.1
MFP1
O
Request to Send output pin for UART1.
UART1_nRTS
PB.8
MFP4
O
Request to Send output pin for UART1.
UART2_RXD
PC.3
MFP3
I
Data receiver input pin for UART2.
UART2_RXD
PB.0
MFP3
I
Data receiver input pin for UART2.
UART2_RXD
PB.5
MFP9
I
Data receiver input pin for UART2.
(M45xD/M45xC Only)
UART2_TXD
PC.2
MFP3
O
Data transmitter output pin for UART2.
UART2_TXD
PB.1
MFP3
O
Data transmitter output pin for UART2.
UART2_TXD
PB.4
MFP9
O
Data transmitter output pin for UART2.
(M45xD/M45xC Only)
UART2_nCTS
PC.0
MFP3
I
Clear to Send input pin for UART2.
UART2_nCTS
PA.14
MFP3
I
Clear to Send input pin for UART2.
UART2_nRTS
PC.1
MFP3
O
Request to Send output pin for UART2.
UART2_nRTS
PA.15
MFP3
O
Request to Send output pin for UART2.
UART3_RXD
PD.13
MFP3
I
Data receiver input pin for UART3.
UART3_RXD
PA.9
MFP3
I
Data receiver input pin for UART3.
UART3_RXD
PB.2
MFP9
I
Data receiver input pin for UART3.
(M45xD/M45xC Only)
UART3_RXD
PE.11
MFP9
I
Data receiver input pin for UART3.
(M45xD/M45xC Only)
UART3_RXD
PC.1
MFP9
I
Data receiver input pin for UART3.
UART1
UART3
Mar. 04, 2016
Page 133 of 219
Rev.2.05
M451 SERIES DATASHEET
UART2
M451
Group
Pin Name
GPIO
MFP*
Type
Description
(M45xD/M45xC Only)
UART3_TXD
PD.12
MFP3
O
Data transmitter output pin for UART3.
UART3_TXD
PA.8
MFP3
O
Data transmitter output pin for UART3.
UART3_TXD
PB.3
MFP9
O
Data transmitter output pin for UART3.
(M45xD/M45xC Only)
UART3_TXD
PE.10
MFP9
O
Data transmitter output pin for UART3.
(M45xD/M45xC Only)
UART3_TXD
PC.0
MFP9
O
Data transmitter output pin for UART3.
(M45xD/M45xC Only)
UART3_nCTS
PD.14
MFP3
I
Clear to Send input pin for UART3.
UART3_nCTS
PA.10
MFP3
I
Clear to Send input pin for UART3.
UART3_nRTS
PD.15
MFP3
O
Request to Send output pin for UART3.
UART3_nRTS
PA.11
MFP3
O
Request to Send output pin for UART3.
USB_VBUS_EN
PC.4
MFP4
O
USB external VBUS regulator enable pin.
(M45xG/M45xE Only)
USB_VBUS_EN
PA.2
MFP1
O
USB external VBUS regulator enable pin.
(M45xG/M45xE Only)
USB_VBUS_ST
PC.3
MFP4
I
USB external VBUS regulator status pin.
(M45xG/M45xE Only)
USB_VBUS_ST
PA.3
MFP1
I
USB external VBUS regulator status pin.
(M45xG/M45xE Only)
X32_IN
PF.1
MFP1
I
External 32.768 kHZ (low speed) crystal input
pin.
X32_OUT
PF.0
MFP1
O
External 32.768 kHZ (low speed) crystal output
pin.
XT1_IN
PF.4
MFP1
I
External 4~20 MHz (high speed) crystal input
pin.
XT1_OUT
PF.3
MFP1
O
External 4~20 MHz (high speed) crystal output
pin.
USB
LXT
M451 SERIES DATASHEET
HXT
Table 4-1 M451 GPIO Multi-function Table
Mar. 04, 2016
Page 134 of 219
Rev.2.05
M451
5
BLOCK DIAGRAM
5.1 NuMicro® M451 Block Diagram
®
Figure 5.1-1 NuMicro M45xG/M45xE Block Diagram
M451 SERIES DATASHEET
Mar. 04, 2016
Page 135 of 219
Rev.2.05
M451
®
Figure 5.1-2 NuMicro M45xD/M45xC Block Diagram
M451 SERIES DATASHEET
Mar. 04, 2016
Page 136 of 219
Rev.2.05
M451
6
FUNCTIONAL DESCRIPTION
6.1 ARM® Cortex® -M4 Core
®
The Cortex -M4 processor, a configurable, multistage, 32-bit RISC processor, has three AMBA
AHB-Lite interfaces for best parallel performance and includes an NVIC component. The
processor with optional hardware debug functionality can execute Thumb code and is compatible
with other Cortex-M profile processors. The profile supports two modes -Thread mode and
Handler mode. Handler mode is entered as a result of an exception. An exception return can only
be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result of
®
®
an exception return. The Cortex -M4F is a processor with the same capability as the Cortex -M4
®
processor and includes floating point arithmetic functionality. The NuMicro M451 family is
®
®
embedded with Cortex -M4F processor. Throughout this document, the name Cortex -M4 refers
®
®
to both Cortex -M4 and Cortex -M4F processors. The following figure shows the functional
controller of the processor.
M451 SERIES DATASHEET
®
Figure 6.1-1 Cortex -M4 Block Diagram
®
Cortex -M4 processor features:

Mar. 04, 2016
A low gate count processor core, with low latency interrupt processing that has:

A subset of the Thumb instruction set, defined in the ARMv7-M Architecture
Reference Manual

Banked Stack Pointer (SP)
Page 137 of 219
Rev.2.05
M451


M451 SERIES DATASHEET



Hardware integer divide instructions, SDIV and UDIV

Handler and Thread modes

Thumb and Debug states

Support for interruptible-continued instructions LDM, STM, PUSH, and POP for
low interrupt latency

Automatic processor state saving and restoration for low latency Interrupt
Service Routine (ISR) entry and exit

Support for ARMv6 big-endian byte-invariant or little-endian accesses

Support for ARMv6 unaligned accesses
®
Floating Point Unit (FPU) in the Cortex -M4F processor providing:

32-bit instructions for single-precision (C float) data-processing operations

Combined Multiply and Accumulate instructions for increased precision (Fused
MAC)

Hardware support for conversion, addition, subtraction, multiplication with
optional accumulate, division, and square-root

Hardware support for denormals and all IEEE rounding modes

32 dedicated 32-bit single precision registers, also addressable as 16 doubleword registers

Decoupled three stage pipeline
Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core
to achieve low latency interrupt processing. Features include:
External interrupts. Configurable from 1 to 240 (the NuMicro M451 family
configured with 64 interrupts)

Bits of priority, configurable from 3 to 8

Dynamic reprioritization of interrupts

Priority grouping which enables selection of preempting interrupt levels and
nonpreempting interrupt levels

Support for tril-chaining and late arrival of interrupts, which enables back-to-back
interrupt processing without the overhead of state saving and restoration
between interrupts.

Processor state automatically saved on interrupt entry, and restored on interrupt
exit with on instruction overhead

Support for Wake-up Interrupt Controller (WIC) with Ultra-low Power Sleep mode
Memory Protection Unit (MPU). An optional MPU for memory protection, including:

Eight memory regions

Sub Region Disable (SRD), enabling efficient use of memory regions

The ability to enable a background region that implements the default memory
map attributes
Low-cost debug solution that features:

Mar. 04, 2016
®

Debug access to all memory and registers in the system, including access to
memory mapped devices, access to internal core registers when the core is
halted, and access to debug control registers even while SYSRESETn is
Page 138 of 219
Rev.2.05
M451
asserted.


Serial Wire Debug Port(SW-DP) or Serial Wire JTAG Debug Port (SWJ-DP)
debug access

Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
and code patches

Optional Data Watchpoint and Trace (DWT) unit for implementing watchpoints,
data tracing, and system profiling

Optional Instrumentation Trace Macrocell (ITM) for support of printf() style
debugging

Optional Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
(TPA), including Single Wire Output (SWO) mode

Optional Embedded Trace Macrocell (ETM) for instruction trace.
Bus interfaces:

Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode,
Dcode, and System bus interfaces

Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB)
interface

Bit-band support that includes atomic bit-band write and read operations.

Memory access alignment

Write buffer for buffering of write data

Exclusive access transfers for multiprocessor systems
M451 SERIES DATASHEET
Mar. 04, 2016
Page 139 of 219
Rev.2.05
M451
6.2 System Manager
6.2.1 Overview
The system manager provides the functions of system control, power modes, wake-up sources,
reset sources, system memory map, product ID and multi-function pin control. The following
sections describe the functions for

System Reset


Power Modes and Wake-up Sources
System Power Distribution

SRAM Memory Organization

System Control Register for Part Number ID, Chip Reset and Multi-function Pin
Control

System Timer (SysTick)

Nested Vectored Interrupt Controller (NVIC)

System Control register
6.2.2 System Reset
The system reset can be issued by one of the events listed below. These reset event flags can be
read from SYS_RSTSTS register to determine the reset source. Hardware reset can reset chip
through peripheral reset signals. Software reset can trigger reset through control registers.
M451 SERIES DATASHEET

Hardware Reset Sources

– Power-on Reset (POR)
– Low level on the nRESET pin
– Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)
– Low Voltage Reset (LVR)
– Brown-out Detector Reset (BOD Reset)
– CPU Lockup Reset (M45xD/M45xC Only)
Software Reset Sources
–
–
–
Mar. 04, 2016
CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0])
MCU Reset to reboot but keeping the booting setting from APROM or LDROM by
writing 1 to SYSRESETREQ (AIRCR[2])
CPU Reset for Cortex® -M4 core Only by writing 1 to CPURST (SYS_IPRST0[1])
Page 140 of 219
Rev.2.05
M451
Glitch Filter
36 us
nRESET
~50k ohm
@5v
VDD
POROFF(SYS_PORCTL[15:0])
Power-on
Reset
LVREN(SYS_BODCTL[7])
AVDD
Reset Pulse Width
3.2ms
Low Voltage
Reset
BODRSTEN(SYS_BODCTL[3])
Brown-out
Reset
WDT/WWDT
Reset
Reset Pulse Width
64 WDT clocks
CPU Lockup
Reset
Reset Pulse Width
2 system clocks
System Reset
CHIP Reset
CHIPRST(SYS_IPRST0[0])
MCU Reset
SYSRSTREQ(AIRCR[2])
Software Reset
Reset Pulse Width
2 system clocks
CPU Reset
CPURST(SYS_IPRST0[1])
Figure 6.2-1 System Reset Sources
M451 SERIES DATASHEET
Mar. 04, 2016
Page 141 of 219
Rev.2.05
M451
®
There are a total of 9 reset sources in the NuMicro family. In general, CPU reset is used to reset
Cortex-M4 only; the other reset sources will reset Cortex-M4 and all peripherals. However, there
are small differences between each reset source and they are listed in Table 6-1.
Reset Sources POR
NRESET
WDT
LVR
BOD
Lockup
CHIP
MCU
CPU
Register
SYS_RSTSTS
0x001
Bit 1 = 1
Bit 2 = 1
Bit 3 = 1
Bit 4 = 1
Bit 8 = 1
Bit 0 = 1
Bit 5 = 1
Bit 7 =
1
CHIPRST
0x0
-
-
-
-
-
-
-
-
(SYS_IPRST0[0])
BODEN
(SYS_BODCTL[0])
Reload
Reload
Reload
Reload
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0
Reload
Reload
Reload
from
from
from
CONFIG0 CONFIG0 CONFIG0
BODVL
(SYS_BODCTL[2:1])
BODRSTEN
(SYS_BODCTL[3])
HXTEN
(CLK_PWRCTL[0])
Reload
Reload
Reload
Reload
Reload
Reload
Reload
Reload
from
from
from
from
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
LXTEN
0x0
-
-
-
-
-
-
-
-
0x1
-
0x1
-
-
-
0x1
-
-
(CLK_PWRCTL[1])
WDTCKEN
(CLK_APBCLK0[0])
HCLKSEL
Reload
Reload
Reload
Reload
Reload
Reload
Reload
Reload
from
from
from
from
from
from
from
from
(CLK_CLKSEL0[2:0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
WDTSEL
M451 SERIES DATASHEET
0x3
0x3
-
-
-
-
-
-
-
0x0
-
-
-
-
-
-
-
-
0x0
-
-
-
-
-
-
-
-
0x0
-
-
-
-
-
-
-
-
0x0
-
-
-
-
-
-
-
-
0x0
0x0
-
-
-
-
-
-
-
Reload
Reload
Reload
Reload
Reload
from
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
Reload
from
CONFIG0
-
0x0700
0x0700
-
(CLK_CLKSEL1[1:0])
HXTSTB
(CLK_STATUS[0])
LXTSTB
(CLK_STATUS[1])
PLLSTB
(CLK_STATUS[2])
HIRCSTB
(CLK_STATUS[4])
CLKSFAIL
(CLK_STATUS[7])
RSTEN
(WDT_CTL[1])
WDTEN
(WDT_CTL[7])
WDT_CTL
0x0700
0x0700
0x0700
0x0700
-
-
except bit 1 and bit 7.
Mar. 04, 2016
Page 142 of 219
Rev.2.05
M451
WDT_ALTCTL
0x0000
0x0000
0x0000
0x0000
0x0000
-
0x0000
-
-
WWDT_RLDCNT
0x0000
0x0000
0x0000
0x0000
0x0000
-
0x0000
-
-
WWDT_CTL
0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 -
0x3F0800 -
-
WWDT_STATUS
0x0000
0x0000
0x0000
0x0000
0x0000
-
0x0000
-
-
WWDT_CNT
0x3F
0x3F
0x3F
0x3F
0x3F
-
0x3F
-
-
BS
Reload
Reload
Reload
Reload
Reload
from
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
Reload
from
CONFIG0
-
FMC_DFBA
Reload
Reload
Reload
Reload
Reload
from
from
from
from
from
CONFIG1 CONFIG1 CONFIG1 CONFIG1 CONFIG1
Reload
from
CONFIG1
-
CBS
Reload
Reload
Reload
Reload
Reload
from
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
Reload
from
CONFIG0
-
0x0
0x0
-
-
Reload
base
on
CONFIG0
-
(FMC_ISPCTL[1])
BL
(FMC_ISPCTL[16])
(FMC_ISPSTS[2:1))
MBS
(FMC_ISPSTS[3])
PGFF
-
0x0
-
-
-
(FMC_ISPSTS[5])
VECMAP
(FMC_ISPSTS[23:9])
Reload
Reload
Reload
Reload
Reload
base
on base
on base
on base
on base
on
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
Other
Peripheral Reset Value
Registers
FMC Registers
-
Reset Value
Note: ‘-‘ means that the value of register keeps original setting.
6.2.2.1
nRESET Reset
The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an
asynchronous reset input pin and can be used to reset system at any time. When the nRESET
voltage is lower than 0.2 VDD and the state keeps longer than 36 us (glitch filter), chip will be
reset. The nRESET reset will control the chip in reset state until the nRESET voltage rises above
0.7 VDD and the state keeps longer than 36 us (glitch filter). The PINRF(SYS_RSTSTS[1]) will be
set to 1 if the previous reset source is nRESET reset. Figure 6.2-2 shows the nRESET reset
waveform.
Mar. 04, 2016
Page 143 of 219
Rev.2.05
M451 SERIES DATASHEET
Table 6-1 Reset Value of Registers
M451
nRESET
0.7 VDD
36 us
0.2 VDD
36 us
nRESET
Reset
Figure 6.2-2 nRESET Reset Waveform
6.2.2.2
Power-on Reset (POR)
The Power-on reset (POR) is used to generate a stable system reset signal and forces the
system to be reset when power-on to avoid unexpected behavior of MCU. When applying the
power to MCU, the POR module will detect the rising voltage and generate reset signal to system
until the voltage is ready for MCU operation. At POR reset, the PORF(SYS_RSTSTS[0]) will be
set to 1 to indicate there is a POR reset event. The PORF(SYS_RSTSTS[0]) bit can be cleared by
writing 1 to it. Figure 6.2-3 shows the power-on reset waveform.
VPOR
M451 SERIES DATASHEET
0.1V
VDD
Power-on
Reset
Figure 6.2-3 Power-on Reset (POR) Waveform
6.2.2.3
Low Voltage Reset (LVR)
If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVREN
(SYS_BODCTL[7]) to 1, after 200us delay, LVR detection circuit will be stable and the LVR
function will be active. Then LVR function will detect AVDD during system operation. When the
AVDD voltage is lower than VLVR and the state keeps longer than De-glitch time set by LVRDGSEL
(SYS_BODCTL[14:12]), chip will be reset. The LVR reset will control the chip in reset state until
the AVDD voltage rises above VLVR and the state keeps longer than De-glitch time set by
LVRDGSEL (SYS_BODCTL[14:12]). The PINRF(SYS_RSTSTS[1]) will be set to 1 if the previous
reset source is nRESET reset. The default setting of Low Voltage Reset is enabled without Deglitch function. Figure 6.2-4 shows the Low Voltage Reset waveform.
Mar. 04, 2016
Page 144 of 219
Rev.2.05
M451
AVDD
VLVR
T1
( < LVRDGSEL)
T2
( =LVRDGSEL)
T3
( =LVRDGSEL)
Low Voltage Reset
200 us
Delay for LVR stable
LVREN
Figure 6.2-4 Low Voltage Reset (LVR) Waveform
6.2.2.4
Brown-out Detector Reset (BOD Reset)
Mar. 04, 2016
Page 145 of 219
Rev.2.05
M451 SERIES DATASHEET
If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit
BODEN (SYS_BODCTL[0]), Brown-Out Detector function will detect AVDD during system
operation. When the AVDD voltage is lower than VBOD and the state keeps longer than De-glitch
time set by BODDGSEL (SYS_BODCTL[10:8]), chip will be reset. The BOD reset will control the
chip in reset state until the AVDD voltage rises above VBOD and the state keeps longer than Deglitch time set by BODDGSEL (SYS_BODCTL[10:8]). The default value of BODEN, BODVL and
BODRSTEN is set by flash controller user configuration register CBODEN (CONFIG0 [23]),
CBOV (CONFIG0 [22:21]) and CBORST(CONFIG0[20]) respectively. User can determine the
initial BOD setting by setting the CONFIG0 register. Figure 6.2-5 shows the Brown-Out Detector
waveform.
M451
AVDD
VBODH
VBODL
Hysteresis
T1
(< BODDGSEL)
T2
(= BODDGSEL)
BODOUT
T3
(= BODDGSEL)
BODRSTEN
Brown-out
Reset
Figure 6.2-5 Brown-out Detector (BOD) Waveform
6.2.2.5
Watchdog Timer Reset (WDT)
M451 SERIES DATASHEET
In most industrial applications, system reliability is very important. To automatically recover the
MCU from failure status is one way to improve system reliability. The watchdog timer(WDT) is
widely used to check if the system works fine. If the MCU is crashed or out of control, it may
cause the watchdog time-out. User may decide to enable system reset during watchdog time-out
to recover the system and take action for the system crash/out-of-control after reset.
Software can check if the reset is caused by watchdog time-out to indicate the previous reset is a
watchdog reset and handle the failure of MCU after watchdog time-out reset by checking
WDTRF(SYS_RSTSTS[2]).
6.2.2.6
CPU Lockup Reset (M45xD/M45xC Only)
CPU enters lockup status after CPU produces hardfault at hardfault handler and chip gives
immediate indication of seriously errant kernel software. This is the result of the CPU being locked
because of an unrecoverable exception following the activation of the processor’s built in system
state protection hardware. When chip enters debug mode, the CPU lockup reset will be ignored.
6.2.2.7
CPU Reset, CHIP Reset and MCU Reset
®
The CPU Reset means only Cortex -M4 core is reset and all other peripherals remain the same
status after CPU reset. User can set the CPURST(SYS_IPRST0[1]) to 1 to assert the CPU Reset
signal.
The CHIP Reset is same with Power-On Reset. The CPU and all peripherals are reset and
BS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG setting. User can set the
CHIPRST(SYS_IPRST0[1]) to 1 to assert the CHIP Reset signal.
The MCU Reset is similar with CHIP Reset. The difference is that BS(FMC_ISPCTL[1]) will not be
Mar. 04, 2016
Page 146 of 219
Rev.2.05
M451
reloaded from CONFIG setting and keep its original software setting for booting from APROM or
LDROM. User can set the SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset.
6.2.3 Power Modes and Wake-up Sources
There are several wake-up sources in Idle mode and Power-down mode. Table 6-2 lists the
available clocks for each power mode.
Power Mode
Normal Mode
Idle Mode
Power-Down Mode
Definition
CPU is in active state
CPU is in sleep state
CPU is in sleep state and all
clocks stop except LXT and
LIRC. SRAM content retended.
Entry Condition
Chip is in normal mode after
system reset released
CPU executes WFI instruction. CPU sets sleep mode enable
and power down enable and
executes WFI instruction.
Wake-up Sources
N/A
All interrupts
RTC, WDT, I²C, Timer, UART,
BOD, GPIO, USBH, USBD,
OTG, CAN and ACMP
Available Clocks
All
All except CPU clock
LXT and LIRC
After Wake-up
N/A
CPU back to normal mode
CPU back to normal mode
Table 6-2 Power Mode Difference Table
System reset released
Normal Mode
CPU Clock ON
HXT, HIRC, LXT, LIRC, HCLK, PCLK ON
Flash ON
Interrupts occur
1. SCR(SCB[2]) = 1
2. PD_EN(PWRCTL[7]) = 1 and
PDWTCPU(PWRCTL[8]) = 1
3. CPU executes WFI
Idle Mode
Wake-up events
occur
Power-down Mode
CPU Clock OFF
HXT, HIRC, LXT, LIRC, HCLK, PCLK ON
Flash Halt
CPU Clock OFF
HXT, HIRC, HCLK, PCLK OFF
LXT, LIRC ON
Flash Halt
Figure 6.2-6 Power Mode State Machine
Mar. 04, 2016
Page 147 of 219
Rev.2.05
M451 SERIES DATASHEET
CPU executes WFI
M451
1. LXT (32768 Hz XTL) ON or OFF depends on SW setting in run mode.
2. LIRC (10 kHz OSC) ON or OFF depends on S/W setting in run mode.
3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on.
4. If WDT clock source is selected as LIRC and LIRC is on.
5. If RTC clock source is selected as LXT and LXT is on.
M451 SERIES DATASHEET
Normal Mode
Idle Mode
Power-Down Mode
HXT (4~20 MHz XTL)
ON
ON
Halt
HIRC (12/16 MHz OSC)
ON
ON
Halt
LXT (32768 Hz XTL)
ON
ON
ON/OFF1
LIRC (10 kHz OSC)
ON
ON
ON/OFF2
PLL
ON
ON
Halt
LDO
ON
ON
ON
CPU
ON
Halt
Halt
HCLK/PCLK
ON
ON
Halt
SRAM retention
ON
ON
ON
FLASH
ON
ON
Halt
EBI
ON
ON
Halt
GPIO
ON
ON
Halt
PDMA
ON
ON
Halt
TIMER
ON
ON
ON/OFF3
PWM
ON
ON
Halt
WDT
ON
ON
ON/OFF4
WWDT
ON
ON
Halt
RTC
ON
ON
ON/OFF5
UART
ON
ON
Halt
SC
ON
ON
Halt
I2C
ON
ON
Halt
SPI
ON
ON
Halt
USBH
ON
ON
Halt
USBG
ON
ON
Halt
OTG
ON
ON
Halt
CAN
ON
ON
Halt
EADC
ON
ON
Halt
DAC
ON
ON
Halt
ACMP
ON
ON
Halt
Table 6-3 Clocks in Power Modes
Mar. 04, 2016
Page 148 of 219
Rev.2.05
M451
Wake-up sources in Power-down mode:
RTC, WDT, I²C, Timer, UART, BOD, GPIO, USBH, USBD, OTG, CAN and ACMP.
After chip enters power down, the following wake-up sources can wake chip up to normal mode.
Table 6-4 lists the condition about how to enter Power-down mode again for each peripheral.
*User needs to wait this condition before setting PD_EN(PWRCTL[6]) and execute WFI to enter
Power-down mode.
Wake-Up
Wake-Up Condition
Source
BOD
System Can Enter Power-Down Mode Again Condition*
Brown-Out Detector Interrupt After software writes 1 to clear SYS_BODCTL[BODIF].
GPIO
GPIO Interrupt
After software write 1 to clear the INTSRC[n] bit.
Timer Interrupt
After software writes 1 to clear TWKF (TIMERx_INTSTS[1]) and TIF
(TIMERx_INTSTS[0]).
WDT
WDT Interrupt
After software writes 1 to clear WKF (WDT_CTL[5]) (Write Protect).
RTC
Alarm Interrupt
After software writes 1 to clear ALMIF (RTC_INTSTS[0]).
Time Tick Interrupt
After software writes 1 to clear TICKIF (RTC_INTSTS[1]).
Snoop Detection Interrupt
After software writes 1 to clear SNPDIF (RTC_INTSTS[2]).
TIMER
UART
I2C
RX Data wake-up
After software writes 1 to clear DATWKIF (UARTx_INTSTS[17]).
nCTS wake-up
After software writes 1 to clear CTSWKIF (UARTx_INTSTS[16]).
Falling edge in the I2C_SDA
After software writes 1 to clear WKIF( I2C_WKSTS[0]).
or I2C_CLK
Remote Wake-up
After software writes 1 to clear CSC (HcRhPortStatus1[16]).
USBD
Remote Wake-up
After software writes 1 to clear BUSIF (USBD_INTSTS[0]).
OTG
OTG ID Pin Wake-Up
CAN
After software writes 1 to clear OTG_INTSTS[IDCHGIF].
Falling edge in the CAN_RX After software writes 0 to clear WAKUP_STS (CAN_WU_STATUS [0]).
Comparator Power-Down
Wake-Up Interrupt
ACMP
After software writes 1 to clear ACMP_STATUS[WKIFx].
Table 6-4 Condition of Entering Power-down Mode Again
6.2.4 System Power Distribution
In this chip, power distribution is divided into five segments:

Analog power from AVDD and AVSS provides the power for analog components
operation. The VREF should be connected with an external 1uF capacitor that should
be located close to the VREF pin to avoid power noise for analog applications.

Digital power from VDD and VSS supplies the power to the internal regulator which
provides a fixed 1.8 V power for digital operation and I/O pins.

USB transceiver power from VBUS (M45xD/M45xC Only) or from VDD (M45xG/M45xE
Only) offers the power for operating the USB transceiver.
Mar. 04, 2016
Page 149 of 219
Rev.2.05
M451 SERIES DATASHEET
USBH
M451

RTC power from VBAT provides the power for PF.0~PF.2, RTC and 80 bytes backup
registers.

A dedicated power from VDDIO supplies the power for PE.8~PE.13.
The outputs of internal voltage regulators, LDO_CAP and USB_VDD33_CAP, require an external
capacitor which should be located close to the corresponding pin. Analog power (AV DD) should be
the same voltage level of the digital power (VDD). The following figure shows the power distribution
of the NuMicro® M451.
AVDD
12-bit ADC
Internal
Reference
Voltage
12-bit DAC
Analog
Comparator
AVSS
Brownout
Detector
SRAM
X32_OUT
(PF.0)
X32_IN
(PF.1)
32.768 kHz
crystal
oscillator
IO Cell
Low Voltage Reset
Temperature
Sensor
PF.0~PF.2
VBAT
1uF
VREF
Note: When chip is powered on, VBAT will have additional leakage due to power-on detect circuit
still being enabled. Please refer to M451 Errata for detailed description (M45xD/M45xC Only).
USB
Transceiver
3.3V
1.8V
USB_VDD33_CAP
1uF
RTC &
80 bytes
backup
register
VBAT to 1.8V
LDO
Flash
5V to 3.3V
LDO
VDD (M45xG/M45xE Only)
VBUS (M45xD/M45xC Only)
Digital Logic
IO Cell
LDO_CAP
USB_D+
USB_D-
PE.8~PE.13
1.8V
1uF
XT1_OUT
XT1_IN
4~20 MHz
crystal
oscillator
22.1184 MHz
HIRC
Oscillator
POR18
POR50
VDD to 1.8V
LDO
10 kHz
LIRC
Oscillator
Power On
Control
VDDIO
IO Cell
GPIO except
PF.0 ~PF.2 and
PE.8~PE.13
VSS
M451 Power Distribution
VDD
M451 SERIES DATASHEET
PLL
Figure 6.2-7 NuMicro® M451 Power Distribution Diagram
Mar. 04, 2016
Page 150 of 219
Rev.2.05
M451
6.2.5 System Memory Map
®
The NuMicro M451 series provides 4G-byte addressing space. The memory locations assigned to
each on-chip controllers are shown in the following table. The detailed register definition, memory
space, and programming will be described in the following sections for each on-chip peripheral. The
®
NuMicro M451 series only supports little-endian data format.
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0000_9FFF
FLASH_BA
FLASH Memory Space (40KB) (M45xC Only)
0x0000_0000 – 0x0001_1FFF
FLASH_BA
FLASH Memory Space (72KB) (M45xD Only)
0x0000_0000 – 0x0001_FFFF
FLASH_BA
FLASH Memory Space (128KB) (M45xE Only)
0x0000_0000 – 0x0003_FFFF
FLASH_BA
FLASH Memory Space (256KB) (M45xG Only)
0x0004_0000 – 0x0005_FFFF
Reserved
Reserved
0x0006_0000 – 0x0007_FFFF
Reserved
Reserved
0x2000_0000 – 0x2000_1FFF
SRAM0_BA
SRAM Memory Space (M45xD/M45xC Only)
0x2000_2000 – 0x2000_3FFF
SRAM1_BA
SRAM Memory Space (M45xD/M45xC Only)
0x2000_0000 – 0x2000_3FFF
SRAM0_BA
SRAM Memory Space (M45xG/M45xE Only)
0x2000_4000 – 0x2000_7FFF
SRAM1_BA
SRAM Memory Space (M45xG/M45xE Only)
0x2000_8000 – 0x2000_BFFF
Reserved
Reserved
0x2000_C000 – 0x2000_FFFF
Reserved
Reserved
0x6000_0000 – 0x6FFF_FFFF
EXTMEM_BA
External Memory Space for EBI Interface (256 MB)
Peripheral Controllers Space (0x4000_0000 – 0x400F_FFFF)
SYS_BA
System Control Registers
0x4000_0200 – 0x4000_02FF
CLK_BA
Clock Control Registers
0x4000_0300 – 0x4000_03FF
NMI_BA
NMI Control Registers
0x4000_4000 – 0x4000_4FFF
GPIO_BA
GPIO Control Registers
0x4000_8000 – 0x4000_8FFF
PDMA_BA
Peripheral DMA Control Registers
0x4000_9000 – 0x4000_9FFF
USBH_BA
USB Host Control Registers (M45xG/M45xE Only)
0x4000_B000 – 0x4000_BFFF
Reserved
Reserved
0x4000_C000 – 0x4000_CFFF
FMC_BA
Flash Memory Control Registers
0x4000_D000 – 0x4000_DFFF
Reserved
Reserved
0x4001_0000 – 0x4001_0FFF
EBI_BA
External Bus Interface Control Registers
0x4001_9000 – 0x4001_9FFF
Reserved
Reserved
0x4003_0000 – 0x4003_0FFF
Reserved
Reserved
0x4003_1000 – 0x4003_1FFF
CRC_BA
CRC Generator Registers
0x5000_8000 – 0x5000_FFFF
Reserved
Reserved
M451 SERIES DATASHEET
0x4000_0000 – 0x4000_01FF
APB Controllers Space (0x4000_0000 ~ 0x400F_FFFF)
0x4004_0000 – 0x4004_0FFF
Mar. 04, 2016
WDT_BA
Watchdog Timer Control Registers
Page 151 of 219
Rev.2.05
M451
M451 SERIES DATASHEET
0x4004_1000 – 0x4004_1FFF
RTC_BA
Real Time Clock (RTC) Control Register
0x4004_3000 – 0x4004_3FFF
EADC_BA
Enhanced Analog-Digital-Converter (EADC) Control Registers
0x4004_4000 – 0x4004_4FFF
Reserved
Reserved
0x4004_5000 – 0x4004_5FFF
ACMP01_BA
Analog Comparator 0/ 1 Control Registers
0x4004_6000 – 0x4004_6FFF
Reserved
Reserved
0x4004_7000 – 0x4004_7FFF
DAC_BA
DAC Control Registers
0x4004_8000 – 0x4004_8FFF
Reserved
Reserved
0x4004_9000 – 0x4004_9FFF
Reserved
Reserved
0x4004_D000 – 0x4004_DFFF
OTG_BA
USB OTG Control Register (M45xG/M45xE Only)
0x4005_0000 – 0x4005_0FFF
TMR01_BA
Timer0/Timer1 Control Registers
0x4005_1000 – 0x4005_1FFF
TMR23_BA
Timer2/Timer3 Control Registers
0x4005_8000 – 0x4005_8FFF
PWM0_BA
PWM0 Control Registers
0x4005_9000 – 0x4005_9FFF
PWM1_BA
PWM1 Control Registers
0x4005_C000 – 0x4005_CFFF
Reserved
Reserved
0x4005_D000 – 0x4005_DFFF
Reserved
Reserved
0x4006_0000 – 0x4006_0FFF
SPI0_BA
SPI0 Control Registers
0x4006_1000 – 0x4006_1FFF
SPI1_BA
SPI1 Control Registers
0x4006_2000 – 0x4006_2FFF
SPI2_BA
SPI2 Control Registers (M45xG/M45xE Only)
0x4006_3000 – 0x4006_3FFF
Reserved
Reserved
0x4007_0000 – 0x4007_0FFF
UART0_BA
UART0 Control Registers
0x4007_1000 – 0x4007_1FFF
UART1_BA
UART1 Control Registers
0x4007_2000 – 0x4007_2FFF
UART2_BA
UART2 Control Registers
0x4007_3000 – 0x4007_3FFF
UART3_BA
UART3 Control Registers
0x4007_4000 – 0x4007_4FFF
Reserved
Reserved
0x4007_5000 – 0x4007_5FFF
Reserved
Reserved
0x4008_0000 – 0x4008_0FFF
I2C0_BA
I2C0 Control Registers
0x4008_1000 – 0x4008_1FFF
I2C1_BA
I2C1 Control Registers
0x4008_2000 – 0x4008_2FFF
Reserved
Reserved
0x4008_3000 – 0x4008_3FFF
Reserved
Reserved
0x4008_4000 – 0x4008_4FFF
Reserved
Reserved
0x4009_0000 – 0x4009_0FFF
SC0_BA
Smartcard Host 0 Control Registers
0x4009_1000 – 0x4009_1FFF
Reserved
Reserved
0x4009_2000 – 0x4009_2FFF
Reserved
Reserved
0x4009_3000 – 0x4009_3FFF
Reserved
Reserved
0x4009_4000 – 0x4009_4FFF
Reserved
Reserved
Mar. 04, 2016
Page 152 of 219
Rev.2.05
M451
0x4009_5000 – 0x4009_5FFF
Reserved
Reserved
0x400A_0000 – 0x400A_0FFF
CAN0_BA
CAN0 Bus Control Registers
0x400A_1000 – 0x400A_1FFF
Reserved
Reserved
0x400B_0000 – 0x400B_0FFF
Reserved
Reserved
0x400B_1000 – 0x400B_1FFF
Reserved
Reserved
0x400B_0000 – 0x400B_0FFF
Reserved
Reserved
0x400B_1000 – 0x400B_1FFF
Reserved
Reserved
0x400C_0000 – 0x400C_0FFF
USBD_BA
USB Device Control Register
0x400E_0000 – 0x400E_0FFF
Reserved
Reserved
0x5008_0000 – 0x5008_0FFF
Reserved
Reserved
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
SCS_BA
System Timer Control Registers
0xE000_E100 – 0xE000_ECFF
SCS_BA
External Interrupt Controller Control Registers
0xE000_ED00 – 0xE000_ED8F
SCS_BA
System Control Registers
Table 6-5 Address Space Assignments for On-Chip Controllers
M451 SERIES DATASHEET
Mar. 04, 2016
Page 153 of 219
Rev.2.05
M451
6.2.6 SRAM Memory Organization
The M45xG/M45xE supports embedded SRAM with total 32 Kbytes size and the SRAM
organization is separated to two banks: SRAM bank0 and SRAM bank1. Each of these two banks
has 16 Kbytes address space and can be accessed simultaneously. The SRAM bank0 supports
parity error check to make sure chip operating more stable.
The M45xD/M45xC supports embedded SRAM with total 16 Kbytes size and the SRAM
organization is separated to two banks: SRAM bank0 and SRAM bank1. Each of these two banks
has 8 Kbytes address space and can be accessed simultaneously. The SRAM bank0 supports
parity error check to make sure chip operating more stable.
Supports total 32 Kbytes SRAM (M45xG/M45xE Only)

Supports total 16 Kbytes SRAM (M45xD/M45xC Only)

Supports byte / half word / word write

Supports fixed 16 Kbytes SRAM bank for independent access (M45xG/M45xE Only)

Supports fixed 8 Kbytes SRAM bank for independent access (M45xD/M45xC Only)

Supports parity error check function for SRAM bank0

Supports oversize response error

Supports remap address to 0x1000_0000
M451 SERIES DATASHEET
AHB Bus

AHB interface
controller
SRAM decoder
SRAM bank0
AHB interface
controller
SRAM decoder
SRAM bank1
Figure 6.2-8 SRAM Block Diagram
Mar. 04, 2016
Page 154 of 219
Rev.2.05
M451
Figure 6.2-9 shows the SRAM organization of M45xG/M45xE. There are two SRAM banks in
M45xG/M45xE and each bank is addressed to 16 Kbytes. The bank0 address space is from
0x2000_0000 to 0x2000_3FFF. The bank1 address space is from 0x2000_4000 to 0x2000_7FFF.
The address between 0x2000_8000 to 0x3FFF_FFFF is illegal memory space and chip will enter
hardfault if CPU accesses these illegal memory addresses.
The address of each bank is remapping from 0x2000_0000 to 0x1000_0000. CPU can read
SRAM bank0 through 0x2000_0000 to 0x2000_3FFF or 0x1000_0000 to 0x1000_3FFF, and read
SRAM bank1 through 0x2000_4000 to 0x2000_7FFF or 0x1000_4000 to 0x1000_7FFF
0x3FFF_FFFF
512MB
Reserved
0x2000_8000
0x2000_7FFF
0x1000_7FFF
remapping
16K byte
SRAM bank1
0x2000_4000
0x1000_4000
0x2000_3FFF
0x1000_3FFF
16K byte
SRAM bank0
remapping
0x2000_0000
M451 SERIES DATASHEET
16K byte
SRAM bank1
16K byte
SRAM bank0
0x1000_0000
32K byte device
32K byte device
Figure 6.2-9 SRAM Memory Organization (M45xG/M45xE)
Mar. 04, 2016
Page 155 of 219
Rev.2.05
M451
Figure 6.2-10 shows the SRAM organization of M45xD/M45xC. There are two SRAM banks in
M45xD/M45xC and each bank is addressed to 8 Kbytes. The bank0 address space is from
0x2000_0000 to 0x2000_1FFF. The bank1 address space is from 0x2000_2000 to 0x2000_3FFF.
The address between 0x2000_4000 to 0x3FFF_FFFF is illegal memory space and chip will enter
hardfault if CPU accesses these illegal memory addresses.
The address of each bank is remapping from 0x2000_0000 to 0x1000_0000. CPU can read
SRAM bank0 through 0x2000_0000 to 0x2000_1FFF or 0x1000_0000 to 0x1000_1FFF, and read
SRAM bank1 through 0x2000_2000 to 0x2000_3FFF or 0x1000_2000 to 0x1000_3FFF
0x3FFF_FFFF
512MB
Reserved
M451 SERIES DATASHEET
0x2000_4000
0x2000_3FFF
0x1000_3FFF
8K byte
SRAM bank1
0x2000_2000
0x2000_1FFF
0x2000_0000
8K byte
SRAM bank1
remapping
0x1000_2000
0x1000_1FFF
8K byte
SRAM bank0
remapping
16K byte device
0x1000_0000
8K byte
SRAM bank0
16K byte device
Figure 6.2-10 SRAM Memory Organization (M45xD/M45xC)
SRAM bank0 has byte parity error check function. When CPU is accessing SRAM bank0, the
parity error checking mechanism is dynamic operating. As parity error occurred, the PERRIF
(SYS_SRAM_STATUS[0]) will be asserted to 1 and the SYS_SRAM_ERRADDR register will
Mar. 04, 2016
Page 156 of 219
Rev.2.05
M451
recode the address with parity error. Chip will enter interrupt when SRAM parity error occurred if
PERRIEN (SYS_SRAM_INTCTL[0]) is set to 1. When SRAM parity error occurred, chip will stop
detecting SRAM parity error until user writes 1 to clear the PERRIF(SYS_SRAM_STATUS[0]) bit.
6.2.7 System Timer (SysTick)
®
The Cortex -M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value
Register (SYST_VAL) to zero, and reload (wrap) to the value in the SysTick Reload Value
Register (SYST_LOAD) on the next clock cycle, and then decrement on subsequent clocks.
When the counter transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit
clears on reads.
The SYST_VAL value is UNKNOWN on reset. Software should write to the register to clear it to
zero before enabling the feature. This ensures the timer will count from the SYST_LOAD value
rather than an arbitrary value when it is enabled.
If the SYST_LOAD is zero, the timer will be maintained with a current value of zero after it is
reloaded with this value. This mechanism can be used to disable the feature independently from
the timer enable bit.
®
®
For more detailed information, please refer to the “ARM Cortex -M4 Technical Reference
®
Manual” and “ARM v6-M Architecture Reference Manual”.
6.2.8 Nested Vectored Interrupt Controller (NVIC)
The NVIC supports:

An implementation-defined number of interrupts, in the range 1-240 interrupts.

A programmable priority level of 0-15 for each interrupt; a higher level corresponds to
a lower priority, so level 0 is the highest interrupt priority.

Level and pulse detection of interrupt signals.

Dynamic reprioritization of interrupts.

Grouping of priority values into group priority and subpriority fields.

Interrupt tail-chaining.

An external Non Maskable Interrupt (NMI)

WIC with Ultra-low Power Sleep mode support
The processor automatically stacks its state on exception entry and unstacks this state on
exception exit, with no instruction overhead. This provides low latency exception handling.
Mar. 04, 2016
Page 157 of 219
Rev.2.05
M451 SERIES DATASHEET
The NVIC and the processor core interface are closely coupled to enable low latency interrupt
processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of
the stacked, or nested, interrupts to enable tail-chaining of interrupts. You can only fully access
the NVIC from privileged mode, but you can cause interrupts to enter a pending state in user
mode if you enable the Configuration and Control Register. Any other user mode access causes a
bus fault. You can access all NVIC registers using byte, halfword, and word accesses unless
otherwise stated. NVIC registers are located within the SCS (System Control Space). All NVIC
registers and system debug registers are little-endian regardless of the endianness state of the
processor.
M451
6.3 Clock Controller
6.3.1 Overview
The clock controller generates clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and a clock divider. The chip will not
enter Power-down mode until CPU sets the Power-down enable bit PDEN(CLK_PWRCTL[7]) and
®
Cortex -M4 core executes the WFI instruction. After that, chip enters Power-down mode and wait
for wake-up interrupt source triggered to leave Power-down mode. In Power-down mode, the
clock controller turns off the 4~20 MHz external high speed crystal (HXT) and 22.1184 MHz
internal high speed RC oscillator (HIRC) to reduce the overall system power consumption. The
following figure shows the clock generator and the overview of the clock source control.
M451 SERIES DATASHEET
Mar. 04, 2016
Page 158 of 219
Rev.2.05
M451
CPUCLK
22.1184
MHz
22.1184 MHz
4~24
MHz
10 kHz
PLLFOUT
32.768 kHz
32.768
kHz
4~24 MHz
10 kHz
CPU
CRC
111
011
EBI
HCLK
PDMA
PCLK0
CAN0
PCLK1
I2C1
1/(HCLKDIV+1)
010
I2C0
001
000
CLK_CLKSEL0[2:0]
DAC
22.1184 MHz
22.1184 MHz
1
4~24 MHz
10 kHz
PLL FOUT
0
32.768 kHz
BOD
22.1184 MHz
PLLFOUT
PCLK1
USB
1/(EADCDIV+1)
EADC
10 kHz
32.768 kHz
4~24 MHz
FMC
1/(USBDIV+1)
22.1184 MHz
HCLK
32.768 kHz
32.768 kHz
4~24 MHz
4~24 MHz
11
10
4~24 MHz
010
001
000
Clock Output
00
22.1184 MHz
HCLK
10
01
00
1/2
111
1/2
011
1/2
010
32.768 kHz
11
4~24 MHz
SPI0
SPI2
11
01
SYST_CTRL[2]
1
M451 SERIES DATASHEET
4~24 MHz
SysTick
CLK_CLKSEL0[5:3]
PCLK0
10
1
0
000
PLLFOUT
PCLK1
PLLFOUT
CPUCLK
001
CLK_CLKSEL2[3:2]
CLK_CLKSEL2[7:6]
22.1184 MHz
TMR 2
TMR 3
01
4~24 MHz
PCLK0
PLLFOUT
111
CLK_CLKSEL1[18:16]
CLK_CLKSEL1[22:20]
CLK_CLKSEL1[29:28]
22.1184 MHz
000
011
PCLK1
CLK_CLKSEL3[8]
22.1184 MHz
001
101
T2~T3
RTC
0
010
CLK_CLKSEL1 [10:8]
CLK_CLKSEL1[14:12]
10 kHz
1
TMR 0
TMR 1
011
PCLK0
10 kHz
111
101
T0~T1
CLK_PLLCTL[19]
ACMP01
PWM 0
0
CLK_CLKSEL2[0]
SPI1
PCLK1
00
PLLFOUT
1
PWM 1
0
CLK_CLKSEL2[5:4]
CLK_CLKSEL2[1]
22.1184 MHz
PCLK0
PLLFOUT
4~24 MHz
11
10
10 kHz
1/(SC0DIV+1)
SC0
01
00
32.768 kHz
PLLFOUT
4~24 MHz
1/2048
32.768 kHz
11
10
WDT
01
CLK_CLKSEL1[1:0]
CLK_CLKSEL3[1:0]
22.1184 MHz
HCLK
10 kHz
11
10
01
HCLK
1/(UARTDIV+1)
1/2048
11
10
WWDT
UART 0-3
CLK_CLKSEL1[31:30]
00
CLK_CLKSEL1[25:24]
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-1 Clock Generator Global View Diagram
Mar. 04, 2016
Page 159 of 219
Rev.2.05
M451
6.3.2 Clock Generator
The clock generator consists of 5 clock sources, which are listed below:

32.768 kHz external low speed crystal oscillator (LXT)

4~20 MHz external high speed crystal oscillator (HXT)

Programmable PLL output clock frequency (PLLFOUT), PLL source can be selected
from external 4~20 MHz external high speed crystal (HXT) or 22.1184 MHz internal
high speed oscillator (HIRC)

22.1184 MHz internal high speed RC oscillator (HIRC)

10 kHz internal low speed RC oscillator (LIRC)
LXTEN (CLK_PWRCTL[1])
X32_IN
External 32.768
kHz Crystal
(LXT)
LXT
X32_OUT
HXTEN (CLK_PWRCTL[0])
HXT
XT1_IN
External 4~24
MHz Crystal
(HXT)
XT1_OUT
PLLSRC (CLK_PLLCTL[19])
0
HIRCEN (CLK_PWRCTL[2])
PLL
PLL FOUT
1
M451 SERIES DATASHEET
Internal
22.1184 MHz
Oscillator
(HIRC)
HIRC
LIRCEN (CLK_PWRCTL[3])
Internal 10 kHz
Oscillator
(LIRC)
LIRC
Figure 6.3-2 Clock Generator Block Diagram
Mar. 04, 2016
Page 160 of 219
Rev.2.05
M451
6.3.3 System Clock and SysTick Clock
The system clock has 5 clock sources, which were generated from clock generator block. The
clock source switch depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The block diagram
is shown in the following figure.
HCLKSEL
(CLK_CLKSEL0[2:0])
HIRC
LIRC
PLLFOUT
LXT
HXT
111
CPUCLK
011
1/(HCLK_N+1)
1/(HCLKDIV+1)
HCLKDIV
(CLK_CLKDIV0[3:0])
010
001
000
CPU in Power Down Mode
HCLK
PCLK0
PCLK1
CPU
AHB
APB0
APB1
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-3 System Clock Block Diagram
There are two clock fail detectors to observe HXT and LXT clock source and they have individual
enable and interrupt control. When HXT detector is enabled, the HIRC clock is enabled
automatically. When LXT detector is enabled, the LIRC clock is enabled automatically.
The HXT clock stop detect and system clock switch to HIRC procedure is shown in the following
figure.
Mar. 04, 2016
Page 161 of 219
Rev.2.05
M451 SERIES DATASHEET
When HXT clock detector is enabled, the system clock will auto switch to HIRC if HXT clock stop
being detected on the following condition: system clock source comes from HXT or system clock
source comes from PLL with HXT as the input of PLL. If HXT clock stop condition is detected, the
HXTFIF (CLK_CLKDSTS[0]) is set to 1 and chip will enter interrupt if HXTFIE (CLK_CLKDCTL[5])
is set to 1. User can trying to recover HXT by disable HXT and enable HXT again to check if the
clock stable bit is set to 1 or not. If HXT clock stable bit is set to 1, it means HXT is recover to
oscillate after re-enable action and user can switch system clock to HXT again.
M451
Set HXTFDEN To enable
HXT clock detector
NO
HXTFIF = 1?
YES
System clock source =
“HXT” or “PLL with
HXT” ?
NO
System clock keep
original clock
YES
Switch system clock to
HIRC
Figure 6.3-4 HXT Stop Protect Procedure
®
M451 SERIES DATASHEET
The clock source of SysTick in Cortex -M4 core can use CPU clock or external clock
(SYST_CTRL[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The
clock source switch depends on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]). The
block diagram is shown in the following figure.
STCLKSEL
(CLK_CLKSEL0[5:3])
HIRC
HCLK
HXT
LXT
HXT
1/2
111
1/2
011
1/2
010
STCLK
001
000
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-5 SysTick Clock Control Block Diagram
6.3.4 Peripherals Clock
The peripherals clock has different clock source switch setting, which depends on the different
peripheral. Please refer to the CLK_CLKSEL1 and CLK_CLKSEL2 register description in 5.3.8.
Mar. 04, 2016
Page 162 of 219
Rev.2.05
M451
6.3.5 Power-down Mode Clock
When entering Power-down mode, system clocks, some clock sources and some peripheral
clocks are disabled. Some clock sources and peripherals clock are still active in Power-down
mode.
For theses clocks, which still keep active, are listed below:


Clock Generator

10 kHz internal low speed RC oscillator (LIRC) clock

32.768 kHz external low speed crystal oscillator (LXT) clock
Peripherals Clock (When the modules adopt LXT or LIRC as clock source)
6.3.6 Clock Output
This device is equipped with a power-of-2 frequency divider which is composed by16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided
1
16
clocks with the frequency from Fin/2 to Fin/2 where Fin is input clock frequency to the clock
divider.
(N+1)
The output formula is Fout = Fin/2
, where Fin is the input clock frequency, Fout is the clock
divider output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).
When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When
writing 0 to CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock
reaches low state and stays in low state.
CLKOSEL (CLK_CLKSEL1[29:28])
HCLK
LXT
HXT
CLKOCKEN (CLK_APBCLK0[6])
11
10
CLKO_CLK
01
00
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-6 Clock Source of Clock Output
Mar. 04, 2016
Page 163 of 219
Rev.2.05
M451 SERIES DATASHEET
HIRC
M451
CLKOEN
(CLK_CLKOCTL[4])
Enable
divide-by-2 counter
CLKO_CLK
1/2
1/22
FREQSEL
(CLK_CLKOCTL[3:0])
16 chained
divide-by-2 counter
1/23
…...
1/215
DIVIDER1*
(FRQDIV[5])
1/216
0000
0001
:
:
1110
1111
16 to 1
MUX
CLK1HZEN
(CLK_CLKOCTL[6])
0
0
1
CLKO
1
RTCSEL(CLK_CLKSEL3[8])
LIRC
0
1 Hz clock from RTC
/32768
LXT
1
Figure 6.3-7 Clock Output Block Diagram
M451 SERIES DATASHEET
Mar. 04, 2016
Page 164 of 219
Rev.2.05
M451
6.4 Flash Memeory Controller (FMC)
6.4.1 Overview
®
The NuMicro M451 series is equipped with 40K/72K/128K/256K bytes on-chip embedded flash
for application and configurable Data Flash to store some application dependent data. A User
Configuration block provides for system initiation. A 4 Kbytes loader ROM (LDROM) is used for
In-System-Programming (ISP) function. A 16K Boot Loader consists of native ISP functions. A
4KB cache with zero wait cycle is used to improve flash access performance. This chip also
supports In-Application-Programming (IAP) function, user switches the code executing without the
chip reset after the embedded flash updated.
6.4.2 Features

Supports 40K/72K/128K/256K bytes application ROM (APROM).

Supports 4 Kbytes loader ROM (LDROM).

Supports Data Flash with configurable memory size.

Supports 8 bytes User Configuration block to control system initiation.

Supports 2 Kbytes page erase for all embedded flash.

Supports Boot Loader with native In-System-Programming (ISP) functions.

Supports 32-bit/64-bit and multi-word flash programming function.

Supports fast flash programming verification function.

Supports checksum calculation function.

Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update
embedded flash memory.

Supports cache memory to improve flash access performance and reduce power
consumption.
M451 SERIES DATASHEET
Mar. 04, 2016
Page 165 of 219
Rev.2.05
M451
6.5 External Bus Interface (EBI)
6.5.1 Overview
®
The NuMicro M451 is equipped with an external bus interface (EBI) for external device used. To
®
save the connections between external device and the NuMicro M451, EBI operating at address
bus and data bus multiplex mode. The EBI supports two chip selects that can connect two
external devices with different timing setting requirement.
6.5.2 Features
The External Bus Interface (EBI) has the following functions:

Supports address bus and data bus multiplex mode to save the address pins

Supports two chip selects with polarity control

Supports external devices with max. 1 MB size for each chip select

Supports variable external bus base clock (MCLK) which based on HCLK

Supports 8-bit or 16-bit data width for each chip select

Supports variable address latch enable time (tALE)

Supports variable data access time (tACC) and data access hold time (tAHD) for each
chip select

Supports configurable idle cycle for different access condition: Idle of Write command
finish (W2X) and Idle of Read-to-Read (R2R)
M451 SERIES DATASHEET
Mar. 04, 2016
Page 166 of 219
Rev.2.05
M451
6.6 General Purpose I/O (GPIO)
6.6.1 Overview
®
The NuMicro M451 series has up to 87(for M45xG/M45xE)/76(for M45xD/M45xC) General
Purpose I/O pins to be shared with other function pins depending on the chip configuration. These
87(for M45xG/M45xE)/76(for M45xD/M45xC) pins are arranged in 6 ports named as PA, PB, PC,
PD, PE and PF. PA, PB, PC, and PD has 16 pins on port. PE has 15 pins on port.PF has 8 pins
on port. Each of the 87(for M45xG/M45xE)/76(for M45xD/M45xC) pins is independent and has
the corresponding register bits to control the pin mode function and data.
The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull
output, Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all
pins are depending on CIOIN (CONFIG0[10]). Each I/O pin has a very weakly individual pull-up
resistor which is about 110 k ~ 300 k for VDD is from 5.0 V to 2.5 V.
6.6.2 Features

Four I/O modes:

Quasi-bidirectional mode

Push-Pull Output mode

Open-Drain Output mode

Input only with high impendence mode

TTL/Schmitt trigger input selectable

I/O pin can be configured as interrupt source with edge/level setting

Supports High Drive and High Slew Rate I/O mode

Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting
CIOIN = 0, all GPIO pins in Quasi-bidirectional mode after chip reset

CIOIN = 1, all GPIO pins in input mode after chip reset

I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode

Enabling the pin interrupt function will also enable the wake-up function
Mar. 04, 2016
Page 167 of 219
M451 SERIES DATASHEET

Rev.2.05
M451
6.7 PDMA Controller (PDMA)
6.7.1 Overview
The peripheral direct memory access (PDMA) controller is used to provide high-speed data
transfer. The PDMA controller can transfer data from one address to another without CPU
intervention. This has the benefit of reducing the workload of CPU and keeps CPU resources free
for other applications. The PDMA controller has a total of 12 channels and each channel can
perform transfer between memory and peripherals or between memory and memory.
6.7.2 Features

Supports 12 independently configurable channels (M45xG/M45xE Only)

Supports 8 independently configurable channels (M45xD/M45xC Only)

Supports selectable 2 level of priority (fixed priority or round-robin priority)

Supports transfer data width of 8, 16, and 32 bits

Supports source and destination address increment size can be byte, half-word, word
or no increment

Supports software and SPI, UART, DAC, ADC and PWM request

Supports Scatter-Gather mode to perform sophisticated transfer through the use of
the descriptor link list table

Supports single and burst transfer type

Supports time-out function for each channel (M45xD/M45xC Only)
M451 SERIES DATASHEET
Mar. 04, 2016
Page 168 of 219
Rev.2.05
M451
6.8 Timer Controller (TMR)
6.8.1 Overview
The Timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily
implement a timer control for applications. The timer can perform functions, such as frequency
measurement, delay timing, clock generation, and event counting by external input pins, and
interval measurement by external capture pins.
6.8.2 Features

Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter

Independent clock source for each timer

Provides one-shot, periodic, toggle-output and continuous counting operation modes

24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])

Supports event counting function

24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])

Supports external capture pin event for interval measurement

Supports external capture pin event to reset 24-bit up counter

Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated

Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to trigger PWM,
EADC and DAC function
M451 SERIES DATASHEET
Mar. 04, 2016
Page 169 of 219
Rev.2.05
M451
6.9 PWM Generator and Capture Timer (PWM)
6.9.1 Overview
The M451 provides two PWM generators － PWM0 and PWM1. Each PWM supports 6 channels
of PWM output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit
PWM counter with 16-bit comparator. The PWM counter supports up, down and up-down counter
types. PWM using comparator compared with counter to generate events. These events use to
generate PWM pulse, interrupt and trigger signal for EADC/DAC to start conversion.
The PWM generator supports two standard PWM output modes: Independent mode and
Complementary mode, they have difference architecture. There are two output functions based
on standard output modes: Group function and Synchronous function. Group function can be
enabled under Independent mode or complementary mode. Synchronous function only enabled
under complementary mode. Complementary mode has two comparators to generate various
PWM pulse with 12-bit dead-time generator and another free trigger comparator to generate
trigger signal for EADC. For PWM output control unit, it supports polarity output, independent pin
mask and brake functions.
The PWM generator also supports input capture function. It supports latch PWM counter value to
corresponding register when input channel has a rising transition, falling transition or both
transition is happened. Capture function also support PDMA to transfer captured data to memory.
6.9.2 Features
6.9.2.1
PWM function features

Supports maximum clock frequency up to144MHz

Supports up to two PWM modules, each module provides 6 output channels.

Supports independent mode for PWM output/Capture input channel

Supports complementary mode for 3 complementary paired PWM output channel
M451 SERIES DATASHEET

Dead-time insertion with 12-bit resolution

Synchronous function for phase control

Two compared values during one period

Supports 12-bit pre-scalar from 1 to 4096

Supports 16-bit resolution PWM counter

Up, down and up/down counter operation type

Supports one-shot or auto-reload counter operation mode

Supports group function

Supports synchronous function

Supports mask function and tri-state enable for each PWM pin

Supports brake function
Mar. 04, 2016

Brake source from pin, analog comparator and system safety events (clock
failed, SRAM parity error, Brown-out detection and CPU lockup).

Noise filter for brake source from pin

Edge detect brake source to control brake state until brake interrupt cleared

Level detect brake source to auto recover function after brake condition removed
Page 170 of 219
Rev.2.05
M451


6.9.2.2
Supports interrupt on the following events:

PWM counter match zero, period value or compared value

Brake condition happened
Supports trigger EADC/DAC on the following events:

PWM counter match zero, period value or compared value

PWM counter match free trigger comparator compared value (only for EADC)
Capture Function Features

Supports up to 12 capture input channels with 16-bit resolution

Supports rising or falling capture condition

Supports input rising/falling capture interrupt

Supports rising/falling capture with counter reload option

Supports PDMA transfer function for PWM all channels
M451 SERIES DATASHEET
Mar. 04, 2016
Page 171 of 219
Rev.2.05
M451
6.10 Watchdog Timer (WDT)
6.10.1 Overview
The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into an
unknown state. This prevents system from hanging for an infinite period of time. Besides, this
Watchdog Timer supports the function to wake-up system from Idle/Power-down mode.
6.10.2 Features

18-bit free running up counter for WDT time-out interval

Selectable time-out interval (2 ~ 2 ) and the time-out interval is 1.6 ms ~ 26.214s if
WDT_CLK = 10 kHz.

System kept in reset state for a period of (1 / WDT_CLK) * 63

Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK reset
delay period

Supports to force WDT enabled after chip powered on or reset by setting CWDTEN[2:0] in
Config0 register

Supports WDT time-out wake-up function only if WDT clock source is selected as LIRC or
LXT.
4
18
M451 SERIES DATASHEET
Mar. 04, 2016
Page 172 of 219
Rev.2.05
M451
6.11 Window Watchdog Timer (WWDT)
6.11.1 Overview
The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified
window period to prevent software run to uncontrollable status by any unpredictable condition.
6.11.2 Features

6-bit down counter value (CNTDAT) and 6-bit compare value (CMPDAT) to make the
WWDT time-out window period flexible

Supports 4-bit value (PSCSEL) to programmable maximum 11-bit prescale counter period of
WWDT counter
M451 SERIES DATASHEET
Mar. 04, 2016
Page 173 of 219
Rev.2.05
M451
6.12 Real Time Clock (RTC)
6.12.1 Overview
The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC
offers programmable time tick and alarm match interrupts. The data format of time and calendar
messages are expressed in BCD format. A digital frequency compensation feature is available to
compensate external crystal oscillator frequency accuracy.
The RTC controller also offers 80 bytes spare registers to store user’s important information. The
spare registers content is cleared when specified event on tamper pin is detected.
6.12.2 Features
M451 SERIES DATASHEET

Supports real time counter in RTC_TIME (hour, minute, second) and calendar counter in
RTC_CAL (year, month, day) for RTC time and calendar check

Supports alarm time (hour, minute, second) and calendar (year, month, day) settings in
RTC_TALM and RTC_CALM

Supports alarm time (hour, minute, second) and calendar (year, month, day) mask enable in
RTC_TAMSK and RTC_CAMSK

Selectable 12-hour or 24-hour time scale in RTC_CLKFMT register

Supports Leap Year indication in RTC_LEAPYEAR register

Supports Day of the Week counter in RTC_WEEKDAY register

Frequency of RTC clock source compensate by RTC_FREQADJ register

All time and calendar message expressed in BCD format

Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second

Supports RTC Time Tick and Alarm Match interrupt

Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is
generated

Supports 80 bytes spare registers and a snoop pin detection to clear the content of these
spare registers
Mar. 04, 2016
Page 174 of 219
Rev.2.05
M451
6.13 UART Interface Controller (UART)
6.13.1 Overview
®
The NuMicro
M451 series provides four channels of Universal Asynchronous
Receiver/Transmitters (UART). UART Controller performs Normal Speed UART and supports
flow control function. The UART Controller performs a serial-to-parallel conversion on data
received from the peripheral and a parallel-to-serial conversion on data transmitted from the CPU.
Each UART Controller channel supports ten types of interrupts. The UART controller also
supports IrDA SIR, RS-485 and auto-baud rate measuring function.
6.13.2 Features

Full-duplex asynchronous communications

Separates receive and transmit 16/16 bytes entry FIFO for data payloads

Supports hardware auto-flow control

Programmable receiver buffer trigger level

Supports programmable baud rate generator for each channel individually

Supports nCTS and RX data wake-up function

Supports 8-bit receiver buffer time-out detection function

Programmable transmitting data delay time between the last stop and the next start bit by
setting DLY (UART_TOUT [15:8])

Supports Auto-Baud Rate measurement

Supports break error, frame error, parity error and receive/transmit buffer overflow detection
function

Fully programmable serial-interface characteristics
Programmable number of data bit, 5-, 6-, 7-, 8- bit character

Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection

Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode



Supports for 3/16 bit duration for normal mode
Supports LIN function mode (Only UART0 /UART1 with LIN function)

Supports LIN master/slave mode

Supports programmable break generation function for transmitter

Supports break detection function for receiver
Supports RS-485 function mode

Supports RS-485 9-bit mode

Supports hardware or software enables to program nRTS pin to control RS-485
transmission direction
UART Feature
Mar. 04, 2016
UART0 / UART1
Page 175 of 219
UART2 / UART3
SC_UART
Rev.2.05
M451 SERIES DATASHEET


M451
FIFO
16 Bytes
16 Bytes
4 Bytes
Auto Flow Control (CTS/RTS)
√
√
-
IrDA
√
√
-
LIN
√
-
-
RS-485 Function Mode
√
√
-
Auto-Flow Control
√
√
-
nCTS Wake-up
√
√
-
RX Data Wake-up
√
√
-
Auto-Baud Rate Measurement
√
√
-
1, 1.5, 2 bit
1, 1.5, 2 bit
1, 2 bit
Word Length 5, 6,7, 8 bits
√
√
√
Even / Odd Parity
√
√
√
Stick Bit
√
√
-
STOP Bit Length
√= Supported
®
Table 6-6 NuMicro M451 Series UART Feature
M451 SERIES DATASHEET
Mar. 04, 2016
Page 176 of 219
Rev.2.05
M451
6.14 Smart Card Host Interface (SC)
6.14.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/INTENC 7816-3 standard and
fully compliant with PC/SC Specifications. It also provides status of card insertion/removal.
6.14.2 Features

ISO-7816-3 T = 0, T = 1 compliant.

EMV2000 compliant

One ISO-7816-3 port

Separates receive/transmit 4 byte entry FIFO for data payloads.

Programmable transmission clock frequency.

Programmable receiver buffer trigger level.

Programmable guard time selection (11 ETU ~ 267 ETU).

A 24-bit and two 8-bit timers for Answer to Request (ATR) and waiting times
processing.

Supports auto inverse convention function.

Supports transmitter and receiver error retry and error number limiting function.

Supports hardware activation sequence, hardware warm reset sequence and
hardware

deactivation sequence process.

Supports hardware auto deactivation sequence when detected the card removal.

Supports UART mode
Full duplex, asynchronous communications.

Separates receiving / transmitting 4 bytes entry FIFO for data payloads.

Supports programmable baud rate generator.

Supports programmable receiver buffer trigger level.

Programmable transmitting data delay time between the last stop bit leaving the
TX-FIFO and the de-assertion by setting EGT (SC_EGT[7:0]).

Programmable even, odd or no parity bit generation and detection.

Programmable stop bit, 1- or 2- stop bit generation
Page 177 of 219
Rev.2.05
M451 SERIES DATASHEET
Mar. 04, 2016

M451
6.15 I2C Serial Interface Controller (I2C)
6.15.1 Overview
2
I C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
2
exchange between devices. The I C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously.
2
There are two sets of I C controller which supports Bus Management (System Management
(SM)/Power Management (PM) bus compatible) and Power-down wake-up function.
6.15.2 Features
2
The I C bus uses two wires (SDA and SCL) to transfer information between devices connected to
2
the bus. The main features of the I C bus include:
2
M451 SERIES DATASHEET

Supports up to two I C ports

Master/Slave mode

Bidirectional data transfer between masters and slaves

Multi-master bus (no central master)

Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus

Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus

Built-in 14-bit time-out counter requesting the I C interrupt if the I C bus hangs up and
timer-out counter overflows.

Programmable clocks allow for versatile rate control

Supports 7-bit addressing mode

Supports multiple address recognition ( four slave address with mask option)

Supports Bus Management (SM/PM compatible) function

Supports Power-down wake-up function
2
Mar. 04, 2016
Page 178 of 219
2
Rev.2.05
M451
6.16 Serial Peripheral Interface (SPI)
6.16.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and
allows full duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bidirection interface. The NuMicro® M451 series contains up to three sets of SPI controllers
performing a serial-to-parallel conversion on data received from a peripheral device, and a
parallel-to-serial conversion on data transmitted to a peripheral device. Each SPI controller can be
configured as a master or a slave device.
SPI0 controller supports 2-bit Transfer mode to perform full-duplex 2-bit data transfer and also
2
supports Dual and Quad I/O Transfer mode. SPI1 and SPI2 controller also support I S mode to
connect external audio CODEC.
SPI2 only supported at M45xG/M45xE Series.
6.16.2 Features

SPI Mode
Up to three sets of SPI controllers

Supports Master or Slave mode operation

Supports 2-bit Transfer mode

Supports Dual and Quad I/O Transfer mode for SPI0

Configurable bit length of a transaction word from 8 to 32-bit

Provides separate 4-/8-level depth transmit and receive FIFO buffers

Supports MSB first or LSB first transfer sequence

Supports Byte Reorder function

Supports PDMA transfer


M451 SERIES DATASHEET

Supports 3-Wire, no slave selection signal, bi-direction interface
2
I S Mode for SPI1 and SPI2

Supports Master or Slave

Capable of handling 8-, 16-, 24- and 32-bit word sizes

Provides separate 4-level depth transmit and receive FIFO buffers

Supports monaural and stereo audio data

Supports PCM mode A, PCM mode B, I S and MSB justified data format

Supports PDMA transfer
2
Mar. 04, 2016
Page 179 of 219
Rev.2.05
M451
6.17 USB Device Controller (USBD)
6.17.1 Overview
There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is
compliant with USB 2.0 full-speed device specification and supports Control/Bulk/Interrupt/
Isochronous transfer types.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes
from the USB PHY transceiver. For the APB bus, the CPU can program control registers through
it. There are 512 bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is
necessary to write data to SRAM or read data from SRAM through the APB interface or SIE. User
needs to set the effective starting address of SRAM for each endpoint buffer through buffer
segmentation register (USBD_BUFSEGx).
There are 8 endpoints in this controller. Each of the endpoint can be configured as IN or OUT
endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are
implemented in this block. The block of “Endpoint Control” is also used to manage the data
sequential synchronization, endpoint state, current start address, transaction status, and data
buffer status for each endpoint.
There are four different interrupt events in this controller. They are the no-event-wake-up, device
plug-in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend
and resume, etc. Any event will cause an interrupt, and users just need to check the related event
flags in interrupt event status register (USBD_INTSTS) to acknowledge what kind of interrupt
occurring, and then check the related USB Endpoint Status Register (USBD_EPSTS) to
acknowledge what kind of event occurring in this endpoint.
A software-disconnect function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables SE0 bit (USBD_SE0), the USB
controller will force the output of USB_D+ and USB_D- to level low and its function is disabled.
After disable the SE0 bit, host will enumerate this USB device again.
For more information on the Universal Serial Bus, please refer to Universal Serial Bus
Specification Revision 1.1.
M451 SERIES DATASHEET
6.17.2 Features

Compliant with USB 2.0 Full-Speed specification

Provides 1 interrupt vector with 4 different interrupt events (NEVWK, VBUSDET, USB
and BUS)

Supports Control/Bulk/Interrupt/Isochronous transfer types

Supports suspend function when no bus activity existing for 3 ms

Supports 8 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer
types and maximum 512 bytes buffer size

Provides remote wake-up capability
Mar. 04, 2016
Page 180 of 219
Rev.2.05
M451
6.18 USB 1.1 Host Controller (USBH)
6.18.1 Overview
This chip is equipped with a USB 1.1 Host Controller (USBH) that supports Open Host Controller
Interface (OpenHCI, OHCI) Specification, a register-level description of a host controller, to
manage the devices and data transfer of Universal Serial Bus (USB).
The USBH supports an integrated Root Hub with a USB port, a DMA for real-time data transfer
between system memory and USB bus, port power control and port over current detection.
The USBH is responsible for detecting the connect and disconnect of USB devices, managing
data transfer, collecting status and activity of USB bus, providing power control and detecting over
current of attached USB devices.
USB 1.1 Host Controller only supported at M45xG/M45xE Series.
6.18.2 Features

Supports Universal Serial Bus (USB) Specification Revision 1.1.

Supports Open Host Controller Interface (OpenHCI) Specification Revision 1.0.

Supports both full-speed (12Mbps) and low-speed (1.5Mbps) USB devices.

Supports Control, Bulk, Interrupt and Isochronous transfers.

Supports an integrated Root Hub.

Supports a USB host port shared with USB device (OTG function).

Supports port power control and port over current detection.

Supports DMA for real-time data transfer.
M451 SERIES DATASHEET
Mar. 04, 2016
Page 181 of 219
Rev.2.05
M451
6.19 USB On-The-Go (OTG)
6.19.1 Overview
The OTG controller interfaces to USB PHY and USB controllers which consist of a USB 1.1 host
controller and a USB 2.0 FS device controller. The OTG controller supports HNP and SRP protocols
defined in the “On-The-Go and Embedded Host Supplement to the USB 2.0 Revision 1.3
Specification”.
USB frame, including USB host, USB device, and OTG controller, can be configured as Host-only,
Device-only, ID-dependent or OTG Device mode defined in USBROLE (SYS_USBPHY[1:0]). In Hostonly mode, USB frame acts as USB host. USB frame can support both full-speed and low-speed
transfer. In Device-only mode, USB frame acts as USB device. USB frame only supports full-speed
transfer. In ID-dependent mode, USB frame can be USB Host or USB device depends on USB_ID pin
state. In OTG device mode, the role of USB frame depends on the definition of OTG specification.
USB frame only supports full-speed transfer when OTG device acts as a peripheral.
USB On-The-Go only supported at M45xG/M45xE Series.
6.19.2 Features

Built in USB PHY

Configurable to operate as:

Host-only

Device-only

ID-dependent: The role of USB frame is only dependent on USB_ID pin value-as USB Host (USB_ID pin is low) or USB Device (USB_ID pin is high). Not
support HNP or SRP protocol.

OTG device: dependent on USB_ID pin status to be A-device (USB_ID pin is
low) or B-device (USB_ID pin is high). Support HNP and SRP protocols.
M451 SERIES DATASHEET
Mar. 04, 2016
Page 182 of 219
Rev.2.05
M451
6.20 Controller Area Network (CAN)
6.20.1 Overview
The C_CAN consists of the CAN Core, Message RAM, Message Handler, Control Registers and
Module Interface. The CAN Core performs communication according to the CAN protocol version 2.0
part A and B. The bit rate can be programmed to values up to 1MBit/s. For the connection to the
physical layer, additional transceiver hardware is required.
For communication on a CAN network, individual Message Objects are configured. The Message
Objects and Identifier Masks for acceptance filtering of received messages are stored in the Message
RAM. All functions concerning the handling of messages are implemented in the Message Handler.
These functions include acceptance filtering, the transfer of messages between the CAN Core and the
Message RAM, and the handling of transmission requests as well as the generation of the module
interrupt.
The register set of the C_CAN can be accessed directly by the software through the module interface.
These registers are used to control/configure the CAN Core and the Message Handler and to access
the Message RAM.
6.20.2 Features
Supports CAN protocol version 2.0 part A and B

Bit rates up to 1 MBit/s

32 Message Objects

Each Message Object has its own identifier mask

Programmable FIFO mode (concatenation of Message Objects)

Maskable interrupt

Disabled Automatic Re-transmission mode for Time Triggered CAN applications

Programmable loop-back mode for self-test operation

16-bit module interfaces to the AMBA APB bus

Supports wake-up function
Mar. 04, 2016
Page 183 of 219
M451 SERIES DATASHEET

Rev.2.05
M451
6.21 CRC Controller (CRC)
6.21.1 Overview
The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with programmable
polynomial settings.
6.21.2 Features

Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
16
12
5

CRC-CCITT: X

CRC-8: X + X + X + 1

CRC-16: X
16
+X
15
+X +1

CRC-32: X
32
+X
26
+X
8
+X
+X +1
2
2
23
+X
22
+X
16
+X
12
+X
11
+X
10
8
7
5
4
2
+X +X +X +X +X +X+1

Programmable seed value

Supports programmable order reverse setting for input data and CRC checksum

Supports programmable 1’s complement setting for input data and CRC checksum

Supports 8/16/32-bit of data width


8-bit write mode: 1-AHB clock cycle operation

16-bit write mode: 2-AHB clock cycle operation

32-bit write mode: 4-AHB clock cycle operation
Supports using PDMA to write data to perform CRC operation
M451 SERIES DATASHEET
Mar. 04, 2016
Page 184 of 219
Rev.2.05
M451
6.22 Enhanced 12-bit Analog-to-Digital Converter (EADC)
6.22.1 Overview
The M451 series contains one 12-bit successive approximation analog-to-digital converter
(SAR A/D converter) with 16 external input channels and 3 internal channels. The A/D
converter can be started by software trigger, PWM0/1 triggers, timer0~3 overflow pulse
triggers, ADINT0, ADINT1 interrupt EOC (End of conversion) pulse trigger and external pin
(STADC) input signal.
6.22.2 Features

Analog input voltage range: 0~VREF (Max to AVDD).

Reference voltage from VREF pin or AVDD.

12-bit resolution and 10-bit accuracy is guaranteed.

Up to 16 single-end analog external input channels or 8 pair differential analog input
channels.

3 internal channels, they are band-gap voltage (VBG), temperature sensor (VTEMP), and
Battery power (VBAT)

Four ADC interrupts (ADINT0~3) with individual interrupt vector addresses.

Maximum ADC clock frequency is 20 MHz.

Up to 1 Msps conversion rate.

Configurable ADC internal sampling time.

Up to 19 sample modules

Each of sample module 0~15 which is configurable for ADC converter channel
EADC_CH0~15 and trigger source.

Sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap
voltage, temperature sensor, and battery power (VBAT).

Double buffer for sample module 0~3

Configurable sampling time for each sample module.

Conversion results are held in 19 data registers with valid and overrun indicators.
An A/D conversion can be started by:

Write 1 to SWTRGn (EADC_SWTRG[n] , n = 0~18)

External pin STADC

Timer0~3 overflow pulse triggers

ADINT0 and ADINT1 interrupt EOC (End of conversion) pulse triggers

PWM triggers
Supports PDMA transfer
Mar. 04, 2016
Page 185 of 219
Rev.2.05
M451 SERIES DATASHEET


M451
6.23 Digital to Analog Converter (DAC)
6.23.1 Overview
The DAC module is a 12-bit, voltage output digital-to-analog converter. It can be used in
conjunction with the PDMA controller. The DAC integrates a voltage output buffer that can be
used to reduce output impendence and drive external loads directly without having to add an
external operational amplifier.
6.23.2 Features

Analog output voltage range: 0~AVDD.

Reference voltage from internal reference voltage (INT_VREF), VREF pin or AVDD.

DAC maximum conversion updating rate 1M sps.

Supports voltage output buffer mode and bypass voltage output buffer mode.

Supports software and hardware trigger to start DAC conversion.

Supports PDMA request.
M451 SERIES DATASHEET
Mar. 04, 2016
Page 186 of 219
Rev.2.05
M451
6.24 Analog Comparator Controller (ACMP)
6.24.1 Overview
The M451 contains two comparators. The comparator output is logic 1 when positive input is
greater than negative input; otherwise, the output is 0. Each comparator can be configured to
generate an interrupt when the comparator output value changes.
6.24.2 Features

Analog input voltage range: 0 ~ VDDA (voltage of AVDD pin)

Supports hysteresis function

Supports wake-up function

Selectable input sources of positive input and negative input

ACMP0 supports

4 positive sources



4 negative sources

ACMP0_N

Comparator Reference Voltage (CRV)

Internal band-gap voltage (VBG)

DAC output (DAC_OUT)
ACMP1 supports

4 positive sources

Mar. 04, 2016
ACMP1_P0, ACMP1_P1, ACMP1_P2, or ACMP1_P3
M451 SERIES DATASHEET


ACMP0_P0, ACMP0_P1, ACMP0_P2, or ACMP0_P3
4 negative sources

ACMP1_N

Comparator Reference Voltage (CRV)

Internal band-gap voltage (VBG)

DAC output (DAC_OUT)
Shares one ACMP interrupt vector for all comparators
Page 187 of 219
Rev.2.05
M451
7
APPLICATION CIRCUIT
AVCC
V REF
AVDD
DVCC
USB_VBUS
USB_DUSB_D+
USB_ID
FB
33R
33R
USB OTG Slot
VDD
VDDIO
0.1uF
Power
1uF
USB_VDD33_CAP
1uF
V BAT
DVCC
0.1uF
VSS
AVSS
4.7K
M451 Series
20p
VDD
SPI Device
VSS
DVCC
VDD
ICE_ CLK
ICE_ DAT
nRESET
VSS
SWD
Interface
CS
CLK
MISO
MOSI
SPI_SS
SPI_CLK
SPI_MISO
SPI_MOSI
FB
DVCC
4.7K
CLK
I2C_SCL
VDD
I2 C Device
XT1_IN
I2C_SDA
20p
DIO
4~ 24 MHz
crystal
DVCC
XT1_OUT
20p
Crystal
X32_IN
20p
32.768 kHz
crystal
X32_OUT
SC_ PWR
Smart Card Slot
SC_ RST
SC_ CLK
SC_ DAT
SC_ Detect
DVCC
M451 SERIES DATASHEET
Reset
Circuit
VSS
CAN Transceiver
10K
CAN_TX
D
CAN_H
CAN_RX
R
CAN_L
ODB Port
CAN
nRST
10uF/10V
RS 232 Transceiver
LDO_ CAP
LDO
RXD
ROUT
TXD
TIN
PC COM Port
RIN
TOUT
UART
1uF
Note1: When chip is powered on, VBAT will have additional leakage due to VBAT power-on detect circuit
still being enabled. Please refer to M451 Errata for detailed description (M45xD/M45xC Only).
Note2: When chip is powered on, the 0.6V glitch will occur on PB.1. If any external device is
connected to this pin, user should avoid this glitch to cause unpredictable behavior on system
(M45xD/M45xC Only).
Mar. 04, 2016
Page 188 of 219
Rev.2.05
M451
8
ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
Symbol
VDD  VSS
VIN
1/tCLCL
Parameter
DC Power Supply
Input Voltage
Oscillator Frequency
Min
Max
Unit
-0.3
+7.0
V
VSS - 0.3
VDD + 0.3
V
4
20
MHz
TA
Operating Temperature
-40
+105
TST
Storage Temperature
-55
+150
℃
IDD
Maximum Current into VDD
-
120
mA
ISS
Maximum Current out of VSS
120
mA
Maximum Current sunk by a I/O pin
35
mA
Maximum Current sourced by a I/O pin
35
mA
Maximum Current sunk by total I/O pins
100
mA
Maximum Current sourced by total I/O pins
100
mA
IIO
Note: Exposure to conditions beyond those listed under absolute maximum ratings may
adversely affect the lift and reliability of the device.
M451 SERIES DATASHEET
Mar. 04, 2016
Page 189 of 219
Rev.2.05
M451
8.2 DC Electrical Characteristics
(VDD - VSS = 2.5 ~ 5.5 V, TA = 25C)
SPECIFICATION
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
VDD
2.5
-
5.5
V
Power supply for
PE.8~PE.13
VDDIO
1.8
-
5.5
V
RTC Operation
voltage for
PF.0~PF.2
VBAT
2.5
-
5.5
V
VSS / AVSS
-0.3
0
0.3
V
LDO Output Voltage
VLDO
1.62
1.8
1.98
V
VDD ≥ 2.5 V
Band-gap Voltage
VBG
1.175
1.21
1.225
V
VDD = 2.5 V ~ 5.5 V, TA = 25C
Allowed voltage
difference for VDD
and AVDD
VDD-AVDD
-0.3
0
0.3
V
IDD1
-
64
-
mA
Operation voltage
Power Ground
Operating Current
VDD = 2.5 V ~ 5.5 V up to 72 MHz
Normal Run Mode
HCLK = 72 MHz
VDD
HXT
HIRC
PLL
All digital
modules
5.5V
12 MHz
X
V
V
IDD2
-
32
-
mA
5.5V
12 MHz
X
V
X
IDD3
-
63
-
mA
3.3V
12 MHz
X
V
V
IDD4
-
31
-
mA
3.3V
12 MHz
X
V
X
IDD5
-
45
-
mA
5.5V
12 MHz
X
V
V
IDD6
-
23
-
mA
5.5V
12 MHz
X
V
X
while(1){}
IDD7
-
45
-
mA
3.3V
12 MHz
X
V
V
executed from flash
IDD8
-
22
-
mA
3.3V
12 MHz
X
V
X
Operating Current
IDD9
-
20
-
mA
5.5V
X
V
X
V
IDD10
-
10
-
mA
5.5V
X
V
X
X
IDD11
-
20
-
mA
3.3V
X
V
X
V
executed from flash
IDD12
-
10
-
mA
3.3V
X
V
X
X
Operating Current
IDD13
-
12
-
mA
5.5V
12 MHz
X
X
V
IDD14
-
6
-
mA
5.5V
12 MHz
X
X
X
while(1){}
IDD15
-
12
-
mA
3.3V
12 MHz
X
X
V
executed from flash
IDD16
-
6
-
mA
3.3V
12 MHz
X
X
X
Operating Current
IDD17
-
3.4
-
mA
5.5V
12 MHz
X
X
V
IDD18
-
1.9
-
mA
5.5V
12 MHz
X
X
X
while(1){}
executed from flash
M451 SERIES DATASHEET
Operating Current
Normal Run Mode
HCLK = 50 MHz
Normal Run Mode
HCLK =22.1184
MHz
while(1){}
Normal Run Mode
HCLK = 12 MHz
Normal Run Mode
Mar. 04, 2016
Page 190 of 219
Rev.2.05
M451
SPECIFICATION
Parameter
HCLK =4 MHz
while(1){}
executed from flash
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
IDD19
-
3.3
-
mA
3.3V
12 MHz
X
X
V
IDD20
-
1.8
-
mA
3.3V
12 MHz
X
X
X
HIRC
PLL
All digital
modules
VDD
IDD21
-
153
-
uA
Operating Current
HCLK = 32.768 kHz
while(1){}
executed from flash
5.5V
32.768
X
X
V
IDD22
139
uA
5.5V
32.768
X
X
X
IDD23
133
uA
3.3V
32.768
X
X
V
uA
3.3V
32.768
X
X
X
PLL
All digital
modules
IDD24
Operating Current
LXT
(kHz)
IDD25
-
-
120
134
-
-
μA
Normal Run Mode
HCLK = 10 kHz
HXT
LIRC
/LXT
(kHz)
5.5V
X
10
X
V
VDD
while(1){}
IDD26
-
130
-
μA
5.5V
X
10
X
X
Executed from
Flash
IDD27
-
121
-
μA
3.3V
X
10
X
V
IDD28
-
117
-
μA
3.3V
X
10
X
X
VDD
HXT
HIRC
PLL
All digital
modules
5.5V
12 MHz
X
V
V
Operating Current
Idle Mode
IIDLE1
-
42
-
mA
HCLK = 72 MHz
Idle Mode
HCLK = 50 MHz
Operating Current
Idle Mode
HCLK =22.1184
MHz
Operating Current
Idle Mode
HCLK =12 MHz
Operating Current
Mar. 04, 2016
-
9
-
mA
5.5V
12 MHz
X
V
X
IIDLE3
-
42
-
mA
3.3V
12 MHz
X
V
V
IIDLE4
-
8
-
mA
3.3V
12 MHz
X
V
X
IIDLE5
-
30
-
mA
5.5V
12 MHz
X
V
V
IIDLE6
-
6
-
mA
5.5V
12 MHz
X
V
X
IIDLE7
-
30
-
mA
3.3V
12 MHz
X
V
V
IIDLE8
-
6
-
mA
3.3V
12 MHz
X
V
X
IIDLE9
-
12
-
mA
5.5V
X
V
X
V
IIDLE10
-
3
-
mA
5.5V
X
V
X
X
IIDLE11
-
12
-
mA
3.3V
X
V
X
V
IIDLE12
-
3
-
mA
3.3V
X
V
X
X
IIDLE13
-
8
-
mA
5.5V
12 MHz
X
X
V
mA
5.5V
12 MHz
X
X
X
IIDLE14
2
IIDLE15
-
8
-
mA
3.3V
12 MHz
X
X
V
IIDLE16
-
2
-
mA
3.3V
12 MHz
X
X
X
IIDLE17
-
2.5
-
mA
5.5V
12 MHz
X
X
V
Page 191 of 219
Rev.2.05
M451 SERIES DATASHEET
Operating Current
IIDLE2
M451
SPECIFICATION
Parameter
Idle Mode
HCLK =4 MHz
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
IIDLE18
-
0.9
-
mA
5.5V
12 MHz
X
X
X
IIDLE19
-
2.4
-
mA
3.3V
12 MHz
X
X
V
IIDLE20
-
0.8
-
mA
3.3V
12 MHz
X
X
X
HIRC
PLL
All digital
modules
Operating Current
Idle Mode
IIDLE21
-
143
-
VDD
uA
32.768 kHz
IIDLE22
-
128
-
32.768
X
X
V
uA
5.5V
32.768
X
X
X
IIDLE23
130
uA
3.3V
32.768
X
X
V
IIDLE24
115
uA
3.3V
32.768
X
X
X
PLL
All digital
modules
IIDLE25
-
131
-
LIRC
(kHz)
5.5V
X
10
X
V
uA
IIDLE26
-
127
-
μA
5.5V
X
10
X
X
IIDLE27
-
118
-
μA
3.3V
X
10
X
V
IIDLE28
-
113
-
μA
3.3V
X
10
X
X
VDD
HXT/HI
RC/PLL
(kHz)
RTC
RAM
retension
5.5V
X
X
X
V
Standby Current
IPWD1
A
20
(Deep Sleep Mode)
M451 SERIES DATASHEET
RTC Operating
Current
HXT
/LXT
VDD
at 10 kHz
Power-down Mode
(kHz)
5.5V
Operating Current
Idle Mode
LXT
LXT
IPWD2
22
A
5.5V
X
32.768
V
V
IPWD3
18
A
3.3V
X
X
X
V
IPWD4
20
A
3.3V
X
32.768
V
V
1.7
1.9
8.1
uA
VBAT = 5.0 V, 32.768 kHz external low speed crystal
oscillator (LXT), RTC ON and VDD/AVDD power
domain OFF.
1.6
1.8
7.7
uA
VBAT = 3.0 V, 32.768 kHz external low speed crystal
oscillator (LXT), RTC ON and VDD/AVDD power
domain OFF.
IVBAT
Input Current at
/RESET[1]
IIN
-55
-45
-30
A
VDD = 3.3V, VIN = 0.45V
Logic 0 Input
Current (Quasibidirectional mode)
IIL
-
-67
-75
A
VDD = VDDIO = VBAT = 5.5 V, VIN = 0V
Logic 1 to 0
Transition Current
(Quasi-bidirectional
mode) [*3]
ITL
-
-610
-650
A
VDD = VDDIO = VBAT =5.5 V, VIN = 2.0V
Input Leakage
Current
ILK
-1
-
+1
A
Mar. 04, 2016
VDD = VDDIO = VBAT =5.5 V, 0 < VIN < VDD
Open-drain or input only mode
Page 192 of 219
Rev.2.05
M451
SPECIFICATION
Parameter
Symbol
Input Low Voltage
(TTL input)
VIL1
Input Low Voltage
(TTL input for PE8
~ PE13)
VIL2
Input High Voltage
(TTL input)
VIH2
Hysteresis voltage of
PA, PB, PC, PD,PE,
PF (Schmitt input)
VHY
Input Low Voltage
XT1[*2]
VIL3
X32 Output Pin
Typ.
Max.
-0.3
-
0.8
-0.3
-
0.6
-0.3
-
0.3
2.0
-
VDD +
0.3
1.5
-
VDD +
0.3
1.0
-
VDDIO +
0.3
0.2VDD
-
0.8
0
-
0.4
3.5
-
VDD +
0.3
2.4
-
VDD +
0.3
VIH3
VIL4
0
Input High Voltage
X32I[*4]
VIH4
VXOUT
+0.3
VIL5
-0.3
VIH5
0.7 VDD
Internal nRESET
pin pull up resistor
RRST
40
Input Low Voltage
(Schmitt input)
VIL6
-0.3
VIL7
VIH6
(Schmitt input),
nRST
Input High Voltage
(Schmitt input)
Mar. 04, 2016
VDD = VBAT = 2.5 ~ 5.5 V
VDDIO = 1.8 V
VDD = VDDIO = VBAT = 5.5 V
VDD = VDDIO = VBAT = 3.0 V
V
VDD = VBAT = 2.5 ~ 5.5 V
VDDIO = 1.8 V
V
VDD = 4.5 V
VDD = 2.5 V
V
VDD = 5.5 V
VDD = 3.0 V
0.9
V
VXOUT 0.3
V
1.8
V
-
0.2 VDD
V
-
VDD +
0.3
V
150
kΩ
-
0.3 VDD
V
VDD = VDDIO = VBAT = 2.5 ~ 5.5 V
-0.3
-
0.3
VDDIO
V
VDDIO = 1.8 V ~ 5.5V
0.7 VDD
-
VDD +
0.3
V
VDD = VDDIO = VBAT = 2.5 ~ 5.5 V
-
Input Low Voltage
(Schmitt input for
PE8~ PE13)
V
M451 SERIES DATASHEET
Input Low Voltage
X32I[*4]
Positive going
threshold
VDD = VDDIO = VBAT = 2.5 V
V
0
0.6
(Schmitt input),
nRST
VDD = VDDIO = VBAT = 4.5 V
V
VXOUT
Negative going
threshold
Unit
V
VIH1
Input High Voltage
(TTL input for PE8
~ PE13)
Input High Voltage
XT1[*2]
Test Conditions
Min.
Page 193 of 219
Rev.2.05
M451
SPECIFICATION
Parameter
Symbol
Input Low Voltage
Test Conditions
Min.
Typ.
Max.
Unit
(Schmitt input for
PE8~ PE13)
VIH7
0.7
VDDIO
-
VDDIO +
0.3
V
VDDIO = 1.8 V ~ 5.5V
Source Current
(Quasi-bidirectional
Mode)
ISR11
-300
-400
-
A
VDD = VDDIO = VBAT = 4.5 V, VS = 2.4 V
ISR12
-50
-80
-
A
VDD = VDDIO = VBAT = 2.7 V, VS = 2.2 V
ISR13
-40
-73
-
A
VDD = VDDIO = VBAT = 2.5 V, VS = 2.0 V
Source Current
(Quasi-bidirectional
Mode for PE8~
PE13)
ISR14
-11
-19
Source Current
(Push-pull Mode)
ISR21
-20
-26
-
mA
VDD = VDDIO = VBAT = 4.5 V, VS = 2.4 V
ISR22
-3
-5.2
-
mA
VDD = VDDIO = VBAT = 2.7 V, VS = 2.2 V
ISR23
-2.5
-5
-
mA
VDD = VDDIO = VBAT = 2.5 V, VS = 2.0 V
ISR24
-1
-1.5
ISR31
-28
-47
-
mA
ISR32
-5.3
-8.8
-
mA
ISR33
-4.9
-8.1
-
mA
ISR34
-1.5
-2.5
ISK11
10
17
-
mA
VDD = VDDIO = VBAT = 4.5 V, VS = 0.45 V
ISK12
6
11
-
mA
VDD = VDDIO = VBAT = 2.7 V, VS = 0.45 V
ISK13
5
10
-
mA
VDD = VDDIO = VBAT = 2.5 V, VS = 0.45 V
ISK14
3.6
6
mA
ISK21
14.7
24.5
mA
ISK22
9.2
15.3
mA
ISK23
8.5
14.1
mA
A
VDD = VBAT = 2.5 ~ 5.5 V
VDDIO = 1.8 V, VS = 1.6 V
Source Current
(Set IO as Push-pull
Mode and basic
driving strength
mA
VDD = VBAT = 2.5 ~ 5.5 V
VDDIO = 1.8 V, VS = 1.6 V
Only for
PE8~PE13)
Source Current
(Set IO as Push-pull
Mode and high
driving strength
M451 SERIES DATASHEET
Only for
PE8~PE13)
Sink Current
(Quasi-bidirectional,
Open-Drain and
Push-pull Mode)
mA
Sink Current
(Only for
PE8~PE13)
Sink Current
(Set IO as high
driving strength
Only for
PE8~PE13)
Mar. 04, 2016
VDD = VBAT = 2.5 ~ 5.5 V
VDDIO = 4.5 V, VS = 2.4 V
VDD = VBAT = 2.5 ~ 5.5 V
VDDIO = 2.7 V, VS = 2.2 V
VDD = VBAT = 2.5 ~ 5.5 V
VDDIO = 2.5 V, VS = 2.0 V
VDD = VBAT = 2.5 ~ 5.5 V
VDDIO = 1.8 V, VS = 1.6 V
VDD = VBAT = 2.5 ~ 5.5 V
VDDIO = 1.8 V, VS = 0.45 V
VDD = VBAT = 2.5 ~ 5.5 V
VDDIO = 4.5 V, VS = 0.45 V
VDD = VBAT = 2.5 ~ 5.5 V
VDDIO = 2.7 V, VS = 0.45 V
VDD = VBAT = 2.5 ~ 5.5 V
VDDIO = 2.5 V, VS = 0.45 V
Page 194 of 219
Rev.2.05
M451
SPECIFICATION
Parameter
Symbol
ISK24
Test Conditions
Min.
Typ.
5.4
9
Max.
Unit
mA
VDD = VBAT = 2.5 ~ 5.5 V
VDDIO = 1.8 V, VS = 0.45 V
Notes:
1. nRESET pin is a Schmitt trigger input.
2. XT1_IN is a CMOS input.
3. All pins can source a transition current when they are being externally driven from 1 to 0. In the
condition of VDD=5.5V, the transition current reaches its maximum value when V IN approximates to 2V.
4. If X32I is as external clock input, the input high voltage should be lower than 1.8V to avoid chip
damage.
M451 SERIES DATASHEET
Mar. 04, 2016
Page 195 of 219
Rev.2.05
M451
8.3 AC Electrical Characteristics
8.3.1 External 4~24 MHz High Speed Crystal (HXT) Input Clock
tCLCL
tCLCH
VIH
90%
tCLCX
VIL
10%
tCHCL
tCHCX
Note: Duty cycle is 50%.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tCHCX
Clock High Time
10
-
-
ns
-
tCLCX
Clock Low Time
10
-
-
ns
-
tCLCH
Clock Rise Time
2
-
15
ns
-
tCHCL
Clock Fall Time
2
-
15
ns
-
VIH
Input High Voltage
0.7VDD
VDD
V
-
VIL
Input Low Voltage
0
0.3VDD
V
-
8.3.2 External 4~20 MHz High Speed Crystal (HXT) Oscillator
M451 SERIES DATASHEET
Symbol
Parameter
Min.
Typ.
Max
Unit
Test Conditions
VHXT
Operation Voltage
2.5
-
5.5
V
-
TA
Temperature
-40
-
105
℃
-
-
2
-
mA
12 MHz, VDD = 5.5V
IHXT
Operating Current
-
0.8
-
mA
4
-
20
MHz
fHXT
8.3.2.1
Clock Frequency
12 MHz, VDD = 3.3V
-
Typical Crystal Application Circuits
Crystal
C1
C2
4 MHz ~ 20 MHz
10~20 pF
10~20 pF
Mar. 04, 2016
Page 196 of 219
Rev.2.05
M451
XTAL1
XTAL2
4~20 MHz
Crystal
C1
C2
Vss
Vss
Figure 8.3-1 Typical Crystal Application Circuit
8.3.3 22.1184 MHz Internal High Speed RC Oscillator (HIRC)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VHRC
Supply Voltage
1.62
1.8
1.98
V
-
Center Frequency
-
22.1184
MHz
-
-1
-
+1
%
-2
-
+2
%
-
790
-
μA
fHRC
TA = 25 ℃, VDD = 5 V
Calibrated Internal
Oscillator Frequency
IHRC
Operating Current
TA = -40
~ 105
VDD = 2.5 V ~ 5 .5 V
TA = 25 ℃, VDD = 5 V
HIRC oscillator accuracy vs. temperature
Deviation Percentage %
0.60%
-50
0.40%
0.20%
0.00%
-0.20% 0
50
100
150
Max
-0.40%
Min
-0.60%
-0.80%
-1.00%
-1.20%
-1.40%
TA ℃
Note: Number of test samples: 10.
Figure 8.3-2 HIRC Accuracy vs. Temperature
Mar. 04, 2016
Page 197 of 219
Rev.2.05
M451 SERIES DATASHEET
0.80%
M451
8.3.4 32.768 kHz External Low Speed Crystal (LXT) Input Clock
tCLCL
tCLCH
Xin_VIH
90%
tCLCX
Xin_VIL
10%
tCHCL
tCHCX
Note: Duty cycle is 50%.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tCHCX
Clock High Time
TBD
-
-
ns
-
tCLCX
Clock Low Time
TBD
-
-
ns
-
tCLCH
Clock Rise Time
TBD
-
TBD
ns
-
tCHCL
Clock Fall Time
TBD
-
TBD
ns
-
Xin_VIH
LXT Input Pin Input High Voltage
Xout+0.3
1.8
V
-
Xin_VIL
LXT Input Pin Input Low Voltage
0
Xout-0.3
V
-
Xout
LXT Output Pin
0.6
0.9
V
8.3.5 32.768 kHz External Low Speed Crystal (LXT) Oscillator
Parameter
M451 SERIES DATASHEET
Condition
Min.
Typ.
Max.
Unit
Operation Voltage VBAT
-
2.5
-
5.5
V
Operation Temperature
-
-40
-
105
℃
Operation Current
32.768KHz at VBAT=5V
Clock Frequency
External crystal
8.3.5.1
A
1.6
-
32.768
-
kHz
LXT Typical Crystal Application Circuits
Mar. 04, 2016
CRYSTAL
C1
C2
32.768 kHz
10~20 pF
10~20 pF
Page 198 of 219
Rev.2.05
M451
X32_IN
X32_OUT
Crystal
C1
C2
Vss
Vss
Figure 8.3-3 Typical Crystal Application Circuit
8.3.6 10 kHz Internal Low Speed RC Oscillator (LIRC)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VLRC
Supply Voltage
2.5
-
5.5
V
-
Center Frequency
-
10
-
kHz
-
-30
-
+30
%
-50
-
+50
%
fLRC
VDD = 2.5 V ~ 5.5 V
TA = 25
Oscillator Frequency
VDD = 2.5 V ~ 5.5 V
TA = -40
~ +105
M451 SERIES DATASHEET
Mar. 04, 2016
Page 199 of 219
Rev.2.05
M451
8.4 Analog Characteristics
8.4.1 12-bit SAR ADC
Symbol
-
Parameter
Min
Resolution
Typ
Max
12
Unit
Test Condition
Bit
-
DNL
Differential Nonlinearity Error
-
-
±2
LSB
-
INL
Integral Nonlinearity Error
-
-
±2
LSB
-
EO
Offset Error
-
3
-
LSB
-
EG
Gain Error (Transfer Gain)
-
-3
-
LSB
-
EA
Absolute Error
-
4
-
LSB
-
-
-
-
Monotonic
Guaranteed
-
FADC
-
21
ADC Clock Frequency
AVDD = 4.5~5.5 V
MHz
-
-
8.4
-
-
1000
AVDD = 2.5~5.5 V
AVDD = 4.5~5.5 V
kSPS
TCONV = 21 clock
FADC = 21 Mhz
FS
Sample Rate (FADC/TCONV)
AVDD = 2.5~5.5 V
-
-
400
kSPS
TCONV = 21 clock
FADC = 8.4 Mhz
TACQ
Acquisition Time (Sample Stage)
TCONV
Total Conversion Time
2~9
1/FADC
16~23
1/FADC
Default: 6 (1/FADC)
EADC_SCTLx[31:24]=0
TCONV = TACQ+ 15
Default: 21 (1/FADC)
M451 SERIES DATASHEET
EADC_SCTLx[31:24]=0
AVDD#1
Supply Voltage
IDDA#1
VIN#1
VREF
CIN#1
RIN#1
2.5
-
5.5
V
Supply Current (Avg.)
-
2.8
-
mA
Analog Input Voltage
0
-
VREF
V
-
Reference Voltage
2.5
-
AVDD
V
AVDD = 5 V
Input Capacitance
-
6
-
pF
-
Input Load
-
6.5
-
kΩ
-
AVDD = 5 V
Note:
#1: Design by guarantee, no test in production.
Mar. 04, 2016
Page 200 of 219
Rev.2.05
M451
EF (Full scale error) = EO + EG
Gain Error
EG
Offset Error
EO
4095
4094
4093
4092
Ideal transfer curve
7
6
ADC
output
code
5
Actual transfer curve
4
3
2
DNL
1
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
Typical connection diagram using the ADC
VDD
(1)
RIN
AINx
12-bit
Converter
(1)
CIN
Figure 8.4-1 Typical connection diagram using the ADC
(1) Refer to ADC spec for the values of RIN, CIN
Mar. 04, 2016
Page 201 of 219
Rev.2.05
M451 SERIES DATASHEET
Note: The INL is the peak difference between the transition point of the steps of the calibrated
transfer curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the
offset and gain error from the actual transfer curve.
M451
8.4.2 LDO
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
VDD
DC Power Supply
2.5
-
5.5
V
-
VLDO
Output Voltage
1.62
1.8
1.98
V
-
TA
Temperature
-40
25
105
℃
Notes:
1. It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of
the device.
2. For ensuring power stability, a 1μF Capacitor must be connected between LDO_CAP pin and the
closest VSS pin of the device.
8.4.3 Low Voltage Reset
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
AVDD
Supply Voltage
0
-
5.5
V
-
TA
Temperature
-40
25
105
℃
-
ILVR
Quiescent Current
-
1
5
μA
AVDD = 5.5 V
2.00
2.20
2.45
V
TA = 105 ℃
1.90
2.00
2.10
V
TA = 25 ℃
1.70
1.90
2.10
V
TA = -40 ℃
VLVR
Threshold Voltage
8.4.4 Brown-out Detector
M451 SERIES DATASHEET
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
AVDD
Supply Voltage
0
-
5.5
V
-
TA
Temperature
-40
25
105
℃
-
IBOD
Quiescent Current
-
-
140
μA
AVDD = 5.5 V
4.2
4.4
4.6
V
BOV_VL [1:0] = 11
Brown-out Voltage
3.5
3.7
3.9
V
BOV_VL [1:0] = 10
(Falling edge)
2.55
2.7
2.85
V
BOV_VL [1:0] = 01
2.05
2.2
2.35
V
BOV_VL [1:0] = 00
4.3
4.5
4.7
V
BOV_VL [1:0] = 11
Brown-out Voltage
3.6
3.8
4.0
V
BOV_VL [1:0] = 10
(Rising edge)
2.6
2.75
2.9
V
BOV_VL [1:0] = 01
2.1
2.25
2.4
V
BOV_VL [1:0] = 00
VBOD
VBOD
Mar. 04, 2016
Page 202 of 219
Rev.2.05
M451
8.4.5 Power-on Reset
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
TA
Temperature
-40
25
105
℃
-
VPOR
Reset Voltage
1.6
2
2.4
V
-
VPOR
VDD Start Voltage to Ensure
Power-on Reset
-
-
100
mV
RRVDD
VDD Raising Rate to Ensure
Power-on Reset
0.025
-
-
V/ms
tPOR
Minimum Time for VDD Stays at
VPOR to Ensure Power-on Reset
0.5
-
-
ms
VDD
tPOR
RRVDD
VPOR
Time
Figure 8.4-2 Power-up Ramp Condition
Symbol
Parameter
Min
Typ
Max
Unit
TA
Temperature
-40
-
105
℃
ITEMP
Current Consumption
-
16
-
μA
-
Gain
-1.55
-1.672
-1.75
mV/℃
-
Offset
735
748
755
mV
Test Condition
TA = 0 ℃
Note:
1. The temperature sensor formula for the output voltage (Vtemp) is as below equation.
2. Vtemp (mV) = Gain (mV/
Mar. 04, 2016
) x Temperature (
) + Offset (mV)
Page 203 of 219
Rev.2.05
M451 SERIES DATASHEET
8.4.6 Temperature Sensor
M451
8.4.7 Comparator
Symbol
Parameter
Min
Typ
Max
Unit
VCMP
Supply Voltage
2.5
-
5.5
V
TA
Temperature
-40
25
105
℃
-
ICMP
Operation Current
-
35
70
μA
AVDD = 5 V
VOFF
Input Offset Voltage
mV
AVDD = 5 V
VSW
Output Swing
0.1
-
AVDD - 0.1
V
-
VCOM
Input Common Mode Range
0.1
-
AVDD – 0.1
V
-
-
DC Gain
40
70*
-
dB
-
TPGD
Propagation Delay
-
125
-
ns
VCM = 1.2 V,
VDIFF = 0.1 V
VHYS
Hysteresis
-
±40
±60
mV
AVDD = 5 V
TSTB
Stable time
-
0.26
1
μs
AVDD = 5 V
Test Condition
10
Test Condition
Note:
*Guaranteed by design, not tested in production.
8.4.8 12-bit DAC
M451 SERIES DATASHEET
Symbol
Parameter
Min
Typ
Max
Unit
AVDD
Analog Supply Voltage
2.5
-
5.5
V
NR
Resolution
VREF
Reference Supply Voltage
DNL
Differential Non-linearity Error
INL
OE
GE
AE
12
2.5
-
AVDD
-
±0.5
-1
V
10-bit, buffer OFF
LSB
-
±0.5
-2.5
-
-
±1
Integral Non-linearity Error
12-bit, buffer OFF
10-bit, buffer OFF
LSB
-
-
±2.5
-
-
+1
Offset Error
12-bit, buffer OFF
10-bit, buffer OFF
LSB
-
-
+2
-
-
-2
Gain Error
12-bit, buffer OFF
10-bit, buffer OFF
LSB
-
-
-8
-
-
-2
-
-
-8
12-bit, buffer OFF
LSB
10-bit, buffer OFF
Absolute Error
-
Monotonic
VO
Output Voltage
0.1
RLOAD
Resistive Load
7.5
RO
Output Impedance
CLOAD
Capacitive Load
Mar. 04, 2016
bit
12-bit, buffer OFF
10-bit guaranteed
VREF – 0.15
V
Buffer ON
-
-
kΩ
Buffer ON
-
8.2
22.5
kΩ
-
-
20
pF
Page 204 of 219
Buffer OFF
Rev.2.05
M451
-
--
50
Buffer ON
IDDA
Analog Supply Current
-
-
350
uA
AVDD = 5.5V, buffer ON
IREF
Reference Supply Current
-
-
260
uA
VREF = 5.5V
TSTAB
Settling Time
-
4
8
us
Transition between the
lowest and the highest
input codes when VO
reaches final value ±1
LSB
FS
Update Rate
-
-
1
MSPS
Transition between
adjacent codes
TWAKEUP
Wake-up Time
-
-
10
us
Min.
Typ.
Max.
Unit
Test Condition
5.5
V
-
8.4.9 Internal Voltage Reference
Symbol
Parameter
VVREF
AVDD
2.5
Vref1
Vref(2.56V)
2.483
2.560
2.637
V
AVDD >= 2.9V
Vref2
Vref(2.048V)
1.986
2.048
2.109
V
AVDD >= 2.5V
Vref3
Vref(3.072V)
2.98
3.072
3.164
V
AVDD >= 3.4V
Vref4
Vref(4.096V)
3.973
4.096
4.219
V
AVDD >= 4.5V
Min.
Typ.
Max.
Unit
Test Conditions
2.0
-
V
-
-
-
V
-
0.2
-
V
|PADP-PADM|
0.8
-
2.5
V
Includes VDI range
0.8
-
2.0
V
-
Receiver Hysteresis
-
200
mV
-
VOL
Output Low (driven)
0
-
0.3
V
-
VOH
Output High (driven)
2.8
-
3.6
V
-
VCRS
Output Signal Cross Voltage
1.3
-
2.0
V
-
RPU
Pull-up Resistor
1.425
-
1.575
kΩ
-
ZDRV
Driver Output Resistance
-
10
-
Ω
Steady state drive*
CIN
Transceiver Capacitance
-
-
20
pF
Pin to GND
8.4.10 USB PHY
8.4.10.1 Low-full-Speed DC Electrical Specifications
Parameter
VIH
Input High (driven)
VIL
Input Low
VDI
Differential Input Sensitivity
VCM
VSE
Differential
Common-mode Range
Single-ended Receiver
Threshold
0.8
*Driver output resistance doesn’t include series resistor resistance.
Mar. 04, 2016
Page 205 of 219
Rev.2.05
M451 SERIES DATASHEET
Symbol
M451
8.4.10.2 USB Full-Speed Driver Electrical Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
TFR
Rise Time
4
-
20
ns
CL=50p
TFF
Fall Time
4
-
20
ns
CL=50p
TFRFF
Rise and Fall Time Matching
90
-
111.11
%
TFRFF=TFR/TFF
Min.
Typ.
Max.
Unit
Test Conditions
8.4.10.3 USB LDO Specification
Symbol
Parameter
VBUS
VBUS Pin Input Voltage
4.0
5.0
5.5
V
-
VDD33
LDO Output Voltage
2.97
3.3
3.63
V
-
Cbp
External Bypass Capacitor
-
1.0
-
uF
-
M451 SERIES DATASHEET
Mar. 04, 2016
Page 206 of 219
Rev.2.05
M451
8.5 Flash DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
VFLA[2]
Supply Voltage
1.62
1.8
1.98
V
NENDUR
Endurance
20,000
-
TRET
Data Retention
100
-
TERASE
Page Erase Time
TPROG
Test Condition
cycles[1]
-
year
20
-
ms
Program Time
60
-
us
IDD1
Read Current
-
-
13.5
mA
IDD2
Program Current
-
10
-
mA
IDD3
Erase Current
-
12
-
mA
TA = 25
Notes:
1. Number of program/erase cycles.
2. VFLA is source from chip LDO output voltage.
M451 SERIES DATASHEET
Mar. 04, 2016
Page 207 of 219
Rev.2.05
M451
8.6 I2C Dynamic Characteristics
Symbol
Standard Mode[1][2]
Fast Mode[1][2]
Min.
Max.
Min.
Max.
Unit
Parameter
tLOW
SCL low period
4.7
-
1.2
-
uS
tHIGH
SCL high period
4
-
0.6
-
uS
tSU; STA
Repeated START condition setup time
4.7
-
1.2
-
uS
tHD; STA
START condition hold time
4
-
0.6
-
uS
tSU; STO
STOP condition setup time
4
-
0.6
-
uS
tBUF
Bus free time
4.7[3]
-
1.2[3]
-
uS
tSU;DAT
Data setup time
250
-
100
-
nS
tHD;DAT
Data hold time
0[4]
3.45[5]
0[4]
0.8[5]
uS
tr
SCL/SDA rise time
-
1000
20+0.1Cb
300
nS
tf
SCL/SDA fall time
-
300
-
300
nS
Cb
Capacitive load for each bus line
-
400
-
400
pF
Notes:
M451 SERIES DATASHEET
1. Guaranteed by design, not tested in production.
2
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I C frequency. It must
2
be higher than 8 MHz to achieve the maximum fast mode I C frequency.
2
3. I C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to
bridge the undefined region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch
the low period of SCL signal.
STOP
Repeated
START
START
STOP
SDA
tBUF
tLOW
tr
SCL
tHD;STA
tf
tHIGH
tHD;DAT
tSU;DAT
tSU;STA
tSU;STO
2
Figure 8.6-1 I C Timing Diagram
Mar. 04, 2016
Page 208 of 219
Rev.2.05
M451
8.7 SPI Dynamic Characteristics
8.7.1 Dynamic Characteristics of Data Input and Output Pin
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
SPI MASTER MODE (VDD = 4.5 V~5.5V, 30 PF LOADING CAPACITOR)
tW(SCKH)
tW(SCKL)
SPI high and low time, peripheral clock
= 20MHz
tDS
22.5
-
27.5
ns
Data input setup time
2
-
-
ns
tH(MI)
Data input hold time
4
-
-
ns
tV
Data output valid time
-
-
1
ns
tH(MO)
Data output hold time
0
-
-
ns
27.5
ns
SPI MASTER MODE (VDD = 3.0~3.6 V, 30 PF LOADING CAPACITOR)
tW(SCKH)
tW(SCKL)
SPI high and low time, peripheral clock
= 20MHz
tDS
Data input setup time
2
ns
tH(MI)
Data input hold time
4
ns
tV
Data output valid time
tH(MO)
Data output hold time
22.5
-
0
-
1
ns
-
-
ns
CLKPOL=0
TXNEG=1
RXNEG=0
CLKPOL=1
TXNEG=0
RXNEG=1
tV
M451 SERIES DATASHEET
SPI Clock
tr(SCK) tf(SCK)
SPI data output
(SPI_MOSI)
Data Valid
tDS
SPI data input
(SPI_MISO)
Data Valid
tDH
Data Valid
Data Valid
CLKPOL=0
TXNEG=0
RXNEG=1
SPI Clock
CLKPOL=1
TXNEG=1
RXNEG=0
tV
SPI data output
(SPI_MOSI)
Data Valid
tDS
SPI data input
(SPI_MISO)
Data Valid
tDH
Data Valid
Data Valid
Figure 8.7-1 SPI Master Mode Timing Diagram
Mar. 04, 2016
Page 209 of 219
Rev.2.05
M451
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
SPI SLAVE MODE (VDD = 4.5 V~5.5V, 30 PF LOADING CAPACITOR)
Peripheral
clock
tSS
Slave select setup time
3
-
-
tSH
Slave select hold time
2
-
-
tDS
Data input setup time
2
-
-
ns
tH(SI)
Data input hold time
5.5
-
-
ns
ta(SO)
Data output access time
-
-
18
ns
tV
Data output valid time
-
18.5-
24.5
ns
tH(SO)
Data output hold time
6
-
-
ns
Peripheral
clock
Peripheral
clock
SPI SLAVE MODE (VDD = 3.0 V ~ 3.6 V, 30 PF LOADING CAPACITOR)
tSS
Slave select setup time
3
-
-
tSH
Slave select hold time
2
-
-
tDS
Data input setup time
2
-
-
ns
tH(SI)
Data input hold time
6
-
-
ns
ta(SO)
Data output access time
-
-
24
ns
tV
Data output valid time
-
23
30
ns
tH(SO)
Data output hold time
7
-
-
ns
Peripheral
clock
M451 SERIES DATASHEET
Mar. 04, 2016
Page 210 of 219
Rev.2.05
M451
SSACTPOL=1
SPI SS
tSS
tSH
SSACTPOL=0
CLKPOL=0
TXNEG=1
RXNEG=0
SPI Clock
CLKPOL=1
TXNEG=0
RXNEG=1
tV
SPI data output
(SPI_MISO)
Data Valid
Data Valid
tDS
SPI data input
(SPI_MOSI)
Data Valid
SSACTPOL=1
SPI SS
tDH
Data Valid
tSS
tSH
SSACTPOL=0
CLKPOL=0
TXNEG=0
RXNEG=1
SPI Clock
CLKPOL=1
TXNEG=1
RXNEG=0 ta(so)
tV
SPI data output
(SPI_MISO)
Data Valid
tDS
tDH
Data Valid
Data Valid
M451 SERIES DATASHEET
SPI data input
(SPI_MOSI)
Data Valid
Figure 8.7-2 SPI Slave Mode Timing Diagram
Mar. 04, 2016
Page 211 of 219
Rev.2.05
M451
8.8
I2S Dynamic Characteristics
Symbol
tw(CKH)
Parameter
I2S clock high time
2
Min
Max
42
-
Unit
Test Conditions
Master fPCLK = MHz, data: 24 bits, audio
frequency = 256 kHz
tw(CKL)
I S clock low time
37
-
tv(WS)
WS valid time
7
-
th(WS)
WS hold time
1
-
Master mode
tsu(WS)
WS setup time
34
-
Slave mode
th(WS)
WS hold time
0
-
Slave mode
DuCy(SCK)
I2S slave input clock
duty cycle
25
75
0
-
Master receiver
0
-
Slave receiver
0
-
Master receiver
0
-
tsu(SD_MR)
%
Slave mode
Data input setup time
tsu(SD_SR)
th(SD_MR)
Master mode
ns
Data input hold time
th(SD_SR)
Slave receiver
ns
tv(SD_ST)
Data output valid time
-
32
Slave transmitter (after enable edge)
th(SD_ST)
Data output hold time
16
-
Slave transmitter (after enable edge)
tv(SD_MT)
Data output valid time
-
5
Master transmitter (after enable edge)
th(SD_MT)
Data output hold time
0
-
Master transmitter (after enable edge)
M451 SERIES DATASHEET
Mar. 04, 2016
Page 212 of 219
Rev.2.05
CK output
M451
CPOL = 0
tw(CKH)
CPOL = 1
tw(CKL)
tv(WS)
th(WS)
WS output
tv(SD_ST)
LSB transmit(2)
SDtransmit
MSB transmit
tsu(SD_MR)
LSB receive(2)
SDreceive
Bitn transmit
th(SD_ST)
LSB transmit
th(SD_MR)
MSB receive
Bitn receive
LSB receive
2
Figure 8.8-1 I S Master Mode Timing Diagram
CK Input
CPOL = 0
CPOL = 1
tw(CKH)
tw(CKL)
th(WS)
WS input
tv(SD_ST)
tsu(WS)
LSB transmit(2)
MSB transmit
tsu(SD_SR)
SDreceive
LSB receive(2)
Bitn transmit
LSB transmit
th(SD_SR)
MSB receive
Bitn receive
LSB receive
2
Figure 8.8-2 I S Slave Mode Timing Diagram
Mar. 04, 2016
Page 213 of 219
Rev.2.05
M451 SERIES DATASHEET
SDtransmit
th(SD_ST)
M451
9
PACKAGE DIMENSIONS
9.1 LQFP 100L (14x14x1.4 mm footprint 2.0 mm)
M451 SERIES DATASHEET
Mar. 04, 2016
Page 214 of 219
Rev.2.05
M451
9.2 LQFP 64L (10x10x1.4 mm footprint 2.0 mm)
M451 SERIES DATASHEET
Mar. 04, 2016
Page 215 of 219
Rev.2.05
M451
9.3 LQFP 64L (7x7x1.4 mm footprint 2.0 mm)
M451 SERIES DATASHEET
Mar. 04, 2016
Page 216 of 219
Rev.2.05
M451
9.4 LQFP 48L (7x7x1.4mm2 Footprint 2.0mm)
H
36
25
37
24
48
13
H
12
1

Controlling dimension : Millimeters
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Y
0
Mar. 04, 2016
Dimension in inch
Dimension in mm
Min Nom Max
Min Nom Max
0.002 0.004
0.006
0.05
0.055
0.057
1.35
1.40
1.45
0.006 0.008
0.010
0.15
0.20
0.25
0.004 0.006
0.008
0.10
0.15
0.20
0.272 0.276
0.280
6.90
7.00
7.10
0.272 0.276
0.280
6.90
7.00
7.10
0.020
0.026
0.35
0.50
0.65
0.053
0.014
0.10
0.15
0.350
0.354
0.358
8.90
9.00
9.10
0.350
0.354
0.358
8.90
9.00
9.10
0.018
0.024
0.030
0.45
0.60
0.75
1.00
0.039
0.004
0
M451 SERIES DATASHEET
Symbol
7
Page 217 of 219
0.10
0
7
Rev.2.05
M451
10 REVISION HISTORY
Date
Revision
Description
2014.08.22
1.00
1. Preliminary version.
1. Updated document format.
2. Updated the VBAT pin description to “Power supply by batteries for RTC and
PF.0~PF.2” in section 4.3.
2015.03.30
1.01
3. Added GPIO information for Power Distribution in section 6.2.4.
4. Revised maximum clock of HXT from 24 MHz to 20 MHz..
5. Revised M451 selection guide in section 4.1.
2015.05.11
2.00
1. Added new part number for M45xD/M45xC and the description about the difference
with M45xG/M45xE.
2. Added 6.2.2.1~6.2.2.7 and 6.2.2 to describe reset sources and power modes.
2015.05.21
2.01
2015.6.12
2.02
1. Revised M451 selection guide in section 4.1.
2. Updated System Reset description in section 6.2.2.1.
1. Added description to note that VREF, LDO_CAP and USB_VDD33_CAP need to be
connected with a 1uF capacitor in section 4.3, 6.2.4 and chapter 7.
2. Added two notes of chip limitations in section 6.2.4 and chapter 7.
1. Changed “external counter input” to “external capture input” in section 4.3.
2. Added a note to indicate LQFP 64L package dimension of M451M series in section
4.1.3.錯誤! 找不到參照來源。
2015.09.01
2.03
3. Added lists to indicate 5V-tolerance pins in section 2.1 and 6.6.2.
4. Added “EBI” column into selection guides in section 4.1.
5. Revised bank size of SRAM Memory Organization (M45xD/M45xC) from 16 KB to 8
KB in Figure 6.2-10.
M451 SERIES DATASHEET
2016.01.29
2.04
1. Removed Touch Key in M451 series.
2016.03.04
2.05
1. Updated general description.
Mar. 04, 2016
Page 218 of 219
Rev.2.05
M451
Important Notice
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Mar. 04, 2016
Page 219 of 219
Rev.2.05
M451 SERIES DATASHEET
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.