MPQ4485 36V, 6A, Step-Down Converter with Dual USB Charging Ports Supporting Type-C 5V @ 3A DFP Mode and BC1.2 CDP Mode for Automotive, AEC-Q100 Qualified DESCRIPTION FEATURES The MPQ4485 integrates a monolithic, stepdown, switch-mode converter with two USB current-limit switches and charging port identification circuitry. The MPQ4485 achieves 6A of output current with excellent load and line regulation over a wide input supply range. The output of the USB switch is current-limited. USB1 supports DCP schemes for battery charging specification (BC1.2), divider mode, 1.2V/1.2V mode, and USB Type-C 5V @ 3A DFP mode, eliminating the need for outside user interaction. USB2 supports DCP and CDP schemes. Full protection features include hiccup current limiting, output over-voltage protection (OVP), and thermal shutdown. The MPQ4485 requires a minimal number of readily available, standard, external components and is available in a QFN-26 (5mmx5mm) package. Wide 6V to 36V Operating Input Voltage Range Fixed 5.17V Output Voltage 90mV Line Drop Compensation Accurate USB1/USB2 Output Current Limit 18mΩ/15mΩ Low RDS(ON) Internal Buck Power MOSFETs 18mΩ/18mΩ Low RDS(ON) Internal USB1/USB2 Power MOSFETs 450kHz Switching Frequency Forced CCM Operation Load Shedding versus Temperature for MPQ4485GU-LS-AEC1 USB Output Over-Voltage Protection (OVP) Fast Over-Current Response for USB Switch Hiccup Current Limit Supports DCP Schemes for BC1.2, Divider Mode, and 1.2V/1.2V Mode USB1 Supports USB Type-C 5V @ 3A Mode, USB2 Supports CDP Mode ±8kV HBM ESD Rating for USB, DP, DM, DP_OUT, and DM_OUT Available in a QFN-26 (5mmx5mm) Package Available in AEC-Q100 Grade 1 APPLICATIONS USB Charging Downstream Port (CDP) USB Dedicated Charging Ports (DCP) USB Type-C Charging Port All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. MPQ4485 Rev.1.0 9/18/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 1 MPQ4485 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS TYPICAL APPLICATION C4 Efficiency vs. Load Current 220nF VIN 12V BST C1 100µF C1A 50µF + IN SW USB1 EN MPQ4485 R1 0Ω C3 1µF 4.7µH OUT POL MODE VCC DM1 DP1 CC2 CC1 USB2 DM2 DP2 DP2_OUT AGND PGND DM2_OUT Vout=5.17V C2A 20µF + 100 C2 270µF 96 C5 4.7µF R4 150Ω C6 4.7µF U S B USB1, 3A C7 1nF R3 1kΩ L3, Bead, 1kΩ@100MHz U S B USB2, 2.5A Efficiency(%) L1 92 88 84 Vin=12V 80 Vin=6V 76 Vin=36V 72 0 1 2 3 4 Load Current (A) 5 To Host Controller MPQ4485 Rev.1.0 9/18/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 2 MPQ4485 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS ORDERING INFORMATION Part Number MPQ4485GU-AEC1* MPQ4485GU-LS-AEC1** Package Top Marking QFN-26 (5mmx5mm) See Below * For Tape & Reel, add suffix –Z (e.g. MPQ4485GU-AEC1–Z) ** For Tape & Reel, add suffix –Z (e.g. MPQ4485GU-LS-AEC1–Z) DEVICE COMPARISON INFORMATION Part Number MPQ4485GU-AEC1 MPQ4485GU-LS-AEC1 Load Shedding versus Temperature No Yes TOP MARKING MPS: MPS prefix YY: Year code WW: Week code MP4485: Product code LLLLLLL: Lot number PACKAGE REFERENCE TOP VIEW CC2 DM1 DP1 EN DP2 DM2 23 22 21 20 19 24 DP2_OUT 18 CC1 1 17 DM2_OUT USB1 2 16 USB2 OUT 3 15 OUT IN 4 14 IN 13 PGND 25 OUT 26 SW PGND 5 6 7 AGND VCC 8 SW 9 10 11 SW BST POL 12 MODE QFN-26 (5mmx5mm) MPQ4485 Rev.1.0 9/18/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 3 MPQ4485 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS θJA θJC ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance Supply voltage (VIN) ..................... -0.4V to +40V VSW ................................... -0.3V (-5V for <10ns) to VIN + 0.3V (43V for <10ns) VBST ..................................................VSW + 5.5V VEN .......................................... -0.3V to +10V (2) VOUT, VUSB ...................................................................................... -0.3V to +6.5V All other pins ............................... -0.3V to +5.5V Continuous power dissipation (TA = +25°C) (3) QFN-26 (5mmx5mm) ............................... 6.25W Junction temperature ............................... 150°C Lead temperature .................................... 260°C Storage temperature ................ -65°C to +150°C QFN-26 (5mmx5mm) JESD51-7 (5) ......................... 44 ........ 9 .... °C/W 50mmx50mm 4-Layer PCB ... 20 ........ 2 .... °C/W Recommended Operating Conditions (4) Operation input voltage range ............ 6V to 36V Output current ........ 3A for USB1, 2.5A for USB2 Operating junction temp. (TJ)... -40°C to +125°C MPQ4485 Rev.1.0 9/18/2017 NOTES: 1) Absolute maximum ratings are rated under room temperature unless otherwise noted. Exceeding these ratings may damage the device. 2) For details on EN’s ABS max rating, please refer to the EN Control section on page 13. 3) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. Measured on a 4-layer PCB (50mmx50mm). 4) The device is not guaranteed to function outside of its operating conditions. 5) Measured on JESD51-7, 4-layer PCB. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 4 MPQ4485 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS ELECTRICAL CHARACTERISTICS VIN = 12V, VEN = 5V, CC1 to ground with 5.1kΩ resistor, TJ = -40°C to +125°C tested at TJ = +25°C, unless otherwise noted. Parameter Symbol Supply current (shutdown) Supply current (quiescent) EN rising threshold EN hysteresis EN pull-up current Thermal shutdown Thermal hysteresis (7) (7) VCC regulator VCC load regulation Step-Down Converter VIN under-voltage lockout threshold rising VIN under-voltage lockout threshold hysteresis HS switch on resistance LS switch on resistance Output voltage IIN IQ Output to ground resistance Low-side current limit Switch leakage Minimum on time (7) Soft-start time USB Switch Units 18 -3% 13 1 1.235 230 8 μA mA V mV μA 4 +3% 12 C TSTD_HYS 20 VCC VCC_LOG 4.3 4.6 1 4.9 3 C V % 4.6 5 5.4 V ICC = 50mA VIN_UVLO VUVLO_HYS 700 RDSON_HS RDSON_LS 18 15 5.17 5.17 5.85 5.7 40 30 +1% +2% 6.25 6.1 mΩ mΩ 160 -2 220 kΩ A TJ = +25°C TJ = -40°C to+125°C VOVP_R VOVP_F RFB TJ = +25°C -1% -2% 5.45 5.3 100 ILS_LIMIT ILIMIT fSW DMAX VEN = 0V, VSW = 36V or 0V, TJ = +25°C VEN = 0V, VSW = 36V or 0V, TJ = -40°C to +125°C VOUT = 0V 130 VUSB_UVR Under-voltage lockout threshold hysteresis VUSB_UVHYS Switch on resistance RDSON_SW RDIS_USB 8 360 91 16 540 99 A kHz % ns ns 1 2 3.4 ms 3.7 4 4.3 V 200 USB disabled, apply 5V voltage on USB output V V μA TON_MIN Output from 10% to 90% V 5 TOFF_MIN FREQ = 450kHz mV 1 12 450 95 110 Under-voltage lockout threshold rising MPQ4485 Rev.1.0 9/18/2017 Max 165 tSS Output discharge resistance Typ TSTD SW LKG High-side current limit Oscillator frequency Maximum duty cycle Minimum off time , typical value is Min VEN = 0V No switching VEN_Rising VEN_HYS IEN VOUT Output over-voltage protection Output OVP recovery Condition (6) 250 mV 18 35 mΩ 500 750 kΩ www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 5 MPQ4485 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, VEN = 5V, TJ = -40°C to +125°C (6), typical value is tested at TJ = +25°C, unless otherwise noted. Parameter Symbol USB OVP clamp VUSB_OV ILimit1 Current limit ILimit2 Line drop compensation VBUS soft-start time Hiccup mode on time Hiccup mode off time BC1.2 DCP Mode DP and DM short resistance VDROP_COM TSS THICP_ON THICP_OFF RDP/DM_Short Condition VOUT drop 10%, Type-C mode, TJ = +25°C VOUT drop 10%, Type-A mode, TJ = +25°C IOUT = 2.4A, VOUT = 5V VOUT = 5V, from 10% to 90% VOUT = 5V, OC, VOUT drop 10%, TJ = +25°C VOUT = 5V, OC, VOUT drop 10%, TJ = -40°C to +125°C VBUS connected to GND Min Typ Max Units 5.3 5.6 5.9 V -6% 3.55 6% 2.6 2.75 2.9 40 1 90 2 140 3 3.5 5 6.5 A mV ms ms 3 5 7 1 2 3 85 155 85 160 2.55 2.7 2.85 V 14 12 22 22 30 34 kΩ 1.12 1.1 70 1.2 1.2 105 1.28 1.3 140 TJ = -40°C to +125°C 60 105 150 CC1 pin, for Type-C mode application, add a 1nF capacitor on CC1 70 VDP = 0.8V, IDM = 1mA, TJ = +25°C VDP = 0.8V, IDM = 1mA, TJ = -40°C to +125°C s Ω Divider Mode DP/DM output voltage VDP/DM_Divider VOUT = 5V DP/DM output impedance RDP/DM_Divider TJ = +25°C TJ = -40°C to +125°C 1.2V/1.2V Mode DP/DM output voltage VDP/DM_1.2V DP/DM output impedance RDP/DM_1.2V VOUT = 5V, TJ = +25°C VOUT = 5V, TJ = -40°C to +125°C TJ = +25°C V kΩ USB Type-C 5V @ 3A Mode (CC1, CC2) CC resistor to disable Type-C mode CC voltage to enable VCONN CC voltage to enable VBUS CC detach threshold CC voltage falling debounce timer CC voltage rising debounce timer VCONN output power POL output low voltage POL leakage MPQ4485 Rev.1.0 9/18/2017 RA VRa VRd VOPEN 0.9 2.75 90 kΩ 0.75 2.45 V V V TCC_debounce VBUS enable deglitch 100 144 200 ms TPD_debounce VBUS disable deglitch 10 15 20 ms PVCONN VPOL VCONN comes from buck output with some series resistance, TJ = +25°C Pull CC1 to ground with 5.1kΩ resistor, POL sink 1mA 1 ILeakage_POL www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. W 150 mV 1 µA 6 MPQ4485 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, VEN = 5V, TJ = -40°C to +125°C (6), typical value is tested at TJ = +25°C, unless otherwise noted. Parameter Symbol Condition VMODE_H MODE has 1MΩ pull-up resistor to internal VDD Min Typ Max Units CDP (MODE) MODE logic high voltage MODE logic low voltage VMODE_L DM CDP output voltage VDM_SRC VDP = 0.6V DP rising lower window VDAT_RE threshold for VDM_SRC activation DP rising lower window threshold hysteresis for VDAT_RE_HYS VDM_SRC activation DP rising upper window threshold for VDM_SRC VLGC_SRC deactivation DP rising upper window threshold hysteresis for VLGC_SRC_HYS VDM_SRC deactivation VDM_SRC_Deglit VDM_SRC on/off deglitch time 2 V 0.5 0.6 0.7 0.7 V V 0.25 0.3 0.4 V 100 0.8 0.9 mV 1 150 mV 5 ms ch RDP_Down, RDM_Down DP/DM switch on resistance DP to DP_OUT SW on cap (7) 3dB bandwidth of analog data SW (7) RDP/DM_Down RON_DP/DM CDP 14.25 19.5 2 5.3 Same for DM switch 500 V 24.8 kΩ Ω pF MHz NOTES: 6) All min/max parameters are tested at TJ = 25oC. Limits over temperature are guaranteed by design, characterization and correlation. 7) Guaranteed by design. MPQ4485 Rev.1.0 9/18/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 7 MPQ4485 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VOUT = 5.17V, L = 4.7µH, TA = 25°C, set USB1 to Type-C 5V @ 3A DFP mode, set USB2 to CDP mode, unless otherwise noted. Efficiency vs. Load Current Line Drop Compensation vs. Load Current Efficiency(%) 96 92 88 84 Vin=12V 80 Vin=6V 76 Vin=36V 72 0 1 2 3 4 Load Current (A) 5 Line Drop Compensation(mV) 100 100 90 80 70 60 50 40 30 20 10 0 0 1 2 Load Current (A) 3 Thermal Image Thermal Image VIN = 12V, USB1_IOUT = USB2_IOUT = 2.4A, four-layer PCB VIN = 12V, USB1_IOUT = 3A, USB2_IOUT = 2.4A, four-layer PCB USB2 Eye Pattern Test Recommended CDP mode set-up MPQ4485 Rev.1.0 9/18/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 8 MPQ4485 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 5.17V, L = 4.7µH, TA = 25°C, set USB1 to Type-C 5V @ 3A DFP mode, set USB2 to CDP mode, unless otherwise noted. Output Ripple Output Ripple USB1_Io = USB2_Io = 0A USB1_Io = 3A, USB2_Io = 2.4A CH1: CH1: USB1_VOUT/AC USB1_VOUT/AC 20mV/div. CH2: 20mV/div. CH2: USB2_VOUT/AC USB2_VOUT/AC 20mV/div. 20mV/div. CH3: VSW 10V/div. CH3: VSW 10V/div. CH4: IL 2A/div. CH4: IL 5A/div. 2µs/div. 2µs/div. Power Start-Up Power Start-Up USB1_Io = USB2_Io = 0A USB1_Io = 3A, USB2_Io = 2.4A CH1: CH1: USB1_VOUT USB1_VOUT 5V/div. 5V/div. CH2: CH2: USB2_VOUT USB2_VOUT 5V/div. 5V/div. CH3: VIN CH3: VIN 10V/div. 10V/div. R1: USB1_IOUT R1: USB1_IOUT 5A/div. 5A/div. CH4:USB2_IOUT CH4:USB2_IOUT 5A/div. 5A/div. 40ms/div. 40ms/div. Power Shutdown Power Shutdown USB1_Io = USB2_Io = 0A USB1_Io = 3A, USB2_Io = 2.4A CH1: CH1: USB1_VOUT USB1_VOUT 5V/div. 5V/div. CH2: CH2: USB2_VOUT USB2_VOUT 5V/div. 5V/div. CH3: VIN CH3: VIN 10V/div. 10V/div. R1: USB1_IOUT R1: USB1_IOUT 5A/div. 5A/div. CH4:USB2_IOUT CH4:USB2_IOUT 5A/div. 5A/div. 40ms/div. MPQ4485 Rev.1.0 9/18/2017 4ms/div. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 9 MPQ4485 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 5.17V, L = 4.7µH, TA = 25°C, set USB1 to Type-C 5V @ 3A DFP mode, set USB2 to CDP mode, unless otherwise noted. Load Shedding Entry (For MPQ4485GU-LS-AEC1 Only) Load Shedding Recovery (For MPQ4485GU-LS-AEC1 Only) USB1_Io = 0.5A USB1 load current from 0.5A to 0A CH1: USB1_VOUT 2V/div. CH1: USB1_VOUT 2V/div. CH2: VCC1 1V/div. CH2: VCC1 1V/div. CH4: USB1_IOUT 1A/div. CH4: USB1_IOUT 1A/div. 10ms/div. 2s/div. USB1 Over-Current Protection CH1: USB1_VOUT 5V/div. CH4: USB1_IOUT 2A/div. 2ms/div. MPQ4485 Rev.1.0 9/18/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 10 MPQ4485 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS PIN FUNCTIONS QFN 5x5 Pin # Name 1 CC1 2 3, 15, 25 USB1 OUT 4, 14 IN 5, 13 PGND 6 7 8, 9, 26 AGND VCC SW 10 BST 11 POL 12 MODE 16 17 USB2 DM2_OUT 18 DP2_OUT 19 DM2 20 DP2 21 EN 22 DP1 23 DM1 24 CC2 MPQ4485 Rev.1.0 9/18/2017 Description Configuration channel. CC1 is used to detect connections and configure the interface across the USB1 Type-C cables and connectors. Once a connection is established, CC1 or CC2 is reassigned to provide power over the VCONN pin of the plug. USB1 output. Buck output. OUT is the power input for USB1 and USB2. Supply voltage. IN is the drain of the internal power device and provides power to the entire chip. The MPQ4485 operates from a 6V to 36V input voltage. The input capacitor (CIN) can prevent large voltage spikes at the input. Place CIN as close to the IC as possible. Power ground. PGND is the reference ground of the regulated output voltage. PGND requires extra care during the PCB layout. Connect PGND to GND with copper traces and vias. Analog ground. Connect AGND to PGND. Internal 4.6V LDO regulator output. Decouple VCC with a 0.22µF capacitor. Switch output. Use a wide PCB trace to make the connection. Bootstrap. A 0.1µF capacitor is connected between SW and BST to form a floating supply across the high-side switch driver. Type-C plug orientation indication. When POL is low, CC1 is used as the CC pin. When POL is high, CC2 is used as the CC pin. USB2 mode control. Float MODE to set USB2 to DCP mode. Pull MODE low to set USB2 to CDP mode. MODE has a 1MΩ pull-up resistor to the internal VCC. USB2 output. D- data line output. D+ data line output. D- data line to USB2 connector. DM2 is the input/output used for handshaking with portable devices. D+ data line to USB2 connector. DP2 is the input/output used for handshaking with portable devices. On/off control input. EN has an internal auto pull-up with a 8μA current source. D+ data line to USB1 connector. DP1 is the input/output used for handshaking with portable devices. D- data line to USB1 connector. DM1 is the input/output used for handshaking with portable devices. Configuration channel. CC2 is used to detect connections and configure the interface across the USB1 Type-C cables and connectors. Once a connection is established, CC1 or CC2 is reassigned to provide power over the VCONN pin of the plug. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 11 MPQ4485 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS BLOCK DIAGRAM IN 8µA EN Current Sense Amplifier VCC Regulator VCC Σ Oscillator Reference Bootstrap Regulator HS Driver Current Limit Comparator Control Logic R2 R1 SS VCC PGND Error Amplifier PWM Comparator 5V OVP Comparator Curent Sense Vconn from OUT USB1 Rd2 Discharge CC1 Curent Sense CC2 Rd4 Charge Pump UVLO Control Logic Current Limit Discharge Type-C Control Thermal Sense AGND SW LS Driver Line Drop Compensation OUT BST USB2 5V 1MΩ DP2_OUT CDP Control 2.7V 1.2V MODE DM2_OUT DP2 Auto Detect DM2 DP1 DM1 Figure 1: Functional Block Diagram MPQ4485 Rev.1.0 9/18/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 12 MPQ4485 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS OPERATION BUCK CONVERTER SECTION The MPQ4485 integrates a monolithic, synchronous, rectified, step-down, switch-mode converter with internal power MOSFETs and two USB current-limit switches with charging port auto-detection. The MPQ4485 offers a compact solution that achieves 6A of continuous output current with excellent load and line regulation over a wide input-supply range. The MPQ4485 operates in a fixed-frequency, peak-current-mode control to regulate the output voltage. The internal clock initiates the pulse-width modulation (PWM) cycle, which turns on the integrated high-side power MOSFET (HS-FET). The HS-FET remains on until its current reaches the value set by the COMP voltage (VCOMP). When the power switch is off, it remains off until the next clock cycle begins. If the duty cycle reaches 95% (450kHz switching frequency) in one PWM period, the current in the power MOSFET cannot reach the COMP-set current value, and the power MOSFET turns off. Error Amplifier (EA) The error amplifier (EA) compares the internal feedback voltage against the internal reference (REF) and outputs VCOMP. VCOMP controls the power MOSFET current. The optimized, internal compensation network minimizes the external component count and simplifies the control loop design. Internal VCC Regulator The 4.6V internal regulator powers most of the internal circuitries. This regulator takes VIN and operates in the full VIN range. When VIN exceeds 4.6V, the output of the regulator is in full regulation. If VIN is less than 4.6V, the output decreases with VIN. VCC requires an external 1µF ceramic decoupling capacitor. After the buck output starts up, the internal VCC LDO output is biased by the buck output through a Schottky diode. MPQ4485 Rev.1.0 9/18/2017 Enable Control (EN) The MPQ4485 has an enable control (EN) pin. An internal 8μA pull-up current allows EN to be floated for automatic start-up. Pull EN high or float EN to enable the IC. Pull EN low to disable the IC. EN is clamped internally using a 7.6V series Zener diode and a 10V breakdown voltage of the ESD cell (see Figure 2). Connect EN through a pull-up resistor to VIN to enhance the EN pull-up current ability. This requires limiting the EN voltage below 10V or limiting the EN input current below 500μA if the EN pull-up voltage is larger than 10V. For example, if connecting EN to VIN = 36V, then RPULLUP ≥ (36V - 10V)/500μA = 52kΩ. 8µA EN 100kΩ ESD 10V GND 7.6V EN Logic Figure 2: Zener Diode between EN and GND Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) protects the chip from operating at an insufficient supply voltage. The UVLO comparator monitors the input voltage. The UVLO rising threshold is 5V, and its falling threshold is 4.3V. Internal Soft Start (SS) Soft start (SS) prevents the converter output voltage from overshooting during start-up. When the chip starts up, the internal circuitry generates an SS voltage that ramps up from 0V to 5V. When SS is lower than REF, the error amplifier uses SS as the reference. When SS is higher than REF, the error amplifier uses REF as the reference. The SS time is set to 2ms internally. If the output of the MPQ4485 is pre-biased to a certain voltage during start-up, the IC disables the switching of both the high-side and low-side switches until the voltage on the internal SS capacitor exceeds the internal feedback voltage. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 13 MPQ4485 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS Forced CCM Operation The MPQ4485 works in forced continuous conduction mode (CCM) continuously. The MPQ4485 operates in a fixed switching frequency regardless of whether it is operating in light load or full load. The advantage of CCM is the controllable frequency, smaller output ripple, and sufficient bootstrap charge time, but it also has low efficiency at light-load condition. A proper inductance should be selected to avoid triggering the low-side switch's negative current limit (typically 2A, from SW to GND). If the negative current limit is triggered, the lowside switch turns off, and the high-side switch turns on when the internal clock begins. Buck Over-Current Protection (OCP) The MPQ4485 has a cycle-by-cycle overcurrent limit when the inductor peak current exceeds the current-limit threshold, and the FB voltage drops below the under-voltage (UV) threshold (typically 50% below the reference). Once UV is triggered, the MPQ4485 enters hiccup mode to restart the part periodically. This protection mode is especially useful when the output is dead-shorted to ground. This reduces the average short-circuit current greatly, alleviates thermal issues, and protects the regulator. The MPQ4485 exits hiccup mode once the over-current condition is removed. Buck Output Over-Voltage Protection (OVP) The MPQ4485 has output over-voltage protection (OVP). If the output is higher than 5.85V, the high-side switch stops turning on. The low-side switch turns on to discharge the output voltage until the output decreases to 5.7V, and then the chip resumes normal operation. Floating Driver and Bootstrap Charging An external bootstrap capacitor powers the floating power MOSFET driver. This floating driver has its own UVLO protection. The UVLO’s rising threshold is 2.2V with a hysteresis of 150mV. The bootstrap capacitor voltage is regulated internally by VIN and VCC through D1, D2, M1, C4, L1, and C2 (see Figure 5). The BST capacitor (C4) voltage is charged up quickly by VCC through M1. MPQ4485 Rev.1.0 9/18/2017 The 2.5μA input to the BST current source can also charge the BST capacitor when the lowside switch does not turn on. VIN 2.5µA M1 D1 VCC BST D2 C4 VOUT L1 Turn on PMOS when LS is turn on SW C2 Figure 3: Internal Bootstrap Charging Circuit Start-Up and Shutdown If both IN and EN exceed their respective thresholds, the chip is enabled. The reference block starts first, generating a stable reference voltage and current, and then the internal regulator is enabled. The regulator provides a stable supply for the remaining circuitries. Three events can shut down the chip: EN low, IN low, and thermal shutdown. During shutdown, the signaling path is blocked to avoid any fault triggering. Then VCOMP and the internal supply rail are pulled down. The floating driver is not subject to this shutdown command. Buck Output Impedance The buck does not involve an output discharge function during EN shutdown. After EN shuts down, there are only two feedback resistors connected to OUT, which have a typical resistance of 160kΩ in total. USB CURRENT-LIMIT SWITCH SECTION Over-Current Protection (OCP) and Hiccup The MPQ4485 integrates two USB current-limit switches. The MPQ4485 provides built-in softstart circuitry, which controls the rising slew rate of the output voltage to limit inrush current and voltage surges. When the load current reaches the current-limit threshold, the USB power MOSFET works in a constant current-limit mode (see Figure 6). If the over-current limit condition lasts longer than 5ms (VOUT does not drop too low), the corresponding USB channel enters hiccup mode with 5ms of on time and 2s of off time. Another USB channel works normally. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 14 MPQ4485 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS Vout(V) Iout(A) Current Limit 5 0 5ms t Figure 6: Over-Current Limit After the soft-start finishes, if the USB output voltage is lower than 3.5V and lasts longer than 50µs, the MPQ4485 enters hiccup mode without having to wait 5ms (see Figure 7). This can prevent an abnormal thermal rise during the constant resistor (CR) load over-current case. Vout(V) Iout(A) Current Limit 5 Enter hiccup mode 0 50us t Figure 7: Over-Current Limit for CR Load Fast Response for Short-Circuit Protection (SCP) If the load current increases rapidly due to a short-circuit event, the current may exceed the current-limit threshold before the control loop is able to respond. If the current reaches the 7A secondary current-limit level, a fast turn-off circuit activates to turn off the power MOSFET. This can help limit the peak current through the switch, keeping the buck output voltage from dropping too much and affecting another USB channel. The total short-circuit response time is less than 1µs. When the fast turn-off function is triggered, the MOSFET turns off for 100µs and restarts with a soft start. During the restart process, if the short still remains, the MPQ4485 regulates the gate voltage to hold the current at a normal currentlimit level. MPQ4485 Rev.1.0 9/18/2017 Output Line Drop Compensation The MPQ4485 can compensate for an output voltage drop, such as high impedance caused by a long trace, to maintain a fairly constant output voltage at the load-side voltage. The internal comparator compares the currentsense output voltage of the two current-limit switches and uses the larger current-sense output voltage to compensate for the line drop voltage. The line drop compensation amplitude increases linearly as the load current increases and also has an upper limitation. The default line drop amplitude at a >2.4A output current is 90mV. USB Output Over-Voltage Protection (OVP) To protect the device at the cable terminal, the USB switch output has a fixed over-voltage protection (OVP) threshold. When the input voltage is higher than the OVP threshold, the output voltage is clamped at the OVP threshold value. USB Output Discharge and Impedance Each USB switch has a fast discharge path that can discharge the external output capacitor’s energy quickly during a power shutdown. This function is active when the CC pins are released or the part is disabled (input voltage is under UVLO or EN off). The discharge path is turned off when the USB output voltage is discharged below 50mV. After the fast discharge path turns off, there is only a high impedance resistor (typically 500kΩ) from USB1 or USB2 to ground. Auto Detection The MPQ4485 USB1 integrates a USBdedicated charging port auto-detect function. This function recognizes most mainstream portable devices and supports the following charging schemes: USB battery charging specification BC1.2/ Chinese Telecommunications Industry Standard YD/T 1591-2009 Divider mode 1.2V/1.2V mode USB Type-C 5V @ 3A DFP mode www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 15 MPQ4485 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS The auto-detect function is a state machine that supports all of the DCP charging schemes above. Connect DP and DM with a 150Ω resistor for DCP mode. CDP Mode USB2 supports dynamically selectable DCP or CDP mode. Float MODE to set USB2 to DCP mode. Pull MODE low to set USB2 to CDP mode. To achieve better data transmission performance, use USB2 CDP mode for handshaking and bypass DP to DP_OUT only. DM to DM_OUT switches internally (see Figure 8). DM2 DP2 MPQ4485 R3, 1kΩ TypeA L3,Bead, 1kΩ@100MHz DM2_OUT DP2_OUT To HOST Controller Figure 8: Data Transmission Enhanced Set-Up Type-C Plug Orientation Indication (POL) POL is an open-drain output that indicates the Type-C plug's orientation. When POL is low, CC1 is used as the CC pin. When POL is high, CC2 is used as the CC pin. USB Type-C Mode and VCONN For USB Type-C solutions, two pins (CC1, CC2) on the connector are used to establish and manage the source-to-sink connection. The general concept for setting up a valid connection between a source and sink is based on being able to detect terminations residing in the product being attached. To aid in defining the functional behavior of CC, a pull-up (Rp) and pull-down (Rd 5.1kΩ) termination model is used based on a pull-up resistor and pull-down resistor (see Figure 9). Figure 9: Current Source/Pull-Down CC Model MPQ4485 Rev.1.0 9/18/2017 Initially, a source exposes independent Rp terminations on its CC1 and CC2 pins, and a sink exposes independent Rd terminations on its CC1 and CC2 pins, the source-to-sink combination of this circuit configuration represents a valid connection. To detect this, the source monitors CC1 and CC2 for a voltage lower than its unterminated voltage. The choice of Rp is a function of the pull-up termination voltage and the source’s detection circuit. This indicates that either a sink, a powered cable, or a sink connected via a powered cable has been attached. Prior to the application of VCONN, a powered cable exposes Ra (typically 1kΩ) on its VCONN. Ra represents the load on VCONN plus any resistive elements to ground. In some cable plugs, this might be pure resistance, and in others, it may be simply the load. The source must be able to differentiate between the presence of Rd and Ra to know whether there is a sink attached and where to apply VCONN. The source is not required to source VCONN unless Ra is detected. Two special termination combinations on the CC pins as seen by a source are defined for directly attached accessory modes: Ra/Ra for audio adapter accessory mode and Rd/Rd for debug accessory mode (see Figure 10 and Table 1). Figure 10: CC Functional Block A port that behaves as a source has the following functional characteristics. 1. The source uses a MOSFET to enable or disable power delivery across VBUS. Initially, the source is disabled. 2. The source supplies pull-up resistors (Rp) on CC1 and CC2 and monitors both to detect a sink. The presence of an Rd pull- www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 16 MPQ4485 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS down resistor on either CC1 or CC2 indicates that a sink is being attached. The value of Rp indicates the initial USB Type-C current level supported by the host. The MPQ4485 default Rp is 10kΩ, which represents a 3A current level. 3. The source uses the CC pull-down characteristic to detect and determine which CC pin is intended to supply VCONN (when Ra is discovered). 4. Once a sink is detected, the source enables VBUS and VCONN. 5. The source can adjust the value of dynamically to indicate a change available USB Type-C current to a sink. example, at high temperatures, MPQ4485GU-LS-AEC1 changes Rp 22kΩ to indicate a 1.5A current ability. Rp in For the to 6. The source monitors the continued presence of Rd to detect a sink detachment. When a detach event is detected, the source is removed, and VBUS and VCONN return to step 2. Load Shedding versus Temperature The MPQ4485GU-LS-AEC1 monitors the die temperature and changes its output current capability dynamically. This feature is supported by both Type-C and USB2.0 applications. When the die temperature is higher than 125°C, the USB port's CC pin pull-up resistance Rp changes to 22kΩ to indicate that its source capability has changed to 1.5A. Meanwhile, VBUS changes to 4.77V. If the die temperature is lower than 100°C for 16 seconds, VBUS reverts to the normal voltage set by OUT_SEL. Meanwhile, the USB Type-C current capability changes back to 3A (Rp = 10kΩ). The current limit threshold remains at 3.55A during this period. Thermal Shutdown Thermal shutdown prevents the chip from operating at exceedingly high temperatures. When the silicon die temperature exceeds 165°C, the entire chip shuts down. When the temperature falls below its lower threshold, (typically 145°C), the chip is enabled. Disable Type-C Mode During the MPQ4485 initial start-up, the IC sources 10µA for 20µs on CC1. If the CC1 voltage falls into the 400mV to 1.2V voltage range, USB1 latches in Type-A mode unless the part is re-enabled. Type-C mode is disabled, so CC is attached, the detach logic is disabled, and VBUS is always enabled. The current limit changes to a Type-A spec. To trigger Type-A mode, the external pull-down resistor should be 70 - 90kΩ. Do not connect extra capacitors on CC1. In normal Type-C mode applications, a 1nF capacitor should be added on CC1 to avoid falsely triggering Type-A mode. The MPQ4485 also supports debug mode and audio adapter accessory mode in Type-C applications. If two Ra resistors pull down CC1 and CC2 or two Rd resistors pull down CC1 and CC2, there is no action inside the IC (VBUS is not enabled). MPQ4485 Rev.1.0 9/18/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 17 MPQ4485 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS Table 2: CC Logic Truth Table EN CC of USB1 Buck VCONN (USB1) USB1 USB2 0 X AUDIO DEBUG “A” (8) Rd, Ra Open Disabled Enabled Enabled Enabled Enabled Enabled Disabled Disabled Disabled Disabled Enabled Disabled Disabled Disabled Disabled Enabled Enabled Disabled Disabled Enabled Enabled Enabled Enabled Enabled 1 NOTE: 8) "A" means Type-A mode. CC1 is requested to be pulled down by a 80.6kΩ resistor to enter this mode. MPQ4485 Rev.1.0 9/18/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 18 MPQ4485 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS APPLICATION INFORMATION Selecting the Inductor For most applications, use an inductor with a DC current rating at least 25% higher than the maximum load current. Select an inductor with a small DC resistance for optimum efficiency. For most designs, the inductor value can be derived with Equation (1): V (VIN VOUT ) L1 OUT VIN IL fOSC (1) Where ∆IL is the inductor ripple current. Choose the inductor ripple current at approximately 30% of the maximum load current. The maximum inductor peak current can be calculated with Equation (2): IL(MAX ) ILOAD IL 2 (2) Selecting Buck Input Capacitor The input current to the step-down converter is discontinuous and therefore requires a capacitor to supply AC current while maintaining the DC input voltage. Use low ESR capacitors for the best performance. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. 100µF electrolytic and 50µF ceramic capacitors are recommended for automotive applications. Since the input capacitor (C1) absorbs the input switching current, it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated with Equation (3): IC1 ILOAD VOUT VOUT 1 VIN VIN (3) The worst-case condition occurs at VIN = 2VOUT, shown in Equation (4): IC1 ILOAD 2 (4) For simplification, choose an input capacitor with an RMS current rating greater than half of the maximum load current. MPQ4485 Rev.1.0 9/18/2017 The input capacitor can be electrolytic, tantalum, or ceramic. When using an electrolytic capacitor, place two additional high-quality ceramic capacitors as close to IN as possible. Estimate the input voltage ripple caused by the capacitance with Equation (5): VIN ILOAD V V OUT 1 OUT fS C1 VIN VIN (5) Selecting Buck Output Capacitor The device requires an output capacitor (C2) to maintain the DC output voltage. Estimate the output voltage ripple with Equation (6): VOUT VOUT VOUT 1 fS L1 VIN 1 RESR 8 f C2 S (6) Where L1 is the inductor value, and RESR is the equivalent series resistance (ESR) value of the output capacitor. For an electrolytic capacitor, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated with Equation (8): ΔVOUT VOUT V 1 OUT fS L1 VIN RESR (8) A 100 - 270μF capacitor with an ESR less than 50mΩ (e.g.: polymer or tantalum capacitors) and two 10μF ceramic capacitors are recommended in the application. ESD Protection for I/O Pins A higher ESD level should be considered for all USB I/O pins. The MPQ4485 features high ESD protection up to ±8kV human body model on DP, DM, DM_OUT, DP_OUT, USB1, and USB2, and ±5.5kV human body model on CC1 and CC2. The ESD structures can withstand high ESD both in normal operation and when the device is powered off. To further extend DP1 and DM1's ESD level for covering complicated application environments, additional resistors and capacitors can be added (see Figure 11). Similar R-C networks cannot be added on CC1 or CC2 because the CC line must support 200mA of current and 300kHz of signaling. Additional ESD diodes can be added on the CC pins. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 19 MPQ4485 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS When USB2 is in DCP mode, the R-C network can be added on DM2 and DP2 for ESD enhancement. When USB2 is in CDP mode, similar R-C networks cannot be added on DP2, DM2, DP2_OUT, or DM2-OUT pins due to the data transmission. 14. Place the VCC decoupling capacitor as close to VCC as possible. NOTE: 9) The recommended layout is based on setting USB1 to DCP mode and USB2 to CDP mode (see the Typical Application Circuits in Figure 13 to Figure 15). CC1 Type-C CC Logic Place C2B at right side CC2 Additional ESD D2 MPQ4485 USB2 Additional ESD D1 DM1 DCP USB1 R1 10Ω C1 100nF SW R2 DP1 10Ω C2 100nF GND Figure 11: I/O Pins for ESD Enhancing VIN Top Layer PCB Layout Guidelines (9) Efficient PCB layout is critical for stable operation and thermal dissipation. For best results, refer to Figure 12 and follow the guidelines below. 1. Use short, direct, and wide traces to connect OUT. GND 2. Add vias under the IC. 3. Route the OUT trace on both PCB layers. VIN Middle Layer 1 4. Place the buck output ceramic capacitor C2A on the left side and C2B on the right side. 5. Add a large copper plane for PGND. OUT VIN 6. Add multiple vias to improve thermal dissipation. GND 7. Connect AGND to PGND. 8. Place a large copper plane for SW, USB1, and USB2. Middle Layer 2 9. Route the USB1 and USB2 traces on both PCB layers. USB2 10. Add multiple vias. OUT 11. Place two ceramic input decoupling capacitors as close to IN and PGND as possible to improve EMI performance. SW GND 12. Place the symmetrical CIN capacitors on each side of the IC. 13. Place the BST capacitor close to BST and SW. MPQ4485 Rev.1.0 9/18/2017 VIN Bottom Layer Figure 12: Recommended Layout www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 20 MPQ4485 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS TYPICAL APPLICATION CIRCUITS C4 220nF L1 4.7µH 10 VIN 12V L2 4.7µH BST 4,14 C1 100µF C1C 4.7µF + C1A 22µF IN 12 MPQ4485 23 DM1 MODE R2 100kΩ 7 CC2 CC1 POL 1 C6 4.7µF 19 VCC DM2 BUS DM DP 18 DP2_OUT 6 R3 1kΩ 20 DP2 L3, Bead, 1kΩ@100MHz 17 PGND DM2_OUT AGND C7 1nF 16 USB2 C3 1µF CC1 22 24 DP1 11 DM USB1, 3A DP Type-C CC2 R4 150Ω R1 0Ω + C2 270µF ESR<50mΩ C2B 10µF C5 4.7µF USB1 EN VOUT 5.17V C2A 10µF 2 21 Optional input filter for improving conduction EMI 3,15,25 OUT C1D 10µF C1B 22µF 8,9,26 SW Type-A USB2, 2.5A To Host Controller 5,13 Figure 13: USB1 5V @ 3A Type-C Mode, USB2 Type-A Port with CDP Mode (10) (11) C4 220nF L1 4.7µH 10 VIN 12V L2 4.7µH 4,14 C1 100µF C1C 4.7µF + C1A 22µF BST IN 21 12 Optional input filter for improving conduction EMI C5 4.7µF MODE 22 24 C6 4.7µF 19 DM2 6 BUS DM DP 18 DP2_OUT Type-A L3, Bead, 1kΩ@100MHz 17 PGND DM2_OUT AGND R3 1kΩ 20 DP2 USB1, 2.5A Type-A To Host Controller 16 USB2 DP R2 80.6kΩ 1 VCC C3 1µF DM CDP Controller 23 CC2 CC1 POL + C2 270µF ESR<50mΩ C2B 10µF 2 USB1 DM1 DP1 7 C2A 10µF MPQ4485 EN R1 0Ω 11 VOUT 5.17V 3,15,25 OUT C1D 10µF C1B 22µF 8,9,26 SW USB2, 2.5A To Host Controller 5,13 Figure 14: Dual Type-A Port with CDP Mode (10) (11) C4 220nF L1 4.7µH 10 VIN 12V L2 4.7µH 4,14 C1 100µF C1C 4.7µF + C1A 22µF C1B 22µF Optional input filter for improving conduction EMI C3 1µF USB2, 5V/2.5A Power 8,9,26 SW IN C1D 10µF OUT 3,15,25 12 7 EN USB1 MODE CC1 CC2 DM1 DP1 VCC 16 DM2 DP2 USB2 C6 10µF 18 17 VOUT 5.17V C2A 10µF MPQ4485 21 R1 0Ω BST + C2 270µF ESR<50mΩ C2B 10µF 2 C5 4.7µF 1 24 23 22 C7 1nF R3 1kΩ 19 20 CC1 CC2 DM USB1, 3A Type-C DP TX RX L3, Bead, 1k@100MHz DP2_OUT USB2.0 Data Transmission To Host Controller DM2_OUT AGND 6 PGND 5,13 POL 11 R2 100K VCC USB3.0 Data Transmission To Host Controller USB3.0 Mux Figure 15: USB1 Type-C 5V @ 3A DFP Mode with USB3.0/USB2.0 Data Transmission, USB2 5V @ 2.5A Power Output (10) (11) NOTES: 10) See Figure 11 for I/O pins’ ESD protection enhancing details. 11) See Figure 8 for enhanced CDP mode data transmission set-up details. MPQ4485 Rev.1.0 9/18/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 21 MPQ4485 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS PACKAGE INFORMATION QFN-26 (5mmx5mm) PIN 1 ID MARKING PIN 1 ID INDEX AREA BOTTOM VIEW TOP VIEW SIDE VIEW NOTE: 1) LAND PATTERNS OF PIN 2~4 AND 14~16 HAVE THE SAME LENGTH AND WIDTH. 2) LAND PATTERNS OF PIN 5 AND PIN13 HAVE THE SAME LENGTH AND WIDTH. 0.25X45º 3) ALL DIMENSIONS ARE IN MILLIMETERS. 4) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX. 5) REFERENCEIS MO-220. 6) DRAWING IS NOT TO SCALE. RECOMMENDED LAND PATTERN NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ4485 rev 1.0 9/18/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 22