AN4057
Application note
SPC560Pxx, SPC56APxx power up HW guideline
INTRODUCTION
This application note is addressed to system hardware designers using
STMicroelectronics® SPC560Pxx/SPC56APxx microcontrollers It gives design references
to ensure a reliable microcontroller power up sequence also in the condition of an offset
voltage on the high voltage regulator supply pin VDD_HV_REG at power up.
The use of the SPC560Pxx/SPC56APxx internal voltage regulator requires a specific design
ST approved ballasts with the recommended supporting network described in the latest
revision of the device data sheet (for further details see Section Appendix A: Additional
information). It is important to respect the power on sequence conditions, ensuring a
monotonic supply ramp starting at ground level and respecting the min and max slew rate
on VDD_HV_REG.
This application note covers:
■
Recommended power on sequence conditions
■
Possible deviations injecting an offset voltage on VDD_HV_REG and its impact on
microcontroller power up
■
Optional proposals to eliminate the effect of offset voltage on VDD_HV_REG pin
September 2013
Doc ID 022842 Rev 2
1/13
www.st.com
Contents
AN4057
Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
2
Offset voltage on VDD_HV_REG and voltage regulator circuitry . . . . . . . 6
2.1
2.2
3
Power up sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Offset voltage on VDD_HV_REG: problem description . . . . . . . . . . . . . . . . . 6
2.1.1
Possible application paths to induce a VDD_HV_REG offset voltage . . . . . 6
2.1.2
Battery short to pin on connector of microcontroller board . . . . . . . . . . . 6
HW guidelines for high/low voltage supply of the internal regulator with offset
voltage on VDD_HV_REG 7
2.2.1
Resistors partition network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.2
VDD_HV_REG pin active path to ground . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SPC560Pxx/SPC56APxx devices affected . . . . . . . . . . . . . . . . . . . . . . 10
Appendix A Additional information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
A.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Resistor partition network values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SPC560Pxx/SPC56APxx device affected from VDD_HV_REG offset issue . . . . . . . . . . . . . 10
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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List of figures
AN4057
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
4/13
Offset voltage on VDD_HV_REG from SPC560Pxx/SPC56APxx input pin . . . . . . . . . . . . . . . 6
Battery short to pin on connector of microcontroller board . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Resistors partition network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Active path to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
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1
Overview
Overview
These SPC560Pxx /SPC56APxx microcontrollers are members of a new microcontroller
family built on the Power Architecture®. The device is supplied externally with a single
voltage supply, which can be either 5 V or 3.3 V depending on application requirements.
Internally the chip operates with 2 supply voltages, namely the main supply (5 V or 3.3 V)
and the core logic supply (1.2 V).
This document provides guideline for the recommended configuration of the high and low
voltage supply for the internal regulator in order to ensure the correct power up sequence of
the microcontroller.
The note describes application fault conditions that may offset VDD_HV_REG significantly and
mitigating circuitries to ensure reliable power up in case of these fault conditions. The
standard supply circuitry and sequence that use in the recommended conditions of initial
power up on VDD_HV_REG pin starting from ground level are described in the
SPC560Pxx/SPC56APxx data sheet (for further details see Section Appendix A: Additional
information).
Possible causes of fault conditions injecting an offset voltage on VDD_HV_REG pin are
described in the following list:
1.1
●
Supply microcontrollers I/O VIN while the microcontroller is switched off with shorted
supply for VDD_HV_REG and VDD_HV_IO pins
●
Offset voltage injected on VDD_HV_REG by external signal(s) shorted to battery.
Power up sequencing
Preventing an overstress event or a malfunction within and outside the device, the
SPC560Pxx/SPC56APxx implements a specific power up sequence, as described in the
data sheet, to ensure each module is started only when all conditions for switching it ON are
available.
In case of a fault condition on the application board, that sequence may not be respected,
causing the device not to exit the power up.
Two possible fault conditions are described in the following sections. However, if the fault
cause is removed, the device (while within the absolute maximum ratings) works again,
without getting damaged, powering up properly.
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Offset voltage on VDD_HV_REG and voltage regulator circuitry
AN4057
2
Offset voltage on VDD_HV_REG and voltage regulator
circuitry
2.1
Offset voltage on VDD_HV_REG: problem description
VDD_HV_REG offset on the devices SPC560Pxx/SPC56APxx, before the module is powered
up, may in some cases prevent the power up device correctly.
A VDD_HV_REG offset before a correct power up supply sequence can set the POR device
logic to an undefined state, preventing the internal logic to switch correctly and initialize the
internal VDD_LV circuitry. The internal regulator remains in power down. The consequence is
that the microcontroller is not able to exit reset.
2.1.1
Possible application paths to induce a VDD_HV_REG offset voltage
Figure 1 describes a GPIO configuration with the pin connected to an externally supplied
signal (Vbatt).
If Vbatt is powered while MCU VDD is not yet provided, GPIO protection circuitry (diode)
induces a voltage on VDD_HV_IO.
In the case VDD_HV_IO is directly connected to VDD_HV_REG, the induced voltage is
propagated to the internal regulator. The same consideration is done when using an
external diode, D1 in Figure 1, connecting GPIO VIN to VDD.
Figure 1.
Offset voltage on VDD_HV_REG from SPC560Pxx/SPC56APxx input pin
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2.1.2
Battery short to pin on connector of microcontroller board
Another possible cause of an initial offset on VDD_HV_REG is battery short to any pin of the
board connector.
6/13
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Offset voltage on VDD_HV_REG and voltage regulator circuitry
The short to battery can be propagated through various components (ASSP, ASICs, Com
Drivers) to the VDD_HV_REG as these components typically share the same supply.
Figure 2.
Battery short to pin on connector of microcontroller board
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2.2
HW guidelines for high/low voltage supply of the internal
regulator with offset voltage on VDD_HV_REG
In general an offset voltage must be avoided to pre-charge VDD_HV_REG through parasitic
paths. The MCU supply must power on from GND to power supply with a monotonic ramp
rate, minimum and maximum value as described in the data sheet (Tvdd). In case of a fault
condition, injecting an offset to VDD_HV_REG while the MCU is not supplied, the following
modifications on the module can prevent the device to remain in reset. The supply voltage
conditions are still respected.
Possible HW solutions on the supplying circuitry of the microcontroller to allow a correct
power up sequence, in case of an offset build up on VDD_HV_REG pin are:
2.2.1
●
Resistive network between VDD_HV_REG, VDD_LV_REG and GND
●
Active discharge on VDD or VDD_HV_REG at power up
●
Other application means to prevent the presence of an offset on VDD_HV_REG during
power up
Resistors partition network
This solution with two partitioning resistors, shown in Figure 3, enables VDD_LV_REG to be
pre- conditioned and the internal VDD_LV_REG to be forced into a defined state as soon as
the ballast regulator turns-on.
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Offset voltage on VDD_HV_REG and voltage regulator circuitry
\
Table 1.
AN4057
Resistor partition network values
Symbol
VDD_HV_REG@ 5 V
Parameter
Value
Unit
R1
Resistor between VDD_HV_REG/ballast
emitter and ballast collector
910
Ω
R2
Resistor between ballast emitter and
ground
300
Ω
R1
Resistor between VDD_HV_REG/ballast
emitter and ballast collector
510
Ω
R2
Resistor between ballast emitter and
ground
300
Ω
VDD_HV_REG@ 3.3 V
Static consumption has to be considered into the board voltage regulator design.
Figure 3.
Resistors partition network
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2.2.2
VDD_HV_REG pin active path to ground
Another solution is to add a controlled active path to ground on VDD_HV_REG/VDD_HV_IO that
forces these pins to ground when the microcontroller is switched off or discharges the
VDD_HV_REG at start up.
Figure 4 describes a generic configuration that uses the enable signal of an external
regulator, VIGN, to drive the gate of NFET to force VDD_HV_REG/VDD_HV_IO pin to ground.
When the external regulator is off there is a discharge path of the current from the
VDD_HV_REG/VDD_HV_IO.
It has to be granted that the VDD rises with the required monotonic slew rate before any fault
condition can build up an offset on VDD_HV_REG, prior to the release of the active discharge
circuit.
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Offset voltage on VDD_HV_REG and voltage regulator circuitry
Figure 4.
Active path to ground
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SPC560Pxx/SPC56APxx devices affected
3
AN4057
SPC560Pxx/SPC56APxx devices affected
Table 2 lists the STMicroelectronics SPC560Pxx/SPC56APxx devices and revisions that are
affected by the previously described phenomenon.
Table 2.
SPC560Pxx/SPC56APxx device affected from VDD_HV_REG offset issue
Part number
10/13
Package device
marking mask identifier
and silicon version
MIDR1 register
SPC560P34xx/P40xx
AB - cut 1.1 (and older)
MAJOR_MASK[3:0]: 4'b0000
MINOR_MASK[3:0]: 4'b0001
SPC560P50xx/P44xx
BD - cut 3.4 (and older)
MAJOR_MASK[3:0]: 4’b0001
MINOR_MASK[3:0]: 4’b0101
SPC560P60xx/P54xx
SPC56AP60xx/AP54xx
AA - cut 1.0
MAJOR_MASK[3:0]: 4’b0000
MINOR_MASK[3:0]: 4’b0000
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Additional information
Appendix A
A.1
Additional information
Reference document
●
32-bit Power Architecture® based MCU with 1088 KB Flash memory and 80 KB RAM
for automotive chassis and safety applications (SPC560P54x, SPC560P60L3,
SPC56AP54L3, SPC56AP60x, Doc ID 18340)
●
32-bit Power Architecture® based MCU with 320 KB Flash memory and 20 KB RAM for
automotive chassis and safety applications (SPC560P34L1, SPC560P34L3,
SPC560P40L1, SPC560P40L3, Doc ID 16100)
●
32-bit Power Architecture® based MCU with 576 KB Flash memory and 40 KB SRAM
for automotive chassis and safety applications (SPC560P44L3, SPC560P44L5,
SPC560P50L3, SPC560P50L5, Doc ID 14723)
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Revision history
AN4057
Revision history
Table 3.
12/13
Document revision history
Date
Revision
Changes
01-Mar-2012
1
Initial release.
13-Sep-2013
2
Updated disclaimer.
Doc ID 022842 Rev 2
AN4057
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