Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 ADS8881x 18-Bit, 1-MSPS, Serial Interface, microPower, Miniature, True-Differential Input, SAR Analog-to-Digital Converter 1 Features 2 Applications • • • • • • • 1 • • • • • • • • Sample Rate: 1 MHz No Latency Output Unipolar, True-Differential Input Range: –VREF to +VREF Wide Common-Mode Voltage Range: 0 V to VREF with 90-dB CMRR (min) SPI™-Compatible Serial Interface with Daisy-Chain Option Excellent AC and DC Performance: – ADS8881C: INL: ±1 LSB (typ), ±2.0 LSB (max) DNL: ±1.0 LSB (max), 18-Bit NMC SNR: 100 dB, THD: –115 dB – ADS8881I: INL: ±1.5 LSB (typ), ±3.0 LSB (max) DNL: +1.5 and –1 LSB (max), 18-Bit NMC SNR: 100 dB, THD: –115 dB Wide Operating Range: – AVDD: 2.7 V to 3.6 V – DVDD: 2.7 V to 3.6 V (Independent of AVDD) – REF: 2.5 V to 5 V (Independent of AVDD) – Operating Temperature: ADS8881C : 0°C to +70°C ADS8881I : –40°C to +85°C Low-Power Dissipation: – 5.5 mW at 1 MSPS – 0.55 mW at 100 kSPS – 55 µW at 10 kSPS Power-Down Current (AVDD): 50 nA Full-Scale Step Settling to 18 Bits: 290 ns Packages: MSOP-10 and VSON-10 Automatic Test Equipment (ATE) Instrumentation and Process Controls Precision Medical Equipment Low-Power, Battery-Operated Instruments 3 Description The ADS8881 is an 18-bit, 1-MSPS, true-differential input, analog-to-digital converter (ADC). The device operates with a 2.5-V to 5-V external reference, offering a wide selection of signal ranges without additional input signal scaling. The reference voltage setting is independent of, and can exceed, the analog supply voltage (AVDD). The device that also cascading indicator bit easy. offers an SPI-compatible serial interface supports daisy-chain operation for multiple devices. An optional busymakes synchronizing with the digital host The device supports unipolar, true-differential analog input signals with a differential input swing of –VREF to VREF. This true-differential analog input structure allows for a common-mode voltage of any value in the range of 0 V to VREF (when both inputs are within the operating input range of –0.1 V to VREF + 0.1 V). Device operation is optimized for very low-power operation. Power consumption directly scales with speed. This feature makes the ADS8881 excellent for lower-speed applications. Device Information(1) PART NUMBER PACKAGE ADS8881x BODY SIZE (NOM) VSSOP (10) 3.00 mm × 3.00 mm VSON (10) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. True-Differential Input Range Traditional Input Range ADS8881 Input Range VDIFF +VREF 2.5 V to 5 V 2.7 V to 3.6 V REF AVDD 2.7 V to 3.6 V VREF VCM 0V 0 V - VREF DVDD AINP VCM DIN ADS8881 VREF SCLK DOUT 0V AINM CONVST 0 V - VREF VREF/2 GND -VREF 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Recommended Devices and Designs .................. Pin Configurations and Functions ....................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 1 1 1 2 4 5 6 Absolute Maximum Ratings ...................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 6 Electrical Characteristics........................................... 7 Timing Requirements: 3-Wire Operation .................. 9 Timing Requirements: 4-Wire Operation ................ 10 Timing Requirements: Daisy-Chain ........................ 11 Typical Characteristics ............................................ 12 8 Parametric Measurement Information ............... 19 9 Detailed Description ............................................ 20 8.1 Equivalent Circuits .................................................. 19 9.1 Overview ................................................................. 20 9.2 Functional Block Diagram ....................................... 20 9.3 Feature Description................................................. 20 9.4 Device Functional Modes........................................ 23 10 Application and Implementation........................ 32 10.1 Application Information.......................................... 32 10.2 Typical Applications .............................................. 35 11 Power-Supply Recommendations ..................... 44 11.1 Power-Supply Decoupling..................................... 44 11.2 Power Saving ........................................................ 44 12 Layout................................................................... 46 12.1 Layout Guidelines ................................................. 46 12.2 Layout Example .................................................... 46 13 Device and Documentation Support ................. 47 13.1 13.2 13.3 13.4 13.5 13.6 Documentation Support ....................................... Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 47 47 47 47 48 48 14 Mechanical, Packaging, and Orderable Information ........................................................... 48 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (July 2014) to Revision D Page • Added Recommended Devices and Designs section ........................................................................................................... 4 • Changed title of Device Comparison table, moved to Recommended Devices and Designs section .................................. 4 • Changed ESD Ratings table to current standards, added HBM and CDM data ................................................................... 6 • Added timing specifications for different operating temperature ranges for the tconv, td-CK-DO, and tquiet parameters in the Timing Requirements: 3-Wire Operation table ................................................................................................................ 9 • Added timing specifications for different operating temperature ranges for the tconv parameter in Timing Requirements: 4-Wire Operation table ................................................................................................................................. 10 • Added timing specifications for different operating temperature ranges for the tconv parameter in Timing Requirements: Daisy-Chain table ........................................................................................................................................ 11 • Added Community Resources section ................................................................................................................................ 47 2 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 Changes from Revision B (December 2014) to Revision C Page • Changed format to meet latest data sheet standards; added new sections, moved existing sections ................................. 1 • Changed ADS8881 to ADS8881C, added ADS8881I ........................................................................................................... 1 • Separated ADS8881C and ADS8881I specifications in Excellent AC and DC Performance Features bullet ....................... 1 • Changed Device Information table to current standards ........................................................................................................ 1 • Updated Family Information Table, changed footnotes.......................................................................................................... 4 • Added Recommended Operating Conditions table ................................................................................................................ 6 • Changed LSB footnote to include how to convert LSB to ppm ............................................................................................. 7 • Changed fSCLK parameter maximum specification from 66.6 MHz to 70 MHz in Timing Requirements: 3-Wire Operation table. ...................................................................................................................................................................... 9 • Changed tSCLK parameter minimum specification from 15 ns to 14.3 ns in Timing Requirements: 3-Wire Operation table. . 9 • Added more information about validity of data on SCLK edges in all interface modes ....................................................... 24 • Changed diagrams and text for better explanation of the daisy-chain feature in the Daisy-Chain Mode section ............... 29 • Changed Equation 2 and Equation 3 .................................................................................................................................. 33 • Added Layout Guidelines section ......................................................................................................................................... 46 Changes from Revision A (July 2013) to Revision B Page • Changed Wide Common-Mode Voltage Range Features bullet ............................................................................................ 1 • Added note 2 to Family Information table............................................................................................................................... 4 • Changed External Reference Input, Reference input current parameter typical specification from 350 to 300 .................... 7 • Added External Reference Input, Reference leakage current parameter to Electrical Characteristics.................................. 7 • Changed Power-Supply Requirements, Power-supply voltage parameter digital interface supply range as a function of SCLK in Electrical Characteristics ...................................................................................................................................... 8 • Added Digital Inputs, Digital input leakage current parameter to Electrical Characteristics .................................................. 8 • Added true-differential input feature details to Analog Input section.................................................................................... 21 • Deleted shading from Figure 64 ........................................................................................................................................... 34 • Deleted shading from Figure 65 ........................................................................................................................................... 35 • Deleted shading from Figure 67 ........................................................................................................................................... 37 • Deleted shading from Figure 69 ........................................................................................................................................... 39 • Deleted shading from Figure 70 ........................................................................................................................................... 39 • Deleted shading from Figure 72 ........................................................................................................................................... 42 • Added power scaling with throughput feature details to Power Saving section................................................................... 44 Changes from Original (May 2013) to Revision A • Page Changed document status to Production Data; pre-RTM changes made throughout document .......................................... 1 Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 3 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com 5 Recommended Devices and Designs Table 1. Device Comparison (1) (2) THROUGHPUT 18-BIT, TRUE-DIFFERENTIAL 16-BIT, SINGLE-ENDED 16-BIT, TRUE-DIFFERENTIAL 100 kSPS ADS8887 ADS8866 ADS8867 250 kSPS — ADS8339 (1) — 400 kSPS ADS8885 ADS8864 ADS8865 500 kSPS — ADS8319 (1) ADS8318 (1) (2) 680 kSPS ADS8883 ADS8862 ADS8863 1 MSPS ADS8881 ADS8860 ADS8861 Pin-to-pin compatible device with AVDD = 5 V. Supports standard for fully-differential input. Table 2. Companion Devices DEVICE DESCRIPTION PRECISION AMPLIFIERS Low-Power Amplifiers OPA313 1-MHz, micropower, low-noise, rail-to-rail I/O 1.8-V operational amplifier OPA333 1.8-V, 17-µA, micropower, precision, zero-drift CMOS operational amplifier Low-Distortion Amplifiers OPA625 High-bandwidth, high-precision, low-noise, and low-distortion amplifier SAR ADC driver with power scaling OPA350 High-speed, single-supply, rail-to-rail operational amplifiers microamplifier™ series OPA320 Precision, 20-MHz, 0.9-pA Ib, RRIO, CMOS operational amplifier THS4521 Very low-power, rail-to-rail output, fully-differential amplifier High-Speed Amplifiers THS4281 Very low-power, high-speed, rail-to-rail input/output, voltage-feedback operational amplifier THS4031 100-MHz low noise voltage-feedback amplifier PGAs and Instrumentation Amplifiers INA333 Low-power, precision instrumentation amplifier INA826 Precision, 200-μA supply current, 36-V supply instrumentation amplifier PRECISION REFERENCES REF50xx Low-noise, very low-drift, precision voltage reference REF33xx 30-ppm/°C drift, 3.9-µA, SOT23-3, SC70-3 voltage reference REF20xx Low-drift, low-power, dual-output VREF and VREF / 2 voltage reference Table 3. Recommended TI Designs DESIGN 4 DESCRIPTION TIPD112 Data acquisition for mux and step inputs, 18-bit, 1-µs, full-scale response reference design TIPD113 Data acquisition for 10-kHz ac, 35-mW, 18-Bit, 1-MSPS reference design TIPD114 Data acquisition at 1-kHz ac, 1-mW, 18-bit, 1-MSPS reference design TIPD115 Data acquisition optimized for lowest distortion, lowest noise, 18-bit, 1-MSPS reference design TIPD116 Data acquisition block for ECG systems, discrete LEAD I ECG implementation reference design Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 Table 4. Related Documentation PRECISION HUB BLOGS Using SAR ADC TINA models: Static behavior, power scaling Using SAR ADC TINA models: Much ado about settling SAR ADC response times: Respond quickly, control quickly Input considerations for SAR ADCs Table 5. Tools & Support TINA MODEL IBIS MODEL EVALUATION MODEL ADS8881 TINA-TI Reference Design ADS8881 IBIS Model ADS8881EVM-PDK 6 Pin Configurations and Functions DGS Package VSSOP-10 Top View, Not to Scale DRC Package VSON-10 Top View, Not to Scale REF 1 10 DVDD AVDD 2 9 DIN SCLK AINP 3 8 SCLK 7 DOUT AINN 4 7 DOUT 6 CONVST GND 5 6 CONVST REF 1 10 DVDD AVDD 2 9 DIN AINP 3 8 AINN 4 GND 5 Thermal PAD Pin Functions PIN NAME NO. I/O DESCRIPTION AINN 4 Analog input Inverting analog signal input AINP 3 Analog input Noninverting analog signal input AVDD 2 Analog CONVST 6 Digital input Convert input. This pin also functions as the CS input in 3-wire interface mode; see the Description and Timing Requirements sections for more details. DIN 9 Digital input Serial data input. The DIN level at the start of a conversion selects the mode of operation (such as CS or daisy-chain mode). This pin also serves as the CS input in 4-wire interface mode; see the Description and Timing Requirements sections for more details. Analog power supply. This pin must be decoupled to GND with a 1-μF capacitor. DOUT 7 Digital output Serial data output DVDD 10 Power supply Digital interface power supply. This pin must be decoupled to GND with a 1-μF capacitor. GND 5 Analog, digital Device ground. Note that this pin is a common ground pin for both the analog power supply (AVDD) and digital I/O supply (DVDD). The reference return line is also internally connected to this pin. REF 1 Analog SCLK 8 Digital input Clock input for serial interface. Data output (on DOUT) are synchronized with this clock. Thermal pad — Thermal pad Exposed thermal pad (only for the DRC package option). Texas Instruments recommends connecting the thermal pad to the printed circuit board (PCB) ground. Positive reference input. This pin must be decoupled with a 10-μF or larger capacitor. Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 5 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT AINP to GND or AINN to GND –0.3 REF + 0.3 V AVDD to GND or DVDD to GND –0.3 4 V REF to GND –0.3 5.7 V Digital input voltage to GND –0.3 DVDD + 0.3 V V Digital output to GND Operating temperature, TA –0.3 DVDD + 0.3 ADS8881C 0 70 ADS8881I –40 85 –65 150 Storage temperature, Tstg (1) °C °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) V ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT AVDD Analog power supply 3 V DVDD Digital power supply 3 V VREF Reference voltage 5 V 7.4 Thermal Information ADS8881 THERMAL METRIC DGS (VSSOP) DRC (VSON) UNIT 10 PINS 10 PINS RθJA Junction-to-ambient thermal resistance 151.9 111.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 45.4 46.4 °C/W RθJB Junction-to-board thermal resistance 72.2 45.9 °C/W ψJT Junction-to-top characterization parameter 3.3 3.5 °C/W ψJB Junction-to-board characterization parameter 70.9 45.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W 6 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 7.5 Electrical Characteristics All minimum and maximum specifications are at AVDD = 3 V, DVDD = 3 V, VREF = 5 V, VCM = VREF / 2 V, and fSAMPLE = 1 MSPS, over the operating free-air temperature range, unless otherwise noted. Typical specifications are at TA = 25°C, AVDD = 3 V, and DVDD = 3 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT –VREF VREF V AINP –0.1 VREF + 0.1 AINN –0.1 VREF + 0.1 ANALOG INPUT Full-scale input span (1) (2) Operating input range (1) (2) VCM Input common-mode range CI Input capacitance AINP – AINN 0 VREF / 2 AINP and AINN terminal to GND V VREF V 59 pF EXTERNAL REFERENCE INPUT VREF Input range Reference input current ADS8881C ADS8881I 3 5 2.5 5 During conversion, 1-MHz sample rate, midcode Reference leakage current CREF Decoupling capacitor at the REF input Input leakage current V 300 μA 250 nA 22 µF 5 nA 18 Bits 10 During acquisition for dc input SYSTEM PERFORMANCE Resolution NMC No missing codes DNL Differential linearity INL Integral linearity (4) EO Offset error (5) 18 –0.99 ±0.6 1 ADS8881I –0.99 ±0.7 1.5 ADS8881C –2 ±1.2 2 ADS8881I –3 ±1.5 3 –4 ±1 4 Offset error drift with temperature EG –0.01 Gain error drift with temperature Common-mode rejection ratio PSRR Power-supply rejection ratio LSB (3) LSB (3) mV ±1.5 Gain error CMRR Bits ADS8881C ±0.005 µV/°C 0.01 ±0.15 90 ppm/°C 100 At mid-code Transition noise %FSR dB 80 dB 0.7 LSB SAMPLING DYNAMICS tconv Conversion time 500 tACQ Acquisition time 290 710 ns Maximum throughput rate with or without latency (1) (2) (3) (4) (5) ns 1000 kHz Aperture delay 4 ns Aperture jitter, RMS 5 ps Step response Settling to 18-bit accuracy 290 ns Overvoltage recovery Settling to 18-bit accuracy 290 ns Ideal input span, does not include gain or offset error. Specified for VCM = VREF / 2; see the Analog Input section for the effect of VCM on the full-scale input range. LSB = least significant bit. 1 LSB at 18-bits is approximately 3.8 ppm. This parameter is the endpoint INL, not best-fit. Measured relative to actual measured reference. Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 7 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com Electrical Characteristics (continued) All minimum and maximum specifications are at AVDD = 3 V, DVDD = 3 V, VREF = 5 V, VCM = VREF / 2 V, and fSAMPLE = 1 MSPS, over the operating free-air temperature range, unless otherwise noted. Typical specifications are at TA = 25°C, AVDD = 3 V, and DVDD = 3 V. PARAMETER TEST CONDITIONS MIN TYP 98 99.9 MAX UNIT DYNAMIC CHARACTERISTICS At 1 kHz, VREF = 5 V SINAD Signal-to-noise + distortion (6) At 10 kHz, VREF = 5 V 98.7 At 100 kHz, VREF = 5 V 93.3 At 1 kHz, VREF = 5 V SNR THD Signal-to-noise ratio (6) Total harmonic distortion (6) (7) SFDR Spurious-free dynamic range (6) BW–3dB –3-dB small-signal bandwidth 98.5 dB 100 At 10 kHz, VREF = 5 V 99.5 At 100 kHz, VREF = 5 V 93.5 At 1 kHz, VREF = 5 V –115 At 10 kHz, VREF = 5 V –112 At 100 kHz, VREF = 5 V –102 At 1 kHz, VREF = 5 V 115 At 10 kHz, VREF = 5 V 112 At 100 kHz, VREF = 5 V 102 dB dB dB 30 MHz POWER-SUPPLY REQUIREMENTS AVDD Power-supply voltage Supply current PVA DVDD AVDD Power dissipation Analog supply 2.7 3 3.6 Digital supply range for SCLK > 40 MHz 2.7 3 3.6 Digital supply range for SCLK < 40 MHz 1.65 1.8 3.6 1-MHz sample rate, AVDD = 3 V 1.8 2.4 1-MHz sample rate, AVDD = 3 V 5.5 7.2 100-kHz sample rate, AVDD = 3 V 0.55 10-kHz sample rate, AVDD = 3 V IAPD Device power-down current (8) V mA mW 55 μW 50 nA DIGITAL INPUTS: LOGIC FAMILY (CMOS) VIH High-level input voltage VIL Low-level input voltage ILK Digital input leakage current 1.65 V < DVDD < 2.3 V 0.8 × DVDD DVDD + 0.3 2.3 V < DVDD < 3.6 V 0.7 × DVDD DVDD + 0.3 1.65 V < DVDD < 2.3 V –0.3 0.2 × DVDD 2.3 V < DVDD < 3.6 V –0.3 0.3 × DVDD ±10 V V ±100 nA 0.8 × DVDD DVDD V V DIGITAL OUTPUTS: LOGIC FAMILY (CMOS) VOH High-level output voltage IO = 500-μA source, CLOAD = 20 pF VOL Low-level output voltage IO = 500-μA sink, CLOAD = 20 pF 0 0.2 × DVDD ADS8881C 0 70 –40 85 TEMPERATURE RANGE TA (6) (7) (8) 8 Operating free-air temperature ADS8881I °C All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale, unless otherwise specified. Calculated on the first nine harmonics of the input frequency. The device automatically enters a power-down state at the end of every conversion, and remains in power-down during the acquisition phase. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 7.6 Timing Requirements: 3-Wire Operation All specifications are at AVDD = 3 V, DVDD = 3 V, and over the operating free-air temperature range, unless otherwise noted. MIN tACQ Acquisition time TYP MAX UNIT 290 ns TA in the range –40°C to 85°C 500 710 TA in the range 0°C to 70°C 500 700 tconv Conversion time tconv Conversion time 1/fsample Time between conversions twh-CNV Pulse duration: CONVST high fSCLK SCLK frequency tSCLK SCLK period 14.3 tclkl SCLK low time 0.45 0.55 tSCLK tclkh SCLK high time 0.45 0.55 tSCLK th-CK-DO SCLK falling edge to current data invalid td-CK-DO ns 500 ns 1000 ns 10 ns 70 MHz ns 3 SCLK falling edge to next data valid delay ns TA in the range –40°C to 85°C 13.4 TA in the range 0°C to 70°C 11.7 TA in the range 25°C to 50°C 10.7 ns td-CNV-DO Enable time: CONVST low to MSB valid 12.3 ns td-CNV-DOhz Disable time: CONVST high or last SCLK falling edge to DOUT 3-state (CS mode) 13.2 ns tquiet Quiet time TA in the range –40°C to 85°C 20 TA in the range 0°C to 70°C 13 ns 1/fsample DIN = HIGH tconv-max tACQ tclkh th-CK-DO CONVST tclkl tquiet SCLK 1 2 td-CNV-DO DOUT 3 16 17 18 D1 D0 tSCLK D17 D16 D15 D2 twh-CNV-min td-CK-DO td-CK-DOhz Figure 1. 3-Wire Operation: CONVST Functions as Chip Select NOTE: Figure 1 shows the timing diagram for the 3-Wire CS Mode Without a Busy Indicator interface option. However, the timing parameters specified in Timing Requirements: 3-Wire Operation are also applicable for the 3-Wire CS Mode With a Busy Indicator interface option, unless otherwise specified; see the Device Functional Modes section for specific details for each interface option. Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 9 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com 7.7 Timing Requirements: 4-Wire Operation All specifications are at AVDD = 3 V, DVDD = 3 V, and over the operating free-air temperature range, unless otherwise noted. MIN tACQ Acquisition time TYP MAX UNIT 290 ns TA in the range –40°C to 85°C 500 710 TA in the range 0°C to 70°C 500 700 tconv Conversion time ns tconv Conversion time 1/fsample Time between conversions twh-DI Pulse duration: DIN high twl-CNV Pulse width: CONVST low td-DI-DO Delay time: DIN low to MSB valid 12.3 ns td-DI-DOhz Delay time: DIN high or last SCLK falling edge to DOUT 3-state 13.2 ns tsu-DI-CNV Setup time: DIN high to CONVST rising edge th-DI-CNV Hold time: DIN high from CONVST rising edge (see Figure 63) 500 ns 1000 ns 10 ns 20 ns 7.5 ns 0 ns 1/fsample tACQ tconv-max CONVST tsu-DI-CNV twl-CNV DIN SCLK 1 DOUT D17 2 3 D16 D15 16 17 18 D1 D0 twh-DI-min D2 td-DI-DO td-DI-DOhz Figure 2. 4-Wire Operation: DIN Functions as Chip Select NOTE: Figure 2 shows the timing diagram for the 4-Wire CS Mode Without a Busy Indicator interface option. However, the timing parameters specified in Timing Requirements: 4-Wire Operation are also applicable for the 4-Wire CS Mode With a Busy Indicator interface option, unless otherwise specified; see the Device Functional Modes section for specific details for each interface option. 10 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 7.8 Timing Requirements: Daisy-Chain All specifications are at AVDD = 3 V, DVDD = 3 V, and over the operating free-air temperature range, unless otherwise noted. MIN tACQ Acquisition time TYP MAX UNIT 290 ns TA in the range -40°C to 85°C 500 710 TA in the range 0°C to 70°C 500 700 tconv Conversion time tconv Conversion time 1/fsample Time between conversions tsu-CK-CNV Setup time: SCLK valid to CONVST rising edge th-CK-CNV Hold time: SCLK valid from CONVST rising edge tsu-DI-CNV Setup time: DIN low to CONVST rising edge (see Figure 2) th-DI-CNV Hold time: DIN low from CONVST rising edge (see Figure 63) tsu-DI-CK Setup time: DIN valid to SCLK falling edge ns 500 ns 1000 ns 5 ns 5 ns 7.5 ns 0 ns 1.5 ns 1/fsample tconv- tACQ max CONVST th-CK-CNV SCLK DIN 1 = LOW 1 2 17 18 19 20 35 36 D17 D16 D1 D0 tsu-DI-CK tsu-CK-CNV DOUT 1, DIN 2 D17 D16 D1 D0 DOUT 2 D17 D16 D1 D0 Device 2 Data Device 1 Data Figure 3. Daisy-Chain Operation: Two Devices NOTE: Figure 3 shows the timing diagram for the Daisy-Chain Mode Without a Busy Indicator interface option. However, the timing parameters specified in Timing Requirements: Daisy-Chain are also applicable for the DaisyChain Mode With a Busy Indicator interface option, unless otherwise specified; see the Device Functional Modes section for specific details for each interface option. Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 11 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com 7.9 Typical Characteristics At TA = 25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 1 MSPS, unless otherwise noted. 1 Typical Differential Nonlinearity (LSB) Typical Integral Nonlinearity (LSB) 3 AVDD = 3 V REF = 2.5 V TA = 25C 2 1 0 ±1 ±2 ±3 ±131072 0.5 0.25 0 -0.25 -0.5 -0.75 -1 ±131072 131071 ADC Output Code 1 AVDD = 3 V REF = 5 V TA = 25C 2 Typical Differential Nonlinearity (LSB) Typical Integral Nonlinearity (LSB) C002 Figure 5. Typical DNL (VREF = 2.5 V) 3 1 0 ±1 ±2 ±3 ±131072 131071 ADC Output Code AVDD = 3 V REF = 5 V TA = 25C 0.75 0.5 0.25 0 -0.25 -0.5 -0.75 -1 ±131072 131071 ADC Output Code C003 Figure 6. Typical INL (VREF = 5 V) C004 Figure 7. Typical DNL (VREF = 5 V) 3 2 AVDD = 3 V REF = 5 V 2 Differential Nonlinearity (LSB) Integral Nonlinearity (LSB) 131071 ADC Output Code C001 Figure 4. Typical INL (VREF = 2.5 V) 1 0 -1 -2 -3 AVDD = 3 V REF = 5 V 1.5 1 0.5 0 -0.5 -1 -40 -15 10 35 Free-Air Temperature (oC) 60 Submit Documentation Feedback 85 -40 -15 C00 Figure 8. INL vs Temperature 12 AVDD = 3 V REF = 2.5 V TA = 25C 0.75 10 35 60 Free-Air Temperature (oC) 85 C00 Figure 9. DNL vs Temperature Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 Typical Characteristics (continued) At TA = 25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 1 MSPS, unless otherwise noted. 2 AVDD = 3 V TA = 25oC 2 Differential Nonlinearity (LSB) Integral Nonlinearity (LSB) 3 1 0 -1 -2 AVDD = 3 V TA = 25oC 1.5 1 0.5 0 -0.5 -1 -3 2.5 3 3.5 4 Reference Voltage (V) 4.5 2.5 5 3 C00 Figure 10. INL vs Reference Voltage 4.5 5 C00 Figure 11. DNL vs Reference Voltage 40 60 AVDD = 3 V REF = 2.5 V TA = 25oC AVDD = 3 V REF = 5 V TA = 25oC 50 Hits per Code (%) 30 Hits per Code (%) 3.5 4 Reference Voltage (V) 20 40 30 20 10 10 0 0 10 12 14 16 ADC Output Code 18 20 4 Figure 12. DC Input Histogram (VREF = 2.5 V) 8 ADC Output Code 10 C01 Figure 13. DC Input Histogram (VREF = 5 V) 0 0 AVDD = 3 V REF = 2.5 V TA = 25C fIN = 1 kHz SNR = 95.4 dB THD = ±119 dB ±40 ±60 ±80 ±40 ±60 ±100 ±120 ±80 ±100 ±120 ±140 ±140 ±160 ±160 ±180 ±180 ±200 0 100 200 300 Input Frequency (kHz) 400 AVDD = 3 V REF = 5 V TA = 25C fIN = 1 kHz SNR = 100 dB THD = ±115 dB ±20 Power (dB) ±20 Power (dB) 6 C00 500 ±200 0 100 C011 Figure 14. Typical FFT (VREF = 2.5 V) 200 300 Input Frequency (kHz) 400 500 C012 Figure 15. Typical FFT (VREF = 5 V) Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 13 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com Typical Characteristics (continued) At TA = 25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 1 MSPS, unless otherwise noted. 102 Signal-to-Noise and Distortion (dBFS) Signal-to-Noise Ratio (dBFS) 102 101 100 99 98 97 96 95 fIN = 1 kHz 94 101 100 99 98 97 96 95 fIN = 1 kHz 94 2.5 3 3.5 4 Reference Voltage (V) 4.5 5 2.5 Figure 16. SNR vs Reference Voltage Total Harmonic Distortion (dBFS) Effective Number of Bits 4.5 5 C01 -109 fIN = 1 kHz 17.5 17 16.5 16 15.5 15 14.5 fIN = 1 kHz -111 -113 -115 -117 -119 -121 -123 -125 14 2.5 3 3.5 4 Reference Voltage (V) 4.5 2.5 5 3 C01 Figure 18. ENOB vs Reference Voltage 3.5 4 Reference Voltage (V) 4.5 5 C01 Figure 19. THD vs Reference Voltage 102 126 fIN = 1 kHz 124 Signal-to-Noise Ratio (dBFS) Spurious-Free Dynamic Range (dBFS) 3.5 4 Reference Voltage (V) Figure 17. SINAD vs Reference Voltage 18 122 120 118 116 114 112 fIN = 1 kHz 101 100 99 98 97 96 95 94 110 2.5 3 3.5 4 Reference Voltage (V) 4.5 Figure 20. SFDR vs Reference Voltage 14 3 C01 Submit Documentation Feedback 5 -40 -15 C01 10 35 Free-Air Temperature (oC) 60 85 C01 Figure 21. SNR vs Temperature Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 Typical Characteristics (continued) At TA = 25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 1 MSPS, unless otherwise noted. 18 fIN = 1 kHz 101 fIN = 1 kHz 17.5 Effective Number of Bits Signal-to-Noise and Distortion (dBFS) 102 100 99 98 97 96 95 17 16.5 16 15.5 15 14.5 94 14 -40 -15 10 35 Free-Air Temperature (oC) 60 85 -40 Figure 22. SINAD vs Temperature Spurious-Free Dynamic Range (dBFS) Total Harmonic Distortion (dBFS) fIN = 1 kHz -113 -115 -117 -119 -121 -123 -125 60 85 C02 126 fIN = 1 kHz 124 122 120 118 116 114 112 110 -40 -15 10 35 Free-Air Temperature (oC) 60 85 -40 -15 C02 Figure 24. THD vs Temperature 10 35 Free-Air Temperature (oC) 60 85 C02 Figure 25. SFDR vs Temperature 101 Signal-to-Noise and Distortion (dBFS) 106 Signal-toNoise Ratio (dBFS) 10 35 Free-Air Temperature (oC) Figure 23. ENOB vs Temperature -109 -111 -15 C01 104 102 100 98 96 94 92 100 99 98 97 96 95 94 93 90 0 20 40 60 Input Frequency (kHz) 80 100 0 20 C02 Figure 26. SNR vs Input Frequency 40 60 Input Frequency (kHz) 80 100 C02 Figure 27. SINAD vs Input Frequency Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 15 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com Typical Characteristics (continued) At TA = 25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 1 MSPS, unless otherwise noted. 18 -100 Total Harmonic Distortion (dBFS) Effective Number of Bits 17.5 17 16.5 16 15.5 15 14.5 14 0 20 40 60 Input Frequency (kHz) 80 -103 -106 -109 -112 -115 -118 -121 -124 100 0 124 121 2.3 118 115 112 109 106 80 100 C02 2.2 2.1 2 1.9 1.8 1.7 103 1.6 100 0 20 40 60 Input Frequency (kHz) 80 -40 100 -15 C02 Figure 30. SFDR vs Input Frequency 10 35 Free-Air Temperature (oC) 60 85 C02 Figure 31. Supply Current vs Temperature 6 2 5.9 1.8 Analog Supply Current (mA) Power Consumption (mW) 40 60 Input Frequency (kHz) Figure 29. THD vs Input Frequency 2.4 Analog Supply Current (mA) Spurious-Free Dynamic Range (dBFS) Figure 28. ENOB vs Input Frequency 5.8 5.7 5.6 5.5 5.4 5.3 5.2 5.1 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 5 -40 -15 10 35 Free-Air Temperature (oC) 60 Figure 32. Power Consumption vs Temperature 16 20 C02 Submit Documentation Feedback 85 0 0 200 C02 400 600 Throughput (kSPS) 800 1000 C03 Figure 33. Supply Current vs Throughput Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 Typical Characteristics (continued) At TA = 25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 1 MSPS, unless otherwise noted. 200 175 5 Power-Down Current (mA) Power Consumption (mW) 6 4 3 2 1 150 125 100 75 50 25 0 0 0 200 400 600 Throughput (kSPS) 800 -40 1000 -15 C03 Figure 34. Power Consumption vs Throughput 10 35 Free-Air Temperature (oC) 60 85 C03 Figure 35. Power-Down Current vs Temperature 4 0.01 3 0.006 Gain Error (%FS) Offset (mV) 2 1 0 -1 -2 0.002 -0.002 -0.006 -3 -4 -0.01 -40 -15 10 35 Free-Air Temperature (oC) 60 85 -40 10 35 Free-Air Temperature (oC) 60 85 C03 Figure 37. Gain Error vs Temperature 18000 103 16000 101 14000 99 12000 Frequency Common-Mode Rejection Ratio (dB) Figure 36. Offset vs Temperature 105 97 95 93 AVDD = 3 V REF = 5 V TA = 25oC 15000 Devices 10000 8000 6000 91 4000 89 2000 87 85 0.001 -15 C03 0 0.01 0.1 1 Input Frequency (kHz) 10 Figure 38. CMRR vs Input Frequency 100 -0.01 -0.005 0 0.005 0.01 Gain Error (% FS) C03 C03 Figure 39. Typical Distribution of Gain Error Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 17 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com Typical Characteristics (continued) At TA = 25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 1 MSPS, unless otherwise noted. 16000 8000 AVDD = 3 V REF = 5 V TA = 25oC 15000 Devices 7000 12000 5000 Frequency Frequency 6000 14000 4000 3000 AVDD = 3 V REF = 5 V TA = 25C 15000 Devices 10000 8000 6000 2000 4000 1000 2000 0 0 -4 -3 -2 -1 0 1 Offset (mV) 2 3 ±1.0 4 C03 Figure 40. Typical Distribution of Offset Error 0.0 0.5 1.0 ±0.5 Differential Nonlinearity Min and Max (LSB) 1.5 C038 Figure 41. Typical Distribution of Differential Nonlinearity (Minimum and Maximum) 14000 12000 Frequency 10000 AVDD = 3 V REF = 5 V TA = 25C 15000 Devices 8000 6000 4000 2000 0 ±3.0 ±2.5 ±2.0 ±1.5 ±1.0 ±0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Integral Nonlinearity Min and Max (LSB) C039 Figure 42. Typical Distribution of Integral Nonlinearity (Minimum and Maximum) 18 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 8 Parametric Measurement Information 8.1 Equivalent Circuits 500 µA IOL 1.4 V DOUT 20 pF 500 µA IOH Figure 43. Load Circuit for Digital Interface Timing VIH DIN CONVST SCLK VIL VOH VOH VOL VOL SDO Figure 44. Voltage Levels for Timing Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 19 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com 9 Detailed Description 9.1 Overview The ADS8881 is a high-speed, successive approximation register (SAR), analog-to-digital converter (ADC) from a 16- and 18-bit device family. This compact device features high performance. Power consumption is inherently low and scales linearly with sampling speed. The architecture is based on charge redistribution that inherently includes a sample-and-hold (S/H) function. The ADS8881 supports a true-differential analog input across two pins (INP and INN). When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both the INP and INN inputs are disconnected from the internal circuit. The ADS8881 uses an internal clock to perform conversions. The device reconnects the sampling capacitors to the INP and INN pins after conversion and then enters an acquisition phase. During the acquisition phase, the device is powered down and the conversion result can be read. The device digital output is available in SPI-compatible format, thus making interfacing with microprocessors, digital signal processors (DSPs), or field-programmable gate arrays (FPGAs) easy. 9.2 Functional Block Diagram Figure 45 shows the detailed functional block diagram for the device. AVDD REF DVDD REF CONVST AINP Sample and Hold AINN SCLK SAR ADC ADC SPI DOUT DIN AGND REFM DGND GND GND Figure 45. Detailed Block Diagram 9.3 Feature Description 9.3.1 Analog Input As shown in Figure 45, the device features a differential analog input. Both positive and negative inputs are individually sampled on 55-pF sampling capacitors and the device converts for the voltage difference between the two sampled values: VINP – VINN. 20 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 Feature Description (continued) Most differential input SAR ADCs prohibit the input common-mode voltage, VCM (that is, the average voltage between the inputs), at AINP or AINM from varying more than approximately 10% beyond the mid-scale input value. As shown in Figure 46, the device has a unique common-mode voltage detection and rejection block that does not have this restriction and thus allows VCM to be set to any value between 0 V and VREF without degrading device performance. REF AINP + ± 2 I N T E R F A C E Binary Search Algorithm (SAR) + ± AINM Common Mode Voltage Detection and Rejection Block Figure 46. Conceptual Diagram: True Differential Input Structure Table 6 shows the full-scale input range of the device as a function of input common-mode voltage. The device offers a maximum dynamic range for VCM = VREF / 2. The differential input with wide common-mode range allows connecting differential signals from sensors without any signal conditioning. Table 6. Full-Scale Input Range ABSOLUTE INPUT RANGE VCM FULL SCALE INPUT RANGE (VFS) VAINP VAINN VCM < VREF / 2 0 to 2 × VCM 0 to 2 × VCM (–2 × VCM) to (2 × VCM) VCM = VREF / 2 0 to VREF 0 to VREF (–VREF) to (VREF) VCM > VREF / 2 (2 × VCM – VREF) to VREF (2 × VCM – VREF) to VREF [–2 × (VCM – VREF)] to [2 × (VCM – VREF)] Figure 47 shows an equivalent circuit of the input sampling stage. The sampling switch is represented by a 96-Ω resistance in series with the ideal switch; see the ADC Input Driver section for more details on the recommended driving circuits. Device in Hold Mode 96 AINP 4 pF 55 pF REF 4 pF 55 pF 96 GND GND AINN Figure 47. Input Sampling Stage Equivalent Circuit Figure 45 and Figure 47 illustrate electrostatic discharge (ESD) protection diodes to REF and GND from both analog inputs. Make sure that these diodes do not turn on by keeping the analog inputs within the specified range. Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 21 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com 9.3.2 Reference The device operates with an external reference voltage and switches binary-weighted capacitors onto the reference terminal (REF pin) during the conversion process. The switching frequency is proportional to the internal conversion clock frequency but the dynamic charge requirements are a function of the absolute value of the input voltage and reference voltage. This dynamic load must be supported by a reference driver circuit without degrading the noise and linearity performance of the device. During the acquisition process, the device automatically powers down and does not take any dynamic current from the external reference source. The basic circuit diagram for such a reference driver circuit for precision ADCs is shown in Figure 48; see the ADC Reference Driver section for more details on the application circuits. RREF_FLT Buffer CREF_FLT RBUF_FLT Voltage Reference REF CBUF_FLT ADC Figure 48. Reference Driver Schematic 9.3.3 Clock The device uses an internal clock for conversion. Conversion duration may vary but is bounded by the minimum and maximum value of tconv, as specified in the Timing Requirements section. An external SCLK is only used for a serial data read operation. Data are read after a conversion completes and when the device is in acquisition phase for the next sample. 22 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 9.3.4 ADC Transfer Function The ADS8881 is a unipolar, differential input device. The device output is in twos compliment format. Figure 49 shows ideal characteristics for the device. The full-scale range for the ADC input (AINP – AINN) is equal to twice the reference input voltage to the ADC (2 × VREF). The LSB for the ADC is given by Equation 1. 1 LSB = [2 × (VREF / 218)] (1) ADC Code (Hex) 1FFFF 00000 3FFFF 20001 20000 ±VREF + 1 LSB ±1 LSB 0 VREF ± 1 LSB VIN Differential Analog Input (AINP AINN) Figure 49. Differential Transfer Characteristics 9.4 Device Functional Modes The ADS8881 is a low pin-count device. However, the device offers six different options for interfacing with the digital host. These options can be broadly classified as being either CS mode (in either a 3- or 4-wire interface) or daisychain mode. The device operates in CS mode if DIN is high at the CONVST rising edge. If DIN is low at the CONVST rising edge, or if DIN and CONVST are connected together, the device operates in daisy-chain mode. In both modes, the device can either operate with or without a busy indicator, where the busy indicator is a bit preceding the output data bits that can be used to interrupt the digital host and trigger the data transfer. The 3-wire interface in CS mode is useful for applications that need galvanic isolation on-board. The 4-wire interface in CS mode allows the user to sample the analog input independent of the serial interface timing and, therefore, allows easier control of an individual device while having multiple, similar devices on-board. The daisychain mode is provided to hook multiple devices in a chain similar to a shift register and is useful in reducing component count and the number of signal traces on the board. 9.4.1 CS Mode CS mode is selected if DIN is high at the CONVST rising edge. There are four different interface options available in this mode: 3-wire CS mode without a busy indicator, 3-wire CS mode with a busy indicator, 4-wire CS mode without a busy indicator, and 4-wire CS mode with a busy indicator. The following sections discuss these interface options in detail. Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 23 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com Device Functional Modes (continued) 9.4.1.1 3-Wire CS Mode Without a Busy Indicator This interface option is most useful when a single ADC is connected to an SPI-compatible digital host. In this interface option, DIN can be connected to DVDD and CONVST functions as CS (as shown in Figure 50). As shown in Figure 51, a CONVST rising edge forces DOUT to 3-state, samples the input signal, and causes the device to enter a conversion phase. Conversion is done with the internal clock and continues regardless of the state of CONVST. As a result, CONVST (functioning as CS) can be pulled low after the start of the conversion to select other devices on the board. However, CONVST must return high before the minimum conversion time (tconv-min) elapses and is held high until the maximum possible conversion time (tconv-max) elapses. A high level on CONVST at the end of the conversion ensures the device does not generate a busy indicator. DVDD DIN CONVST CNV SCLK CLK DOUT SDI ADC Digital Host Figure 50. Connection Diagram: 3-Wire CS Mode Without a Busy Indicator (DIN = 1) 1/fsample DIN = HIGH CONVST = 1 CONVST SCLK 1 DOUT D17 2 3 D16 D15 16 17 18 D1 D0 D2 tACQ tconv-max tconv-min ADC STATE Acquiring Sample N Conversion Result of Sample N Clocked-out while Acquiring Sample N+1 Converting Sample N End-of-Conversion Figure 51. Interface Timing Diagram: 3-Wire CS Mode (DIN = 1) When conversion is complete, the device enters an acquisition phase and powers down. CONVST (functioning as CS) can be brought low after the maximum conversion time (tconv-max) elapses. On the CONVST falling edge, DOUT comes out of 3-state and the device outputs the MSB of the data. The lower data bits are output on subsequent SCLK falling edges. Fast sampling rates require high frequency SCLK and data must be read at SCLK falling edges. For slow sampling rates and SCLK frequency ≤ 36 MHz, data can be read at either SCLK falling or rising edges. Note that with any SCLK frequency, reading data at SCLK falling edge requires the digital host to clock in the data during the th_CK_DO-min time frame. DOUT goes to 3-state after the 18th SCLK falling edge or when CONVST goes high, whichever occurs first. 24 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 Device Functional Modes (continued) 9.4.1.2 3-Wire CS Mode With a Busy Indicator This interface option is most useful when a single ADC is connected to an SPI-compatible digital host and an interrupt-driven data transfer is desired. In this interface option, DIN can be connected to DVDD and CONVST functions as CS (as shown in Figure 52). The pull-up resistor on the DOUT pin ensures that the IRQ pin of the digital host is held high when DOUT goes to 3-state. As shown in Figure 53, a CONVST rising edge forces DOUT to 3-state, samples the input signal, and causes the device to enter a conversion phase. Conversion is done with the internal clock and continues regardless of the state of CONVST. As a result, CONVST (functioning as CS) can be pulled low after the start of the conversion to select other devices on the board. However, CONVST must be pulled low before the minimum conversion time (tconv-min) elapses and must remain low until the maximum possible conversion time (tconv-max) elapses. A low level on the CONVST input at the end of a conversion ensures the device generates a busy indicator. DVDD CNV CONVST CLK SCLK DIN DVDD DOUT SDI ADC IRQ Digital Host Figure 52. Connection Diagram: 3-Wire CS Mode With a Busy Indicator 1/fsample DIN = DVDD CONVST CONVST = 0 SCLK 1 2 3 D17 D16 17 18 19 D1 D0 SDO Pulled-up DOUT BUSY D2 tACQ tconv-max tconv-min ADC STATE Acquiring Sample N Conversion Result of Sample N Clocked-out while Acquiring Sample N+1 Converting Sample N End-of-Conversion Figure 53. Interface Timing Diagram: 3-Wire CS Mode With a Busy Indicator (DIN = 1) When conversion is complete, the device enters an acquisition phase and powers down, DOUT comes out of 3state, and the device outputs a busy indicator bit (low level) on the DOUT pin. This configuration provides a highto-low transition on the IRQ pin of the digital host. The data bits are clocked out, MSB first, on the subsequent SCLK falling edges. Fast sampling rates require high frequency SCLK and data must be read at SCLK falling edges. For slow sampling rates and SCLK frequency ≤ 36 MHz, data can be read at either SCLK falling or rising edges. Note that with any SCLK frequency, reading data at SCLK falling edge requires the digital host to clock in the data during the th_CK_DO-min time frame. DOUT goes to 3-state after the 19th SCLK falling edge or when CONVST goes high, whichever occurs first. Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 25 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com Device Functional Modes (continued) 9.4.1.3 4-Wire CS Mode Without a Busy Indicator This interface option is useful when one or more ADCs are connected to an SPI-compatible digital host. Figure 54 shows the connection diagram for single ADC; see Figure 56 for the connection diagram for two ADCs. CS CNV DIN CONVST DOUT SDI SCLK CLK ADC Digital Host Figure 54. Connection Diagram: Single ADC With 4-Wire CS Mode Without a Busy Indicator In this interface option, DIN is controlled by the digital host and functions as CS. As shown in Figure 55, with DIN high, a CONVST rising edge selects CS mode, forces DOUT to 3-state, samples the input signal, and causes the device to enter a conversion phase. In this interface option, CONVST must be held at a high level from the start of the conversion until all data bits are read. Conversion is done with the internal clock and continues regardless of the state of DIN. As a result, DIN (functioning as CS) can be pulled low to select other devices on the board. However, DIN must be pulled high before the minimum conversion time (tconv-min) elapses and remains high until the maximum possible conversion time (tconv-max) elapses. A high level on DIN at the end of the conversion ensures the device does not generate a busy indicator. 1/fsample tconv-max tACQ tconv-min CONVST DIN = 1 DIN SCLK 1 2 DOUT D17 D16 17 18 ADC STATE Acquiring Sample N D1 D0 End-ofConversion Read Sample N Converting Sample N Acquiring Sample N+1 Figure 55. Interface Timing Diagram: Single ADC With 4-Wire CS Mode 26 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 Device Functional Modes (continued) When conversion is complete, the device enters acquisition phase and powers down. DIN (functioning as CS) can be brought low after the maximum conversion time (tconv-max) elapses. On the DIN falling edge, DOUT comes out of 3-state and the device outputs the MSB of the data. The lower data bits are output on subsequent SCLK falling edges. Fast sampling rates require high frequency SCLK and data must be read at SCLK falling edges. For slow sampling rates and SCLK frequency ≤ 36 MHz, data can be read at either SCLK falling or rising edges. Note that with any SCLK frequency, reading data at SCLK falling edge requires the digital host to clock in the data during the th_CK_DO-min time frame. DOUT goes to 3-state after the 18th SCLK falling edge or when DIN goes high, whichever occurs first. As shown in Figure 56, multiple devices can be hooked together on the same data bus. In this case, as shown in Figure 57, the DIN of the second device (functioning as CS for the second device) can go low after the first device data are read and the DOUT of the first device is in 3-state. Care must be taken so that CONVST and DIN are not both low together at any time during the cycle. CS1 CS2 CNV CONVST DIN CONVST DIN DOUT DOUT SCLK SDI SCLK CLK ADC #1 ADC #2 Digital Host Figure 56. Connection Diagram: Two ADCs With 4-Wire CS Mode Without a Busy Indicator 1/fsample tconv-max tACQ tconv-min CONVST DIN = 1 DIN (ADC 1) DIN = 1 DIN (ADC 2) SCLK 1 2 DOUT D17 D16 17 18 19 20 D0 D17 D16 ADC STATE Acquiring Sample N Converting Sample N 36 End-ofConversion 35 D1 D1 D0 Read Sample N ADC 1 Read Sample N ADC 2 Acquiring Sample N+1 Figure 57. Interface Timing Diagram: Two ADCs With 4-Wire CS Mode Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 27 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com Device Functional Modes (continued) 9.4.1.4 4-Wire CS Mode With a Busy Indicator This interface option is most useful when a single ADC is connected to an SPI-compatible digital host and an interrupt-driven data transfer is desired. In this interface option, the analog sample is least affected by clock jitter because the CONVST signal (used to sample the input) is independent of the data read operation. In this interface option, DIN is controlled by the digital host and functions as CS (as shown in Figure 58). The pull-up resistor on the DOUT pin ensures that the IRQ pin of the digital host is held high when DOUT goes to 3-state. As shown in Figure 59, when DIN is high, a CONVST rising edge selects CS mode, forces DOUT to 3-state, samples the input signal, and causes the device to enter a conversion phase. In this interface option, CONVST must be held high from the start of the conversion until all data bits are read. Conversion is done with the internal clock and continues regardless of the state of DIN. As a result, DIN (acting as CS) can be pulled low to select other devices on the board. However, DIN must be pulled low before the minimum conversion time (tconv-min) elapses and remains low until the maximum possible conversion time (tconv-max) elapses. A low level on the DIN input at the end of a conversion ensures the device generates a busy indicator. CS DIN CNV CONVST CLK SCLK DVDD DOUT SDI IRQ ADC Digital Host Figure 58. Connection Diagram: 4-Wire CS Mode With a Busy Indicator 1/fsample tACQ tconv-max tconv-min CONVST DIN =0 DIN SCLK 1 2 3 D17 D16 17 18 19 D1 D0 DOUT ADC STATE SDO Pulled-up Acquiring Sample N Converting Sample N BUSY D2 Conversion Result of Sample N Clocked-out while Acquiring Sample N+1 Figure 59. Interface Timing Diagram: 4-Wire CS Mode With a Busy Indicator 28 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 Device Functional Modes (continued) When conversion is complete, the device enters an acquisition phase and powers down, DOUT comes out of 3state, and the device outputs a busy indicator bit (low level) on the DOUT pin. This configuration provides a highto-low transition on the IRQ pin of the digital host. The data bits are clocked out, MSB first, on the subsequent SCLK falling edges. Fast sampling rates require high frequency SCLK and data must be read at SCLK falling edges. For slow sampling rates and SCLK frequency ≤ 36 MHz, data can be read at either SCLK falling or rising edges. Note that with any SCLK frequency, reading data at SCLK falling edge requires the digital host to clock in the data during the th_CK_DO-min time frame. DOUT goes to 3-state after the 19th SCLK falling edge or when DIN goes high, whichever occurs first. Care must be taken so that CONVST and DIN are not both low together at any time during the cycle. 9.4.2 Daisy-Chain Mode Daisy-chain mode is selected if DIN is low at the time of a CONVST rising edge or if DIN and CONVST are connected together. Similar to CS mode, this mode features operation with or without a busy indicator. The following sections discuss these interface modes in detail. 9.4.2.1 Daisy-Chain Mode Without a Busy Indicator This interface option is most useful in applications where multiple ADC devices are used but the digital host has limited interfacing capability. Figure 60 shows a connection diagram with N ADCs connected in the daisy-chain. The CONVST pins of all ADCs in the chain are connected together and are controlled by a single pin of the digital host. Similarly, the SCLK pins of all ADCs in the chain are connected together and are controlled by a single pin of the digital host. The DIN pin for ADC 1 (DIN-1) is connected to GND. The DOUT pin of ADC 1 (DOUT-1) is connected to the DIN pin of ADC 2 (DIN-2), and so on. The DOUT pin of the last ADC in the chain (DOUT-N) is connected to the SDI pin of the digital host. CNV CONVST DIN1 DOUT1 SCLK CONVST DIN2 CONVST DOUT2 } SCLK DINN-2 DOUTN-1 CONVST DINN-1 SCLK DOUTN SDI SCLK CLK ADC 1 ADC 2 } ADC N1 ADC N Digital Host Figure 60. Connection Diagram: Daisy-Chain Mode Without a Busy Indicator (DIN = 0) Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 29 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com Device Functional Modes (continued) As shown in Figure 61, the device DOUT pin is driven low when DIN and CONVST are low together. With DIN low, a CONVST rising edge selects daisy-chain mode, samples the analog input, and causes the device to enter a conversion phase. In this interface option, CONVST must remain high from the start of the conversion until all data bits are read. When started, the conversion continues regardless of the state of SCLK, however SCLK must be low at the CONVST rising edge so that the device does not generate a busy indicator at the end of the conversion. tconv-min 1/fsample tconv-max tACQ CONVST SCLK 1 2 17 18 19 20 35 36 DIN-1 = LOW DOUT-1 & DIN-2 D17 D17 DOUT-2 End-ofConversion ADC STATE Acquiring 6DPSOHµQ¶ Converting 6DPSOHµQ¶ ADC 1 data D16 D1 D16 D0 D1 D0 ADC 1 data D16 D1 D17 ADC 2 data ADC 2 GDWDIRUVDPSOHµQ¶ D0 ADC 1 GDWDIRUVDPSOHµQ¶ $FTXLULQJ6DPSOHµQ+1¶ Figure 61. Interface Timing Diagram: For Two Devices in Daisy-Chain Mode At the end of conversion, every ADC in the chain loads its own conversion result into the internal, 18-bit, shift register and also outputs the MSB bit of this conversion result on its own DOUT pin. All ADCs enter an acquisition phase and power-down. On every subsequent SCLK falling edge, the internal shift register of each ADC latches the data available on its DIN pin and shifts out the next bit of data on its DOUT pin. Therefore, the digital host receives the data of ADC N, followed by the data of ADC N–1, and so on (in MSB-first fashion). A total of 18 x N SCLK falling edges are required to capture the outputs of all N devices in the chain. Fast sampling rates require high frequency SCLK and data must be read at SCLK falling edges. For slow sampling rates and SCLK frequency ≤ 36 MHz, data can be read at either SCLK falling or rising edges. Note that with any SCLK frequency, reading data at SCLK falling edge requires the digital host to clock in the data during the th_CK_DO-min time frame. 30 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 Device Functional Modes (continued) 9.4.2.2 Daisy-Chain Mode With a Busy Indicator This interface option is most useful in applications where multiple ADC devices are used but the digital host has limited interfacing capability and an interrupt-driven data transfer is desired. Figure 62 shows a connection diagram with N ADCs connected in the daisy-chain. The CONVST pins of all ADCs in the chain are connected together and are controlled by a single pin of the digital host. Similarly, the SCLK pins of all ADCs in the chain are connected together and are controlled by a single pin of the digital host. The DIN pin for ADC 1 (DIN-1) is connected to its CONVST. The DOUT pin of ADC 1 (DOUT-1) is connected to the DIN pin of ADC 2 (DIN-2), and so on. The DOUT pin of the last ADC in the chain (DOUT-N) is connected to the SDI and IRQ pins of the digital host. CNV CONVST DIN1 DOUT1 CONVST DIN2 SCLK CONVST DOUT2 } SCLK DINN-1 CONVST DOUTN-1 DINN SCLK IRQ DOUTN SDI SCLK CLK ADC 1 ADC 2 } ADC N ADC N1 Digital Host Figure 62. Connection Diagram: Daisy-Chain Mode With a Busy Indicator (DIN = 0) As shown in Figure 63, the device DOUT pin is driven low when DIN and CONVST are low together. A CONVST rising edge selects daisy-chain mode, samples the analog input, and causes the device to enter a conversion phase. In this interface option, CONVST must remain high from the start of the conversion until all data bits are read. When started, the conversion continues regardless of the state of SCLK, however SCLK must be high at the CONVST rising edge so that the device generates a busy indicator at the end of the conversion. tconv-min 1/fsample tconv-max tACQ CONVST SCLK 1 th-DI-CNV DIN-1 = CONVST DOUT-1 & DIN-2 BUSY BUSY DOUT-2 End-ofConversion ADC STATE Acquiring 6DPSOHµQ¶ 18 2 19 ADC 1 data D17 D1 D0 D17 21 36 37 ADC 1 data D1 D0 D17 ADC 2 data ADC 2 GDWDIRUVDPSOHµQ¶ Converting 6DPSOHµQ¶ 20 D16 D1 D0 ADC 1 GDWDIRUVDPSOHµQ¶ $FTXLULQJ6DPSOHµQ+1¶ Figure 63. Interface Timing Diagram: For Two Devices in Daisy-Chain Mode With a Busy Indicator Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 31 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com Device Functional Modes (continued) At the end of conversion, every ADC in the chain loads its own conversion result into the internal, 18-bit, shift register and also forces its DOUT pin high, thereby providing a low-to-high transition on the IRQ pin of the digital host. All ADCs enter an acquisition phase and power-down. On every subsequent SCLK falling edge, the internal shift register of each ADC latches the data available on its DIN pin and shifts out the next bit of data on its DOUT pin. Therefore, the digital host receives the interrupt signal followed by the data of ADC N followed by the data of ADC N–1, and so on (in MSB-first fashion). A total of (18 × N) + 1 SCLK falling edges are required to capture the outputs of all N devices in the chain. Fast sampling rates require a high-frequency SCLK and data must be read at the SCLK falling edges. For slow sampling rates and SCLK frequency ≤ 36 MHz, data can be read at either SCLK falling or rising edges. Note that with any SCLK frequency, reading data at the SCLK falling edge requires the digital host to clock in the data during the th_CK_DO-min time frame. Note that the busy indicator bits of ADC 1 to ADC N–1 do not propagate to the next device in the chain. NOTE: For SCLK ≤ 36 MHz, SPI mode-3 (CPOL = 1, CPHA = 1) allows reading the conversion results of N ADCs in 18 × N SCLK cycles because the busy indicator bit is not clocked in by the host. 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The two primary circuits required to maximize the performance of a high-precision, successive approximation register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This section details some general principles for designing these circuits, followed by some application circuits designed using the ADS8881. 10.1.1 ADC Reference Driver The external reference source to the ADS8881 must provide low-drift and very accurate voltage for the ADC reference input and support the dynamic charge requirements without affecting the noise and linearity performance of the device. The output broadband noise of most references can be in the order of a few hundred μVRMS. Therefore, to prevent any degradation in the noise performance of the ADC, the output of the voltage reference must be appropriately filtered by using a low-pass filter with a cutoff frequency of a few hundred hertz. After band-limiting the noise of the reference circuit, the next important step is to design a reference buffer that can drive the dynamic load posed by the reference input of the ADC. The reference buffer must regulate the voltage at the reference pin such that the value of VREF stays within the 1-LSB error at the start of each conversion. This condition necessitates the use of a large capacitor, CBUF_FLT (see Figure 48) for regulating the voltage at the reference input of the ADC. The amplifier selected to drive the reference pin must have an extremely low offset and temperature drift with a low output impedance to drive the capacitor at the ADC reference pin without any stability issues. 10.1.2 ADC Input Driver The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a fly-wheel RC filter. The amplifier is used for signal conditioning of the input voltage and its low output impedance provides a buffer between the signal source and the switched capacitor inputs of the ADC. The RC filter helps attenuate the sampling charge injection from the switched-capacitor input stage of the ADC and functions as an antialiasing filter to band-limit the wideband noise contributed by the front-end circuit. Careful design of the front-end circuit is critical to meet the linearity and noise performance of a high-precision, 18-bit ADC such as the ADS8881. 32 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 Application Information (continued) 10.1.2.1 Input Amplifier Selection Selection criteria for the input amplifiers is highly dependent on the input signal type as well as the performance goals of the data acquisition system. Some key amplifier specifications to consider while selecting an appropriate amplifier to drive the inputs of the ADC are: • Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance of the amplifier, thus allowing the amplifier to more easily drive the low cutoff frequency RC filter (see the Antialiasing Filter section) at the inputs of the ADC. Higher bandwidth also minimizes the harmonic distortion at higher input frequencies. In order to maintain the overall stability of the input driver circuit, select the amplifier bandwidth as described in Equation 2: § 1 Unity Gain Bandwidth t 4 u ¨¨ © 2S u ( RFLT RFLT ) u C FLT • · ¸¸ ¹ (2) Noise. Noise contribution of the front-end amplifiers must be as low as possible to prevent any degradation in SNR performance of the system. As a rule of thumb, to ensure that the noise performance of the data acquisition system is not limited by the front-end circuit, the total noise contribution from the front-end circuit must be kept below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is bandlimited by designing a low cutoff frequency RC filter, as explained in Equation 3. 2 § V 1 _ AM P_ PP · S ¨ ¸ NG u 2 u ¨ f en2 _ RM S u u f3dB ¸ 6 . 6 2 ¨ ¸ © ¹ d § SNR dB · ¸ 20 ¹ ¨ 1 VREF u u 10 © 5 2 where: • • • • • V1 / f_AMP_PP is the peak-to-peak flicker noise in µV, en_RMS is the amplifier broadband noise density in nV/√Hz, f–3dB is the 3-dB bandwidth of the RC filter, and NG is the noise gain of the front-end circuit, which is equal to 1 in a buffer configuration. THD AMP d THD ADC 10 dB • (3) Distortion. Both the ADC and the input driver introduce nonlinearity in a data acquisition block. As a rule of thumb, to ensure that the distortion performance of the data acquisition system is not limited by the front-end circuit, the distortion of the input driver must be at least 10 dB lower than the distortion of the ADC, as shown in Equation 4. (4) Settling Time. For dc signals with fast transients that are common in a multiplexed application, the input signal must settle within an 18-bit accuracy at the device inputs during the acquisition time window. This condition is critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the desired 18-bit accuracy. Therefore, always verify the settling behavior of the input driver by TINA™-SPICE simulations before selecting the amplifier. 10.1.2.2 Antialiasing Filter Converting analog-to-digital signals requires sampling an input signal at a constant rate. Any higher frequency content in the input signal beyond half the sampling frequency is digitized and folded back into the low-frequency spectrum. This process is called aliasing. Therefore, an analog, antialiasing filter must be used to remove the harmonic content from the input signal before being sampled by the ADC. An antialiasing filter is designed as a low-pass, RC filter, for which the 3-dB bandwidth is optimized based on specific application requirements. For dc signals with fast transients (including multiplexed input signals), a high-bandwidth filter is designed to allow accurately settling the signal at the inputs of the ADC during the small acquisition time window. For ac signals, keep the filter bandwidth low to band-limit the noise fed into the input of the ADC, thereby increasing the signalto-noise ratio (SNR) of the system. Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 33 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com Application Information (continued) Besides filtering the noise from the front-end drive circuitry, the RC filter also helps attenuate the sampling charge injection from the switched-capacitor input stage of the ADC. A differential filter capacitor, CFLT, is connected across the inputs of the ADC (as shown in Figure 64). This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition process. As a rule of thumb, the value of this capacitor must be at least 10 times the specified value of the ADC sampling capacitance. For the ADS8881, the input sampling capacitance is equal to 59 pF, thus the value of CFLT must be greater than 590 pF. The capacitor must be a COG- or NPO-type because these capacitor types have a high-Q, low-temperature coefficient, and stable electrical characteristics under varying voltages, frequency, and time. RFLT 22 f 3 dB 2S u R FLT 1 R FLT u CFLT V AINP + CFLT 590 pF Device AINM GND RFLT 22 Figure 64. Antialiasing Filter Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance, input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability and distortion of the design. For the ADS8881, TI recommends limiting the value of RFLT to a maximum of 22 Ω in order to avoid any significant degradation in linearity performance. The tolerance of the selected resistors can be chosen as 1% because the use of a differential capacitor at the input balances the effects resulting from any resistor mismatch. The input amplifier bandwidth must be much higher than the cutoff frequency of the antialiasing filter. TI strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase margin with the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some amplifiers might require more bandwidth than others to drive similar filters. If an amplifier has less than a 40° phase margin with 22-Ω resistors, using a different amplifier with higher bandwidth or reducing the filter cutoff frequency with a larger differential capacitor is advisable. This section describes some common application circuits using the ADS8881. These data acquisition (DAQ) blocks are optimized for specific input types and performance requirements of the system. For simplicity, powersupply decoupling capacitors are not shown in these circuit diagrams; see the Power Supply section for suggested guidelines. 34 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 10.2 Typical Applications 10.2.1 DAQ Circuit for a 1-µs, Full-Scale Step Response Reference Drive Circuit 20 k 1 µF THS4281 + 0.2 OPA+ - 1k + OPA333 1 µF + 1k + OPA+ 10 µF REF5045 (See Reference Datasheet for Detailed Pin Configuration) OPA+ 1 µF + OPA+ VIN+ + AVDD + OPA350 10 REF AVDD VCM V + AINP 1 nF CONVST Device AINM GND + VIN- - CONVST 10 OPA350 + + SAR ADC OPA+ Input Driver Figure 65. DAQ Circuit for a 1-µs, Full-Scale Step Response 10.2.1.1 Design Requirements Step input signals are common in multiplexed applications when switching between different channels. In a worst-case scenario, one channel is at the negative full-scale (NFS) and the other channel is at the positive fullscale (PFS) voltage, in which case the step size is the full-scale range (FSR) of the ADC when the MUX channel is switched. Design an application circuit optimized for using the ADS8881 to achieve • full-scale step input settling to 18-bit accuracy and • INL of < ±2 LSB and • maximum specified throughput of 1 MSPS 10.2.1.2 Detailed Design Procedure The application circuit is shown in Figure 65. In such applications, the primary design requirement is to ensure that the full-scale step input signal settles to 18bit accuracy at the ADC inputs. This condition is critical to achieve the excellent linearity specifications of the ADC. Therefore, the bandwidth of the antialiasing RC filter must be large enough to allow optimal settling of the input signal during the ADC acquisition time. The filter capacitor helps reduce the sampling charge injection at the ADC inputs, but degrades the phase margin of the driving amplifier, thereby leading to stability issues. Amplifier stability is maintained by the series isolation resistor. The application circuit in Figure 65 shows the schematic of a complete reference driver circuit that generates a voltage of 4.5 V dc using a single 5-V supply. This circuit is suitable to drive the reference of the ADS8881 at higher sampling rates up to 1 MSPS. The reference voltage of 4.5 V in this design is generated by the highprecision, low-noise REF5045 circuit. The output broadband noise of the reference is heavily filtered by a lowpass filter with a 3-dB cutoff frequency of 160 Hz. Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 35 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com Typical Applications (continued) The reference buffer is designed with the THS4281 and OPA333 in a composite architecture to achieve superior dc and ac performance at a reduced power consumption, compared to using a single high-performance amplifier. The THS4281 is a high-bandwidth amplifier with a very low output impedance of 1 Ω at a frequency of 1 MHz. The low output impedance makes the THS4281 a good choice for driving a high capacitive load to regulate the voltage at the reference input of the ADC. The high offset and drift specifications of the THS4281 are corrected by using a dc-correcting amplifier (OPA333) inside the feedback loop. The composite scheme inherits the extremely low offset and temperature drift specifications of the OPA333. For the input driving amplifiers, key specifications include rail-to-rail input and output swing, high bandwidth, high slew rate, and fast settling time. The OPA350 CMOS amplifier meets all these specification requirements for this circuit with a single-supply and low quiescent current. The component values of the antialiasing filter are selected to meet the settling requirements of the system as well as to maintain the stability of the input driving amplifiers. 10.2.1.3 Application Curve 1.5 Integral Nonlinearity (LSB) 1.25 1 0.75 0.5 0.25 0 -0.25 -0.5 -0.75 -1 -1.25 -1.5 ±131072 131071 Code C001 18-bit INL Figure 66. Limited Point Linearity For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, see 18-Bit Data Acquisition (DAQ) Block Optimized for 1-μs Full-Scale Step Response (TIDU012). 36 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 10.2.2 Low-Power DAQ Circuit for Excellent Dynamic Performance at 1 MSPS Reference Drive Circuit 20 k 1 µF THS4281 + 0.2 OPA+ - 1k + OPA333 1 µF + 1k + OPA+ 10 µF REF5045 (See Reference Datasheet for Detailed Pin Configuration) OPA+ 1 µF + OPA+ VIN+ + AVDD + OPA320 22 REF AVDD VCM V + AINP 2.2 nF CONVST Device AINM GND + VIN- - CONVST 22 OPA320 + + SAR ADC OPA+ Input Driver Figure 67. DAQ Circuit for Lowest Power and Excellent Dynamic Performance at 1 MSPS 10.2.2.1 Design Requirements Design an application circuit optimized for using the ADS8881 to achieve • ENOB > 17 bits and • < 35 mW of total power consumption and • maximum specified throughput of 1 MSPS 10.2.2.2 Detailed Design Procedure The application circuit in Figure 67 shows the schematic of a complete reference driver circuit that generates a voltage of 4.5 V dc using a single 5-V supply. This circuit is suitable to drive the reference of the ADS8881 at higher sampling rates up to 1 MSPS. The reference voltage of 4.5 V in this design is generated by the highprecision, low-noise REF5045 circuit. The output broadband noise of the reference is heavily filtered by a lowpass filter with a 3-dB cutoff frequency of 160 Hz. The reference buffer is designed with the THS4281 and OPA333 in a composite architecture to achieve superior dc and ac performance at a reduced power consumption, compared to using a single high-performance amplifier. The THS4281 is a high-bandwidth amplifier with a very low output impedance of 1 Ω at a frequency of 1 MHz. The low output impedance makes the THS4281 a good choice for driving a high capacitive load to regulate the voltage at the reference input of the ADC. The high offset and drift specifications of the THS4281 are corrected by using a dc-correcting amplifier (OPA333) inside the feedback loop. The composite scheme inherits the extremely low offset and temperature drift specifications of the OPA333. In such applications, the input driver must be low in power and noise as well as able to support rail-to-rail input and output swing with a single supply. A high amplifier bandwidth is also preferred to help attenuate highfrequency distortion. However, oftentimes bandwidth and noise are traded off with the power consumption of the amplifier. This circuit uses the OPA320 as the front-end driving amplifier because this device has a relatively low noise density of 7 nV/√Hz for a maximum-specified quiescent current of 1.45 mA per channel. The noise contribution from the front-end amplifier is band-limited by the 3-dB bandwidth of the RC filter and is designed to be 1.65 MHz in this application. Again, the component values of the antialiasing filter are carefully selected to maintain the stability of the input driving amplifiers. Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 37 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com 10.2.2.3 Application Curve 16000 14000 Number of Hits 12000 10000 8000 6000 4000 2000 0 -11 -10 -9 -8 -7 -6 -5 Code -4 C002 Vdiff close to 0 V, 32768 data points, standard deviation = 0.82 bits, ENOB (dc) = 17.18 bits Figure 68. DC Input Histogram For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, see 18-Bit, 1-MSPS Data Acquisition (DAQ) Block Optimized for Lowest Power (SLAU513). 38 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 10.2.3 DAQ Circuit for Lowest Distortion and Noise Performance at 1 MSPS Reference Drive Circuit 20 k 1 µF THS4281 + 0.2 OPA+ - 1k + OPA333 + 1 µF 1k REF5045 + (See Reference Datasheet for Detailed Pin Configuration) OPA+ OPA+ 10 µF 1 µF 1k 1k AVDD OPA+ VIN+ VCM + 10 + REF AVDD V + 10 nF CONVST Device AINM 10 CONVST GND + VIN- AINP THS4521 + - 1k 1k SAR ADC Input Driver Figure 69. Differential Input DAQ Circuit for Lowest Distortion and Noise at 1 MSPS Reference Drive Circuit 20 k 1 µF THS4281 + 0.2 OPA+ - 1k + OPA333 1 µF + 1k + OPA+ 10 µF REF5045 (See Reference Datasheet for Detailed Pin Configuration) OPA+ 1 µF 1k 1k AVDD OPA+ VIN+ + THS4521 + - 10 REF AVDD + 10 nF CONVST Device AINM 10 1k V + AINP GND 1k CONVST SAR ADC Input Driver Figure 70. Single-Ended to Differential DAQ Circuit for Lowest Distortion and Noise at 1 MSPS Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 39 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com 10.2.3.1 Design Requirements Design an application circuit optimized for using the ADS8881 to achieve • > 98.5-dB SNR, < –110-dB THD and • ± 1.5-LSB linearity and • maximum specified throughput of 1 MSPS 10.2.3.2 Detailed Design Procedure The application circuits are shown in Figure 69 and Figure 70. In both applications, the input signal is processed through a high-bandwidth, low-distortion, fully-differential amplifier (FDA) designed in an inverting gain configuration and a low-pass RC filter before being fed into the ADC. The reference driver circuit, shown in Figure 69 and Figure 70, generates a voltage of 4.5 V dc using a single 5V supply. This circuit is suitable to drive the reference of the ADS8881 at higher sampling rates up to 1 MSPS. The reference voltage of 4.5 V in this design is generated by the high-precision, low-noise REF5045 circuit. The output broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 160 Hz. The reference buffer is designed with the THS4281 and OPA333 in a composite architecture to achieve superior dc and ac performance at a reduced power consumption, compared to using a single high-performance amplifier. The THS4281 is a high-bandwidth amplifier with a very low output impedance of 1 Ω at a frequency of 1 MHz. The low output impedance makes the THS4281 a good choice for driving a high capacitive load to regulate the voltage at the reference input of the ADC. The high offset and drift specifications of the THS4281 are corrected by using a dc-correcting amplifier (OPA333) inside the feedback loop. The composite scheme inherits the extremely low offset and temperature drift specifications of the OPA333. As a rule of thumb, the distortion from the input driver must be at least 10 dB less than the ADC distortion. The distortion resulting from variation in the common-mode signal is eliminated by using the FDA in an inverting gain configuration that establishes a fixed common-mode level for the circuit. This configuration also eliminates the requirement of a rail-to-rail swing at the amplifier input. Therefore, these circuits use the low-power THS4521 as an input driver that provides exceptional ac performance because of its extremely low-distortion and highbandwidth specifications. In addition, the components of the antialiasing filter are such that the noise from the front-end circuit is kept low without adding distortion to the input signal. The circuit in Figure 69 shows a fully-differential DAQ block optimized for low distortion and noise using the THS4521 and ADS8881. This front-end circuit configuration requires a differential signal at the input of the FDA and provides a differential output to drive the ADC inputs. The common-mode voltage of the input signal provided to the ADC is set by the VOCM pin of the THS4521 (not shown in Figure 69). To use the complete dynamic range of the ADC, VOCM can be set to VREF / 2 by using a simple resistive divider. However, note that the ADS8881 allows the common-mode input voltage (VCM) to be set to any value in the range of 0 V to VREF. The circuit in Figure 70 shows a single-ended to differential DAQ block optimized for low distortion and noise using the THS4521 and the ADS8881. This front-end circuit configuration requires a single-ended ac signal at the input of the FDA and provides a fully-differential output to drive the ADC inputs. The common-mode voltage of the input signal provided to the ADC is set by the VOCM pin of the THS4521 (not shown in Figure 70). To use the complete dynamic range of the ADC, VOCM can be set to VREF / 2 by using a simple resistive divider. However, note that the ADS8881 allows the common-mode input voltage (VCM) to be set to any value in the range of 0 V to VREF. 40 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 10.2.3.3 Application Curve 0 Signal Power (dB) ±20 ±40 ±60 ±80 ±100 ±120 ±140 ±160 0 100 200 300 400 Input Frequency (kHz) 500 C003 fIN = 10 kHz, SNR = 99 dB, THD = –112 dB Figure 71. FFT Plot For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, see 18-Bit, 1-MSPS Data Acquisition (DAQ) Block Optimized for Lowest Distortion and Noise (SLAU515). Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 41 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com 10.2.4 Ultralow-Power DAQ Circuit at 10 kSPS 1k Reference Drive Circuit 1 µF AVDD - 4.7 OPA313 10 k REF3325 + + (See Reference Datasheet for Detailed Pin Configuration) 22 µF 1 µF AVDD 10 k AVDD 10 nF REF AVDD AINP CONVST Device AINM - 1k GND CONVST + OPA333 + + VIN+ VCM AVDD 4.7 nF VIN+ + + 1k OPA333 Device running at 10 kSPS. - 10 nF 10 k Input Driver Figure 72. Ultralow-Power DAQ Circuit at 10 kSPS 10.2.4.1 Design Requirements Portable and battery-powered applications require ultralow-power consumption and do not need very high throughput from the ADC. Design a single-supply, data acquisition circuit optimized for using the ADS8881 to achieve • ENOB > 16 bits and • Ultralow-power consumption of < 1 mW at throughput of 10 kSPS. 10.2.4.2 Detailed Design Procedure The application circuit in Figure 72 shows the schematic of a complete reference driver circuit that generates a voltage of 2.5 V dc using a single 3.3-V supply. This ultralow power reference block is suitable to drive the ADS8881 for power-sensitive applications at a relatively lower throughput. This design uses the high-precision REF3325 circuit that provides an accurate 2.5-V reference voltage at an extremely low quiescent current of 5 µA. The output broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 16 Hz. The reference buffer is designed with the low-power OPA313 that can operate from a 3.3-V supply at an extremely low quiescent current of 50 µA. The wideband noise contribution from the amplifier is limited by a lowpass filter of a cutoff frequency equal to 1.5 kHz, formed by a 4.7-Ω resistor in combination with a 22-μF capacitor. The 4.7-Ω series resistor creates an additional drop in the reference voltage that is corrected by a dual-feedback configuration. 42 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 The input driver circuit uses extremely low-power, dual amplifiers (such as the OPA2333) with a maximum quiescent current of 28 µA per channel to drive the ADC inputs. The input amplifiers are configured in a modified unity-gain buffer configuration. The filter capacitor at the ADC inputs attenuates the sampling charge-injection noise from the ADC but effects the stability of the input amplifiers by degrading the phase margin. This attenuation requires a series isolation resistor to maintain amplifier stability. The value of the series resistor is directly proportional to the open-loop output impedance of the driving amplifier to maintain stability, which is high (in the order of kΩ) in the case of low-power amplifiers such as the OPA333. Therefore, a high value of 1 kΩ is selected for the series resistor at the ADC inputs. However, this series resistor creates an additional voltage drop in the signal path, thereby leading to linearity and distortion issues. The dual-feedback configuration used in Figure 72 corrects for this additional voltage drop and maintains system performance at ultralow-power consumption. 10.2.4.3 Application Curve 10000 9000 Number of Hits 8000 7000 6000 5000 4000 3000 2000 1000 0 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 -13 -12 -11 Code C004 Vdiff close to 0 V, 32768 data points, standard deviation = 1.7 bits, ENOB (dc) = 16.3 bits Figure 73. DC Input Histogram For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, see 18-Bit, 10kSPS Data Acquisition (DAQ) Block Optimized for Ultra Low Power < 1mW (SLAU514). Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 43 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com 11 Power-Supply Recommendations The device has two separate power supplies: AVDD and DVDD. The internal circuits of the device operate on AVDD; DVDD is used for the digital interface. AVDD and DVDD can be independently set to any value within the permissible range. 11.1 Power-Supply Decoupling Decouple the AVDD and DVDD pins with GND, using individual 1-µF decoupling capacitors placed in close proximity to the pin, as shown in Figure 74. Digital Supply REF Analog Supply DVDD AVDD 1 µF 1 µF DIN AINP SCLK AINN DOUT GND CONVST Figure 74. Supply Decoupling 11.2 Power Saving The device has an auto power-down feature that powers down the internal circuitry at the end of every conversion. Referring to Figure 75, the input signal is acquired on the sampling capacitors when the device is in a power-down state (tacq); at the same time, the result for the previous conversion is available for reading. The device powers up on the start of the next conversion. During conversion phase (tconv), the device also consumes current from the reference source (connected to the REF pin). tTHROUGHPUT Device Phase tCONV tACQ IREF tACQ ~50000X ~50000X IAVDD tCONV 2 x tTHROUGHPUT ~1200X ~1200X ~2X IAVG(AVDD+REF) Figure 75. Power Scaling With Throughput 44 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 Power Saving (continued) The conversion time, tconv, is independent of the SCLK frequency. When operating the device at speeds lower than the maximum rated throughput, the conversion time, tconv, does not change; the device spends more time in power-down state. Therefore, as shown in Figure 76, the device power consumption from the AVDD supply and the external reference source is directly proportional to the speed of operation. Extremely low AVDD power-down current (50 nA, typical) and extremely low external reference leakage current (250 nA, typical), make this device ideal for very low throughput applications (such as pulsed measurements). Power Consumption (mW) 6 5 4 3 2 1 0 0 200 400 600 Throughput (kSPS) 800 1000 C03 Figure 76. Power Scaling With Throughput Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 45 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com 12 Layout 12.1 Layout Guidelines Figure 77 shows a board layout example for the device. Appropriate layout that interconnects accompanying capacitors and converters with low inductance is critical for achieving optimum performance. Thus, a PCB board with at least four layers is recommended to keep all critical components on the top layer and interconnected to a solid (low inductance) analog ground plane at the subsequent inner layer using 15-mil vias. Avoid crossing digital lines with the analog signal path and keep the analog input signals and the reference input signals away from noise sources. As shown in Figure 77, the analog input and reference signals are routed on the left side of the board and the digital connections are routed on the right side of the device. As a result of dynamic currents during conversion and data transfer, each supply pin (AVDD and DVDD) must have a decoupling capacitor to keep the supply voltage stable. To maximize decoupling capabilities, inductance between each supply capacitor and the supply pin of the converter is kept less than 5 nH by placing the capacitor within 0.2-inches from the pin and connecting it with 20-mil traces and a 15-mil grounding via, as shown in Figure 77. TI recommends using one 1-μF ceramic capacitor at each supply pin. Avoid placing vias between the supply pin and its decoupling capacitor. Dynamic currents are also present at the REF pin during the conversion phase and very good decoupling is critical to achieve optimum performance. The inductance between the reference capacitor and the REF pin is kept less than 2 nH by placing the capacitor within 0.1-inches from the pin and connecting it with 20-mil traces and multiple 15-mil grounding vias, as shown in Figure 77. A single, 10-μF, X7R-grade, 0805-size, ceramic capacitor with at least a 10-V rating is recommended for good performance over the rated temperature range. Avoid using additional lower value capacitors because the interactions between multiple capacitors may affect the ADC performance at higher sampling rates. A small, 0.1-Ω to 0.47-Ω, 0603-size resistor placed in series with the reference capacitor (as shown in Figure 77) keeps the overall impedance low and constant, especially at very high frequencies. The fly-wheel RC filters are placed immediately next to the input pins. Among ceramic surface-mount capacitors, COG (NPO) ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes. R AVDD 12.2 Layout Example EF GND DVDD REF 1: REF Positive Input Differential Inputs Negative Input 1PF 1PF DVDD GND 0.1Ot 0.47O AVDD 10PF GND 47O 10: DVDD 2: AVDD 9: SDI 47O 3: AINP 8: SCLK 4: AINN 7: SDO 5: GND 6: CONVST GND SDO 47O Figure 77. Recommended Layout 46 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I ADS8881C, ADS8881I www.ti.com SBAS547D – MAY 2013 – REVISED AUGUST 2015 13 Device and Documentation Support 13.1 Documentation Support 13.1.1 Related Documentation • TIPD112 Verified Design Reference Guide: Data Acquisition for MUX and Step Inputs, 18-Bit, 1-μs, Full-Scale Response Reference Design, TIDU012 • TIPD113 Verified Design Reference Guide: Data Acquisition for 10-kHz AC, 35-mW, 18-Bit, 1-MSPS Reference Design, SLAU513 • TIPD114 Verified Design Reference Guide: Data Acquisition at 1-kHz AC, 1-mW, 18-Bit, 1-MSPS Reference Design, SLAU514 • TIPD115 Verified Design Reference Guide: Data Acquisition Optimized for Lowest Distortion, Lowest Noise, 18-Bit, 1-MSPS Reference Design, SLAU515 • TIPD116 Verified Design Reference Guide: Data Acquisition Block for ECG Systems, Discrete LEAD I ECG Implementation Reference Design, SLAU516 • OPA313 Data Sheet, SBOS649 • OPA333, OPA2333 Data Sheet, SBOS351 • OPA350 Data Sheet, SBOS099 • THS4521 Data Sheet, SBOS458 • THS4281 Data Sheet, SLOS432 • Precision Hub: – Using SAR ADC TINA Models: Static behavior, power scaling – Using SAR ADC TINA Models: Much ado about settling – SAR ADC Response Times: Respond quickly, control quickly – Input Considerations for SAR ADCs 13.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 7. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ADS8881C Click here Click here Click here Click here Click here ADS8881I Click here Click here Click here Click here Click here 13.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.4 Trademarks E2E is a trademark of Texas Instruments. TINA is a trademark of Texas Instruments Inc.. SPI is a trademark of Motorola Inc. All other trademarks are the property of their respective owners. Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I Submit Documentation Feedback 47 ADS8881C, ADS8881I SBAS547D – MAY 2013 – REVISED AUGUST 2015 www.ti.com 13.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 13.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 48 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS8881C ADS8881I PACKAGE OPTION ADDENDUM www.ti.com 4-Aug-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADS8881CDGS ACTIVE VSSOP DGS 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 8881C ADS8881CDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 8881C ADS8881CDRCR ACTIVE VSON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 8881C ADS8881CDRCT ACTIVE VSON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 8881C ADS8881IDGS ACTIVE VSSOP DGS 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 8881 ADS8881IDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 8881 ADS8881IDRCR ACTIVE VSON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 8881 ADS8881IDRCT ACTIVE VSON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 8881 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 4-Aug-2015 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Aug-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8881CDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8881CDRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS8881CDRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS8881IDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8881IDRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS8881IDRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Aug-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8881CDGSR VSSOP DGS 10 2500 367.0 367.0 35.0 ADS8881CDRCR VSON DRC 10 3000 367.0 367.0 35.0 ADS8881CDRCT VSON DRC 10 250 210.0 185.0 35.0 ADS8881IDGSR VSSOP DGS 10 2500 367.0 367.0 35.0 ADS8881IDRCR VSON DRC 10 3000 367.0 367.0 35.0 ADS8881IDRCT VSON DRC 10 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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