TI1 LMH6655MM/NOPB Lmh6654, lmh6655 single and dual low power, 250 mhz, low noise amplifier Datasheet

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LMH6654, LMH6655
SNOS956E – JUNE 2001 – REVISED AUGUST 2014
LMH6654, LMH6655 Single and Dual Low Power, 250 MHz, Low Noise Amplifiers
1 Features
3 Description
•
The LMH6654 and LMH6655 single and dual high
speed voltage feedback amplifiers are designed to
have unity-gain stable operation with a bandwidth of
250 MHz. They operate from ±2.5 V to ±6 V and each
channel consumes only 4.5 mA. The amplifiers
feature very low voltage noise and wide output swing
to maximize signal-to-noise ratio, and possess a true
single supply capability with input common mode
voltage range extending 150 mV below negative rail
and within 1.3 V of the positive rail. The high speed
and low power combination of the LMH6654 and
LMH6655 make these products an ideal choice for
many portable, high speed applications where power
is at a premium.
1
•
•
•
•
•
•
•
•
•
•
(VS = ±5 V, TJ = 25 °C, Typical Values Unless
Specified)
Voltage Feedback Architecture
Unity Gain Bandwidth 250 MHz
Supply Voltage Range ±2.5V to ±6V
Slew Rate 200 V/µsec
Supply Current 4.5 mA/channel
Input Common Mode Voltage −5.15V to +3.7V
Output Voltage Swing (RL = 100 Ω) −3.6V to 3.4V
Input Voltage Noise 4.5 nV/√Hz
Input Current Noise 1.7 pA/√Hz
Settling Time to 0.01% 25 ns
2 Applications
•
•
•
•
•
•
ADC Drivers
Consumer Video
Active Filters
Pulse Delay Circuits
xDSL Receiver
Pre-amps
The LMH6654 and LMH6655 are built on TI’s
Advance VIP10™ (Vertically Integrated PNP)
complementary bipolar process.
The LMH6654 is packaged in 5-Pin SOT-23 and 8Pin SOIC. The LMH6655 is packaged in 8-Pin
VSSOP (DGK) and 8-Pin SOIC.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMH6654
SOIC (8)
4.90 mm x 3.91 mm
LMH6654
SOT-23 (5)
2.90 mm x 1.60 mm
LMH6655
SOIC (8)
4.90 mm x 3.91 mm
LMH6655
VSSOP (8)
3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Figure 1. Input Voltage and Curernt Noise vs.
Frequency (Vs= ±5V)
100
10
en
10
in
1
100
1k
100k
10k
FREQUENCY (Hz)
1M
INPUT CURRENT NOISE (pA/ Hz)
INPUT VOLTAGE NOISE (nV/ Hz)
100
1
10M
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH6654, LMH6655
SNOS956E – JUNE 2001 – REVISED AUGUST 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
7
9
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
±5V Electrical Characteristics ...................................
5V Electrical Characteristics .....................................
Typical Characteristics ..............................................
7
Application and Implementation ........................ 16
7.1 Application Information............................................ 16
7.2 Typical Application .................................................. 16
8
Power Supply Recommendations...................... 20
9
Layout ................................................................... 20
8.1 Power Dissipation ................................................... 20
9.1 Layout Guidelines ................................................... 20
10 Device and Documentation Support ................. 21
10.1 Documentation Support ........................................ 21
10.2 Electrostatic Discharge Caution ............................ 21
10.3 Glossary ................................................................ 21
11 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2013) to Revision E
Page
•
Changed data sheet structure and organization. Added, updated, or renamed the following sections: Device
Information Table, Application and Implementation; Power Supply Recommendations; Device and Documentation
Support; Mechanical, Packaging, and Ordering Information. Deleted Switching Characteristics due to redundancy. ......... 1
•
Changed from Junction Temperature Range to "Operating Temperature Range" ................................................................ 4
•
Deleted TJ = 25°C................................................................................................................................................................... 5
•
Deleted TJ = 25°C .................................................................................................................................................................. 7
Changes from Revision C (March 2013) to Revision D
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 19
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SNOS956E – JUNE 2001 – REVISED AUGUST 2014
5 Pin Configuration and Functions
5-Pin (LMH6654)
Package DBV
Top View
8-Pin (LMH6654)
Package D
Top View
5
1
OUTPUT
V
1
+
8-Pin (LMH6655)
SOIC and VSSOP (DGK)
Top View
8
N/C
1
N/C
8
+
V
OUT A
A
-IN
V
-
2
7
-
+
V
2
-
+
7
-IN A
2
+
+IN
-
3
6
+
OUT B
OUTPUT
3
6
+IN A
+IN
4
3
-IN
-
4
+
N/C
V
V
-
-IN B
B
5
4
5
+IN B
Pin Functions
PIN
NAME
LMH6654
LMH6655
I/O
DESCRIPTION
DBV
D
DGK
-IN
4
2
I
Inverting Input
+IN
3
3
I
Non-inverting Input
-IN A
2
I
ChA Inverting Input
+IN A
3
I
ChA Non-inverting Input
-IN B
6
I
ChB Inverting Input
I
ChB Non-inverting Input
+IN B
5
N/C
1, 5, 8
OUT A
OUT B
––
No Connection
1
O
ChA Output
7
O
ChB Output
O
Output
OUTPUT
1
6
V-
2
4
4
I
Negative Supply
V+
5
7
8
I
Positive Supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VIN Differential
Output Short Circuit Duration
See
Voltage at Input pins
Soldering Information
(1)
(2)
(3)
UNIT
±1.2
V
(2)
Supply Voltage (V+ − V−)
Junction Temperature
MAX
(3)
13.2
V
V+ +0.5
V- -0.5
V
150
°C
Infrared or Convection (20 sec.)
235
°C
Wave Soldering (10 sec.)
260
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature
at 150°C.
The maximum power dissipation is a function of TJ(MAX), RθJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) − TA)/RθJA. All numbers apply for packages soldered directly onto a PC board.
6.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
(2)
(3)
Electrostatic discharge (1)
MIN
MAX
UNIT
−65
150
°C
Human body model (HBM),
per ANSI/ESDA/JEDEC JS-001, all pins (2)
2000
Machine model (MM) (3)
200
V
Human body model, 1.5 kΩ in series with 100 pF. Machine model: 0Ω in series with 100 pF.
JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions (1)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Supply Voltage (V+ - V−)
±2.5
±6.0
V
Operating Temperature Range
−40
85
°C
(1)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Table.
6.4 Thermal Information
THERMAL METRIC (1)
RθJA
(1)
4
Junction-to-ambient thermal resistance
SOIC (D)
VSSOP (DGK)
SOT-23 (D)
8 PINS
8 PINS
5 PINS
172
235
265
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SNOS956E – JUNE 2001 – REVISED AUGUST 2014
6.5 ±5V Electrical Characteristics
Unless otherwise specified, all limits ensured for V+ = +5V, V− = −5V, VCM = 0V, AV = +1, RF = 25Ω for gain = +1, RF = 402Ω
for gain ≥ +2, and RL = 100Ω. Boldface limits apply at the temperature extremes.
PARAMETER
TEST CONDITIONS
MIN (1)
TYP (2)
MAX (1)
UNIT
DYNAMIC PERFORMANCE
fCL
Close Loop Bandwidth
GBWP
φm
AV = +1
250
AV = +2
130
AV = +5
52
AV = +10
26
Gain Bandwidth Product
AV ≥ +5
Bandwidth for 0.1 dB Flatness
AV +1
Phase Margin
(3)
AV = +1, VIN = 2 VPP
MHz
260
MHz
18
MHz
50
deg
200
V/µs
25
ns
SR
Slew Rate
tS
Settling Time
0.01%
15
ns
tr
Rise Time
AV = +1, 0.2V Step
1.4
ns
tf
Fall Time
AV = +1, 0.2V Step
1.2
ns
AV = +1, 2V Step
0.1%
DISTORTION and NOISE RESPONSE
en
Input Referred Voltage Noise
f ≥ 0.1 MHz
4.5
nV/√Hz
in
Input-Referred Current Noise
f ≥ 0.1 MHz
1.7
pA/√Hz
Second Harmonic Distortion
AV = +1, f = 5 MHz
−80
Third Harmonic Distortion
VO = 2 VPP, RL = 100Ω
−85
Xt
Crosstalk (for LMH6655 only)
Input Referred, 5 MHz,
Channel-to-Channel
−80
DG
Differential Gain
AV = +2, NTSC, RL = 150Ω
0.01%
DP
Differential Phase
AV = +2, NTSC, RL = 150Ω
0.025
dBc
dB
deg
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
VCM = 0V
TC VOS
Input Offset Average Drift
VCM = 0V
IB
Input Bias Current
VCM = 0V
IOS
Input Offset Current
VCM = 0V
RIN
Input Resistance
−3
−4
(4)
±1
3
4
6
−1
−2
Common Mode
mV
µV/°C
5
12
18
µA
0.3
1
2
µA
4
MΩ
Differential Mode
20
kΩ
Common Mode
1.8
CIN
Input Capacitance
CMRR
Common Mode Rejection Ration
Input Referred,
VCM = 0V to −5V
CMVR
Input Common- Mode Voltage Range
CMRR ≥ 50 dB
Differential Mode
pF
1
70
68
90
−5.15
3.5
3.7
60
58
67
dB
−5.0
V
TRANSFER CHARACTERISTICS
AVOL
(1)
(2)
(3)
(4)
VO = 4 VPP, RL = 100Ω
Large Signal Voltage Gain
dB
All limits are specified by testing or statistical analysis.
Typical Values represent the most likely parametric norm.
Slew rate is the slower of the rising and falling slew rates. Slew rate is rate of change from 10% to 90% of output voltage step.
Offset voltage average drift is determined by dividing the change in VOS at temperature extremes into the total temperature change.
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±5V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for V+ = +5V, V− = −5V, VCM = 0V, AV = +1, RF = 25Ω for gain = +1, RF = 402Ω
for gain ≥ +2, and RL = 100Ω. Boldface limits apply at the temperature extremes.
PARAMETER
TEST CONDITIONS
MIN (1)
TYP (2)
3.4
3.2
3.6
MAX (1)
UNIT
OUTPUT CHARACTERISTICS
VO
ISC
Output Swing High
No Load
Output Swing Low
No Load
Output Swing High
RL = 100Ω
Output Swing Low
RL = 100Ω
Short Circuit Current
IOUT
Output Current
RO
Output Resistance
(5)
−3.9
3.2
3.0
V
3.4
−3.6
Sourcing, VO = 0V
ΔVIN = 200 mV
145
130
280
Sinking, VO = 0V
ΔVIN = 200 mV
100
80
185
Sourcing, VO = +3V
−3.7
−3.5
−3.4
−3.2
mA
80
Sinking, VO = −3V
120
AV = +1, f <100 kHz
0.08
mA
Ω
POWER SUPPLY
PSRR
Power Supply Rejection Ratio
IS
Supply Current (per channel)
(5)
6
Input Referred,
VS = ±5V to ±6V
60
dB
76
4.5
6
7
mA
Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature
at 150°C.
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6.6 5V Electrical Characteristics
Unless otherwise specified, all limits ensured for V+ = +5V, V− = −0V, VCM = 2.5V, AV = +1, RF = 25 Ω for gain = +1,
RF = 402Ω for gain ≥ +2, and RL = 100Ω to V+/2. Boldface limits apply at the temperature extremes.
PARAMETER
TEST CONDITIONS
MIN (1)
TYP (2)
MAX (1)
UNIT
DYNAMIC PERFORMANCE
fCL
Close Loop Bandwidth
GBWP
φm
AV = +1
230
AV = +2
120
AV = +5
50
AV = +10
25
MHz
Gain Bandwidth Product
AV ≥ +5
250
MHz
Bandwidth for 0.1 dB Flatness
AV = +1
17
MHz
48
deg
190
V/µs
Phase Margin
(3)
SR
Slew Rate
tS
Settling Time
0.01%
AV = +1, VIN = 2 VPP
20
ns
tr
Rise Time
AV = +1, 0.2V Step
1.5
ns
tf
Fall Time
AV = +1, 0.2V Step
1.35
ns
ns
30
AV = +1, 2V Step
0.1%
DISTORTION and NOISE RESPONSE
en
Input Referred Voltage Noise
f ≥ 0.1 MHz
4.5
nV/√Hz
in
Input Referred Current Noise
f ≥ 0.1 MHz
1.7
pA/√Hz
Second Harmonic Distortion
AV = +1, f = 5 MHz
−65
Third Harmonic Distortion
VO = 2 VPP, RL = 100Ω
−70
Crosstalk (for LMH6655 only)
Input Referred, 5 MHz
−78
Xt
dBc
dB
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
TC VOS
−5
−6.5
VCM = 2.5V
Input Offset Average Drift
VCM = 2.5V
IB
Input Bias Current
VCM = 2.5V
IOS
Input Offset Current
VCM = 2.5V
RIN
Input Resistance
(4)
Input Capacitance
CMRR
Common Mode Rejection Ration
CMVR
Input Common Mode Voltage Range
5
6.5
6
−2
−3
Common Mode
CIN
±2
mV
µV/°C
6
12
18
µA
0.5
2
3
µA
4
MΩ
Differential Mode
20
kΩ
Common Mode
1.8
Differential Mode
Input Referred,
VCM = 0V to −2.5V
pF
1
70
68
CMRR ≥ 50 dB
90
−0.15
3.5
3.7
58
55
64
dB
0
V
TRANSFER CHARACTERISTICS
AVOL
(1)
(2)
(3)
(4)
VO = 1.6 VPP, RL = 100Ω
Large Signal Voltage Gain
dB
All limits are specified by testing or statistical analysis.
Typical Values represent the most likely parametric norm.
Slew rate is the slower of the rising and falling slew rates. Slew rate is rate of change from 10% to 90% of output voltage step.
Offset voltage average drift is determined by dividing the change in VOS at temperature extremes into the total temperature change.
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5V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for V+ = +5V, V− = −0V, VCM = 2.5V, AV = +1, RF = 25 Ω for gain = +1,
RF = 402Ω for gain ≥ +2, and RL = 100Ω to V+/2. Boldface limits apply at the temperature extremes.
PARAMETER
TEST CONDITIONS
MIN (1)
TYP (2)
3.6
3.4
3.75
MAX (1)
UNIT
OUTPUT CHARACTERISTICS
VO
ISC
Output Swing High
No Load
Output Swing Low
No Load
Output Swing High
RL = 100Ω
Output Swing Low
RL = 100Ω
Short Circuit Current
IOUT
Output Current
RO
Output Resistance
(5)
0.9
3.5
3.35
1.1
1.3
V
3.70
1
Sourcing , VO = 2.5V
ΔVIN = 200 mV
90
80
170
Sinking, VO = 2.5V
ΔVIN = 200 mV
70
60
140
1.3
1.45
mA
Sourcing, VO = +3.5V
30
Sinking, VO = 1.5V
60
AV = +1, f <100 kHz
.08
mA
Ω
POWER SUPPLY
PSRR
Power Supply Rejection Ratio
IS
Supply Current (per channel)
(5)
8
Input Referred ,
VS = ± 2.5V to ± 3V
60
dB
75
4.5
6
7
mA
Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature
at 150°C.
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6.7 Typical Characteristics
4
9
2
6
0
3
-2
0
-4
-3
GAIN (dB)
GAIN (dB)
25°C, V+ = ±5 V, V− = −5, RF = 25 Ω for gain = +1, RF = 402 Ω for gain ≥ +2 and RL = 100 Ω, unless otherwise specified.
VS = ±2.5V
-6
-8
VS = ±5V
-10
-9
-15
-14
-18
10M
100M
FREQUENCY (Hz)
-21
1M
1G
Figure 2. Closed Loop Bandwidth (G = +1)
VS = ±5V
10M
100M
FREQUENCY (Hz)
1G
Figure 3. Closed Loop Bandwidth (G = +2)
25
24
20
19
VS = ±5V
14
9
10
4
5
-1
-6
VS = ±2.5V
-11
0
-5
-10
-16
-15
-21
-20
-26
1M
10M
100M
FREQUENCY (dB)
VS = ±5V
15
GAIN (dB)
GAIN (dB)
VS = ±2.5V
-12
-12
-16
1M
-25
1M
1G
Figure 4. Closed Loop Bandwidth (G = +5)
VS = ±2.5V
1G
10M
100M
FREQUENCY (Hz)
Figure 5. Closed Loop Bandwidth (G = +10)
5.0
5
4.9
4.9
85°C
4.8
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
-6
4.7
4.6
4.5
4.4
25°C
4.3
-40°C
4.8
4.7
VS = ±5V
4.6
4.5
4.4
4.2
4.3
4.1
4.2
20 40 60
-60 -40 -20 0
TEMPERATURE (°C)
4
5
6
7
8
9
10
SUPPLY VOLTAGE (V)
11
12
Figure 6. Supply Current per Channel
vs. Supply Voltage
VS = 5V
80
100
Figure 7. Supply Current per Channel
vs. Temperature
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Typical Characteristics (continued)
25°C, V+ = ±5 V, V− = −5, RF = 25 Ω for gain = +1, RF = 402 Ω for gain ≥ +2 and RL = 100 Ω, unless otherwise specified.
0
0
-0.2
-0.1
VS = ±5V
-40°C
-40°C
-0.2
VOS (mV)
-0.6
85°C
-0.8
25°C
-0.3
85°C
-0.4
25°C
-0.5
-1
-0.6
-1.2
4
5
6
7
8
9
VSUPPLY (V)
10
11
0
12
2
3
4
5
VCM (V)
6
7
8
Figure 9. Offset Voltage
vs. Common Mode
Figure 8. Offset Voltage
vs. Supply Voltage (VCM = 0V)
0
7
VS = ±2.5V
IBIAS
INPUT BIAS CURRENT (µA)
-0.1
-0.2
-0.3
VOS (mV)
1
-0.4
-40°C
-0.5
-0.6
25°C
-0.7
-0.8
85°C
6
OFFSET VOLTAGE (mV)
VOS (mV)
-0.4
5
4
3
2
VOS
1
-0.9
-1
0
0.5
1
1.5
2
2.5
3
3.5
0
-50
0
50
100
TEMPERATURE (°C)
VCM (V)
Figure 11. Bias Current and Offset Voltage
vs. Temperature
Figure 10. Offset Voltage
vs. Common Mode
7
-40°C
VS = 5V
6
POSITIVE IBIAS (µA)
25°C
5
4
85°C
3
2
1
0
-1
0
0.5
1
1.5
2
2.5
3
3.5
VCM (V)
Figure 13. Bias Current
vs. Common Mode Voltage
Figure 12. Bias Current
vs. Common Mode Voltage
10
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Typical Characteristics (continued)
25°C, V+ = ±5 V, V− = −5, RF = 25 Ω for gain = +1, RF = 402 Ω for gain ≥ +2 and RL = 100 Ω, unless otherwise specified.
INPUT
110
100
(1 V/div)
CMRR
90
PSRR
80
OUTPUT
AoL, PSRR, AND CMRR (dB)
120
70
AoL @ ±5V
60
-50
AoL @ 5V
0
50
100
TIME (12.5 ns/div)
TEMPERATURE (°C)
OUTPUT
OUTPUT
(1 V/div)
(1 V/div)
INPUT
INPUT
Figure 14. AOL, PSRR and CMRR
vs. Temperature
Figure 15. Inverting Large Signal Pulse Response
(VS = 5V)
TIME (12.5 ns/div)
TIME (12.5 ns/div)
Figure 17. Non-Inverting Large Signal Pulse Response
(VS = 5V)
OUTPUT
OUTPUT
(1 V/div)
(100 mV/div)
INPUT
INPUT
Figure 16. Inverting Large Signal Pulse Response
(VS = ±5V)
TIME (12.5 ns/div)
TIME (12.5 ns/div)
Figure 18. Non-Inverting Large Signal Pulse Response
(VS = ±5V)
Figure 19. Non-Inverting Small Signal Pulse Response
(VS = 5V)
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Typical Characteristics (continued)
OUTPUT
OUTPUT
(100 mV/div)
(100 mV/div)
INPUT
INPUT
25°C, V+ = ±5 V, V− = −5, RF = 25 Ω for gain = +1, RF = 402 Ω for gain ≥ +2 and RL = 100 Ω, unless otherwise specified.
TIME (12.5 ns/div)
TIME (12.5 ns/div)
Figure 21. Inverting Small Signal Pulse Response
(VS = 5V)
OUTPUT
(100 mV/div)
INPUT VOLTAGE NOISE (nV/ Hz)
INPUT
100
100
10
en
10
in
1
100
1k
100k
10k
FREQUENCY (Hz)
1M
INPUT CURRENT NOISE (pA/ Hz)
Figure 20. Non-Inverting Small Signal Pulse Response
(VS = ±5V)
1
10M
TIME (12.5 ns/div)
Figure 22. Inverting Small Signal Pulse Response
(VS = ±5V)
100
en
10
in
1
100
1k
100k
10k
FREQUENCY (Hz)
1M
1
10M
HARMONIC DISTORTION (dBc)
10
-30
INPUT CURRENT NOISE (pA/ Hz)
INPUT VOLTAGE NOISE (nV/ Hz)
100
Figure 23. Input Voltage and Current Noise
vs. Frequency (VS = 5V)
-40
-50
-60
3RD
-70
2ND
-80
-90
-100
-110
0.1
Figure 24. Input Voltage and Current Noise
vs. Frequency (VS = ±5V)
12
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1
10
100
FREQUENCY (MHz)
Figure 25. Harmonic Distortion
vs. Frequency
G = +1, VO = 2 VPP, VS = 5V
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Typical Characteristics (continued)
-30
-60
-40
-65
HARMONIC DISTORTION (dBc)
HARMONIC DISTORTION (dBc)
25°C, V+ = ±5 V, V− = −5, RF = 25 Ω for gain = +1, RF = 402 Ω for gain ≥ +2 and RL = 100 Ω, unless otherwise specified.
-50
-60
-70
-80
3RD
-90
2ND
-100
-110
0.1
1
10
2ND
-70
-75
-80
3RD
-85
-90
-95
-100
20 40 60
-60 -40 -20 0
TEMPERATURE (°C)
100
FREQUENCY (MHz)
80
100
Figure 27. Harmonic Distortion
vs. Temperature
VS = 5V, f = 5 MHz, VO = 2 VPP
Figure 26. Harmonic Distortion
vs. Frequency
G = +1, VO = 2 VPP, VS = ±5V
-45
-60
HARMONIC DISTORTION (dBc)
HARMONIC DISTORTION (dBc)
2ND
-65
-70
-75
3RD
-80
-85
2ND
-90
-50
-55
-60
-65
-70
3RD
-75
-80
-85
-90
-95
-95
-100
20 40 60
-60 -40 -20 0
TEMPERATURE (°C)
1
80
2
3
4
100
5
6
7
8
9
10
GAIN (V/V)
Figure 29. Harmonic Distortion
vs. Gain
VS = 5V, f = 5 MHz, VO = 2 VPP
Figure 28. Harmonic Distortion
vs. Temperature
VS = ±5V, f = 5 MHz, VO = 2 VPP
-45
-30
HARMONIC DISTORTION (dBc)
HARMONIC DISTORTION (dBc)
-50
2ND
-55
-60
-65
-70
-75
-80
3RD
-85
-90
-95
1
2
3
4
5
6
7
8
9
10
-40
-50
2ND
-60
-70
-80
3RD
-90
-100
0.0
0.5
1.0
1.5
2.0
2.5
GAIN (V/V)
OUTPUT SWING (VPP)
Figure 30. Harmonic Distortion
vs. Gain
VS = ±5V, f = 5 MHz, VO = 2 VPP
Figure 31. Harmonic Distortion
vs. Output Swing
(G = +2, VS = 5V, f = 5 MHz)
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Typical Characteristics (continued)
25°C, V+ = ±5 V, V− = −5, RF = 25 Ω for gain = +1, RF = 402 Ω for gain ≥ +2 and RL = 100 Ω, unless otherwise specified.
100
-30
NEGATIVE
80
-50
70
PSRR (dB)
HARMONIC DISTORTION (dBc)
90
-40
2ND
-60
-70
60
POSITIVE
50
40
30
-80
3RD
20
-90
10
0
10
-100
0
1
2
3
4
5
6
7
8
100
10k
1k
100k
1M
10M
OUTPUT SWING (VPP)
FREQUENCY (Hz)
Figure 32. Harmonic Distortion
vs. Output Swing
(G = +2, VS = ±5V, f = 5 MHz)
Figure 33. PSRR vs. Frequency
5
120
VOUT REFERENCED TO V (V)
VS = ±5V
4
-
100
CMRR (dB)
80
60
40
20
0
10
3
2
VS = 5V
1
VS = ±5V
100
1k
10k 100k
FREQUENCY
1M
0
.01
10M
0.1
1
10
1
k
100
OUTPUT SINKING CURRENT (mA)
Figure 34. CMRR vs. Frequency
Figure 35. Output Sinking Current
-20
VS = 5V
-30
CROSSTALK REJECTION (dB)
+
VOUT REFERENCED TO V (V)
5
4
3
VS = ±5V
2
1
VS = 5V
0
.01
0.1
1
10
100
-40
-50
-60
-70
-80
-90
-100
-110
1
k
-120
100k
OUTPUT SOURCING CURRENT (mA)
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100M
Figure 37. CrossTalk
vs. Frequency (LMH6655 only)
Figure 36. Output Sourcing Current
14
10M
1M
FREQUENCY (Hz)
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SNOS956E – JUNE 2001 – REVISED AUGUST 2014
Typical Characteristics (continued)
25°C, V+ = ±5 V, V− = −5, RF = 25 Ω for gain = +1, RF = 402 Ω for gain ≥ +2 and RL = 100 Ω, unless otherwise specified.
-20
100
VS = ±5V
ISOLATION RESISTANCE, RISO (:)
CROSSTALK REJECTION (dB)
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
100k
25:
90
+
80
×
70
RISO
CL
1 k:
60
50
40
30
20
10
0
10M
1M
FREQUENCY (Hz)
100M
0
10 20 30 40 50 60 70 80 90 100
CAPACITIVE LOAD, CL (pF)
Figure 38. CrossTalk
vs. Frequency (LMH6655 only)
Figure 39. Isolation Resistance
vs. Capacitive Load
100
90
80
180
GAIN (dB)
144
60
108
50
72
40
36
30
0
20
-36
GAIN
10
-72
0
-108
-10
-144
-20
1k
PHASE (°)
PHASE
70
-180
10k
100k
1M
10M 100M 500M
FREQUENCY (Hz)
Figure 40. Open Loop Gain and Phase
vs. Frequency
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7 Application and Implementation
7.1 Application Information
The LMH6654 single and LMH6655 dual high speed, voltage feedback amplifiers are manufactured on TI’s new
VIP10™ (Vertically Integrated PNP) complementary bipolar process. These amplifiers can operate from ±2.5 V to
±6 V power supply. They offer low supply current, wide bandwidth, very low voltage noise and large output
swing. Many of the typical performance plots found in the datasheet can be reproduced if 50 Ω coax and 50 Ω
RIN/ROUT resistors are used.
7.2 Typical Application
7.2.1 Design Requirements
7.2.1.1 Components Selection and Feedback Resistor
It is important in high-speed applications to keep all component leads short since wires are inductive at high
frequency. For discrete components, choose carbon composition axially leaded resistors and micro type
capacitors. Surface mount components are preferred over discrete components for minimum inductive effect.
Never use wire wound type resistors in high frequency applications.
Large values of feedback resistors can couple with parasitic capacitance and cause undesired effects such as
ringing or oscillation in high-speed amplifiers. Keep resistors as low as possible consistent with output loading
consideration. For a gain of 2 and higher, 402 Ω feedback resistor used for the typical performance plots gives
optimal performance. For unity gain follower, a 25 Ω feedback resistor is recommended rather than a direct short.
This effectively reduces the Q of what would otherwise be a parasitic inductance (the feedback wire) into the
parasitic capacitance at the inverting input.
7.2.2 Detailed Design Procedure
7.2.2.1 Driving Capacitive Loads
Capacitive loads decrease the phase margin of all op amps. The output impedance of a feedback amplifier
becomes inductive at high frequencies, creating a resonant circuit when the load is capacitive. This can lead to
overshoot, ringing and oscillation. To eliminate oscillation or reduce ringing, an isolation resistor can be placed as
shown in Figure 41 below. At frequencies above
1
F=
2 S RISO CLOAD
(1)
the load impedance of the Amplifier approaches RISO. The desired performance depends on the value of the
isolation resistor. The isolation resistance vs. capacitance load graph in the typical performance characteristics
provides the means for selection of the value of RS that provides ≤ 3 dB peaking in closed loop AV = 1 response.
In general, the bigger the isolation resistor, the more damped the pulse response becomes. For initial evaluation,
a 50Ω isolation resistor is recommended.
25:
-
RISO
VOUT
VIN
+
Figure 41. Isolation Resistor Placement
16
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Typical Application (continued)
7.2.2.2 Bias Current Cancellation
In order to cancel the bias current errors of the non-inverting configuration, the parallel combination of the gain
setting Rg and feedback Rf resistors should equal the equivalent source resistance Rseq as defined in Figure 42.
Combining this constraint with the non-inverting gain equation, allows both Rf and Rg to be determined explicitly
from the following equations:
Rf = AVRseq and Rg = Rf/(AV−1)
(2)
For inverting configuration, bias current cancellation is accomplished by placing a resistor Rb on the non-inverting
input equal in value to the resistance seen by the inverting input (Rf//(Rg+Rs). The additional noise contribution of
Rb can be minimized through the use of a shunt capacitor.
Figure 42. Non-Inverting Amplifier Configuration
Figure 43. Inverting Amplifier Configuration
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Typical Application (continued)
7.2.2.3 Total Input Noise vs. Source Resistance
The noise model for the non-inverting amplifier configuration showing all noise sources is described in Figure 44.
In addition to the intrinsic input voltage noise (en) and current noise (in = in+ = in−) sources, there also exits
thermal voltage noise et = 4kTR associated with each of the external resistors. Equation 3 provides the general
form for total equivalent input voltage noise density (eni). Equation 4 is a simplification of Equation 3 that
assumes Rf || Rg = Rseq for bias current cancellation. Figure 45 illustrates the equivalent noise model using this
assumption. The total equivalent output voltage noise (eno) is eni * AV.
Figure 44. Non-Inverting Amplifier Noise Model
eni = en2 + (in+ · RSeq)2 + 4kTRSeq + (in- · (Rf || Rg))2 + 4kT(Rf || Rg)
(3)
Figure 45. Noise Model with Rf || Rg = Rseq
eni =
en2 + 2 (in · RSeq)2 + 4kT (2RSeq)
(4)
If bias current cancellation is not a requirement, then Rf || Rg does not need to equal Rseq. In this case, according
to Equation 3, Rf and Rg should be as low as possible in order to minimize noise. Results similar to Equation 3
are obtained for the inverting configuration on if Rseq is replaced by Rb || Rg is replaced by Rg + Rs. With these
substitutions, Equation 3 will yield an eni referred to the non-inverting input. Referring eni to the inverting input is
easily accomplished by multiplying eni by the ratio of non-inverting to inverting gains.
18
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Typical Application (continued)
7.2.2.3.1 Noise Figure
Noise Figure (NF) is a measure of the noise degradation caused by an amplifier.
Si/Ni
NF = 10LOG
So/No
eni
= 10LOG
2
2
et
(5)
The noise figure formula is shown in Equation 5. The addition of a terminating resistor RT, reduces the external
thermal noise but increases the resulting NF.
The NF is increased because the RT reduces the input signal amplitude thus reducing the input SNR.
en2 + in2 (RSeq + (Rf || Rg))2 + 4KTRSeq + 4kt (Rf || Rg)
4kTRSeq
(6)
The noise figure is related to the equivalent source resistance (Rseq) and the parallel combination of Rf and Rg.
To minimize noise figure, the following steps are recommended:
1. Minimize Rf||Rg
2. Choose the Optimum Rs (ROPT)
ROPT is the point at which the NF curve reaches a minimum and is approximated by:
ROPT ≈ (en/in)
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8 Power Supply Recommendations
8.1 Power Dissipation
The package power dissipation should be taken into account when operating at high ambient temperature and/or
high power dissipative conditions. In determining maximum operable temperature of the device, make sure the
total power dissipation of the device is considered; this power dissipated in the device with a load connected to
the output as well as the nominal dissipation of the op amp.
9 Layout
9.1 Layout Guidelines
With all high frequency devices, board layouts with stray capacitance have a strong influence on the AC
performance. The LMH6654/LMH6655 are not exception and the inverting input and output pins are particularly
sensitive to the coupling of parasitic capacitance to AC ground. Parasitic capacitances on the inverting input and
output nodes to ground could cause frequency response peaking and possible circuit oscillation. Therefore, the
power supply, ground traces and ground plan should be placed away from the inverting input and output pins.
Also, it is very important to keep the parasitic capacitance across the feedback to an absolute minimum.
The PCB should have a ground plane covering all unused portion of the component side of the board to provide
a low impedance path. All trace lengths should be minimized to reduce series inductance.
Supply bypassing is required for the amplifiers performance. The bypass capacitors provide a low impedance
return current path at the supply pins. They also provide high frequency filtering on the power supply traces. It is
recommended that a ceramic decoupling capacitor 0.1 µF chip should be placed with one end connected to the
ground plane and the other side as close as possible to the power pins. An additional 10 µF tantalum electrolytic
capacitor should be connected in parallel, to supply current for fast large signal changes at the output.
+
V
10 µF
+
0.1 µF
0.1 µF
+
10 µF
V
-
Figure 46. Supply Bypass Capacitors
9.1.1 Evaluation Boards
TI provides the following evaluation boards as a guide for high frequency layout and as an aid in device testing
and characterization.
20
DEVICE
PACKAGE
EVALULATION BOARD PN
LMH6654MF
5-Pin SOT-23
LMH730216
LMH6654MA
8-Pin SOIC
LMH730227
LMH6655MA
8-Pin SOIC
LMH730036
LMH6655MM
8-Pin VSSOP (DGK)
LMH730123
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SNOS956E – JUNE 2001 – REVISED AUGUST 2014
Components Needed to Evaluate the LMH6654 on the LMH730227 Evaluation Board:
• Rf, Rg use the datasheet to select values.
• RIN, ROUT typically 50 Ω (Refer to the Basic Operation section of the evaluation board datasheet for details)
• Rf is an optional resistor for inverting again configurations (select Rf to yield desired input impedance = Rg||Rf)
• C1, C2 use 0.1 µF ceramic capacitors
• C3, C4 use 10 µF tantalum capacitors
Components not used:
1. C5, C6, C7, C8
2. R1 thru R8
The evaluation boards are designed to accommodate dual supplies. The board can be modified to provide single
operation. For best performance;
1) Do not connect the unused supply.
2) Ground the unused supply pin.
10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
10.1.1.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LMH6654
Click here
Click here
Click here
Click here
Click here
LMH6655
Click here
Click here
Click here
Click here
Click here
10.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
10.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2001–2014, Texas Instruments Incorporated
Product Folder Links: LMH6654 LMH6655
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21
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jan-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMH6654MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMH66
54MA
LMH6654MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMH66
54MA
LMH6654MF
NRND
SOT-23
DBV
5
1000
TBD
Call TI
Call TI
-40 to 85
LMH6654MF/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
A66A
LMH6654MFX/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
A66A
LMH6655MA
NRND
SOIC
D
8
95
TBD
Call TI
Call TI
-40 to 85
LMH6655MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMH66
55MA
LMH6655MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMH66
55MA
LMH6655MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
A67A
LMH6655MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
A67A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jan-2016
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Jan-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMH6654MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMH6654MF/NOPB
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMH6654MFX/NOPB
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMH6655MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMH6655MM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Jan-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMH6654MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMH6654MF/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LMH6654MFX/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LMH6655MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMH6655MM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
Pack Materials-Page 2
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