4:1 Differential-to-LVDS Clock Multiplexer ICS854S054I DATA SHEET General Description Features The ICS854S054I is a 4:1 Differential-to-LVDS Clock Multiplexer which can operate up to 2.5GHz. The ICS854S054I has 4 selectable differential clock inputs. The PCLK, nPCLK input pairs can accept LVPECL, LVDS or CML levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The select pins have internal pulldown resistors. The SEL1 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects PCLK0, nPCLK0). • • • • High speed 4:1 differential multiplexer • • Maximum output frequency: 2.5GHz • • • • • • Additive phase jitter, RMS: 0.147ps (typical) One differential LVDS output pair Four selectable differential PCLK, nPCLK input pairs PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx input Part-to-part skew: 300ps (maximum) Propagation delay: 700ps (maximum) Supply voltage range: 3.135V to 3.465V -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram PCLK0 nPCLK0 PCLK1 nPCLK1 Pin Assignment PCLK0 nPCLK0 PCLK1 nPCLK1 VDD SEL0 SEL1 GND Pulldown Pullup/Pulldown 00 (default) PCLK2 PCLK3 nPCLK3 16 15 14 13 12 11 10 9 VDD Q nQ GND nPCLK3 PCLK3 nPCLK2 PCLK2 Pulldown Pullup/Pulldown ICS854S054I 01 Q nPCLK2 1 2 3 4 5 6 7 8 Pulldown Pullup/Pulldown nQ 10 16-Lead TSSOP 5.0mm x 4.4mm x 0.92mm package body G Package Top View Pulldown Pullup/Pulldown SEL1 SEL0 11 Pulldown Pulldown ICS854S054AGI REVISION A SEPTEMBER 28, 2012 1 ©2012 Integrated Device Technology, Inc. ICS854S054I Data Sheet 4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER Table 1. Pin Descriptions Number Name 1 PCLK0 Input Type Pulldown Non-inverting differential clock input. Description 2 nPCLK0 Input Pullup/ Pulldown Inverting differential clock input. VDD/2 default when left floating. 3 PCLK1 Input Pulldown Non-inverting differential clock input. 4 nPCLK1 Input Pullup/ Pulldown Inverting differential clock input. VDD/2 default when left floating. 5, 16 VDD Power 6, 7 SEL0, SEL1 Input Pulldown Clock select input pins. LVCMOS/LVTTL interface levels. 9 PCLK2 Input Pulldown Non-inverting differential clock input. Inverting differential clock input. VDD/2 default when left floating. Positive supply pins. 10 nPCLK2 Input Pullup/ Pulldown 11 PCLK3 Input Pulldown Non-inverting differential clock input. Pullup/ Pulldown Inverting differential clock input. VDD/2 default when left floating. 12 nPCLK3 Input 8, 13 GND Power Power supply ground. 14, 15 nQ, Q Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 2 pF RPULLDOWN Pulldown Resistor 75 kΩ RVDD/2 RPullup/Pulldown Resistor 50 kΩ Table 3. Clock Input Function Table Inputs Outputs SEL1 SEL0 Q nQ 0 0 PCLK0 nPCLK0 0 1 PCLK1 nPCLK1 1 0 PCLK2 nPCLK2 1 1 PCLK3 nPCLK3 ICS854S054AGI REVISION A SEPTEMBER 28, 2012 2 ©2012 Integrated Device Technology, Inc. ICS854S054I Data Sheet 4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 100°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions VDD Positive Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 57 68 mA Typical Maximum Units Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum VIH Input High Voltage 2.2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current SEL[1:0] VDD = VIN = 3.465V 150 µA IIL Input Low Current SEL[1:0] VDD = 3.465V, VIN = 0V -10 µA Table 4C. Differential LVPECL Input DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage VCMR Common Mode Input Voltage; NOTE 1 Minimum Typical Maximum Units 150 µA PCLK[0:3], nPCLK[0:3] VDD = VIN = 3.465V PCLK[0:3] VDD = 3.465V, VIN = 0V -10 µA nPCLK[0:3] VDD = 3.465V, VIN = 0V -150 µA 0.15 1.2 V GND + 1.2 VDD V NOTE 1: Common mode input voltage is defined as VIH. ICS854S054AGI REVISION A SEPTEMBER 28, 2012 3 ©2012 Integrated Device Technology, Inc. ICS854S054I Data Sheet 4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER Table 4D. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage ∆VOD VOD Magnitude Change VOS Offset Voltage ∆VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 247 380 454 mV 50 mV 1.375 V 50 mV 1.125 1.28 AC Electrical Characteristics Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency tPD Propagation Delay; NOTE 1 tjit(Ø) Buffer Additive Phase Jitter, RMS; Refer to Additive Phase Jitter Section tsk(pp) Part-to-Part Skew; NOTE 2, 3 tsk(i) Input Skew tR / tF Output Rise/Fall Time MUXISOLATION MUX Isolation; NOTE 4 Test Conditions Minimum Typical Maximum Units 2.5 GHz 295 470 700 ps 155.52MHz, Integration Range: 12kHz – 20MHz 20% to 80% 155.52MHz, VPP = 800mV 0.147 70 ps 300 ps 10 50 ps 150 250 ps 86 dB NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured ≤ 1.0GHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Q, nQ output measured differentially. See Parameter Measurement Information for MUX Isolation diagram. ICS854S054AGI REVISION A SEPTEMBER 28, 2012 4 ©2012 Integrated Device Technology, Inc. ICS854S054I Data Sheet 4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio SSB Phase Noise dBc/Hz of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Offset from Carrier Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is ICS854S054AGI REVISION A SEPTEMBER 28, 2012 shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. Measured using a Rohde & Schwarz SMA100 as the input source. 5 ©2012 Integrated Device Technology, Inc. ICS854S054I Data Sheet 4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER Parameter Measurement Information VDD SCOPE Qx VDD 3.3V±5% POWER SUPPLY + Float GND – nPCLK[0:3] V Cross Points PP V CMR PCLK[0:3] nQx GND Differential Input Level 3.3V Output Load AC Test Circuit Par t 1 nPCLK[0:3] nQ PCLK[0:3] Q nQ nQ Par t 2 Q Q tPD tsk(pp) Part-to-Part Skew Propagation Delay nPCLKx Spectrum of Output Signal Q PCLKx MUX selects active input clock signal Amplitude (dB) A0 nPCLKy PCLKy nQ MUX_ISOL = A0 – A1 MUX selects static input A1 Q tPD2 tPD1 ƒ (fundamental) tsk(i) Frequency tsk(i) = |tPD1 - tPD2| MUX Isolation Input Skew ICS854S054AGI REVISION A SEPTEMBER 28, 2012 6 ©2012 Integrated Device Technology, Inc. ICS854S054I Data Sheet 4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER Parameter Measurement Information, continued VDD nQ 80% 80% out VOD 20% 20% Q DC Input LVDS 100 tF tR out Differential Output Voltage Setup Output Rise/Fall Time VDD out DC Input LVDS out VOS/∆ VOS ä Offset Voltage Setup ICS854S054AGI REVISION A SEPTEMBER 28, 2012 7 ©2012 Integrated Device Technology, Inc. ICS854S054I Data Sheet 4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER Applications Information Recommendations for Unused Input Pins Inputs: PCLK/nPCLK Inputs For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from PCLK to ground. Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage V1= VCC/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1 in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set V1 at 1.25V. The values below are for when both the single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50Ω applications, R3 and R4 can be 100Ω. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. VCC VCC Ro VCC R3 100 RS R1 1K Zo = 50 Ohm + V1 Driver R4 Ro + Rs = Zo VCC Receiv er - 100 C1 0.1uF R2 1K Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS854S054AGI REVISION A SEPTEMBER 28, 2012 8 ©2012 Integrated Device Technology, Inc. ICS854S054I Data Sheet 4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER 3.3V LVPECL Clock Input Interface The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, LVDS, CML and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the PCLK/nPCLK input driven by the most common driver types. 3.3V 3.3V 3.3V 3.3V 3.3V R1 50Ω Zo = 50Ω R2 50Ω Zo = 50Ω PCLK R1 100Ω PCLK Zo = 50Ω nPCLK Zo = 50Ω nPCLK LVPECL Input CML LVPECL Input CML Built-In Pullup Figure 2B. PCLK/nPCLK Input Driven by a Built-In Pullup CML Driver Figure 2A. PCLK/nPCLK Input Driven by a CML Driver 3.3V 3.3V 3.3V 3.3V R3 125Ω 3.3V 3.3V R4 125Ω Zo = 50Ω R3 84 3.3V LVPECL Zo = 50Ω C1 Zo = 50Ω C2 R4 84 PCLK PCLK Zo = 50Ω nPCLK nPCLK LVPECL Input LVPECL R1 84Ω R2 84Ω R5 100 - 200 R6 100 - 200 R1 125 R2 125 LVPECL Input Figure 2D. PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver with AC Couple Figure 2C. PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V Zo = 50Ω PCLK R1 100Ω Zo = 50Ω nPCLK LVDS LVPECL Input Figure 2E. PCLK/nPCLK Input Driven by a 3.3V LVDS Driver ICS854S054AGI REVISION A SEPTEMBER 28, 2012 9 ©2012 Integrated Device Technology, Inc. ICS854S054I Data Sheet 4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90Ω and 132Ω. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100Ω parallel resistor at the receiver and a 100Ω differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The LVDS Driver standard termination schematic as shown in Figure 3A can be used with either type of output structure. Figure 3B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output. ZO ≈ ZT ZT LVDS Receiver Figure 3A. Standard Termination LVDS Driver ZO ≈ ZT C ZT 2 LVDS ZT Receiver 2 Figure 3B. Optional Termination LVDS Termination ICS854S054AGI REVISION A SEPTEMBER 28, 2012 10 ©2012 Integrated Device Technology, Inc. ICS854S054I Data Sheet 4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER LVDS Power Considerations This section provides information on power dissipation and junction temperature for the ICS854S054I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS854S054I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 68mA = 235.62mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 100°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.236W * 100°C/W = 108.6°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance θJA for 16 Lead TSSOP, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS854S054AGI REVISION A SEPTEMBER 28, 2012 0 1 2.5 100°C/W 94.2°C/W 90.2°C/W 11 ©2012 Integrated Device Technology, Inc. ICS854S054I Data Sheet 4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER Reliability Information Table 7. θJA vs. Air Flow Table for a 16 Lead TSSOP θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 100°C/W 94.2°C/W 90.2°C/W Transistor Count The transistor count for ICS854S054I is: 450 This device is pin and function compatible, and a suggested replacement for ICS854054I. Package Outline and Package Dimensions Package Outline - G Suffix for 16 Lead TSSOP Table 8. Package Dimensions Symbol N A A1 A2 b c D E E1 e L α aaa All Dimensions in Millimeters Minimum Maximum 16 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.10 6.40 Basic 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS854S054AGI REVISION A SEPTEMBER 28, 2012 12 ©2012 Integrated Device Technology, Inc. ICS854S054I Data Sheet 4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER Ordering Information Table 9. Ordering Information Part/Order Number 854S054AGILF 854S054AGILFT Marking 4S054AIL 4S054AIL ICS854S054AGI REVISION A SEPTEMBER 28, 2012 Package “Lead-Free” 16 Lead TSSOP “Lead-Free” 16 Lead TSSOP 13 Shipping Packaging Tube Tape & Reel Temperature -40°C to 85°C -40°C to 85°C ©2012 Integrated Device Technology, Inc. ICS854S054I Data Sheet 4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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