www.fairchildsemi.com FAN5231 Precision Dual PWM Controller And Linear Regulator for Notebook CPUs Features • Provides 3 Regulated Voltages – Microprocessor core (SpeedStep™-enabled) – Microprocessor I/O – Microprocessor Clock Generator • High Efficiency Over Wide Load Range • Not Dissipative Current-Sense Scheme – Uses MOSFET’s R DS(ON) – Optional Current-Sense Resistor for Precision Overcurrent • Adaptive Dead Time Drivers for N-Channel MOSFETs • Operates from +5V, +3.3V and Battery (5.6-24V) Inputs • Precision Core Voltage Control: – Remote “Kelvin” Sensing – Summing Current-Mode Control – On-Chip Mode-Compensated “Droop” for Optimum Transient Response and Lower Processor Power Dissipation • TTL-Compatible 5-Bit Digital Output Voltage Selection – Wide Range - 0.925VDC to 1.3VDC in 25mV Steps, and from 1.3VDC to 2.0VDC in 50mV Steps – Programmable “On-the-Fly” VID code change with customer programmable slew rate and 100ms settling time • Power-Good Output Voltage Monitor • No negative Core and I/O voltage on turn-off • Over-Voltage, Under-Voltage and Over-Current Fault Monitors • 300kHz Fixed Switching Frequency • Thermal Shut-Down Applications • Converters for Mobile Dual-Mode CPUs • Web Tablets • Internet Appliances +V IN V OUT2 I/ O +V IN 3.3V V OUT3 CPU CLK PWM 2 PWM 1 CONTROLLER CONTROLLER V OUT1 CORE LI NEAR VI D CODE REGULATOR FAN5231 Figure 1. Simplified Power System Diagram REV. 1.1.1 8/15/01 FAN5231 Description feedback-loop compensation that dramatically reduces the number of external components. At nominal loads PWM controllers operate at fixed frequency 300kHz. At light loads when the filter inductor current becomes discontinuous, controllers operate in a hysteretic mode. The out-of-phase operation of two PWM controllers reduces input current ripple in both modes of operation. The linear regulator uses an internal pass device to provide 2.5V for the CPU clock generator. The FAN5231 is a highly integrated power controller, which provides a complete power management solution for mobile CPUs. The IC integrates two PWM controllers and a linear regulator as well as monitoring and protection circuitry into a single 28-lead plastic SSOP package. The two PWM controllers regulate the microprocessor core and I/O voltages with synchronous-rectified buck converters, while the linear regulator powers the CPU clock. The FAN5231 monitors all the output voltages. A single Power-Good signal is issued when soft start is completed and all outputs are within ±10% of their respective set points. A built-in over-voltage protection for the core and I/O outputs forces the lower MOSFETs on to prevent output voltages from going above 115% of their settings. Under-voltage protection latches the chip off when any of the three outputs drops below 75% of the set value. The PWM controller's overcurrent circuitry monitors the output current by sensing the voltage drop across the lower MOSFETs. If precision overcurrent protection is required, an external current-sense resistor may be used. The FAN5231 includes 5-bit digital-to-analog converter (DAC) that adjusts the core PWM output voltage from 0.925VDC to 2.0VDC and conforms to the Intel Mobile VID specification. The DAC setting may be changed during operation to accommodate Dual-Mode processors. Special measures are taken to provide such a transition with controlled rate in a specified 100 µs. A precision reference, remote sensing, and a proprietary architecture with integrated processor mode-compensated "droop" provide excellent static and dynamic core voltage regulation. The second PWM controller has a fixed 1.5V output voltage and powers the I/O circuitry. Both PWM controllers have integrated Block Diagram EN VBATT VCC GND LI NEAR REGULA TOR V3I N BOOT1 HGDR1 HI FL OGON FFBK 1 - RAM P 2 + VOUT3 CLK RAMP 1 UGATE1 SHUTOFF POWER-ON PHASE1 - + RESET (POR) GATE L OGI C 1 0.9V CLK 2 CLK1 GATE CONTROL FCCM DEADT VCC PWM /HYST BOOT2 PWM ON HYST ON UGATE2 LO HI OC COMP1 FL OGON SHUTOFF + - PWM ON - HYST ON EA1 DYNAM I C DUTY CYCLE CLAMP FFBK 1 - + D Q R < Q + - DYNA MI C DUTY CYCLE CLAMP + - LG ATE2 R1=20k ISEN2 LG ATE2 + PHASE1 ∑ + 0.9V MO DE CONTROL COMP 2 OVP1 OUTPUT VOLTAGE MO NIT OR OVP2 R1= 20k LG ATE1 - ISEN1 FCCM TTL DAC REFERENCE SOFT START MO DE CONTROL LO GI C 1 PGOOD 2 PHASE1 DACOUT VCC PWM LATCH 2 OC LOGI C2 VRET1 + - - - + 2.8V EA2 + + LG ATE1 OC COM P2 MO DE CONTROL LO GI C 1 VSEN1 FAST FEEDBACK COMP 1 + HY ST COM P2 CLK2 + - ∑ + LO OVP2 CLK 1 DAC OUT PRE AM P + LG DR2 PGND2 + Q D R Q < DEADT PWM /HYST VCC - - OC LOGI C1 PGND1 HY ST COM P1 + VCC PWM LATCH 1 GATE LOGI C 2 GATE CONTROL VSEN2 LG ATE1 OVP1 HGDR2 PHASE2 LG ATE2 LGDR1 VI D4 SOFT VI D0 VI D2 VI D1 VI D3 REV. 1.1.1 8/15/01 FAN5231 Pinout LG ATE2 1 PGND2 2 28 VCC 27 LGATE1 BOOT2 3 26 PGND1 UGATE2 4 25 BOOT1 5 24 UGATE1 ISEN2 6 23 PHASE1 PHASE2 VI D4 7 22 ISEN1 VI D3 8 21 PGOOD VI D2 9 20 EN VI D1 10 19 VI N VI D0 11 18 SOFT VSEN2 12 17 VSEN1 V3I N 13 16 VRET1 VOUT3 14 15 GND Absolute Maximum Ratings Parameter Min. Max. Units Supply Voltage, VCC + 6.5 V Input Voltage, Vin + 29.0 V V3in + 6.5 V PHASE1,2 + 29.0 V BOOT1,2 + 29.0 V BOOT1,2 with respect to PHASE1,2 + 6.5 V PGOOD, RT/FAULT, and GATE Voltage GND - 0.3 VCC + 0.3 V Core Output or I/O Voltage GND - 0.3 + 6.5 V ESD Classification Class 2 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Recommended Operating Conditions Parameter Min. Supply Voltage, VCC Input Voltage, Vin +7.5 V3in Max. Units +5.0 ±5% V 22.0 V +3.3 ±10% V Ambient Temperature Range -20 85 °C Junction Temperature Range -20 125 °C Min. Max. Units θJA (°C/W) Thermal Information Parameter Thermal Resistance (Typical, Note 1) QSOP Package 55 QSOP Package (with 3 in2 of copper) TBD Maximum Junction Temperature (Plastic Package) 150 °C 150 °C 300 °C Maximum Storage Temperature Range -65 Maximum Lead Temperature (Soldering 10s) (QSOP - Lead Tips Only) Note 1. θJA is measured with the component mounted on an evaluation PC board in free air. REV. 1.1.1 8/15/01 3 FAN5231 Electrical Specifications (Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3) Parameter Symbol Test Condition Min. Typ. Max Units VCC Supply Nominal Supply Current ICC Shut-down Supply Current GATE1, GATE2 Open – 2 2.5 mA ICCS – 30 50 µA Battery Pin Supply Current IVIN – – 100 µA Battery Pin Leakage Current at Shut-Down IVINSD – – 5 µA Rising VCC Threshold 4.3 4.5 4.6 V Falling VCC Threshold 3.9 4.1 4.3 V 255 300 345 kHz – 2 – V – 0.5 – V VID0-VID4 Input Low Voltage – – 0.8 V VID0-VID4 Input High Voltage 2.0 – – V – 1 – µA -1.0 – +1.0 % Power-On Reset Oscillator Free Running Frequency Ramp Amplitude, pk-pk Vbat = 16V Ramp Offset Reference, DAC and Soft Start VID0-VID4 Pull-up Current to VCC DAC Voltage Accuracy Measured at pin 18 Soft-Start Current During Start-Up ISS VSS = 0V…0.9V 18 27 36 µA Soft-Start Current During Mode Change ISSM VSS = 0.925V…2.0V 350 500 650 µA Enable Voltage Low VENLOW IC Inhibited – – 0.8 V Enable Voltage High VENHIGH IC Enabled Input has internal pull-up current source 2µA typ 2.0 – – V VOUT1 Defined by the current VID code (Table 1) 0.925 – 2.0 V -2.0 – +2.0 % 70 75 80 % – 1.4 – µs 110 115 120 % – 2.4 – µs 100 135 170 µA Enable PWM 1 Converter Output Voltage Static Load Regulation 100mA < IVOUT1 < 15.0A Under-Voltage Shut-Down Level VUV1 Under-Voltage Shut Down Delay TDOC1 Over-Voltage VOVP1 Over-Voltage Shut Down Delay TDOV1 Over-Current Comparator Threshold IOC1 Percent of the voltage set by VID code. Disabled during dynamic VID code change. Percent of the voltage set by VID code. PWM 2 Converter Output Voltage Load Regulation 4 VOUT2 1.5 100mA < IVOUT3 < 2.1A -2.0 – V +2.0 % REV. 1.1.1 8/15/01 FAN5231 Electrical Specifications (Continued) (Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3) Parameter Symbol Test Condition Min. Typ. Max Units Under-Voltage Shut-Down Level VUV2 1.05 – 1.20 V Under-Voltage Shut Down Delay TDOC2 – 1.4 – µs Over-Voltage Shut-Down VOVP2 1.65 – 1.80 V Over-Voltage Shut Down Delay TDOV2 – 2.4 – µs Over-Current Comparator Threshold IOC2 100 135 170 µA Linear Regulator Output Voltage VOUT3 2.5 10mA < IVOUT3 < 150mA Load Regulation -2.0 – V 2.0 % Under-Voltage Shut-Down Level VUV3 1.8 – 2.0 % Current Limit IOC3 190 250 340 mA By design – 86 – dB PWM Controller Error Amplifiers DC Gain Gain-Bandwidth Product GBWP By design – 2.7 – MHz Slew Rate SR By design – 1 – V/µs PWM 1 Controller Gate Drivers Upper Drive Pull-Up Resistance R1UGPUP – 6 8 Ω Upper Drive Pull-Down Resistance R1UGPDN – 3 5 Ω Lower Drive Pull-Up Resistance R1LGPUP – 6 8 Ω Lower Drive Pull-Down Resistance R1LGPDN – 0.8 1.5 Ω Upper Drive Pull-Up Resistance R2UGPUP – 12 20 Ω Upper Drive Pull-Down Resistance R2UGPDN – 6 10 Ω Lower Drive Pull-Up Resistance R2LGPUP – 10 20 Ω Lower Drive Pull-Down Resistance R2LGPDN – 6 10 Ω PWM 2 Controller Gate Drivers Power Good VOUT1 Upper Threshold Percent of the voltage defined by the VID code 108 – 114 % VOUT1 Lower Threshold, Falling Edge Percent of the voltage defined by the VID code 85 – 92 % VOUT1 Lower Threshold, Risisng Edge Percent of the voltage defined by the VID code 87 – 94 % VOUT2 Upper Threshold 1.60 – 1.75 V VOUT2 Lower Threshold 1.30 – 1.45 V VOUT3 Upper Threshold 2.65 – 2.85 V VOUT3 Lower Threshold 2.15 – 2.35 V PGOOD Voltage Low VPGOOD IPGOOD = -1.6mA – – 0.4 V PGOOD Leakage Current IPGlLKG VPULLUP = 5.0V – – 1.0 µA REV. 1.1.1 8/15/01 5 FAN5231 Functional Pin Description VOUT3 (Pin 14) VID0, VID1, VID2, VID3, VID4 (Pins 11, 10, 9, 8 and 7 respectively) Output of the 2.5V linear regulator. Supplies current up to 150mA. The output current on this pin is internally limited to 250mA. VID0-VID4 are the input pins to the 5-bit DAC. The states of these five pins program the internal voltage reference (DACOUT). The level of DACOUT sets the core converter output voltage (VOUT1). It also sets the core PGOOD, UVP and OVP thresholds. VSEN1, VRTN1 (Pins 17 and 16) These pins are connected to the core converter’s output voltage to provide remote sensing. The PGOOD, UVP and OVP comparators use this pins for protection. BOOT1, BOOT2 (Pins 25 and 3) SOFT (Pin 18) These pins provide power to the upper MOSFET drivers of the core and I/O converters. Connect these pins to their respective junctions of the bootstrap capacitors and the cathodes of the bootstrap diodes. The anodes of the bootstrap diodes are connected to pin 28, VCC. Connect a capacitor from this pin to the ground. This capacitor (typically 0.1mF), along with an internal 25µA current source, sets the soft-start interval of the converter. When voltage on this pin exceeds 0.9V, the soft start is completed. After the soft-start is completed, the pin function is changed. The internal circuit regulates voltage on this pin to the value commanded by VID code. The pin now has 500µA source/ sink capability that allows to set desired slew rate for upward and downward VID code changes. PHASE1, PHASE2 (Pins 23 and 5) The PHASE nodes are the junction points of the upper MOSFET sources, output filter inductors, and lower MOSFET drains. Connect the PHASE pins to the respective PWM converter’s upper MOSFET source. VIN (Pin 19) ISEN1, ISEN2 (Pins 22 and 6) VIN provides battery voltage to the oscillator for feed-forward rejection of input voltage variations. These pins are used to monitor the voltage drop across the lower MOSFETs for current feedback, output voltage droop and over-current protection. For precise current detection these inputs could be connected to optional current sense resistors placed in series with sources of the lower MOSFETs. To set the gain of the current sense amplifier, a resistor should be placed in series with each of these inputs. UGATE1, UGATE2 (Pins 24 and 4) These pins provide the gate drive for the upper MOSFETs. LGATE1, LGATE 2 (Pin 27 and 1) These pins provide the gate drive for the lower MOSFETs. PGND1, PGND2 (Pin 26 and 2) These are the power ground connection for the core and I/O converters, respectively. Tie each lower MOSFET source to the corresponding pin. VSEN2 (Pin 12) This pin is connected to the I/O output and provides voltage feedback to the I/O error amplifier. The PGOOD, UVP and OVP comparators use this signal. V3IN (Pin 13) This pin provides input power for the 2.5V linear regulator. The typical input voltage for that pin is 3.3V. Alternatively, 5.0V system rail can be used while efficiency will be proportionally lower. 6 EN (Pin 20) This pin enables IC operation when left open or pulled-up to VCC. Also, it unlatches the chip after fault when being cycled. PGOOD (Pin 21) PGOOD is an open drain output used to indicate the status of the PWM converters’ output voltages. This pin is pulled low when the core output is not within ±10% of the DACOUT reference voltage, or when any of the other outputs are not within their respective under-voltage and over-voltage thresholds. The PGOOD output is pulled low for “01111” and ‘11111’ VID code. See Table 1. GND (Pin 15) Signal ground for the IC. All voltage levels are measured with respect to this pin. VCC (Pin 28) Supplies all the power necessary to operate the chip. The IC starts to operate when the voltage on this pin exceeds 4.5V and shuts down when the voltage on this pin drops below 4.0V. REV. 1.1.1 8/15/01 FAN5231 Description Operation Overview The FAN5231 three-in-one power mangement integrated circuit provides complete power solution for modern processors for notebook and sub-notebook PCs. The IC controls operation of two synchronous buck converters and one linear regulator. The output voltage of the core converter can be adjusted in the range from 0.925V to 2.0 by changing the DAC code settings (see Table 1). The output voltage of the I/O converter is fixed to 1.5V. The internal linear regulator provides fixed 2.5V for the CPU clock generator from the system +3.3V bus. The output voltage of the core converter can be changed on-the-fly with programable slew rate, which makes it especially suitable for the processors that feature modern power savings techniques as SpeedStep™ or PowerNow!™ . In this mode SOFT has both sourcing and sinking capabilities to maintain voltage across the soft-start capacitor conforming to the VID code. This dual slope approach helps to provide safe rise of voltages and currents in the converters during initial start-up and at the same time sets a controlled speed of the core voltage change when the processor commands to do so. Soft-start circuits for the I/O converter is slaved to the core output soft-start circuit and they complete their ramp-up when voltage on the SOFT pin reaches 0.9V. 1 Both, core and I/O converters can operate in two modes: fixed frequency PWM and variable frequency hysteretic depending on the load level. At loads lower than the critical where filter inductor current becomes discontinuous, hysteretic mode of operation is activated. Switchover from PWM to hysteretic operation at light loads improves the converters' efficiency and prolongs battery run time. In hysteretic mode, comparators are synchronized to the main clock that allows seamless transition between the operational modes and reduced channel-to-channel interaction. As the filter inductor resumes continuous current, the PWM mode of operation is restored. The core converter incorporates a proprietary output voltage droop circuit for optimum handling of the fast load transients found in modern processors. The droop is compensated for the processor mode changes, which allows for relatively equal droop in any operation mode and to specify the droop as a fraction of the VID set voltage. Initialization The FAN5231 initializes upon receipt of input power assuming EN is high or not connected. The Power-On Reset (POR) function continually monitors the input supply voltage on the VCC pin and initiates soft-start operation after input supply voltage exceeds 4.5V. Should this voltage drop lower than 4.0V, POR disables the chip. 2 3 4 (1) Ch1 VCPU 500mV (2) Ch2 VIO 500mV (4) Ch4 VEN 5.0V (3) Ch3 VCLK 1.0V M1.00ms VIN = 20V Figure 2. Initial Startup The value of the soft-start capacitor can be estimated by the following equation: ∆Issm Css = ----------------- ∆t ∆Vdac For the typical conditions when ∆Vdac = 0.25V, ∆t = 100µs 500µA Css = ----------------100µs ≈ 0.2µF 0.25V With this value of the soft-start capacitor, soft start time will be equal to: 0.2µF • 0.9V Tss = -------------------------------- = 7.2ms 25µA Soft-Start When soft start is initiated, the voltage on the SOFT pin starts to ramp gradually due to the 25µA current sourced into the external capacitor. When SOFT-pin voltage reaches 0.9V, the value of the sourcing current rapidly changes to 500µA charging the soft-start capacitor to the level determined by the DAC. This completes the soft start sequence, Fig. 2. As long as the SOFT voltage is above 0.9V, the maximum value of the internal soft-start current is set to 500µA allowing fast rate-of-change in the core output voltage due to a VID code change. REV. 1.1.1 8/15/01 OUT1 Voltage Program This output of PWM1 converter is designated to supply the microprocessor core voltage. The OUT1 voltage is programmed to discrete levels between 0.925VDC and 2.0VDC as specified in Table 1. The voltage identification (VID) pins program an internal voltage reference (DAC) through a TTL-compatible 5-bit digital-to-analog converter. The level of the DAC voltage also sets the PGOOD, UVP and OVP thresholds. The VID pins can be left open for a logic 1 input due to an internal 1µA pull-up to Vcc. 7 FAN5231 VID4 VID3 VID2 VID1 VID0 Nominal OUT1 Voltage 0 0 0 0 0 2.00 0 0 0 0 1 1.95 0 0 0 1 0 1.90 applied to the inverting input of the PWM comparator. To provide output voltage droop for enhanced dynamic load regulation, a signal proportional to the output current is added to the voltage feedback signal. This feedback scheme in conjunction with a PWM ramp proportional to the input voltage allows for fast and stable loop response over a wide range of input voltage and output current variations. For the sake of efficiency and maximum simplicity, the current sense signal is derived from the voltage drop across the lower MOSFET during its conduction time. 0 0 0 1 1 1.85 Mode-Compensated Droop 0 0 1 0 0 1.80 0 0 1 0 1 1.75 0 0 1 1 0 1.70 0 0 1 1 1 1.65 0 1 0 0 0 1.60 0 1 0 0 1 1.55 0 1 0 1 0 1.50 0 1 0 1 1 1.45 0 1 1 0 0 1.40 An output voltage "droop" or an active voltage positioning is now widely used in the computer power applications. The technique is based on raising the converter voltage at light load in anticipation of the possible load current step. Conversely, the output voltage is lowered at high load in anticipation of possible load drop. The output voltage varies with the load like it is a resistor connected in series with the converter’s output. When done as part of the feedback in a closed loop, the "droop" is not associated with substantial power losses, though. There is no such resistor in a real circuit, but rather the feature is emulated by the feedback. 0 1 1 0 1 1.35 0 1 1 1 0 1.30 0 1 1 1 1 No CPU* 1 0 0 0 0 1.275 1 0 0 0 1 1.250 1 0 0 1 0 1.225 1 0 0 1 1 1.200 1 0 1 0 0 1.175 1 0 1 0 1 1.150 1 0 1 1 0 1.125 1 0 1 1 1 1.100 1 1 0 0 0 1.075 1 1 0 0 1 1.050 1 1 0 1 0 1.025 1 1 0 1 1 1.000 1 1 1 0 0 0.975 1 1 1 0 1 0.950 0 1 1 1 1 0 0.925 Figure 3. Mode-Compensated Droop 1 1 1 1 1 No CPU* When powering the dual mode processor, it is desired to have an adequate "droop" (equal fractions of the programmed output voltage) in both performance and batteryoptimized modes of operation. The traditional "droop" is normally tuned to the worse case load, which is associated with the performance mode. In the battery optimized mode, the CPU operating voltage and the clock frequency are both scaled down. Due to the constant gain in the current loop, the traditional "droop" compensates only for the operating voltage change. The degree of the droop achieved in this case is The ‘11111’ and ‘0111‘VID codes, as shown in Table 1, shut the IC down and set PGOOD low. Table 1. Pin Name Note: 1. 0 = connected to GND or VSS, 1 = open or connected to 3.3V through pull-up resistors. Core Converter PWM Operation At the nominal current core converter operates in a fixed frequency PWM mode. The output voltage is compared with a reference voltage set by the DAC. The derived error signal is amplified by an internally compensated error amplifier and 8 The "droop" allows a reduction in size and cost of the output capacitors required to handle the transient. Additionally to that, the CPU power dissipation is also slightly reduced as it is proportional to the applied voltage squared and even slight voltage decrease translates in a measurable reduction in power dissipated. VCPU Performance Mode 1.6 Battery-Optimized Mode Traditional Droop 1.35 Mode-Compensated Droop 5 10 I CPU REV. 1.1.1 8/15/01 FAN5231 not the same because the CPU current is significantly lower as it is illustrated by the following equaton. VCPU =1.00V 1 ICPU = KCPU • VCPUi • FCPUi • KF; Where, KCPU — is a processor constant; VCPUi — is processor operating voltage; FCPUi — is processor clock frequency; KF — is a coefficient that varies from 0 to 1 and indicates how heavily processor is engaged by the software; i — is a denominator associated with the processor mode of operation (performance or battery optimized). I CPU =0.3A>>12.0A 2 VCPU =1.6V 1 Ch1 50mV Ch2 5.0A M50µs Figure 6. To accommodate the droop the output voltage of core converter is raised 2% at no load conditions. The resistor connected to ISEN1 pin programs the amount of droop. I MAX ⋅ R DS ( ON ) R CS = -------------------------------------75µA I CPU =0.3A>>18A 2 Ch1 50mV Ch2 5.0A M50µs This resistor sets the gain in the current feedback loop. The droop is scaled to 5.5% of the VID code when current into ISEN1 pin equals 75µA. Figure 4. This leads to deterioration of the droop benefits in the battery-optimized mode where they are mostly appreciable, Fig. 3. Feedback Loop Compensation Due to implemented average current mode control, the modulator has a single pole response with -1 slope at frequency determined by load VCPU =1.35V 1 The output voltage waveforms with droop subjected to load step are shown on Fig. 4–Fig. 6 . 1 F PO = ---------------------------- ’ 2π ⋅ R 0 ⋅ C 0 where Ro – is load resistance, Co – is load capacitance. For this type of modulator Type 2 compensation circuit is usually sufficient. To reduce number of external components and remove the burden at determining compensation components from a system designer, both PWM controllers have internally compensated error amplifiers. I CPU = 0.3A>>13 . 5A 2 Ch1 50mV Ch2 5.0A M50µs Figure 5. The FAN5231 incorporates a new proprietary droop technique specially designed for the SpeedStep-enabled converters and provides mode-compensated, relatively equal droop in both, the performance and the battery-optimized modes. The droop is set as a fraction of the VID programmed voltage and the gain in the current loop is different for each VID combination, those providing the droop, which is compensated for the voltage and the frequency changes associated with the different CPU modes of operation. REV. 1.1.1 8/15/01 Figure 7 shows Type 2 amplifier and its response along with responses of current mode modulator and the converter. The Type 2 amplifier, in addition to the pole at origin, has a zeropole pair that causes a flat gain region at frequencies in between the zero and the pole. 1 F Z = ---------------------------- = 6kHz ; 2π ⋅ R 2 ⋅ C 1 1 F P = ---------------------------- = 600kHz ; 2π ⋅ R 2 ⋅ C 1 9 FAN5231 This region is also associated with phase ‘bump’ or reduced phase shift. The amount of phase shift reduction depends on how wide the region of flat gain is and has a maximum value of 90 degrees. To further simplify the converter compensation, the modulator gain is kept independent of the input voltage variation by providing feed-forward of VIN to the oscillator ramp. Converter R2 C2 C1 ation. The low level — corresponds to the discontinuous mode of operation. When the low level on the comparator output is detected eight times in a row, the mode control flipflop is set and converter is commanded to operate in the hysteretic mode. If during this pulse counting process the comparator's output happens to be high, the counter of the delay circuit will be reset and circuit will continue to monitor for eight low level pulses in a row from the very beginning, Fig. 8. VOUT t R1 EA Type 2 EA GEA=18dB Modulator IIN D GEA=14dB FZ FPO t FP FC PHASE COMP 1 Figure 7. The zero frequency, the amplifier high-frequency gain and the modulator gain are chosen to satisfy most of typical applications. The crossover frequency will appear at the point where the modulator attenuation equals the amplifier high frequency gain. The only task that the system designer has to complete is to specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero frequency. With this type of compensation plenty of phase margin is easily achieved due to zero-pole pair phase ‘boost’. Conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. In this case, the ESR zero placed within 10kHz...50kHz range gives some additional phase ‘boost’. Fortunately, there is an opposite trend in mobile applications to keep the output capacitor as small as possible. Automatic Operation Mode Control The mode control circuit changes the converter’s mode of operation depending on the level of the load current. At nominal current converter operates in a fixed frequency PWM mode. When the load current drops lower than the critical value, inductor current becomes discontinuous and the operation mode is changed to hysteretic. MO DE OF OPERATI ON 2 3 4 5 6 t 7 8 Hysteretic PWM t Figure 8. PWM to Hysteretic Transistion VOUT t IIN D 1 2 3 4 5 t 6 7 8 PHASE COMP t MODE OF OPERATION Hysteretic PWM t Figure 9. Hysteretic to PWM Transistion The circuit which restores normal PWM operation mode works in the same way and is looking for eight in a row high level pulses on the comparator's output. If during this counting process the comparator’s output happens to be low, the counter will be reset and the mode control flip-flop will not change the state. The operation mode will only be changed when eight pulses in a row fill the counter, Fig 9. This technique prevents jitter and chatter of the operation mode control logic at the load levels close to the critical. Hysteretic Operation The mode control circuit consists of a flip-flop whose outputs provide HYST and NORMAL signals. These signals inhibit normal PWM operation and activate hysteretic comparator and diode emulation mode of the synchronous MOSFET. The inputs of the flip-flop are controlled by the outputs of two delay circuits that constantly monitor output of the phase node comparator. High level on the comparator output during PWM cycle is associated with continuous mode of oper10 When the discontinuous inductor current is detected, the mode control logic changes the way the signals in the chip are processed by entering the hysteretic mode. The comparator and the error amplifier that provide control in the PWM mode are inhibited and hysteretic comparators are now activated. Changes are also made to the gate logic. The synchronous rectifier MOSFET is now controlled in the diode emulation mode, hence the controlled conduction in the second quadrant is prohibited. REV. 1.1.1 8/15/01 FAN5231 The converter output voltage is applied to the negative input of the hysteretic comparator. The voltage on the reference input of the hysteretic comparator is the DAC output voltage with a small addition of the clock frequency pulses. Synchronization of the upper MOSFET turn-on pulses with the main clock positively contributes to the seamless transition between the operation modes. A sustained overload on any output latches-off all the converters and sets the PGOOD pin low. The chip operation can be restored by cycling VCC voltage or EN pin. V IO 1 Operation During Processor Mode Changes The PWM1 controller is specially designed to provide “on the fly” automatic core voltage changes required by some advanced processors for mobile applications. Dual core voltage and operation frequency scaling allows for significant power savings without sacrificing system performance in battery operation mode. I IO 2 As processor mode changes can happen when chip is in PWM or hysteretic mode, measures were taken to provide equally fast response to these changes. As soon as a DAC code change is received, the chip is switched into the forced PWM mode for about 150ms regardless of the load level. Operating the controller in the synhronous PWM mode allows faster output voltage transitions especially when a downward output voltage change is commanded. Ch1 50mV Ch2 500mA M50µs Figure 10. I/O Converter Load Transient in PWM Mode V IO 1 I/O Converter Architecture The I/O converter architecture is close to the one of the core converter. It has the same mode control logic and can operate in a costant frequency PWM mode or in the hysteretic mode depending on the load level, but its structure is much simpler mainly because of absense of the differential input amlifier and the DAC. This controller is synchronized to the same clock as the core converter, but out-of phase. Those, some reduction of the input current ripple is achieved. Gate Control Logic The gate control logic translates generated PWM signals into the MOSFETs gate drive signals providing necessary amplification, level shift and shoot-trough protection. Also, it incorporates functions that help to optimize the IC performance over a wide range of operating conditions. As MOSFET switching time can very dramatically from type to type and with input voltage variation, gate control logic provides adaptive dead time by monitoring gate voltages of both upper and lower MOSFETs. Output Voltage Adjustment The output voltage of the I/O converter can be increased by as much as 10% by inserting a resistor divider in the feedback line. I IO 2 Ch1 50mV Ch2 500mA M50µs Figure 11. I/O Converter Load Transient with Mode Change Over-Current Protection Both PWM controllers use the lower MOSFET’s on-resistance — rDS(ON) to monitor the current for protection against shorted outputs. The sensed voltage drop after amplification is compared with an internally set threshold. Several scenarios of the current protection circuit behavior are possible. If load step is strong enough to pull output voltage lower than the under-voltage threshold, chip shuts down. If the output voltage sag does not reach the under-voltage threshold but the current exceeds the over-current threshold, the pulse skipping circuit is activated. This breaks the output voltage regulation and limits the current supplied to the load. Fault Protection All three outputs are monitored and protected against extreme overload, short circuit and under-voltage conditions. Both PWM outputs are monitored and protected from overvoltage conditions. Only monitoring functions for over-voltage conditions is incorporated for the linear regulator. REV. 1.1.1 8/15/01 Because of the nature of used current sensing technique, and to accommodate wide range of the rDS(ON) variation, the value of the threshold should represent overload current about 180% of the nominal value. This could lead to the situation where the converter continuously delivers power about two times the nominal without significant drop in the output 11 FAN5231 voltage. To eliminate this, the time delay circuit (8:1 counter which counts the clock cycles) is activated when the overcurrent condition is detected for the first time. If after the delay the overcurrent condition persists, the converter shuts down. If not - normal operation restores. The overcurrent protection circuit trips when the peak value of the lower MOSFET current is higher than the one obtained from the following equation. I th • R CS I OC = ---------------------R DSON temperatures below 125°C trough the full soft-start cycle by either cycling EN or VCC pin. 1.60V CORE 1 1.50V IO 2 2.50VCL K 3 where: RCS — is a resistor from ISEN pin to PHASE pin; Ioc — desired overload current trip level; RDSON - either rDS(ON) of the lower MOSFET, or the value of the optional current sense resistor; Ith - threshold of the current protection circuitry (140uA). In the linear regulator the maximum current of the integrated power device is actively limited to 250mA that eventually creates an under-voltage condition and sets the fault latch. EN 4 Ch1 500mV Ch3 1.0V Ch2 500mV Ch4 5.0V M1 .0ms Figure 12. Shutdown Waveforms Application Guidelines Overvoltage Protection Layout Considerations During operation, severe load dump or a short of an upper MOSFET can cause the output voltage to increase significantly over normal operation range. When the output exceeds the over-voltage threshold of 115% of the DAC voltage (1.7V for PWM2), the over-voltage comparator forces the lower gate driver high and turns the lower MOSFET on. This will pull down the output voltage and eventually blow the battery fuse. As soon as output voltage drops below the threshold, the OVP comparator is disengaged. Switching type of converters even during normal operation produce short pulses of current which could cause substantial ringing and be a source of EMI pollution if layout constrains are not observed. The OVP scheme provides a soft crowbar function and does not interfere with on-the-fly VID code changes. During downward changes in the converter output voltage, the condition when the OVP threshold is set before the new value of the output voltage is reached is quite expectable. Also, it does not invert output voltage when activated, a common problem for OVP schemes with a latch. Overvoltage protection is not provided for the linear regulator. Shutdown When EN (pin 20) is pulled to the ground, chip is disabled and enters a low-current state. Both high-side and low-side gate drivers are turned off. This control scheme produces no negative output voltage at shutdown, Fig. 12. A rising edge on EN clears the fault latch. Thermal Shutdown The chip incorporates an over temperature protection circuit that shuts all the outputs down when the die temperature of 150°C is reached. Normal operation restores at the die 12 There are two sets of critical components in a DC-DC converter. The switching power components processing large amounts of energy at high rate are a source of a noise, and low power components responsible for bias and feedback functions, are mainly recipients of the noise. The situation with the FAN5231 is even more critical as it provides control functions for two independent converters. Poor layout design could lead to cross talk between the converters and result in degraded performance or even malfunction. A multi-layer printed circuit board is recommended. Dedicate one solid layer for a ground plane. Dedicate another solid layer as a power plane and break this plane into smaller island at common voltage levels. Notice all the nodes that are subjected to high dV/dt voltage swing as PHASE1,2 nodes, for example. All surrounding circuitry will tend to couple the noise from this nodes trough stray capacitance. Do not oversize copper traces connected to these nodes. Do not place traces connected to the feedback components adjacent to these traces. Keep the wiring traces from the control IC to the MOSFET gate and source as short as possible and capable to handle peak currents up to 2A. Minimize the area within gatesource path to reduce stray inductance and eliminate parasitic ringing at the gate. REV. 1.1.1 8/15/01 FAN5231 Locate small critical components like soft start capacitor and current sense resistors as close, as possible to the respective pins of the IC. high frequency de coupling for the Pentium Pro processor to be composed of at least fourty 1uF ceramic capacitors in the 1206 surface-mount package. Design Procedure and Component Selection Guidelines Use only specialized low-ESR electrolytic capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor’s ESR will determine the output ripple voltage and the initial voltage drop after a transient. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. As an initial step, define operating voltage range, maximum load current in performance mode, Output Capacitor Selection An output capacitor serves two major functions in a switching power supply. Along with an inductor it filters the sequence of pulses produced by the switcher and supply the load transient currents. The filtering requirements are a function of the switching frequency and the ripple current allowed, and are usually easy to satisfy in high frequency converters. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. Modern microprocessors produce transient load rates in excess of 10A/µs. High frequency ceramic capacitors placed beneath the processor socket initially supply the transient and reduce the slew rate seen by the bulk capacitors. The bulk capacitor values are generally determined by the total allowable ESR rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the processor power pins as physically possible. Consult with the processor manufacturer for specific decoupling requirements. For example, Intel recommends that the Output Inductor Selection The minimum practical output inductor value is the one that keeps inductor current just on the boundary of continuous conduction at some minimum load. The industry standard practice is to choose the minimum current some where from 10% to 25% of the nominal current. At light load, FAN5231 PWM controllers switch to a hysteretic mode of operation to sustain high efficiency operation. It is suggested that transition to the hysteretic mode occurred before inductor current becomes discontinuous. Following equations help to choose proper value of the output filter inductor.. ∆I = 2 ⋅ I min ∆Vout ∆I = ---------------ESR Vin – Vout Vout L = --------------------------- × -----------Fs × ∆I Vin Table 2. Component Circuit 1 Circuit 2 Circuit 3 8.0A 12.0A 18.0A Inductor 2.0µH Panasonic ETQP6F2R0BFA 1.0µH Panasonic ETQP6F2R0BFA 0.8µH Panasonic ETQP6F2R0BFA Output Capacitor 3x270µF Panasonic EEFUE0D271R or Sanyo 4x2R5TPC220M 5x270µF Panasonic EEFUE0D271R or Sanyo 6x2R5TPC220M 6x270µF Panasonic EEFUE0D271R High-Side MOSFET FDS6690A FDS6690A 2x FDS6690A Low-Side MOSFET 2x FDS6670A 2x FDS6670A 2x FDS6670A 1.27kΩ 1.00kΩ 1.50kΩ Maximum CPU Current Current-Input Resistor for ~6% Droop @ Vo=1.6V REV. 1.1.1 8/15/01 13 FAN5231 MOSFET Selection and Considerations Requirements for upper and lower MOSFETs are different in mobile applications. The reason for this is the 10:1 difference in conduction time of the lower and the upper MOSFETs driven by a difference between the input voltage which is nominally in the range from 8V to 20V and output voltage which is about 1.5V. Requirements for the upper MOSFET Rdson are less stringent than for the lower MOSFET because its conduction time is significantly shorter while switching losses can dominate especially at higher input voltages. It is recommended to have equal conduction and switching losses in the upper MOSFET at the nominal input voltage and load current. In this case maximum converter efficiency is tuned to the operation point that it is most desired. Requirements for the lower MOSFET are simpler than those for the upper one. The lower the Rdson of this device the lower the conduction losses, and the higher converter’s efficiency. Switching losses and gate drive losses are not significant because of zero-voltage switching conditions inherent for this device in the buck converter. Important is low reverse recovery charge of the body diode which causes shoot-trough current spikes when the upper MOSFET turns on. Also, important is to verify that the lower MOSFET gate voltage does not reach threshold when high dV/dt transition occurs on the phase node. Specially for that reason, FAN5231 is equipped with a low, 1.0Ω typical, pull-down resistance of low side driver. Precise calculation of power dissipation in the MOSFETs is very complex because many parameters affecting turn-on and turn-off times such as gate reverse transfer charge, gate internal resistance, body diode reverse recovery charge, package and layout impedances and their variation with the operation conditions are not available to a designer. Following equations are provided only for crude estimation of the power losses and should be accompanied by a detail breadboard evaluation. Attention should be paid to the input voltage extremes where power dissipation in the MOSFETs is usually higher. 2 I o × Rdson × Vout Io × Vin × Fs × ( ton + toff ) Pupper = ------------------------------------------------- + -------------------------------------------------------------------Vin 2 2 Vout Plower = Io × Rdson × 1 – ------------ Vin 14 REV. 1.1.1 8/15/01 FAN5231 FAN5231 DC-DC Converter Application Circuit +5-24VDC, +5VDC and +3.3VDC. For detailed information on the circuit, including a Bill-of-Materials and circuit board description, see Application Note ANXXXX. Figure 13 shows an application circuit of a power supply for a notebook PC microprocessor system. The power supply provides the microprocessor core voltage (Vcore), the I/O voltage (VI/O) and the clock generator voltage (VCLK) from Visit Fairchild’s website for the latest product information, www.fairchildsemi.com. +5V V IN +7.5V-24.0V C1 + 56µF GND C5-6 2x1µF C4 10µF CR2 BAT54WT1 CR1 BAT54WT1 VCC VBATT BOOT2 C2 0.22µF Q1 FDS6612A UGATE2 PHASE2 V I/ O (1.5V ) L1 + + C3 330µF 28 21 3 25 4 24 5 23 FAN5231 R1 ISEN2 22 6 Q2 FDS6612A PGND2 VSEN2 1 27 2 26 12 17 16 EN VR_ON 10 V3I N V CL K (2.5V) 9 13 8 7 VSEN3 + C4 10µF UGATE1 PHASE1 ISEN1 R2 LG ATE1 PGND1 Q3 FDS6690A C7 0.22µF V core (0.925 TO 2.0V) L2 2µH Q4 C8 + Two FDS6670A 3x680 µF in parallel + C9 2x1µF 2x10µF VSEN1 FROM CPU CORE VRTN1 20 11 +3.3VI N BOOT1 1k LG ATE2 VGATE PGOOD 500 10µH 1µF 19 14 18 VID0 VID1 VID2 VID3 VID4 VI D0 VI D1 VI D2 VI D3 VI D4 SOFT C10 0.22µF 15 GND Figure 13. Application Circuit REV. 1.1.1 8/15/01 15 FAN5231 Mechanical Dimensions Shrink SMall Outline Plastic Packages (QSOP) Inches Symbol A A1 A2 b c D E E1 e L N α ccc Notes: Millimeters Min. Max. Min. Max. — .002 .065 .009 .004 .340 .078 — 2.00 — .073 .015 .010 .413 — 0.05 1.65 0.22 0.09 9.90 1.85 0.38 0.25 10.50 .291 .323 7.40 8.20 .197 .220 .026 BSC .022 .037 5.00 5.60 0.65 BSC 0.55 0.95 28 28 0° 8° 0° 8° — .004 — 0.10 Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 5 2, 4 5. "b" and "c" dimensions include solder finish thickness. 6. Symbol "N" is the maximum number of terminals. 2 3 6 D E1 A E C A1 A2 b e SEATING PLANE –C– α L LEAD COPLANARITY ccc C 16 REV. 1.1.1 8/15/01 FAN5231 Ordering Information Part Number Temp. (°C) Package FAN5231QSC 0 to 70 28 Ld QSOP DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 8/15/01 0.0m 002 Stock#DS30005230 1999 Fairchild Semiconductor Corporation