M48T254V 3.3V, 16 Mbit (2 Mb x 8 bit) TIMEKEEPER® SRAM WITH PHANTOM CLOCK ■ INTEGRATED ULTRA LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT, BATTERY AND CRYSTAL ■ REAL TIME CLOCK KEEPS TRACK OF TENTHS/HUNDREDTHS OF SECONDS, SECONDS, MINUTES, HOURS, DAYS, DATE, MONTHS, and YEARS. ■ CLOCK FUNCTION IS TRANSPARENT TO RAM OPERATION. ■ PRECISION POWER MONITORING and POWER SWITCHING CIRCUITRY ■ AUTOMATIC WRITE-PROTECTION WHEN VCC IS OUT-OF-TOLERANCE ■ POWER-FAIL DESELECT VOLTAGE: – VCC = 3.3V ± 10%; 2.8V ≤ VPFD ≤ 2.97V ■ BATTERY LOW (BL) ■ 10 YEARS of DATA RETENTION and CLOCK OPERATION IN THE ABSENCE OF POWER ■ SNAPHAT HOUSING (BATTERY/CRYSTAL) IS REPLACEABLE ■ 100ns ACCESS (READ = WRITE) May 2003 Rev. 2.0 Figure 1. 168-ball PBGA Module M48T254V FEATURES SUMMARY ■ 3.3V ± 10% 168-ball PBGA Module (ZA) Figure 2. SNAPHAT Crystal/Battery SNAPHAT (SH) Crystal/Battery 1/24 M48T254V TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 4. PBGA Connections (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 5. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 6. M48T254V PBGA Module Solution (Side/Top) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 7. AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 8. Memory READ Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 9. Memory WRITE Cycle, WRITE Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 10. Memory WRITE Cycle, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7. AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 11. Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 8. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PHANTOM CLOCK OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 12. Comparison Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Clock Register Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 AM-PM/12/24 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Oscillator Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Zero Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 9. RTC Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 13. Phantom Clock READ Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 14. Phantom Clock WRITE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Battery Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 11. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/24 M48T254V SUMMARY DESCRIPTION The M48T254V TIMEKEEPER® RAM is a 2Mbit x 8 non-volatile static RAM and real time clock organized as 2,097,152 words by 8 bits. The special BGA package provides a fully integrated battery back-up memory and real time clock solution. In the event of power instability or absence, a selfcontained battery maintains the timekeeping operation and provides power for a CMOS static RAM. Control circuitry monitors VCC and invokes write protection to prevent data corruption in the memory and RTC. Figure 3. Logic Diagram The clock keeps track of tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. The last day of the month is automatically adjusted for months with less than 31 days, including leap year correction. The clock operates in one of two formats: – a 12-hour mode with an AM/PM indicator; or – a 24-hour mode The M48T254V is a 168-ball PBGA module that integrates the RTC, the battery, and SRAM in one package. Table 1. Signal Names VCC A0 - A20 Address Inputs DQ0 - DQ7 Data Input/Output CE Chip Enable WE WRITE Enable Inputs OE Output Enable BL Battery Low Output (Open Drain) NC No Connect VCC Supply Voltage VSS Ground A0 – A20 DQ0 – DQ7 CE M48T254V BL WE OE VSS AI04217 3/24 M48T254V 41 40 39 38 37 36 35 34 33 32 31 30 VCC A8 A9 A10 A11 GND A12 A13 A14 A15 A16 VCC Figure 4. PBGA Connections (Top View) 1 VCC VCC 29 2 A7 A17 28 3 A6 A18 27 4 A5 A19 26 5 GND GND 25 6 A4 A20 24 7 A3 CE 23 8 A2 OE 22 9 A1 WE 21 A0 DQ0 DQ1 DQ2 DQ3 GND DQ4 DQ5 DQ6 DQ7 BL 10 11 12 13 14 15 16 17 18 19 20 M48T254V AI04216 Note: This diagram is TOP VIEW perspective (view through package). 4/24 M48T254V VCC E 8 VCC M68Z512W E DQ0-DQ7 A0-A18 A0-A18 VOUT VOUT 19 VCC 19 M40Z300W 8 3.3V DQ0-DQ7 Figure 5. Hardware Hookup G M68Z512W .1µF E W W G WE OE 3.3V BL (Not Bonded) To Battery Monitor Circuitry M40Z300W VCC VOUT CEO DQ0-DQ7 3.3V 8 WE A0-A18 OE WE 19 CEI OE DQ0-DQ7 DQ0 8 D Q RST A0-A18 VCC CE THS VSS M41T315V 19 3.3V VCC VCC E1CON E E2CON A19 A E3CON A20 B E4CON THS VSS RST M68Z512W E G W .1µF M68Z512W E G W WE OE BL AI04215 5/24 M48T254V Figure 6. M48T254V PBGA Module Solution (Side/Top) AI04214b MAXIMUM RATING Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 2. Absolute Maximum Ratings Symbol TA Parameter Operating Temperature Value Unit 0 to 70 °C TSTG Storage Temperature (VCC, Oscillator Off) –40 to 85 °C TSLD Lead Solder Temperature for 10 seconds 260 °C VCC Supply Voltage (on any pin relative to Ground) –0.3 to +4.6 V VIO Input or Output Voltages –0.3 to VCC + 0.3 V IO Output Current 20 mA PD Power Dissipation 1 W CAUTION! Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up Mode. 6/24 M48T254V DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 3. DC and AC Measurement Conditions Parameter M41T254V VCC Supply Voltage 3.0 to 3.6V Ambient Operating Temperature 0 to 70°C Load Capacitance (CL) 50pF Input Rise and Fall Times ≤ 5ns Input Pulse Voltages 0 to 3V Input and Output Timing Ref. Voltages 1.5V Note: Output Hi-Z is defined as the point where data is no longer driven. Figure 7. AC Testing Load Circuit 645Ω DEVICE UNDER TEST CL = 50 pF 1.75V AI04644 Table 4. Capacitance Symbol Parameter(1,2) Max Unit Input Capacitance (A0-A18, OE, WE, CE) 40 pF Input Capacitance (A19-A20) 10 pF COUT Output Capacitance (BL) 20 pF CIO(3) Input / Output Capacitance 40 pF CIN Min Note: 1. Effective capacitance measured with power supply at 3V. Sampled only; not 100% tested. 2. At 25°C, f = 1MHz. 3. Outputs were deselected. 7/24 M48T254V Table 5. DC Characteristics Sym Parameter ILI Input Leakage Current ILO Output Leakage Current ICC1 Supply Current ICC2 Supply Current (TTL Standby) ICC3 VCC Power Supply Current VIL(2) Input Low Voltage VIH(2) Input High Voltage VOL(3) VOH M48T254V Unit Min Typ 0V ≤ VIN ≤ VCC ±4 µA 0V ≤ VOUT ≤ VCC ±4 µA 50 mA CE = VIH 5 7 mA CE = VCCI – 0.2 2 3 mA –0.3 0.6 V 2.2 VCC + 0.3 V IOL = 10mA 0.4 V Output Low Voltage IOL = 2.0mA 0.4 V Output High Voltage IOH = –1.0mA Battery Back-up Switchover 2.4 V 2.80 2.97 2.5 Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 3.0 to 3.6V (except where noted). 2. All voltages are referenced to Ground. 3. For BL pin (Open Drain). 8/24 Max Output Low Voltage (Open Drain) VPFD(2) Power Fail Deselect VSO(2) Test Condition(1) V V M48T254V OPERATION MODES READ A READ cycle executes whenever WRITE Enable (WE) is high and Chip Enable (CE) is low (see Figure 8, page 10). The distinct address defined by the 21 address inputs (A0-A20) specifies which of the 2M bytes of data is to be accessed. Valid data will be accessed by the eight data output drivers within the specified Access Time (tACC) after the last address input signal is stable, the CE and OE access times, and their respective parameters are satisfied. When CE tACC and OE tACC are not satisfied, then data access times must be measured from the more recent CE and OE signals, with the limiting parameter being tCO (for CE) or tOE (for OE) instead of address access. WRITE WRITE Mode occurs whenever CE and WE signals are low (after address inputs are stable, see Figure 9, page 10 and Figure 10, page 11). The most recent falling edge of CE and WE will determine when the WRITE cycle begins (the earlier, rising edge of CE or WE determines cycle termination). All address inputs must be kept stable throughout the WRITE cycle. WE must be high (inactive) for a minimum recovery time (tWR) before a subsequent cycle is initiated. The OE control signal should be kept high (inactive) during the WRITE cycles to avoid bus contention. If CE and OE are low (active), WE will disable the outputs for Output Data WRITE Time (tODW) from its falling edge. Table 6. Operating Modes Mode VCC CE OE WE DQ7-DQ0 Power VIH X X High-Z Standby VIL X VIL DIN Active READ VIL VIL VIH DOUT Active READ VIL VIH VIH High-Z Active Deselect WRITE 3.0V to 3.6V Deselect VSO to VPFD (min)(1) X X X High-Z CMOS Standby Deselect ≤ VSO(1) X X X High-Z Battery Back-Up Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage 1. See Table 8, page 13 for details. 9/24 M48T254V Figure 8. Memory READ Cycle tRC ADDRESSES tACC tOH tCO CE tOD tOE OE tCOE tODO tCOE DATA OUTPUT VALID DQ0 - DQ7 AI04230 Note: WE is high for a READ cycle. Figure 9. Memory WRITE Cycle, WRITE Enable Controlled tWC ADDRESSES tAW CE tAH1 tWP WE tOEW tODW HIGH IMPEDANCE DQ0–DQ7 tDH1 tDS DATA IN STABLE AI05655 Note: 1. OE = VIH or VIL. If OE = VIH during a WRITE cycle, the output buffers remain in a high impedance state. 2. If the CE low transition occurs simultaneously with or later than the WE low transition in WE Controlled WRITE, the output buffers remain in a high impedance state during this period. 3. If the CE high transition occurs simultaneously with the WE high transition, the output buffers remain in a high impedance state during this period. 10/24 M48T254V Figure 10. Memory WRITE Cycle, Chip Enable Controlled tWC ADDRESSES tAW tWP tAH2 CE tOEW WE tODW tCOE DQ0–DQ7 tDS tDH2 DATA IN STABLE AI05656 Note: 1. OE = VIH or VIL. If OE = VIH during a WRITE cycle, the output buffers remain in a high impedance state. 2. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period. 11/24 M48T254V Table 7. AC Electrical Characteristics Parameter(1) Symbol M48T254V Unit Min Max tAVAV tRC READ Cycle Time tAVQV tACC Access Time 100 ns tELQV tCO Chip Enable Low to Output Valid 100 ns tGLQV tOE Output Enable Low to Output Valid 55 ns tELQX tCOE(2) tAXQX tOH tEHQZ tOD(2) tGHQZ 100 ns Chip Enable or Output Enable Low to Output Transition 5 ns Output Hold from Address Change 5 ns Chip Enable High to Output Hi-Z 35 ns tODO(2) Output Enable High to Output Hi-Z 35 ns tWLQZ tODW(2) Output Hi-Z from WE 35 ns tAVAV tWC tWLWH tELEH WRITE Cycle Time 100 ns tWP(3) WE, CE Pulse Width 70 ns tAVEL tAW Address Setup Time 0 ns tWHAX tAH1 Address Hold Time from WE 5 ns tEHAX tAH2 Address Hold Time from CE 25 ns tWHQX tOEW(2) Output Active from WE 5 ns tDVEH tDVWH tDS Data Setup Time 40 ns tWHDX tDH1 Data Hold Time from WE 0 ns tEHDX tDH2 Data Hold Time from CE 20 ns tRR READ Recovery (Clock Access Only) 20 ns tWR(4) WRITE Recovery (Clock Access Only) 20 ns Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 3.0 to 3.6V (except where noted). 2. These parameters are sampled with a 5 pF load are not 100% tested. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tWR is a function of the latter occurring edge of WE or CE. 12/24 M48T254V Data Retention Mode Data can be read or written only when VCC is greater than VPFD. When VCC is below VPFD (the point at which write protection occurs), the clock registers and the SRAM are blocked from any access. When VCC falls below the Battery Switch Over threshold (VSO), the device is switched from VCC to battery backup (VBAT). RTC operation and SRAM data are maintained via battery backup until power is stable. All control, data, and address signals must be powered down when VCC is powered down. The lithium power source is designed to provide power for RTC activity as well as RTC and RAM data retention when VCC is absent or unstable. The capability of this source is sufficient to power the device continuously for the life of the equipment into which it has been installed. For specification purposes, life expectancy is ten (10) years at 25°C with the internal oscillator running without VCC. The actual life expectancy will be much longer if no battery energy is used (e.g., when VCC is present). Figure 11. Power Down/Up Mode AC Waveforms VCC tF tR VPFD (max) VPFD (min) VSO tFB tREC tPD DON'T CARE CE tDR AI05657 Table 8. Power Down/Up Trip Points DC Characteristics Symbol Parameter(1) Min Max Unit VPFD (max) to CE low 40 120 ms tF VPFD (max) to VPFD (min) VCC Fall Time 300 µs tFB VPFD (min) to VSO VCC Fall Time 10 µs tR VPFD (min) to VPFD (max) VCC Rise Time 0 µs CE High to Power-Fail 0 µs Expected Data Retention Time 10 Years tREC tPD tDR(2) Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 3.0 to 3.6V (except where noted). 2. At 25°C, VCC = 0V; the expected tDR is defined as cumulative time in the absence of VCC with the clock oscillator running. (Requires use of three M4T32-BR12SH SNAPHAT ® tops.) 13/24 M48T254V PHANTOM CLOCK OPERATION Communication with the Phantom Clock is established by pattern recognition of a serial bit-stream of 64 bits which must be matched by executing 64 consecutive WRITE cycles containing the proper data on DQ0. All accesses which occur prior to recognition of the 64-bit pattern are directed to memory. After recognition is established, the next 64 READ or WRITE cycles either extract or update data in the clock while disabling the memory. Data transfer to and from the timekeeping function is accomplished with a serial bit-stream under control of Chip Enable (CE), Output Enable (OE), and WRITE Enable (WE). Initially, a READ cycle using the CE and OE control of the clock starts the pattern recognition sequence by moving the pointer to the first bit of the 64-bit comparison register (see Figure 12, page 15). Next, 64 consecutive WRITE cycles are executed using the CE and WE control of the device. These 64 WRITE cycles are used only to gain access to the clock. Therefore, any address to the memory is acceptable. However, the WRITE cycles generated to gain access to the Phantom Clock are also writing data to a location in the mated RAM. The preferred way to manage this requirement is to set 14/24 aside just one address location in RAM as a Phantom Clock scratch pad. When the first WRITE cycle is executed, it is compared to Bit 1 of the 64-bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next WRITE cycle. If a match is not found, the pointer does not advance and all subsequent WRITE cycles are ignored. If a READ cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64 WRITE cycles as described above until all of the bits in the comparison register have been matched. With a correct match for 64-bits, the Phantom Clock is enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the Phantom Clock to either receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with CE cycles without interrupting the pattern recognition sequence or data transfer sequence to the Phantom Clock. M48T254V Figure 12. Comparison Register Definition Hex Value 7 6 5 4 3 2 1 0 BYTE 0 1 1 0 0 0 1 0 1 C5 BYTE 1 0 0 1 1 1 0 1 0 3A BYTE 2 1 0 1 0 0 0 1 1 A3 BYTE 3 0 1 0 1 1 1 0 0 5C BYTE 4 1 1 0 0 0 1 0 1 C5 BYTE 5 0 0 1 1 1 0 1 0 3A BYTE 6 1 0 1 0 0 0 1 1 A3 BYTE 7 0 1 0 1 1 1 0 0 5C AI04262 Note: The odds of this pattern being accidentally duplicated and sending aberrant entries to the RTC is less than 1 in 1019. This pattern is sent to the clock LSB to MSB. 15/24 M48T254V Clock Register Information Clock information is contained in eight registers of 8 bits, each of which is sequentially accessed one (1) bit at a time after the 64-bit pattern recognition sequence has been completed. When updating the clock registers, each must be handled in groups of 8 bits. Writing and reading individual bits within a register could produce erroneous results. These READ/WRITE registers are defined in the clock register map (see Table 9). Data contained in the clock registers is in Binary Coded Decimal format (BCD). Reading and writing the registers is always accomplished by stepping through all eight registers, starting with Bit 0 of Register 0 and ending with Bit 7 of Register 7. AM-PM/12/24 Mode Bit 7 of the hours register is defined as the 12-hour or 24-hour mode select bit. When it is high, the 12hour mode is selected. In the 12-hour mode, Bit 5 is the AM/PM bit with the logic high being “PM.” In the 24-hour mode, Bit 5 is the second 10-hour bit (20-23 hours). Oscillator Bit Bit 5 controls the oscillator. When set to logic '0,' the oscillator turns on and the RTC/calendar begins to increment. Zero Bits Registers 1, 2, 3, 4, 5, and 6 contain one (1) or more bits that will always read logic '0.' When writing to these locations, either a logic '1' or '0' is acceptable. Table 9. RTC Register Map Register D7 0 D6 D4 D3 0.1 Seconds D2 D1 D0 0.01 Seconds Seconds 00-99 1 0 10 Seconds Seconds Seconds 00-59 2 0 10 Minutes Minutes Minutes 00-59 3 12/24 0 10/ A/P Hrs Hours (24 Hour Format) Hours 01-12/ 00-23 4 0 0 OSC 1 Day 01-7 5 0 0 Date: Day of the Month Date 01-31 6 0 0 Month Month 01-12 Year Year 00-99 7 10 date 0 10 Years Keys: A/P = AM/PM Bit 12/24 = 12 or 24-hour mode Bit OSC = Oscillator Bit RST = Reset Bit 0 = Must be set to '0' 1 = Must be set to '1' 16/24 D5 Function/Range BCD Format 10M 0 Day of the Week M48T254V Figure 13. Phantom Clock READ Cycle WE tRC tCW tRR tCO CE tOD tOW OE tODO tOE tOEE tCOE DATA OUTPUT VALID Q AI04259 Figure 14. Phantom Clock WRITE Cycle OE tWC tWP tWR WE tAH2 tCW CE tDH2 tDH1 tDS D DATA INPUT STABLE AI05658 17/24 M48T254V Battery Low The M48T254V automatically performs battery voltage monitoring upon power-up, and at factoryprogrammed time intervals of at least 24 hours. The Battery Low (BL) signal will be asserted if the battery voltage is found to be less than approximately 2.5V. The BL signal will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that one of the batteries is below 2.5V and may not be able to maintain data integrity in the SRAM. Data should be considered suspect, and verified as correct. All three SNAPHAT® tops should be replaced. If a battery low indication is generated during the 24-hour interval check, this indicates that one of the batteries is near end of life. However, data is 18/24 not compromised due to the fact that a nominal VCC is supplied. In order to insure data integrity during subsequent periods of battery back-up mode, the batteries should be replaced. The SNAPHAT top should be replaced with valid VCC applied to the device. The M48T254V only monitors the batteries when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. The BL signal is an open drain output and an appropriate pull-up resistor should be chosen to control the rise time. Note: The BL signal is available only for the external SRAM, not for the Real-Time Clock. M48T254V PART NUMBERING Table 10. Ordering Information Scheme Example: M48T 254V –10 ZA 1 Device Type M48T Supply Voltage and Write Protect Voltage 254V = VCC = 3.0 to 3.6V; VPFD = 2.8 to 2.97V Speed –10 = 100ns Package(1) ZA = 42.5mm x 42.5mm(2), 1.27mm Ball Pitch, BGA Module Temperature Range 1 = 0 to 70°C Note: 1. The SOIC packages (SO28/SO44) require the battery/crystal package (SNAPHAT) which is ordered separately under the part number “M4T32-BR12SH” in plastic tube or “M4T32-BR12SHTR” in Tape and Reel form. 2. Where “Z” is the symbol for BGA packages and “A” denotes 1.27mm ball pitch For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. Table 11. SNAPHAT Battery Table Part Number M4T32-BR12SH Description Lithium Battery (120mAh) SNAPHAT Package SH 19/24 M48T254V PACKAGE MECHANICAL INFORMATION Figure 15. PBGA-ZA – 168-ball Plastic Ball Grid Array Package Outline A B D GD JE B1 A3 A A1 A2 E SIDE VIEW (SH x 1) B HD HE TOP VIEW FE 45˚ GE PIN 1 CORNER ddd C SIDE VIEW (SH x 2) eee S C A S B S fff S C E E1 e DETAIL A b e SOLDER BALL (Typ) e b Detail A D1 FD 0.20 (4X) D BOTTOM VIEW Note: Drawing is not to scale. 20/24 PBGA-Z02 M48T254V Table 12. PBGA-ZA – 168-ball Plastic Ball Grid Array Package Mechanical Data mm inches Symb Typ Min Max Typ Min Max A 2.94 2.74 3.14 0.116 0.108 0.124 A1 0.89 0.69 1.09 0.035 0.027 0.043 A2 11.53 11.18 11.88 0.454 0.440 0.468 7.24 8.00 0.285 0.315 38.34 38.74 1.509 1.525 21.21 21.84 0.835 0.860 A3 B 38.54 B1 1.517 b 0.76 0.71 0.81 0.030 0.028 0.032 D 42.50 42.30 42.70 1.673 1.665 1.681 D1 27.94 E 42.50 1.665 1.681 E1 22.86 0.900 e 1.27 0.050 FD 7.28 7.18 7.38 0.287 0.283 0.291 FE 9.82 9.72 9.92 0.387 0.383 0.391 GD 1.75 1.55 1.95 0.069 0.061 0.077 GE 1.50 1.30 1.70 0.059 0.051 0.067 HD 1.98 1.78 2.18 0.078 0.070 0.086 HE 0.51 0.31 0.71 0.020 0.012 0.028 JE 1.50 1.30 1.70 0.059 0.051 0.067 n 1.100 42.30 42.70 1.673 168 168 Tolerance Tolerance ddd 0.15 0.006 eee 0.30 0.012 fff 0.15 0.006 21/24 M48T254V Figure 16. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline A1 eA A2 A A3 B L eB D E SHTK-A Note: Drawing is not to scale. Table 13. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mechanical Data mm inches Symb Typ Min A Typ Min 10.54 Max 0.415 A1 8.00 8.51 0.315 .0335 A2 7.24 8.00 0.285 0.315 A3 22/24 Max 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 17.27 18.03 0.680 .0710 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 M48T254V REVISION HISTORY Table 14. Document Revision History Date Rev. # Revision Details September 2002 1.0 First Issue 31-Mar-03 1.1 Updated test condition (Table 8) 19-May-03 2.0 v2.2 template update; modify package dimensions (Table 12) 23/24 M48T254V Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. © 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com 24/24