IXYS MX860 /-15v epaper source driver Datasheet

MX860
+/-15V ePaper Source Driver
INTEGRATED CIRCUITS DIVISION
Features
Description
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The MX860 is a selectable 240, 256, or 268 bit long;
2-bit wide; serial-input parallel-output digital shift
register with level conversion on each parallel output.
Level conversion converts the 2 digital bits into VPOS ,
VSS , or VNEG analog output voltages. An 8-bit input
bus simultaneously inputs 4 groups of 2 bits each.
CMOS Technology
+/-15 Volt Output Driver Supply Voltage
Drives Segment or Active Matrix Displays
4-Level Gray Scale
25MHz Clock Frequency
Bidirectional Data Transfer
Selectable Register Length
2.7V to 5.5V Logic Supply Voltage
Cascadable
Applications
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eBooks / eReaders
Electronic Shelf Labels / Point Of Purchase Displays
Mobile Phones / Portable Hand Held Devices
Smart Cards
Signage
Ordering Information
Part
Description
MX860WB
Gold Bumped Die / Wafer Form
MX860XB
Gold Bumped Die / Waffle Pack
MX860TC
48mm Super Wide Tape Carrier
The MX860 consists of a selectable length
Bidirectional Input Register, Transfer Latch, and
268-bit Level Shifter / Output Driver. Each OUT pin is
switched to one of [VSS , VPOS , VNEG] according to
the D0...D7 logic levels clocked into the MX860,
modified by the OE pin.
The MX860 is designed to operate over a temperature
range of -40°C to +85°C, and is available as Gold
Bumped Die in Wafer Form or Waffle Pack, and 48mm
Super-Wide Tape Carrier Package.
Figure 1. Functional Block Diagram
OUT1
OUT2
VPOS
VSS
VNEG
. . .
LEVEL SHIFTER / DRIVER
OE
DECODE
LE
LATCH
4-way Interleaved
2-bit Register
Stages
4x(1 - 60)
Data path when
SHR = 1
D(7..0)
OUT267 OUT268
61 - 64
when
SHR = 0
mode 240
CONTROL LOGIC
65 - 67
256
268
Clock
Direction
SHR
MODE1
MODE0
CE
CL
PB-MX860-January 21, 2014
www.ixysic.com
1
MX860
INTEGRATED CIRCUITS DIVISION
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Specification: PB-MX860-January 21, 2014
©Copyright 2014, IXYS Integrated Circuits Division
All rights reserved. Printed in USA.
1/21/2014
January 21, 2014
www.ixysic.com
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