SMSC EMC1702-1-KP-TR High-side current-sense and dual 1â°c temperature monitor Datasheet

EMC1702
High-Side Current-Sense and Dual
1°C Temperature Monitor
PRODUCT FEATURES
Datasheet
General Description
Features
The EMC1702 is a combination high-side current sensing
device with precision temperature measurement. It
measures the voltage developed across an external sense
resistor to represent the high-side current of a battery or
voltage regulator. It also measures the source voltage and
uses these measured values to present a proportional
power calculation. The EMC1702 contains additional bidirectional peak detection circuitry to flag instantaneous
current spikes with programmable time duration and
magnitude threshold. Finally, the EMC1702 includes an
external diode channel for temperature measurement as
well as an internal diode for ambient temperature
measurements.
„
The temperature measurement includes advanced features
such as Resistance Error Correction (REC), Beta
Compensation (to support CPU diodes requiring the
BJT/transistor model including 45nm and 65nm
processors), and automatic diode type detection.
Both current sensing and temperature monitoring include
two tiers of protection: one that can be masked and causes
the ALERT pin to be asserted, and the other that cannot be
masked and causes the THERM pin to be asserted.
Applications
„
„
„
„
—
—
—
—
—
„
Bi-directional current measurement
Measures source voltage and indicates power ratio
1% current measurement accuracy
Integrated over 82ms to 2.6sec with 11-bit resolution
3V to 24V bus voltage range
Independent hardware set instantaneous current peak
detector
— Software controls to program time duration and
magnitude threshold
„
Power supply options
„
„
Wide temperature operating range: -40°C to +85°C
One external temperature monitor
— Bus or separately powered for low voltage operation
— 1°C accuracy (20°C < TDIODE < 110°C) with 0.125°C
resolution
— Ideality factor setting
— Support for 45nm and 65nm CPU diodes requiring the
BJT/transistor model w/ beta compensation
— Determines external diode type and optimal settings
— Resistance Error Correction
„
Internal temperature monitor
„
ALERT and THERM outputs for temperature, voltage,
and out-of-current limit reporting
SMBus 2.0 interface
— ±1°C accuracy (-5°C < TA < 85°C)
„
Notebook and Desktop Computers
Industrial
Power Management Systems
Embedded Applications
High-side current sensor
— Pin-selectable SMBus Address
— Block Read and Write
„
Available in a 12-pin 4mm x 4mm QFN RoHS Compliant
Package
DUR_SEL
TH_SEL
SENSE-
SENSE+
Block Diagram
Peak
Detection
DP
DN
External
Temp
Diode
Current Limits
Analog
Mux
Internal
Temp
Diode
13 - 15 bit
Σ Δ ADC
Current Registers
Configuration
Power Register
11 - 15 bit
Σ Δ ADC
Voltage and
Temp Registers
ADDR_SEL
SMBus
Slave
Protocol
SMCLK
SMDATA
ALERT
THERM
Voltage and
Temp Limits
SMSC EMC1702
DATASHEET
Revision 1.2 (09-27-10)
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Ordering Information:
ORDERING NUMBER
EMC1702-1-KP-TR
PACKAGE
12-pin 4mm x 4mm QFN
(Lead-free ROHS compliant)
FEATURES
External Diode, current sensor,
hardware set peak detector
REEL SIZE IS 4,000 PIECES
This product meets the halogen maximum concentration values per IEC61249-2-21
For RoHS compliance and environmental information, please visit www.smsc.com/rohs
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123
Copyright © 2010 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property
damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of
this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered
trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE
OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL
DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;
TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD
TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 1.2 (09-27-10)
2
DATASHEET
SMSC EMC1702
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Table of Contents
Chapter 1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chapter 3 Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
3.2
System Management Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1
SMBus Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2
SMBus Address and RD / WR Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3
SMBus ACK and NACK Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.4
SMBus Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.5
SMBus Time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.6
SMBus and I2C Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMBus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1
Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2
Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3
Send Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.4
Receive Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.5
Block Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.6
Block Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.7
Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
15
16
16
16
16
17
17
17
17
18
18
18
19
Chapter 4 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Source Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1
Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2
Voltage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.3
Power Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.4
Current Peak Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VDD Biasing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ALERT Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1
ALERT Pin Interrupt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2
ALERT Pin Comparator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
THERM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.1
Resistance Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.2
Beta Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.3
Ideality Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.4
Dynamic Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diode Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.1
Diode Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
22
22
23
25
25
26
26
26
26
27
27
27
27
28
28
28
Chapter 5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Data Read Interlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conversion Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMSC EMC1702
3
DATASHEET
32
32
32
33
34
35
36
Revision 1.2 (09-27-10)
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.18
5.19
5.20
5.21
5.22
5.23
5.24
5.25
5.26
5.27
5.28
5.29
5.30
5.31
One-Shot Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tcrit Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Diode Fault Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Consecutive Alert Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Beta Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Diode Ideality Factor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crit Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Averaging Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Sampling Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sense Sampling Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak Detection Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sense Voltage Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Source Voltage Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Ratio Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VSENSE Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Source Voltage Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Critical Voltage Limit Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Features Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMSC ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
37
37
37
38
39
40
41
42
42
43
43
44
46
48
49
49
50
50
50
51
51
52
52
Chapter 6 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1
6.2
EMC1702 Package Drawing (12-Pin QFN 4mm x 4mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
EMC1702 Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chapter 7 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Revision 1.2 (09-27-10)
4
DATASHEET
SMSC EMC1702
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
List of Figures
Figure 1.1
Figure 3.1
Figure 4.1
Figure 4.2
Figure 4.3
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
EMC1702 Pin Diagram 12-Pin QFN 4mm x 4mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SMBus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
EMC1702 System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Peak Detection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Diode Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12-Pin QFN 4mm x 4mm Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12-Pin QFN 4mm x 4mm Package Dimensions and Notes . . . . . . . . . . . . . . . . . . . . . . . . . . 54
12-Pin QFN 4mm x 4mm PCB Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
EMC1702 Package Markings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
SMSC EMC1702
5
DATASHEET
Revision 1.2 (09-27-10)
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
List of Tables
Table 1.1 Pin Description for EMC1702 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 1.2 Pin Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2.3 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3.1 ADDR_SEL Resistor Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3.2 Protocol Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3.3 Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3.4 Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3.5 Send Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3.6 Receive Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3.7 Block Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3.8 Block Read Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3.9 Alert Response Address Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4.1 TH_SEL Resistor Setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4.2 DUR_SEL Resistor Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 4.3 Dynamic Averaging Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 5.1 Register Set in Hexadecimal Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 5.2 Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 5.3 Temperature Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 5.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 5.5 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 5.6 Conversion Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 5.7 Conversion Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 5.8 Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 5.9 One-Shot Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 5.10 Tcrit Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 5.11 External Diode Fault Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 5.12 Channel Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 5.13 Consecutive Alert Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 5.14 Consecutive ALERT / THERM Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 5.15 Beta Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 5.16 Beta Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 5.17 Ideality Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 5.18 Ideality Factor Look-Up Table (Diode Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 5.19 High Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 5.20 Low Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 5.21 Crit Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 5.22 Filter Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 5.23 Averaging Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 5.24 Voltage Sampling Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 5.25 Voltage Queue Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 5.26 Voltage Averaging Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 5.27 Current Sense Sampling Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 5.28 Sense Queue Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 5.29 Current Sense Averaging Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 5.30 Current Sensing Sampling Time Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 5.31 Total Sampling Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 5.32 Current Sensing Range (Full Scale Range) Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 5.33 Peak Detection Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 5.34 PEAK_DET_TH[3:0] Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 5.35 PEAK_DET_DUR[3:0] Bit Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Revision 1.2 (09-27-10)
6
DATASHEET
SMSC EMC1702
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Table 5.36 Sense Voltage Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.37 VSENSE Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.38 Source Voltage Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.39 Power Ratio Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.40 VSENSE Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.41 Source Voltage Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.42 Critical Voltage Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.43 Product Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.44 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.45 Manufacturer ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.46 Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMSC EMC1702
7
DATASHEET
48
48
49
49
50
50
50
51
51
52
52
56
Revision 1.2 (09-27-10)
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
10 TH_SEL
6
3
ALERT
DN
EMC1702
12-QFN
5
2
THERM
DP
4
1
ADDR_SEL
VDD
11 SENSE-
12 SENSE+
Chapter 1 Pin Description
9
DUR_SEL
8
SMCLK
7
SMDATA
GND
Figure 1.1 EMC1702 Pin Diagram 12-Pin QFN 4mm x 4mm
Table 1.1 Pin Description for EMC1702
PIN NUMBER
PIN NAME
PIN FUNCTION
PIN TYPE
1
VDD
Positive power supply voltage
Power (24V)
2
DP
External Diode positive (anode) connection
AIO (2V)
3
DN
External Diode negative (cathode)
connection
AIO (2V)
4
ADDR_SEL
Selects SMBus Address
AI
5
THERM
Active low output - requires pull-up resistor
OD (5V)
6
ALERT
Active low output - requires pull-up resistor
OD (5V)
7
SMDATA
SMBus data input/output - requires external
pull-up resistor
DIOD (5V)
8
SMCLK
SMBus clock input - requires external pullup resistor
DI (5V)
9
DUR_SEL
Selects peak detector duration
AI
Revision 1.2 (09-27-10)
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DATASHEET
SMSC EMC1702
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Table 1.1 Pin Description for EMC1702 (continued)
PIN NUMBER
PIN NAME
PIN FUNCTION
PIN TYPE
10
TH_SEL
Selects peak detector threshold
AI
11
SENSE-
Negative current sense measurement point
AI (24V)
12
SENSE+
Positive current sense measurement point
AI (24V)
Bottom Pad
GND
Ground
Power
The pin types are described in Table 1.2. All pins labeled with (5V) are 5V tolerant. All pins labeled
with (24V) are 24V tolerant.
Table 1.2 Pin Types
PIN TYPE
SMSC EMC1702
DESCRIPTION
Power
This pin is used to supply power or ground to the device.
AI
Analog Input - this pin is used as an input for analog
signals.
AIO
Analog Input / Output - this pin is used as an I/O for
analog signals.
OD
Open Drain Digital Output - this pin is used as a digital
output. It is open drain and requires a pull-up resistor.
This pin is 5V tolerant.
DI
Digital Input - this pin is used for digital inputs. This pin is
5V tolerant.
DIOD
Open Drain Digital Input / Output - this pin is bi-directional.
It is open drain and requires a pull-up resistor. This pin is
5V tolerant.
9
DATASHEET
Revision 1.2 (09-27-10)
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Chapter 2 Electrical Characteristics
Table 2.1 Absolute Maximum Ratings
Voltage on 5V tolerant pins
-0.3 to 5.5
V
Voltage on 2V tolerant pins
-0.3 to 2
V
Voltage on VDD, SENSE- and SENSE+ pins
-0.3 to 26
V
Voltage on any other pin to GND
-0.3 to 4
V
Voltage between Sense pins ( |(SENSE+ - SENSE-)| )
<6
V
Package Power Dissipation
0.5W up to TA = 85°C
W
Junction to Ambient (θJA) (QFN12 package)
58
°C/W
Operating Ambient Temperature Range
-40 to 85
°C
Storage Temperature Range
-55 to 150
°C
ESD Rating - SMCLK, SMDATA, ALERT, THERM pins - HBM
4000
V
ESD Rating - All other pins - HBM
2000
V
Note 2.1
Stresses at or above those values listed could cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at any other condition
above those indicated in the operation sections of this specification is not implied.
Prolonged stresses above the stated operating levels and below the Absolute Maximum
Ratings may degrade device performance and lead to permanent damage.
Note 2.2
All voltages are relative to ground.
Note 2.3
The Package Power Dissipation specification assumes a thermal via design with the
thermal landing be soldered to the PCB ground plane with four 12 mil vias.
Note 2.4
Junction to Ambient (θJA) is dependent on the design of the thermal vias. Without thermal
vias and a thermal landing, the θJA is approximately 60°C/W including localized PCB
temperature increase.
Revision 1.2 (09-27-10)
10
DATASHEET
SMSC EMC1702
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
2.1
Electrical Specifications
Table 2.2 Electrical Specifications
VDD = VBUS = 3V TO 24V, VPULLUP = 3V TO 5.5V, TA = -40°C TO 85°C,
ALL TYPICAL VALUES AT VDD = VPULLUP = 3.3V, VBUS = 12V, AND TA = 27°C UNLESS OTHERWISE NOTED.
CHARACTERISTIC
SYMBOL
MIN
TYP
MAX
UNIT
CONDITIONS
DC POWER
Supply Voltage
VDD Pin Supply
Current
VDD
3
IDD
24
610
750
uA
Temp conversions at 0.0625
conversions / second,
dynamic averaging disabled
current sense active
650
950
uA
Temp conversions at 4
conversions / second,
dynamic averaging disabled
current sense active
1100
uA
Temp conversions at 8
conversions / second,
dynamic averaging enabled
current sense active
750
uA
Temp conversions disabled
(TMEAS / STOP = ‘1’)
current sense active
uA
Temp conversions disabled
(TMEAS / STOP = ‘1’)
Current sense disabled
(IMEAS / STOP = ‘1’)
90
uA
VSENSE = 0V, VDD = 3V to 24V,
Current sense active
15
uA
VSENSE = 0V, VDD = 3V to 24V,
current sense disabled
uA
VDD = 0V
10
uA
VSENSE = 0V, VDD = 3V to 24V,
Current sense active
10
uA
VSENSE = 0V, VDD = 3V to 24V,
current sense disabled
0
uA
VDD = 0V
V
Pull-up voltage for SMBus,
ALERT, and THERM pins
uA
ALERT and THERM pins,
SMDATA and SMCLK pins
powered or unpowered,
TA < 85°C
950
VDD Pin Supply
Current
VDD Pin Supply
Current
SENSE+ Pin Bias
Current
IDD_
T_STANDBY
IDD_ALL_
300
STANDBY
ISENSE+
10
SENSE- Pin Bias
Current
Pull-up Voltage
V
ISENSE-
VPULLUP
20
3
5.5
Leakage Current (±)
ILEAK
SMSC EMC1702
5
11
DATASHEET
Revision 1.2 (09-27-10)
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Table 2.2 Electrical Specifications (continued)
VDD = VBUS = 3V TO 24V, VPULLUP = 3V TO 5.5V, TA = -40°C TO 85°C,
ALL TYPICAL VALUES AT VDD = VPULLUP = 3.3V, VBUS = 12V, AND TA = 27°C UNLESS OTHERWISE NOTED.
CHARACTERISTIC
SYMBOL
MIN
TYP
MAX
UNIT
CONDITIONS
CURRENT SENSE
Common Mode
Voltage
VCM
3
24
V
Voltage on SENSE+ and/or
SENSE- pins, referenced to
Ground
Differential Mode
Voltage
VDIFF
-6
+6
V
Voltage between SENSE+ and
SENSE- pins
0
10
mV
1 LSB = 4.885uV
0
20
mV
1 LSB = 9.77uV
0
40
mV
1 LSB = 19.54uV
0
80
mV
1 LSB = 39.08uV
1
%
Total Error, FSR = 80mV
Full Scale Range (±)
FSR
(see Section 5.20)
0.5
Total Measurement
Error (±)
VSENSE
_ERR
3
%
Total Error, FSR = 10mV to
40mV
Offset Error (±)
VSENSE
3
LSB
Offset Error, FSR = 80mV
-120
dB
FSR = 10mV to 80mV,
3V < VDD < 24V
-110
dB
FSR = 10mV to 80mV,
3V < VBUS < 24V
23.9883
V
Voltage on SENSE+ pin
0.5
%
_OFF
Power Supply
Rejection
VSENSE
Common Mode
Rejection
VSENSE
_PSR
_CMR
SOURCE VOLTAGE
Full Scale Voltage
FSV
Total Measurement
Error (±)
VSOURCE
(see Section 4.1.2)
3
0.2
_ERR
POWER RATIO
Full Scale Range
Total Measurement
Error (±)
0
PRATIO
_ERR
100
%
1 LSB = 1.53m%
1.6
%
FSR = 80mV
3
%
FSR = 10mV to 40mV
CURRENT SENSE PEAK DETECTION
Peak Detector
Threshold Range
VTH
10
85
mV
Programmable via TH_SEL pin
Peak Detector
Duration Range
TDUR
1
4096
ms
Programmable via DUR_SEL
pin
VSENSE Peak
Detection
tFILTER
Revision 1.2 (09-27-10)
5
us
12
DATASHEET
SMSC EMC1702
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Table 2.2 Electrical Specifications (continued)
VDD = VBUS = 3V TO 24V, VPULLUP = 3V TO 5.5V, TA = -40°C TO 85°C,
ALL TYPICAL VALUES AT VDD = VPULLUP = 3.3V, VBUS = 12V, AND TA = 27°C UNLESS OTHERWISE NOTED.
CHARACTERISTIC
SYMBOL
Threshold Accuracy
(±)
VTH_ERR
MIN
TYP
MAX
UNIT
CONDITIONS
2
5
%
VTH = 80mV
EXTERNAL TEMPERATURE MONITORS
0.25
1
°C
+20°C < TDIODE < +110°C
0°C < TA < 85°C
0.5
2
°C
-40°C < TDIODE < 127°C
Temperature
Accuracy (±)
Temperature
Resolution
0.125
Diode Decoupling
Capacitor
CFILTER
Series Resistance
Canceled
RSERIES
2200
°C
2700
pF
Connected across external
diode, CPU, GPU, or AMD diode
100
Ohm
Sum of series resistance in both
DP and DN lines
INTERNAL TEMPERATURE MONITOR
Temperature
Accuracy (±)
0.25
Temperature
Resolution
0.125
1
°C
-5°C < TA < 85°C
2
°C
-40°C < TA < 85°C
°C
CONVERSION TIMES
First Conversion
Ready
tCONV_T
SMBus Delay
tSMB_D
180
300
ms
Time after power up before
temperature and voltage
measurements updated and
PRATIO updated
25
ms
Time before SMBus
communications should be sent
by host
DIGITAL I/O PINS (SMCLK, SMDATA, THERM, ALERT)
2.0
V
Input High Voltage
VIH
Input Low Voltage
VIL
0.8
V
Output Low Voltage
VOL
0.4
V
SMCLK, SMDATA
OD pins pulled up to VPULLUP
OD pin pulled to VPULLUP
4 mA current sink
APPLICATION NOTE: The EMC1702 is trimmed at the 80mV range for best accuracy.
SMSC EMC1702
13
DATASHEET
Revision 1.2 (09-27-10)
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
2.2
SMBus Electrical Specifications
Table 2.3 SMBus Electrical Specifications
VDD= VBUS = 3V to 24V, VPULLUP = 3V to 5.5V, TA = -40°C to 85°C Typical values are at TA = 27°C unless
otherwise noted.
CHARACTERISTIC
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
SMBUS INTERFACE
Input Capacitance
CIN
4
10
pF
SMBUS TIMING
Clock Frequency
fSMB
10
400
kHz
50
ns
Spike Suppression
tSP
Bus Free Time Start to
Stop
tBUF
1.3
us
Setup Time: Start
tSU:STA
0.6
us
Setup Time: Stop
tSU:STO
0.6
us
Data Hold Time
tHD:DAT
0
us
Data Setup Time
tSU:DAT
0.6
us
Clock Low Period
tLOW
1.3
us
Clock High Period
tHIGH
0.6
us
Clock/Data Fall time
tFALL
300
ns
Min = 20+0.1CLOAD ns
Clock/Data Rise time
tRISE
300
ns
Min = 20+0.1CLOAD ns
CLOAD
400
pF
Total per bus line
Capacitive Load
Revision 1.2 (09-27-10)
14
DATASHEET
SMSC EMC1702
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Chapter 3 Communications
3.1
System Management Bus Interface Protocol
The EMC1702 communicates with a host controller, such as an SMSC SIO, through the SMBus. The
SMBus is a two-wire serial communication protocol between a computer host and its peripheral
devices. A detailed timing diagram is shown in Figure 3.1. Stretching of the SMCLK signal is supported;
however, the EMC1702 will not stretch the clock signal.
T HIGH
T LOW
T HD:STA
T SU:STO
T FALL
SMCLK
T RISE
T HD:STA
T HD:DAT
T SU:DAT
T SU:STA
SMDATA
T BUF
S
P
S
S - Start Condition
P - Stop Condition
P
Figure 3.1 SMBus Timing Diagram
3.1.1
SMBus Start Bit
The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic
‘0’ state while the SMBus Clock line is in a logic ‘1’ state.
3.1.2
SMBus Address and RD / WR Bit
The SMBus Address Byte consists of the 7-bit client address followed by a 1-bit RD / WR indicator. If
this RD / WR bit is a logic ‘0’, the SMBus host is writing data to the client device. If this RD / WR bit
is a logic ‘1’, the SMBus host is reading data from the client device.
The EMC1702 SMBus address is determined by a single resistor connected between ground and the
ADDR_SEL pin as shown in Table 3.1.
Table 3.1 ADDR_SEL Resistor Setting
RESISTOR (5%)
SMBUS ADDRESS
RESISTOR (5%)
SMBUS ADDRESS
0
1001_100(r/w)
1600
0101_000(r/w)
100
1001_101(r/w)
2000
0101_001(r/w)
180
1001_110(r/w)
2700
0101_010(r/w)
300
1001_111(r/w)
3600
0101_011(r/w)
430
1001_000(r/w)
5600
0101_100(r/w)
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Table 3.1 ADDR_SEL Resistor Setting (continued)
RESISTOR (5%)
SMBUS ADDRESS
RESISTOR (5%)
SMBUS ADDRESS
560
1001_001(r/w)
9100
0101_100(r/w)
750
1001_010(r/w)
20000
0101_101(r/w)
1270
1001_011(r/w)
Open
0011_000(r/w)
All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.
3.1.3
SMBus ACK and NACK Bits
The SMBus client will acknowledge all data bytes that it receives (as well as the client address if it
matches and the ARA address if the ALERT pin is asserted). This is done by the client device pulling
the SMBus Data line low after the 8th bit of each byte that is transmitted.
The host will NACK (not acknowledge) the data received from the client by holding the SMBus data
line high after the 8th data bit has been sent.
3.1.4
SMBus Stop Bit
The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic
‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the EMC1702 detects an SMBus Stop
bit, and it has been communicating with the SMBus protocol, it will reset its client interface and prepare
to receive further communications.
3.1.5
SMBus Time-out
The EMC1702 includes an SMBus time-out feature. Following a 30ms period of inactivity on the
SMBus, the device will time-out and reset the SMBus interface.
The time-out functionality defaults to disabled and can be enabled by writing to the TIMEOUT bit (see
Section 5.12).
3.1.6
SMBus and I2C Compliance
The major differences between SMBus and I2C devices are highlighted here. For complete compliance
information, refer to the SMBus 2.0 specification.
1. Minimum frequency for SMBus communications is 10kHz.
2. The client protocol will reset if the clock is held at a logic ‘0’ for longer than 30ms. This time-out
functionality is disabled by default.
3. The client protocol will reset if both the clock and data lines are held at a logic ‘1’ for longer than
150us. This function is disabled by default.
4. I2C devices do not support the Alert Response Address functionality (which is optional for SMBus).
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3.2
SMBus Protocols
The EMC1702 is SMBus 2.0 compatible and supports Send Byte, Read Byte, Receive Byte, Write
Byte, Block Read, and Block Write as valid protocols. It will respond to the Alert Response Address
protocol but is not in full compliance.
All of the protocols listed below use the convention in Table 3.2.
Table 3.2 Protocol Format
DATA SENT
TO DEVICE
DATA SENT TO
THE HOST
# of bits sent
3.2.1
# of bits sent
Write Byte
The Write Byte is used to write one byte of data to the registers, as shown in Table 3.3:
Table 3.3 Write Byte Protocol
START
SLAVE
ADDRESS
WR
ACK
REGISTER
ADDRESS
ACK
REGISTER
DATA
ACK
STOP
1 -> 0
YYYY_YYY
0
0
XXh
0
XXh
0
0 -> 1
3.2.2
Read Byte
The Read Byte protocol is used to read one byte of data from the registers, as shown in Table 3.4.
Table 3.4 Read Byte Protocol
START
SLAVE
ADDRESS
WR
ACK
Register
Address
ACK
START
Slave
Address
RD
ACK
Register
Data
NACK
STOP
1 -> 0
YYYY_YYY
0
0
XXh
0
0 -> 1
YYYY_YYY
1
0
XXh
1
0 -> 1
3.2.3
Send Byte
The Send Byte protocol is used to set the internal address register pointer to the correct address
location. No data is transferred during the Send Byte protocol, as shown in Table 3.5.
Table 3.5 Send Byte Protocol
START
SLAVE
ADDRESS
WR
ACK
REGISTER
ADDRESS
ACK
STOP
1 -> 0
YYYY_YYY
0
0
XXh
0
0 -> 1
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3.2.4
Receive Byte
The Receive Byte protocol is used to read data from a register when the internal register address
pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads
of the same register, as shown in Table 3.6.
Table 3.6 Receive Byte Protocol
START
SLAVE
ADDRESS
RD
ACK
REGISTER DATA
NACK
STOP
1 -> 0
YYYY_YYY
1
0
XXh
1
0 -> 1
3.2.5
Block Write
The Block Write is used to write multiple data bytes to a group of contiguous registers, as shown in
Table 3.7. It is an extension of the Write Byte Protocol.
Table 3.7 Block Write Protocol
START
SLAVE
ADDRESS
WR
ACK
REGISTER
ADDRESS
ACK
REGISTER
DATA
ACK
1 ->0
YYYY_YYY
0
0
XXh
0
XXh
0
REGISTER
DATA
ACK
REGISTER
DATA
ACK
...
REGISTER
DATA
ACK
STOP
XXh
0
XXh
0
...
XXh
0
0 -> 1
3.2.6
Block Read
The Block Read is used to read multiple data bytes from a group of contiguous registers, as shown in
Table 3.8. It is an extension of the Read Byte Protocol.
Table 3.8 Block Read Protocol
START
SLAVE
ADDRESS
WR
ACK
REGISTER
ADDRESS
ACK
START
SLAVE
ADDRESS
RD
ACK
REGISTER
DATA
1->0
YYYY_YYY
0
0
XXh
0
1 ->0
YYYY_YYY
1
0
XXh
ACK
REGISTER
DATA
ACK
REGISTER
DATA
ACK
REGISTER
DATA
ACK
...
REGISTER
DATA
NACK
STOP
0
XXh
0
XXh
0
XXh
0
...
XXh
1
0 -> 1
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3.2.7
Alert Response Address
The ALERT output can be used as a processor interrupt or as an SMBus Alert when configured to
operate as an interrupt.
When it detects that the ALERT pin is asserted, the host will send the Alert Response Address (ARA)
to the general address of 0001_100xb. All devices with active interrupts will respond with their client
address, as shown in Table 3.9.
Table 3.9 Alert Response Address Protocol
START
ALERT
RESPONSE
ADDRESS
RD
ACK
DEVICE
ADDRESS
NACK
STOP
1 -> 0
0001_100
1
0
YYYY_YYY
1
0 -> 1
The EMC1702 will respond to the ARA in the following way if the ALERT pin is asserted.
1. Send Slave Address and verify that full slave address was sent (i.e. the SMBus communication
from the device was not prematurely stopped due to a bus contention event).
2. Set the MASK bit to clear the ALERT pin.
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Chapter 4 General Description
The EMC1702 is a combination high-side current sensing device with precision voltage and
temperature measurement capabilities. It measures the voltage developed across an external sense
resistor to represent the high-side current of a battery or voltage regulator. The EMC1702 also
measures the source voltage and uses these measured values to present a proportional power
calculation. The EMC1702 contains additional bi-directional peak detection circuitry to flag
instantaneous current spikes with programmable time duration and magnitude threshold. Finally, the
EMC1702 includes an external diode channel for temperature measurement as well as an internal
diode for ambient temperature measurements.
The EMC1702 current-sense measurement converts differential input voltage measured across an
external sense resistor to a proportional output voltage. This voltage is digitized using a variable
resolution (13-bit to 15-bit) Sigma-Delta ADC and transmitted via the SMBus or I2C protocol. The
current range allows for large variations in measured current with high accuracy and low voltage drop
across the resistor.
The supply voltage is also measured and stored. When combined with the sense resistor voltage
measurement the power provided from the source can be determined. Programmable limits on both
voltage and current levels are used to generate an interrupt.
The EMC1702 has two levels of monitoring. The first provides a maskable ALERT signal to the host
when the measured temperatures or voltages meet or exceed user programmable limits. This allows
the EMC1702 to be used as an independent thermal watchdog to warn the host of temperature hot
spots without direct control by the host. The second level of monitoring provides a non maskable
interrupt on the THERM pin if the measured values meet or exceed a second programmable limit.
The temperature measurement includes advanced features such as Resistance Error Correction
(REC), Beta Compensation (to support CPU diodes requiring the BJT/transistor model including 45nm
and 65nm processors) and automatic diode type detection. These features combine to provide a robust
solution for complex environmental monitoring applications.
A system diagram is shown in Figure 4.1.
Sense Resistor
DC Supply
DC Load
3.0V to 5.5V
SENSE+
SENSE-
DP
THERM
DN
SMCLK
2N3904 typ.
Host
SMDATA
ALERT
ADDR_SEL
VDD*
VDD
TH_SEL
GND
DUR_SEL
EMC1702
* Can either be DC Supply voltage or a separate supply
Figure 4.1 EMC1702 System Diagram
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4.1
Source Monitoring
The EMC1702 includes circuitry for both source current sensing and source voltage measurement.
From these measurements, a ratiometric value corresponding to the power delivered at the SENSE+
pin is provided.
4.1.1
Current Measurement
The EMC1702 includes a high-side current sensing circuit. This circuit measures the voltage, VSENSE,
induced across a fixed external current sense resistor, RSENSE, and stores a representative voltage as
a signed 11-bit number in the Sense Voltage Registers (see Section 5.22).
This circuitry is able to measure the direction of current flow (from SENSE+ to SENSE- or from
SENSE- to SENSE+). Current flowing from SENSE+ to SENSE- is defined as positive current. Current
flowing from SENSE- to SENSE+ is defined as negative.
The EMC1702 contains user programmable bipolar Full Scale Sense Ranges (FSSR) of ±10mV,
±20mV, ±40mV, or ±80mV (see Section 5.20). The default for this setting is ±80mV.
Each VSENSE measurement is averaged over a user programmable time (see Section 5.20). It is
compared against programmable high and low limits (see Section 5.25). If VSENSE exceeds (or drops
below) the respective limits, the ALERT pin may be asserted (the default operation is to enable current
sense interrupts on the ALERT pin).
The EMC1702 also contains user programmable current peak detection circuitry (see Section 4.1.4)
that will assert the THERM pin if a current spike is detected larger than the programmed threshold and
of longer duration than the programmed time. This circuitry is independent of VSENSE.
Full Scale Current (FSC) can be calculated from:
where:
FSC is the Full-Scale Current
FSR
FSC = --------------------R SENSE
FSR, the Full Scale Range, is either
10mV, 20mV, 40mV or 80mV (see
Section 5.20)
[1]
RSENSE is the external sense resistor
value
Actual source current through RSENSE can then be calculated using:
where:
ISOURCE is the actual source current
I SOURCE
FSC is the Full-Scale Current value
(from Equation [1])
V SENSE
= FSC × --------------------2, 047
[2]
VSENSE is the value read from the Sense
Voltage Registers, ignoring the four
lowest bits which are always zero (see
Section 5.22)
For example: Suppose the system is drawing 1.65A through a 10mΩ resistor and the FSR is set for
20mV. Therefore, by Equation [1], the FSC is 2A.
For a positive voltage the Sense Voltage Registers are read, ignoring the lower four bits since they are
always zero, as 69_8h (0110_1001_1000b or 1688d) which is 82.5% of the full scale source current.
This results in a calculated source current of 1.649A using Equation [2].
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For a negative voltage the Sense Voltage Registers are read as 96_8h, also ignoring the lower four
bits since they are always zero. To calculate source current the binary value is first converted from
two’s complement by inverting the bits and adding one:
96_8h = 1001_0110_1000b. Inverting equals 0110_1001_0111b (69_7h) and adding one gives
0110_1001_1000b (69_8h).
This results in the same calculated value as in the positive voltage case.
4.1.2
Voltage Measurement
Source voltage is measured on the supply side of the RSENSE resistor (SENSE+) and stored as an
unsigned 11-bit number in the Source Voltage Registers as VSOURCE (see Section 5.23).
Each VSOURCE measurement is averaged over a user programmable time (see Section 5.6 and
Section 5.19). The measurement is delayed by the programmed conversion rate. V SOURCE is
compared against programmable high, low, and critical limits (see Section 5.15, Section 5.16, and
Section 5.17). If the value meets or exceeds the high limits or drops below the low limits, the ALERT
pin may be asserted (default is to enable this function). If the value meets or exceeds the critical limit,
the THERM pin will be asserted (see Section 5.27).
Full Scale Voltage (FSV) is given by the maximum value of the Source Voltage Registers:
where:
FSV = 23.9883V
[3]
FSV is the Full-Scale Voltage (a
constant)
Actual source voltage at the SENSE+ pin can be calculated using:
where:
Source Voltage is the voltage at the
SENSE+ pin
V SOURCE
Source Voltage = FSV × -------------------------4, 094
FSV is the Full-Scale Voltage (from
Equation [3])
[4]
VSOURCE is the digital value read from
the Source Voltage Registers. Note that
the lowest five bits are always zero (see
Section 5.23)
For example: Suppose that the actual source voltage is 10.65V. The Source Voltage Registers are read
as VSOURCE = 71_Ah (0111_0001_1010b or 1818d) which is 44.4% of the full scale source voltage.
This results in a calculated source voltage of 10.65V using Equation [4].
Note that the actual source voltage may also be determined by scaling each bit set by the indicated
bit weighting as described in Section 5.23.
4.1.3
Power Calculation
The EMC1702 may be used to determine the average power provided at the source side of RSENSE
(SENSE+) using the value, PRATIO, contained in the Power Ratio Registers (see Section 5.24). The
value represents the % of maximum calculable power.
PRATIO is mathematically generated by multiplying the absolute values of VSENSE and VSOURCE (see
Section 4.1.1 and Section 4.1.2) and stored as a shifted 16-bit unsigned number. PRATIO is updated
whenever either VSENSE or VSOURCE is updated.
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Full Scale Power can be calculated from:
where:
FSP is the Full-Scale Power
FSP = FSC × FSV
FSC is the Full-Scale Current (from
Equation [1])
[5]
FSV is the Full-Scale Voltage (from
Equation [3])
Actual power drawn from the source can be calculated using:
where:
P RATIO
P SOURCE = FSP × ------------------65, 535
PSOURCE is the actual power
provided by the source
measured at SENSE+
FSP is the Full-Scale Power
(from Equation [5])
[6]
PRATIO is the value read from
the Power Ratio Registers
(see Section 5.24)
For example: Suppose that the actual source voltage is 10.65V and the source current through a 10mΩ
resistor is 1.65A. The FSC value is 2A per Equation [1]; thus, the expected power is 17.573W which
is 36.6% of the FSP value.
Reading the Power Ratio Registers will report P RATIO as 24,003d (0101_1101_1100_0011b or
5D_C3h), which is 36.6% of the full scale source power. This results in a calculated source power of
17.6W.
4.1.4
Current Peak Detection
The EMC1702 includes a hardware set instantaneous current peak detector. The peak detector
threshold and duration values may also be set via the SMBus.
The peak detector supports detection of current spikes that occur faster than the minimum current
sensing conversion time. This allows quick reaction to events requiring system-level response. The
circuitry compares the measured current against a user-defined threshold value and user-defined time
duration. If the measured current exceeds the threshold, an internal timer is started. If the timer
reaches the programmed duration, the THERM pin is asserted (see Figure 4.2 for an example of peak
current detection) and the PEAK status bit set.
The THERM pin will remain asserted until the Peak is no longer detected at which point it will be
released. The PEAK status bit will likewise be cleared.
The Peak Detection circuitry may also assert the ALERT pin. In this case, the ALERT pin must be
configured to operate in Comparator mode. If the ALERT pin is configured to operate in Interrupt mode,
the Peak Detection circuitry will not cause the ALERT pin to be asserted.
The Peak Detection circuitry includes filtering (tFILTER). When the instantaneous current exceeds the
threshold, it must drop below the threshold for a period of time greater than tFILTER before the timer is
reset. The Peak Detection circuitry works for current flowing in either direction through the sense
resistor (RSENSE).
APPLICATION NOTE: The Peak Detector circuitry works independently of the current measurement integration.
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Peak
Detector
Threshold
t < tFILTER
t < tFILTER
t > tFILTER
THERM Pin
t > tFILTER
t < tDURATION
t > tDURATION
Figure 4.2 Peak Detection Example
The peak detector threshold is determined upon device power up by the value of the resistor
connected between the TH_SEL pin and ground or via the SMBus (see Section 5.21). The resistor
selects one of 16 different VSENSE measurement limits (from 10mV to 85mV) as shown in Table 4.1.
Table 4.1 TH_SEL Resistor Setting
RESISTOR (5%)
PEAK DETECTION
THRESHOLD
RESISTOR (5%)
PEAK DETECTION
THRESHOLD
0
10mV
1600
50mV
100
15mV
2000
55mV
180
20mV
2700
60mV
300
25mV
3600
65mV
430
30mV
5600
70mV
560
35mV
9100
75mV
750
40mV
20000
80mV
1270
45mV
Open
85mV
The peak detector duration is determined upon device power up by the value of the resistor between
the DUR_SEL pin and ground or via the SMBus (see Section 5.21). The resistor selects one of 16
different time durations from 1 ms to 4.096s as shown in Table 4.2.
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Table 4.2 DUR_SEL Resistor Setting
RESISTOR (5%)
PEAK DETECTION MINIMUM
DURATION
(TDURATION)
RESISTOR (5%)
PEAK DETECTION MINIMUM
DURATION
(TDURATION)
0
1ms
1600
384ms
100
5ms
2000
512ms
180
26 ms
2700
768ms
300
51 ms
3600
1024ms
430
77 ms
5600
1536ms
560
102ms
9100
2048ms
750
128ms
20000
3072ms
1270
256ms
Open
4096ms
4.2
VDD Biasing Options
The wide device operating voltage range allows the EMC1702 to be powered from either the source
voltage or an external supply. The EMC1702 contains circuitry to detect the voltage supply level on
the VDD pin and enable an internal regulator as necessary.
4.3
Modes of Operation
The EMC1702 has multiple modes of operation as described here:
„
Fully Active - In this mode of operation, the device is measuring all temperature channels, source
voltage, and sense voltage. All data is updated at the end of the respective conversion and the
limits are checked. Writing to the One-Shot register will have no effect.
„
Current Sense only - In this mode of operation, the device is measuring source voltage and sense
voltage only. The temperature data is not updated. VSOURCE and VSENSE data are updated at the
end of the respective conversion and the limits are checked. Writing to the One-Shot register will
update the temperature measurements. This one-shot measurement may cause the ALERT or
THERM pins to be asserted if the measured temperature violates the respective limits.
„
Temperature only - In this mode of operation, the device is measuring the temperature channels
only. VSOURCE and VSENSE data are not updated. The temperature data is updated at the end of
the conversion and the limits are checked. Writing to the One-Shot register will update VSOURCE
and VSENSE. This one-shot measurement may cause the ALERT or THERM pins to be asserted if
the measured voltage or current sense readings meet or exceed the respective limits.
„
Standby (Stop) - In this mode of operation, the majority of circuitry is powered down to reduce
supply current. The temperature, source voltage, and sense voltage measurements are not
updated and the limits are not checked. In this mode of operation, the SMBus is fully active and
the part will return requested data. Writing to the One-Shot register (see Section 5.8) will enable
the device to update all measurement channels (temperature, VSOURCE, and VSENSE). This oneshot measurement may cause the ALERT or THERM pins to be asserted if any of the measured
values violate their respective limits. Once all the channels are updated, the device will return to
the Standby mode.
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4.4
ALERT Output
The ALERT pin is an open drain output and requires a pull-up resistor to VPULLUP and has two modes
of operation: Interrupt mode and Comparator mode. The mode of the ALERT output is selected via
the ALERT / COMP bit in the Configuration Register (see Section 5.5).
The ALERT pin modes apply to the High Limit only for all channels. The Low Limits and diode faults
will always cause the ALERT pin to behave as if it were in Interrupt mode.
The ALERT pin is used as an interrupt signal or as an SMBus Alert signal that allows an SMBus slave
to communicate an error condition to the master. One or more SMBus Alert outputs can be hard-wired
together.
4.4.1
ALERT Pin Interrupt Mode
When configured to operate in Interrupt mode, the ALERT pin asserts low when an out-of-limit
measurement (> high limit or < low limit) is detected on any temperature measurement and the
consecutive alert queue has been filled. The ALERT pin will also be asserted if a diode fault is
detected.
Additionally, the ALERT pin may be asserted if the measured current or the source voltage are out of
limit (> high limit or < low limit).
The ALERT pin will remain asserted as long as an out-of-limit condition remains. Once the out-of-limit
condition has been removed, the ALERT pin will remain asserted until the appropriate status bits are
cleared. The pin can be masked by setting the MASK_ALL bit. Once the ALERT pin has been masked,
it will be de-asserted and remain de-asserted until the MASK_ALL bit is cleared by the user. Any
interrupt conditions that occur while the ALERT pin is masked will update the Status Register normally.
When the ALERT pin is configured to operate in Interrupt mode, the Peak Detector circuitry will not
generate interrupts when a current peak is detected.
4.4.2
ALERT Pin Comparator Mode
When the ALERT pin is configured to operate in Comparator mode, it will be asserted if any of the
measured temperatures meets or exceeds the respective high limit. The ALERT pin will remain
asserted until all temperatures drop below the corresponding high limit minus the Tcrit Hysteresis value
(see Section 5.9).
Additionally, the ALERT pin may be asserted if the measured current or the source voltage meet or
exceed their respective high limit. The ALERT pin will remain asserted until the measured values drop
below the corresponding high limit minus the Vcrit Hysteresis value (see Section 5.27).
When the ALERT pin is asserted in Comparator mode, the corresponding high limit status bits will be
set. Reading these bits will not clear them until the ALERT pin is deasserted. Once the ALERT pin is
deasserted, the status bits will be automatically cleared.
The MASK_ALL (see Section 5.5) bit will not block the ALERT pin in this mode; however, individual
mask bits (see Section 5.11) will control the respective events that will assert the ALERT pin.
When the ALERT pin is configured to operate in Comparator mode and the Peak Detector circuitry is
linked to the ALERT pin, an interrupt will be generated when a current peak is detected (see
Section 5.19).
4.5
THERM Output
The THERM output is asserted independently of the ALERT output and cannot be masked. Whenever
any of the measured temperatures meets or exceeds the user programmed Tcrit Limit values for the
programmed number of consecutive measurements, the THERM output is asserted. Once it has been
asserted, it will remain asserted until all measured temperatures drops below the Tcrit Limit minus the
Tcrit Hysteresis (also programmable).
Additionally, the THERM pin will be asserted if the current sense Peak Detection circuitry has detected
a current spike (see Section 4.1.4). The THERM pin will remain asserted so long as the Peak Detection
circuitry continues to detect excessive instantaneous current (greater than the programmed threshold).
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As well, the THERM pin will be asserted if the measured current or source voltage meet or exceed
the user programmed Vcrit Limit values. In this case, the THERM pin will remain asserted until all
measured voltages drop below the Vcrit Limit minus the Vcrit Hysteresis (see Section 5.27).
4.6
Temperature Measurement
The EMC1702 can monitor the temperature of one externally connected diode. The external diode
channel is configured with Resistance Error Correction and Beta Compensation based on user settings
and system requirements.
The EMC1702 also measures the internal or ambient temperature.
The device contains programmable High, Low, and Tcrit limits for all measured temperature channels.
If the measured temperature drops below the Low limit or above the High limit, the ALERT pin can be
asserted (based on user settings). If the measured temperature meets or exceeds the Tcrit limit, the
THERM pin is asserted unconditionally, providing two tiers of temperature detection.
4.6.1
Resistance Error Correction
The EMC1702 includes active Resistance Error Correction to remove the effect of up to 100 ohms of
series resistance. Without this automatic feature, voltage developed across the parasitic resistance in
the remote diode path causes the temperature to read higher than what the true temperature is. The
error induced by parasitic resistance is approximately +0.7°C per ohm. Sources of series resistance
include bulk resistance in the remote temperature transistor junctions, series resistance in the CPU
resistance due to off-board connections, and resistance in the printed circuit board traces and package
leads. Resistance Error Correction in the EMC1702 eliminates the need to characterize and
compensate for parasitic resistance in the remote diode path.
The Resistance Error Correction can be disabled for each channel.
APPLICATION NOTE: When measuring AMD diodes, disable REC.
4.6.2
Beta Compensation
The forward current gain, or beta, of a transistor is not constant as emitter currents change. The
variation in beta causes an error in temperature reading. Compensating for this error is also known as
implementing the BJT or transistor model for temperature measurement.
For discrete transistors configured with the collector and base shorted together, the beta is generally
sufficiently high such that the percent change in beta variation is very small. For example, a 10%
variation in beta for two forced emitter currents with a transistor whose ideal beta is 50 would contribute
approximately 0.25°C error at 100°C. However for substrate transistors where the base-emitter junction
is used for temperature measurement and the collector is tied to the substrate, the proportional beta
variation will cause large error. For example, a 10% variation in beta for two forced emitter currents
with a transistor whose ideal beta is 0.5 would contribute approximately 8.25°C error at 100°C.
The Beta Compensation circuitry in the EMC1702 corrects for this beta variation to eliminate any error
which would normally be induced. It automatically detects the appropriate beta setting to use and will
properly recognize and measure a discrete diode.
4.6.3
Ideality Factor
The EMC1702 is designed for external diodes with an ideality factor of 1.008. Not all external diodes,
processor or discrete, will have this exact value. This variation of the ideality factor introduces error in
the temperature measurement which must be corrected for. This correction is typically done using
programmable offset registers. Since an ideality factor mismatch introduces an error that is a function
of temperature, this correction is only accurate within a small range of temperatures. To provide
maximum flexibility to the user, the EMC1702 provides a register for each external diode where the
ideality factor of the diode used may be programmed to eliminate errors across all temperatures.
SMSC EMC1702
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DATASHEET
Revision 1.2 (09-27-10)
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
APPLICATION NOTE: When monitoring a substrate transistor or CPU diode and beta compensation is enabled, the
Ideality Factor should not be adjusted. Beta Compensation automatically corrects for most
ideality errors.
4.6.4
Dynamic Averaging
The EMC1702 supports dynamic averaging. When enabled, this feature changes the conversion time
for all channels based on the selected conversion rate. This essentially increases the averaging factor
as shown in Table 4.3. The benefits of Dynamic Averaging are improved noise rejection due to the
longer integration time as well as less random variation on the temperature measurement.
Table 4.3 Dynamic Averaging Behavior
AVERAGING FACTOR (RELATIVE TO 11-BIT CONVERSION)
CONVERSION RATE
4.7
DYNAMIC AVERAGING
ENABLED
DYNAMIC AVERAGING
DISABLED
< 1 / sec
16x
1x
2 / sec
8x
1x
4 / sec
4x
1x
8 / sec
1x
1x
Diode Connections
For the EMC1702, the external diode channel supports any of the diode connections shown in
Figure 4.3.
to DP
to DP
to DP
to DN
to DN
to DN
Local
Ground
Typical remote
substrate transistor
i.e. CPU substrate PNP
Typical remote
discrete PNP transistor
i.e. 2N3906
Typical remote
discrete NPN transistor
i.e. 2N3904
Figure 4.3 Diode Connections
4.7.1
Diode Faults
The EMC1702 actively detects an open and short condition on each measurement channel. When a
diode fault is detected, the temperature data MSByte is forced to a value of 80h and the FAULT bit is
set in the Status Register.
Revision 1.2 (09-27-10)
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DATASHEET
SMSC EMC1702
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Chapter 5 Register Description
The registers shown in Table 5.1 are accessible through the SMBus. An entry of ‘-’ indicates that the
bit is not used and will always read ‘0’.
Table 5.1 Register Set in Hexadecimal Order
REGISTER
ADDRESS
R/W
REGISTER NAME
FUNCTION
DEFAULT
VALUE
PAGE
00h
R
Internal Diode Data
High Byte
Stores the integer data for the
Internal Diode (mirrored at address
38h)
00h
Page 32
01h
R
External Diode 1
Data High Byte
Stores the integer data for External
Diode 1 (mirrored at address 3Ah)
00h
Page 32
02h
R
Status
Stores the status bits for the
Internal Diode and External Diode
(mirrored at address 34h)
00h
Page 33
03h
R/W
Configuration
Controls the general operation of
the device (mirrored at address
09h)
00h
Page 34
04h
R/W
Conversion Rate
Controls the conversion rate for
updating measurement data
(mirrored at address 0Ah)
06h
(4/sec)
Page 35
05h
R/W
Internal Diode High
Limit
Stores the 8-bit high limit for the
Internal Diode (mirrored at address
0Bh)
55h
(85°C)
Page 36
06h
R/W
Internal Diode Low
Limit
Stores the 8-bit low limit for the
Internal Diode (mirrored at address
0Ch)
80h
(-128°C)
Page 36
07h
R/W
External Diode 1
High Limit High Byte
Stores the integer portion of the
high limit for External Diode 1
(mirrored at register 0Dh)
55h
(85°C)
Page 36
08h
R/W
External Diode 1 Low
Limit High Byte
Stores the integer portion of the
low limit for External Diode 1
(mirrored at register 0Eh)
80h
(-128°C)
Page 36
09h
R/W
Configuration
Controls the general operation of
the device (mirrored at address
03h)
00h
Page 34
0Ah
R/W
Conversion Rate
Controls the conversion rate for
updating measurement data
(mirrored at address 04h)
06h
(4/sec)
Page 35
0Bh
R/W
Internal Diode High
Limit
Stores the 8-bit high limit for the
Internal Diode (mirrored at address
05h)
55h
(85°C)
Page 36
0Ch
R/W
Internal Diode Low
Limit
Stores the 8-bit low limit for the
Internal Diode (mirrored at address
06h)
80h
(-128°C)
Page 36
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DATASHEET
Revision 1.2 (09-27-10)
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Table 5.1 Register Set in Hexadecimal Order (continued)
REGISTER
ADDRESS
R/W
REGISTER NAME
FUNCTION
0Dh
R/W
External Diode 1
High Limit High Byte
Stores the integer portion of the
high limit for External Diode 1
(mirrored at register 07h)
55h
(85°C)
Page 36
0Eh
R/W
External Diode 1 Low
Limit High Byte
Stores the integer portion of the
low limit for External Diode 1
(mirrored at register 08h)
80h
(-128°C)
Page 36
0Fh
W
One-Shot
A write to this register initiates a
one-shot update.
00h
Page 36
10h
R
External Diode 1
Data Low Byte
Stores the fractional data for
External Diode 1 (mirrored at
address 3Bh)
00h
Page 32
13h
R/W
External Diode 1
High Limit Low Byte
Stores the fractional portion of the
high limit for External Diode 1
00h
Page 36
14h
R/W
External Diode 1 Low
Limit Low Byte
Stores the fractional portion of the
low limit for External Diode 1
00h
Page 36
19h
R/W
External Diode 1 Tcrit
Limit
Stores the 8-bit critical temperature
limit for External Diode 1
64h
(100°C)
Page 37
1Bh
R-C
External Diode Fault
Stores status bits indicating which
external diode detected a diode
fault
00h
Page 37
1Fh
R/W
Channel Mask
Register
Controls the masking of individual
channels
00h
Page 37
20h
R/W
Internal Diode Tcrit
Limit
Stores the 8-bit critical temperature
limit for the Internal Diode
64h
(100°C)
Page 37
21h
R/W
Tcrit Hysteresis
Stores the 8-bit hysteresis value
that applies to all THERM limits
0Ah
(10°C)
Page 37
22h
R/W
Consecutive Alert
Controls the number of out-of-limit
conditions that must occur before
an interrupt is asserted
70h
Page 38
25h
R/W
External Diode 1
Beta Configuration
Stores the Beta Compensation
circuitry settings for External Diode
1
10h
Page 39
27h
R/W
External Diode 1
Ideality Factor
Stores the ideality factor for
External Diode 1
12h
(1.008)
Page 40
29h
R
Internal Diode Data
Low Byte
Stores the fractional data for the
Internal Diode (mirrored at register
39h)
00h
Page 32
34h
R-C
Status
Stores the status bits for the
measured temperature channels,
Current Sense circuitry, and Peak
Detector circuitry.
00h
Page 33
35h
R-C
High Limit Status
Status bits for the High Limits
00h
Page 41
36h
R-C
Low Limit Status
Status bits for the Low Limits
00h
Page 42
Revision 1.2 (09-27-10)
30
DATASHEET
DEFAULT
VALUE
PAGE
SMSC EMC1702
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Table 5.1 Register Set in Hexadecimal Order (continued)
REGISTER
ADDRESS
R/W
REGISTER NAME
FUNCTION
DEFAULT
VALUE
PAGE
37h
R-C
Crit Limit Status
Status bits for the Tcrit and Vcrit
Limits
00h
Page 42
38h
R
Internal Diode High
Byte
Stores the integer data for the
Internal Diode
00h
Page 32
39h
R
Internal Diode Low
Byte
Stores the fractional data for the
Internal Diode
00h
Page 32
3Ah
R
External Diode 1
High Byte
Stores the integer data for External
Diode 1
00h
Page 32
3Bh
R
External Diode 1 Low
Byte
Stores the fractional data for
External Diode 1
00h
Page 32
40h
R/W
Averaging Control
Controls the digital averaging
setting for the all external diode
channels
00h
Page 43
Current Sense Control and Measurement
50h
R/W
Voltage Sampling
Configuration
Controls voltage sampling
80h
Page 43
51h
R/W
Current Sense
Sampling
Configuration
Controls the current sensing
sampling and update times
03h
Page 44
52h
R/W
Peak Detection
Config
Controls the peak detection
configuration
00h
Page 46
54h
R
Sense Voltage High
Byte
Stores the voltage measured
across RSENSE
00h
Page 48
55h
R
Sense Voltage Low
Byte
00h
Page 48
58h
R
Source Voltage High
Byte
00h
Page 49
59h
R
Source Voltage Low
Byte
00h
Page 49
5Bh
R
Power Ratio High
Byte
00h
Page 49
5Ch
R
Power Ratio Low
Byte
00h
Page 49
Stores voltage measured on the
source side of RSENSE
Stores the power ratio value
Current Sense and Source Voltage Limits
60h
R/W
Sense Voltage High
Limit
Stores the high limit for VSENSE
7Fh
Page 50
61h
R/W
Sense Voltage Low
Limit
Stores the low or negative limit for
the VSENSE voltage
80h
Page 50
64h
R/W
Source Voltage High
Limit
Stores the high limit for the voltage
on the source side of RSENSE
FFh
Page 50
65h
R/W
Source Voltage Low
Limit
Stores the low limit for the voltage
on the source side of RSENSE
00h
Page 50
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DATASHEET
Revision 1.2 (09-27-10)
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Table 5.1 Register Set in Hexadecimal Order (continued)
REGISTER
ADDRESS
R/W
REGISTER NAME
FUNCTION
DEFAULT
VALUE
PAGE
66h
R/W
Sense Voltage Vcrit
Limit
Stores the critical limit for VSENSE
7Fh
Page 50
68h
R/W
Source Voltage Vcrit
Limit
Stores the critical limit for the
voltage on the source side of
RSENSE
FFh
Page 50
69h
R/W
Sense Vcrit
Hysteresis
Stores the hysteresis for the
VSENSE Vcrit limit
0Ah
Page 50
6Ah
R/W
Source Voltage Vcrit
Hysteresis
Stores the hysteresis for the
source voltage Vcrit limits
0Ah
Page 50
FCh
R
Product Features
Stores information about which pin
controlled product features are set
00h
Page 51
FDh
R
Product ID
Stores a fixed value that identifies
each product
39h
Page 51
FEh
R
SMSC ID
Stores a fixed value that
represents SMSC
5Dh
Page 52
FFh
R
Revision
Stores a fixed value that
represents the revision number
82h
Page 52
5.1
Data Read Interlock
When any measurement channel high byte register is read (temperature or VSOURCE or VSENSE), the
corresponding low byte is copied into an internal ‘shadow’ register. The user is free to read the low
byte at any time and be guaranteed that it will correspond to the previously read high byte. Regardless
if the low byte is read or not, reading from the same high byte register again will automatically refresh
this stored low byte data.
5.2
Block Mode Support
All of the status and temperature data may be retrieved with a block read of 8 bytes starting at register
address 34h.
All of the voltage measurement, current sense data, and power information may be retrieved with a
block read of 6 bytes starting at register address 54h.
5.3
Temperature Data Registers
Table 5.2 Temperature Data Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
00h
R
Internal Diode
High Byte
Sign
64
32
16
8
4
2
1
00h
R
Internal Diode
Low Byte
0.5
0.25
0.125
-
-
-
-
-
00h
38h
29h
39h
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SMSC EMC1702
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Table 5.2 Temperature Data Registers (continued)
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
01h
R
External Diode
1 High Byte
Sign
64
32
16
8
4
2
1
00h
R
External Diode
1 Low Byte
0.5
0.25
0.125
-
-
-
-
-
00h
3Ah
10h
3Bh
As shown in Table 5.2, temperature data is stored as an 11-bit value with the high byte representing
the integer value and the low byte representing the fractional value left justified to occupy the MSBits.
Table 5.3 Temperature Data Format
TEMPERATURE (°C)
BINARY
HEX (AS READ BY REGISTERS)
Diode Fault
1000_0000_000b
80_00h
-63.875
1100_0000_001b
C0_20h
-63
1100_0001_000b
C1_00h
-1
1111_1111_000b
FF_00h
-0.125
1111_1111_111b
FF_E0h
0
0000_0000_000b
00_00h
0.125
0000_0000_001b
00_20h
1
0000_0001_000b
01_00h
63
0011_1111_000b
3F_00h
64
0100_0000_000b
40_00h
65
0100_0001_000b
41_00h
127
0111_1111_000b
7F_00h
127.875
0111_1111_111b
7F_E0h
5.4
Status Register
Table 5.4 Status Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
02h
R
Status
BUSY
PEAK
-
HIGH
LOW
FAULT
CRIT
-
00h
34h
The Status Register reports general error conditions. To identify specific channels, refer to
Section 5.10, Section 5.15, Section 5.16, and Section 5.17. The individual Status Register bits are
cleared when the appropriate High Limit, Low Limit, or Crit Limit status register has been read or
cleared.
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DATASHEET
Revision 1.2 (09-27-10)
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Bit 7 - BUSY - This bit indicates that one of the ADCs is currently converting. This bit does not cause
either the ALERT or THERM pins to be asserted.
Bit 6 - PEAK - This bit is set when the Peak Detector circuitry has detected a current peak that is
greater than the programmed threshold for longer than the programmed duration. This bit is not sticky
and will be cleared when the condition has been removed. When set, the THERM pin or ALERT pin
(Comparator mode only) may be asserted (see Section 5.19).
Bit 4 - HIGH - This bit is set when any of the temperature channels meets or exceeds its programmed
high limit. This bit will also be set if the VSENSE or VSOURCE channels meet or exceed their respective
high limits. See the High Limit Status Register for specific channel information (Section 5.15). When
set, the ALERT pin is asserted.
Bit 3 - LOW - This bit is set when any of the temperature channels drops below its programmed low
limit. This bit will also be set if the VSENSE or VSOURCE channels drop below their respective low limits.
See the Low Limit Status Register for specific channel information (Section 5.16). When set, the
ALERT pin is asserted.
Bit 2 - FAULT - This bit is set when a diode fault is detected on any of the external diode channels.
See the External Diode Fault Register for specific channel information (Section 5.10). When set, the
ALERT pin is asserted.
Bit 1 - CRIT - This bit is set when any of the temperature channels meets or exceeds its programmed
Tcrit limit. This bit will also be set if the VSENSE or VSOURCE channels meet or exceed their respective
Vcrit limits (see the Section 5.17, "Crit Limit Status Register" for specific channel information). When
set, the THERM pin is asserted. This bit is not sticky and will be cleared when the error condition has
been removed.
5.5
Configuration Register
Table 5.5 Configuration Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
03h
R/W
Configuration
MASK_
ALL
TMEAS
/STOP
ALERT/
COMP
DIS_
REC1
-
IMEAS
/STOP
DAVG_
DIS
-
00h
09h
The Configuration Register controls the basic operation of the device. This register is fully accessible
at either address.
Bit 7 - MASK_ALL - Masks the ALERT pin from asserting.
„
‘0’ (default) - The ALERT pin is not masked. If any of the appropriate status bits are set, the ALERT
pin will be asserted.
„
‘1’ - The ALERT pin is masked if configured in Interrupt mode (see Section 4.4.1, "ALERT Pin
Interrupt Mode"). The Status Registers will be updated normally.
Bit 6 - TMEAS / STOP - Controls Temperature measurement modes.
„
‘0’ (default) - The device is active, measuring all of the temperature channels.
„
‘1’ - The device is not measuring temperature channels. It will update all of the temperature
channels when a One-Shot command is given.
Bit 5 - ALERT/COMP - Controls the operation of the ALERT pin.
„
‘0’ (default) - The ALERT pin acts in Interrupt mode as described in Section 4.4.1.
„
‘1’ - The ALERT pin acts in Comparator mode as described in Section 4.4.2. In this mode the
MASK_ALL bit is ignored.
Revision 1.2 (09-27-10)
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SMSC EMC1702
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Bit 4 - DIS_REC1- Disables the Resistance Error Correction (REC) for External Diode 1.
„
‘0’ (default) - REC is enabled for External Diode 1.
„
‘1’ - REC is disabled for External Diode 1.
Bit 2 - IMEAS / STOP - Controls VSENSE and VSOURCE measurement modes.
„
‘0’ (default) - The device is measuring source voltage and sense voltage.
„
‘1’ -The device is not measuring the source voltage and sense voltage. It will update VSENSE and
VSOURCE registers when a One-Shot command is given.
Bit 1 - DAVG_DIS - Disables the dynamic averaging feature on all temperature channels.
5.6
„
‘0’ (default) - The dynamic averaging feature is enabled. All temperature channels will be converted
with an averaging factor that is based on the conversion rate as shown in Table 4.3.
„
‘1’ - The dynamic averaging feature is disabled. All temperature channels will be converted with a
maximum averaging factor of 1x (equivalent to 11-bit conversion).
Conversion Rate Register
Table 5.6 Conversion Rate Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
04h
R/W
Conversion
Rate
-
-
-
-
B3
B2
B1
B0
T_CONV[2:0]
DEFAULT
06h
(4/sec)
0Ah
The Conversion Rate Register controls how often the VSOURCE and temperature measurement
channels are updated and compared against the limits. This register is fully accessible at either
address.
Bits 2-0 - T_CONV[2:0] - Determines the conversion rate as shown in Table 5.7. This conversion rate
applies to temperature measurement and source voltage measurement.
Table 5.7 Conversion Rate
T_CONV[2:0]
2
1
0
CONVERSION RATE
0
0
0
1 per 16 sec
0
0
1
1 per 8 sec
0
1
0
1 per 4 sec
0
1
1
1 per 2 sec
1
0
0
1 per sec
1
0
1
2 per sec
1
1
0
4 per sec (default)
1
1
1
8 per sec
SMSC EMC1702
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DATASHEET
Revision 1.2 (09-27-10)
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
5.7
Temperature Limit Registers
Table 5.8 Temperature Limit Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
05h
R/W
Internal Diode
High Limit
Sign
64
32
16
8
4
2
1
55h
(85°C)
R/W
Internal Diode
Low Limit
Sign
64
32
16
8
4
2
1
80h
(-128°C)
R/W
External
Diode 1 High
Limit High
Byte
Sign
64
32
16
8
4
2
1
55h
(85°C)
13h
R/W
External
Diode 1 High
Limit Low
Byte
0.5
0.25
0.125
-
-
-
-
-
00h
08h
R/W
External
Diode 1 Low
Limit High
Byte
Sign
64
32
16
8
4
2
1
80h
(-128°C)
R/W
External
Diode 1 Low
Limit Low
Byte
0.5
0.25
0.125
-
-
-
-
-
00h
0Bh
06h
0Ch
07h
0Dh
0Eh
14h
The device contains both high and low limits for the temperature channels. If the measured
temperature meets or exceeds the high limit, the corresponding status bit is set, and the ALERT pin
is asserted. Likewise, if the measured temperature is less than or equal to the low limit, the
corresponding status bit is set and the ALERT pin is asserted.
The limit registers with multiple addresses are fully accessible at either address.
When the device is Standby or Current Sense only mode, updating the limit registers will have no effect
until the next conversion cycle occurs. This conversion cycle can be initiated via a write to the OneShot Register or by clearing the TMEAS_STOP bit in the Configuration Register (see Section 5.5).
5.8
One-Shot Register
Table 5.9 One-Shot Register
ADDR.
R/W
REGISTER
0Fh
W
One-Shot
B7
B6
B5
B4
B3
B2
B1
B0
Writing to this register initiates a single conversion cycle. Data
is not stored and always reads 00h
DEFAULT
00h
Writing to the One-Shot register will automatically update those channels that are not currently
measured. If the device is Fully Active, writing to this register will have no effect. If the IMEAS_STOP
bit is set, writing to this register will update the VSENSE and VSOURCE voltage measurements. If the
TMEAS_STOP bit is set, writing to this register will update all of the temperature channel
measurements.
Revision 1.2 (09-27-10)
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DATASHEET
SMSC EMC1702
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
5.9
Tcrit Limit Registers
Table 5.10 Tcrit Limit Registers
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
19h
R/W
External
Diode 1 Tcrit
Limit
Sign
64
32
16
8
4
2
1
64h
(100°C)
20h
R/W
Internal Diode
Tcrit Limit
Sign
64
32
16
8
4
2
1
64h
(100°C)
21h
R/W
Tcrit
Hysteresis
-
64
32
16
8
4
2
1
0Ah
(10°C)
The Tcrit Limit Registers are used to determine whether a critical thermal event has occurred. If the
measured temperature meets or exceeds the Tcrit Limit, the THERM pin is asserted.
Unlike the ALERT pin, the THERM pin cannot be masked. Additionally, the THERM pin will be released
once the temperature drops below the corresponding threshold minus the Tcrit Hysteresis.
5.10
External Diode Fault Register
Table 5.11 External Diode Fault Register
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
1Bh
R-C
External
Diode Fault
-
-
-
-
-
-
E1FLT
-
00h
The External Diode Fault Register indicates that External Diode 1 caused the FAULT bit in the Status
Register to be set. This register is cleared when it is read.
Bit 1 - E1FLT - This bit is set if the External Diode 1 channel reported a diode fault.
5.11
Channel Mask Register
Table 5.12 Channel Mask Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
1Fh
R/W
Channel
Mask
VSENSE_
MASK
VSRC_
MASK
PEAK_
MASK
-
-
-
E1
MASK
INT
MASK
00h
The Channel Mask Register controls individual channel masking. When a channel is masked, the
ALERT pin will not be asserted when the masked channel reads a diode fault or out-of-limit error. The
channel mask does not mask the THERM pin.
Bit 7 - VSENSE_MASK - Masks the ALERT pin from asserting when the VSENSE value meets or
exceeds the high limit or drops below the low limit. This bit will have no effect on the THERM pin
functionality.
„
‘0’ (default) - The VSENSE voltage channel will cause the ALERT pin to be asserted (if enabled).
„
‘1’ - The VSENSE voltage channel will not cause the ALERT pin to be asserted (if enabled).
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Datasheet
Bit 6 - VSRC_MASK - Masks the ALERT pin from asserting when the VSOURCE value meets or
exceeds the high limit or drops below the low limit. This bit will have no effect on the THERM pin
functionality.
„
‘0’ (default) - The VSOURCE voltage channel will cause the ALERT pin to be asserted (if enabled).
„
‘1’ - The VSOURCE voltage channel will not cause the ALERT pin to be asserted (if enabled).
BIt 5 - PEAK_MASK - Masks the ALERT pin from asserting when the Peak Detector circuitry detects
a current spike. This bit will have no effect on the THERM pin functionality.
„
‘0’ (default) - The Peak Detector circuitry will cause the ALERT pin to be asserted (if enabled).
„
‘1’ - The Peak Detector circuitry will not cause the ALERT pin to be asserted (if enabled).
Bit 1 - E1MASK - Masks the ALERT pin from asserting when the External Diode 1 channel is out-oflimit or reports a diode fault.
„
‘0’ (default) - The External Diode 1 channel will cause the ALERT pin to be asserted if it is out-oflimit or reports a diode fault.
„
‘1’ - The External Diode 1 channel will not cause the ALERT pin to be asserted if it is out-of-limit
or reports a diode fault.
Bit 0 - INTMASK - Masks the ALERT pin from asserting when the Internal Diode temperature is outof-limit.
5.12
„
‘0’ (default) - The Internal Diode channel will cause the ALERT pin to be asserted if it is out-of-limit.
„
‘1’ - The Internal Diode channel will not cause the ALERT pin to be asserted if it is out-of-limit.
Consecutive Alert Register
Table 5.13 Consecutive Alert Register
ADDR
R/W
REGISTER
B7
22h
R/W
Consecutive
Alert
TIME
OUT
B6
B5
B4
CTHRM[2:0]
B3
B2
B1
CALRT[2:0]
B0
DEFAULT
-
70h
The Consecutive Alert Register determines how many times an out-of-limit error or diode fault must
be detected in consecutive measurements before the interrupt status registers are asserted. This
applies to temperature limits only. The voltage measurement and current sense measurements are
controlled via the Voltage Channel Configuration register and Current Sense Configuration register
respectively (see Section 5.19 and Section 5.20).
When the ALERT pin is configured as a comparator, the consecutive alert counter will ignore diode
fault and low limit errors and only increment if the measured temperature meets or exceeds the High
Limit.
Each measurement channel has a separate fault queue associated with the high limit, low limit, and
diode fault condition except the internal diode.
Bit 7 - TIMEOUT - Determines whether the SMBus Timeout function is enabled.
„
‘0’ (default) - The SMBus Timeout feature is disabled. The SMCLK line can be held low indefinitely
without the device resetting its SMBus protocol.
„
‘1’ - The SMBus Timeout feature is enabled. If the SMCLK line is held low for more than 30ms,
the device will reset the SMBus protocol.
Bits 6-4 - CTHRM[2:0] - Determines the number of consecutive measurements that must exceed the
corresponding Tcrit Limit before the THERM pin is asserted.
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High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Bits 3-1 - CALRT[2:0] - Determines the number of consecutive measurements that must have an outof-limit condition or diode fault before the ALERT pin is asserted. All temperature channels use this
value to set the respective counters. The bits are decoded as shown in Table 5.14. The default setting
is 1 consecutive out-of-limit conversion.
Table 5.14 Consecutive ALERT / THERM Settings
5.13
NUMBER OF CONSECUTIVE OUT-OF-LIMIT
MEASUREMENTS
2
1
0
0
0
0
1
(default for CALRT[2:0])
0
0
1
2
0
1
1
3
1
1
1
4
(default for CTHRM[2:0])
Beta Configuration Registers
Table 5.15 Beta Configuration Registers
ADDR.
R/W
REGISTER
B7
B6
B5
B4
25h
R/W
External
Diode 1 Beta
Configuration
-
-
-
AUTO1
B3
B2
B1
B0
DEFAULT
BETA1[3:0]
This register is used to set the Beta Compensation factor that is used for the external diode channels.
Bit 4 - AUTO - Enables the Beta Compensation factor autodetection function.
„
‘0’ - The Beta Compensation Factor autodetection circuitry is disabled. The External Diode will
always use the Beta Compensation factor set by the BETAx[3:0] bits.
„
‘1’ (default) - The Beta Compensation factor autodetection circuitry is enabled. At the beginning of
every conversion, the optimal Beta Compensation factor setting will be determined and applied.
The BETAx[3:0] bits will be automatically updated to indicate the current setting.
Bit 3-0 - BETA[3:0] - These bits always reflect the current beta configuration settings. If autodetection
circuitry is enabled, these bits will be updated automatically and writing to these bits will have no effect.
If the autodetection circuitry is disabled, these bits will determine the beta configuration setting that is
used for their respective channels.
Care should be taken when setting the BETA1[3:0] bits when the autodetection circuitry is disabled. If
the Beta Compensation factor is set at a beta value that is higher than the transistor beta, the circuit
may introduce measurement errors. When measuring a discrete thermal diode (such as 2N3904) or a
CPU diode that functions like a discrete thermal diode (such as an AMD processor diode), the
BETA1[3:0] bits should be set to ‘1111b’.
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High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Table 5.16 Beta Compensation
BETA1[3:0]
AUTO
MINIMUM BETA
3
2
1
0
0
0
0
0
0
0.050
0
0
0
0
1
0.066
0
0
0
1
0
0.087
0
0
0
1
1
0.114
0
0
1
0
0
0.150
0
0
1
0
1
0.197
0
0
1
1
0
0.260
0
0
1
1
1
0.342
0
1
0
0
0
0.449
0
1
0
0
1
0.591
0
1
0
1
0
0.778
0
1
0
1
1
1.024
0
1
1
0
0
1.348
0
1
1
0
1
1.773
0
1
1
1
0
2.333
0
1
1
1
1
Disabled
1
X
X
X
X
Automatically detected
5.14
External Diode Ideality Factor Registers
Table 5.17 Ideality Configuration Registers
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
27h
R/W
External
Diode 1
Ideality
Factor
-
-
0
1
0
B2
B1
IDCF1[2:0]
B0
DEFAULT
12h
These registers store the ideality factors that are applied to the external diodes. Table 5.18 defines
each setting and the corresponding ideality factor. Beta Compensation and Resistance Error Correction
automatically correct for most diode ideality errors; therefore, it is not recommended that these settings
be updated without consulting SMSC.
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High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Table 5.18 Ideality Factor Look-Up Table (Diode Model)
SETTING
FACTOR
10h
1.0053
11h
1.0066
12h
1.0080
13h
1.0093
14h
1.0106
15h
1.0119
16h
1.0133
17h
1.0146
APPLICATION NOTE: When measuring a 65nm Intel CPUs, the Ideality Setting should be the default 12h. When
measuring 45nm Intel CPUs, the Ideality Setting should be 15h.
5.15
High Limit Status Register
Table 5.19 High Limit Status Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
35h
R-C
High Limit
Status
VSENSE_
HIGH
VSRC_
HIGH
-
-
-
-
E1
HIGH
I
HIGH
00h
The High Limit Status Register contains the status bits that are set when a temperature or voltage
channel high limit is met or exceeded. If any of these bits are set, the HIGH status bit in the Status
Register is set. Reading from the High Limit Status Register will clear all bits if the error condition has
been removed. Reading from the register will also clear the HIGH status bit in the Status Register if
the error condition has been removed.
If not masked, the ALERT pin will be set if the programmed number of consecutive alert counts have
been met and any of these status bits are set. Once set, the status bits will remain set until read unless
the ALERT pin is configured as a comparator output (see Section 4.4.2).
Bit 7 - VSENSE_HIGH - This bit is set when the VSENSE value meets or exceeds its programmed high
limit.
Bit 6 - VSRC_HIGH - This bit is set when the VSOURCE value meets or exceeds its programmed high
limit.
Bit 1 - E1HIGH - This bit is set when the External Diode 1 channel meets or exceeds its programmed
high limit.
Bit 0 - IHIGH - This bit is set when the Internal Diode channel meets or exceeds its programmed high
limit.
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Datasheet
5.16
Low Limit Status Register
Table 5.20 Low Limit Status Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
36h
R-C
Low Limit
Status
VSENSE_
LOW
VSRC_
LOW
-
-
-
-
E1
LOW
ILOW
00h
The Low Limit Status Register contains the status bits that are set when a temperature or voltage
channel drops below the low limit. If any of these bits are set, the LOW status bit in the Status Register
is set. Reading from the Low Limit Status Register will clear all bits. Reading from the register will also
clear the LOW status bit in the Status Register if the error status has been removed.
If not masked, the ALERT pin will be set if the programmed number of consecutive alert counts have
been met and any of these status bits are set.
Once set, the status bits will remain set until read.
Bit 7 - VSENSE_LOW - This bit is set when the VSENSE value drops below its programmed low limit.
Bit 6 - VSRC_LOW - This bit is set when the VSOURCE value drops below its programmed low limit.
Bit 1 - E1LOW - This bit is set when the External Diode 1 channel drops below its programmed low
limit.
Bit 0 - ILOW - This bit is set when the Internal Diode channel drops below its programmed low limit.
5.17
Crit Limit Status Register
Table 5.21 Crit Limit Status Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
37h
R-C
Crit Limit
Status
VSENSE_
VCRIT
VSRC_
VCRIT
-
-
-
-
E1
TCRIT
ITCRIT
00h
The Crit Limit Status register contains the status bits that are set when a temperature or voltage
channel Tcrit or Vcrit Limit is met or exceeded (see Section 5.9 and Section 5.27). If any of these bits
are set, the CRIT status bit in the Status register is set. Reading from the Crit Limit Status register will
not clear the status bits. Once the temperature drops below the Tcrit Limit minus the Tcrit Hysteresis,
the corresponding status bits will be automatically cleared. Once the voltage drops below the Vcrit Limit
minus the Vcrit Hysteresis, the corresponding status bits will be automatically cleared. The CRIT bit in
the Status register will be cleared when all individual bits are cleared.
Bit 7 - VSENSE_VCRIT - This bit is set when the VSENSE value meets or exceeds its programmed
Vcrit limit. When set, this bit will assert the THERM pin.
Bit 6 - VSRC_VCRIT- This bit is set when the VSOURCE value meets or exceeds its programmed Vcrit
limit. When set, this bit will assert the THERM pin.
Bit 1 - E1TCRIT - This bit is set when the External Diode 1 channel meets or exceeds its programmed
Tcrit limit. When set, this bit will assert the THERM pin.
Bit 0 - ITCRIT - This bit is set when the Internal Diode channel meets or exceeds its programmed Tcrit
limit. When set, this bit will assert the THERM pin.
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High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
5.18
Averaging Control Register
Table 5.22 Filter Configuration Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
40h
R/W
Filter Control
-
-
-
-
-
-
B1
B0
DEFAULT
AVG1[1:0]
00h
The Averaging Control Register controls the digital averaging on the external diode channels.
Bits 1-0 - AVG1[1:0] - Controls the digital averaging that is applied to the External Diode 1 temperature
measurements as shown in Table 5.23.
Table 5.23 Averaging Settings
AVGX[1:0]
5.19
1
0
AVERAGING
0
0
Disabled (default)
0
1
2x
1
0
4x
1
1
8x
Voltage Sampling Configuration Register
Table 5.24 Voltage Sampling Configuration Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
50h
R/W
Voltage
Sampling
Config
PK_
ALERT_
THERM
-
-
-
B3
B2
V_QUEUE[1:0]
B1
B0
DEFAULT
V_AVG[1:0]
80h
The Voltage Sampling Configuration register controls functionality for the source voltage measurement
and Peak Detector circuitry.
Bit 7 - PK_ALERT_THERM - Determines whether the ALERT pin or THERM pin is asserted if the Peak
Detector detects a current spike. If configured to assert the ALERT pin, the PEAK_MASK can block
the pin assertion normally. If configured to assert the THERM pin, it will not be masked.
„
‘0’ - The Peak Detector circuitry will assert the ALERT pin when a current spike is detected. The
ALERT pin must be configured to operate in Comparator mode or it will not be asserted.
„
‘1’ (default) - The Peak Detector circuitry will assert the THERM pin when a current spike is
detected.
Bits 3 - 2 - V_QUEUE[1:0] - Determine the number of consecutive measurements that VSOURCE must
exceed the limits before flagging an interrupt.
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High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Table 5.25 Voltage Queue Settings
V_QUEUE[1:0]
1
0
NUMBER OF CONSECUTIVE OUT-OF-LIMIT MEASUREMENTS
0
0
1 (default)
0
1
2
1
0
3
1
1
4
Bits 1-0 - V_AVG[1:0] - Controls the digital averaging that is applied to the source voltage
measurement, as shown in Table 5.26.
Table 5.26 Voltage Averaging Settings
V_AVG[1:0]
5.20
1
0
AVERAGING
0
0
Disabled (default)
0
1
2x
1
0
4x
1
1
8x
Current Sense Sampling Configuration Register
Table 5.27 Current Sense Sampling Configuration Register
ADDR
R/W
REGISTER
B7
51h
R/W
Current Sense
Sampling Config
B6
B5
CS_QUEUE
[1:0]
B4
CS_SAMP_
AVG [1:0]
B3
B2
CS_SAMP_
TIME[1:0]
B1
B0
CS_RNG
[1:0]
DEFAULT
03h
The Current Sense Sampling Configuration register stores the controls for determining the Current
Sense sampling / update time.
Bits 7 - 6 - CS_QUEUE[1:0] - Determine the number of consecutive measurements that the measured
VSENSE must exceed the limits before flagging an interrupt.
Table 5.28 Sense Queue Settings
CS_QUEUE[1:0]
1
0
NUMBER OF CONSECUTIVE OUT-OF-LIMIT MEASUREMENTS
0
0
1 (default)
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High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Table 5.28 Sense Queue Settings (continued)
CS_QUEUE[1:0]
1
0
NUMBER OF CONSECUTIVE OUT-OF-LIMIT MEASUREMENTS
0
1
2
1
0
3
1
1
4
Bits 5 - 4 - CS_SAMP_AVG[1:0] - Determines the number of averages that the Current Sensing
Circuitry will take as shown in Table 5.29.
Table 5.29 Current Sense Averaging Settings
CS_SAMP_AVG[1:0]
1
0
AVERAGING
0
0
1x (default)
0
1
2x
1
0
4x
1
1
8x
Bits 3 - 2 - CS_SAMP_TIME[1:0] - Determines the sampling time of the Current Sensing Circuitry as
shown in Table 5.30. The VSENSE voltage will be updated at this rate representing the average current
over the Sampling Time multiplied by the Averaging factor as shown in Table 5.31.
Table 5.30 Current Sensing Sampling Time Settings
CS_SAMP_TIME[1:0]
1
0
CURRENT SENSOR SAMPLING TIME
0
0
82ms (default)
0
1
82ms
1
0
164ms
1
1
328ms
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Revision 1.2 (09-27-10)
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Table 5.31 Total Sampling Times
AVERAGING SELECTION
SAMPLING TIME
1X
2X
4X
8X
82ms
82ms
164ms
328ms
655ms
164ms
164ms
328ms
655ms
1310ms
328ms
328ms
655ms
1310ms
2620ms
Bits 1 - 0 - CS_RNG[1:0] - Determines the Current Sense maximum expected voltage (full scale range)
as shown in Table 5.32.
Table 5.32 Current Sensing Range (Full Scale Range) Settings
CS_RNG[1:0]
5.21
1
0
CURRENT SENSOR RANGE
0
0
10mV
0
1
20mV
1
0
40mV
1
1
80mV (default)
Peak Detection Configuration Register
Table 5.33 Peak Detection Configuration Register
ADDR
R/W
REGISTER
52h
R/W
Peak
Detection
Config
B7
B6
B5
B4
PEAK_DET_TH[3:0]
B3
B2
B1
B0
PEAK_DET_DUR[3:0]
DEFAULT
00h
The Peak Detection Configuration register controls the threshold and durations used by the Peak
Detection circuitry. At all times, the Peak Detection threshold and duration are set by the values written
into this register. The resistors on the TH_SEL and DUR_SEL pins are used to determine the initial
values of this register and will not be retained if the value is over written by the user.
These values may be updated at any time via the SMBus.
Bits 7-4 - PEAK_DET_TH[3:0] - Determines the Peak Detector Threshold level as shown in Table 5.34.
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High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Table 5.34 PEAK_DET_TH[3:0] Bit Decode
PEAK_DET_TH[3:0]
3
2
1
0
PEAK DETECTION THRESHOLD
0
0
0
0
10mV
0
0
0
1
15mV
0
0
1
0
20mV
0
0
1
1
25mV
0
1
0
0
30mV
0
1
0
1
35mV
0
1
1
0
40mV
0
1
1
1
45mV
1
0
0
0
50mV
1
0
0
1
55mV
1
0
1
0
60mV
1
0
1
1
65mV
1
1
0
0
70mV
1
1
0
1
75mV
1
1
1
0
80mV
1
1
1
1
85mV
Bits 4-0 - PEAK_DET_DUR[3:0] - Determines the Peak Detector minimum time threshold as shown in
Table 5.35.
Table 5.35 PEAK_DET_DUR[3:0] Bit Decode
PEAK_DET_DUR[3:0]
3
2
1
0
PEAK DETECTION MINIMUM
DURATION
0
0
0
0
1ms
0
0
0
1
5.12ms
0
0
1
0
25.6 ms
0
0
1
1
51.2 ms
0
1
0
0
76.8 ms
0
1
0
1
102.4ms
0
1
1
0
128.0ms
0
1
1
1
256.0ms
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Revision 1.2 (09-27-10)
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Table 5.35 PEAK_DET_DUR[3:0] Bit Decode (continued)
PEAK_DET_DUR[3:0]
3
2
1
0
PEAK DETECTION MINIMUM
DURATION
1
0
0
0
384.0ms
1
0
0
1
512.0ms
1
0
1
0
768.0ms
1
0
1
1
1024.0ms
1
1
0
0
1536.0ms
1
1
0
1
2048.0ms
1
1
1
0
3072.0ms
1
1
1
1
4096.0ms
5.22
Sense Voltage Registers
Table 5.36 Sense Voltage Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
54h
R
Sense Voltage
High Byte
Sign
1024
512
256
128
64
32
16
00h
55h
R
Sense Voltage
Low Byte
8
4
2
1
00h
The Sense Voltage registers store the measured VSENSE voltage across the sense resistor (RSENSE)
placed between the SENSE+ and SENSE- pins (see Section 4.1.1, "Current Measurement"). Note that
the bit weighting values are for representation of the voltage relative to full scale. There is no internal
scaling of data and all normal binary bit weightings still apply.
The Sense Voltage register data format is standard 2’s complement format with the positive full scale
value (7F_Fh) and negative full scale value (80_0h) equal to the programmed maximum sense voltage
(see Section 5.20, "Current Sense Sampling Configuration Register").
The Sign bit indicates the direction of current flow. If the Sign bit is ‘0’, current is flowing through
RSENSE from the SENSE+ pin to the SENSE- pin. If the Sign bit is ‘1’, the current is flowing through
RSENSE from the SENSE- pin to the SENSE+ pin. See Section 4.1.1, "Current Measurement" for
examples.
Table 5.37 VSENSE Data Format
VSENSE
BINARY
HEX (AS READ BY REGISTERS)
Minus Full Scale
1000_0000_0000
80_0h
-2 LSB
1111_1111_1110
FF_Eh
-1 LSB
1111_1111_1111
FF_Fh
Zero
0000_0000_0000
00_0h
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High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Table 5.37 VSENSE Data Format (continued)
5.23
VSENSE
BINARY
HEX (AS READ BY REGISTERS)
+1 LSB
0000_0000_0001
00_1h
+2 LSB
0000_0000_0010
00_2h
Plus Full Scale
0111_1111_1111
7F_Fh
Source Voltage Registers
Table 5.38 Source Voltage Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
58h
R
VSOURCE
High Byte
12
6
3
1.5
0.75
0.375
0.1875
0.0938
00h
59h
R
VSOURCE
low Byte
0.0469
0.0234
0.0117
-
-
-
-
-
00h
The Source Voltage registers store the voltage measured at the SENSE+ pin (see Section 4.1.2,
"Voltage Measurement") as a digital value, VSOURCE, consisting of a high byte and low byte with five
of its LSBs always zero.
The measured voltage is determined by summing the bit weights of each bit set. For example, if VBUS
was 7.4V, the Source Voltage registers would read 0100_1110 for the high byte and 1100_0000b for
the low byte corresponding to 6V + 0.75V + 0.375V + 0.1875V + 0.0469V + 0.0234V = 7.383V.
The bit weightings are assigned for human interpretation. They should be disregarded when translating
the information via a computing system as shown in Section 4.1.2, "Voltage Measurement".
The Source Voltage registers cannot support negative values, and all values less than 0V will be
recorded as 0V.
5.24
Power Ratio Registers
Table 5.39 Power Ratio Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
5Bh
R
Power Ratio
High Byte
32768
16384
8192
4096
2048
1024
512
256
00h
5Ch
R
Power Ratio
Low Byte
128
64
32
16
8
4
2
1
00h
The Power Ratio registers store a power factor value that is used to determine the final average power
delivered to the system (see Section 4.1.3, "Power Calculation"). The power factor value is the result
of the multiplication of the VSENSE reading and the VSOURCE reading values shifted to a 16-bit number.
It represents the ratio of delivered power with respect to maximum power.
SMSC EMC1702
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DATASHEET
Revision 1.2 (09-27-10)
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
5.25
VSENSE Limit Registers
Table 5.40 VSENSE Limit Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
60h
R/W
Sense Voltage
High Limit
Sign
1024
512
256
128
64
32
16
7Fh
61h
R/W
Sense Voltage
Low Limit
Sign
1024
512
256
128
64
32
16
80h
The VSENSE Limit registers store a high and low limit for VSENSE. VSENSE is compared against both
limits after each update.
The data format for the limit is a raw binary form that is relative to the maximum VSENSE that has been
programmed.
If the measured sense voltage meets or exceeds the high limit or drops below the low limit, the ALERT
pin is asserted and the VSENSE_HIGH or VSENSE_LOW status bits are set in the High Limit Status
or Low Limit Status registers (see Section 5.15 and Section 5.16).
APPLICATION NOTE: VSENSE is always checked to be greater than the high limit or less than the low limit including
when VSENSE is negative.
5.26
Source Voltage Limit Registers
Table 5.41 Source Voltage Limit Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
64h
R/W
Source
Voltage
High Limit
12
6
3
1.5
0.75
0.375
0.1875
0.0938
FFh
65h
R/W
Source
Voltage Low
Limit
12
6
3
1.5
0.75
0.375
0.1875
0.0938
00h
The Source Voltage Limit registers store the high and low limits for VSOURCE. VSOURCE is compared
against all limits after each update.
If VSOURCE meets or exceeds the corresponding high limit or drops below the low limit, the ALERT pin
is asserted and the VSRC_HIGH or VSRC_LOW status bits are set in the High Limit Status or Low
Limit Status registers (see Section 5.15 and Section 5.16).
5.27
Critical Voltage Limit Registers
Table 5.42 Critical Voltage Limit Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
66h
R/W
Sense Voltage
Vcrit Limit
Sign
1024
512
256
128
64
32
16
7Fh
Revision 1.2 (09-27-10)
50
DATASHEET
SMSC EMC1702
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Table 5.42 Critical Voltage Limit Registers (continued)
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
68h
R/W
Source Voltage
Vcrit Limit
12
6
3
1.5
0.75
0.375
0.1875
0.0938
FFh
69h
R/W
Sense Voltage
Vcrit Hysteresis
-
-
-
256
128
64
32
16
0Ah
6Ah
R/W
Source Voltage
Vcrit Hysteresis
-
-
-
1.5
0.75
0.375
0.1875
0.0938
0Ah
The Critical Voltage Limit registers store the critical voltage limits (Vcrit limits) for VSENSE and VSOURCE.
If the respective value meets or exceeds its critical limit, the THERM pin will be asserted low and the
respective VCRIT status bit will be set (see Section 5.17, "Crit Limit Status Register"). It will remain
asserted until the respective value drops below its limit minus the respective Vcrit Hysteresis value.
5.28
Product Features Register
Table 5.43 Product Features
ADDR
R/W
REGISTER
FCh
R
Product
Features
B7
B6
B5
B4
B3
TH_SEL[3:0]
B2
B1
B0
DUR_SEL[3:0]
DEFAULT
00h
The Product Features register indicates functionality that is selected by the user based on pin states
upon device power up.
Bits 7-4 - TH_SEL[3:0] - Indicates the selected Peak Detector Threshold setting as determined by the
TH_SEL pin. This value will be the default setting for the PEAK_DET_TH[3:0] bits and uses the same
decode as given in Table 5.34.
Bits 3-0 - DUR_SEL[3:0] - Indicates the selected Peak Detector minimum duration setting as
determined by the DUR_SEL pin. This value will be the default setting for the PEAK_DET_DUR[3:0]
bits and uses the same decode as given in Table 5.35.
5.29
Product ID Register
Table 5.44 Product ID Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
FDh
R
Product ID
0
0
1
1
1
0
0
1
39h
The Product ID Register holds a unique value that identifies the device.
SMSC EMC1702
51
DATASHEET
Revision 1.2 (09-27-10)
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
5.30
SMSC ID Register
Table 5.45 Manufacturer ID Register
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
FEh
R
SMSC ID
0
1
0
1
1
1
0
1
5Dh
The Manufacturer ID register contains an 8-bit word that identifies SMSC as the manufacturer of the
EMC1702.
5.31
Revision Register
Table 5.46 Revision Register
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
FFh
R
Revision
1
0
0
0
0
0
1
0
82h
The Revision register contains an 8-bit word that identifies the die revision.
Revision 1.2 (09-27-10)
52
DATASHEET
SMSC EMC1702
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Chapter 6 Package Description
6.1
EMC1702 Package Drawing (12-Pin QFN 4mm x 4mm)
Figure 6.1 12-Pin QFN 4mm x 4mm Package Drawings
SMSC EMC1702
53
DATASHEET
Revision 1.2 (09-27-10)
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Figure 6.2 12-Pin QFN 4mm x 4mm Package Dimensions and Notes
Figure 6.3 12-Pin QFN 4mm x 4mm PCB Footprint
Revision 1.2 (09-27-10)
54
DATASHEET
SMSC EMC1702
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
6.2
EMC1702 Package Markings
TOP
0.41
LINE: 1 – SMSC Logo without circled (R) symbol
LINE: 2 – Device Number - Version
LINE: 3 – Last 7 digits of Lot Number
LINE: 4 – Revision and Country Code (RCC)
E 1 7 0 2 - 1
1 2 3 4 5 6 a
RCC
e3
3x 0.56
PB-FREE/GREEN SYMBOL
(Matte Sn)
PIN 1
LINES 1 to 3: CENTER HORIZONTAL ALIGNMENT
LINE 4: LEFT HORIZONTAL ALIGNMENT
BOTTOM
BOTTOM MARKING NOT ALLOWED
Figure 6.4 EMC1702 Package Markings
SMSC EMC1702
55
DATASHEET
Revision 1.2 (09-27-10)
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Chapter 7 Datasheet Revision History
Table 7.1 Customer Revision History
REVISION LEVEL & DATE
Rev. 1.2 (09-27-10)
Rev. 1.1 (06-16-10)
SECTION/FIGURE/ENTRY
CORRECTION
Table 2.1, "Absolute
Maximum Ratings"
Added spec for voltage between SENSE pins.
Table 2.2, "Electrical
Specifications"
Updated all electrical specs for current sense
measurement, supply current, and peak detector.
Electrical Specifications
APPLICATION NOTE:
Added note: The EMC1702 is trimmed at the
80mV range for best accuracy.
Section 5.13, "Beta
Configuration Registers"
“BETAx[2:0] bits” changed to “BETAx[3:0] bits”.
System Diagram
Updated.
Section 5.15, "High Limit
Status Register" and Section
5.16, "Low Limit Status
Register"
ALERT# pin won’t be set if masked.
Table 5.32, "Current
Sensing Range (Full Scale
Range) Settings"
Changed title from Current Sensing Range to
Current Sensing Range (Full Scale Range)
Settings.
Table 2.2, "Electrical
Specifications"
TA upper limit changed from 125°C to 85°C.
Bus voltage symbol changed from VSOURCE to
VBUS.
IDD at 4 conversions/second with dynamic
averaging enabled changed from 0.95 typ and
1.375 max to 0.9 typ and 1.3 max.
IDD at 4 conversions/second with dynamic
averaging disabled changed from 0.80 typ to 0.8
typ.
IDD at 1 conversion/second with dynamic
averaging disabled changed from 650 typ and 1
max to 0.7 typ and 1.0 max.
VSENSE Full Scale Sense Range values changed
from 0 min and +/- max values to - min values and
+ max values; conditions changed.
Total Unadjusted VSENSE Measurement Error
(VSENSE_TUE) renamed VSENSE Measurement
Error (VSENSE_ERR); typ value at 20-80mV FSR
changed from 0.8 to +/-0.5 and max changed from
+/-1.5 to +/-1; typ value at 10mV FSR changed
from 0.2 to +/-0.8 and max changed from +/-2 to
+/-1.5.
VSENSE_OFF condition added.
VSENSE Measurement Gain Error has new symbol
VSENSE_GN; added typ +/-0.2 and changed max
from 0.5 to +/-0.5.
VTH_ERR changed from +/-20 to +/-2.
VSOURCE_ERR changed conditions; typ changed
from 0.05 to +/-0.2 and max changed from 1 to +/0.5.
Added Power Ratio Measurement specs.
Data hold time changed from 0.6 min and 6 max
to 0 min and no max.
Figure 4.1, "EMC1702
System Diagram"
Revision 1.2 (09-27-10)
Diagram modified
56
DATASHEET
SMSC EMC1702
High-Side Current-Sense and Dual 1°C Temperature Monitor
Datasheet
Table 7.1 Customer Revision History (continued)
REVISION LEVEL & DATE
SECTION/FIGURE/ENTRY
Section 5.31, "Revision
Register"
Rev. 1.0 (11-09-09)
SMSC EMC1702
CORRECTION
Functional revision C changed default from 81h to
82h.
Formal release
57
DATASHEET
Revision 1.2 (09-27-10)
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