CET CEU30N08 Ced30n08 Datasheet

CED30N08/CEU30N08
N-Channel Enhancement Mode Field Effect Transistor
PRELIMINARY
FEATURES
80V, 30A, RDS(ON) = 30mΩ @VGS = 10V.
RDS(ON) = 38mΩ @VGS = 4.5V.
Super high dense cell design for extremely low RDS(ON).
D
High power and current handing capability.
Lead-free plating ; RoHS compliant.
TO-251 & TO-252 package.
G
D
G
S
CEU SERIES
TO-252(D-PAK)
ABSOLUTE MAXIMUM RATINGS
Parameter
G
D
S
CED SERIES
TO-251(I-PAK)
S
Tc = 25 C unless otherwise noted
Symbol
Limit
Drain-Source Voltage
VDS
Gate-Source Voltage
VGS
Drain Current-Continuous @ TC = 25 C
ID
@ TC = 100 C
Drain Current-Pulsed a
IDM
Maximum Power Dissipation @ TC = 25 C
PD
- Derate above 25 C
EAS
Single Pulsed Avalanche Energy e
80
Units
V
±20
V
30
A
19.5
A
120
A
57.7
W
0.38
W/ C
100
mJ
IAS
20
A
TJ,Tstg
-55 to 150
C
Symbol
Limit
Units
Thermal Resistance, Junction-to-Case
RθJC
2.2
C/W
Thermal Resistance, Junction-to-Ambient
RθJA
50
C/W
Single Pulsed Avalanche Current
e
Operating and Store Temperature Range
Thermal Characteristics
Parameter
This is preliminary information on a new product in development now
Details are subject to change without notice .
1
Rev 1. 2014.Nov
http://www.cetsemi.com
CED30N08/CEU30N08
Electrical Characteristics
Parameter
TA = 25 C unless otherwise noted
Symbol
Test Condition
Min
Drain-Source Breakdown Voltage
BVDSS
VGS = 0V, ID = 250µA
80
Zero Gate Voltage Drain Current
IDSS
Gate Body Leakage Current, Forward
Gate Body Leakage Current, Reverse
Typ
Max
Units
VDS = 80V, VGS = 0V
1
µA
IGSSF
VGS = 20V, VDS = 0V
100
nA
IGSSR
VGS = -20V, VDS = 0V
-100
nA
Off Characteristics
V
On Characteristics c
Gate Threshold Voltage
Static Drain-Source
On-Resistance
VGS(th)
RDS(on)
VGS = VDS, ID = 250µA
3
V
VGS = 10V, ID = 30A
1
22
30
mΩ
VGS = 4.5V, ID =15A
27
38
mΩ
Dynamic Characteristics d
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
VDS = 25V, VGS = 0V,
f = 1.0 MHz
1600
pF
185
pF
100
pF
16
ns
7
ns
45
ns
Switching Characteristics d
Turn-On Delay Time
td(on)
Turn-On Rise Time
tr
Turn-Off Delay Time
td(off)
VDD = 50V, ID = 15A,
VGS = 10V, RGEN = 6Ω
Turn-Off Fall Time
tf
8
ns
Total Gate Charge
Qg
37
nC
Gate-Source Charge
Qgs
6
nC
Gate-Drain Charge
Qgd
9
nC
VDS = 50V, ID = 15A,
VGS = 10V
Drain-Source Diode Characteristics and Maximun Ratings
Drain-Source Diode Forward Current b
IS
Drain-Source Diode Forward Voltage c
VSD
VGS = 0V, IS = 20A
Notes :
a.Repetitive Rating : Pulse width limited by maximum junction temperature.
b.Surface Mounted on FR4 Board, t < 10 sec.
c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.
d.Guaranteed by design, not subject to production testing.
e.L = 0.5mH, IAS =20A, VDD = 25V, RG = 25Ω, Starting TJ = 25 C
2
30
A
1.2
V
CED30N08/CEU30N08
50
30
24
ID, Drain Current (A)
ID, Drain Current (A)
VGS=10,8,6V
18
12
VGS=3V
6
0
0
0.5
1.0
1.5
TJ=125 C
0
-55 C
2
4
6
8
Figure 1. Output Characteristics
Figure 2. Transfer Characteristics
RDS(ON), Normalized
RDS(ON), On-Resistance(Ohms)
1200
800
400
Coss
Crss
0
5
10
15
20
25
2.6
2.2
ID=30A
VGS=10V
1.8
1.4
1.0
0.6
0.2
-100
-50
0
50
100
150
200
VDS, Drain-to-Source Voltage (V)
TJ, Junction Temperature( C)
Figure 3. Capacitance
Figure 4. On-Resistance Variation
with Temperature
VDS=VGS
ID=250µA
IS, Source-drain current (A)
C, Capacitance (pF)
VTH, Normalized
Gate-Source Threshold Voltage
10
VGS, Gate-to-Source Voltage (V)
Ciss
1.1
1.0
0.9
0.8
0.7
0.6
-50
25 C
VDS, Drain-to-Source Voltage (V)
1600
1.2
20
0
2000
1.3
30
2.0
2400
0
40
-25
0
25
50
75
100
125
150
VGS=0V
10
2
10
1
10
0
0.4
0.6
0.8
1.0
1.2
1.4
TJ, Junction Temperature( C)
VSD, Body Diode Forward Voltage (V)
Figure 5. Gate Threshold Variation
with Temperature
Figure 6. Body Diode Forward Voltage
Variation with Source Current
3
10
VDS=50V
ID=15A
8
ID, Drain Current (A)
VGS, Gate to Source Voltage (V)
CED30N08/CEU30N08
6
4
2
0
0
8
16
24
32
40
10
3
10
2
10
1
10
0
10
-1
RDS(ON)Limit
1ms
10ms
100ms
DC
TA=25 C
TJ=150 C
Single Pulse
10
-1
10
0
10
1
10
Qg, Total Gate Charge (nC)
VDS, Drain-Source Voltage (V)
Figure 7. Gate Charge
Figure 8. Maximum Safe
Operating Area
VDD
t on
V IN
RL
D
VGS
RGEN
toff
tr
td(on)
td(off)
tf
90%
90%
VOUT
VOUT
10%
INVERTED
10%
G
90%
S
VIN
50%
50%
10%
PULSE WIDTH
Figure 10. Switching Waveforms
r(t),Normalized Effective
Transient Thermal Impedance
Figure 9. Switching Test Circuit
10
0
D=0.5
0.2
10
0.1
-1
PDM
0.05
t1
0.02
0.01
1. RθJC (t)=r (t) * RθJC
2. RθJC=See Datasheet
3. TJM-TC = P* RθJC (t)
4. Duty Cycle, D=t1/t2
Single Pulse
10
-2
10
-4
t2
10
-3
10
-2
10
-1
10
0
Square Wave Pulse Duration (sec)
Figure 11. Normalized Thermal Transient Impedance Curve
4
10
1
10
2
2
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