STMicroelectronics M27V102-120B6TR 1 mbit 64kb x 16 low voltage uv eprom and otp eprom Datasheet

M27V102
1 Mbit (64Kb x 16) Low Voltage UV EPROM and OTP EPROM
LOW VOLTAGE READ OPERATION:
3V to 3.6V
FAST ACCESS TIME: 90ns
LOW POWER CONSUMPTION:
– Active Current 15mA at 5MHz
– Standby Current 20µA
PROGRAMMING VOLTAGE: 12.75V ± 0.25V
PROGRAMMING TIME: 100µs/byte (typical)
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code: 008Ch
DESCRIPTION
The M27W102 is a low voltage 1 Mbit EPROM
offeredin the two ranges UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systems requiring large data or
program storage and is organized as 65,536 words
by 16 bits.
The M27V102 operates in the read mode with a
supply voltage as low as 3V. The decrease in
operating power allows either a reduction of the
size of the battery or an increase in the time between battery recharges.
The FDIP40W (window ceramic frit-seal package)
has a transparent lid which allows the user to
expose the chip to ultraviolet light to erase the bit
pattern. A new pattern can then be written to the
device by following the programming procedure.
Table 1. Signal Names
A0 - A15
Address Inputs
Q0 - Q15
Data Outputs
E
Chip Enable
G
Output Enable
P
Program
VPP
Program Supply
VCC
Supply Voltage
VSS
Ground
40
40
1
1
FDIP40W (F)
PDIP40 (B)
PLCC44 (K)
TSOP40 (N)
10 x 14mm
Figure 1. Logic Diagram
VCC
VPP
16
16
A0-A15
P
Q0-Q15
M27V102
E
May 1998
G
VSS
AI01912
1/15
M27V102
Figure 2A. DIP Pin Connections
VCC
P
NC
A15
A14
A13
A12
A11
A10
A9
VSS
A8
A7
A6
A5
A4
A3
A2
A1
A0
Q13
Q14
Q15
E
VPP
NC
VCC
P
NC
A15
A14
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
9
32
10
31
M27V102
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
1 44
Q12
Q11
Q10
Q9
Q8
VSS
NC
Q7
Q6
Q5
Q4
12
M27V102
34
A13
A12
A11
A10
A9
VSS
NC
A8
A7
A6
A5
23
Q3
Q2
Q1
Q0
G
NC
A0
A1
A2
A3
A4
VPP
E
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
VSS
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
G
Figure 2B. LCC Pin Connections
AI01914
AI01913
Warning: NC = Not Connected.
Warning: NC = Not Connected.
Figure 2C. TSOP Pin Connections
DESCRIPTION (cont’d)
A9
A10
A11
A12
A13
A14
A15
NC
P
VCC
VPP
E
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
1
10
11
40
M27V102
(Normal)
20
31
30
21
AI01915
Warning: NC = Not Connected.
2/15
VSS
A8
A7
A6
A5
A4
A3
A2
A1
A0
G
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VSS
For application where the content is programmed
only one time and erasure is not required, the
M27V102 is offered in PDIP40, PLCC32 and
TSOP40 (10 x 14 mm) packages.
DEVICE OPERATION
The operating modes of the M27V102 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for Vpp and 12V on A9 for Electronic
Signature.
Read Mode
The M27V102 has two control functions, both of
which must be logically active in order to obtaindata
at the outputs. Chip Enable (E) is the power control
and should be used for device selection. Output
Enable (G) is the output control and should be used
to gate data to the output pins, independent of
device selection. Assuming that the addresses are
stable, the address access time (t AVQV) is equal to
the delay from E to output (t ELQV). Data is available
at the output after a delay of tOE from the falling
edge of G, assuming that E has been low and the
addresses have been stable for at least tAVQVtGLQV.
M27V102
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Ambient Operating Temperature
TA
Value
(3)
Unit
–40 to 125
°C
TBIAS
Temperature Under Bias
–50 to 125
°C
TSTG
Storage Temperature
–65 to 150
°C
Input or Output Voltages (except A9)
–2 to 7
V
Supply Voltage
–2 to 7
V
A9 Voltage
–2 to 13.5
V
Program Supply Voltage
–2 to 14
V
VIO
(2)
VCC
VA9
(2)
VPP
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes
Mode
E
G
P
A9
VPP
Q0 - Q15
Read
VIL
VIL
VIH
X
VCC or VSS
Data Output
Output Disable
VIL
VIH
X
X
VCC or VSS
Hi-Z
Program
VIL
X
VIL Pulse
X
VPP
Data Input
Verify
VIL
VIL
VIH
X
VPP
Data Output
Program Inhibit
VIH
X
X
X
VPP
Hi-Z
Standby
VIH
X
X
X
VCC or VSS
Hi-Z
Electronic Signature
VIL
VIL
VIH
VID
VCC
Codes
Note: X = VIH or VIL, VID = 12V ±0.5V
Table 4. Electronic Signature
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Hex Data
Manufacturer’s Code
VIL
0
0
1
0
0
0
0
0
20h
Device Code
VIH
1
0
0
0
1
1
0
0
8Ch
Standby Mode
The M27V102 has a standby mode which reduces
the active current from 15mA to 20µA with low
voltage operation VCC ≤ 3.6V, see Read Mode DC
Characteristics table for details. The M27V102 is
placed in the standby mode by applying a TTL high
signal to the E input. When in the standby mode,
the outputs are in a high impedance state, independent of the G input.
Two Line Output Control
BecauseEPROMs are usually used in larger memory arrays, this product features a 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
3/15
M27V102
Table 5. AC Measurement Conditions
High Speed
Standard
Input Rise and Fall Times
≤ 10ns
≤ 20ns
Input Pulse Voltages
0 to 3V
0.4V to 2.4V
1.5V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
Standard
2.4V
OUT
CL
2.0V
0.8V
0.4V
CL = 30pF for High Speed
CL = 100pF for Standard
AI01822
CL includes JIG capacitance
AI01823B
Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
CIN
C OUT
Parameter
Test Condition
Input Capacitance
Output Capacitance
Min
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% tested.
For the most efficient use of thesetwo control lines,
E should be decoded and used as the primary
device selecting function, while G should be made
a common connection to all devices in the array
and connected to the READ line from the system
control bus. This ensures that all deselectedmemory devices are in their low power standby mode
and that the output pins are only active when data
is required from a particular memory device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three segments that are of interest to the system designer :
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
4/15
transientcurrent peaks is dependenton the capacitive and inductive loading of the device at the
output.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between VCC
and VSS. This should be a high frequency capacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7µF bulk electrolytic capacitor should be used
between Vcc and VSS for every eight devices. The
bulk capacitor should be located near the power
supply connection point. The purpose of the bulk
capacitor is to overcome the voltage drop caused
by the inductive effects of PCB traces.
M27V102
Table 7. Read Mode DC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 3.3V ± 10%; VPP = VCC)
Symbol
Parameter
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ VCC
±10
µA
0V ≤ VOUT ≤ VCC
±10
µA
E = VIL, G = VIL, IOUT = 0mA,
f = 5MHz, VCC ≤ 3.6V
15
mA
E = VIH
1
mA
E > VCC – 0.2V, V CC ≤ 3.6V
20
µA
VPP = VCC
10
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
Supply Current
ICC1
Supply Current (Standby) TTL
ICC2
Supply Current (Standby)
CMOS
IPP
Program Current
VIL
Input Low Voltage
–0.3
0.8
V
Input High Voltage
2
VCC + 1
V
0.4
V
VIH
(2)
Output Low Voltage
VOL
VOH
IOL = 2.1mA
Output High Voltage TTL
IOH = –400µA
2.4
V
Output High Voltage CMOS
IOH = –100µA
VCC – 0.7V
V
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Maximum DC voltage on Output is VCC +0.5V
Table 8A. Read Mode AC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 3.3V ± 10%; VPP = VCC)
M27V102
Symbol
Alt
Parameter
Test Condition
-90
Min
tAVQV
tACC
Address Valid to Output Valid
tELQV
tCE
tGLQV
(3)
Max
Unit
-100
Min
Max
E = VIL, G = VIL
90
100
ns
Chip Enable Low to Output Valid
G = VIL
90
100
ns
45
50
ns
tOE
Output Enable Low to Output Valid
E = VIL
tEHQZ
(2)
tDF
Chip Enable High to Output Hi-Z
G = VIL
0
30
0
30
ns
tGHQZ
(2)
tDF
Output Enable High to Output Hi-Z
E = VIL
0
30
0
30
ns
tOH
Address Transition to Output Transition
E = VIL, G = VIL
0
tAXQX
0
ns
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously with or after V PP.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
5/15
M27V102
Table 8B. Read Mode AC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 3.3V ± 10%; VPP = VCC)
M27V102
Symbol
Alt
Parameter
Test Condition
-120
-150
-200
Unit
Min Max Min Max Min Max
tAVQV
tACC
Address Valid to Output Valid
tELQV
tCE
tGLQV
E = VIL, G = VIL
120
150
200
ns
Chip Enable Low to Output Valid
G = VIL
120
150
200
ns
50
60
90
ns
tOE
Output Enable Low to Output Valid
E = VIL
tEHQZ
(2)
tDF
Chip Enable High to Output Hi-Z
G = VIL
0
40
0
50
0
70
ns
tGHQZ
(2)
tDF
Output Enable High to Output Hi-Z
E = VIL
0
40
0
50
0
70
ns
tOH
Address Transition to Output
Transition
E = VIL, G = VIL
0
tAXQX
0
0
ns
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously with or after V PP.
2. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
A0-A15
VALID
tAVQV
VALID
tAXQX
E
tGLQV
tEHQZ
G
tELQV
Q0-Q15
tGHQZ
Hi-Z
AI00705B
Programming
The M27V102 has been designed to be fully compatible with the M27C1024 and has the same
elecronic signature. As a result the M27V102 can
be programmed as the M27C1024 on the same
programming equipments applying 12.75V on VPP
and 6.25V on VCC by the use of the same PRESTO
II algorithm. When delivered (and after each ’1’s
erasure for UV EPROM), all bits of the M27V102
are in the ’1’ state. Data is introduced by selectively
6/15
programming ’0’s into the desired bit locations.
Although only ’0’s will be programmed, both ’1’s
and ’0’s can be present in the data word. The only
way to change a ’0’ to a ’1’ is by die exposure to
ultraviolet light (UV EPROM). The M27V102 is in
the programming mode when VPP input is at
12.75V, E is at VIL and P is pulsed to VIL. The data
to be programmed is applied to 16 bits in parallel
to the data output pins. The levels required for the
address and data inputs are TTL. V CC is specified
to be 6.25V ± 0.25V.
M27V102
Table 9. Programming Mode DC Characteristics (1)
(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol
Parameter
Test Condition
Min
0 ≤ VIN ≤ VIH
Max
Unit
±10
µA
50
mA
50
mA
ILI
Input Leakage Current
ICC
Supply Current
IPP
Program Current
VIL
Input Low Voltage
–0.3
0.8
V
V IH
Input High Voltage
2
VCC + 0.5
V
VOL
Output Low Voltage
0.4
V
V OH
Output High Voltage TTL
V ID
A9 Voltage
E = VIL
IOL = 2.1mA
IOH = –400µA
2.4
V
11.5
12.5
V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously with or after V PP.
Table 10. Programming Mode AC Characteristics (1)
(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol
Alt
tAVPL
tAS
Address Valid to Program Low
2
µs
tQVPL
tDS
Input Valid to Program Low
2
µs
tVPHPL
tVPS
VPP High to Program Low
2
µs
tVCHPL
tVCS
VCC High to Program Low
2
µs
tELPL
tCES
Chip Enable Low to Program Low
2
µs
tPLPH
tPW
Program Pulse Width
95
tPHQX
tDH
Program High to Input Transition
2
µs
tQXGL
tOES
Input Transition to Output Enable
Low
2
µs
tGLQV
tOE
Output Enable Low to Output Valid
tDFP
Output Enable High to Output Hi-Z
0
tAH
Output Enable High to Address
Transition
0
tGHQZ
(2)
tGHAX
Parameter
Test Condition
Min
Max
105
Unit
µs
100
ns
130
ns
ns
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously with or after V PP.
2. Sampled only, not 100% tested.
7/15
M27V102
Figure 6. Programming and Verify Modes AC Waveforms
VALID
A0-A15
tAVPL
Q0-Q15
DATA IN
tQVPL
DATA OUT
tPHQX
VPP
tVPHPL
tGLQV
tGHQZ
VCC
tVCHPL
tGHAX
E
tELPL
P
tPLPH
tQXGL
G
PROGRAM
VERIFY
AI00706
Figure 7. Programming Flowchart
VCC = 6.25V, VPP = 12.75V
n =0
P = 100µs Pulse
NO
++n
= 25
YES
FAIL
NO
VERIFY
++ Addr
YES
Last
Addr
NO
YES
CHECK ALL WORDS
1st: VCC = 6V
2nd: VCC = 4.2V
AI00707C
8/15
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows programming of the whole array with a guaranteed
margin, in a typical time of 6.5 seconds. Programming with PRESTO II consists of applying a sequenceof 100 µs program pulses toeach word until
a correct verify occurs (see Figure 7). During programming and verify operation, a MARGIN MODE
circuit is automaticallyactivated in order to guarantee that each cell is programmed with enough
margin. No overprogrampulse is applied since the
verify in MARGIN MODE at VCC much higher than
3.6V provides necessary margin to each programmed cell.
Program Inhibit
Programming of multiple M27V102s in parallel with
different data is also easily accomplished. Except
for E, all like inputs including G of the parallel
M27V102 may be common. A TTL low level pulse
applied to a M27V102’sP input, with E low and VPP
at 12.75V, will program that M27V102. A high level
E input inhibits the other M27V102s from being
programmed.
Program Verify
A verify (read) should be performed on the programmed bits to determine that they were correctly
programmed. The verify is accomplished with E
M27V102
and G at VIL, P at VIH, VPP at 12.75V and VCC at
6.25V.
On-Board Programming
The M27V102 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its correspondingprogramming algorithm. The
ES mode is functional in the 25°C ± 5°C ambient
temperature range that is required when programming the M27V102. To activate the ES mode, the
programming equipmentmust force 11.5Vto 12.5V
on address line A9 of the M27V102 with VPP = VCC
= 5V. Two identifier bytes may then be sequenced
from the device outputs by togglingaddress line A0
from VIL to VIH. All other address lines must be held
at VIL during Electronic Signature mode. Byte 0
(A0=VIL) represents the manufacturer code and
byte 1 (A0=VIH) the device identifier code. For the
STMicroelectronics M27V102, these two iden-tifier
bytes are given in Table 4 and can be read-out on
outputs Q0 to Q7. Note that the M27V102 and
M27C1024 have the same identifier bytes.
ERASURE OPERATION (applies to UV EPROM)
Theerasure characteristics of the M27V102is such
that erasure begins when the cells are exposed to
light with wavelengths shorter than approximately
4000 Å. It should be noted that sunlight and some
type of fluorescent lamps have wavelengths in the
3000-4000Å range. Research shows that constant
exposure to room level fluorescent lighting could
erase a typical M27V102 in about 3 years, while it
would take approximately 1 week to cause erasure
when exposed to direct sunlight. If the M27V102
is to be exposed to these types of lighting conditions for extended periods of time, it is suggested
that opaque labels be put over the M27V102 window to prevent unintentionalerasure. The recommended erasure procedure for the M27V102 is
exposure to short wave ultraviolet light which has
wavelength 2537 Å. The integrated dose (i.e. UV
intensity x exposure time) for erasure should be a
minimum of 15 W-sec/cm2. The erasure time with
this dosage is approximately 15 to 20 minutes
using an ultravioletlamp with 12000 µW/cm2 power
rating. The M27V102 should be placed within 2.5
cm (1 inch) of the lamp tubes during the erasure.
Some lamps have a filter on their tubes which
should be removed before erasure.
9/15
M27V102
ORDERING INFORMATION SCHEME
Example:
M27V102
-90
Package
Speed
K
1
TR
Option
Temperature Range
90 ns
F
FDIP40W
1
0 to 70 °C
-100
100 ns
B
PDIP40
6
–40 to 85 °C
-120
120 ns
K
PLCC44
-150
150 ns
N
-200
200 ns
TSOP40
8 x 14mm
-90
(1)
TR
Tape & Reel
Packing
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further informationon any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
10/15
M27V102
FDIP40W - 40 pin Ceramic Frit-seal DIP, with window
mm
Symb
Typ
inches
Min
Max
A
Typ
Min
5.72
Max
0.225
A1
0.51
1.40
0.020
0.055
A2
3.91
4.57
0.154
0.180
A3
3.89
4.50
0.153
0.177
B
0.41
0.56
0.016
0.022
–
–
–
–
B1
1.45
0.057
C
0.23
0.30
0.009
0.012
D
51.79
52.60
2.039
2.071
–
–
1.900
–
–
0.600
D2
48.26
E
15.24
E1
–
–
13.06
13.36
–
–
0.514
0.526
e
2.54
–
–
0.100
–
–
eA
14.99
–
–
0.590
–
–
16.18
18.03
0.637
0.710
eB
L
3.18
S
1.52
2.49
–
–
α
4°
11°
N
40
∅
7.62
0.125
0.098
–
–
4°
11°
40
A2
A3
A1
B1
0.300
0.060
B
A
L
e
α
eA
D2
C
eB
D
S
N
∅
E1
E
1
FDIPW-a
Drawing is not to scale.
11/15
M27V102
PDIP40 - 40 pin Plastic DIP, 600 mils body width
mm
Symb
inches
Typ
Min
Max
Typ
Min
Max
A
4.45
–
–
0.175
–
–
A1
0.64
0.38
–
0.025
0.015
–
A2
3.56
3.91
0.140
0.154
B
0.38
0.53
0.015
0.021
B1
1.14
1.78
0.045
0.070
C
0.20
0.31
0.008
0.012
D
51.78
52.58
2.039
2.070
–
–
–
–
E
14.80
16.26
0.583
0.640
E1
13.46
13.99
0.530
0.551
–
D2
48.26
1.900
e1
2.54
–
–
0.100
–
eA
15.24
–
–
0.600
–
eB
15.24
17.78
0.600
0.700
L
3.05
3.81
0.120
0.150
S
1.52
2.29
0.060
0.090
α
0°
15°
0°
15É
N
40
40
A2
A1
B1
B
A
L
e1
α
eA
D2
C
eB
D
S
N
E1
E
1
PDIP
Drawing is not to scale.
12/15
M27V102
PLCC44 - 44 lead Plastic Leaded Chip Carrier, square
mm
Symb
Typ
inches
Min
Max
A
4.20
A1
Min
Max
4.70
0.165
0.185
2.29
3.04
0.090
0.120
A2
–
0.51
–
0.020
B
0.33
0.53
0.013
0.021
B1
0.66
0.81
0.026
0.032
D
17.40
17.65
0.685
0.695
D1
16.51
16.66
0.650
0.656
D2
14.99
16.00
0.590
0.630
E
17.40
17.65
0.685
0.695
E1
16.51
16.66
0.650
0.656
E2
14.99
16.00
0.590
0.630
–
–
–
–
0.00
0.25
0.000
0.010
–
–
–
–
e
1.27
F
R
0.89
N
Typ
0.050
0.035
44
CP
44
0.10
0.004
D
A1
D1
A2
1 N
B1
E1 E
Ne
e
D2/E2
F
B
0.51 (.020)
1.14 (.045)
A
Nd
R
CP
PLCC
Drawing is not to scale.
13/15
M27V102
TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14mm
mm
Symb
Typ
inches
Min
Max
A
Typ
Min
1.20
0.047
A1
0.05
0.15
0.002
0.006
A2
0.95
1.05
0.037
0.041
B
0.17
0.27
0.007
0.011
C
0.10
0.21
0.004
0.008
D
13.80
14.20
0.543
0.559
D1
12.30
12.50
0.484
0.492
E
9.90
10.10
0.390
0.398
–
–
–
–
L
0.50
0.70
0.020
0.028
α
0°
5°
0°
5°
N
40
e
0.50
0.020
40
CP
0.10
0.004
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
TSOP-a
Drawing is not to scale.
14/15
Max
A1
α
L
M27V102
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