TI1 INA110SG2 Fast-settling fet-input instrumentation amplifier Datasheet

INA110
INA
INA
110
110
SBOS147A – SEPTEMBER 1986 – JULY 2005
Fast-Settling FET-Input
INSTRUMENTATION AMPLIFIER
FEATURES
APPLICATIONS
●
●
●
●
●
●
●
●
● MULTIPLEXED INPUT DATA
ACQUISITION SYSTEM
● FAST DIFFERENTIAL PULSE AMPLIFIER
● HIGH SPEED GAIN BLOCK
● AMPLIFICATION OF HIGH IMPEDANCE
SOURCES
LOW BIAS CURRENT: 50pA max
FAST SETTLING: 4µs to 0.01%
HIGH CMR: 106dB min; 90dB at 10kHz
INTERNAL GAINS: 1, 10, 100, 200, 500
VERY LOW GAIN DRIFT: 10 to 50ppm/°C
LOW OFFSET DRIFT: 2µV/°C
LOW COST
PINOUT SIMILAR TO AD524 AND AD624
DESCRIPTION
1
–In
The INA110 is a versatile monolithic FET-input
instrumentation amplifier. Its current-feedback circuit topology and laser trimmed input stage provide
excellent dynamic performance and accuracy. The INA110
settles in 4µs to 0.01%, making it ideal for high speed or
multiplexed-input data acquisition systems.
Internal gain-set resistors are provided for gains of 1, 10,
100, 200, and 500V/V. Inputs are protected for differential
and common-mode voltages up to ±VCC. Its very high input
impedance and low input bias current make the INA110 ideal
for applications requiring input filters or input protection
circuitry.
INA110
FET
Input
13 4.44kΩ
10kΩ
X 10
10kΩ
10
A1
12
404Ω
16
201Ω
11
80.2Ω
Sense
X 100
(1)
20kΩ
X 200
9
A3
X 500
Output
20kΩ
3
RG
10kΩ
10kΩ
6
A2
Ref
2
+In
The INA110 is available in 16-pin plastic and ceramic DIPs,
and in the SOL-16 surface-mount package. Military, industrial and commercial temperature range grades are available.
FET
Input
4
5
Input
Offset
Adjust
8
7
+VCC
–VCC
14
15
Output
Offset
Adjust
NOTE: (1) Connect to RG for desired gain.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 1986-2005, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage .................................................................................. ±18V
Input Voltage Range .......................................................................... ±VCC
Operating Temperature Range: G .................................. –55°C to +125°C
P, U ............................... –25°C to +85°C
Storage Temperature Range: G ..................................... –65°C to +150°C
P, U ................................... –40°C to +85°C
Lead Temperature (soldering, 10s): G, P ...................................... +300°C
(soldering, 3s): U ............................................ +260°C
Output Short Circuit Duration ............................... Continuous to Common
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
PACKAGE/ORDERING INFORMATION
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
For the most current package and ordering information, see
the Package Option Addendum at the end of this document,
or see the TI website at www.ti.com.
PIN CONFIGURATION
Top View
2
DIP/SOIC
–In
1
16
x200
+In
2
15
Output Offset Adj.
RG
3
14
Output Offset Adj.
Input Offset Adj.
4
13
x10
Input Offset Adj.
5
12
x100
Reference
6
11
x500
–VCC
7
10
Output Sense
+VCC
8
9
Output
INA110
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ELECTRICAL CHARACTERISTICS
At +25°C, ±VCC = 15VDC, and RL = 2kΩ, unless otherwise specified.
INA110AG
PARAMETER
CONDITIONS
GAIN
Range of Gain
Gain Equation(1)
Gain Error, DC: G = 1
G = 10
G = 100
G = 200
G = 500
Gain Temp. Coefficient: G = 1
G = 10
G = 100
G = 200
G = 500
Nonlinearity, DC: G = 1
G = 10
G = 100
G = 200
G = 500
OUTPUT
Voltage, RL = 2kΩ
Current
Short-Circuit Current
Capacitive Load
MIN
TYP
1
*
0.002
0.01
0.02
0.04
0.1
±3
±4
±6
±10
±25
±0.001
±0.002
±0.004
±0.006
±0.01
Over Temperature
Over Temperature
±10
±5
Stability
INPUT OFFSET VOLTAGE(2)
Initial Offset: G, P
INA110BG, SG
MIN
800
*
*
G = 1 + [40k/(RG + 50Ω)]
*
0.02
0.005
0.05
0.01
0.1
0.02
0.2
0.05
0.5
*
±10
±2
±10
±3
±20
±5
±30
±10
±50
±0.0005 ±0.005
±0.001 ±0.005
±0.002
±0.01
±0.003
±0.01
±0.005
±0.02
0.04
0.1
0.2
0.4
1
±20
±20
±40
±60
±100
±0.01
±0.01
±0.02
±0.02
±0.04
±12.7
±25
±25
5000
*
*
±(100 + ±(500 +
1000/G) 5000/G)
TYP
INA110KP, KU
MAX
MAX
*
*
*
*
±(50 +
600/G)
MIN
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
±(250 +
3000/G)
vs Supply
BIAS CURRENT
Initial Bias Current
Initial Offset Current
Impedance: Differential
Common-Mode
VOLTAGE RANGE
Range, Linear Response
CMR with 1kΩ Source Imbalance:
G=1
G = 10
G = 100
G = 200
G = 500
VCC = ±6V to ±18V
Each Input
VIN Diff. = 0V(3)
DC
DC
DC
DC
DC
±(2 +
20/G)
±(4 +
60/G)
±(5 +
100/G)
±(30 +
300/G)
±(1 +
10/G)
±(2 +
30/G)
±(2 +
50/G)
±(10 +
180/G)
20
2
5x1012||6
2x1012||1
100
50
10
1
*
*
50
25
±10
±12
70
87
100
100
100
90
104
110
110
110
80
96
106
106
106
100
112
116
116
116
MAX
UNITS
*
V/V
V/V
%
%
%
%
%
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
% of FS
% of FS
% of FS
% of FS
% of FS
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
V
mA
mA
pF
*
±(200 + ±(1000 +
2000/G) 5000/G)
*
U
vs Temperature
TYP
µV
µV
µV/°C
*
*
µV/V
*
*
*
*
*
*
pA
pA
Ω || pF
Ω || pF
*
*
V
*
*
*
*
*
*
*
*
*
*
dB
dB
dB
dB
dB
INPUT NOISE(4)
Voltage, fO = 10kHz
fB = 0.1Hz to 10Hz
Current, fO = 10kHz
10
1
1.8
*
*
*
*
*
*
nV/√Hz
µVPP
fA/√Hz
OUTPUT NOISE(4)
Voltage, fO = 10kHz
fB = 0.1Hz to 10Hz
65
8
*
*
*
*
nV/√Hz
µVPP
2.5
2.5
470
240
100
*
*
*
*
*
*
*
*
*
*
MHz
MHz
kHz
kHz
kHz
*
*
*
*
*
*
*
*
*
*
*
*
*
*
DYNAMIC RESPONSE
Small Signal: G = 1
G = 10
G = 100
G = 200
G = 500
Full Power
Slew Rate
Settling Time:
0.1%, G = 1
G = 10
G = 100
G = 200
G = 500
–3dB
VOUT = ±10V,
G = 2 to 100
G = 2 to 100
VO = 20V Step
190
12
270
17
4
2
3
5
11
INA110
SBOS147A
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*
*
*
*
kHz
V/µs
µs
µs
µs
µs
µs
3
ELECTRICAL CHARACTERISTICS
(Cont)
At +25°C, ±VCC 15VDC, and RL = 2KΩ, unless otherwise specified.
INA110AG
PARAMETER
DYNAMIC RESPONSE (CONT)
Settling Time:
0.01%,G = 1
G = 10
G = 100
G = 200
G = 500
Recovery(5)
POWER SUPPLY
Rated Voltage
Voltage Range
Quiescent Current
TEMPERATURE RANGE
Specification: P, U
G
Operation
Storage
θJA
CONDITIONS
MIN
VO = 20V Step
50% Overdrive
±6
INA110BG, SG
TYP
MAX
5
3
4
7
16
1
12.5
7.5
7.5
12.5
25
±15
MIN
*
–25
+85
–55
–65
+125
+150
*
–55
*
*
±3
TYP
MAX
*
*
*
*
*
*
*
*
*
*
*
MIN
100
*
*
TYP
MAX
*
*
*
*
*
+125
*
*
0
+70
–25
–40
+85
+85
*
*
UNITS
µs
µs
µs
µs
µs
µs
*
*
*
*
*
*
*
±18
±4.5
VO = 0V
INA110KP, KU
*
*
V
V
mA
°C
°C
°C
°C
°C/W
* Same as INA110AG.
NOTES: (1) Gains other than 1, 10, 100, 200, and 500 can be set by adding an external resistor, RG, between pin 3 and pins 11, 12 and 16. Gain accuracy is a function
of RG and the internal resistors which have a ±20% tolerance with 20ppm/°C drift. (2) Adjustable to zero. (3) For differential input voltage other than zero, see Typical
Characteristics. (4) VNOISE RTI = √VN2 INPUT + (VN OUTPUT/Gain)2. (5) Time required for output to return from saturation to linear operation following the removal of an input
overdrive voltage.
4
INA110
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SBOS147A
TYPICAL CHARACTERISTICS
At TA = +25°C and ±VCC = 15VDC, unless otherwise noted.
OUTPUT SWING vs SUPPLY
±16
±12
±13
Output Voltage (V)
Input Voltage Range (V)
INPUT VOLTAGE RANGE vs SUPPLY
±15
±9
±6
RL = 2kΩ
±10
±7
±3
±4
±6
±9
±15
±12
±18
±6
±9
Power Supply Voltage (V)
OUTPUT SWING vs LOAD RESISTANCE
±18
Input Bias Current (pA)
25
±12
±8
±4
0
20
15
10
5
0
0
400
800
1.2k
1.6k
2M
±6
±12
±9
Load Resistance (Ω)
±15
±18
Power Supply Voltage (V)
GAIN vs FREQUENCY
BIAS CURRENT vs TEMPERATURE
1k
100nA
G = 500
G = 200
10nA
G = 100
100
Gain (V/V)
Input Bias Current
±15
BIAS CURRENT vs SUPPLY
±16
Output Voltage (V)
±12
Power Supply Voltage (V)
1pA
100pA
G = 10
10
10pA
G=1
1
1pA
–55
–25
5
35
65
95
125
100
1k
10k
100k
1M
10M
Frequency (Hz)
Temperature (°C)
INA110
SBOS147A
10
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5
TYPICAL CHARACTERISTICS (Cont)
At TA = +25°C and ±VCC = 15VDC, unless otherwise noted.
POWER SUPPLY REJECTION vs FREQUENCY
CMR vs FREQUENCY
120
120
G = 500
Power Supply Rejection (dB)
Common-Mode Rejection (dB)
G = 500
100
G = 200
80
G = 100
60
G = 10
40
G=1
20
100
G = 200
80
G = 100
60
G = 10
40
G=1
20
0
0
1
10
100
1k
10k
100k
1
1M
10
100
Frequency (Hz)
10
0
1M
–10
10
0
–100
20
10
0
20
Time (µs)
SETTLING TIME vs GAIN
(0.01%, 20V Step)
OUTPUT NOISE VOLTAGE vs FREQUENCY
20
1000
Output Noise Voltage (nV/√Hz)
Settling Time (µs)
100k
100
Time (µs)
15
10
5
0
500
200
100
50
20
10
1
10
100
1k
1
Gain (V/V)
6
10k
SMALL SIGNAL TRANSIENT RESPONSE
(G = 100)
Output Voltage (V)
Output Voltage (V)
LARGE SIGNAL TRANSIENT RESPONSE
(G = 100)
0
1k
Frequency (Hz)
10
100
1k
10k
Frequency (Hz)
INA110
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SBOS147A
TYPICAL CHARACTERISTICS (Cont)
At TA = +25°C and ±VCC = 15VDC, unless otherwise noted.
COMMON-MODE VOLTAGE vs
DIFFERENTIAL INPUT VOLTAGE
INPUT NOISE VOLTAGE vs FREQUENCY
12
50
Common-Mode Voltage (V)
Input Noise Voltage (nV/√Hz)
100
20
10
5
9
6
3
2
0
1
1
10
100
1k
0
10k
3
6
9
12
Differential Input Voltage x Gain (V) = VO
Frequency (Hz)
WARM-UP DRIFT vs TIME
Change In Input Offset Voltage (µV)
50
40
30
20
10
0
0
1
2
3
4
5
Time (minutes)
INA110
SBOS147A
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7
DISCUSSION OF
PERFORMANCE
A simplified diagram of the INA110 is shown on the first
page. The design consists of the classical three operational
amplifier configuration using current-feedback type op amps
with precision FET buffers on the input. The result is an
instrumentation amplifier with premium performance not
normally found in integrated circuits.
INA110’s input (RTI) is the offset of the input stage plus
the offset of the output stage divided by the gain of the
input stage. This allows specification of offset independent
of gain.
+VCC –VCC
Input
Offset
Adjust
100kΩ 100kΩ
The input section (A1 and A2) incorporates high performance, low bias current, and low drift amplifier circuitry.
The amplifiers are connected in the noninverting configuration to provide high input impedance (1012Ω). Laser-trimming is used to achieve low offset voltage. Input cascoding
assures low bias current and high CMR. Thin-film resistors
on the integrated circuit provide excellent gain accuracy and
temperature stability.
The output section (A3) is connected in a unity-gain difference amplifier configuration. Precision matching of the four
10kΩ resistors, especially over temperature and time,
assures high common-mode rejection.
BASIC POWER SUPPLY
AND SIGNAL CONNECTIONS
Figure 1 shows the proper connections for power supply and
signal. Supplies should be decoupled with 1µF tantalum
capacitors as close to the amplifier as possible. To avoid
gain and CMR errors introduced by the external circuit,
connect grounds as indicated, being sure to minimize ground
resistance. Resistance in series with the reference (pin 6)
will degrade CMR. To maintain stability, avoid capacitance
from the output to the gain set, offset adjust, and input pins.
∆VIN
x10
x100
x200
x500
1
13
12
16
11
3
2
10
4
5
1
∆VIN
14
15
10
INA110
9
VOUT
2
6
FIGURE 2. Offset Adjustment Circuit.
For systems using computer autozeroing techniques, neither
offset nor offset drift are of concern. In many other applications, the factory-trimmed offset gives excellent results.
When greater accuracy is desired, one adjustment is usually
sufficient. In high gains (>100) adjust only the input offset,
and in low gains the output offset. For higher precision in all
gains, both can be adjusted by first selecting high gain and
adjusting input offset and then low gain and adjusting output
offset. The offset adjustment will, however, add to the drift
by approximately 0.33µV/°C per 100µV of input offset
voltage that is adjusted. Therefore, care should be taken
when considering use of adjustment.
Output offsetting can be accomplished as shown in Figure 3
by applying a voltage to the reference (pin 6) through a
buffer. This limits the resistance in series with pin 6 to
minimize CMR error. Be certain to keep this resistance low.
Note that the offset error can be adjusted at this reference
point with no appreciable degradation in offset drift.
Sense
INA110
Output
Offset
Adjust
9
VOUT
6
RL
8
7
1
1µF
10
VOUT = ∆VIN G
∆VIN
+VCC
–VCC
INA110
2
9
VOUT
+VCC
6
R1
1µF
OPA177
VOFFSETTING
FIGURE 1. Basic Circuit Connection.
VOFFSETTING
R2
–VCC
R3
VOUT = VOFFSETTING + ∆VIN G.
OFFSET ADJUSTMENT
Figure 2 shows the offset adjustment circuit for the INA110.
Both the offset of the input stage and output stage can be
adjusted separately. Notice that the offset referred to the
8
With ±VCC = 15V, R1 = 100kΩ, R2 = 1MΩ.
R3 = 10kΩ, VOFFSETTING = ±150mV.
FIGURE 3. Output Offsetting.
INA110
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SBOS147A
GAIN SELECTION
Gain selection is accomplished by connecting the appropriate pins together on the INA110. Table I shows possible
gains from the internal resistors. Keep the connections as
short as possible to maintain accuracy.
CONNECT PIN 3
TO PIN
GAIN
GAIN
ACCURACY (%)
The following gains have assured accuracy:
1
none
0.02
10
13
0.05
100
12
0.1
200
16
0.2
500
11
0.5
The following gains have typical accuracy as shown:
300
12, 16
0.25
600
11, 12
0.25
700
11, 16
2
800
11, 12, 16
2
are eliminated since they are inside the feedback loop.
Proper connection is shown in Figure 1. When more current
is to be supplied, a power booster can be placed within the
feedback loop as shown in Figure 5. Buffer errors are
minimized by the loop gain of the output amplifier.
GAIN
DRIFT (ppm/°C)
R1
1
10
10
20
30
50
10
∆VIN
VOUT
9
6
2
Output Stage Gain
10
40
40
80
R3
(R2 || 20kΩ) + R1 + R3
=
R2 || 20kΩ
FIGURE 4. Gain Adjustment of Output Stage Using H Pad
Attenuator.
TABLE I. Internal Gain Connections.
Gains other than 1, 10, 100, 200, and 500 can be set by
adding an external resistor, RG, between pin 3 and pins 12,
16, and 11. Gain accuracy is a function of RG and the
internal resistors which have a ±20% tolerance with
20ppm/°C drift. The equation for choosing RG is shown
below.
40kΩ
– 50Ω
RG =
G –1
Gain can also be changed in the output stage by adding
resistance to the feedback loop shown in Figure 4. This is
useful for increasing the total gain or reducing the input
stage gain to prevent saturation of input amplifiers.
The output gain can be changed as shown in Table II.
Matching of R1 and R3 is required to maintain high CMR. R2
sets the gain with no effect on CMR.
OUTPUT STAGE GAIN
R1 AND R3
R2
2
5
10
1.2kΩ
1kΩ
1.5kΩ
2.74kΩ
511Ω
340Ω
TABLE II. Output Stage Gain Control.
COMMON-MODE INPUT RANGE
It is important not to exceed the input amplifiers’ dynamic
range (see Typical Characteristics). The differential input
signal and its associated common-mode voltage should not
cause the output of A1 and A2 (input amplifiers) to exceed
approximately ±10V with ±15V supplies or nonlinear operation will result. Such large common-mode voltages, when
the INA110 is in high gain, can cause saturation of the input
stage even though the differential input is very small. This
can be avoided by reducing the input stage gain and increasing the output stage gain with an H pad attenuator (see
Figure 4).
OUTPUT SENSE
An output sense has been provided to allow greater accuracy
in connecting the load. By attaching this feedback point to
the load at the load site, IR drops due to load currents that
Sense
1
10
∆VIN
INA110
2
9
VOUT
3553
6
RL
IL = 100mA
FIGURE 5. Current Boosting the Output.
LOW BIAS CURRENT
OF FET INPUT ELIMINATES DC ERRORS
Because the INA110 has FET inputs, bias currents drawn
through input source resistors have a negligible effect on DC
accuracy. The picoamp levels produce no more than microvolts through megohm sources. Thus, input filtering and
input series protection are readily achievable.
A return path for the input bias currents must always be
provided to prevent charging of stray capacitance. Otherwise, the output can wander and saturate. A 1MΩ to 10MΩ
resistor from the input to common will return floating
sources such as transformers, thermocouples, and
AC-coupled inputs (see Applications section).
DYNAMIC PERFORMANCE
The INA110 is a fast-settling FET input instrumentation
amplifier. Therefore, careful attention to minimize stray
capacitance is necessary to achieve specified performance.
High source resistance will interact with input capacitance to
reduce the overall bandwidth. Also, to maintain stability,
avoid capacitance from the output to the gain set, offset
adjust, and input pins.
Applications with balanced-source impedance will provide
the best performance. In some applications, mismatched
source impedances may be required. If the impedance in the
INA110
SBOS147A
INA110
R2
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9
negative input exceeds that in the positive input, stray
capacitance from the output will create a net negative feedback and improve the circuit stability. If the impedance in
the positive input is greater, the feedback due to stray
capacitance will be positive and instability may result. The
degree of positive feedback depends upon source impedance
imbalance, operating gain, and board layout. The addition of
a small bypass capacitor of 5pF to 50pF directly between the
inputs of the IA will generally eliminate any positive feedback. CMR errors due to the input impedance mismatch will
also be reduced by the capacitor.
The INA110 is designed for fast settling with easy gain
selection. It has especially excellent settling in high gain. It
can also be used in fast-settling unity-gain applications. As
with all such amplifiers, the INA110 does exhibit significant
gain peaking when set to a gain of 1. It is, however,
unconditionally stable. The gain peaking can be cancelled
by band-limiting the negative input to 400kHz with a simple
external RC circuit for applications requiring flat response.
CMR is not affected by the addition of the 400kHz RC in a
gain of 1.
Another distinct advantage of the INA110 is the high frequency CMR response. High frequency noise and sharp
common-mode transients will be rejected. To preserve AC
CMR, be sure to minimize stray capacitance on the input
lines. Matching the RCs in the two inputs will help to
maintain high AC CMR.
APPLICATIONS
In addition to general purpose uses, the INA110 is designed
to accurately handle two important and demanding applications: (1) inputs with high source impedances such as
capacitance/crystal/photodetector sensors and low-pass
filters and series-input protection devices, and (2) rapidscanning data acquisition systems requiring fast settling
time. Because the user has access to the output sense, current
sources can also be constructed using a minimum of external
components. Figures 6 through 19 show application circuits.
+15V
1
8
X200 16
3
10
INA110
VOUT
6
2
Transducer
9
7
–15V
FIGURE 6. Transformer-Coupled Amplifier.
+15V
1
+15V
1
X100
12
3
Thermocouple
Transducer or
Other Floating
Source
2
1MΩ
X200
∆VIN
8
10
INA110
9
16
3
2
VOUT
8
10
INA110
9
VOUT
6
7
6
–15V
7
100Ω
–15V
OPA121
Divider minimizes degredation of CMR due to
distributed capacitance on the input lines.
FIGURE 7. Floating Source Instrumentation Amplifier.
10
FIGURE 8. Instrumentation Amplifier with Shield Driver.
INA110
www.ti.com
SBOS147A
VREF
+15V
75kΩ(1)
1
8
X500 11
300Ω
1µF(1)
75kΩ(1)
3
10
INA110
2
9
VOUT
6
7
–15V
FET input allows low-pass filtering with minimal effect on DC accuracy.
NOTE: (1) Larger resistors and a smaller capacitor can be used.
FIGURE 9. Bridge Amplifier with 1Hz Low-Pass Input Filter.
+15V
+15V
1µF
1
X100
3
100mVPP
10
INA110
10MΩ
9
In 1
In 2
VOUT
6
2
1µF
1
7
8
1
B-B
MPC800
10MΩ
8
12
In 15
In 16
X10
8
13
3
10
INA110
VOUT
SHC5320
6
2
–15V
9
7
–15V
FIGURE 10. AC-Coupled Differential Amplifier for
Frequencies Greater Than 0.016Hz.
FIGURE 12. Rapid-Scanning-Rate Data Acquisition Channel
with 5µs Settling to 0.01%.
+15V
1
+15V
∆VIN
X10
X100
X200
X500
Decoder/
Latch/Driver
1
13
12
16
11
3
2
8
X10 13
8
10
3
9
VIN
VOUT
5.34MΩ(1)
5.34MΩ(1)
10
INA110
2
9
VOUT
6
7
6
7
1000pF
–15V
2.67MΩ(1)
–15V
2kΩ
A0 A1 A2
500pF
NOTE: Use manual switch or low resistance relay.
Layout is critical (see section on Dynamic Performance).
500pF
NOTE: (1) For 50Hz use 3.16MΩ and 6.37MΩ.
2kΩ potentiometer sets Q.
FIGURE 11. Programmable-Gain Instrumentation Amplifier
(Precision Noninverting or Inverting Buffer with
Gain).
FIGURE 13. 60Hz Input Notch Filter.
INA110
SBOS147A
www.ti.com
11
+15V
R1
+15V
D1
V1
D2
–15V
+15V
∆VIN
R2
V2
V1
1
X200
8
16
3
D3
10
INA110
∆VIN
9
VOUT
V2
X100
3
D4
990kΩ
–15V
10
INA110
9
VOUT
6
2
10kΩ
For lower voltage, lower resistor noise:
R1 = R2 = 20kΩ, D1 – D4 = FDH300 (1nA leakage)
8
12
10kΩ
7
–15V
Overall G = 1
1
6
2
+15V
990kΩ
7
–15V
For higher voltage, higher resistor noise:
R1 = R2 = 100kΩ, D1 – D4 = 2N4117A (1pA leakage)
Common-mode range = ±1000V.
CMR is dependent on ratio matching
of external input resistors.
Matching of RCs on inputs will affect CMR, but
can be optimized by trimming R1 or R2.
FIGURE 14. Input-Protected Instrumentation Amplifier.
FIGURE 15. High Common-Mode Voltage Differential
Amplifier.
–15V
+15V
+15V
13
1
8
X10 13
∆VIN
3
RG
10
INA110
6
7
8
9
6
2
16
15
PGA102
VOUT
2
7
1
3
4
–15V
CODE
GAIN
TYPICAL 0.01% SETTLING TIME
00
01
10
10
100
1000
6µs
6µs
12µs
X10 X100
PGA Gain
Select
FIGURE 16. Digitally-Controlled Fast-Settling Programmable Gain Instrumentation Amplifier.
+15V
+15V
∆VIN
X10
X100
X200
X500
RG
1
13
12
16
11
3
2
+15V
8
X10
X100
X200
X500
RG
R
10
INA110
9
2N2222A
6
7
–15V
1kΩ
1
13
12
16
11
3
2
8
10
INA110
9
6
7
+
∆VOUT
–
–15V
R
IOUT
RL
∆VIN
IOUT = (∆VIN) (G) (1/10k + 1/R)
For 0mA to 20mA output, R = 50.25Ω with (∆VIN) (G) = 1V
FIGURE 17. Differential Input FET Buffered Current
Source.
12
X10
X100
X200
X500
RG
1
13
12
16
11
3
2
8
10
INA110
9
6
7
FIGURE 18. Differential Input/Differential Output
Amplifier.
INA110
www.ti.com
SBOS147A
PACKAGE OPTION ADDENDUM
www.ti.com
5-Aug-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
INA110AG
NRND
ZZ (BB)
ZZ109
16
TBD
Call TI
Call TI
INA110KP
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-55 to 125
INA110KP
INA110KPG4
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-55 to 125
INA110KP
INA110KU
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU-DCC
Level-3-260C-168 HR
INA110KU
INA110KUG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU-DCC
Level-3-260C-168 HR
INA110KU
INA110SG
NRND
CDIP SB
JD
16
1
Green (RoHS
& no Sb/Br)
AU
N / A for Pkg Type
INA110SG
INA110SG1
OBSOLETE
TO-100
LME
10
TBD
Call TI
Call TI
INA110SG2
OBSOLETE
TO-100
LME
10
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
5-Aug-2016
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
®
PACKAGE DRAWING
MCDI012
MECHANICAL DATA
MMBC006 – MARCH 2001
LME (O–MBCY–W10)
METAL CYLINDRICAL PACKAGE
ø
0.370 (9,40)
0.335 (8,51)
ø
0.335 (8,51)
0.305 (7,75)
0.040 (1,02)
0.010 (0,25)
0.185 (4,70)
0.165 (4,19)
0.040 (1,02)
0.010 (0,25)
0.500 (12,70) MIN
Seating
Plane
ø
ø
0.021 (0,53)
0.016 (0,41)
0.160 (4,06)
0.120 (3,05)
0.120 (3,05)
0.110 (2,79)
4
3
0.034 (0,86)
0.028 (0,71)
36°
5
2
6
1
10
7
9
8
0.230 (5,84)
0.045 (1,14)
0.029 (0,74)
4202488/A 03/01
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Leads in true position within 0.010 (0,25) R @ MMC at seating plane.
Pin numbers shown for reference only. Numbers may not be marked on package.
Falls within JEDEC MO–006/TO-100.
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• DALLAS, TEXAS 75265
1
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