Precision Integrated Analog Front End, Controller, and PWM for Battery Test and Formation Systems AD8452 Data Sheet FEATURES GENERAL DESCRIPTION CC and CV battery test and formation modes with transparent and automatic switchover, for systems of 20 Ah or less Precise measurement of voltage and current Independent feedback control blocks Highly accurate, factory trimmed instrumentation and differential amplifiers In-amp for current sense gain: 66 V/V Difference amplifier for voltage sense gain: 0.4 V/V Stable over temperature: offset voltage drift <0.6 μV/°C (maximum) Gain drift: <3 ppm/°C (maximum) Current sense CMRR: 120 dB minimum Popular SMPS control for charge/discharge High PWM linearity with internal ramp voltage 50 kHz to 300 kHz user controlled switching frequency Synchronization output or input with adjustable phase shift Programmable soft start The AD8452 combines a precision analog front-end controller and switch mode power supply (SMPS), pulse-width modulator (PWM) driver into a single silicon platform for high volume battery testing and formation manufacturing. A precision instrumentation amplifier (in-amp) measures the battery charge/ discharge current to better than ±0.1% accuracy, while an equally accurate difference amplifier measures the battery voltage. Internal laser trimmed resistor networks establish the in-amp and difference amplifier gains (66 V/V and 0.4 V/V, respectively), and stabilize the AD8452 performance across the rated operating temperature range. Desired battery cycling current and voltage levels are established by applying precise control voltages to the ISET and VSET inputs. Actual charge and discharge current levels are sensed (usually by a high power, highly accurate shunt resistor) whose value is carefully selected according to system parameters. Switching between constant current (CC) and constant voltage (CV) loop integration is instantaneous, automatic, and completely transparent to the observer. A logic high at the MODE input selects the charge or discharge mode (high for charge, low for discharge). APPLICATIONS Battery formation and testing High efficiency battery test systems with recycle capability Battery conditioning (charging and discharging) systems The AD8452 simplifies designs by providing excellent performance, functionality, and overall reliability in a space saving 48-lead, 7 mm × 7 mm × 1.4 mm LQFP package rated for operation at temperatures from −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM CLN CLP EN VCL +DCBUS VIN SYNC CC FILTER AMPLIFIER SCFG VCL DH MODE SELECT VBAT IBAT DIFF IN-AMP AMP CV FILTER AMPLIFIER ISREFH/ ISREFL DL SS PWM ×1 MOSFET DRIVER CLVT ISV VINT ISET VSET MODE IVE0/IVE1 ISMEA SYSTEM CONTROL VVE0/VVE1 BVMEA LOOP COMP (×4) DT VREF DMAX FAULT BV AD8452 DGND 16187-001 BV FREQ VREF 66× ISVP BVP BVN 0.4× ISVN BVREFH/ BVREFL ISV Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved. 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AD8452 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Shutdown ..................................................................................... 24 Applications ....................................................................................... 1 Undervoltage Lockout (UVLO) ............................................... 24 General Description ......................................................................... 1 Soft Start ...................................................................................... 24 Functional Block Diagram .............................................................. 1 PWM Drive Signals.................................................................... 25 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Peak Current Protection and Diode Emulation (Synchronous)............................................................................. 25 Analog Front-End and Controller Specifications .................... 3 Frequency and Phase Control .................................................. 26 Pulse-Width Modulator Specifications ..................................... 5 Maximum Duty Cycle ............................................................... 26 Digital Interface Specifications ................................................... 6 Fault Input ................................................................................... 27 Power Supply ................................................................................. 7 Thermal Shutdown (TSD) ........................................................ 27 Temperature Range Specifications ............................................. 7 Applications Information .............................................................. 28 Absolute Maximum Ratings............................................................ 8 Analog Controller ...................................................................... 28 Thermal Resistance ...................................................................... 8 Functional Description .............................................................. 28 ESD Caution .................................................................................. 8 Power Supply Connections ....................................................... 29 Pin Configuration and Function Descriptions ............................. 9 Current Sense In-Amp Connections ....................................... 29 Typical Performance Characteristics ........................................... 11 Voltage Sense Differential Amplifier Connections ................ 29 In-Amp Characteristics ............................................................. 11 Battery Current and Voltage Control Inputs (ISET and VSET) ........................................................................ 29 Difference Amplifier Characteristics ....................................... 12 CC and CV Loop Filter Amplifiers and VSET Buffer (except where Noted)............................................................................... 13 Loop Filter Amplifiers ............................................................... 30 Selecting Charge or Discharge Options .................................. 30 Reference Characteristics .......................................................... 15 Select RCL and RCLVT for the Peak Current Limit .................. 30 Pulse-Width Modulator............................................................. 16 Setting the Operating Frequency and Programming the Synchonization Pin .................................................................... 31 Theory of Operation ...................................................................... 18 Introduction ................................................................................ 18 Instrumentation Amplifier (In-Amp) ..................................... 19 Difference Amplifier .................................................................. 20 CC and CV Loop Filter Amplifiers .......................................... 20 Charge and Discharge Control ................................................. 23 Programming the Maximum Duty Cycle ............................... 32 Selecting CSS ................................................................................ 33 Additional Information ............................................................. 33 Outline Dimensions ....................................................................... 34 Ordering Guide .......................................................................... 34 Input and Output Supply Pins .................................................. 23 REVISION HISTORY 10/2017—Revision 0: Initial Version Rev. 0 | Page 2 of 34 Data Sheet AD8452 SPECIFICATIONS AVCC = 15 V, AVEE = −15 V, VIN = 24 V, and TA = 25°C, unless otherwise noted. ANALOG FRONT-END AND CONTROLLER SPECIFICATIONS Table 1. Parameter CURRENT SENSE INSTRUMENTATION AMPLIFIER Gain Gain Error Gain Drift Offset Voltage Referred to Input (RTI) Offset Voltage Drift Input Bias Current Input Common-Mode Voltage Range Differential Input Impedance Common-Mode Input Impedance Output Voltage Swing Reference Input Voltage Range Reference Bias Current Output Voltage Level Shift Maximum Scale Factor Short-Circuit Current Common-Mode Rejection Ratio (CMRR) Temperature Coefficient Power Supply Rejection Ratio (PSRR) Small Signal −3 dB Bandwidth Slew Rate VOLTAGE SENSE DIFFERENCE AMPLIFIER Gain Gain Error Gain Drift Offset Voltage Referred to Output (RTO) Offset Voltage Drift Differential Input Voltage Range Input Common-Mode Voltage Range Differential Input Impedance Input Common-Mode Impedance Output Voltage Swing Reference Input Voltage Range Output Voltage Level Shift Maximum Scale Factor Short-Circuit Current CMRR Temperature Coefficient PSRR Small Signal −3 dB Bandwidth Slew Rate Test Conditions/Comments Min Typ Max 66 VISMEA = ±10 V TA = TMIN to TMAX ISREFH pin and ISREFL pin grounded TA = TMIN to TMAX −100 −0.6 VISVP − VISVN = 0 V AVEE + 2.3 −0.1 15 ±0.1 3 +100 +0.6 30 AVCC − 2.4 150 150 RL = 10 kΩ ISREFH pin and ISREFL pin tied together VISVP = VISVN = 0 V ISREFL pin grounded ISREFH pin connected to VREF pin VISMEA/VISREFH AVEE + 1.5 AVEE + 1.5 ΔVCM = 20 V TA = TMIN to TMAX ΔVS = 10 V 120 AVCC − 1.2 AVCC − 1.5 5 11 4.4 12.5 5 40 14 5.6 0.01 122 ΔVISMEA = 10 V 140 675 5 0.4 VIN = ±10 V TA = TMIN to TMAX BVREFH pin and BVREFL pin grounded TA = TMIN to TMAX VBVN = 0 V, VBVREFL = 0 V VBVMEA = 0 V −250 −2 −17 −40 −0.1 ±0.1 3 +250 +2 +17 +40 400 140 RL = 10 kΩ BVREFH pin and BVREFL pin connected BVREFL pin grounded BVREFH pin connected to VREF pin VBVMEA/VBVREFH AVEE + 1.5 AVEE + 1.5 ΔVCM = 10 V, RTO TA = TMIN to TMAX ΔVS = 10 V, RTO 90 11.0 4.4 AVCC − 1.2 AVCC − 1.5 12.5 5 40 14.0 5.6 0.05 114 ΔVBVMEA = 10 V Rev. 0 | Page 3 of 34 123 3.0 0.9 Unit V/V % ppm/°C µV µV/°C nA V GΩ GΩ V V µA mV mV/V mA dB µV/V/°C dB kHz V/µs V/V % ppm/°C µV µV/°C V kΩ kΩ V V mV mV/V mA dB µV/V/°C dB MHz V/µs AD8452 Parameter CC AND CV LOOP FILTER AMPLIFIERS Offset Voltage Offset Voltage Drift Input Bias Current Input Common-Mode Voltage Range Output Voltage Swing Source Short-Circuit Current Sink Short-Circuit Current PSRR Small Signal Gain Bandwidth Product Slew Rate CC to CV Transition Time VSET VOLTAGE BUFFER Nominal Gain Offset Voltage Offset Voltage Drift Input Bias Current Input/Output Voltage Range Short-Circuit Current PSRR Small Signal −3 dB Bandwidth Slew Rate VOLTAGE REFERENCE Nominal Output Voltage Output Voltage Error Temperature Drift Line Regulation Load Regulation Source Short-Circuit Current Data Sheet Test Conditions/Comments Min Typ TA = TMIN to TMAX −1 −5 AVEE + 1.5 AVEE + 1.5 +0.02 VVINT voltage range ΔVS = 10 V 113 ΔVVINT = 10 V Max Unit 150 1 +5 AVCC − 1.8 5 µV µV/°C nA V V mA mA dB MHz V/μs µs 1 40 122 3 1 1.8 1 TA = TMIN to TMAX −1 −5 AVEE + 1.5 ΔVS = 10 V 113 +0.06 ΔVVSETBF = 10 V 40 122 4 1 With respect to AGND 2.5 ±1 16 10 300 TA = TMIN to TMAX ΔVS = 10 V ΔIVREF = 1 mA (source only) 15 Rev. 0 | Page 4 of 34 150 +1 +5 AVCC − 1.8 V/V µV µV/°C nA V mA dB MHz V/μs V % ppm/°C ppm/V ppm/mA mA Data Sheet AD8452 PULSE-WIDTH MODULATOR SPECIFICATIONS Table 2. Parameter SOFT START (SS) SS Pin Current SS Threshold Rising SS Threshold Falling End of Soft Start PWM CONTROL Frequency Frequency Range Oscillator Frequency FREQ Pin Voltage SYNC Output (Internal Frequency Control) Internal SYNC Range SYNC Output Clock Duty Cycle SYNC Sink Pull Down Resistance SYNC Input (External Frequency Control) External SYNC Range SYNC Internal Pull-Down Resistor Maximum SYNC Pin Voltage SYNC Threshold Rising SYNC Threshold Falling SCFG SCFG High Threshold Rising Falling SCFG Low Threshold Rising Falling SCFG Pin Current DMAX Maximum Internal Duty Cycle DMAX Setting Current DMAX and SCFG Current Matching 1 DT DT Pin Current Maximum DT Programming Voltage CURRENT LIMIT (CL) CLVT CLVT Pin Current CLP, CLN Common-Mode Range Input Resistance Current Limit Threshold Offset CLFLG Max CLFLG Voltage CFLG Pull-Down Resistance Current Limit Overload Time Cool Down Time Test Conditions/Comments Min Typ Max Unit VSS = 0 V Switching enable threshold Switching disable threshold Asynchronous to synchronous threshold 4 6 0.65 0.4 4.4 5 0.52 0.5 4.5 4.6 µA V V V RFREQ = 33.2 kΩ to 200 kΩ RFREQ = 100 kΩ RFREQ = 100 kΩ VSCFG ≥ 4.53 V or SCFG pin floating 50 90 1.1 100 1.255 300 110 1.4 kHz kHz V For SYNC output VSCFG = VVREG, RFREQ = 100 kΩ VSCFG = 5 V, ISYNC = 10 mA VSCFG < 4.25 V For SYNC input clock 50 40 50 10 300 60 20 kHz % Ω 300 1.5 kHz MΩ V V V 50 0.5 0.7 1 5 1.2 1.05 SYNC set to input SYNC set to output 4.53 4.47 4.7 4.25 V V Programmable phase shift above threshold No phase shift RFREQ = 100 kΩ, VSCFG = DGND 0.55 0.5 11 0.65 0.4 10 12 V V µA VDMAX, VSS, and VSCFG = 5 V VDMAX = 0 V, RFREQ = 100 kΩ 10 97 11 12 10 % µA % 20 24 3.5 µA V 21 27 µA 8 36 V kΩ mV 5.5 8 V Ω 160 160 μs μs For external sync operation RFREQ = 100 kΩ, VDT = DGND See Figure 28 Minimum CLVT pin voltage = 50 mV 16 VCLP = VCLN 0 24 VCLP = VCLN, RCLVT = 2.49 kΩ Open-drain, active low output Open-drain output 30 50 1.5 RFREQ = 100 kΩ, 16 consecutive clock pulses Rev. 0 | Page 5 of 34 AD8452 Parameter ZERO CROSSING DETECTION (ZCD) ZCD Threshold Offset VREG Low Dropout (LDO) Regulator Output Voltage Load Regulation PWM DRIVE LOGIC SIGNALS (DH/DL) DL Drive Voltage DH Drive Voltage DL and DH Sink Resistance DL and DH Source Resistance DL and DH Pull-Down Resistor THERMAL SHUTDOWN (TSD) TSD Threshold Rising Falling 1 Data Sheet Test Conditions/Comments Min Typ Max 0 (VCLP + VCLN)/2, for common-mode voltage (CMV) = 0 V to 8 V Unit mV VIN = 6 V to 60 V, no external load 4.9 5 5.1 V VIN = 6 V, IOUT = 0 mA to 5 mA 4.9 5 5.1 V 0.5 VREG VREG 1.4 1.4 1 2.6 2.6 1.5 V V Ω Ω MΩ No load No load IDL = 10 mA IDL = 10 mA 150 125 °C °C The DMAX and SCFG current matching specification is calculated by taking the absolute value of the difference between the measured ISCFG and IDMAX currents, dividing them by the 11 µA typical value, and multiplying this result by 100. DMAX and SCFG current matching (%) = (ISCFG – IDMAX/11 µA) × 100 DIGITAL INTERFACE SPECIFICATIONS Table 3. Parameter DIGITAL INTERFACE, MODE INPUT MODE Threshold Rising MODE Threshold Falling MODE Switching Time PRECISION ENABLE LOGIC (EN) Maximum EN Pin Voltage EN Threshold Rising EN Threshold Falling EN Pin Current FAULT Maximum FAULT Pin Voltage FAULT Threshold Rising FAULT Threshold Falling FAULT Pin Current Test Conditions/Comments MODE pin Min Typ Max Unit 1.2 1.0 400 1.4 0.7 V V ns 60 1.4 1.1 1.26 1.2 0.25 V V V µA VEN = 5 V, internal pull-down Active low input 0.7 VFAULT = 5 V, internal 8.5 MΩ pulldown resistor Rev. 0 | Page 6 of 34 1.2 1.0 0.5 2 60 1.5 2 V V V µA Data Sheet AD8452 POWER SUPPLY Table 4. Parameter ANALOG POWER SUPPLY Operating Voltage Range AVCC AVEE Analog Supply Range Quiescent Current AVCC AVEE PWM POWER SUPPLY (VIN) VIN Voltage Range VIN Supply Current UVLO Threshold Rising UVLO Threshold Falling Test Conditions/Comments Min AVCC − AVEE 10 −26 10 Typ Max Unit 36 0 36 V V V 4.7 4.4 6.5 6.0 mA mA 2.2 60 3.0 V mA 6 V V 6 RFREQ = 100 kΩ, VSS = 0 V, SYNC = open circuit (OC), FAULT = low, EN = high VIN rising VIN falling 5.1 5.75 5.34 TEMPERATURE RANGE SPECIFICATIONS Table 5. Parameter TEMPERATURE RANGE For Specified Performance Operational Min −40 −55 Rev. 0 | Page 7 of 34 Typ Max Unit +85 +125 °C °C AD8452 Data Sheet ABSOLUTE MAXIMUM RATINGS Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 6. Parameter Analog Supply Voltage (AVCC − AVEE) PWM Supply Voltage (VIN – DGND) Internal Regulator Voltage (VREG − DGND) Voltage Input Pins (ISVP, ISVN, BVP, and BVN) Analog Controller and Front-End Pins (ISREFH, ISREFL, BVREFL, BVREFH, VREF, VSET, VVP0, BVMEA, VVE0, VVE1, VINT, IVE0, IVE1, ISMEA, ISET) PWM Pins SYNC, MODE DH, DL, SS, DMAX, SCFG, DT, FREQ, CLVT Current Limit Sense Pins (CLP, CLN) FAULT Pin and EN Pin Maximum Digital Supply Voltage Positive Analog Supply (VREG − AVCC) Negative Analog Supply (VREG − AVEE) Maximum Digital Ground Positive Analog Supply (DGND − AVCC) Negative Analog Supply (DGND − AVEE) Maximum Analog Ground Positive Analog Supply (AGND − AVCC) Negative Analog Supply (AGND − AVEE) Analog Ground with Respect to the Digital Ground (AGND − DGND) Maximum Minimum Storage Temperature Range Rating 36 V −0.3 V to +61 V 5.5 V AVEE + 40 V AVCC − 40 V THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. −0.3 V to +5.5 V −0.3 V to VREG + 0.3 V −0.3 V to +61 V −0.3 V to +61 V Table 7. Thermal Resistance Package Type ST-481 1 2 0.3 V −0.3 V θJA2 81 Unit °C/W Dissipation ≤ 0.3, TA = 25°C. θJA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. ESD CAUTION 0.3 V −0.3 V 0.3 V −0.3 V 0.3 V −0.3 V −65°C to +150°C Rev. 0 | Page 8 of 34 Data Sheet AD8452 CLVT CLP CLN AVCC VINT IVE1 IVE0 ISMEA ISET AVCC AGND VREF PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 ISREFH 1 36 FREQ ISREFL 2 35 DMAX ISREFLS 3 34 SS ISVP 4 33 DT 32 DGND ISVN 5 AD8452 BVP 6 31 DH TOP VIEW (Not to Scale) BVPS 7 30 DL 29 VIN BVN 8 28 VREG BVNS 9 27 SCFG BVREFL 10 26 SYNC BVREFLS 11 25 CLFLG BVREFH 12 16187-002 FAULT EN MODE AVEE VINT VVE1 VVE0 VSETB BVMEA VVP0 VSET AVEE 13 14 15 16 17 18 19 20 21 22 23 24 Figure 2. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 Mnemonic ISREFH Type 1 Input 2 3 4 ISREFL ISREFLS ISVP Input Test Input 5 ISVN Input 6 7 8 9 10 BVP BVPS BVN BVNS BVREFL Input Test Input Test Input 11 12 BVREFLS BVREFH Test Input 13, 21 14 15 16 17 18 19 20, 41 22 AVEE VSET VVP0 BVMEA VSETB VVE0 VVE1 VINT MODE N/A Input Input Output Output Input Input Output Logic input 23 EN Logic input 24 FAULT Logic input Description Reference Input for the Current Sense Amplifier. Connect this pin to the VREF pin to shift the current-sense instrumentation amplifier output by 12.5 mV. Otherwise, connect this pin to the ISREFL pin. Reference Input for the Current Sense Amplifier. The default connection is to ground. Kelvin Sense Pin for the ISREFL Pin. Current Sense Instrumentation Amplifier Positive (Noninverting) Input. Connect this pin to the high side of the current sense shunt. Current Sense Instrumentation Amplifier Negative (Inverting) Inputs. Connect this pin to the low side of the current sense shunt. Battery Voltage Difference Amplifier Positive (Noninverting) Input. Kelvin Sense Pin for the Battery Voltage Difference Amplifier Input, BVP. Battery Voltage Difference Amplifier Negative (Inverting) Input. Kelvin Sense Pin for the Battery Voltage Difference Amplifier Input, BVN. Reference Input for the Voltage Sense Difference Amplifier. The default connection for this pin is to ground. Kelvin Sense Pin for the BVREFL Pin. Reference Input for the Difference Amplifier. Connect to the VREF pin to level shift VBVMEA by approximately 12.5 mV. Otherwise, connect this pin to the BVREFL pin. Analog Negative Supply Pins. Scaled CV Loop Control Input for Battery Charge or Discharge Cycle. Noninverting CV Loop Filter Amplifier Input for Discharge Mode. Scaled Battery Voltage, Difference Amplifier Output. Buffered VSET Voltage. Inverting Input of the CV Loop Filter Amplifier When in Discharge Mode. Inverting Input of the CV Loop Filter Amplifier When in Charge Mode. Aggregated Result of the Battery Voltage and Current Sense Integration. Logic Level Input to Select between Charge and Discharge Modes. Bring this pin low for discharge mode, and bring this pin high for charge mode. Logic Level Enable Input. Drive EN logic low to shut down the device. Drive EN logic high to turn on the device. External Fault Comparator Connection. When not connected, this pin is pulled up using a 10 kΩ resistor to the VREG pin. The DH and DL drivers are disabled when FAULT is low, and are enabled when FAULT is high. Rev. 0 | Page 9 of 34 AD8452 Data Sheet Pin No. 25 Mnemonic CLFLG Type 1 Output 26 SYNC 27 SCFG 28 VREG Input/ output Input/ output Output 29 30 VIN DL Input Output 31 32 33 DH DGND DT Output N/A Output 34 SS Output 35 DMAX Input 36 FREQ N/A 37 CLVT Input 38 39 40, 46 42 43 44 45 CLP CLN AVCC IVE1 IVE0 ISMEA ISET Input Input N/A Input Input Output Input 47 48 AGND VREF N/A Output 1 Description Current-Limit Flag. CLFLG goes low and stays low when the AD8452 is in current limit mode. Connect a 10 kΩ (minimum) resistor to the VREG pin. C lock Synchronization Pin. Synchronizes the clock (switching frequency) when multiple channels are phase interleaved. Connect a 10 kΩ (minimum) resistor to the VREG pin. Synchronization Configuration Pin. See Table 10. Internal LDO 5 V Regulator Output and Internal Bias Supply. Connect a bypass capacitor of 1 µF or greater from this pin to ground. Supply Voltage to the PWM Section. VIN is typically the same as the output switch supply voltage. Logic Drive Output for the External Low-Side Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) Driver. Logic Drive Output for the External High-Side MOSFET Driver. Digital and PWM Ground. Dead Time Programming Pin. Connect an external resistor between this pin and ground to set the dead time. Do not leave this pin floating. Soft Start Control Pin. A capacitor connected from the SS pin to ground sets the soft start ramp time. See the Selecting CSS section. Maximum Duty Cycle Input. Connect an external resistor to ground to set the maximum duty cycle. If the 97% internal maximum duty cycle is sufficient for the application, tie this pin to VREG. If DMAX is left floating, this pin is internally pulled up to VREG. Frequency Set Pin. Connect an external resistor between this pin and ground to set the frequency between 50 kHz and 300 kHz. When the AD8452 is synchronized to an external clock (slave mode), set the slave frequency to 90% of the master frequency by multiplying the master RFREQ value by 1.11. Current-Limit Voltage Threshold. With user selected resistor value, CLVT establishes a threshold voltage for the current limit comparator. See the Select RCL and RCLVT for the Peak Current Limit section. Current-Limit/Diode Emulation Amplifier Positive Sense Pin. Current-Limit/Diode Emulation Amplifier Negative Sense Pin. Analog Positive Supply Pins. Inverting Input of the CC Loop Filter Amplifier When in Charge Mode. Inverting Input of the CC Loop Filter Amplifier When in Discharge Mode. Current Sense Instrumentation Amplifier Output. Scaled CC Voltage Loop Control Input for Battery Charge or Discharge Cycles. ISET is typically the same for charge and discharge cycle. Analog Ground. 2.5 V Reference. Bypass this pin with a high quality 10 nF NP0 ceramic capacitor in series with a 10 Ω (maximum) resistor. N/A means not applicable. Rev. 0 | Page 10 of 34 Data Sheet AD8452 TYPICAL PERFORMANCE CHARACTERISTICS AVCC = 15 V, AVEE = −15 V, VIN = 24 V, TA = 25°C, and RL = ∞, unless otherwise noted. –60 40 –70 20 –80 0 –90 –20 –40 –100 –110 –60 –120 –80 –130 –100 −40 −30 −20 −10 0 10 20 30 40 50 60 80 70 90 TEMPERATURE (°C) –140 10 100 1k 100k 10k FREQUENCY (Hz) 16187-006 CMRR (dB) 60 16187-003 GAIN ERROR (ppm) IN-AMP CHARACTERISTICS Figure 6. CMRR vs. Frequency Figure 3. Gain Error vs. Temperature –50 17.0 –60 –70 16.5 –80 16.0 –90 PSRR (dB) INPUT BIAS CURRENT (nA) +PSRR –PSRR 15.5 –100 –110 –120 15.0 –130 –140 14.5 −5 0 5 10 15 INPUT COMMON-MODE VOLTAGE (V) –160 10 100 10k 100k Figure 7. PSRR vs. Frequency Figure 4. Input Bias Current vs. Input Common-Mode Voltage 19 1k FREQUENCY (Hz) 16187-007 −10 16187-004 –150 14.0 −15 40 ISVP ISVN 30 GAIN (dB) 17 16 15 14 20 10 12 –40 –30 –20 –10 0 10 20 30 40 50 60 70 TEMPERATURE (°C) 80 90 0 100 1k 10k 100k FREQUENCY (Hz) Figure 8. Gain vs. Frequency Figure 5. Input Bias Current vs. Temperature Rev. 0 | Page 11 of 34 1M 10M 16187-008 13 16187-005 INPUT BIAS CURRENT (nA) 18 AD8452 Data Sheet DIFFERENCE AMPLIFIER CHARACTERISTICS –120 –10 ISVP ISVN –20 –140 +PSRR –PSRR –30 –50 PSRR (dB) GAIN ERROR (ppm) –40 –160 –180 –200 –60 –70 –80 90 –100 –220 –110 –240 –120 –260 –40 –30 –20 –10 –140 10 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) 100 1k 10k 100k FREQUENCY (Hz) Figure 9. Gain Error vs. Temperature 16187-011 0 16187-009 –130 Figure 11. PSRR vs. Frequency –50 0 –60 –10 GAIN (dB) –80 –90 –100 –110 –20 –30 –130 10 100 1k 10k FREQUENCY (Hz) 100k –40 100 1k 10k 100k FREQUENCY (Hz) Figure 10. CMRR vs. Frequency Figure 12. Gain vs. Frequency Rev. 0 | Page 12 of 34 1M 10M 16187-012 –120 16187-010 CMRR (dB) –70 Data Sheet AD8452 400 100 200 INPUT BIAS CURRENT (pA) 150 50 0 –50 –200 –400 –600 –10 –5 0 5 10 15 INPUT COMMON-MODE VOLTAGE (V) –1000 –15 –10 –5 0 5 10 INPUT COMMON-MODE VOLTAGE (V) 15 Figure 15. Input Bias Current vs. Input Common-Mode Voltage 0.30 1.7 0.25 1.6 OUTPUT SOURCE CURRENT (mA) Figure 13. Input Offset Voltage vs. Input Common-Mode Voltage 0.20 0.15 0.10 0.05 0 16187-015 –800 16187-013 1.5 1.4 1.3 1.2 1.1 –0.05 –40 –30 –20 –10 0 10 20 30 40 50 60 70 TEMPERATURE (°C) 80 90 Figure 14. Input Bias Current vs. Temperature 1.0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) Figure 16. Output Source Current vs. Temperature Rev. 0 | Page 13 of 34 90 16187-016 –150 –15 INPUT BIAS CURRENT (nA) 0 –100 16187-014 INPUT OFFSET VOLTAGE (µV) CC AND CV LOOP FILTER AMPLIFIERS AND VSET BUFFER (EXCEPT WHERE NOTED) AD8452 Data Sheet 1.5 –20 –30 ISET (V) VINT (V) +PSRR –PSRR –40 1.0 OUTPUT VOLTAGE (V) –50 PSRR (dB) –60 –70 –80 –90 –100 –110 0.5 0 –0.5 –120 –1.0 –130 100 1k 10k 100k FREQUENCY (Hz) –1.5 16187-017 –150 10 0 –45.0 –67.5 100 –90.0 –112.5 60 GAIN 40 –135.0 20 –157.5 0 –180.0 –20 –202.5 10k 100k 1M –225.0 10M FREQUENCY (Hz) 16187-018 80 PHASE (Degrees) OPEN LOOP GAIN (dB) PHASE 1k 15 20 25 30 35 Figure 19. CC to CV Transition 120 100 10 TIME (µs) Figure 17. PSRR vs. Frequency –40 10 5 Figure 18. Open-Loop Gain and Phase vs. Frequency for CC and CV Loop Amplifiers Rev. 0 | Page 14 of 34 40 45 50 16187-019 –140 Data Sheet AD8452 REFERENCE CHARACTERISTICS 2.498 300 2.496 2.494 2.492 2.490 0 1 2 3 4 5 6 7 8 9 10 OUTPUT CURRENT—SOURCING (mA) 250 200 150 100 –55 16187-020 OUTPUT VOLTAGE (V) 2.500 –35 –15 5 25 45 65 85 105 TEMPERATURE (°C) Figure 20. Sourcing Regulation for Three Values of Temperature Figure 21. Source Load Regulation vs. Temperature Rev. 0 | Page 15 of 34 125 16187-021 SOURCE LOAD REGULATION (ppm/mA) T = +85°C T = +25°C T = –40°C AD8452 Data Sheet PULSE-WIDTH MODULATOR 5.10 VIN = 6V VIN = 24V VIN = 60V 5.08 SS PIN CURRENT (µA) EN 1 5.06 5.04 C SS = 0.1µF MODE = 0V 5.02 5.00 SS 2 4.98 4.96 DH 3 4.94 DL 4.90 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) 16187-022 4 CH1 5.00V 1MΩ BW 20.0M CH2 5.00V 1MΩ CH3 5.00V 1MΩ BW 20.0M CH4 5.00V 1MΩ B W B W 2.3V 20.0M CH1 20.0M 20ms/DIV 16187-025 4.92 Figure 25. Shows Reversal of DH Pin and DL Pin Timing at Startup (0 V to 5 V at EN Pin) When AD8452 Is in Discharge Mode Figure 22. SS Pin Current vs. Temperature 210 1 190 EN 170 RFREQ (MASTER) (kΩ) SYNC 2 DH 150 130 110 90 70 DL 4 B B W W 20.0M 20.0M CH1 3.1V 20µs/DIV 30 50 100 150 200 250 300 fSET (kHz) Figure 23. Timing, Referred to Startup (0 V to 5 V at EN Pin), As Observed at Three Logic Output Pins When AD8452 Is in Charge Mode 16187-026 CH1 5.00V 1MΩ BW 20.0M CH2 5.00V 1MΩ CH3 5.00V 1MΩ BW 20.0M CH4 5.00V 1MΩ 16187-023 50 Figure 26. RFREQ (MASTER) vs. Switching Frequency (fSET) 500 450 1 EN 400 350 RSCFG (kΩ) 2 CSS = 0.1µF MODE = 5V SS DH 300 250 200 150 3 100 DL B W B W 20.0M CH1 2.3V 20.0M 20ms/DIV 0 16187-024 CH1 5.00V 1MΩ BW 20.0M CH2 2.00V 1MΩ CH3 5.00V 1MΩ BW 20.0M CH4 5.00V 1MΩ 0 1.5 3.0 4.5 6.0 7.5 PHASE DELAY (µs) Figure 24. Soft Start Ramp Timing at SS Pin, Referred to Startup (0 V to 5 V at the EN Pin) As Observed at Logic Level Outputs, DH and DL, When AD8452 Is in Charge Mode Rev. 0 | Page 16 of 34 Figure 27. RSCFG (Calculated) vs. Phase Time Delay (tDELAY) 9.0 16187-027 50 4 Data Sheet AD8452 175 2.30 150 QUIESCENT CURRENT (mA) 100 75 50 25 2.15 2.10 2.05 100 200 300 400 DEAD TIME (ns) 500 600 700 1.95 16187-028 0 6 5.9 VIN UVLO THRESHOLD (V) 4.994 4.992 4.990 4.988 15 24 33 42 51 16187-029 6 60 INPUT VOLTAGE (V) Figure 29. VREG vs. Input Voltage (VIN) at Various Temperatures and No Load 1.25 51 60 UVLO THRESHOLD RISING UVLO THRESHOLD FALLING 5.7 5.6 5.5 5.4 5.3 4.986 1.26 42 5.8 4.996 4.984 33 Figure 31. Quiescent Current vs. Input Voltage (VIN) at Various Temperatures, EN Pin Low T = −40°C T = +25°C T = +85°C 4.998 24 INPUT VOLTAGE (V) Figure 28. DT Pin Resistance (RDT) vs. Dead Time (tDEAD) 5.000 15 16187-031 2.00 0 VREG (V) 2.20 VEN RISING VEN FALLING 1.24 1.23 1.22 1.21 1.20 1.18 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) 90 16187-030 1.19 Figure 30. EN Pin Threshold Voltage (VEN) vs. Temperature Rev. 0 | Page 17 of 34 5.2 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) Figure 32. Input Voltage (VIN) UVLO Threshold vs. Temperature 16187-032 RDT (kΩ) 125 VEN (V) T = −40°C T = +25°C T = +85°C 2.25 AD8452 Data Sheet THEORY OF OPERATION of current into or out of the battery until the voltage reaches a target value. At this point, a set constant voltage is applied across the battery terminals, reducing the charge current until reaching zero. INTRODUCTION Lithium ion (Li-Ion) batteries require an elaborate and time consuming postproduction process known as forming. Battery formation consists of a series of charge/discharge cycles that require precise current and voltage control and monitoring. The AD8452 provides not only the stringent current and voltage accuracy requirements, but also a highly accurate PWM, with logic level DH and DL outputs ready for a half-H bridge configured switch mode power output converter—all in a highly compact 7 mm × 7 mm package. The AD8452 features a complete PWM including on-board user adjustable features such as clock frequency, duty cycle, clock phasing, current limiting, soft start timing, and multichannel synchronization. Figure 33 is the block diagram of the AD8452, illustrating the distinct sections of the AD8452, including the in-amp and difference amplifier measurement blocks, loop filter amplifiers, and PWM. The analog front end of the AD8452 includes a precision current sense in-amp with gain of 66× ±0.1% and a precision voltage sense difference amplifier with a gain of 0.4 × ±0.1% for battery voltage. 45 44 43 D 42 ISREFLS ISVP ISVN BVP BVPS BVN BVNS 39 1MΩ CL C 500Ω BATTERY CURRENT SENSE IA G = 66 3 MODE_B 5 CURRENT LIMIT AND DIODE EMULATION CONFIG DETECT CC LOOP FILTER AMPLIFIER AVEE 200kΩ 7 8 DMAX VCTRL COMP 9 SS SCFG VREG = 5V SYNC VBG = 1.252V 21 Figure 33. AD8452 Detailed Block Diagram Rev. 0 | Page 18 of 34 CLFLG 8.5MΩ 0.3µA 22 MODE 20 AVEE 19 VINT 18 29 28 VREG TSD BAND GAP C VVE1 D 30 UVLO MODE_B VVE0 17 VSETB 16 VSET BUFFER 15 BVMEA 14 VVP0 13 1MΩ 1MΩ MODE_B 1× 34 31 SS DISCHARGE D 35 32 1.64pF DRIVE LOGIC AVEE 12 60kΩ VSET BVREFH C AVEE BVREFLS 11 36 33 4V CL MODE_B 300Ω SS 20µA 10µA 5µA 10 DMAX 1× CV LOOP FILTER AMPLIFIER 80kΩ 200kΩ ISCFG 11µA SCFG IDMAX 11µA AVCC SOFT START AMPLIFIER BATTERY VOLTAGE SENSE DA SS G = 0.4 AVEE 6 VFREQ = 1.252V VREG 1.1mA +/– CLFLG 20µA 79.7kΩ BVREFL 37 OSCILLATOR 2 4 38 SYNC DETECT 100kΩ 1 CLP CLN VINT AVCC SYNC 40 23 EN ISREFL 41 AVCC MODE' ISREFH IVE1 IVE0 ISMEA ISET AVCC 46 AVCC 27 26 25 FREQ DMAX SS DT DGND DH DL VIN VREG SCFG SYNC CLFLG 24 16187-033 47 FAULT 48 2.5V VREF AGND VREF As shown in Figure 38, the AD8452 provides constant CC/CV charging technologies, with transparent internal switching between the two. Typical systems induce predetermined levels CLVT Figure 34 is a block diagram of the AD8452 integrated within a battery formation and test system. The AD8452 is usable over a wide range of current and voltage applications simply by judicious selection of a current sense shunt, selected according to system requirements. Data Sheet SET BATTERY CURRENT AD8452 1.1mA CONSTANT CURRENT LOOP FILTER AMPLIFIER ISET SELECT IBAT POLARITY C VINT BUFFER MODE SWITCHES (3) C D AVEE BUCK BOOST PWM DC TO DC POWER CONVERSION AD8452 CONTROLLER C VINT VVE1 VSETB VVP0 VSET SET BATTERY VOLTAGE IVE1 IVE0 1× VVE0 D VCTRL 1× CONSTANT VOLTAGE LOOP FILTER AMPLIFIER D VREG C = CHARGE D = DISCHARGE CURRENT LIMIT AND DIODE EMULATION CLP CLN ISVP IN-AMP ISVN CURRENT SENSE SHUNT DISCHARGE COMPENSATION MATRIX BATTERY CURRENT (IBAT) ISMEA CHARGE BVP BVMEA BATTERY DIFF AMP 16187-034 BVN Figure 34. Signal Path of a Li-Ion Battery Formation and Test System Using the AD8452 INSTRUMENTATION AMPLIFIER (IN-AMP) Reversing Polarity When Charging and Discharging Figure 35 is a block diagram of the AD8452 in-amp used to monitor battery current when connected to a low ohmic value shunt. The architecture of the in-amp is the classic 3-op-amp topology, similar to the Analog Devices, Inc., industry-standard AD8221 or AD620, and is configured for a fixed gain of 66 V/V. This architecture, combined with ADI exclusive precision laser trimming, provides the highest achievable CMRR and optimizes error free (gain error better than 0.1%) high-side battery current sensing. For more information about instrumentation amplifiers, see A Designer's Guide to Instrumentation Amplifiers. Figure 34 shows that during the charge cycle, the power converter drives current into the battery, generating a positive voltage across the current sense shunt. During the discharge cycle, however, the power converter drains current from the battery, generating a negative voltage across the shunt resistor. In other words, the battery current reverses polarity when the battery discharges. When in the constant current discharge mode control loop, this reversal of the in-amp output voltage drives the integrator to the negative rail unless the polarity of the target current is reversed. To solve this problem, the AD8452 in-amp includes a double pole, double throw switch preceding its inputs that implements an input polarity inversion, thus correcting the sign of the output voltage (see Figure 33). This multiplexer is controlled via the MODE pin. When the MODE pin is logic high (charge mode), the in-amp gain is noninverting, and when the MODE pin is logic low (discharge mode), the in-amp gain is inverting. The polarity control of the current sense voltage to the input of the in-amp enables the integrator output voltage (VINT) to always swing positive, regardless of the polarity of the battery current. OPTIONAL CONNECTION FOR VOS OF 12.5mV 2.5V VREF +/– 10kΩ 19.5kΩ 10kΩ CHARGE/ DISCHARGE POLARITY INVERTER ISREFL G=2 SUBTRACTOR 10kΩ – CURRENT SHUNT ISREFH 500Ω ISMEA 305Ω 10kΩ ISVN 100kΩ 20kΩ +/– INSTRUMENTATION AMPLIFIER G = 66 16187-035 + CURRENT SHUNT ISVP Figure 35. Simplified Block Diagram of the Precision 3-Op-Amp In-Amp Rev. 0 | Page 19 of 34 AD8452 Data Sheet In-Amp Offset Option The resistors that form the difference amplifier gain network are laser trimmed to a matching level better than ±0.1%. This level of matching minimizes the gain error and gain error drift of the difference amplifier while maximizing the CMRR of the difference amplifier. This matching also allows the controller to set a stable target voltage for the battery over temperature while rejecting the ground bounce in the battery negative terminal. As shown in Figure 35, the in-amp reference node is connected to the ISREFL pin and ISREFH pin via an internal resistor divider. This resistor divider can be used to introduce a temperature insensitive offset to the output of the in-amp such that it always reads a voltage higher than zero for a zero differential input. Because the output voltage of the in-amp is always positive, a unipolar analog-to-digital converter (ADC) can digitize it. Like the in-amp, the difference amplifier can also level shift its output voltage via an internal resistor divider that is tied to the difference amplifier reference node. This resistor divider is connected to the BVREFH pin and BVREFL pin. When the ISREFH pin is tied to the VREF pin with the ISREFL pin grounded, the voltage at the ISMEA pin is increased by an offset voltage, VOS, of 12.5 mV, guaranteeing that the output of the in-amp is always positive for zero differential inputs. Other voltage shifts can be realized by tying the ISREFH pin to an external voltage source. The gain from the ISREFH pin to the ISMEA pin is 5 mV/V. For zero offset, connect the ISREFL pin and ISREFH pin to ground. When the BVREFH pin is tied to the VREF pin with the BVREFL pin grounded, the voltage at the BVMEA pin is increased by 12.5 mV, guaranteeing that the output of the difference amplifier is always positive for zero differential inputs. Other voltage offsets are realized by tying the BVREFH pin to an external voltage source. The gain from the BVREFH pin to the BVMEA pin is 5 mV/V. For zero offset, tie the BVREFL pin and the BVREFH pin to ground. Battery Reversal and Overvoltage Protection The AD8452 in-amp can be configured for high-side or low-side current sensing. If the in-amp is configured for high-side current sensing (see Figure 34) and the battery is connected backward, the in-amp inputs may be held at a voltage that is below the negative power rail (AVEE), depending on the battery voltage. CC AND CV LOOP FILTER AMPLIFIERS The CC and CV loop filter amplifiers are high precision, low noise specialty amplifiers with very low offset voltage and very low input bias current. These amplifiers serve two purposes: To prevent damage to the in-amp under these conditions, the in-amp inputs include overvoltage protection circuitry that allows them to be held at voltages of up to 55 V from the opposite power rail. In other words, the safe voltage span for the in-amp inputs extends from AVCC − 55 V to AVEE + 55 V. • • DIFFERENCE AMPLIFIER Figure 36 is a block diagram of the difference amplifier used to monitor the battery voltage. The architecture of the difference amplifier is a subtractor amplifier with a fixed gain of 0.4 V/V. This gain value allows the difference amplifier to funnel the voltage of a 5 V battery to a level that can be read by a 5 V ADC with a 4.096 V reference. Figure 37 is a functional block diagram of the AD8452 CC and CV feedback loops for charge mode (the MODE pin is logic high). For illustrative purposes, the external networks connected to the loop amplifiers are simple RC networks configured to form single-pole inverting integrators. This type of configuration exhibits very high dc precision when the feedback loop is closed, due to the high loop gain when the feedback loop is in place. The outputs of the CC and CV loop filter amplifiers are internally connected to the VINT pins via an analog NOR circuit (minimum output selector circuit), such that they can only pull the VINT node down. In other words, the loop amplifier that requires the lowest voltage at the VINT pins is in control of the node. Thus, only one loop, CC or CV, can be in control of the system charging control loop at any given time. When the loop is inactive (open, such as when the EN pin is low), the voltage at the VINT pins must be railed at AVCC. CONNECT FOR VOS OF 12.5mV AD8452 DIFFAMP + BATTERY TERMINAL BVP 200kΩ VREF 79.7kΩ 60kΩ 300Ω BVN 200kΩ 80kΩ BVREFH BVREFL BVMEA 16187-036 – BATTERY TERMINAL Using external components, the amplifiers implement active loop filters that set the dynamics (transfer function) of the CC and CV loops. The amplifiers perform a seamless transition from CC to CV mode after the battery reaches its target voltage. Figure 36. Difference Amplifier Simplified Block Diagram Rev. 0 | Page 20 of 34 Data Sheet AD8452 IAC HVAC/12V DC INVERTER/CONVERTER IBAT R1 ISET ISMEA + SHUNT RS CC LOOP AMPLIFIER IVE1 IA BVP MIN OUTPUT SELECT + VSET BUFFER BVN MODE VCTRL/ COMP + DA + 0.4× – BAT VINT – 66× – ISVN ½ BRIDGE AND LPF GH GL BVMEA ½ BRIDGE DRIVER DH PWM DL – 1× VSETB 5V CV LOOP AMPLIFIER VVE1 VSET DL DH VINT VVSET R2 16187-037 ISVP C1 VISET C2 Figure 37. Functional Block Diagram of the CC and CV Loops in Charge Mode (MODE Pin High) VISET G IA × RS where: IBAT is the steady state charging current. GIA is the in-amp gain. RS is the value of the shunt resistor. 1.25 5 1A CC CHARGE BEGINS TRANSITION FROM 1A CC TO 4.2V CV 1.00 BATTERY CURRENT (A) The target voltage is set at VBAT = Batteries can be charged in constant current or constant voltage modes. Figure 38 shows a typical CC/CV multiphase charge profile for a Li-Ion battery. In the first stage of the charging process, the battery is charged with a CC of 1 A. When the battery voltage reaches a target voltage of 4.2 V, the charging process transitions such that the battery is charged with a CV of 4.2 V. VVSET GDA where: VBAT is the steady state battery voltage. GDA is the difference amplifier gain. 4 VOLTAGE RISES TO VSET 0.75 3 VOLTAGE RISES TO VSET CHARGE TERMINATES 0.50 2 0.25 Because the offset voltage of the loop amplifiers is in series with the target voltage sources, VISET and VVSET, the high precision of these amplifiers minimizes this source of error. Li-Ion batteries also exhibit the highest energy density per unit of weight and volume than any other style. Such high levels of energy density make them the first choice for portable applications, large and small, from cell phones to high capacity energy storage banks. Realizing their greatest potential requires careful attention to their charge characterization signature. 1 CURRENT (A) VOLTAGE (V) 0 0 1 2 3 4 5 TIME (Hours) Charging Lithium-Ion (Li-Ion) Cells Charging Li-Ion cells is a demonstrably more difficult process than charging most other batteries employing recyclable technologies. The voltage margin of error between optimum storage capacity and damage caused by overcharge is around 1%. Thus, Li-Ion cells are more critical to over/undercharging than any other type battery style, rechargeable or not. BATTERY VOLTAGE (V) IBAT = Concepts of Constant Current (CC) and Constant Voltage (CV) 16187-038 The VISET voltage source and VVSET voltage source set the target constant current and the target constant voltage, respectively. When the CC and CV feedback loops are in a steady state, the charging current is set at Figure 38. Representative Li-Ion Battery Charge Profile Showing Seamless CC to CV Transition The following sequence of events describes how the AD8452 implements a typical CC/CV charging profile required for a Li-Ion battery. The scenario assumes a newly manufactured, unformed, never before charged battery, and the charge and discharge voltage and current levels along with appropriate time intervals have already been established empirically. Energy levels (CC, CV, and time intervals are just a small percent of the battery final ratings). For this example, assume a 3.2 V 10 Ah battery is charging at IBAT = 2 A and VBAT = 4.2 V. The process begins with ISET = 66 mV and VSET = 1.68 V, configured for charge mode. Following the target VSET and ISET, the system is enabled by applying a logic high to the EN pin. Rev. 0 | Page 21 of 34 AD8452 1. Data Sheet 7. At turn on, the default start-up voltages at the ISMEA pin and BVMEA pin are both zero, and both integrators (loop amplifiers) begin to ramp, increasing the voltage at the VINT node. (The voltage at the VINT pin always rises following an enable regardless of mode setting). As the voltage at the VINT node increases, the output current IBAT from the power converter starts to rise. When the IBAT current reaches the target CC steady state value IBAT, the battery voltage is considerably less than the target steady state value, VBAT. Therefore, the CV loop amplifier forces its output voltage high enough to disconnect itself from VINT. The CC loop prevails, maintaining the target charge current until the target VBAT is achieved and the CC loop stops integrating. Due to the analog OR circuit, the loop amplifiers can only pull the VINT node down. The CC loop takes control of the charging feedback loop, and the CV loop is disabled. As the charging process continues, the battery voltage increases until it reaches the steady state value, VBAT, and the voltage at the BVMEA pin reaches the target voltage, VVSET. The CV loop tries to pull the VINT node down to reduce the charging current (IBAT) and prevent the battery voltage from rising any further. At the same time, the CC loop tries to keep the VINT node at its current voltage to keep the battery current at IBAT. 2. 3. 4. 5. 6. Because the loop amplifiers can only pull the VINT node down due to the analog NOR circuit, the CV loop takes control of the charging feedback loop, and the CC loop is disabled. The analog OR (minimum output selector) circuit that couples the outputs of the loop amplifiers is optimized to minimize the transition time from CC to CV control. Any delay in the transition causes the CC loop to remain in control of the charge feedback loop after the battery voltage reaches its target value. Therefore, the battery voltage continues to rise beyond VBAT until the control loop transitions; that is, the battery voltage overshoots its target voltage. When the CV loop takes control of the charge feedback loop, it reduces the battery voltage to the target voltage. A large overshoot in the battery voltage due to transition delays can damage the battery; thus, it is crucial to minimize delays by implementing a fast CC to CV transition. Figure 39 is the functional block diagram of the AD8452 CC and CV feedback loops for discharge mode (MODE logic pin is low). In discharge mode, the feedback loops operate in a similar manner as in charge mode. The only difference is in the CV loop amplifier, which operates as a noninverting integrator in discharge mode. For illustration purposes, the external networks connected to the loop amplifiers are simple RC networks configured to form single-pole integrators. AC IAC INVERTER 12V DC IBAT R1 VISET HALF BRIDGE AND LPF GH ISMEA + SHUNT RS ISVN BVP + – IA BVN MIN OUTPUT SELECT + 5V DH PWM DL – 1× MODE HALF BRIDGE DRIVER DH DL + VSET BUFFER GL VINT – 66× – DA + 0.4× – BAT CC LOOP AMPLIFIER IVE0 BVMEA VSET VSETB VVSET VVP0 CV LOOP AMPLIFIER VVE0 VINT R2 R2 C2 Figure 39. Functional Block Diagram of the CC and CV Loops in Discharge Mode (MODE Pin Low) Rev. 0 | Page 22 of 34 16187-039 ISVP ISET Data Sheet AD8452 Compensation In battery formation and test systems, the CC and CV feedback loops have significantly different open-loop gain and crossover frequencies; therefore, each loop requires its own frequency compensation. The active filter architecture of the AD8452 CC and CV loops allows the frequency response of each loop to be set independently via external components. Moreover, due to the internal switches in the CC and CV amplifiers, the frequency response of the loops in charge mode does not affect the frequency response of the loops in discharge mode. Unlike simpler controllers that use passive networks to ground for frequency compensation, the AD8452 allows the use of feedback networks for its CC and CV loop filter amplifiers. These networks enable the implementation of both proportional differentiator (PD) Type II and proportional integrator differentiator (PID) Type III compensators. Note that in charge mode, both the CC and CV loops implement inverting compensators, whereas in discharge mode, the CC loop implements an inverting compensator, and the CV loop implements a noninverting compensator. As a result, the CV loop in discharge mode includes an additional amplifier, the VSET buffer, to buffer the VSET node from the feedback network VINT buffer. When the AD8452 operates in charge mode, the PWM operates in a buck configuration. In discharge mode, the configuration changes to boost. See Figure 40 and Figure 41 for the AD8452 DH and DL behavior in each mode. On the rising edge of EN, the state of the MODE pin is latched, preventing the mode of operation from being changed while the device is enabled. To change between charge and discharge modes of operation, shut down or disable the AD8452, adjust the MODE pin to change the operating mode, and reenable the system. The operating mode can be changed when the EN pin is driven low, the FAULT pin is driven low, or the AD8452 is disabled via a TSD event or UVLO condition. On the rising edge of the FAULT control signal, the state of the MODE pin is latched, preventing the mode of operation from being changed while the device is enabled. DH AND DL IN CHARGE MODE 4.5V 2.5V (TYP) INTERNAL RAMP (4V p-p) 0.5V 0V VREG (5V TYP) PIN DH 0V CHARGE AND DISCHARGE CONTROL Conditions to Charge and Discharge a Battery 16187-040 VREG (5V TYP) PIN DL 0V Battery charging and discharging requires separate paradigms in terms of the analog requirements and the PWM configurations. These paradigms are based on manufacturer provided information, most importantly the C rating where C is simply the battery capacity expressed in ampere hours. For example, if the battery is C rated as 10 Ah, and the charge rate is specified as 0.2 C, the charge current is 2 A for a duration of 5 hours. Multiple charge/discharge sequences can last for days at a time before the battery achieves its optimum storage capacity, and the charge/discharge currents and voltages must be accurately monitored. MODE Pin The MODE pin is a logic level input that selects charge with a logic high (VMODE > 2 V) or discharge with a logic low (VMODE < 0.8 V). All the analog and PWM circuitry for charging and discharging of the battery is configured and is latched in when the EN pin goes high. DH AND DL IN DISCHARGE MODE 4.5V INTERNAL RAMP (4V p-p) 2.5V (TYP) 0.5V 0V VREG (5V TYP) PIN DH 0V 16187-041 VREG (5V TYP) PIN DL 0V Figure 41. DH and DL Output Waveforms for Discharge Mode INPUT AND OUTPUT SUPPLY PINS The AD8452 has five power supply input pins, a pair each of the internally connected AVCC pin and AVEE pin for the analog section and Input VIN for the PWM section. The maximum supply voltage for the VIN pin is 60 V; if operating with an input voltage greater than 50 V, see Figure 42 for recommended additional input filtering. The MODE pin controls the polarity of the internal analog loop and the DH/DL sequence. In charge mode, DH precedes DL; in discharge mode, DL precedes DH. Rev. 0 | Page 23 of 34 AD8452 SUPPLY > 50V 4.7µF VIN R C 16187-042 To charge, the applied voltage must be greater than the voltage of the battery under charge and the current must not exceed the manufacturers specification, usually expressed as a fraction of the full C rating. When discharging, the opposite conditions apply; the discharge voltage must be less than the unloaded battery voltage, and the current flows out of the battery, reversing the polarity of the shunt voltage. Figure 40. DH and DL Output Waveforms for Charge Mode Figure 42. Recommended Filter Configuration for Input Voltages Greater Than 50 V AD8452 Data Sheet 5V For optimum protection from switching and other ambient noise, all of these supply pins must be bypassed to ground with high quality ceramic capacitors (X7R or better), located as near as possible to the device. DH DH BEGINS 5V DL VREG is an internal 5 V supply that powers the control circuitry including all the current sources for user selected PWM features. It is active as long as VIN is above the internal UVLO (5.75 V typical). VREG may be used as a pull-up voltage for the MODE, SYNC, DMAX, and FAULT pins and any other external pull-ups as long as the additional current does not exceed 5 mA. Bypass the VREG pin to ground with a 1 μF ceramic capacitor. DL FOLLOWS 5V 4.5V SYNCHRONOUS OPERATION ENABLED AT ~90% RAMP SS 0.52V 0V BEGIN RAMP SHUTDOWN The EN input turns the AD8452 PWM section on or off and can operate from voltages up to 60 V. When the EN voltage is less than 1.2 V (typical), the PWM shuts down, and DL and DH are driven low. When the PWM shuts down, the VIN supply current is 15 μA (typical). When the EN voltage is greater than 1.26 V (typical), the PWM is enabled. PWM SWITCHING ENABLED AT ~10% RAMP 16187-043 5V EN EN GOES HIGH 0V Figure 43. DH and DL Sequence in Charge Mode 5V DH In addition to the EN pin, the PWM is disabled via a fault condition flagged by an TSD, an undervoltage lockout (UVLO) condition on VIN, or an external fault condition via the FAULT pin. DL FOLLOWS 5V DL DH BEGINS When changing the operating mode, it is necessary to disable the AD8452 by setting the EN pin low. UNDERVOLTAGE LOCKOUT (UVLO) 5V 4.5V The UVLO function prevents the PWM from turning on until voltage VIN ≥ 5.75 V (typical). The UVLO enable state has ~410 mV of hysteresis to prevent the PWM from turning on and off repeatedly if the supply voltage to the VIN pin ramps slowly. The UVLO disables the PWM when VIN drops below 5.34 V (typical). SS 0.52V 0V BEGIN RAMP SYNCHRONOUS OPERATION ENABLED AT ~90% RAMP PWM SWITCHING ENABLED AT ~10% RAMP EN The AD8452 has a programmable soft start that prevents output voltage overshoot during startup. When the EN pin goes high, an internal 5 μA current source connected to the SS pin begins charging the external capacitor, CSS, that is connected to VREG (5 V), creating a linear voltage ramp (VSS) that controls several time sensitive PWM control functions. When VSS < 0.52 V (typical), the DH and DL logic outputs are both low. When VSS exceeds 0.52 V (typical), nonsynchronous switching is enabled, either the DH pin or the DL pin logic output become active, and the PWM duty cycle gradually increases. When VSS > 4.5 V (typical), synchronous switching is enabled (see Figure 43 and Figure 44). E N GO ES HIGH 0V 16187-044 5V SOFT START Figure 44. DH and DL Sequence in Discharge Mode In conjunction with the MODE pin, the VSS ramp also establishes when the DH and DL, logic outputs and thus the output FET switches, become active. In charge mode (Mode high), the pulse sequence at the DH pin precedes that at the DL pin. Conversely, in discharge mode, the sequence is reversed and the DL pin precedes the DH pin. The duty cycle of the DH and DL drive pins increase in proportion to the ramp level, reducing the output voltage overshoot during startup (see the Selecting CSS section). Rev. 0 | Page 24 of 34 Data Sheet AD8452 REPEATED CURRENT LIMIT VIOLATION DETECTED FOR UP TO 16 COUNTS NORMAL SOFT START SEQUENCE PIN DH AND PIN DL GO LOW FOR 16 COUNTS UPPER SWITCH GATE DRIVE (DH) IRCL CURRENT-LIMIT RESET COOL DOWN CURRENT LIMIT THRESHOLD (VCLVT ) PIN SS GOES LOW AND NORMAL SOFT START (SS) BEGINS t SOFT START (PIN SS) 0V 16187-046 CURRENT LIMIT FLAG (PIN CLFLG) 0V 5V Figure 45. Recovery from a Peak Current-Limit Event PWM DRIVE SIGNALS The AD8452 has two 5 V logic level output drive signals, DH and DL, that are compatible with MOSFET drivers such as the ADuM3223 or ADuM7223. The DH and DL drive signals synchronously turn on and off the high-side and low-side switches driven from the external driver. The AD8452 provides a resistor programmable dead time to prevent the DH pin and DL pin from transitioning at the same time, as shown in Figure 46. Connect a resistor from the DT pin to ground to program the dead time. DL tDEAD tDEAD 16187-045 DH Figure 46. Dead Time (tDEAD) Between DH and DL Transitions When driving capacitive loads with the DH and DL pins, a 20 Ω resistor must be placed in series with the capacitive load to reduce ground noise and ensure signal integrity. PEAK CURRENT PROTECTION AND DIODE EMULATION (SYNCHRONOUS) Peak Current-Limit Detection The AD8452 provides an adjustable peak current limit for fast response to overcurrent conditions. When the peak current limit is reached, the main switching FET is turned off, limiting the peak current for the switching cycle and the CLFLG pin is driven low. When the peak inductor current exceeds the programmed current limit for more than 16 consecutive clock cycles, a peak current overload condition occurs. If the current overload condition exists for less than 16 consecutive cycles, the counter is reset to zero and the peak current overload condition is avoided. During the peak current-limit condition, the SS capacitor is discharged to ground, and the drive signals (DL and DH) are disabled for the next 16 clock cycles to allow the FETs to cool down (current overload mode). When the 16 clock cycles expire, the AD8452 restarts with a new soft start cycle. Figure 45 shows the sequence for a peak current-limit event. As shown in Figure 47, the inductor current, IRCL ,is sensed by a low value resistor, RCL (for example, 5 mΩ), placed between the output inductor and capacitor. The IRCL current is bidirectional, depending on whether the AD8452 is in charge or discharge mode. The MODE pin automatically controls the polarity of the voltage sampled across RCL to set the peak current-limit detection. Because the average output voltage at the junction of the low-pass filter inductor and capacitor is equal to the battery potential, the common-mode voltage is rejected, leaving only the desired differential result. Rev. 0 | Page 25 of 34 AD8452 Data Sheet FREQUENCY AND PHASE CONTROL +DCBUS The FREQ, SYNC, and SCFG pins determine the source, frequency, and synchronization of the clock signal that operates the PWM control of the AD8452. IRCL RSH VBAT RCL Internal Frequency Control The AD8452 frequency can be programmed with an external resistor connected between FREQ and ground. The frequency range can be set from a minimum of 50 kHz to a maximum of 300 kHz. If the SCFG pin is tied to VREG, forcing VSCFG ≥ 4.53 V (typical), or if the SCFG pin is left floating, the SYNC pin is configured as an output, and the AD8452 operates at the frequency set by RFREQ, which outputs from the SYNC pin through the open-drain device. The output clock of the SYNC pin operates with a 50% (typical) duty cycle. In this configuration, the SYNC pin can synchronize other switching regulators in the system to the AD8452. When the SYNC pin is configured as an output, an external pull-up resistor is needed from the SYNC pin to an external supply. The VREG pin of the AD8452 can be used as the external supply rail for the pull-up resistor. VRCL CLP CLN PEAK CURRENT LIMITING AND DIODE EMULATION +– MODE VREG (CLP – CLN) CUR LIM VREG DH ICLVT = 20µA DUTY CYCLE DH SYNC OFF DL 1mV V DUTY CYCLE DL AD8452 VCLVT External Frequency Control 16187-047 CLVT RCLVT When VSCFG ≤ 0.5 V (typical), the SYNC pin is configured as an input, the AD8452 synchronizes to the external clock applied to the SYNC pin, and the AD8452 operates as a slave device. This synchronization allows the AD8452 to operate at the same switching frequency with the same phase as other switching regulators or devices in the system. When operating the AD8452 with an external clock, select RFREQ to provide a frequency that approximates but is not equal to the external clock frequency, which is further explained in the Applications Information section. Figure 47. Peak Current Limiting and Diode Emulation Block Diagram The threshold voltage for the peak current comparator is user adjustable by connecting a resistor from the current-limit voltage threshold (CLVT pin) to ground. The AD8452 generates this voltage from a 20 μA current source (see the Select RCL and RCLVT for the Peak Current Limit section). Diode Emulation/Synchronous Mode Operation The RCL current sense resistor is also used to detect and control current reversal. When the voltage across RCL drops to −5 mV ≤ VRCL ≤ +5 mV (for charge and discharge modes) during the synchronous FET switching cycle, the synchronous FET is turned off to stop the flow of reverse current. Operating Frequency Phase Shift When the voltage applied to the SCFG pin is 0.65 V < VSCFG < 4.25 V, the SYNC pin is configured as an input, and the AD8452 synchronizes to a phase shifted version of the external clock applied to the SYNC pin. To adjust the phase shift, place a resistor (RSCFG) from SCFG to ground. The phase shift can be used to reduce the input supply ripple for systems containing multiple switching power supplies. Information on how to set the current limit and the current sense resistor RCL is available in the Applications Information section. DH AND DL WITH INDUCTOR CURRENT WHILE IN CHARGE MODE MAXIMUM DUTY CYCLE DH Referring to Figure 52, the maximum duty cycle of the AD8452 can be externally programmed for any value between 0% and 97% by installing a resistor from the DMAX pin to ground. The maximum duty cycle defaults to 97% if the DMAX pin is left floating or connected to 5 V (the VREG pin). DL 2.5A 2.5A p-p 0A 16187-048 INDUCTOR CURRENT DIODE EMULATION BEGINS Figure 48. Diode Emulation in Charge Mode, Low Charge Current Required Rev. 0 | Page 26 of 34 Data Sheet AD8452 FAULT INPUT THERMAL SHUTDOWN (TSD) The AD8452 FAULT pin is a logic level input intended to be driven by an external fault detector. The external fault signal stops PWM operation of the system to avoid damage to the application and components. When a voltage of less than 1.0 V (typical) is applied to the FAULT pin, the AD8452 is disabled, driving the DL and DH PWM drive signals low. The soft start capacitor (CSS) is discharged through a switch until a voltage ≥1.2 V is applied to the FAULT pin, and the AD8452 resumes switching. The FAULT pin sustains voltages as high as 60 V. The AD8452 has a TSD protection circuit. The TSD triggers and disables switching when the junction temperature reaches 150°C (typical). While in TSD, the DL and DH signals are driven low, the CSS capacitor discharges to ground, and VREG remains high. Normal operation resumes when the junction temperature decreases to 135°C (typical). Rev. 0 | Page 27 of 34 AD8452 Data Sheet APPLICATIONS INFORMATION The AD8452 includes the following blocks (see Figure 33 and the Theory of Operation section for more information): ANALOG CONTROLLER This section describes how to use the AD8452 in the context of a battery formation and test system and includes design examples. • • FUNCTIONAL DESCRIPTION The AD8452 is a precision analog front end and controller for battery formation and test systems. Such systems are differentiated from typical battery charger or battery management systems by the high level of voltage and current measurement precision required to optimize Li-Ion batteries for capacity and energy density. Figure 49 shows the analog signal path of a simplified switching battery formation and test system using the AD8452 controller. • • • The AD8452 is suitable for systems that test and form Li-Ion and the legacy NiCad and NiMH electrolyte batteries. The output is a digital format (PWM), designed to drive a switching power output stage. • • A fixed gain in-amp that senses low-side or high-side battery current. A fixed gain difference amplifier that measures the terminal voltage of the battery. Two loop filter error amplifiers that receive the battery target current and voltage and establish the dynamics of the CC and CV feedback loops. A minimum output selector circuit that combines the outputs of the loop filter error amplifiers to perform automatic CC to CV switching. A PWM with high- and low-side half bridge logic level outputs suitable for driving a MOSFET gate driver. A 2.5 V reference whose output node is the VREF pin. A logic input pin (MODE) that switches the controller configuration between charge mode (high) and discharge mode (low). AVCC CONSTANT CURRENT LOOP FILTER AMPLIFIER 1.1mA SELECT IBAT POLARITY VCTRL 1× VINT BUFFER CONSTANT VOLTAGE LOOP FILTER AMPLIFIER C D MODE SWITCHES (3) C VVE0 VVP0 VSET D VSETB SET BATTERY VOLTAGE IVE1 IVE0 1× BUCK BOOST PWM LPF RCL LEVEL SHIFTER DC TO DC POWER CONVERSION AVEE C VVE1 D OUTPUT SWITCHES VREG VINT C = CHARGE D = DISCHARGE AD8452 CONTROLLER CURRENT LIMIT AND DIODE EMULATION ISVP ISVN C D CLP C D PGIA D CLN CURRENT SENSE SHUNT D ISMEA C BVP D COMPENSATION MATRIX C BVMEA BATTERY PGDA BVN D Figure 49. Complete Signal Path of a Battery Test or Formation System Suitable for Li-Ion Batteries Rev. 0 | Page 28 of 34 BATTERY CURRENT (IBAT) 16187-049 SET BATTERY CURRENT ISET Data Sheet AD8452 POWER SUPPLY CONNECTIONS Optional Low-Pass Filter The AD8452 requires three analog power supplies (AVCC, VIN, and AVEE). Two separate ground pins, AGND and DGND, provide options for isolating analog and digital ground paths in high noise environments. In most applications, however, these two pins can be connected to a common ground. Due to the extremely high impedance of the instrumentation amplifier used for a current shunt amplifier, power stage switching noise can become an issue if the input circuitry is in close proximity to the power stage components. This issue is mitigated by shielding the input leads with ground potential shielding designed into the PCB artwork and keeping the input leads close together between the current sense shunt and the input pins. The rated absolute maximum value for AVCC − AVEE is 36 V, and the minimum operating AVCC and AVEE voltages are +10 V and −26 V, respectively. Due to the high PSRR of the AD8452 analog circuitry, the AVCC pin can be connected directly to the high current power bus (the input voltage of the power converter) without risking injection of supply noise to the controller outputs. A commonly used power supply combination is +12 V for AVCC and −5 V for AVEE. The 12 V rail for AVCC provides enough headroom to the in-amp such that it can be connected in a high-side current sensing configuration. The −5 V AVEE rail allows the difference amplifier output to become negative if the battery under test (BUT) is accidentally connected in reverse. The condition can be detected by monitoring BVMEA for reverse voltage. It is good practice to connect decoupling capacitors to all the supply pins. A 1 µF ceramic capacitor in parallel with a 0.1 µF capacitor is recommended. CURRENT SENSE IN-AMP CONNECTIONS For a description of the instrumentation amplifier, see the Theory of Operation section, Figure 33, and Figure 35. The in-amp fixed gain is 66 V/V. Current Sensors Two common options for current sensors are isolated current sensing transducers and shunt resistors. Isolated current sensing transducers are galvanically isolated from the power converter and are affected less by the high frequency noise generated by switch mode power supplies. Shunt resistors are far less expensive, easier to deploy and generally more popular. If a shunt resistor sensor is used, a 4-terminal, low resistance shunt resistor is recommended. Two of the four terminals conduct the battery current, whereas the other two terminals conduct virtually no current. The terminals that conduct no current are sense terminals that are used to measure the voltage drop across the resistor (and, therefore, the current flowing through it) using an amplifier such as the in-amp of the AD8452. To interface the in-amp with the current sensor, connect the sense terminals of the sensor to the ISVP pin and ISVN pin of the AD8452 (see Figure 50). Connecting an external differential low-pass filter between the current sensor and the in-amp inputs is also an effective method to reduce the injection of switching noise into the in-amp (see Figure 50). ISVP 10kΩ IBAT 10kΩ 4-TERMINAL SHUNT 20kΩ IMEAS OPT LPF 305Ω BATTERY UNTER TEST 10kΩ – 10kΩ 20kΩ ISVN + Figure 50. 4-Terminal Shunt Resistor Connected to the Current Sense In-Amp VOLTAGE SENSE DIFFERENTIAL AMPLIFIER CONNECTIONS For a description of the difference amplifier, see the Theory of Operation section, Figure 33, and Figure 36. The gain of the difference amplifier is fixed at 0.4×. For AD8452 applications in large installations, the best practice is to connect each battery with a dedicated pair of conductors to avoid accuracy issues. This recommendation applies whether using wiring harnesses or a distributed PCB approach (mother/ daughter boards) to the system design. BATTERY CURRENT AND VOLTAGE CONTROL INPUTS (ISET AND VSET) The voltages at the ISET pin and the VSET pin set the target battery current and voltage (CC mode and CV mode) and require highly accurate and stable voltages to drive them. For a locally controlled system, a low noise LDO regulator such as the ADP7102ARDZ-5.0 is appropriate. For large scale computer controlled systems, a digital-to-analog converter (DAC) such as the dual channel, 16-bit AD5689RBRUZ is suitable for these purposes. In either event, the source output voltage and the in-amp and difference amplifier reference pins (ISREFH/ISREFL and BVREFH/BVREFL, respectively) must use the same ground reference. For example, if the in-amp reference pins are connected to AGND, the voltage source connected to ISET must also be referenced to AGND. In the same way, if the difference amplifier Rev. 0 | Page 29 of 34 16187-050 AVCC and AVEE power all the analog blocks, including the in-amp, difference amplifier, and op amps. VIN powers an internal 5 V LDO regulated supply (VREG) that powers the mode logic and PWM. AD8452 Data Sheet SELECTING CHARGE OR DISCHARGE OPTIONS reference pins are connected to AGND, the voltage source connected to VSET must also be referenced to AGND. In constant current mode, when the CC feedback loop is in a steady state, the ISET input sets the battery current as follows: IBAT = VISET VISET = G IA × RS 66 × RS where: GIA is the in-amp gain. RS is the value of the current sense resistor. Note that the system accuracy is highly dependent on the physical properties of the shunt as well as the in-amp GIA and VISET values. When selecting a shunt, be sure to consider temperature performance as well as basic precision. In constant voltage mode, when the CV feedback loop is in a steady state, the VSET input sets the battery voltage according to the equation: VBAT = VVSET = VVSET GDA 0. 4 SELECT RCL AND RCLVT FOR THE PEAK CURRENT LIMIT Figure 47 is the block diagram for peak current limit and diode emulation. Note that the current-limit sense resistor is floating between the output filter inductor and capacitor. The current generated by a fault condition defines the peak current. In turn, the peak current equals the sum of the average current (rated battery charging or discharging current) and the peak incremental inductor current: IPK = IAVG + IMAX where GDA is the difference amplifier gain. Therefore, the accuracy and temperature stability of the formation and test system are not only dependent on the accuracy and stability of the AD8452 but also on the accuracy external components. LOOP FILTER AMPLIFIERS The AD8452 has two loop filter amplifiers, also known as error amplifiers (see Figure 49). One amplifier is for constant current control (CC loop filter amplifier), and the other amplifier is for constant voltage control (CV loop filter amplifier). The outputs of these amplifiers are combined using a minimum output selector circuit to perform automatic CC to CV switching. Table 9 lists the inputs of the loop filter amplifiers for charge mode and discharge mode. where: IAVG is the battery charge/discharge current. ILMAX is the the inductor saturation current. Typically, the peak current level is set to the sum of the average current and the value of the inductor saturation current. Use the following equation to calculate the minimum current-limit sense resistor value: RCL MIN (Ω) = 50 mV I PK ( A) (2) where: IPK is the desired peak current limit in A. RCL MIN is the minimum current limit sense resistor value in Ω. 50 mV is the minimum IR drop across RCL for sufficient noise immunity during operation. Select the next higher standard resistor value for RCL. Table 9. Integrator Input Connections Feedback Loop Function Control the Current While Discharging a Battery Control the Current While Charging a Battery Control the Voltage While Discharging a Battery Control the Voltage While Charging a Battery To operate the AD8452 in discharge mode (including energy recycling) mode, apply a voltage less than 1.05 V (typical) to the MODE pin. To operate the AD8452 in charge mode, drive the MODE pin high, greater than 1.20 V (typical). The state of the MODE pin can change when the AD8452 is shut down via the EN pin or via an external fault condition signaled on the FAULT pin, a TSD event, or an UVLO condition. Reference Input ISET Feedback Terminal IVE0 ISET IVE1 VSET VVE0 VSET VVE1 The CC and CV amplifiers in charge mode and the CC amplifier in discharge mode are inverting integrators, whereas the CV amplifier in discharge mode is a noninverting integrator. Therefore, the CV amplifier in discharge mode uses an extra amplifier, the VSET buffer, to buffer the VSET input pin (see Figure 33). In addition, the CV amplifier in discharge mode uses the VVP0 pin to couple the signal from the BVMEA pin to the integrator. Next, the value for RCLVT is calculated using the following equation: I PK × RCL I CLVT RCLVT (Ω) = (3) where: RCLVT is the current-limit threshold voltage resistor value in Ω. IPK is the desired peak current limit in A. RCL is the current-limit sense resistor value in Ω. ICLVT is the CLVT pin current (21 µA typical) The AD8452 is designed so that the peak current limit is the same in both the buck mode and the boost mode of operation. A 1% or better tolerance for the RCL and RS resistors is recommended. Rev. 0 | Page 30 of 34 Data Sheet AD8452 SETTING THE OPERATING FREQUENCY AND PROGRAMMING THE SYNCHONIZATION PIN Operating modes of the AD8452 clock rely on the state of the FREQ pin and one of three possible voltage options applied to the SCFG pin. See Table 10 for a summary of synchronization options. When the voltage at the SCFG pin exceeds 4.53 V (or the pin is floating and internally connected to VREG), the AD8452 operates at the frequency set by RFREQ. The SYNC pin is configured as an output, displaying a clock signal at the programmed frequency. In this state, the clock voltage at the SYNC pin can be used as a master clock for synchronized applications. If VSCFG is ≤0.5 V, the SYNC pin is configured as an input, and the AD8452 operates as a slave device. As a slave device, the AD8452 synchronizes to the external clock applied to the SYNC pin. If the voltage applied to the SCFG pin is 0.65 V < VSCFG < 4.25 V, and a resistor is connected between SCFG and ground, the SYNC pin is configured as an input, and the AD8452 synchronizes to a phase shifted version of the external clock applied to the SYNC pin. Whether operating the AD8452 as a master or as a slave device, carefully select RFREQ using the equations in the following sections. master clock period. The slave device can synchronize to a master clock frequency running from 2% to 20% higher than the slave clock frequency. Setting RFREQ (SLAVE) to 1.11× larger than RFREQ (MASTER) runs the synchronization loop in approximately the center of the adjustment range. Programming the External Clock Phase Shift If a phase shift is not required for slave devices, connect the SCFG pin of each slave device to ground. For devices that require a phase shifted version of the synchronization clock that is applied to the SYNC pin of the slave devices, connect a resistor (RSCFG) from SCFG to ground to program the desired phase shift. To determine the RSCFG value for a desired phase shift (φSHIFT), start by calculating the frequency of the slave clock (fSLAVE). f SLAVE (kHz) = 10 4 R FREQ (SLAVE) Next, calculate the period of the slave clock. t SLAVE (µs) = 1 × 10 3 f SLAVE (kHz) Select RFREQ for Standalone or Master Clock where: tSLAVE is the period of the slave clock in µs. fSLAVE is the frequency of the slave clock in kHz. Whether master or slave, the clock frequency can be selected graphically or by applying Equation 4. Next, determine the phase time delay (tDELAY) for the desired phase shift (φSHIFT) using the following equation: Figure 26 shows the relationship between the RFREQ (MASTER) value and the programmed switching frequency. Simply identify the desired clock frequency on Axis fSET, and read the corresponding resistor value on Axis RFREQ (MASTER). To calculate the RFREQ (MASTER) value for a desired master clock synchronization frequency, use the following equation: RFREQ ( MASTER ) (kΩ ) = 4 10 f SET (kHz) t SLAVE (µs) = ϕSHIFT × t SLAVE (μs ) 360 (7) (8) where: tDELAY is the phase time delay in µs. φSHIFT is the desired phase shift. Lastly, use the following equation to calculate tDELAY: (4) where RFREQ (MASTER) is the resistor in kΩ to set the frequency for the master device, and fSET is the switching frequency in kHz. Selecting RFREQ for a Slave Device To configure the AD8452 as a slave device, drive VSCFG < 4.53 V, and the device operates at the frequency of an external clock applied to the SYNC pin. To ensure proper synchronization, select RFREQ to set the frequency to a value slightly slower than that of the master clock by using the following equation: RFREQ (SLAVE) = 1.11 × RFREQ (MASTER) (6) (5) RSCFG (kΩ) = 0.45 × RFREQ (SLAVE) (kΩ) + 50 × tDELAY (µs) (9) where: RSCFG is the corresponding resistor for the desired phase shift in kHz. See Figure 27 for the RSCFG vs. tDELAY graph. When using the phase shift feature, connect a capacitor of 47 pF or greater in parallel with RSCFG. Alternatively, the SCFG pin can be controlled with a voltage source but if an independent voltage source is used, ensure VSCFG ≤ VREG under all conditions. When the AD8452 is disabled via UVLO, VREG = 0 V, and the voltage source must be adjusted accordingly to ensure VSCFG ≤ VREG. where RFREQ (SLAVE) is the resistor value that appropriately scales the frequency for the slave device, 1.11 is the RFREQ slave to master ratio for synchronization and RFREQ (MASTER) is the resistor value of the master clock applied to the SYNC pin. The frequency of the slave device is set to a frequency slightly lower than that of the master device to allow the digital synchronization loop of the AD8452 to synchronize to the Rev. 0 | Page 31 of 34 AD8452 Data Sheet Table 10. Summary of Synchronization Options of the AD8452 SYNC Pin Input/Output State and Delay Options Input/ Output Input Input Output Delay No delay 0 μs to 7.5 μs delay (see Figure 27) No delay Figure 51 shows the internal voltage ramp of the AD8452. The voltage ramp is a well controlled 4 V p-p. T 4.5V PROGRAMMING THE MAXIMUM DUTY CYCLE The AD8452 is designed with a 97% (typical) maximum internal duty cycle. By connecting a resistor from DMAX to ground, the maximum duty cycle can be programmed at any value from 0% to 97% by using the following equation: 4V p-p D MAX (% ) = 0.03T 0.97T 16187-051 0.5V 0V Figure 51. Internal Voltage Ramp Programming the Dead Time To adjust the dead time on the synchronous DH and DL outputs, connect a resistor (RDT) from DT to DGND and bypass with a 47 pF capacitor. Select RDT for a given dead time using Figure 28 or calculate RDT using the following equations. To create a single equation for RDT, combine the equations for VDT and RDT. VDT (V ) = RDT = I DT × (t DEAD (ns) − 10.00) 3.76 VDT I DT (10) I DMAX = I FREQ = − 10.5 (13) VFREQ (14) RFREQ where IDMAX = IFREQ, the current programmed on the FREQ pin. 450 TA = +25°C MAXIMUM RESISTOR VALUE (APPROX 400kΩ) 350 300 RDMAX (kΩ) MAXIMUM DUTY CYCLE 97% 250 200 150 100 To calculate RDT for a given tDEAD, the resulting equation used is 3.76 RFREQ The DMAX current source is equivalent to the programmed current of the FREQ pin: 400 where: VDT is the DT pin programming voltage. IDT is the 20 µA (typical) internal current source. tDEAD is the desired dead time in ns. RDT is the resistor value in kΩ for the desired dead time. RDT (kΩ) = 21.5 × VFREQ × RDMAX where: DMAX is the programmed maximum duty cycle. VFREQ = 1.252 V (typical). RDMAX is the value of the resistance used to program the maximum duty cycle. RFREQ is the frequency set resistor used in the application. (11) t DEAD (ns) − 10.00 Master/Slave Sync Slave Slave Master 50 (12) 0 0 20 40 60 80 100 DUTY CYCLE (%) 16187-052 DC Control Bias Applied to the SCFG Pin (V) 0 to 0.50 0.65 to 4.25 4.53 to 5 Figure 52. RDMAX vs. Duty Cycle, RFREQ = 100 kΩ, VINT = 5 V The default maximum duty cycle of the AD8452 is 97% (typical) even if the value of RDMAX indicates a larger percentage. If a 97% internal maximum duty cycle is sufficient for the application, the DMAX pin may be pulled to VREG or left floating. The CDMAX capacitor connected from the DMAX pin to the ground plane must be 47 pF or greater. Rev. 0 | Page 32 of 34 Data Sheet AD8452 SELECTING CSS ADDITIONAL INFORMATION There are instances where it is useful to adjust the soft start delay to fit specific applications, for example, to accommodate charge or discharge battery characteristics, and the state of charge. The soft start delay is user adjustable by selecting the value of Capacitor CSS. The following reference materials provide additional insight and practical information that supplement the data sheet material contained herein: When the EN pin goes high, and with a capacitor connected to the SS pin, a 5 μA current source, ISS, becomes active and begins charging CSS, initiating a timing ramp determined by the following equation: I = C dV/dt In the limit, dV = 5 V and, because the applied current is 5 μA, CSS can be calculated for any desired time by transposing the terms of the equation. Therefore, CSS = I(dt/dV) For a 1 sec delay, CSS = 5 e – 6(1/5) or 1 μF, a 0.5 sec delay requires 0.5 μF, and so on. Rev. 0 | Page 33 of 34 AN-1319 Application Note, Compensator Design for a Battery Charge/Discharge Unit Using the AD8450 or the AD8451. AD8452-EVALZ (UG-1180), Universal Evaluation Board for the AD8452. The AD8452-EVALZ has an embedded AD8452 with reference and test loops and is designed for product evaluation and experimenters. AD8452 System Demo User Guide (UG-1181), AD8452 Battery Testing and Formation Evaluation Board. This user guide features plug and play complete on one channel and a working system, including PC control. AD8452 Data Sheet OUTLINE DIMENSIONS 0.75 0.60 0.45 9.20 9.00 SQ 8.80 1.60 MAX 37 48 36 1 PIN 1 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY (PINS DOWN) 25 12 13 VIEW A 0.50 BSC LEAD PITCH VIEW A 24 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC 051706-A 0.15 0.05 7.20 7.00 SQ 6.80 TOP VIEW 1.45 1.40 1.35 Figure 53. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD8452ASTZ AD8452ASTZ-RL AD8452-EVALZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 48-Lead Low Profile Quad Flat Package [LQFP] 48-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board Z = RoHS Compliant Part. ©2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16187-0-10/17(0) Rev. 0 | Page 34 of 34 Package Option ST-48 ST-48