NJU7291 SYSTEM RESET IC WITH WATCHDOG TIMER ■ GENERAL DESCRIPTION ■ PACKAGE OUTLINE The NJU7291 is a system reset IC with watchdog timer. It can detect an instantaneous voltage drop and break, and generates a reset signal. The NJU7291 provides a fail-safe function with an internal watchdog timer on various microcomputer systems. It is available in 8-lead DIP and MSOP (TVSP) packages. NJU7291RB1 (MSOP8 (TVSP8)) NJU7291D (DIP8) ■ FEATURES ● Supply Voltage Range : V+ = 2.5 V to 7.0 V ● RESET Detection Voltage : VRL = ± 1.0 % and Adjustable Detection Voltage with External Resistance ● Rising RESET Hold Time and Watchdog Timer RESET Time Setting Ratio = 30 : 1 ● Configurable Watchdog Timer Watching Time Independent Setting ● Configurable Stopping Watchdog Timer Function ● Package Outline : MSOP8 (TVSP8)*, DIP8 *MEET JEDEC MO-187-DA / THIN TYPE ■ PIN CONFIGRATION / PIN FUNCTION 1 3 8 NJU7291 2 PIN No. 1. 2. 3. 4. 5. 6. 7. 8. 7 6 4 5 PIN NAME CR CW CK GND V+ WDEN RSADJ RESET FUNCTION External Capacitor Pin for Setting Reset Pin External Capacitor Pin for Clock Pin Clock Input Pin Ground Pin Power Supply Pin External Register Pin for Setting Watchdog Timer Pin External Register Pin for Setting Reset Pin Reset Signal Output Pin ■ BLOCK DIAGRAM V+ 5 8 RESET REG RD1 7 CR Control VREF RD3 V CK WDT Enable RD2 V+ Reset Enable RSADJ 1 V CR CR + + 2 CW Control 3 CW CW 100kΩ 100kΩ 4 6 GND Ver.2013-08-28 WDEN -1- NJU7291 ■ ABSOLUTE MAXIMUM RATING ( Ta = 25 °C ) PARAMETER SYMBOL TEST CONDITION RATINGS UNIT Supply Voltage V+ 8.0 V Detect Voltage Input voltage VRSADJ 8.0 V Clock Input Voltage VCK ( *1 ) 8.0 V ( *1 ) 8.0 V WDEN Input Voltage VWDEN 8.0 V RESET Output Voltage VRESET 20 mA RESET Output Sink Current IRESET MSOP8(TVSP8) ( *2 ) 470 Power Dissipation PD mW DIP8( *3 ) 500 Operating Temperature Topj - 40 to + 85 °C Storage Temperature Tstg - 40 to +125 °C (*1) : When input voltage is less than +8V, the absolute maximum control voltage is equal to the input voltage. (*2) : Mounted on glass epoxy board ( 76.2 × 114.3 × 1.6mm: 2Layers FR-4 ) (*3) : Device itself ----------------------- ------------------------- ------------------------- ----------------------- ------------------------- ------------------------- ■ RECOMMENDED OPERATING CONDITION PARAMETER SYMBOL Supply Voltage V+ Detect Voltage Input voltage VRSADJ Clock Input Voltage VCK WDEN Input Voltage VWDEN ----------------------- MIN. 2.5 to 7.0 0 to V+ 0 to V+ 0 to V+ ----------------------- ■ ELECTRICAL CHARACTERISTICS < Voltage Detector Block > PARAMETER SYMBOL Reset Voltage VRL Hysteresis Voltage VHYS_RS Reference Voltage VTRS Average temperature coefficient of Reference ∆VTRS/∆Ta Voltage Output Delay Hold time TPR CR Pin Charge Current ICRD at Detect Voltage CR Pin Threshold Voltage VTCRD at Reset Release (*4) : VRH : Release Voltage < Output Block > PARAMETER TEST CONDITION (Ta = 25 °C ) TYP. V V V V Unless otherwise noted, (V+ = VRL＋0.3V, Ta = 25°C) TEST CONDITION MIN. TYP. MAX. UNIT - 1.0 % +1.0 % V VHYS_RS = VRH (*4) - VRL 63 90 117 mV 0.95 1.00 1.05 V Ta = - 40 °C to + 85°C - ±200 - ppm/°C CR = 0.01µF 1.9 2.5 3.5 ms VCR = 0.05V 3 4 5 µA VCW = 0.05V 0.95 1.00 1.05 V Unless otherwise noted, (V+ = VRL＋0.3V, Ta = 25°C) TEST CONDITION MIN. TYP. MAX. UNIT SYMBOL ------------------------- RESET Output Voltage at “ L ” Output RESET Output Sink Current at “ L ” Output RESET Minimum Operating Voltage (*5) : Rpu : Pull up Resistor VRSTL IRESET = 0.5mA, VRSADJ = 0V IRST VRESET = 0.5V, VRSADJ = 0V ------------------------- - 0.2 0.4 V 5 10 - mA - 0.8 1.2 V ------------------------- ------------------------- -2- ------------------------- ------------------------- VOPL VRESET = 0.4V, Rpu (*5) = 330kΩ Ver.2013-08-28 NJU7291 < Watch Dog Timer Block > Unless otherwise noted, (V+ = VRL＋0.3V, Ta = 25°C) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Clock Input Threshold 0.6 0.9 1.2 V VTCK Voltage Clock Input Pulse With TCKW 0.05 ms Clock Input Cycle TCK 0.1 ms WDT Monitor Time TWD CW = 0.01µF 1.5 2.0 2.8 ms CW Pin Charge Current ICK VCW = 0.05V 3 4 5 µA CW Pin Threshold Voltage VCR = 0.05V 0.95 1.00 1.05 V VTCWH at WDT Reset CW Pin Discharge Current VCW = 0.05V 30 40 50 µA ICWL at Clock Detect CW Pin Threshold Voltage VCR = 0.05V 0.18 0.20 0.22 V VTCWL at Changing Charge WDT Reset Time TWR CR = 0.01µA 0.063 0.083 0.117 ms CR Pin Charge Current VCR = 0.05V 45 60 75 µA ICRW at Timer Reset CR Pin Threshold Voltage VCW = 0.05V 0.48 0.50 0.53 V VTCRW at Release Timer Reset WDENPin Threshold Voltage 1.6 V+ V VTWDIS at Stop WDT WDENPin Threshold Voltage VTWEN 0 0.3 V at Release Stop WDT ----------------------- ----------------------- < General Characteristics > PARAMETER Operating Current Unless otherwise noted, (V+ = VRL＋0.3V, Ta = 25°C) SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT ISS WDT Active 170 250 µA ■ DETECT VOLTAGE LINE UP DEVICE NAME VRL NJU7291RB1-03 3.0V NJU7291RB1-46 4.6V Ver.2013-08-28 STATUS MP PLAN DEVICE NAME NJU7291D46 VRL 4.6V STATUS MP -3- NJU7291 ■ TIMING CHART ③ ① V + VRH VRL ② ④ ⑤ ⑦ ⑧ ⑥ ⑨ VHYS_RS VOPL WDEN CK VTCRD CR VTCRW VTCWH CW VTCWL TWD TPR RESET TWR Fig. 1 NJU7291 Timing Chart ■ OPERATING EXPLANATION ● Output Delay Hold Period ① Initial Condition Under this condition, V+ is less than release voltage: (V+<VRH (VRH =VRL+VHYS_RS)). The CR Pin and CW Pin are 0(zero) V. ――――――― (VCR=0V，VCW=0V) and RESET level is ”L”. ② In the case of V+ exceeding the Reset Release Voltage: VRH. The CR at the CR Pin is charged by “CR Pin Charge Current at Detect Voltage”: ICRD (typ. 4µA), then VCR voltage rises. ――――――― The CW Pin is 0(zero) V. And RESET level keeps ”L”. The condition returns to the state of ① when V+ decreases less than release voltage: VH. ③ In the case of the CR Pin Capacitor Voltage: VCR reaching to the CR Pin Threshold Voltage at Release Timer Reset: VTCRD (typ. 1V), after release. ――――――― The RESET level becomes from ”L” to ”H”. At this time, “Output Delay Hold Time”: TPR becomes the following period: ―――――― Time to becoming of WDEN="H" from VRH. And CR at the CR Pin is discharged then the CR Pin Voltage becomes 0(zero) V. And the CW at the CW Pin is charged by “CW Pin Charge Current”: ICW (typ. 4µA), then the VCW voltage rises. From this condition, "RESET Detection Voltage": VRL will be detectable. -4- Ver.2013-08-28 NJU7291 ● WDT Monitor Period ④ The standby condition of the clock CK falling edge detection The CW is charged by charge current: ICW. It becomes possible to detect the clock CK falling edge with greater than equal to the CW Pin threshold voltage VTCWL (typ. 0.205V). ⑤ In the case of clock CK falling edge detection When it detects the clock CK falling edge, it changes to discharging mode by ICWL (typ. 36µA) from charging mode by ICW, and the CW Pin voltage: VCW falls. Then, when the CW Pin voltage: VCW reaches the threshold voltage: VTCWL, it changes to charging mode by ICW, and the CW Pin voltage: VCW rises. ⑥ In the case of clock CK falling edge undetection In this condition, the WDT Reset Time: TWD is the time that the CW Pin voltage reaches to the threshold voltage VTCWH from the threshold voltage VTCWL. ● WDT Reset Period ⑦ Until the CR Pin Voltage: VCR exceeds “Timer Reset Release Threshold Voltage”: VTCRW (typ. 0.5V). ――――――― ――――――― Until this condition, the reset signal is kept RESET =”L”. The period keeping RESET =”L” becomes WDT Reset Time: TWR. ● Detection of Reset Voltage ⑧ In the case of Supply Voltage: V+ < Reset Voltage: VRL ――――――― At the watchdog timer monitoring period and the watchdog timer reset period, the reset signal outputs RESET =”L” at this condition. The CR Pin and CW Pin become VCR=0V and VCW=0V to discharge the CR and CW. The CR Pin and CW Pin become VCR=0V and VCW=0V in order to discharge the CR and CW. Then the operating condition returns to the state of ①. ● Stop of WDT Function ―――――― ⑨ In the case of WDT Timer Setting Pin: WDEN=”H” ―――――― Setting to WDEN=”H”, WDT Monitor operation is stopped. At this time, the CW is discharged and VCW becomes 0(zero) ――――――― ―――――― V. If Power Supply: V+ is greater than Reset Voltage: VRL, RESET is kept “H” level. Setting to WDEN=”L” or OPEN, the CW charge operation starts and returns WDT Monitor operation. ―――――― Also, when it is set the WDEN=”H” in the WDT Reset period, the WDT Monitor operation stops after the elapse of the WDT Reset Time. ―――――― When you want to not use WDT, the Pin(s) handling is the following. WDEN=”H”, CK Pin =GND or OPEN and CW Pin =OPEN. Ver.2013-08-28 -5- NJU7291 ■ External Parts Setting ● CR for Reset Time Setting The CR set the following two parameters: “Output Delay Hold Time”: TPR and “WDT Reset Time”: TWR. The TPR is calculated the following. CR ⋅ VTCRD ICRD TPR = ・・・・・・ <1> From formula<1>, CR is calculated as follows: CR = ICRD ⋅ TPR VTCRD ・・・・・・ <2> The CR value can calculate by the following formula. The CR Pin Charge Current at Detect Voltage: ICRD is 4µA (typ.). The CR Pin Threshold Voltage at Reset Release: VTCRD is 1V (typ.). CR = 4 × TPR × 10 −6 [F] ・・・・・・ <3> The unit of TPR is [s] (second). The WDT Reset Time: TWR is decided depending on the value of capacitor: CR. The TWR is calculated the following. TWR = CR ⋅ VTCRW ・・・・・・ <4> ICRW The WDT Reset Time: TWR can calculate by the following formula. The CR Pin Charge Current at Timer Reset: ICRW is 60µA (typ.). The CR Pin Threshold Voltage at Release Timer Reset: VTCRW is 0.5V (typ.). TWR = CR × 10 6 [s] ・・・・・・ <5> 120 1000 From formula<3> and <5>, the relation between TPR and TWR becomes the following. ・・・・・・ <6> From above mention, the relation between CR, TPR and TWR becomes fig 2. TPR,TWR [ms] TPR TWR = [s] 30 100 TPR TWR 10 1 0.1 0.01 0.001 0.01 0.1 1 10 CR [µF] Fig 2. Output Delay Hold Time(TPR) and WDT Reset Time(TWR) vs.CR for Reset Time Setting -6- Ver.2013-08-28 NJU7291 ● CW for Clock Monitor Time Setting The CW set the following: “WDT Monitor Time”: TWD. The TWD is calculated the following. TWD = CW ⋅ (VTCWH − VTCWL )・・ <7> ICW From formula<7>, CW is calculated as follows: ICW ⋅ TWD・・・・ <8> VTCWH − VTCWL The CW value can calculate by the following formula.The CW Pin Charge Current: ICW is 4µA (typ.). The CW Pin Threshold Voltage at WDT Reset: VTCWH is 1V (typ.). The CW Pin Threshold Voltage at Changing Charge: VTCWH is 0.2V (typ.). −6 CW = 5 × TWD × 10 [F] ・・・・・ <9> The unit of TWD is [s] (second). The relation between CW and TWD becomes Fig 3. ― PRECAUTION ― The CW discharge time becomes long as with the increasing of CW as shown in Fig 4. For this reason, if the CW discharge is not completed within the TWR, a malfunction occurs in next watchdog timer operation. To prevent this malfunction, you should set the CR value greater than one-fifth of CW value. 100 TWD [ms] CW = 1000 10 1 0.1 0.001 0.01 0.1 1 10 CW [µF] Fig 3. WDT Monitor Time(TWD) vs.CW for Clock Monitor Time Setting RESET Waveform CW Pin Waveform GND TWR (a) at CW fully discharge TWR (b) at CW faulty discharge Fig 4. WDT Reset Time (TWR) and CW Pin Voltage Waveform Ver.2013-08-28 -7- NJU7291 ● External R1/R2 for Reset Voltage Setting V+ Rpu 1 CR CR RESET 8 RESET R1 CW 2 CW RSADJ 7 R2 3 CK WDEN 6 4 GND V+ 5 マイコン MCU CK Fig 5. Application example using external resistance for Reset Voltage Setting You should consider IC internal resistance for reset voltage setting when setting reset voltage using external resistance R1/R2 like Fig 5. The Fig 6 shows the block including IC internal resistance for reset voltage setting. The Reset Voltage: VRL and Release Voltage: VRH are calculated the following using external resistance R1/R2. V+ [Reset Voltage: VRL (Transistor M1 is OFF)] ⎧ RD1 1 + (RD 2 + RD 3 ) R 2 ⎫ VRL = ⎨ ⋅ + 1⎬ ⋅ VREF・ <10> 1 + RD1 R1 ⎭ ⎩ RD 2 + RD 3 VRH R2 ・・・ <11> From Reset Voltage VRL and Release Voltage VRH , Hysteresis Voltage VHYS_RS is calculated as follows: [Hysteresis Voltage: VHYS_RS] VHYS _ RS = RD1 RSADJ RD2 [Release Voltage: VRH (Transistor M1 is ON)] ⎛ RD1 1 + RD 2 R 2 ⎞ = ⎜⎜ ⋅ + 1⎟⎟ ⋅ VREF ⎠ ⎝ RD 2 1 + RD1 R1 R1 M1 RD3 VREF Fig 6. Reset Voltage Detection Block RD1 ⋅ RD 3 ⋅ VREF ・・・<12> RD 2 ⋅ (RD 2 + RD 3) ⋅ (1 + RD1 R1) How to decide the R1/R2 value you want to set arbitrary reset voltage VRL is as follows. First, you should decide R1 value. At this time, the Hysteresis Voltage is calculated by formula<12>. Next, R2 decides The R2 value is decided by applying VRL obtained from formula <10> to formula following <13>. Because the RD1/RD2/RD3 are different depending on the reset detection voltage rank, you should confirm separately to our sales department. The VREF is equal to voltage detection reference voltage, therefore VREF=1V. R2 = -8- RD 2 + RD 3 RD 2 + RD 3 ⎛ RD1 ⎞ ⋅ (VRL − 1) ⋅ ⎜1 + ⎟ −1 RD1 R1 ⎠ ⎝ ・・・・ <13> Ver.2013-08-28 NJU7291 Ex. Using NJU7291x-03 NJU7291x-03 Reset Voltage: VRL is set at 3.0V (initial value). The IC internal resistance: RD1 to RD3 for reset voltage setting is shown Table 1. Applying these values to the formula <10> to <13>, the formula Table1. IC internal resistance value of the reset voltage detection block <14> to <17> is obtained. VREF = 1[V] and a resistance unit is [kΩ]. [NJU7291x-03] [Reset Voltage: VRL] RD1 418 kΩ R 200 kΩ D2 1 + 209 R 2 VRL = 2 ⋅ + 1 [V] ・・・・・・ <14> RD3 9 kΩ 1 + 418 R1 [Release Voltage: VRH] VRH = 2.09 ⋅ 1 + 200 R 2 + 1 [V] 1 + 418 R1 ・・・・・・ <15> [Hysteresis Voltage: VHYS_RS] VHYS _ RS = 0.09 [V] 1 + 418 R1 ・・・・・・ <16> [Calculation of R2] R2 = Ver.2013-08-28 209 [kΩ] ⎛ 418 ⎞ 0.5 ⋅ (VRL − 1) ⋅ ⎜1 + ⎟ −1 R1 ⎠ ⎝ ・・ <17> -9- NJU7291 [ CAUTION ] The specifications on this data sheet are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this data sheet are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 10 - Ver.2013-08-28