Infineon HYS72V32220GU-8-C2 3.3 v 16m x 64/72-bit 1 bank 128mbyte sdram module 3.3 v 32m x 64/72-bit 2 bank 256mbyte sdram module 168-pin unbuffered dimm module Datasheet

HYS 64/72V16300/32220GU
SDRAM-Modules
3.3 V 16M x 64/72-Bit 1 Bank 128MByte SDRAM Module
3.3 V 32M x 64/72-Bit 2 Bank 256MByte SDRAM Module
168-Pin Unbuffered DIMM Modules
• Programmed Latencies:
• 168-Pin unbuffered 8-Byte Dual-In-Line
SDRAM Modules for PC main memory
applications
Product Speed
CL
tRCD
tRP
• PC100-222, PC133-333 and PC133-222
versions
-7
PC133-222
2
2
2
-7.5
PC133-333
3
3
3
• 1 bank 16M × 64, 16M × 72 and 2 bank
32M × 64, 32M × 72 organzation
-8
PC100-222
2
2
2
• Single +3.3 V( ±0.3 V) Power Supply
• Optimized for byte-write non-parity (x64) or
ECC (x72) applications
• Programmable CAS Latency, Burst Length,
and Wrap Sequence
(Sequential and Interleave)
• JEDEC standard Synchronous DRAMs
(SDRAM)
• Auto-Refresh (CBR) and Self-Refresh
• Fully PC board layout compatible to INTEL’s
Rev. 1.0 Module Specification
• Decoupling capacitors mounted on substrate
• All inputs and outputs are LVTTL compatible
• SDRAM Performance:
• Serial Presence Detect with E2PROM
fCK Max. Clock
-7 /-7.5
-8
Unit
PC133
PC100
133
100
MHz
5.4
6
ns
• Utilizes 16M × 8 SDRAMs in TSOPII-54
packages with 4096 refresh cycles every
64 ms
Frequency
tAC Clock Access
• 133.35 mm × 31.75 mm × 4,00 mm card size
with gold-contact pads
(JEDEC MO-161-BA)
Time
Description
The HYS 64(72)V16300GU and HYS 64(72)V32220GU are industry-standard 168-pin 8-byte Dual
In-line Memory Modules (DIMMs) which are organized as 16M × 64, 16M × 72 in 1 bank and
32M × 64 and 32M × 72 in two banks of high-speed memory arrays designed with 128Mbit
Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs use -7 speed
sorted 16M × 8 SDRAM devices in TSOP54 packages to meet the PC133-222 requirements, -7.5
speed sorted for PC133-333 and use -8 components for the standard PC100-222 applications.
Decoupling capacitors are mounted on the PC board. The PC board design is in accordance with
INTEL’s Module Specification. The DIMMs have Serial Presence Detect, implemented with a serial
E 2PROM using the two-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer
and the second 128 bytes are available to the end user. All INFINEON 168-pin DIMMs provide a
high performance, flexible 8-byte interface in a 133.35 mm long footprint, with 1.25“ (31.75 mm)
height.
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SDRAM-Modules
Ordering Information
Type
Code
Package
Descriptions
Module
Height
128 MByte DIMMs
PC133-222-520 L-DIM-168-33 133 Mhz 16M × 64
1 bank SDRAM module
1.25“
HYS 64V16300GU-7.5-C2 PC133-333-520 L-DIM-168-33 133 Mhz 16M × 64
1 bank SDRAM module
1.25“
HYS 64V16300GU-8-C2
PC100-222-620 L-DIM-168-33 100 MHz 16M × 64
1 bank SDRAM module
1.25“
HYS 72V16300GU-7-C2
PC133-222-520 L-DIM-168-33 133 Mhz 16M × 72
1 bank SDRAM module
1.25“
HYS 72V16300GU-7.5-C2 PC133-333-520 L-DIM-168-33 133 Mhz 16M × 72
1 bank SDRAM module
1.25“
PC100-222-620 L-DIM-168-33 100 MHz 16M × 72
1 bank SDRAM module
1.25“
PC133-222-520 L-DIM-168-30 133 MHz 32M × 64
2 bank SDRAM module
1.25“
HYS 64V32220GU-7.5-C2 PC133-333-520 L-DIM-168-30 133 MHz 32M × 64
2 bank SDRAM module
1.25“
HYS 64V32220GU-8-C2
PC100-222-620 L-DIM-168-30 100 MHz 32M × 64
2 bank SDRAM module
1.25“
HYS 72V32220GU-7-C2
PC133-222-520 L-DIM-168-30 133 Mhz 32M × 72
2 bank SDRAM module
1.25“
HYS 72V32220GU-7.5-C2 PC133-333-520 L-DIM-168-30 133 Mhz 32M × 72
2 bank SDRAM module
1.25“
PC100-222-620 L-DIM-168-30 100 Mhz 32M × 72
2 bank SDRAM module
1.25“
HYS 64V16300GU-7-C2
HYS 72V16300GU-8-C2
256 MByte DIMMs
HYS 64V32220GU-7-C2
HYS 72V32220GU-8-C2
Note: All part numbers end with a place code, designating the die revision. Consult factory for
current revision. Example: HYS 64V16300GU-8-C2, indicates that Rev.C2 dies are used for
SDRAM components.
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SDRAM-Modules
Pin Definitions and Functions
A0-A11
Address Inputs
WE
Read/Write Input V SS
BA0, BA1
Bank Selects
CKE0, CKE1 *)
Clock Enable
SCL Clock for SPD
DQ0 - DQ63 Data Input/Output
CLK0 - CLK3
Clock Input
SDA Serial Data Out
CB0-CB7
Check Bits
(x72 modules only)
DQMB0 - DQMB7 Data Mask
N.C. No Connection
RAS
Row Address Strobe CS0 - CS3 *)
CAS
Column Address
Strobe
VDD
Ground
Chip Select
–
–
Power (+3.3 V)
–
–
*) CKE1, CS1 and CS3 on two bank modules only
Address Format
Rows
Columns
Bank Select
Refresh Period Interval
16M × 64 HYS 64V16300GU
Part Number
12
10
2
4k
64 ms
15,6 µs
16M × 72 HYS 72V16300GU
12
10
2
4k
64 ms
15,6 µs
32M × 64 HYS 64V32220GU
12
10
2
4k
64 ms
15,6 µs
32M × 72 HYS 72V32220GU
12
10
2
4k
64 ms
15,6 µs
Pin Configuration
PIN# Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
1
VSS
43
VSS
85
VSS
127
VSS
2
DQ0
44
DU
86
DQ32
128
CKE0
3
DQ1
45
CS2
87
DQ33
129
CS3
4
DQ2
46
DQMB2
88
DQ34
130
DQMB6
5
DQ3
47
DQMB3
89
DQ35
131
DQMB7
6
VDD
48
DU
90
VDD
132
N.C.
7
DQ4
49
VDD
91
DQ36
133
VDD
8
DQ5
50
N.C.
92
DQ37
134
N.C.
9
DQ6
51
N.C.
93
DQ38
135
N.C.
10
DQ7
52
N.C. (CB2)
94
DQ39
136
CB6
11
DQ8
53
N.C. (CB3)
95
DQ40
137
CB7
12
VSS
54
VSS
96
VSS
138
VSS
13
DQ9
55
DQ16
97
DQ41
139
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
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SDRAM-Modules
Pin Configuration (cont’d)
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
16
PIN# Symbol
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
VDD
101
DQ45
143
VDD
18
VDD
60
DQ20
102
VDD
144
DQ52
19
DQ14
61
N.C.
103
DQ46
145
N.C.
20
DQ15
62
DU
104
DQ47
146
DU
21
N.C. (CB0)
63
CKE1
105
N.C. (CB4)
147
N.C.
22
N.C. (CB1)
64
VSS
106
N.C. (CB5)
148
VSS
23
VSS
65
DQ21
107
VSS
149
DQ53
24
N.C.
66
DQ22
108
N.C.
150
DQ54
25
N.C.
67
DQ23
109
N.C.
151
DQ55
26
VDD
68
VSS
110
VDD
152
VSS
27
WE
69
DQ24
111
CAS
153
DQ56
28
DQMB0
70
DQ25
112
DQMB4
154
DQ57
29
DQMB1
71
DQ26
113
DQMB5
155
DQ58
30
CS0
72
DQ27
114
CS1
156
DQ59
31
DU
73
VDD
115
RAS
157
VDD
32
VSS
74
DQ28
116
VSS
158
DQ60
33
A0
75
DQ29
117
A1
159
DQ61
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
36
A6
78
VSS
120
A7
162
VSS
37
A8
79
CLK2
121
A9
163
CLK3
38
A10
80
N.C.
122
BA0
164
N.C.
39
BA1
81
WP
123
A11
165
SA0
40
VDD
82
SDA
124
VDD
166
SA1
41
VDD
83
SCL
125
CLK1
167
SA2
42
CLK0
84
VDD
126
N.C.
168
VDD
Note: Pin names in parentheses are for the x72 ECC versions; example: Pin 106 = (CB5).
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SDRAM-Modules
WE
CS0
DQMB0
DQ(7:0)
CS
WE
DQM
DQ0-DQ7
D0
DQMB4
DQ(39:32)
CS
WE
DQM
DQ0-DQ7
D4
DQMB1
DQ(15:8)
CS
WE
DQM
DQ0-DQ7
D1
DQMB5
DQ(47:40)
CS
WE
DQM
DQ0-DQ7
D5
CS
WE
DQM
DQ0-DQ7
D8
CB(7:0)
CS2
DQMB2
DQ(23:16)
CS
WE
DQM
DQ0-DQ7
D2
DQMB6
DQ(55:48)
WE
CS
DQM
DQ0-DQ7
D6
DQMB3
DQ(31:24)
CS
WE
DQM
DQ0-DQ7
D3
DQMB7
DQ(63:56)
CS
WE
DQM
DQ0-DQ7
D7
A0-A11, BA0, BA1
VCC
VSS
2
E PROM (256 word x 8 Bit)
D0-D7, (D8)
SA0
SA1
SA2
SCL
D0-D7, (D8)
C0-C15, (C16, C17)
D0-D7, (D8)
RAS
D0-D7, (D8)
CAS
D0-D7, (D8)
CKE0
D0-D7, (D8)
SA0
SA1
SA2
SCL
SDA
WP
47 k Ω
Clock Wiring
16 M x 64
CLK0
CLK1
CLK2
CLK3
Note: D8 is only used in the x72 ECC version and
all resistor values are 10 Ohm except
otherwise noted.
4 SDRAM + 3.3 pF
Termination
4 SDRAM + 3.3 pF
Termination
16 M x 72
5 SDRAM
Termination
4 SDRAM + 3.3 pF
Termination
Block Diagram for 16M x 64/72 SDRAM DIMM Modules (HYS 64/72V16300GU)
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SDRAM-Modules
CS1
CS0
CS
DQM
DQ0-DQ7
D0
CS
DQM
DQ0-DQ7
D8
DQMB4
DQ(39:32)
CS
DQM
DQ0-DQ7
D4
CS
DQM
DQ0-DQ7
D12
CS
DQM
DQ0-DQ7
DQMB5
DQ(47:40)
D1
CS
DQM
DQ0-DQ7
D9
CS
DQM
DQ0-DQ7
D5
CS
DQM
DQ0-DQ7
D13
CS
DQM
DQ0-DQ7
D16
CS
DQM
DQ0-DQ7
D17
DQMB2
DQ(23:16)
CS
DQM
DQ0-DQ7
D2
CS
DQM
DQ0-DQ7
D10
DQMB6
DQ(55:48)
CS
DQM
DQ0-DQ7
D6
CS
DQM
DQ0-DQ7
D14
DQMB3
DQ(31:24)
CS
DQM
DQ0-DQ7
D3
CS
DQM
DQ0-DQ7
D11
DQMB7
DQ(63:56)
CS
DQM
DQ0-DQ7
D7
CS
DQM
DQ0-DQ7
D15
DQMB0
DQ(7:0)
DQMB1
DQ(15:8)
CB(7:0)
CS3
CS2
A0-A11, BA0, BA1
VDD
VSS
2
E PROM (256 Word x 8 Bit)
D0-D15, (D16, D17)
SA0
SA1
SA2
SCL
D0-D15, (D16, D17)
C0-C31, (C32...C35)
D0-D7, (D8)
RAS, CAS, WE
SA0
SA1
SA2
SCL
SDA
WP
47 kΩ
D0-D15, (D16, D17)
CKE0
Clock Wiring
D0-D7, (D16)
VDD
32 M x 64
10 kΩ
CKE1
CLK0
CLK1
CLK2
CLK3
D9-D15, (D17)
4 SDRAM
4 SDRAM
4 SDRAM
4 SDRAM
+ 3.3 pF
+ 3.3 pF
+ 3.3 pF
+ 3.3 pF
32 M x 72
5 SDRAM
5 SDRAM
4 SDRAM + 3.3 pF
4 SDRAM + 3.3 pF
Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10Ω except otherwise noted.
BL01
Block Diagram for 32M x 64/72 SDRAM DIMM Modules (HYS 64/72V32220GU)
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SDRAM-Modules
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
min.
max.
Unit
Input / Output voltage relative to VSS
VIN, VOUT
– 1.0
4.6
Power supply voltage on VDD
VDD
– 1.0
4.6
V
V
Storage temperature range
T STG
-55
+150
o
Power dissipation per SDRAM component
PD
–
1
W
Data out current (short circuit)
IOS
–
50
mA
C
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended operation conditions.
Exposure to higher than recommended voltage for extended periods of time affect device reliability
DC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ±0.3 V
Parameter
Symbol
Limit Values
Unit
min.
max.
Input High Voltage
VIH
2.0
VDD + 0.3
Input Low Voltage
VIL
–0.5
0.8
V
Output High Voltage (IOUT = – 4.0 mA)
VOH
2.4
–
V
V
Output Low Voltage (IOUT = 4.0 mA)
VOL
–
0.4
V
Input Leakage Current, any input
(0 V < VIN < 3.6 V, all other inputs = 0 V)
II(L)
–40
40
µA
Output Leakage Current
(DQ is disabled, 0 V < VOUT < VDD)
IO(L)
–40
40
µA
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V ±0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
Unit
max.
max.
max.
16M×64 16M×72 32M×64
max.
32M×72
Input Capacitance
(A0 to A11, BA0, BA1, RAS, CAS, WE)
CI1
65
72
105
144
pF
Input Capacitance (CS0 - CS3)
CCS
32
40
35
43
pF
Input Capacitance (CLK0 - CLK3)
CCLK
38
40
42
45
pF
Input Capacitance (CKE0, CKE1)
CCKE
65
72
65
72
pF
Input Capacitance (DQMB0 - DQMB7)
CI4
13
13
20
20
pF
Input/Output Capacitance
(DQ0 - DQ63, CB0 - CB7)
CIO
10
10
17
17
pF
Input Capacitance (SCL, SA0-2)
CSC
8
8
8
8
pF
Input/Output Capacitance
CSD
8
8
8
8
pF
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SDRAM-Modules
Operating Currents per SDRAM Component
TA = 0 to 70 oC, VDD = 3.3 V ±0.3 V
Parameter
Operating Current
Test
Condition
Symbol
-7 /7.5 -8
Unit Note
–
ICC1
160
150
mA
1)
tCK = min.
ICC2P
1.5
1.5
mA
1)
tCK = min.
ICC2N
40
35
mA
1)
CKE ≥ V IH(MIN.) ICC3N
50
45
mA
1)
CKE ≤ V IL(MAX.) ICC3P
10
10
mA
1)
max.
tRC = tRCMIN., tCK = tCKMIN.
Outputs open, Burst Length = 4, CL = 3
All banks operated in random access,
all banks operated in ping-pong manner
to maximize gapless data access
Precharge Standby Current
in Power Down Mode
CS = V IH (min.), CKE ≤ VIL(MAX)
Precharge Stand-by Current
in Non-Power Down Mode
CS = V IH (MIN.), CKE ≥ V IH(MIN)
No Operating Current
tCK = min., CS = VIH(MIN),
active state (max. 4 banks)
Burst Operating Current
tCK = min.,
Read command cycling
–
ICC4
100
90
mA
1), 2)
Auto-Refresh Current
tCK = min.,
Auto-Refresh command cycling
–
ICC5
230
210
mA
1)
Self-Refresh Current
Self-Refresh Mode, CKE = 0.2 V
–
ICC6
1.5
1.5
mA
1)
1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7 and 7.5 modules
and at 100 Mhz for -8 modules. Input signals are changed once during tCK, except for ICC6 and for standby
currents when tCK = infinity. All values are shown per memory component.
2. These parameters are measured with continuous data stream during read access and all DQ toggling. CL = 3
and BL = 4 assumed and the data-out current is excluded
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SDRAM-Modules
AC Characteristics
3), 4)
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ±0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
-7
PC133-222
-7.5
PC133-333
Unit
Note
-8
PC100-222
min.
max. min.
max. min.
max.
7.5
7.5
–
–
7.5
10
–
–
10
10
–
–
ns
ns
–
–
133
133
–
–
133
100
–
–
100
100
MHz
MHz
–
–
5.4
5.4
–
–
5.4
6
–
–
6
6
ns
ns
Clock and Access Time
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
tCK
System Frequency
CAS Latency = 3
CAS Latency = 2
fCK
Clock Access Time
CAS Latency = 3
CAS Latency = 2
tAC
Clock High Pulse Width
tCH
2.5
–
2.5
–
3
–
ns
6)
Clock Low Pulse Width
tCL
2.5
–
2.5
–
3
–
ns
6)
Input Setup Time
tIS
1.5
–
1.5
–
2
–
ns
7)
Input Hold Time
tIH
0.8
–
0.8
–
1
–
ns
7)
Power Down Mode Entry
Time
tSB
–
1
–
1
–
1
CLK
8)
Power Down Mode Exit
Setup Time
tPDE
1
–
1
–
1
–
CLK
9)
Mode Register Setup Time
tRSC
2
–
2
–
2
–
CLK
1
–
1
–
1
–
ns
–
–
–
4), 5)
Setup & Hold Parameters
Transition Time (rise and fall) tT
Common Parameters
RAS to CAS Delay
tRCD
15
–
20
–
20
–
ns
–
Precharge Time
tRP
15
–
20
–
20
–
ns
–
Active Command Period
tRAS
42
100k
45
100k
50
100k
ns
–
Cycle Time
tRC
60
–
67.5
–
70
–
ns
–
Bank-to-Bank Delay Time
tRRD
14
–
15
–
16
–
ns
–
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SDRAM-Modules
AC Characteristics (cont’d) 3), 4)
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ±0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
-7
PC133-222
-7.5
PC133-333
Note
CLK
–
-8
PC100-222
min.
max. min.
max. min.
max.
tCCD
1
–
1
–
1
–
Refresh Period (4096 cycles) tREF
CAS to CAS Delay Time
(same bank)
Unit
Refresh Cycle
–
64
–
64
–
64
ms
tSREX
1
–
1
–
1
–
CLK
10)
Data Out Hold Time
tOH
3
–
3
–
3
–
ns
4)
Data Out to Low Impedance
tLZ
0
–
0
–
0
–
ns
–
Data Out to High Impedance
tHZ
3
7
3
7
3
8
ns
11
DQM Data Out Disable
Latency
tDQZ
–
2
–
2
–
2
CLK
–
Data Input to Precharge
(write recovery)
tWR
2
–
2
–
2
–
CLK
–
DQM Write Mask Latency
tDQW
0
–
0
–
0
–
CLK
–
Self-Refresh Exit Time
Read Cycle
Write Cycle
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SDRAM-Modules
Notes
3. All AC characteristics are shown on SDRAM component level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must
be given followed by eight Auto-Refresh (CBR) cycles before the Mode Register Set Operation
can begin.
4. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between V IH and VIL. All AC measurements assume
tT = 1 ns with the AC output load circuit show. Specified tAC and tOH parameters are measured
with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate
between 0.8 V and 2.0 V.
5. If clock rising time is longer than 1 ns, a time (tT/2 – 0.5) ns must be added to this parameter.
6. Rated at 1.4 V
7. If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.
8. Anytime the Refresh Period has been exceeded, a minimum of two Auto-Refresh (CBR)
commands must be given to “wake-up” the device.
9. Timing is asynchronous. If setup time is not met by rising edge of the clock then the CKE signal
is assumed latched on the next cycle.
10.Self-Refresh Exit is a synchronous operation and begins on the second positive clock edge after
CKE returns high. Self-Refresh Exit is not complete until a time period equal to tRC is satisfied
after the Self Refresh Exit command is registered.
11.This is referenced to the time at which the output achieves the open circuit condition, not to
output voltage levels.
t CH
2.4 V
0.4 V
1.4 V
CLOCK
t CL
t IS
tT
t IH
1.4 V
INPUT
tAC
t LZ
t AC
t OH
OUTPUT
I/O
1.4 V
50 pF
t HZ
Measurement conditions for
tAC and tOH
IO.vsd
A Serial Presence Detect storage device—E2PROM—is assembled onto the module. Information about the
module configuration, speed, etc. is written into the E2PROM device during module production using a Serial
Presence Detect protocol (I2C synchronous 2-wire bus).
INFINEON Technologies
11
9.01
HYS 64/72V16300/32220GU
SDRAM-Modules
SPD-Table for PC133-222 Modules:
Byte#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Description
Number of SPD bytes
Total bytes in Serial PD
Memory Type
Number of Row Addresses
(without BS bits)
Number of Column Addresses
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL=3
SDRAM Access time from
Clock at CL=3
Dimm Config
Refresh Rate/Type
SDRAM width, Primary
Error Checking SDRAM data
width
Minimum clock delay for
back-to-back random column
address
Burst Length supported
Number of SDRAM banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM module
attributes
SDRAM Device Attributes
:General
Min. Clock Cycle Time at
CAS Latency = 2
Max. data access time from
Clock for CL=2
Minimum Clock Cycle Time
at CL = 1
Maximum Data Access Time
from Clock at CL=1
Minimum Row Precharge
Time
Minimum Row Active to Row
Active delay tRRD
INFINEON Technologies
SPD Entry
Value
Hex
128
256
SDRAM
12
16Mx64 16Mx72 32Mx64 32Mx72
-7
-7
-7
-7
80
08
04
0C
10
0A
1/2
64 / 72
0
LVTTL
7.5 ns
5.4 ns
none / ECC
Self-Refresh,
15.6 µs
x8
n/a / x8
01
40
02
48
48
00
02
00
08
00
01
75
54
00
02
80
08
00
08
t ccd = 1 CLK
01
1, 2, 4 & 8
4
CAS latency = 2
& 3
CS latency = 0
Write latency = 0
non buffered/non
reg.
Vcc tol +/- 10%
0F
04
06
0E
7.5 ns
75
5.4 ns
54
not supported
FF
not supported
FF
15 ns
0F
14 ns
0E
12
40
01
01
00
9.01
HYS 64/72V16300/32220GU
SDRAM-Modules
Byte#
Description
29
Minimum RAS to CAS delay
tRCD
30 Minimum RAS pulse width
tRAS
31 Module Bank Density (per
bank)
32 SDRAM input setup time
33 SDRAM input hold time
34 SDRAM data input hold time
35 SDRAM data input setup
time
62-61 Superset information (may be
used in future)
62 SPD Revision
63 Checksum for bytes 0 - 62
64- Manufacturers information
125
126 Frequency Specification
127 Support Details
128+ Unused storage locations
INFINEON Technologies
SPD Entry
Value
Hex
15 ns
16Mx64 16Mx72 32Mx64 32Mx72
-7
-7
-7
-7
0F
42 ns
2A
128 MByte
20
1.5
0.8
1.5
0.8
ns
ns
ns
ns
15
08
15
08
FF
Revision 1.2
12
CE
XX
E0
XX
tbd
XX
tbd
XX
64
AF
FF
FF
13
9.01
HYS 64/72V16300/32220GU
SDRAM-Modules
SPD-Table for PC133-333 Modules:
Byte#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Description
Number of SPD bytes
Total bytes in Serial PD
Memory Type
Number of Row Addresses
(without BS bits)
Number of Column Addresses
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL=3
SDRAM Access time from
Clock at CL=3
Dimm Config
Refresh Rate/Type
SDRAM width, Primary
Error Checking SDRAM data
width
Minimum clock delay for
back-to-back random column
address
Burst Length supported
Number of SDRAM banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM module
attributes
SDRAM Device Attributes
:General
Min. Clock Cycle Time at
CAS Latency = 2
Max. data access time from
Clock for CL=2
Minimum Clock Cycle Time
at CL = 1
Maximum Data Access Time
from Clock at CL=1
Minimum Row Precharge
Time
Minimum Row Active to Row
Active delay tRRD
INFINEON Technologies
SPD Entry
Value
Hex
128
256
SDRAM
12
16Mx64 16Mx72 32Mx64 32Mx72
-7.5
-7.5
-7.5
-7.5
80
08
04
0C
10
0A
1/2
64 / 72
0
LVTTL
7.5 ns
5.4 ns
none / ECC
Self-Refresh,
15.6 µs
x8
n/a / x8
01
40
02
48
48
00
02
00
08
00
01
75
54
00
02
80
08
00
08
t ccd = 1 CLK
01
1, 2, 4 & 8
4
CAS latency = 2
& 3
CS latency = 0
Write latency = 0
non buffered/non
reg.
Vcc tol +/- 10%
0F
04
06
0E
10.0 ns
A0
6.0 ns
60
not supported
FF
not supported
FF
20 ns
14
15 ns
0F
14
40
01
01
00
9.01
HYS 64/72V16300/32220GU
SDRAM-Modules
Byte#
Description
29
Minimum RAS to CAS delay
tRCD
30 Minimum RAS pulse width
tRAS
31 Module Bank Density (per
bank)
32 SDRAM input setup time
33 SDRAM input hold time
34 SDRAM data input hold time
35 SDRAM data input setup
time
62-61 Superset information (may be
used in future)
62 SPD Revision
63 Checksum for bytes 0 - 62
64- Manufacturers information
125
126 Frequency Specification
127 Support Details
128+ Unused storage locations
INFINEON Technologies
SPD Entry
Value
Hex
20 ns
16Mx64 16Mx72 32Mx64 32Mx72
-7.5
-7.5
-7.5
-7.5
14
45 ns
2D
128 MByte
20
1.5
0.8
1.5
0.8
ns
ns
ns
ns
15
08
15
08
FF
Revision 1.2
12
13
XX
25
XX
14
XX
26
XX
64
AF
FF
FF
15
9.01
HYS 64/72V16300/32220GU
SDRAM-Modules
SPD-Table for PC100 Modules:
Byte#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Description
Number of SPD bytes
Total bytes in Serial PD
Memory Type
Number of Row Addresses
(without BS bits)
Number of Column Addresses
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL=3
SDRAM Access time from
Clock at CL=3
Dimm Config
Refresh Rate/Type
SDRAM width, Primary
Error Checking SDRAM data
width
Minimum clock delay for
back-to-back random column
address
Burst Length supported
Number of SDRAM banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM module
attributes
SDRAM Device Attributes
:General
Min. Clock Cycle Time at
CAS Latency = 2
Max. data access time from
Clock for CL=2
Minimum Clock Cycle Time
at CL = 1
Maximum Data Access Time
from Clock at CL=1
Minimum Row Precharge
Time
Minimum Row Active to Row
Active delay tRRD
INFINEON Technologies
SPD Entry
Value
Hex
128
256
SDRAM
12
16Mx64 16Mx72 32Mx64 32Mx72
-8
-8
-8
-8
80
08
04
0C
10
0A
1/2
64 / 72
0
LVTTL
10.0 ns
6.0 ns
none / ECC
Self-Refresh,
15.6 µs
x8
n/a / x8
01
40
02
48
48
00
02
00
08
00
01
A0
60
00
02
80
08
00
08
t ccd = 1 CLK
01
1, 2, 4 & 8
4
CAS latency = 2
& 3
CS latency = 0
Write latency = 0
non buffered/non
reg.
Vcc tol +/- 10%
0F
04
06
0E
10.0 ns
A0
6.0 ns
60
not supported
FF
not supported
FF
20 ns
14
16 ns
10
16
40
01
01
00
9.01
HYS 64/72V16300/32220GU
SDRAM-Modules
Byte#
Description
29
Minimum RAS to CAS delay
tRCD
30 Minimum RAS pulse width
tRAS
31 Module Bank Density (per
bank)
32 SDRAM input setup time
33 SDRAM input hold time
34 SDRAM data input hold time
35 SDRAM data input setup
time
62-61 Superset information (may be
used in future)
62 SPD Revision
63 Checksum for bytes 0 - 62
64- Manufacturers information
125
126 Frequency Specification
127 Support Details
128+ Unused storage locations
INFINEON Technologies
SPD Entry
Value
Hex
20 ns
16Mx64 16Mx72 32Mx64 32Mx72
-8
-8
-8
-8
14
45 ns
2D
128 MByte
20
2 ns
1 ns
2 ns
1 ns
20
10
20
10
FF
Revision 1.2
12
71
XX
83
XX
100 MHz
72
XX
84
XX
64
AF
FF
FF
17
9.01
HYS 64/72V16300/32220GU
SDRAM-Modules
Package Outlines
L-DIM-168-30 (JEDEC MO-161-BA)
SDRAM DIMM Module Package
133.35 +- 0.15
4 max.
4
31.75 +- 0.13
127.35
*)
3
1
10
3
11
6.35
1.27
40
41
6.35
84
1.27 +- 0.1
42.18
85
94
2
95
124
125
168
17.78
3.125
91 x 1.27 = 115.57
*)
3 min.
3
*) on ECC modules only
2.55
0.25
Detail of Contacts
1
1.27
L-DIM-168-30
Note: All tolerances according to JEDEC standard
INFINEON Technologies
18
9.01
HYS 64/72V16300/32220GU
SDRAM-Modules
Package Outlines
L-DIM-168-33 (JEDEC MO-161-BA)
SDRAM DIMM Module Package
HYS 64/72V16300GU
133.35 -+ 0.15
3 max.
4
+
- 0.13
127.35
31.75
*)
3
1
10
3
11
6.35
1.27
40
41
6.35
84
1.27 +- 0.1
42.18
2
85
94
95
124
125
168
17.78
3.125
91 x 1.27 = 115.57
3 min.
3
*) on ECC modules only
2.55
0.25
Detail of Contacts
1
1.27
L-DIM-168-33
Note: All tolerances according to JEDEC standard
INFINEON Technologies
19
9.01
HYS 64/72V16300/32220GU
SDRAM-Modules
Update Releases:
June 1, 1999
June 17, 1999
August 3, 1999
August 5, 1999
August 23, 1999
Sept.30, 1999
Dec. 2, 1999
Feb. 23, 2000
10.5.2000
21.8.2000
06.09.2001
INFINEON Technologies
Explanation for factory specific code in part numbers added
Byte 22 for PC100 modules changed from 06 to 0E
PC133 spec incorpoated
SPD tables added
Byte 126 changed to 64h for PC133 modules
Some errors corrected, checksums added
Some timing parameters adjusted according to INTELs PC133 specification
-8A speedsort removed
ICC currents updated in accordance to 128Mbit component datasheets
Capacitance values updated according to module C-measurements
Block Diagrams corrected, R&L template
Reference to JEDEC MO-161-BA added
PC133-222 modules “-7 speed sort” added
SCR : Absolute Maximum Ratings table added
20
9.01
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