Crystal or Differential to Differential Clock Fanout Buffer IDT8T39S10I DATASHEET General Description Features The IDT8T39S10I is a high-performance clock fanout buffer. The input clock can be selected from two differential inputs or one crystal input. The internal oscillator circuit is automatically disabled if the crystal input is not selected. The crystal pin can be driven by single-ended clock when crystal is bypassed.The selected signal is distributed to ten differential outputs which can be configured as LVPECL, LVDS or HSCL outputs. In addition, an LVCMOS output is provided. All outputs can be disabled into a high-impedance state. The device is designed for signal fanout of high-frequency, low phase-noise clock and data signal. The outputs are at a defined level when inputs are open circuit or tied to ground. It is designed to operate from a 3.3V or 2.5V core power supply, and either a 3.3V or 2.5V output operating supply. • • Two differential reference clock input pairs • • • Crystal Oscillator Interface • Two banks, each has five differential output pairs that can be configured as LVPECL or LVDS or HCSL • One single-ended reference output with synchronous enable to avoid clock glitch • Output skew: (Bank A and Bank B at the same output level) 70ps (max) • • • Part-to-part skew: 250ps (max) • • -40°C to 85°C ambient operating temperature IDT8T39S10NLGI REVISION A MARCH 18. 2014 1 Differential input pairs can accept the following differential input levels: LVPECL, LVDS, HCSL Crystal input frequency range: 10MHz to 40MHz Maximum Output Frequency LVPECL - 2GHz LVDS - 2GHz HCSL - 250MHz LVCMOS - 250MHz Additive RMS phase jitter: 0.153ps (typical) Supply voltage modes: VDD/VDDO 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V Lead-free (RoHS 6) packaging ©2014 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Block Diagram SMODEA[1:0] Pulldown REF_SEL[1:0] Pulldown CLK0 Pulldown nCLK0 CLK1 nCLK1 QA0 nQA0 QA1 nQA1 QA2 nQA2 QA3 nQA3 QA4 nQA4 00 Pullup/Pulldown Pulldown 01 Pullup/Pulldown XTAL_IN 10 or 11 OSC XTAL_OUT QB0 nQB0 QB1 nQB1 QB2 nQB2 QB3 nQB3 QB4 nQB4 IREF SMODEB[1:0] Pulldown REFOUT OE_SE Pulldown SYNC QB2 nQB2 VDDO 33 32 31 30 29 nQB4 VDDO 34 QB4 nQB1 35 QB3 QB1 36 nQB3 QB0 nQB0 Pin Assignment 28 27 26 25 GND 37 24 GND IREF 38 23 SMODEB0 SMODEB1 39 22 REF_SEL1 21 nCLK0 20 CLK0 19 REF_SEL0 18 GND 17 XTAL_OUT 16 XTAL_IN nCLK1 40 CLK1 41 VDD 42 GND 43 REFOUT 44 VDDO 45 IDT8T39S10I 48-Lead VFQFN 7.0mm x 7.0mm x 0.925mm, package body 5.65mm x 5.65mm Epad size NL Package Top View IDT8T39S10NLGI REVISION A MARCH 18. 2014 7 8 2 9 10 11 12 nQA4 6 QA4 5 QA3 4 nQA3 3 VDDO 2 nQA2 1 QA2 GND VDDO SMODEA0 13 nQA1 14 GND 48 QA1 VDD QA0 15 nQA0 OE_SE 46 SMODEA1 47 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type 1, 2 QA0, nQA0 Output Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels. 3, 4 QA1, nQA1 Output Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels. 5, 8, 29, 32, 45 VDDO Power Output supply pins. 6, 7 QA2, nQA2 Output Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels. 9, 10 QA3, nQA3 Output Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels. 11, 12 QA4, nQA4 Output Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels. 13, 18, 24, 37, 43, 48 GND Power Power supply ground. 14, 47 SMODEA0, SMODEA1 Input 15, 42 VDD Power Power supply pins. 16, 17 XTAL_IN, XTAL_OUT Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 19, 22 REF_SEL0, REF_SEL1 Input Pulldown Input clock selection. LVCMOS/LVTTL interface levels. See Table 3A for function. 20 CLK0 Input Pulldown Non-inverting differential clock. 21 nCLK0 Input Pullup/ Pulldown Inverting differential clock. Internal resistor bias to VDD/2. 23, 39 SMODEB0, SMODEB1 Input Pulldown Output driver select for Bank B outputs. See Table 3D for function. LVCMOS/LVTTL interface levels. 25, 26 nQB4, QB4 Output Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels. 27, 28 nQB3, QB3 Output Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels. 30, 31 nQB2, QB2 Output Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels. 33, 34 nQB1, QB1 Output Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels. 35, 36 nQB0, QB0 Output Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels. 38 IREF Input 40 nCLK1 Input Pullup/ Pulldown Inverting differential clock. Internal resistor bias to VDD/2. 41 CLK1 Input Pulldown Non-inverting differential clock. 44 REFOUT Output 46 OE_SE Input Pulldown Description Output driver select for Bank A outputs. See Table 3D for function. LVCMOS/LVTTL interface levels. An external fixed precision resistor (475) from this pin to ground provides a reference current used for HCSL mode. QXx, nQXx clock outputs. Single-ended reference clock output. LVCMOS/LVTTL interface levels Pulldown Output enable. LVCMOS/LVTTL interface levels. See Table 3B. NOTE: Pulldown and Pullup refer to an internal input resistors. See Table 2, Pin Characteristics, for typical values. IDT8T39S10NLGI REVISION A MARCH 18. 2014 3 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Table 2. Pin Characteristics Symbol Parameter Test Conditions CIN Input Capacitance RPULLDOWN Minimum SMODEx[0:1], REF_SEL[0:1], OE_SE pins Typical Maximum Units 4 pF Input Pulldown Resistor 51 k RPULLUP Input Pullup Resistor 51 k CPD Power Dissipation Capacitance VDDO = 3.3V 3.5 pF CPD Power Dissipation Capacitance REFOUT VDDO = 3.3V 8 pF VDDO = 2.5V 7 pF ROUT Output Impedance REFOUT VDDO = 3.3V 15 REFOUT VDDO = 2.5V 20 Qx, nQx Function Tables Table 3A. REF_SELx Function Table Control Input Table 3B. OE_SE Function Table Selected Input Reference Clock REF_SEL[1:0] 00 (default) CLK0, nCLK0 01 CLK1, nCLK1 10 XTAL 11 XTAL OE_SE REFOUT 0 (default) High-Impedance 1 Enabled NOTE: Synchronous output enable to avoid clock glitch. Table 3C. Input/Output Operation Table, OE_SE Input Status Output State OE_SE REF_SEL [1:0] CLKx and nCLKx 0 (default) Don’t care Don’t Care High Impedance 1 10 or 11 Don’t Care Fanout crystal oscillator 1 1 00 (default) 01 REFOUT CLK0 and nCLK0 are both open circuit Logic low CLK0 and nCLK0 are tied to ground Logic low CLK0 is high, nCLK0 is low Logic High CLK0 is low, nCLK0 is high Logic Low CLK1 and nCLK1 are both open circuit Logic low CLK1 and nCLK1 are tied to ground Logic low CLK1 is high, nCLK1 is low Logic High CLK1 is low, nCLK1 is high Logic Low IDT8T39S10NLGI REVISION A MARCH 18. 2014 4 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Table 3D. Input/Output Operation Table, SMODEA Input Status Output State SMODEA[1:0] REF_SEL[1:0] CLKx and nCLKx 11 Don’t care Don’t Care High Impedance 00, 01 or 10 10 or 11 Don’t Care Fanout crystal oscillator 00, 01 or 10 00, 01 or 10 QA[4:0], nQA[4:0] CLK0 and nCLK0 are both open circuit QA[4:0] = Low nQA4:0] = High CLK0 and nCLK0 are tied to ground QA[4:0] = Low nQA[4:0] = High CLK0 is high, nCLK0 is low QA[4:0] = High nQA[4:0] = Low CLK0 is low, nCLK0 is high QA[4:0] = Low nQA[4:0] = High CLK1 and nCLK1 are both open circuit QA[4:0] = Low nQA4:0] = High CLK1 and CLK1 are tied to ground. QA[4:0] = Low nQA[4:0] = High CLK1 is high, nCLK1 is low QA[4:0] = High nQA[4:0] = Low CLK1 is low, nCLK1 is high QA[4:0] = Low nQA4:0]=High 00 (default) 01 Table 3E. Input/Output Operation Table, SMODEB Input Status Output State SMODEB[1:0] REF_SEL[1:0] CLKx and nCLKx 11 Don’t care Don’t Care High Impedance 00, 01 or 10 10 or 11 Don’t Care Fanout crystal oscillator 00, 01 or 10 00, 01 or 10 QB[4:0], nQB[4:0] CLK0 and nCLK0 are both open circuit QB[4:0] = Low nQB4:0] = High CLK0 and nCLK0 are tied to ground QB[4:0] = Low nQB[4:0] = High CLK0 is high, nCLK0 is low QB[4:0] = High nQB[4:0] = Low CLK0 is low, nCLK0 is high QB[4:0] = Low nQB[4:0] = High CLK1 and nCLK1 are both open circuit QB[4:0] = Low nQB[4:0] = High CLK1 and nCLK1 are tied to ground QB[4:0] = Low nQB[4:0] = High CLK1 is high, nCLK1 is low QB[4:0] = High nQB[4:0] = Low CLK1 is low, nCLK1 is high QB[4:0] = Low nQB[4:0] = High 00 (default) 01 IDT8T39S10NLGI REVISION A MARCH 18. 2014 5 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Table 3F. Output Level Selection Table, QA[0:4], nQA[0:4] SMODEA1 SMODEA0 Output Type 0 0 LVPECL (default) 0 1 LVDS 1 0 HCSL 1 1 High-impedance Table 3G. Output Level Selection Table, QB[0:4], nQB[0:4] SMODEB1 SMODEB0 0 0 LVPECL (default) 0 1 LVDS 1 0 HCSL 1 1 High-impedance IDT8T39S10NLGI REVISION A MARCH 18. 2014 Output Type 6 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to 2V -0.5V to VDD + 0.5V Outputs, VO, (HCSL, LVCMOS) -0.5V to VDDO + 0.5V Outputs, IO, (LVPECL) Continuous Current Surge Current 50mA 100mA Outputs, IO, (LVDS) Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, qJA 30.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V±5%, GND = 0V, TA = -40°C to 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current SMODEA/B[1:0] = 01 61 75 mA IDDO Output Supply Current SMODEA/B[1:0] = 01 211 255 mA IEE Power Supply Current SMODEA/B[1:0] = 00 (default) 151 184 mA IDD Power Supply Current SMODEA/B[1:0] = 10 43 55 mA IDDO Power Supply Current SMODEA/B[1:0] = 10 25 35 mA NOTE: Characterized with all outputs unloaded. IDDO includes REFOUT. Table 4B. Power Supply DC Characteristics, VDD = 3.3V±5%, VDDO = 2.5V±5%, GND = 0V, TA = -40°C to 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current SMODEA/B[1:0] = 01 61 75 mA IDDO Output Supply Current SMODEA/B[1:0] = 01 210 255 mA IEE Power Supply Current SMODEA/B[1:0] = 00 (default) 147 184 mA IDD Power Supply Current SMODEA/B[1:0] = 10 43 55 mA IDDO Power Supply Current SMODEA/B[1:0] = 10 25 35 mA NOTE: Characterized with all outputs unloaded. IDDO includes REFOUT. IDT8T39S10NLGI REVISION A MARCH 18. 2014 7 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Table 4C. Power Supply DC Characteristics, VDD = 2.5V±5%, VDDO = 2.5V±5%, GND = 0V, TA = -40°C to 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Power Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current SMODEA/B[1:0] = 01 56 69 mA IDDO Output Supply Current SMODEA/B[1:0] = 01 202 245 mA IEE Power Supply Current SMODEA/B[1:0] = 00 (default) 141 173 mA IDD Power Supply Current SMODEA/B[1:0] = 10 40 50 mA IDDO Power Supply Current SMODEA/B[1:0] = 10 24 32 mA Typical Maximum Units NOTE: Characterized with all outputs unloaded. IDDO includes REFOUT. Table 4D. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V±5%, 2.5V±5%, VDDO = 3.3V±5% or 2.5V±5%, GND = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum VIH Input High Voltage VDD = 3.3V±5% 2 VDD + 0.3 V VDD = 2.5V±5% 1.7 VDD + 0.3 V VIL Input Low Voltage VDD = 3.3V±5% -0.3 0.8 V VDD = 2.5V±5% -0.3 0.7 V IIH Input High Current REF_SEL, SMODEA, SMODEB, OE_SE 150 µA IIL Input Low Current OE_SE VOH REFOUT Output High Voltage; NOTE 1 REFOUT VOL Output Low REFOUT Voltage; NOTE 1 VDDO = 3.3V±5% or 2.5V±5%: IOL = 8mA VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V -5 µA VDDO = 3.3V±5%: IOH = -8mA 2.6 V VDDO = 2.5V±5%: IOH = -8mA 1.8 V 0.5 V Maximum Units 150 µA Table 4E. Differential DC Characteristics, VDD = 3.3V±5% or 2.625V TA = -40°C to 85°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical CLK[0:1], nCLK[0:1] VDD = VIN = 3.465V or 2.625V CLK[0:1] VDD = 3.465V or 2.625V, VIN = 0V -5 µA nCLK[0:1] VDD = 3.465V or 2.625V, VIN = 0V -150 µA VPP Peak-to-Peak Input Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 0.240 1.3 V GND + 0.5 VDD – 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2. Common mode voltage is defined as the crosspoint. IDT8T39S10NLGI REVISION A MARCH 18. 2014 8 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Table 4F. LVPECL DC Characteristics, VDD = VDDO = 3.3V±5%, GND = 0V, TA = -40°C to 85°C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VDDO – 1.4 VDDO – 0.9 V VDDO – 2.0 VDDO – 1.7 V 0.6 1.0 V NOTE 1: Outputs terminated with 50 to VDDO – 2V. Table 4G. LVPECL DC Characteristics, VDD = 3.3V±5% or 2.625V, VDDO = 2.5V±5%, GND = 0V, TA = -40°C to 85°C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VDDO – 1.4 VDDO – 0.9 V VDDO – 2.0 VDDO – 1.7 V 0.4 1.0 V NOTE 1: Outputs terminated with 50 to VDDO – 2V. Table 4H. LVDS DC Characteristics, VDD = 3.3V±5% or 2.625V, VDDO = 2.5V±5%, GND = 0V, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 247 400 462 mV 50 mV 1.25 V 50 mV 1.00 1.16 Table 4I. LVDS DC Characteristics, VDD = VDDO = 2.5V±5%, GND = 0V, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 247 400 462 mV 50 mV 1.21 V 50 mV Maximum Units 40 MHz Equivalent Series Resistance (ESR) 50 Shunt Capacitance 7 pF 18 pF 1.00 1.12 . Table 5. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Fundamental Frequency 10 Capacitive Loading (CL) IDT8T39S10NLGI REVISION A MARCH 18. 2014 Typical 12 9 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER AC Electrical Characteristics Table 6A. AC Characteristics, VDD = VDDO = 3.3V±5%, TA = -40°C to 85°C Symbol fOUT tjit Parameter Output Frequency Maximum Units 40 MHz LVDS, LVPECL Outputs 2000 MHz HCSL Outputs 250 MHz LVCMOS Output 250 MHz Buffer Additive Phase Jitter, RMS: 156.25MHz Integration Range 12kHz - 20MHz REF_SEL[1:0] = 00 or 01 tjit(Ø) RMS Phase Jitter; 25MHz Integration Range: 100Hz - 1MHz tPD Propagation Delay; CLK0, nCLK0 or CLK1, nCLK1 to any Qx, nQx Outputs; NOTE 1 Test Conditions Minimum Using External Crystal 10 Typical SMODEA/B[1:0] = 00 0.153 0.200 ps SMODEA/B[1:0] = 01 0.163 0.200 ps SMODEA/B[1:0] = 10 0.198 0.250 ps REF_SEL[1:0] = 10 or 11 0.250 0.525 ps SMODEA/B[1:0] = 00 0.65 1.10 ns SMODEA/B[1:0] = 01 0.59 1.15 ns SMODEA/B[1:0] = 10 1.70 2.65 ns tsk(o) Output Skew; NOTE 2, 3 70 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 250 ps VRB Ring-back Voltage Margin; NOTE 5, 6 HCSL Outputs 100 mV VMAX Voltage High; NOTE 7, 8 HCSL Outputs HCSL Outputs 920 mV VMIN Voltage Low; NOTE 7, 9 HCSL Outputs HCSL Outputs -150 +150 mV VCROSS Absolute Crossing Voltage; NOTE 7, 10, 11 HCSL Outputs HCSL Outputs 250 520 mV VCROSS Total Variation of VCROSS over all edges; NOTE 7, 10, 12 HCSL Outputs HCSL Outputs 140 mV Rise/Fall Edge Rate; NOTE 13 HCSL Outputs Measured between 150mV to +150mV 0.6 4.0 V/ns SMODEA/B[1:0] = 00; 20% to 80% 60 200 310 ps SMODEA/B[1:0] = 01; 20% to 80% 40 170 300 ps tR / tF MUX_ISOLATION Output Rise/Fall Time MUX Isolation -100 156.25MHz 70 dB NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All LVDS and LVPECL parameters characterized up to 1.5GHz. HCSL parameters characterized up to 250MHz. NOTE 1: Measured from the differential input crosspoint to the differential output crosspoint. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoint. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoint. NOTE 5: Measurement taken from differential waveform. Notes continued on next page. IDT8T39S10NLGI REVISION A MARCH 18. 2014 10 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER NOTE 6: TSTABLE is the time the differential clock must maintain a minimum ± 150mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB ±100mV differential range. NOTE 7: Measurement taken from single-ended waveform. NOTE 8: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 9: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 10: Measured at crosspoint where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx. NOTE 11: Refers to the total variation from the lowest crosspoint to the highest, regardless of which edge is crossing. Refers to all crosspoint for this measurement. NOTE 12: Defined as the total variation of all crossing voltages of rising Qx and falling nQx, This is the maximum allowed variance in Vcross for any particular system. NOTE 13: Measured from -150mV to +150mV on the differential waveform (Qx minus nQx). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. Table 6B. AC Characteristics, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C to 85°C Symbol fOUT tjit Parameter Output Frequency Maximum Units 40 MHz LVDS, LVPECL Outputs 2000 MHz HCSL Outputs 250 MHz LVCMOS Output 250 MHz Additive Phase Jitter: 156.25MHz Integration Range: 12kHz - 20MHz REF_SEL[1:0] = 00 or 10 tjit(Ø) RMS Phase Jitter; 25MHz Integration Range: 100Hz - 1MHz tPD Propagation Delay; CLK0, nCLK0 or CLK1, nCLK1 to any Qx, nQx Outputs; NOTE 1 Test Conditions Minimum Using External Crystal 10 Typical SMODEA/B[1:0] = 00 0.181 0.235 ps SMODEA/B[1:0] = 01 0.181 0.235 ps SMODEA/B[1:0] = 10 0.200 0.250 ps REF_SEL[1:0] = 10 or 11 0.258 0.525 ps SMODEA/B[1:0] = 00 0.40 1.60 ns SMODEA/B[1:0] = 01 0.57 1.10 ns SMODEA/B[1:0] = 10 1.75 2.85 ns tsk(o) Output Skew; NOTE 2, 3 70 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 250 ps VRB Ring-back Voltage Margin; NOTE 5, 6 HCSL Outputs 100 mV VMAX Voltage High; NOTE 7, 8 HCSL Outputs 920 mV VMIN Voltage Low; NOTE 7, 9 HCSL Outputs -150 +150 mV VCROSS Absolute Crossing Voltage; NOTE 7, 10, 11 HCSL Outputs 250 520 mV VCROSS Total Variation of VCROSS over all edges; NOTE 7, 10, 12 HCSL Outputs 140 mV 4.0 V/ns Rise/Fall Edge Rate; NOTE 13 tR / tF MUX_ISOLATION Output Rise/Fall Time MUX Isolation HCSL Outputs -100 Measured between 150mV to +150mV 0.6 SMODEA/B[1:0] = 00; 20% to 80% 60 200 310 ps SMODEA/B[1:0] = 01; 20% to 80% 40 170 300 ps 156.25MHz 70 dB Notes continued on next page. IDT8T39S10NLGI REVISION A MARCH 18. 2014 11 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All LVDS and LVPECL parameters characterized up to 1.5GHz. HCSL parameters characterized up to 250MHz. NOTE 1: Measured from the differential input crosspoint to the differential output crosspoint. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoint. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoint. NOTE 5: Measurement taken from differential waveform. NOTE 6: TSTABLE is the time the differential clock must maintain a minimum ± 150mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB ±100mV differential range. NOTE 7: Measurement taken from single-ended waveform. NOTE 8: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 9: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 10: Measured at crosspoint where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx. NOTE 11: Refers to the total variation from the lowest crosspoint to the highest, regardless of which edge is crossing. Refers to all crosspoint for this measurement. NOTE 12: Defined as the total variation of all crossing voltages of rising Qx and falling nQx, This is the maximum allowed variance in Vcross for any particular system. NOTE 13: Measured from -150mV to +150mV on the differential waveform (Qx minus nQx). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. IDT8T39S10NLGI REVISION A MARCH 18. 2014 12 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Table 6C. AC Characteristics, VDD = VDDO = 2.5V±5%, TA = -40°C to 85°C Symbol fOUT tjit Parameter Output Frequency Maximum Units 40 MHz LVDS, LVPECL Outputs 2000 MHz HCSL Outputs 250 MHz LVCMOS Output 250 MHz Additive Phase Jitter:156.25MHz Integration Range 12kHz - 20MHz REF_SEL[1:0] = 00 or 01 tjit(Ø) RMS Phase Jitter; 25MHz Integration Range: 100Hz - 1MHz tPD Propagation Delay; CLK0, nCLK0 or CLK1, nCLK1 to any Qx, nQx Outputs; NOTE 1 Test Conditions Minimum Using External Crystal 10 Typical SMODEA/B[1:0] = 00 0.159 0.205 ps SMODEA/B[1:0] = 01 0.173 0.215 ps SMODEA/B[1:0] = 10 0.211 0.250 ps REF_SEL[1:0] = 10 or 11 0.254 0.510 ps SMODEA/B[1:0] = 00 0.68 1.15 ns SMODEA/B[1:0] = 01 0.56 1.15 ns SMODEA/B[1:0] = 10 1.79 2.90 ns tsk(o) Output Skew; NOTE 2, 3 70 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 250 ps VRB Ring-back Voltage Margin; NOTE 5, 6 HCSL Outputs 100 mV VMAX Voltage High; NOTE 7, 8 HCSL Outputs 920 mV VMIN Voltage Low; NOTE 7, 9 HCSL Outputs -150 +150 mV VCROSS Absolute Crossing Voltage; NOTE 7, 10, 11 HCSL Outputs 250 520 mV VCROSS Total Variation of VCROSS over all edges; NOTE 7, 10, 12 HCSL Outputs 140 mV Rise/Fall Edge Rate; NOTE 13 HCSL Outputs 4.0 V/ns tR / tF Output Rise/Fall Time -100 Measured between 150mV to +150mV 0.6 SMODEA/B[1:0] = 00; 20% to 80% 60 200 310 ps SMODEA/B[1:0] = 01; 20% to 80% 40 170 300 ps MUX_ISOLATION MUX Isolation 156.25MHz 70 dB NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All LVDS and LVPECL parameters characterized up to 1.5GHz. HCSL parameters characterized up to 250MHz. NOTE 1: Measured from the differential input crosspoint to the differential output crosspoint. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoint. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoint. NOTE 5: Measurement taken from differential waveform. NOTE 6: TSTABLE is the time the differential clock must maintain a minimum ± 150mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB ±100mV differential range. Notes continued on next page. IDT8T39S10NLGI REVISION A MARCH 18. 2014 13 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER NOTE 7: Measurement taken from single-ended waveform. NOTE 8: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 9: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 10: Measured at crosspoint where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx. NOTE 11: Refers to the total variation from the lowest crosspoint to the highest, regardless of which edge is crossing. Refers to all crosspoint for this measurement. NOTE 12: Defined as the total variation of all crossing voltages of rising Qx and falling nQx, This is the maximum allowed variance in Vcross for any particular system. NOTE 13: Measured from -150mV to +150mV on the differential waveform (Qx minus nQx). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing IDT8T39S10NLGI REVISION A MARCH 18. 2014 14 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Noise Power (dBc/Hz) Typical Phase Noise at 25MHz Offset Frequency (Hz) IDT8T39S10NLGI REVISION A MARCH 18. 2014 15 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Additive Phase Jitter (LVPECL, 3.3V) The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. SSB Phase Noise (dBc/Hz) Additive Phase Jitter @ 156.25MHz 12kHz to 20MHz = 0.153ps (typical) Offset from Carrier Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. The additive phase jitter is dependent on the input source and measurement equipment. IDT8T39S10NLGI REVISION A MARCH 18. 2014 The additive phase jitter for this device was measured using a Wenzel 156.25MHz oscillator as the input source and an Agilent E5052 Signal Source Analyzer. 16 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Additive Phase Jitter (LVDS, 3.3V) The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. SSB Phase Noise (dBc/Hz) Additive Phase Jitter @ 156.25MHz 12kHz to 20MHz = 0.163ps (typical) Offset from Carrier Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. The additive phase jitter is dependent on the input source and measurement equipment. IDT8T39S10NLGI REVISION A MARCH 18. 2014 The additive phase jitter for this device was measured using a Wenzel 156.25MHz oscillator as the input source and an Agilent E5052 Signal Source Analyzer. 17 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Additive Phase Jitter (HCSL, 3.3V) The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. SSB Phase Noise (dBc/Hz) Additive Phase Jitter @ 156.25MHz 12kHz to 20MHz = 0.198ps (typical) Offset from Carrier Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. The additive phase jitter is dependent on the input source and measurement equipment. IDT8T39S10NLGI REVISION A MARCH 18. 2014 The additive phase jitter for this device was measured using a Wenzel 156.25MHz oscillator as the input source and an Agilent E5052 Signal Source Analyzer. 18 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Parameter Measurement Information 3.3V±5% 3.3V±5% SCOPE SCOPE VDD, VDDO 50Ω 33Ω 49.9Ω 50Ω 33Ω GND VDD, VDDO 450Ω 2pF HCSL IREF Qx 49.9Ω nQx HCSL 450Ω IREF GND 2pF 475Ω 0V 0V This load condition is used for VMAX, VMIN, VRB, VCROSS and VCROSS measurements. 0V This load condition is used for tjit, tjit(Ø), tsk(o), tsk(pp) and tPD measurements. 3.3V Core/3.3V HCSL Output Load Test Circuit 3.3V Core/3.3V HCSL Output Load Test Circuit 3.3V±5% 3.3V±5% 2.5V±5% 2.5V±5% SCOPE SCOPE 50Ω 33Ω VDD VDDO 49.9Ω 50Ω 33Ω 450Ω VDDO 2pF HCSL IREF Qx 50Ω VDD nQx HCSL 50Ω 450Ω IREF GND 49.9Ω GND 2pF 475Ω 475Ω 0V 0V This load condition is used for VMAX, VMIN, VRB, VCROSS and VCROSS measurements. This load condition is used for tjit, tjit(Ø), tsk(o), tsk(pp) and tPD measurements. 3.3V Core/2.5V HCSL Output Load Test Circuit 3.3V Core/2.5V HCSL Output Load Test Circuit 2.5V±5% 2.5V±5% SCOPE SCOPE 50Ω 33Ω VDD, VDDO 49.9Ω IREF GND 450Ω 2pF HCSL 50Ω 33Ω Qx VDD, VDDO 49.9Ω 475Ω nQx HCSL 450Ω IREF GND 2pF 0V 0V This load condition is used for VMAX, VMIN, VRB, VCROSS and VCROSS measurements. 2.5V Core/2.5V HCSL Output Load Test Circuit IDT8T39S10NLGI REVISION A MARCH 18. 2014 0V This load condition is used for tjit, tjit(Ø), tsk(o), tsk(pp) and tPD measurements. 3.3V Core/2.5V HCSL Output Load Test Circuit 19 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Parameter Measurement Information, continued 2V 2V VDD, VDDO Qx SCOPE VDD, VDDO Qx nQx SCOPE nQx GND GND -0.5V±0.125V -1.3V+0.165V 2.5V Core/2.5V LVPECL Output Load Test Circuit 3.3V Core/3.3V LVPECL Output Load Test Circuit 2.8V±0.04V 2V VDD Qx SCOPE VDD, VDDO VDDO LVPECL GND nQx -0.5V±0.125V 3.3V Core/3.3V LVDS Output Load Test Circuit 3.3V Core/2.5V LVPECL Output Load Test Circuit 2.5V ±5% 3.3V ±5% VDD, VDDO VDD VDDO 2.5V Core/2.5V LVDS Output Load Test Circuit 3.3V Core/2.5V LVDS Output Load Test Circuit IDT8T39S10NLGI REVISION A MARCH 18. 2014 20 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Parameter Measurement Information, continued nQx nQXx Qx Par t 1 QXx nQy nQXy Qy Par t 2 QXy tsk(pp) Where X = Bank A or Bank B Part-to-Part Skew Output Skew VDD nCLK[0:1] CLK[0:1] nCLKx nQA[0:4], nQB[0:4] CLKx QA[0:4], QB[0:4] tPD GND Differential Input Levels Propagation Delay nQx nQx 80% 80% VOD Qx 20% 20% tR Qx tF LVPECL Output Rise/Fall Time LVDS Output Rise/Fall Time IDT8T39S10NLGI REVISION A MARCH 18. 2014 21 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Parameter Measurement Information, continued Differential Output Voltage Setup Offset Voltage Setup Spectrum of Output Signal Q MUX selects active input clock signal Amplitude (dB) A0 MUX_ISOL = A0 – A1 MUX selects static input A1 ƒ (fundamental) Frequency MUX Isolation RMS Phase Jitter Single-ended Measurement Points for Absolute Crosspoint/Swing Single-ended Measurement Points for Delta Crosspoint IDT8T39S10NLGI REVISION A MARCH 18. 2014 22 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Parameter Measurement Information, continued Differential Measurement Points for Rise/Fall Edge Rate IDT8T39S10NLGI REVISION A MARCH 18. 2014 Differential Measurement Points for Ringback 23 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Applications Information Recommendations for Unused Input and Output Pins Inputs: Outputs: CLK/nCLK Inputs LVCMOS Outputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. All unused LVCMOS output can be left floating We recommend that there is no trace attached. Differential Outputs Crystal Inputs All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. LVPECL Outputs All unused LVPECL output pairs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS Control Pins All control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVDS Outputs All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached. Crystal Input Interface The IDT8T39S10I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 1 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. In addition, the recommended 12pF parallel resonant crystal tuning is shown in Figure 2.The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_IN C1 15pF X1 18pF Parallel Crystal XTAL_OUT C2 15pF Figure 1. Crystal Input Interface XTAL_IN C1 3pF X1 12pF Parallel Crystal XTAL_OUT C2 3pF Figure 2. Crystal Input Interface IDT8T39S10NLGI REVISION A MARCH 18. 2014 24 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Overdriving the XTAL Interface The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 3A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This VCC can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 3B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. XTAL_OUT R1 100 Ro Rs C1 Zo = 50 ohms XTAL_IN R2 100 Zo = Ro + Rs .1uf LVCMOS Driver Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface XTAL_OUT C2 Zo = 50 ohms XTAL_IN .1uf Zo = 50 ohms LVPECL Driver R1 50 R2 50 R3 50 Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface IDT8T39S10NLGI REVISION A MARCH 18. 2014 25 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Wiring the Differential Input to Accept Single-Ended Levels Figure 4 shows how a differential input can be wired to accept single ended levels. The reference voltage V1= VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted to set V1 at 1.25V. The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 4. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels IDT8T39S10NLGI REVISION A MARCH 18. 2014 26 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER 3.3V Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, HCSL and other differential signals. Both differential signals must meet the VPP and VCMR input requirements. Figures 5A to 5D show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. 3.3V 3.3V 3.3V 3.3V 3.3V Zo = 50Ω CLK CLK Zo = 50Ω nCLK R1 50Ω Differential Input LVPECL Differential Input LVPECL nCLK R2 50Ω R2 50Ω Figure 5B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 5A. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V 3.3V Zo = 50Ω *R3 CLK CLK R1 100Ω nCLK HCSL *R4 Zo = 50Ω Differential Input LVDS Receiver Figure 5D. CLK/nCLK Input Driven by a 3.3V LVDS Driver Figure 5C. CLK/nCLK Input Driven by a 3.3V HCSL Driver IDT8T39S10NLGI REVISION A MARCH 18. 2014 nCLK 27 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER 2.5V Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, HCSL and other differential signals. Both differential signals must meet the VPP and VCMR input requirements. Figures 6A to 6D show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. 2.5V 2.5V 2.5V 2.5V 2.5V R3 250 R4 250 Zo = 50 CLK Zo = 50 CLK Zo = 50 nCLK Zo = 50 R1 50 Differential Input LVPECL R1 62.5 Differential Input LVPECL nCLK R2 62.5 R2 50 R3 18 Figure 6A. CLK/nCLK Input Driven by a 2.5V LVPECL Driver Figure 6B. CLK/nCLK Input Driven by a 2.5V LVPECL Driver 2.5V 2.5V 2.5V 2.5V Zo = 50 *R3 33 Zo = 50 CLK CLK R1 100 Zo = 50 LVDS Zo = 50 nCLK nCLK Differential Input HCSL *R4 33 R1 50 R2 50 Differential Input *Optional – R3 and R4 can be 0 Figure 6C. CLK/nCLK Input Driven by a 2.5V LVDS Driver IDT8T39S10NLGI REVISION A MARCH 18. 2014 Figure 6D. CLK/nCLK Input Driven by a 2.5V HCSL Driver 28 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as LVDS Driver shown in Figure 7A can be used with either type of output structure. Figure 7B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output. ZO ZT ZT LVDS Receiver Figure 7A. Standard Termination LVDS Driver ZO ZT C ZT 2 LVDS ZT Receiver 2 Figure 7B. Optional Termination LVDS Termination IDT8T39S10NLGI REVISION A MARCH 18. 2014 29 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 8A and 8B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 R3 125 3.3V R4 125 3.3V 3.3V Zo = 50 + _ LVPECL Input Zo = 50 R1 84 Figure 8A. 3.3V LVPECL Output Termination IDT8T39S10NLGI REVISION A MARCH 18. 2014 R2 84 Figure 8B. 3.3V LVPECL Output Termination 30 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Termination for 2.5V LVPECL Outputs level. The R3 in Figure 9B can be eliminated and the termination is shown in Figure 9C. Figure 9A and Figure 9B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VDDO – 2V. For VDDO = 2.5V, the VDDO – 2V is very close to ground 2.5V VDDO = 2.5V 2.5V 2.5V VDDO = 2.5V R1 250 R3 250 50Ω + 50Ω + 50Ω – 50Ω 2.5V LVPECL Driver – R1 50 2.5V LVPECL Driver R2 62.5 R2 50 R4 62.5 R3 18 Figure 9A. 2.5V LVPECL Driver Termination Example Figure 9B. 2.5V LVPECL Driver Termination Example 2.5V VDDO = 2.5V 50Ω + 50Ω – 2.5V LVPECL Driver R1 50 R2 50 Figure 9C. 2.5V LVPECL Driver Termination Example IDT8T39S10NLGI REVISION A MARCH 18. 2014 31 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Recommended Termination Figure 10A is the recommended source termination for applications where the driver and receiver will be on a separate PCBs. This termination is the standard for PCI Express™and HCSL output types. 0.5" Max Rs All traces should be 50 impedance single-ended or 100 differential. 0.5 - 3.5" 1-14" 0-0.2" 22 to 33 +/-5% L1 L2 L4 L1 L2 L4 L5 L5 PCI Expres s PCI Expres s Connector Driver 0-0.2" L3 L3 PCI Expres s Add-in Card 49.9 +/- 5% Rt Figure 10A. Recommended Source Termination (where the driver and receiver will be on separate PCBs) Figure 10B is the recommended termination for applications where a point-to-point connection can be used. A point-to-point connection contains both the driver and the receiver on the same PCB. With a matched termination at the receiver, transmission-line reflections will 0.5" Max Rs 0 to 33 L1 be minimized. In addition, a series resistor (Rs) at the driver offers flexibility and can help dampen unwanted reflections. The optional resistor can range from 0 to 33. All traces should be 50 impedance single-ended or 100 differential. 0-18" 0-0.2" L2 L3 L2 L3 0 to 33 L1 PCI Expres s Driver 49.9 +/- 5% Rt Figure 10B. Recommended Termination (where a point-to-point connection can be used) IDT8T39S10NLGI REVISION A MARCH 18. 2014 32 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 11. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Lead frame Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 11. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) IDT8T39S10NLGI REVISION A MARCH 18. 2014 33 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER LVPECL Power Considerations This section provides information on power dissipation and junction temperature for the IDT8T39S10I. Equations and example calculations are also provided. LVPECL Power Considerations 1. Power Dissipation. The total power dissipation for the IDT8T39S10I is the sum of the core power plus the power dissipated due to loading. The following is the power dissipation for VDD = 3.3V+5% = 3.465V, which gives worst case results. The Maximum current at 85°C is as follows IEE_MAX = 184mA NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading. • Power (core)MAX = IEE_MAX * VDD_MAX = 3.465V * 184mA = 637.56mW • Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 10 * 30mW = 300mW LVCMOS Output Power Dissipation • Output Impedance ROUT Power Dissipation due to loading 50 to VDDO/2 Output Current: IOUT = VDDO_MAX / [2 * (RLOAD + ROUT)] = 3.465V / [2 * (50 + 15 ] = 26.654mA • Power Dissipation on ROUT per LVCMOS output: Power (ROUT) = ROUT * IOUT2 = 15 * (26.654mA)2 = 10.656mW • Dynamic Power Dissipation at 250MHz, (REFOUT) • Power (250MHz) = CPD * Frequency * VDDO2 = 8pF * 250MHz * 3.465V2 = 24.012mW • Total Power (250MHz) = 24.012mW * 1 = 24.012mW Total Power_Max = 637.56mW + 300mW + 10.656mW + 24.012mW = 972.228mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 30.5°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.972W * 30.5°C/W = 114.66°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance JA for 48 Lead VQFN, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards IDT8T39S10NLGI REVISION A MARCH 18. 2014 0 1 2.5 30.5°C/W 26.7°C/W 23.9°C/W 34 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 12. VDDO Q1 VOUT RL 50Ω VDDO - 2V Figure 12. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VDDO – 2V. • For logic high, VOUT = VOH_MAX = VDDO_MAX – 0.9V (VDDO_MAX – VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VDDO_MAX – 1.7V (VDDO_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VDDO_MAX – 2V))/RL] * (VDDO_MAX – VOH_MAX) = [(2V – (VDDO_MAX – VOH_MAX))/RL] * (VDDO_MAX – VOH_MAX) = [(2V – 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VDDO_MAX – VOL_MAX) = [(2V – (VDDO_MAX – VOL_MAX))/RL] * (VDDO_MAX – VOL_MAX) = [(2V – 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT8T39S10NLGI REVISION A MARCH 18. 2014 35 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER HCSL Power Considerations This section provides information on power dissipation and junction temperature for the IDT8T39S10I. Equations and example calculations are also provided. HCSL Power Considerations 1. Power Dissipation. The total power dissipation for the IDT8T39S10I is the sum of the core power plus the power dissipated due to loading. The following is the power dissipation for VDD = 3.3V+5% = 3.465V, which gives worst case results. The Maximum current at 85°C is as follows IDD_MAX = 55mA IDDO_MAX = 35mA NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading. • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDO_MAX)= 3.465V * (55mA + 35mA) = 311.85mW • Power (outputs)MAX = 44.5mW/Loaded Output pair If all outputs are loaded, the total power is 10 * 44.5mW = 445mW • Dynamic Power Dissipation at 250MHz, (QAx/nQAx, QBx/nQBx) • Power (250MHz) = CPD * Frequency * VDDO2 = 3.5pF * 250MHz * 3.4652 = 10.51mW/differential output • Total Power (250MHz) = 10.51mW * 10 = 105.1mW LVCMOS Output Power Dissipation • Output Impedance ROUT Power Dissipation due to loading 50 to VDDO/2 Output Current: IOUT = VDDO_MAX / [2 * (RLOAD + ROUT)] = 3.465V / [2 * (50 + 15 ] = 26.654mA • Power Dissipation on ROUT per LVCMOS output: Power (ROUT) = ROUT * IOUT2 = 15 * (26.654mA)2 = 10.656mW • Dynamic Power Dissipation at 250MHz, (REFOUT) • Power (250MHz) = CPD * Frequency * VDDO2 = 8pF * 250MHz * 3.465V2 = 24.012mW • Total Power (250MHz) = 24.012mW * 1 = 24.012mW • Total Power_Max = 311.85mW + 445mW + 105.1mW + 10.656mW + 24.012mW = 896.62mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 30.5°C/W per Table 8 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.897W * 30.5°C/W = 112.4°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). IDT8T39S10NLGI REVISION A MARCH 18. 2014 36 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Table 8. Thermal Resistance JA for 48 Lead VQFN, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards IDT8T39S10NLGI REVISION A MARCH 18. 2014 0 1 2.5 30.5°C/W 26.7°C/W 23.9°C/W 37 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 13. VDDO IOUT = 17mA ➤ VOUT RREF = 475Ω ± 1% RL 50Ω IC Figure 13. HCSL Driver Circuit and Termination HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation, use the following equations which assume a 50 load to ground. The highest power dissipation occurs when VDDO_MAX. Power= (VDDO_MAX – VOUT) * IOUT, since VOUT – IOUT * RL = (VDDO_MAX – IOUT * RL) * IOUT = (3.465V – 17mA * 50) * 17mA Total Power Dissipation per output pair = 44.5mW IDT8T39S10NLGI REVISION A MARCH 18. 2014 38 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER LVDS Power Considerations This section provides information on power dissipation and junction temperature for the IDT8T39S10I. Equations and example calculations are also provided. LVDS Power Considerations 1. Power Dissipation. The total power dissipation for the IDT8T39S10I is the sum of the core power plus the power dissipated due to loading. The following is the power dissipation for VDD = 3.3V+5% = 3.465V, which gives worst case results. The Maximum current at 85°C is as follows IDD_MAX = 75mA IDDO_MAX = 255mA Power (core) Max = VDD_MAX *(IDD_MAX + IDDO_MAX) = 3.465V * (75mA + 255mA) = 1143.45mW LVCMOS Output Power Dissipation • Output Impedance ROUT Power Dissipation due to loading 50 to VDDO/2 Output Current: IOUT = VDDO_MAX / [2 * (RLOAD + ROUT)] = 3.465V / [2 * (50 + 15 ] = 26.654mA • Power Dissipation on ROUT per LVCMOS output: Power (ROUT) = ROUT * IOUT2 = 15 * (26.654mA)2 = 10.656mW • Dynamic Power Dissipation at 250MHz, (REFOUT) • Power (250MHz) = CPD * Frequency * VDDO2 = 8pF * 250MHz * 3.465V2 = 24.012mW • Total Power (250MHz) = 24.012mW * 1 = 24.012mW • Total Power_Max = 1143.45mW + 10.656mW + 24.012mW = 1178.118mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 30.5°C/W per Table 9 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 1.178W * 30.5°C/W = 121°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 9. Thermal Resistance JA for 48 Lead VQFN, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards IDT8T39S10NLGI REVISION A MARCH 18. 2014 0 1 2.5 30.5°C/W 26.7°C/W 23.9°C/W 39 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Reliability Information Table 10. JA vs. Air Flow Table for a 48 Lead VFQFN JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 30.5°C/W 26.7°C/W 23.9°C/W Transistor Count The transistor count for IDT8T39S10I is: 9427 IDT8T39S10NLGI REVISION A MARCH 18. 2014 40 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER 48-Lead VFQFN Package Outline and Package Dimensions IDT8T39S10NLGI REVISION A MARCH 18. 2014 41 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Ordering Information Table 11. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 8T39S10NLGI IDT8T39S10NLGI Lead-Free, 48 Lead VFQFN Tray -40°C to 85°C 8T39S10NLGI8 IDT8T39S10NLGI Lead-Free, 48 Lead VFQFN Tape & Reel -40°C to 85°C IDT8T39S10NLGI REVISION A MARCH 18. 2014 42 ©2013 Integrated Device Technology, Inc. IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL TO DIFFERENTIAL CLOCK FANOUT BUFFER We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support Sales [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. 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