16 V Rail-to-Rail, Zero-Drift, Precision Instrumentation Amplifier AD8230 CONNECTION DIAGRAM Resistor programmable gain range: 10 1 to 1000 Supply voltage range: ±4 V to ±8 V Rail-to-rail input and output Maintains performance over −40°C to +125°C Excellent ac and dc performance 110 dB minimum CMR @ 60 Hz, G = 10 to 1000 10 μV maximum offset voltage (RTI, ±5 V operation) 50 nV/°C maximum offset drift 20 ppm maximum gain nonlinearity –VS 1 8 VOUT +VS 2 7 RG VREF 1 3 +IN 4 6 VREF 2 5 –IN AD8230 05063-041 FEATURES TOP VIEW (Not to Scale) Figure 1. 8-Lead SOIC (R-8) 2.0 1.5 OFFSET VOLTAGE (µV RTI) APPLICATIONS Pressure measurements Temperature measurements Strain measurements Automotive diagnostics GENERAL DESCRIPTION 0.5 0 –0.5 –1.0 –2.0 –50 05063-001 –1.5 The AD8230 is a low drift, differential sampling, precision instrumentation amplifier. Auto-zeroing reduces offset voltage drift to less than 50 nV/°C. The AD8230 is well-suited for thermocouple and bridge transducer applications. The AD8230’s high CMR of 110 dB (minimum) rejects line noise in measurements where the sensor is far from the instrumentation. The 16 V rail-to-rail, common-mode input range is useful for noisy environments where ground potentials vary by several volts. Low frequency noise is kept to a minimal 3 μV p-p, making the AD8230 perfect for applications requiring the utmost dc precision. Moreover, the AD8230 maintains its high performance over the extended industrial temperature range of −40°C to +125°C. –30 –10 10 30 50 70 90 110 130 150 TEMPERATURE (°C) Figure 2. Relative Offset Voltage vs. Temperature +5V –5V 0.1µF 0.1µF 2 4 1 AD8230 TYPE K THERMOCOUPLE 8 VOUT 7 5 3 6 34.8kΩ 284Ω 05063-002 Two external resistors are used to program the gain. By using matched external resistors, the gain stability of the AD8230 is much higher than instrumentation amplifiers that use a single resistor to set the gain. In addition to allowing users to program the gain between 101 and 1000, users can adjust the output offset voltage. 1.0 Figure 3. Thermocouple Measurement The AD8230 is versatile yet simple to use. Its auto-zeroing topology significantly minimizes the input and output transients typical of commutating or chopper instrumentation amplifiers. The AD8230 operates on ±4 V to ±8 V (+8 V to +16 V) supplies and is available in an 8-lead SOIC. 1 The AD8230 can be programmed for a gain as low as 2, but the maximum input voltage is limited to approximately 750 mV. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2004–2007 Analog Devices, Inc. All rights reserved. AD8230* Product Page Quick Links Last Content Update: 11/01/2016 Comparable Parts Design Resources View a parametric search of comparable parts • • • • Documentation Application Notes • AN-282: Fundamentals of Sampled Data Systems • AN-671: Reducing RFI Rectification Errors in In-Amp Circuits Data Sheet • AD8230: 16 V Rail-to-Rail, Zero-Drift, Precision Instrumentation Amplifier Data Sheet Technical Books • A Designer's Guide to Instrumentation Amplifiers, 3rd Edition, 2006 Reference Materials AD8230 Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints Discussions View all AD8230 EngineerZone Discussions Sample and Buy Visit the product page to see pricing options Technical Support Submit a technical question or find your regional support number Technical Articles • Auto-Zero Amplifiers • High-performance Adder Uses Instrumentation Amplifiers • Input Filter Prevents Instrumentation-amp RF-Rectification Errors • The AD8221 - Setting a New Industry Standard for Instrumentation Amplifiers * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. 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AD8230 TABLE OF CONTENTS Features .............................................................................................. 1 Level-Shifting the Output ......................................................... 12 Applications....................................................................................... 1 Source Impedance and Input Settling Time ........................... 12 General Description ......................................................................... 1 Input Voltage Range................................................................... 13 Connection Diagram ....................................................................... 1 Input Protection ......................................................................... 13 Revision History ............................................................................... 2 Power Supply Bypassing ............................................................ 13 Specifications..................................................................................... 3 Power Supply Bypassing for Multiple Channel Systems ....... 13 Absolute Maximum Ratings............................................................ 5 Layout .......................................................................................... 14 Thermal Characteristics .............................................................. 5 Applications ................................................................................ 14 ESD Caution.................................................................................. 5 Outline Dimensions ....................................................................... 15 Typical Performance Characteristics ............................................. 6 Ordering Guide .......................................................................... 15 Theory of Operation ...................................................................... 11 Setting the Gain .......................................................................... 11 REVISION HISTORY 9/07—Rev. A to Rev. B Changes to Features and Layout..................................................... 1 Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 4 Changes to Layout ............................................................................ 5 Inserted Figure 13, Figure 14, and Figure 15; Renumbered Sequentially ....................................................................................... 7 Changes to Figure 16 and Figure 19............................................... 8 Updated Outline Dimensions ....................................................... 15 7/05—Rev. 0 to Rev. A Changes to Excellent AC and DC Performance............................1 Changes to Table 1.............................................................................3 Changes to Table 2.............................................................................4 Changes to Figure 7 and Figure 8....................................................6 Changes to Figure 10 and Figure 11................................................7 Changes to Level-Shifting the Output Section ........................... 11 Changes to Figure 31...................................................................... 11 Inserted Figure 32 and Figure 33; Renumbered Sequentially .. 11 Changes to Source Impedance and Input Settling Time Section, Input Protection Section and Power Supply Bypassing for Multiple Channel Systems Section............................................... 12 Changes to Figure 36...................................................................... 13 Changes to Applications Section.................................................. 13 10/04—Revision 0: Initial Version Rev. B | Page 2 of 16 AD8230 SPECIFICATIONS VS = ±5 V, VREF = 0 V, RF = 100 kΩ, RG = 1 kΩ (@ TA = 25°C, G = 202, RL = 10 kΩ, unless otherwise noted). Table 1. Parameter VOLTAGE OFFSET RTI Offset, VOSI Offset Drift COMMON-MODE REJECTION (CMR) CMR to 60 Hz with 1 kΩ Source Imbalance VOLTAGE OFFSET RTI vs. SUPPLY (PSR) G=2 G = 202 GAIN Gain Range Gain Error 2 G=2 G = 10 G = 100 G = 1000 Gain Nonlinearity Gain Drift G = 2, 10, 102 G = 1002 INPUT Input Common-Mode Operating Voltage Range Over Temperature Input Differential Operating Voltage Range Average Input Offset Current 3 Average Input Bias Current3 OUTPUT Output Swing Over Temperature Short-Circuit Current REFERENCE INPUT Voltage Range 4 NOISE Voltage Noise Density, 1 kHz, RTI Voltage Noise SLEW RATE INTERNAL SAMPLE RATE POWER SUPPLY Operating Range (Dual Supplies) Operating Range (Single Supply) Quiescent Current TEMPERATURE RANGE Specified Performance Conditions Min Typ V+IN = V−IN = 0 V V+IN = V−IN = 0 V, TA = −40°C to +125°C VCM = −5 V to +5 V Max Unit 10 50 μV nV/°C 110 120 dB 120 120 120 140 dB dB G = 2(1 + RF/RG) 10 1 0.01 0.01 0.01 0.02 T = −40°C to +125°C −VS −VS 750 33 0.15 VCM = 0 V VCM = 0 V T = −40°C to +125°C −VS + 0.1 −VS + 0.1 1000 V/V 0.04 0.04 0.04 0.05 20 % % % % ppm 14 60 ppm/°C ppm/°C +VS +VS V V mV pA nA 300 1 +VS − 0.2 +VS − 0.2 V V mA +VS − 2.5 V 15 −VS + 3.5 VIN+, VIN−, VREF = 0 V f = 0.1 Hz to 10 Hz VIN = 500 mV, G = 10 240 3 2 6 ±4 8 T = −40°C to +125°C 2.7 −40 1 nV/√Hz μV p-p V/μs kHz ±8 16 3.5 V V mA +125 °C The AD8230 can operate as low as G = 2. However, since the differential input range is limited to approximately 750 mV, the AD8230 configured at G < 10 does not make use of the full output voltage range. 2 Gain drift is determined by the TC match of the external gain setting resistors. 3 Differential source resistance less than 10 kΩ does not result in voltage offset due to input bias current or mismatched series resistors. 4 For G < 10, the reference voltage range is limited to −VS + 4.24 V to +VS – 2.75 V. Rev. B | Page 3 of 16 AD8230 VS = ±8 V, VREF = 0 V, RF = 100 kΩ, RG = 1 kΩ (@ TA = 25°C, G = 202, RL = 10 kΩ, unless otherwise noted). Table 2. Parameter VOLTAGE OFFSET RTI Offset, VOSI Offset Drift COMMON-MODE REJECTION (CMR) CMR to 60 Hz with 1 kΩ Source Imbalance VOLTAGE OFFSET RTI vs. SUPPLY (PSR) G=2 G = 202 GAIN Gain Range Gain Error 2 G=2 G = 10 G = 100 G = 1000 Gain Nonlinearity Gain Drift G = 2, 10, 102 G=1002 INPUT Input Common-Mode Operating Voltage Range Over Temperature Input Differential Operating Voltage Range Average Input Offset Current 3 Average Input Bias Current3 OUTPUT Output Swing Over Temperature Short-Circuit Current REFERENCE INPUT Voltage Range 4 NOISE Voltage Noise Density, 1 kHz, RTI Voltage Noise SLEW RATE INTERNAL SAMPLE RATE POWER SUPPLY Operating Range (Dual Supplies) Operating Range (Single Supply) Quiescent Current TEMPERATURE RANGE Specified Performance Conditions Min Typ V+IN = V−IN = 0 V V+IN = V−IN = 0 V, T = −40°C to +125°C VCM = −8 V to +8 V Max Unit 20 50 μV nV/°C 110 120 dB 120 120 120 140 dB dB G = 2(1 + RF/RG) 10 1 0.01 0.01 0.01 0.02 T = −40°C to +125°C −VS −VS 750 33 0.15 VCM = 0 V VCM = 0 V T = −40°C to +125°C −VS + 0.1 −VS + 0.1 1000 V/V 0.04 0.04 0.04 0.05 20 % % % % ppm 14 60 ppm/°C ppm/°C +VS +VS V V mV pA nA 300 1 +VS − 0.2 +VS − 0.4 V V mA +VS − 2.5 V 15 −VS + 3.5 VIN+, VIN−, VREF = 0 V f = 0.1 Hz to 10 Hz VIN = 500 mV, G = 10 240 3 2 6 ±4 8 T = −40°C to +125°C 3.2 −40 1 nV/√Hz μV p-p V/μs kHz ±8 16 4 V V mA +125 °C The AD8230 can operate as low as G = 2. However, since the differential input range is limited to approximately 750 mV, the AD8230 configured at G < 10 does not make use of the full output voltage range. 2 Gain drift is determined by the TC match of the external gain setting resistors. 3 Differential source resistance less than 10 kΩ does not result in voltage offset due to input bias current or mismatched series resistors. 4 For G < 10, the reference voltage range is limited to −VS + 4.24 V to +VS − 2.75V. Rev. B | Page 4 of 16 AD8230 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 3. Parameter Supply Voltage Internal Power Dissipation Output Short-Circuit Current Input Voltage (Common-Mode) Differential Input Voltage Storage Temperature Range Operational Temperature Range Specification is for device in free air SOIC. Rating ±8 V, +16 V 304 mW 20 mA ±VS ±VS −65°C to +150°C −40°C to +125°C Table 4. Parameter θJA (4-Layer JEDEC Board) ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 5 of 16 Value 121 Unit °C/W AD8230 TYPICAL PERFORMANCE CHARACTERISTICS 20 TOTAL NUMBER OF SAMPLES = 2839 FROM 3 LOTS NORMALIZED FOR VCM = 0V 500 OFFSET VOLTAGE (µV RTI) 15 SAMPLES 400 300 200 10 5 0 –5 –10 05063-004 100 –9 –6 –3 0 3 6 05063-007 0 –15 –20 9 –6 –4 OFFSET VOLTAGE (µV RTI) Figure 4. Offset Voltage (RTI) Distribution at ±5 V, CM = 0 V, TA = 25°C 40 0 2 4 6 Figure 7. Offset Voltage (RTI) vs. Common-Mode Voltage, VS = ±5 V 20 TOTAL NUMBER OF SAMPLES = 300 FROM 3 LOTS NORMALIZED FOR VCM = 0V 35 15 OFFSET VOLTAGE (µV RTI) 30 25 20 15 10 05063-005 5 0 –50 –30 –10 10 30 10 5 0 –5 –10 –15 –20 –10 50 05063-008 SAMPLES –2 COMMON-MODE VOLTAGE (V) –8 –6 OFFSET VOLTAGE DRIFT (nV/°C) –4 –2 0 2 4 6 8 10 COMMON-MODE VOLTAGE (V) Figure 5. Offset Voltage (RTI) Drift Distribution Figure 8. Offset Voltage (RTI) vs. Common-Mode Voltage, VS = ±8 V 0 0 –2 –1 –8 –10 VS = ±8V –12 –14 –16 –18 –20 –50 –30 –10 10 30 50 70 90 110 130 –3 –4 –5 ±5V SUPPLY –6 –7 ±8V SUPPLY –8 150 0 TEMPERATURE (°C) Figure 6. Offset Voltage (RTI) vs. Temperature –2 05063-009 OFFSET VOLTAGE (µV) VS = ±5V –6 05063-006 OFFSET VOLTAGE (µV RTI) –4 1 2 3 4 5 6 SOURCE IMPEDANCE (kΩ) Figure 9. Offset Voltage (RTI) vs. Source Impedance, 1 μF Across Input Pins Rev. B | Page 6 of 16 AD8230 10 INPUT COMMON-MODE VOLTAGE RANGE (V) NORMALIZED FOR VREF = 0V 20 10 0 –10 –20 –1.0 –0.5 0 0.5 1.0 1.5 0V, +8.4V 6 4 –812mV, +5V VS = ±5V 0 –2 –4 –652mV, –5V –6 –8 –616mV, –8.2V 0V, –8.4V –10 0 200 –1000 –800 –600 –400 –200 10 INPUT COMMON-MODE VOLTAGE RANGE (V) CMR WITH NO SOURCE IMBALANCE 120 110 CMR (dB) 100 90 80 CMR WITH 1kΩ SOURCE IMBALANCE 60 05063-011 50 40 100 1k 10k VS = ±8V –7.9V, +8V 6 –4.9V, +5V 4 INPUT COMMON-MODE VOLTAGE RANGE (V) 126 124 122 ±5V SUPPLY 118 ±8V SUPPLY 05063-012 114 112 110 4 6 +7.9V, +8V +4.88V, +5V VS = ±5V 2 0 –2 –4 –6 –4.9V, –5V –8 –7.9V, –8V –10 –10 –8 –6 10 128 2 1000 +4.88V, –5V +7.9V, –8V –4 –2 0 2 4 6 8 10 Figure 14. Input Common-Mode Voltage Range vs. Output Voltage, G = 10 130 0 800 OUTPUT VOLTAGE (V) Figure 11. Common-Mode Rejection (CMR) vs. Frequency 116 600 8 FREQUENCY (Hz) 120 +840mV, –8.2V 400 Figure 13. Input Common-Mode Voltage Range vs. Output Voltage, G = 2 130 10 +800mV, –5V 0V, –5.5V OUTPUT VOLTAGE (mV) Figure 10. Offset Voltage (RTI) vs. Reference Voltage CMR (dB) 0V, +5.5V +644mV, +5V 2 VREF (V) 70 +592mV, +8.2V VS = ±8V 05063-014 –40 –1.5 05063-010 –30 –856mV, +8.2V 8 8 10 12 +7.9V, +8V VS = ±8V 6 4 –4.8V, +5.5V +4.8V, +5.5V 2 VS = ±5V 0 –2 –4 –4.8V, –5.5V +4.8V, –5.5V –6 –8 –7.9V, –8V –10 –10 –8 –6 +7.9V, –8V –4 –2 0 2 4 6 8 10 OUTPUT VOLTAGE (V) SOURCE IMPEDANCE (kΩ) Figure 12. Common-Mode Rejection (CMR) vs. Source Impedance, 1.1 μF Across Input Pins –7.9V, +8V 8 05063-015 OFFSET VOLTAGE (µV RTI) 30 05063-013 40 Figure 15. Input Common-Mode Voltage Range vs. Output Voltage, G = 100 Rev. B | Page 7 of 16 AD8230 90 6.8 80 6.6 6.4 60 ±8V GAIN (dB) CLOCK FREQUENCY (kHz) 70 6.2 6.0 ±5V 5.8 50 40 30 20 05063-016 5.4 –50 –30 –10 10 30 50 70 90 110 05063-019 10 5.6 0 –10 10 130 100 1k TEMPERATURE (°C) Figure 16. Clock Frequency vs. Temperature 90 +85°C 80 +125°C 0.6 70 –40°C 0.4 60 GAIN (dB) 0.2 0 –0.2 50 40 30 20 0°C –0.6 +25°C –0.8 –1.0 –6 –4 –2 0 2 4 05063-020 10 05063-017 AVERAGE INPUT BIAS CURRENT (µA) 0.8 0 –10 6 10 100 1k COMMON-MODE VOLTAGE (V) 10k 100k FREQUENCY (Hz) Figure 17. Average Input Bias Current vs. Common-Mode Voltage, −40°C, +25°C, +85°C, +125°C Figure 20. Gain vs. Frequency, G = 10 40 3.5 G = +20 3.4 30 ±8V 3.3 20 NONLINEARITY (ppm) 3.2 3.1 3.0 ±5V 2.9 2.8 10 0 –10 –20 2.7 0 50 100 –40 150 05063-021 2.6 2.5 –50 –30 05063-018 SUPPLY CURRENT (mA) 100k Figure 19. Gain vs. Frequency, G = 2 1.0 –0.4 10k FREQUENCY (Hz) –5 –4 –3 –2 –1 0 1 2 VOUT (V) TEMPERATURE (°C) Figure 18. Supply Current vs. Temperature Figure 21. Gain Nonlinearity, G = 20 Rev. B | Page 8 of 16 3 4 5 AD8230 90 0.35 80 0.30 VOLTAGE NOISE (µV/ Hz) 70 50 40 30 20 10 –10 10 100 1k 10k 0.20 0.15 0.10 0.05 05063-022 0 0.25 0 100k 05063-025 GAIN (dB) 60 1 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 22. Gain vs. Frequency, G = 100 Figure 25. Voltage Noise Spectral Density vs. Frequency 90 3.90 70 GAIN (dB) 60 50 40 30 20 05063-023 10 0 –10 10 100 1k 10k 3.70 3.50 3.30 3.10 2.90 2.70 2.50 2µV/DIV –50 –30 100k FREQUENCY (Hz) 05063-026 POSITIVE SUPPLY CURRENT (mA) 80 –10 10 30 50 70 Figure 23. Gain vs. Frequency, G = 1000 1s/DIV 110 130 Figure 26. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 100 0.010 160 0.008 140 0.006 G = +1000 120 0.004 100 PSR (dB) 0.002 0 –0.002 G = +100 G = +10 80 G = +2 60 –0.004 40 –0.006 –0.008 –0.010 0 5 10 15 0 0.1 20 SOURCE IMPEDANCE (kΩ) 05063-027 20 05063-024 GAIN ERROR (%) 90 TEMPERATURE (°C) 1 FREQUENCY (kHz) Figure 24. Gain Error vs. Differential Source Impedance Figure 27. Positive PSR vs. Frequency, RTI Rev. B | Page 9 of 16 10 AD8230 140 G = +10 60 G = +2 40 20 0 0.1 05063-028 PSR (dB) G = +1000 1 –40 °C 6 –40°C 4 +125 °C +25°C VS = ±5V 2 +125°C +25°C 0 –2 –40 °C –6 –8 +25°C +125°C VS = ±5V –4 +25°C +125 °C VS = ±8V –40 °C –10 10 0 FREQUENCY (kHz) 05063-029 G = +100 100 80 VS = ±8V 8 OUTPUT VOLTAGE SWING (V) 120 10 2 4 6 8 10 OUTPUT CURRENT (mA) Figure 28. Negative PSR vs. Frequency, RTI Figure 29. Output Voltage Swing vs. Output Current, −40°C, +25°C, +85°C, +125°C Rev. B | Page 10 of 16 12 AD8230 THEORY OF OPERATION Auto-zeroing is a dynamic offset and drift cancellation technique that reduces input-referred voltage offset to the μV level and voltage offset drift to the nV/°C level. A further advantage of dynamic offset cancellation is the reduction of low frequency noise, in particular the 1/f component. The AD8230 is an instrumentation amplifier that uses an auto-zeroing topology and combines it with high commonmode signal rejection. The internal signal path consists of an active differential sample-and-hold stage (preamp) followed by a differential amplifier (gain amp). Both amplifiers implement auto-zeroing to minimize offset and drift. A fully differential topology increases the immunity of the signals to parasitic noise and temperature effects. Amplifier gain is set by two external resistors for convenient TC matching. In Phase B, the differential signal is transferred to the hold capacitors refreshing the value stored on CHOLD. The output of the preamplifier is held at a common-mode voltage determined by the reference potential, VREF. In this manner, the AD8230 is able to condition the difference signal and set the output voltage level. The gain amplifier conditions the updated signal stored on the hold capacitors, CHOLD. SETTING THE GAIN Two external resistors set the gain of the AD8230. The gain is expressed in the following equation: Gain = 2(1 + RF ) RG +VS –VS The signal sampling rate is controlled by an on-chip, 6 kHz oscillator and logic to derive the required nonoverlapping clock phases. For simplification of the functional description, two sequential clock phases, A and B, are shown to distinguish the order of internal operation, as depicted in Figure 30 and Figure 31, respectively. 0.1µF 10µF 0.1µF AD8230 CSAMPLE V–IN VREF 1 6 RF 3 RG 05063-032 + – – + VOUT Figure 32. Gain Setting CHOLD Table 5. Gains Using Standard 1% Resistors VREF RG RF 05063-030 –VS Figure 30. Phase A of the Sampling Phase During Phase A, the sampling capacitors are connected to the inputs. The input signal’s difference voltage, VDIFF, is stored across the sampling capacitors, CSAMPLE. Because the sampling capacitors only retain the difference voltage, the common-mode voltage is rejected. During this period, the gain amplifier is not connected to the preamplifier so its output remains at the level set by the previously sampled input signal held on CHOLD, as shown in Figure 30. GAIN AMP PREAMP –VS Gain 2 10 50 100 200 500 1000 CSAMPLE + – – + CHOLD RG Figure 31. Phase B of the Sampling Phase RF 05063-031 VREF RL||(RF + RG) > 2 kΩ VOUT –VS RF 0 Ω (short) 8.06 kΩ 12.1 kΩ 9.76 kΩ 10 kΩ 49.9 kΩ 100 kΩ RG None 2 kΩ 499 Ω 200 Ω 100 Ω 200 Ω 200 Ω Actual Gain 2 10 50.5 99.6 202 501 1002 Figure 32 and Table 5 provide an example of some gain settings. As Table 5 shows, the AD8230 accepts a wide range of resistor values. Because the instrumentation amplifier has finite driving capability, ensure that the output load in parallel with the sum of the gain setting resistors is greater than 2 kΩ. CHOLD V+IN V–IN VOUT 8 CHOLD V+IN VDIFF +VCM 1 RG VREF 2 7 5 –VS VDIFF +VCM 10µF 2 4 GAIN AMP PREAMP (1) (2) Offset voltage drift at high temperature can be minimized by keeping the value of the feedback resistor, RF, small. This is due to the junction leakage current on the RG pin, Pin 7. The effect of the gain setting resistor on offset voltage drift is shown in Figure 33. In addition, experience has shown that wire-wound resistors in the gain feedback loop may degrade the offset voltage performance. Rev. B | Page 11 of 16 0 The following steps can be taken to set the gain and level-shift the output: –1 1. Select an RF value. Table 5 shows RF values for various gains. 2. Solve for RO using Equation 4. –2 RO = − –3 RF = 100kΩ, RG = 1kΩ –4 RF = 10kΩ, RG = 100Ω 0 50 TEMPERATURE (°C) 100 (4) 3. Solve for RG. 150 RG = Figure 33. Effect of Feedback Resistor on Offset Voltage Drift RO ⎛ Gain − 1⎞ RO − 1 ⎜ ⎟ ⎝ 2 ⎠ RF LEVEL-SHIFTING THE OUTPUT (5) +VS –VS A reference voltage, as shown in Figure 34, can be used to level-shift the output. The reference voltage, VR, is limited to −VS + 3.5 V to +VS − 2.5 V. (For G < 10, the reference voltage range is limited to −VS + 4.24 V to +VS – 2.75 V.) Otherwise, it is nominally tied to midsupply. The voltage source used to levelshift the output should have a low output impedance to avoid contributing to gain error. In addition, it should be able to source and sink current. To minimize offset voltage, the VREF pins should be connected either to the local ground or to a reference voltage source that is connected to the local ground. 0.1µF 0.1µF 2 4 1 AD8230 VOUT 8 7 5 RF 6 3 RG RO 05063-035 –5 –50 VR' × RF VDESIRED −LEVEL where: VR’ is a voltage source, such as a supply voltage. VDESIRED-LEVEL is the desired output bias voltage. 05063-033 OFFSET VOLTAGE (µV RTI) AD8230 VR' +VS Figure 35. Level-Shifting the Output Without an Additional Voltage Reference –VS 0.1µF +5V 0.1µF –5V 2 4 0.1µF 1 AD8230 8 0.1µF VOUT 7 5 2 6 4 RF 3 1 AD8230 RG VOUT 8 7 5 9.76kΩ 6 203Ω Figure 34. Level-Shifting the Output +5V The output can also be level-shifted by adding a resistor, RO, as shown in Figure 35. The benefit is that the output can be levelshifted to as low as 100 mV of the negative supply rail and to as high as 200 mV of the positive supply rail, increasing unipolar output swing. This can be useful in applications, such as strain gauges, where the force is only applied in one direction. Another benefit of this configuration is that a supply rail can be used for VR’ eliminating the need to add an additional external reference voltage. The gain changes with the inclusion of RO. The full expression is ⎛ RF ⎞ ⎛ R (R + RO ) ⎞ R R VOUT = 2⎜⎜ + 1⎟⎟VIN − F VR' = 2⎜⎜ F G + 1⎟⎟VIN − F VR' R || R R R R R O O G O O ⎝ G ⎠ ⎝ ⎠ 10.2kΩ (3) 05063-036 VR 05063-034 3 Figure 36. An AD8230 with its Output Biased at −4.8 V; G = 100; VDESIRED-LEVEL = −4.8 V SOURCE IMPEDANCE AND INPUT SETTLING TIME The input stage of the AD8230 consists of two actively driven, differential switched capacitors, as described in Figure 30 and Figure 31. Differential input signals are sampled on CSAMPLE such that the associated parasitic capacitances, 70 pF, are balanced between the inputs to achieve high common-mode rejection. On each sample period (approximately 85 μs), these parasitic capacitances must be recharged to the common-mode voltage by the signal source impedance (10 kΩ maximum). If resistors and capacitors are used at the input of the AD8230, care should be taken to maintain close match to maximize CMRR. Rev. B | Page 12 of 16 AD8230 INPUT VOLTAGE RANGE POWER SUPPLY BYPASSING The input common-mode range of the AD8230 is rail to rail. However, the differential input voltage range is limited to approximately 750 mV. The AD8230 does not phase invert when its inputs are overdriven. A regulated dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. Bypass capacitors should be used to decouple the amplifier. INPUT PROTECTION The AD8230 has internal clocked circuitry that requires adequate supply bypassing. A 0.1 μF capacitor should be placed as close to each supply pin as possible. As shown in Figure 32, a 10 μF tantalum capacitor can be used further away from the part. The input voltage is limited to within 0.6 V beyond the supply rails by the internal ESD protection diodes. Resistors and low leakage diodes can be used to limit excessive, external voltage and current from damaging the inputs, as shown in Figure 37. Figure 39 shows an overvoltage protection circuit between the thermocouple and the AD8230. POWER SUPPLY BYPASSING FOR MULTIPLE CHANNEL SYSTEMS The best way to prevent clock interference in multichannel systems is to lay out the PCB with a star node for the positive supply and a star node for the negative supply. Using such a technique, crosstalk between clocks is minimized. If laying out star nodes is not feasible, use wide traces to minimize parasitic inductance and decouple frequently along the power supply traces. Examples are shown in Figure 38. Care and forethought go a long way in maximizing performance. +VS –VS BAV199 0.1µF +VS –VS 0.1µF 2 4 2.49kΩ 1 AD8230 2.49kΩ VOUT 8 7 5 3 6 19.1kΩ 200Ω 05063-037 +VS –VS BAV199 Figure 37. Overvoltage Input Protection –VS +VS 1µF 10µF 0.1µF 1 2 0.1µF 1µF –VS 1 8 +VS 1 8 +VS 2 3 6 4 5 2 3 6 4 5 AD8230 –VS 7 7 0.1µF 1µF 1µF 0.1µF 0.1µF AD8230 0.1µF 0.1µF 0.1µF –VS 1 8 +VS 2 3 6 3 4 5 2 3 6 4 5 AD8230 AD8230 –VS 1 8 +VS 7 7 0.1µF –VS 0.1µF +VS 4 8 7 6 AD8230 5 STAR –VS 10µF STAR +VS 10µF 0.1µF 0.1µF 1 +VS 1 8 7 2 3 6 4 5 2 0.1µF –VS AD8230 0.1µF 0.1µF 0.1µF –VS +VS 1 8 1 2 3 6 3 4 5 2 3 6 4 5 AD8230 +VS 8 7 7 0.1µF –VS AD8230 0.1µF 4 –VS +VS 7 6 AD8230 Figure 38. Use Star Nodes for +VS and −VS or Use Thick Traces and Decouple Frequently Along the Supply Lines Rev. B | Page 13 of 16 8 5 05063-038 10µF AD8230 LAYOUT The AD8230 has two reference pins: VREF1 and VREF2. VREF1 draws current to set the internal voltage references. In contrast, VREF2 does not draw current. It sets the common mode of the output signal. As such, VREF1 and VREF2 should be star-connected to ground (or to a reference voltage). In addition, to maximize CMR, the trace between VREF2 and the gain resistor, RG, should be kept short. An antialiasing filter reduces unwanted high frequency signals. The matched 100 MΩ resistors serve to provide input bias current to the input transistors and serve as an indicator as to when the thermocouple connection is broken. Well-matched 1% 4.99 kΩ resistors are used to form the antialiasing filter. It is good practice to match the source impedances to ensure high CMR. The circuit is configured for a gain of 193, which provides an overall temperature sensitivity of 10 mV/°C. +VS APPLICATIONS –VS 0.1µF The AD8230 can be used in thermocouple applications, as shown in Figure 3 and Figure 39. Figure 39 is an example of such a circuit for use in an industrial environment. Series resistors and low leakage diodes serve to clamp overload voltages (see the Input Protection section for more information). 0.1µF 0.1µF 4.99kΩ 4 –VS 100MΩ 3 –VS 8 VOUT 7 5 6 19.1kΩ 200Ω +VS –VS BAV199 6 102kΩ Figure 40. Bridge Measurement with Filtered Output 1 AD8230 1µF 3 VOUT 1µF 1kΩ 2 4.99kΩ 350Ω 4kΩ 8 7 5 350Ω 05063-039 TYPE J THERMOCOUPLE 1 AD8230 350Ω 05063-040 +VS 350Ω –VS 100MΩ 2 4 +VS BAV199 +VS –VS 0.1µF +VS Figure 39. Type J Thermocouple with Overvoltage Protection and RFI Filter Measuring load cells in industrial environments can be a challenge. Often, the load cell is located some distance away from the instrumentation amplifier. The common-mode potential can be several volts, exceeding the common-mode input range of many 5 V auto-zero instrumentation amplifiers. Fortunately, the wide common-mode input voltage range of the AD8230 spans 16 V, relieving designers of having to worry about the common-mode range. Rev. B | Page 14 of 16 AD8230 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 1 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012407-A 4.00 (0.1574) 3.80 (0.1497) Figure 41. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model AD8230YRZ 1 AD8230YRZ-REEL1 AD8230YRZ-REEL71 AD8230-EVAL 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead SOIC_N 8-Lead SOIC_N, 13" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel Evaluation Board Z = RoHS Compliant Part. Rev. B | Page 15 of 16 Package Option R-8 R-8 R-8 AD8230 NOTES ©2004–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05063-0-9/07(B) Rev. B | Page 16 of 16