TI LP3852ES-1.8/NOPB 1.5-a fast response ultra-low dropout linear regulator Datasheet

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LP3852, LP3855
SNVS174I – FEBRUARY 2003 – REVISED FEBRUARY 2015
LP385x 1.5-A Fast Response Ultra-Low Dropout Linear Regulators
1 Features
3 Description
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The LP3852 and LP3855 series of fast ultra-low
dropout linear regulators operate from a 2.5-V to 7-V
input supply. A wide range of preset output voltage
options are available. These ultra-low dropout linear
regulators respond very quickly to step changes in
load, which makes them suitable for low voltage
microprocessor applications. The LP3852 and
LP3855 are developed on a CMOS process which
allows low quiescent-current operation independent
of output load current, typically 4 mA at 1.5-A load
current. This CMOS process also allows the LP3852
and LP3855 to operate under extremely low dropout
conditions, typically 24 mV at 150-mA load current
and 240 mV at 1.5-A load current.
1
Input Supply Voltage: 2.5 V to 7 V
Ultra-Low Dropout Voltage
Stable with Selected Ceramic Capacitors
Low Ground-Pin Current
Load Regulation of 0.06%
10-nA Quiescent Current in Shutdown Mode
Specified Output Current of 1.5 A DC
Output Voltage Accuracy ± 1.5%
ERROR Pin Indicates Output Status
SENSE Option Improves Load Regulation
Overtemperature/Overcurrent Protection
−40°C to 125°C Junction Temperature Range
The LP3852 has an ERROR pin; it goes low when
the output voltage drops 10% below nominal value.
The LP3855 has a SENSE pin to improves regulation
at remote loads.
2 Applications
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Microprocessor Power Supplies
GTL, GTL+, BTL, and SSTL Bus Terminators
Power Supplies for DSPs
SCSI Terminator
Post Regulators
High Efficiency Linear Regulators
Battery Chargers
Other Battery Powered Applications
The LP3852 and LP3855 are available with fixed
output voltages from 1.8 V to 5 V with a specified
accuracy of ±1.5% at room temperature, and ±3%
over all conditions (varying line, load, and
temperature). Contact Texas Instruments Sales for
specific voltage option needs.
Device Information(1)
PART NUMBER
LP3852
LP3855
PACKAGE
BODY SIZE (NOM)
SOT (5)
6.50 mm x 3.56 mm
TO-263 (5)
10.16 mm x 8.42 mm
TO-220 (5)
14.986 mm x 10.16 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematics
INPUT
3.3V ± 10%
IN
CIN*
10 PF
OUT
COUT*
LP3852-2.5
SD**
SD
ERROR
GND
ERROR**
VOUT
2.5V, 1.5A
10 PF
* TANTALUM OR CERAMIC
**SD and ERROR pins must be pulled high through a 10-kΩ pull-up resistor. Connect the ERROR pin to ground if this
function is not used.
INPUT
3.3V ± 10%
OUT
IN
CIN*
10 PF
LP3855-2.5
SD**
SD
SENSE
GND
COUT*
VOUT
2.5V, 1.5A
10 PF
* TANTALUM OR CERAMIC
**SD must be pulled high through a 10-kΩ pull-up resistor.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP3852, LP3855
SNVS174I – FEBRUARY 2003 – REVISED FEBRUARY 2015
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Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematics...........................................
Revision History.....................................................
Voltage Options .....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
5
8.1
8.2
8.3
8.4
8.5
8.6
5
5
5
5
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
9.1 Overview ................................................................. 11
9.2 Functional Block Diagrams ..................................... 11
9.3 Feature Description................................................. 12
9.4 Device Functional Modes........................................ 13
10 Application and Implementation........................ 14
10.1 Application Information.......................................... 14
10.2 Typical Applications ............................................. 14
11 Power Supply Recommendations ..................... 17
12 Layout................................................................... 18
12.1
12.2
12.3
12.4
Layout Guidelines .................................................
Layout Example ....................................................
RFI and/or EMI Susceptibility................................
Power Dissipation/Heatsinking..............................
18
18
19
19
13 Device and Documentation Support ................. 21
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
14 Mechanical, Packaging, and Orderable
Information ........................................................... 21
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (December 2014) to Revision I
Page
•
Changed pin names to TI nomenclature; correct typos ........................................................................................................ 1
•
Changed pin numbers and I/O types to correct errors .......................................................................................................... 4
•
Changed Handling to ESD Ratings ....................................................................................................................................... 5
Changes from Revision G (April 2013) to Revision H
•
Added Device Information and Handling Rating tables, Feature Description, Device Functional Modes, Application
and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and
Mechanical, Packaging, and Orderable Information sections; moved some curves to Application Curves section;
updated Thermal Values ....................................................................................................................................................... 1
Changes from Revision F (April 2013) to Revision G
•
2
Page
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 20
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6 Voltage Options (1) (2)
DEVICE NUMBER
PACKAGE
LP3852
LP3855
TO-220 (5)
DDPAK/TO-263 (5)
SOT-223 (5)
VOLTAGE OPTION (V)
1.8
2.5
3.3
5.0
(1)
(2)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available on the Packaging Information page at www.ti.com.
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7 Pin Configuration and Functions
SD
1
IN
2
5
GND
3
4
OUT ERROR/SENSE
SOT-223 (NDC)
5 Pins
Top View
5 Pins
DDPAK/TO-263 (KTT)
Top View
5 Pins
TO-220 (NDH)
Top View, Bent, Staggered Leads
Pin Functions for SOT-223
PIN
LP3852
LP3855
NDC
NDC
ERROR
4
N/A
O
ERROR flag
GND
5
5
—
Ground
IN
2
2
I
Input supply
OUT
3
3
O
Output voltage
1
1
I
Shutdown
N/A
4
I
Remote sense pin
NAME
SD
SENSE
I/O
DESCRIPTION
Pin Functions for TO-220 and TO-263
PIN
LP3852
LP3855
KTT/NDH
KTT/NDH
ERROR
5
N/A
O
ERROR flag
GND
3
3
—
Ground
IN
2
2
I
Input supply
OUT
4
4
O
Output voltage
1
1
I
Shutdown
N/A
5
I
Remote sense pin
NAME
SD
SENSE
4
I/O
DESCRIPTION
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
Lead temperature (soldering, 5 sec.)
Power dissipation
(2)
MAX
UNIT
260
°C
Internally limited
Input supply voltage (survival)
–0.3
7.5
Shutdown input voltage (survival)
–0.3
7.5
–0.3
6
Output voltage (survival)
(3) (4)
,
IOUT (survival)
V
Short-circuit protected
Maximum voltage for ERROR pin
VIN
Maximum voltage for SENSE pin
VOUT
Storage temperature, Tstg
(1)
(2)
(3)
(4)
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO-220 package must be
derated at RθJA = 32°C/W (with 0.5 in2, 1-oz. copper area), junction-to-ambient (with no heat sink). The devices in the TO-263 surfacemount package must be derated at RθJA = 40.3°C/W (with 0.5 in2, 1-oz. copper area), junction-to-ambient. See Application and
Implementation section.
If used in a dual-supply system where the regulator load is returned to a negative supply, the output must be diode-clamped to ground.
The output PMOS structure contains a diode between the IN and OUT terminals. This diode is normally reverse biased. This diode will
get forward biased if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can
typically withstand 200 mA of DC current and 1 A of peak current.
8.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Input supply voltage (1)
2.5
7
Shutdown input voltage
−0.3
7
1.5
A
−40
125
°C
Maximum operating current (DC)
Junction temperature
(1)
V
The minimum operating value for VIN is equal to either [VOUT(NOM) + VDROPOUT] or 2.5 V, whichever is greater.
8.4 Thermal Information
LP3852/LP3855
THERMAL METRIC (1)
NDC
KTT
NDH
5 PINS
5 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance, High-K
65.2
40.3
32
RθJC(top)
Junction-to-case (top) thermal resistance
47.2
43.4
43.8
RθJB
Junction-to-board thermal resistance
9.9
23.1
18.6
ψJT
Junction-to-top characterization parameter
3.4
11.5
8.8
ψJB
Junction-to-board characterization parameter
9.7
22
18
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
1
1.2
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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8.5 Electrical Characteristics
Unless otherwise specified: VIN = VOUT(NOM) + 1 V, IOUT = 10 mA, COUT = 10 µF, VSD = 2 V, TJ = 25°C.
PARAMETER
TEST CONDITIONS
VOUT +1 V ≤ VIN ≤ 7 V
10 mA ≤ IOUT ≤ 1.5 A
Output voltage tolerance (3)
VOUT
For –40°C ≤ TJ ≤ 125°C
ΔVOUT/ΔVIN
ΔVOUT/ΔIOUT
Output voltage line regulation (3)
Output voltage load regulation (3)
MIN (1)
TYP (2)
–1.5%
0
–3%
0.02%
For –40°C ≤ TJ ≤ 125°C
0.06%
10 mA ≤ IOUT ≤ 1.5 A
0.06%
For –40°C ≤ TJ ≤ 125°C
0.12%
35
240
280
45
IOUT = 1.5A
For –40°C ≤ TJ ≤ 125°C
380
IOUT = 150mA
26
35
260
320
For –40°C ≤ TJ ≤ 125°C
Dropout voltage
SOT (4), (5)
435
IOUT = 150 mA
3
For –40°C ≤ TJ ≤ 125°C
Ground pin current in normal
operation mode
3
For –40°C ≤ TJ ≤ 125°C
IGND
Ground pin current in shutdown
mode
IOUT(PK)
Peak output current
VO ≥ VO(NOM) – 4%
9
10
IOUT = 1.5 A
VSD ≤ 0.3V
mV
45
IOUT = 1.5 A
For –40°C ≤ TJ ≤ 125°C
IGND
1.5%
24
For –40°C ≤ TJ ≤ 125°C
VIN - VOUT
UNIT
3%
VOUT +1 V ≤ VIN ≤ 7 V
IOUT = 150 mA
Dropout voltage
TO-263 and TO-220 (4)
MAX (1)
9
mA
10
0.01
-40°C ≤ TJ ≤ 85°C
10
50
µA
1.8
A
3.2
A
SHORT CIRCUIT PROTECTION
ISC
Short circuit current
SHUTDOWN INPUT
VSDT Rising from 0.3 V until
Output = ON
VSDT
Shutdown threshold
For –40°C ≤ TJ ≤ 125°C
1.3
2
VSDT Falling from 2 V until
Output = OFF
V
1.3
For –40°C ≤ TJ ≤ 125°C
0.3
TdOFF
Turnoff delay
IOUT = 1.5 A
20
TdON
Turnon delay
IOUT = 1.5 A
25
µs
µs
ISD
SD input current
VSD = VIN
1
nA
ERROR PIN
VT
VTH
(1)
(2)
(3)
(4)
(5)
(6)
6
Threshold
Threshold hysteresis
See (6)
For –40°C ≤ TJ ≤ 125°C
10%
5%
See (6)
For –40°C ≤ TJ ≤ 125°C
16%
5%
2%
8%
Limits are specified by testing, design, or statistical correlation.
Typical numbers are at 25°C and represent the most likely parametric norm.
Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage.
Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in load current. The line
and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the
output voltage tolerance specification.
Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value.
Dropout voltage specification applies only to output voltages of 2.5V and above. For output voltages below 2.5 V, the drop-out voltage is
nothing but the input to output differential, since the minimum input voltage is 2.5 V.
The SOT-223 package devices have slightly higher dropout due to increased bond wire resistance.
ERROR threshold and hysteresis are specified as percentage of regulated output voltage. See ERROR Flag Operation.
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Electrical Characteristics (continued)
Unless otherwise specified: VIN = VOUT(NOM) + 1 V, IOUT = 10 mA, COUT = 10 µF, VSD = 2 V, TJ = 25°C.
PARAMETER
VEF(Sat)
ERROR pin saturation
Td
Flag reset delay
Ilk
ERROR pin leakage current
Imax
ERROR pin sink current
TEST CONDITIONS
Isink = 100 µA
MIN (1)
TYP (2)
UNIT
0.02
For –40°C ≤ TJ ≤ 125°C
V
0.1
1
VError = 0.5 V
MAX (1)
µs
1
nA
1
mA
AC PARAMETERS
PSRR
ρn(l/f)
en
Ripple rejection
Output noise density
Output noise voltage
VIN = VOUT + 1 V
COUT = 10 µF
VOUT = 3.3V, f = 120 Hz
73
VIN = VOUT + 0.5 V
COUT = 10 µF
VOUT = 3.3V, f = 120 Hz
57
f = 120 Hz
0.8
BW = 10Hz – 100 kHz
VOUT = 2.5 V
150
BW = 300 Hz – 300 kHz
VOUT = 2.5 V
100
dB
µV
µV (rms)
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8.6 Typical Characteristics
600
6
500
5
400
12
300
o
5C
oC
25
200
oC
- 40
GROUND PIN CURRENT (mA)_
DROPOUT VOLTAGE (mV)
Unless otherwise specified: TJ = 25°C, COUT = 10 µF, CIN = 10 µF, SD pin is tied to VIN, VOUT = 2.5 V, VIN = VOUT(NOM) + 1 V,
IOUT = 10 mA.
4
3
2
1
100
0
1.8
0
0
0.5
2.3
2.8
3.3
3.8
4.3
5.0
1.5
1
OUTPUT VOLTAGE (V)
OUTPUT LOAD CURRENT (A)
IOUT = 1.5 A
Figure 1. Dropout Voltage vs Output Load Current
Figure 2. Ground Current vs Output Voltage
10
ERROR THRESHOLD (% of VOUT)
14
SHUTDOWN IQ (PA)
1
0.1
0.01
0.001
-40 -20
12
10
8
6
4
2
0
0
20
40
60
80
-40 -20
100 125
Figure 3. SD IQ vs Junction Temperature
40
60
80 100 125
3
' VOUT/VOLT CHANGE in VIN (mV)
DC LOAD REGULATION (mV/A)
8
20
Figure 4. ERROR Threshold vs Junction Temperature
3
2.5
2
1.5
1
0.5
0
-40
0
JUNCTION TEMPERATURE (oC)
TEMPERATURE (oC)
-20
0
20
40
60
80
2.5
2
1.5
1
0.5
0
-40
100 125
-20
0
20
40
60
80
100 125
JUNCTION TEMPERATURE (oC)
JUNCTION TEMPERATURE (oC)
Figure 5. DC Load Reg. vs Junction Temperature
Figure 6. DC Line Regulation vs Temperature
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Typical Characteristics (continued)
Unless otherwise specified: TJ = 25°C, COUT = 10 µF, CIN = 10 µF, SD pin is tied to VIN, VOUT = 2.5 V, VIN = VOUT(NOM) + 1 V,
IOUT = 10 mA.
3.0
3.000
2.5
2.500
-40oC
0.5
2.000
NOISE (PV/ Hz
VOUT (V)
1.5
1.0
IL = 100mA
CIN = COUT = 10PF
(
2.0
25oC
1.500
1.000
0.500
125oC
0.000
0.0
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
1k
10k
100k
FREQUENCY (Hz)
VIN (V)
Figure 8. Noise vs Frequency
Figure 7. VIN vs VOUT Over Temperature
VOUT
100mV/DIV
MAGNITUDE
MAGNITUDE
VOUT
100mV/DIV
ILOAD
1A/DIV
ILOAD
1A/DIV
TIME (50Ps/DIV)
TIME (50Ps/DIV)
CIN = COUT = 100 µF, OSCON
CIN = COUT = 100 µF, POSCAP
Figure 9. Load Transient Response
Figure 10. Load Transient Response
VOUT
100 mV/DIV
VOUT = 2.5V
1
T
IOUT
1A/DIV
T
MAGNITUDE
VOUT
100mV/DIV
ILOAD
1A/DIV
IOUT
@ 1A
2
TIME (50Ps/DIV)
TIME (2 Ps/DIV)
CIN = 2 X 10 µF Ceramic
COUT = 2 X 10µF Ceramic
CIN = COUT = 100 µF, Tantalum
Figure 11. Load Transient Response
Figure 12. Load Transient Response
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Typical Characteristics (continued)
Unless otherwise specified: TJ = 25°C, COUT = 10 µF, CIN = 10 µF, SD pin is tied to VIN, VOUT = 2.5 V, VIN = VOUT(NOM) + 1 V,
IOUT = 10 mA.
1
VOUT
@ 2.5V
T
IOUT
@ 1A
T
2
TIME (1 Ps/DIV)
CIN = 2 X 10 µF Ceramic
COUT = 2 X 10µF Ceramic
Figure 13. Load Transient Response
10
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9 Detailed Description
9.1 Overview
The LP3852 and LP3855 series of fast ultra-low dropout linear regulators operate from a 2.5-V to 7-V input
supply. A wide range of preset output voltage options are available. These ultra-low dropout linear regulators
respond very quickly to step changes in load, which makes them suitable for low voltage microprocessor
applications. The LP3852 and LP3855 are developed on a CMOS process which allows low quiescent current
operation independent of output load current. This CMOS process also allows the LP3852 and LP3855 to
operate under extremely low dropout conditions.
9.2 Functional Block Diagrams
Figure 14. LP3852 Block Diagram
Figure 15. LP3855 Block Diagram
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9.3 Feature Description
9.3.1 SENSE Pin
In applications where the regulator output is not very close to the load, LP3855 can provide better remote load
regulation using the SENSE pin. Figure 16 depicts the advantage of the SENSE option. The LP3852 regulates
the voltage at the OUT pin. Hence, the voltage at the remote load will be the regulator output voltage minus the
drop across the trace resistance. For example, in the case of a 3.3-V output, if the trace resistance is 100 mΩ,
the voltage at the remote load will be 3.15 V with 1.5 A of load current, ILOAD. The LP3855 regulates the voltage
at the SENSE pin. Connecting the SENSE pin to the remote load will provide regulation at the remote load, as
shown in Figure 16. If the SENSE pin is not required, the SENSE pin must be connected to the OUT pin.
Figure 16. Improving Remote Load Regulation Using LP3855
9.3.2 SHUTDOWN (SD) Operation
A CMOS Logic low level signal at the SD pin will turn off the regulator. SD must be actively terminated through a
10-kΩ pullup resistor for a proper operation. If this pin is driven from a source that actively pulls high and low
(such as a CMOS rail-to-rail comparator), the pullup resistor is not required. This pin must be tied to VIN if not
used.
The SD pin threshold has no voltage hysteresis. If the SD pin is actively driven, the voltage transition must rise
and fall cleanly and promptly.
9.3.3 Dropout Voltage
The dropout voltage of a regulator is defined as the minimum input-to-output differential required to stay within
2% of the nominal output voltage. For CMOS LDOs, the dropout voltage is the product of the load current and
the Rds(on) of the internal MOSFET.
9.3.4 Reverse Current Path
The internal MOSFET in LP3852 and LP3855 has an inherent parasitic diode. During normal operation, the input
voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is
pulled above the input in an application, then current flows from the output to the input as the parasitic diode gets
forward biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to
200-mA continuous and 1-A peak.
9.3.5 Short-Circuit Protection
The LP3852 and LP3855 are short-circuit protected and in the event of a peak overcurrent condition, the shortcircuit control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts
down, the control loop will rapidly cycle the output on and off until the average power dissipation causes the
thermal shutdown circuit to respond to servo the on/off cycling to a lower frequency. Please refer to for power
dissipation calculations.
12
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Feature Description (continued)
9.3.6 ERROR Flag Operation
The LP3852 and LP3855 produce a logic low signal at the ERROR pin when the output drops out of regulation
due to low input voltage, current limiting, or thermal limiting. This flag has a built in hysteresis. The timing
diagram in Figure 17 shows the relationship between the ERROR flag and the output voltage. In this example,
the input voltage is changed to demonstrate the functionality of the ERROR Flag.
The internal ERROR comparator has an open drain output stage; thus, the ERROR pin should be pulled high
through a pullup resistor. Although the ERROR flag pin can sink current of 1 mA, this current is energy drain
from the input supply. Hence, the value of the pullup resistor should be in the range of 10 kΩ to 1 MΩ. The
ERROR pin must be connected to ground if this function is not used. It should also be noted that when the
shutdown pin is pulled low, the ERROR pin is forced to be invalid for reasons of saving power in shutdown
mode.
Figure 17. ERROR Operation
9.4 Device Functional Modes
9.4.1 Operation with VOUT(TARGET) + 0.1 V ≤ VIN ≤ 7 V
The device operate if the input voltage is equal to, or exceeds VOUT(TARGET) + 0.1 V. At input voltages below the
minimum VIN requirement, the devices do not operate correctly and output voltage may not reach target value.
9.4.2 Operation With SD Pin Control
A CMOS Logic low level signal at the SD pin will turn off the regulator. The SD pin must be actively terminated
through a 10-kΩ pullup resistor for a proper operation.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The LP3852 and LP3855 devices can provide 1.5-A output current with 2.5-V to 7-V input. A minimum 10-uF
output capacitor is required for loop stability. An input capacitor of at least 10 µF is required . Pin SD must be
tied to input if not used. For LP3852, ERROR pin should be pulled high through a pullup resistor. For LP3855, if
the sense option is not required , the SENSE pin must be connected to the OUT pin.
10.2 Typical Applications
INPUT
3.3V ± 10%
IN
CIN*
10 PF
OUT
COUT*
LP3852-2.5
SD**
SD
ERROR
GND
ERROR**
VOUT
2.5V, 1.5A
10 PF
* TANTALUM OR CERAMIC
Figure 18. LP3852 Typical Application
INPUT
3.3V ± 10%
IN
CIN*
10 PF
OUT
COUT*
LP3855-2.5
SD**
SD
VOUT
2.5V, 1.5A
10 PF
SENSE
GND
* TANTALUM OR CERAMIC
Figure 19. LP3855 Typical Application
10.2.1 Design Requirements
DESIGN PARAMETERS
VALUE
Input voltage
3.3 V, ±10%
Output voltage
2.5 V, ±3%
Output current
1.5 A (maximum)
Input capacitor
10 µF (minimum)
Output capacitor
10 µF (minimum)
ERROR pullup resistor (LP3852 only)
10 kΩ
10.2.2 Detailed Design Procedure
10.2.2.1 External Capacitors
Like any low dropout regulator, external capacitors are required to assure stability. These capacitors must be
correctly selected for proper performance.
10.2.2.1.1 Input Capacitor
An input capacitor of at least 10 µF is required. Ceramic or tantalum may be used, and capacitance may be
increased without limit.
14
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10.2.2.1.2 Output Capacitor
An output capacitor is required for loop stability. It must be located less than 1 cm from the device and connected
directly to the output and ground pins using traces which have no other currents flowing through them (see
Layout Guidelines).
The minimum amount of output capacitance that can be used for stable operation is 10 µF. For general usage
across all load currents and operating conditions, the part was characterized using a 10-µF tantalum input
capacitor. The minimum and maximum stable equivalent series resistance (ESR) range for the output capacitor
was then measured which kept the device stable, assuming any output capacitor whose value is greater than 10
µF (see Figure 20).
10
COUT > 10 PF
STABLE REGION
COUT ESR (:)
1.0
0.1
.01
.001
0
1
LOAD CURRENT (A)
2
Figure 20. ESR Curve For COUT (with 10-µF Tantalum Input Capacitor)
It should be noted that it is possible to operate the part with an output capacitor whose ESR is below these limits,
assuming that sufficient ceramic input capacitance is provided. This will allow stable operation using ceramic
output capacitors (see Operation with Ceramic Output Capacitors).
10.2.2.2 Operation with Ceramic Output Capacitors
LP385X voltage regulators can operate with ceramic output capacitors if the values of the input and output
capacitors are selected appropriately. The total ceramic output capacitance must be equal to or less than a
specified maximum value in order for the regulator to remain stable over all operating conditions. This maximum
amount of ceramic output capacitance is dependent upon the amount of ceramic input capacitance used as well
as the load current of the application. This relationship is shown in Figure 21, which graphs the maximum stable
value of ceramic output capacitance as a function of ceramic input capacitance for load currents of 1.5 A.
CERAMIC INPUT CAPACITANCE (PF)
100
IL = 1.5A
10
100
1000
MAX. ALLOWABLE CERAMIC
OUTPUT CAPACITANCE (PF)
Figure 21. Maximum Ceramic Output Capacitance vs Ceramic Input Capacitance
If the maximum load current is 1.5 A and a 10-µF ceramic input capacitor is used, the regulator will be stable with
ceramic output capacitor values from 10 µF up to about 150 µF. When calculating the total ceramic output
capacitance present in an application, it is necessary to include any ceramic bypass capacitors connected to the
regulator output.
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10.2.2.3 Selecting A Capacitor
It is important to note that capacitance tolerance and variation with temperature must be taken into consideration
when selecting a capacitor so that the minimum required amount of capacitance is provided over the full
operating temperature range. In general, a good tantalum capacitor will show very little capacitance variation with
temperature, but a ceramic may not be as good (depending on dielectric type). Aluminum electrolytics also
typically have large temperature variation of capacitance value.
Equally important to consider is a capacitor's ESR change with temperature: this is not an issue with ceramics,
as their ESR is extremely low. However, it is very important in Tantalum and aluminum electrolytic capacitors.
Both show increasing ESR at colder temperatures, but the increase in aluminum electrolytic capacitors is so
severe they may not be feasible for some applications (see Capacitor Characteristics).
10.2.2.4 Capacitor Characteristics
10.2.2.4.1 Ceramic
For values of capacitance in the 10-µF to 100-µF range, ceramics are usually larger and more costly than
tantalums but give superior AC performance for bypassing high frequency noise because of very low ESR
(typically less than 10 mΩ). However, some dielectric types do not have good capacitance characteristics as a
function of voltage and temperature.
Z5U and Y5V dielectric ceramics have capacitance that drops severely with applied voltage. A typical Z5U or
Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage applied to it. The Z5U and Y5V
also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of
the temperature range.
X7R and X5R dielectric ceramic capacitors are strongly recommended if ceramics are used, as they typically
maintain a capacitance range within ±20% of nominal over full operating ratings of temperature and voltage. Of
course, they are typically larger and more costly than Z5U/Y5U types for a given voltage and capacitance.
10.2.2.4.2 Tantalum
Solid tantalum capacitors are typically recommended for use on the output because their ESR is very close to
the ideal value required for loop compensation.
Tantalum capacitors also have good temperature stability: a good quality tantalum capacitor will typically show a
capacitance value that varies less than 10-15% across the full temperature range of 125°C to −40°C. ESR will
vary only about 2X going from the high to low temperature limits.
The increasing ESR at lower temperatures can cause oscillations when marginal quality capacitors are used (if
the ESR of the capacitor is near the upper limit of the stability range at room temperature).
10.2.2.4.3 Aluminum
This capacitor type offers the most capacitance for the money. The disadvantages are that they are larger in
physical size, not widely available in surface mount, and have poor AC performance (especially at higher
frequencies) due to higher ESR and ESL.
Compared by size, the ESR of an aluminum electrolytic is higher than either tantalum or ceramic, and it also
varies greatly with temperature. A typical aluminum electrolytic can exhibit an ESR increase of as much as 50X
when going from 25°C down to −40°C.
It should also be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which
indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance
specified at a higher frequency (between 20 kHz and 100 kHz) should be used for the LP385X. Derating must be
applied to the manufacturer's ESR specification, since it is typically only valid at room temperature.
Any applications using aluminum electrolytics should be thoroughly tested at the lowest ambient operating
temperature where ESR is maximum.
16
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10.2.2.5 Turnon Characteristics For Output Voltages Programmed to 2 V or Below
As VIN increases during start-up, the regulator output will track the input until VIN reaches the minimum operating
voltage (typically about 2.2 V). For output voltages programmed to 2 V or below, the regulator output may
momentarily exceed its programmed output voltage during start up. Outputs programmed to voltages above 2 V
are not affected by this behavior.
10.2.2.6 Output Noise
Noise is specified in two ways:
• Spot Noise or Output Noise Density is the RMS sum of all noise sources, measured at the regulator output, at
a specific frequency (measured with a 1-Hz bandwidth). This type of noise is usually plotted on a curve as a
function of frequency.
• Total Output Noise or Broad-Band Noise is the RMS sum of spot noise over a specified bandwidth, usually
several decades of frequencies.
Attention should be paid to the units of measurement. Spot noise is measured in units µV/√Hz or nV/√Hz, and
total output noise is measured in µVRMS.
The primary source of noise in low-dropout regulators is the internal reference. In CMOS regulators, noise has a
low frequency component and a high frequency component, which depend strongly on the silicon area and
quiescent current. Noise can be reduced in two ways: by increasing the transistor area or by increasing the
current drawn by the internal reference. Increasing the area will decrease the chance of fitting the die into a
smaller package. Increasing the current drawn by the internal reference increases the total supply current
(ground pin current). Using an optimized trade-off of ground pin current and die size, LP3852 and LP3855
achieve low noise performance and low quiescent-current operation.
The total output noise specification for LP3852 and LP3855 is presented in the Electrical Characteristics table.
The Output noise density at different frequencies is represented by a curve under Typical Characteristics.
10.2.3 Application Curves
VOUT
100mV/DIV
MAGNITUDE
MAGNITUDE
VOUT
100mV/DIV
ILOAD
1A/DIV
ILOAD
1A/DIV
TIME (50Ps/DIV)
TIME (50Ps/DIV)
CIN = COUT = 10 µF, OSCON
CIN = COUT = 10 µF, Tantalum
Figure 22. Load Transient Response
Figure 23. Load Transient Response
11 Power Supply Recommendations
The LP3852 and LP3855 devices are designed to operate from an input voltage supply range between 2.5 V and
7 V. The input voltage range provides adequate headroom in order for the device to have a regulated output.
This input supply must be well regulated. An input capacitor of at least 10 μF is required.
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12 Layout
12.1 Layout Guidelines
Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops.
The input and output capacitors must be directly connected to the IN, OUT, and ground pins of the regulator
using traces which do not have other currents flowing in them (Kelvin connect).
The best way to do this is to lay out CIN and COUT near the device with short traces to the IN, OUT, and ground
pins. The regulator ground pin should be connected to the external circuit ground so that the regulator and its
capacitors have a "single point ground".
It should be noted that stability problems have been seen in applications where "vias" to an internal ground plane
were used at the ground points of the IC and the input and output capacitors. This was caused by varying ground
potentials at these nodes resulting from current flowing through the ground plane. Using a single point ground
technique for the regulator and its capacitors fixed the problem.
Since high current flows through the traces going into IN and coming from OUT, Kelvin connect the capacitor
leads to these pins so there is no voltage drop in series with the input and output capacitors.
12.2 Layout Example
SD
ERROR
Pull-up
Resistor
Pull-up
Resistor
OUT
IN
Input
Capacitor
Output
Capacitor
Ground
Figure 24. LP3852 TO-263 Package Typical Layout
SD
SENSE
Pull-up
Resistor
IN
OUT
Input
Capacitor
Output
Capacitor
Ground
Figure 25. LP3855 TO-263 Package Typical Layout
18
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12.3 RFI and/or EMI Susceptibility
Radio frequency interference (RFI) and electromagnetic interference (EMI) can degrade any integrated circuit
performance because of the small dimensions of the geometries inside the device. In applications where circuit
sources are present which generate signals with significant high frequency energy content (> 1 MHz), care must
be taken to ensure that this does not affect the device regulator.
If RFI and/or EMI noise is present on the input side of the regulator (such as applications where the input source
comes from the output of a switching regulator), good ceramic bypass capacitors must be used at the IN pin of
the device.
If a load is connected to the device output which switches at high speed (such as a clock), the high-frequency
current pulses required by the load must be supplied by the capacitors on the device output. Since the bandwidth
of the regulator loop is less than 100 kHz, the control circuitry cannot respond to load changes above that
frequency. This means the effective output impedance of the device at frequencies above 100 kHz is determined
only by the output capacitor or capacitors.
In applications where the load is switching at high speed, the output of the IC may need RF isolation from the
load. It is recommended that some inductance be placed between the output capacitor and the load, and good
RF bypass capacitors be placed directly across the load.
PCB layout is also critical in high noise environments, since RFI and/or EMI is easily radiated directly into PC
traces. Noisy circuitry should be isolated from "clean" circuits where possible, and grounded through a separate
path. At MHz frequencies, ground planes begin to look inductive and RFI and/or EMI can cause ground bounce
across the ground plane.
In multi-layer PCB applications, care should be taken in layout so that noisy power and ground planes do not
radiate directly into adjacent layers which carry analog power and ground.
12.4 Power Dissipation/Heatsinking
The LP3852 and LP3855 can deliver a continuous current of 1.5 A over the full operating temperature range. A
heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of
the application. Under all possible conditions, the junction temperature must be within the range specified under
operating conditions. The total power dissipation of the device is given by:
PD = (VIN − VOUT)IOUT+ (VIN)IGND
where
•
IGND is the operating ground current of the device (specified under Electrical Characteristics).
(1)
The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the
application, and the maximum allowable junction temperature (TJmax):
TRmax = TJmax − TAmax
(2)
The maximum allowable value for junction to ambient thermal resistance, RθJA, can be calculated using the
formula:
RθJA = TRmax / PD
(3)
The LP3852 and LP3855 are available in TO-220 and TO-263 packages. The thermal resistance depends on
amount of copper area or heat sink, and on air flow. If the maximum allowable value of RθJA calculated in
Equation 3 is ≥ 60 °C/W for TO-220 package and ≥ 60°C/W for TO-263 package, no heatsink is needed since
the package can dissipate enough heat to satisfy these requirements. If the value for allowable RθJA falls below
these limits, a heat sink is required.
12.4.1 Heatsinking TO-220 Package
The thermal resistance of a TO-220 package can be reduced by attaching it to a heat sink or a copper plane on
a PC board. If a copper plane is to be used, the values of RθJA will be same as shown in next section for TO-263
package.
The heatsink to be used in the application should have a heatsink to ambient thermal resistance,
RθHA≤ RθJA − RθCH − RθJC.
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Power Dissipation/Heatsinking (continued)
In this equation, RθCH is the thermal resistance from the case to the surface of the heat sink, and RθJC is the
thermal resistance from the junction to the surface of the case. RθJC is about 3°C/W for a TO-220 package. The
value for RθCH depends on method of attachment, insulator, etc. RθCH varies between 1.5°C/W to 2.5°C/W. If the
exact value is unknown, 2°C/W can be assumed.
12.4.2 Heatsinking TO-263 Package
The TO-263 package uses the copper plane on the PCB as a heatsink. The tab of these packages are soldered
to the copper plane for heat sinking. Figure 26 shows a curve for the RθJA of TO-263 package for different copper
area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat sinking.
Figure 26. RθJA vs Copper (1 Ounce) Area for TO-263 package
As shown in the figure, increasing the copper area beyond 1 square inch produces very little improvement. The
minimum value for RθJA for the TO-263 package mounted to a PCB is 32°C/W.
Figure 27 shows the maximum allowable power dissipation for TO-263 packages for different ambient
temperatures, assuming RθJA is 35°C/W and the maximum junction temperature is 125°C.
Figure 27. Maximum Power Dissipation vs Ambient Temperature for TO-263 Package
20
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13 Device and Documentation Support
13.1 Related Links
Table 1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LP3852
Click here
Click here
Click here
Click here
Click here
LP3855
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LP3852EMP-1.8
NRND
SOT-223
NDC
5
1000
TBD
Call TI
Call TI
-40 to 125
LHTB
LP3852EMP-1.8/NOPB
ACTIVE
SOT-223
NDC
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LHTB
LP3852EMP-2.5
NRND
SOT-223
NDC
5
1000
TBD
Call TI
Call TI
-40 to 125
LHUB
LP3852EMP-2.5/NOPB
ACTIVE
SOT-223
NDC
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LHUB
LP3852EMP-3.3
NRND
SOT-223
NDC
5
1000
TBD
Call TI
Call TI
-40 to 125
LHVB
LP3852EMP-3.3/NOPB
ACTIVE
SOT-223
NDC
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LHVB
LP3852EMP-5.0/NOPB
ACTIVE
SOT-223
NDC
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LHXB
LP3852EMPX-1.8/NOPB
ACTIVE
SOT-223
NDC
5
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LHTB
LP3852ES-1.8/NOPB
ACTIVE
DDPAK/
TO-263
KTT
5
45
Pb-Free (RoHS
Exempt)
CU SN
Level-3-245C-168 HR
-40 to 125
LP3852ES
-1.8
LP3852ES-2.5/NOPB
ACTIVE
DDPAK/
TO-263
KTT
5
45
Pb-Free (RoHS
Exempt)
CU SN
Level-3-245C-168 HR
-40 to 125
LP3852ES
-2.5
LP3852ES-3.3
NRND
DDPAK/
TO-263
KTT
5
45
TBD
Call TI
Call TI
-40 to 125
LP3852ES
-3.3
LP3852ES-3.3/NOPB
ACTIVE
DDPAK/
TO-263
KTT
5
45
Pb-Free (RoHS
Exempt)
CU SN
Level-3-245C-168 HR
-40 to 125
LP3852ES
-3.3
LP3852ES-5.0/NOPB
ACTIVE
DDPAK/
TO-263
KTT
5
45
Pb-Free (RoHS
Exempt)
CU SN
Level-3-245C-168 HR
-40 to 125
LP3852ES
-5.0
LP3852ESX-1.8/NOPB
ACTIVE
DDPAK/
TO-263
KTT
5
500
Pb-Free (RoHS
Exempt)
CU SN
Level-3-245C-168 HR
-40 to 125
LP3852ES
-1.8
LP3852ESX-2.5/NOPB
ACTIVE
DDPAK/
TO-263
KTT
5
500
Pb-Free (RoHS
Exempt)
CU SN
Level-3-245C-168 HR
-40 to 125
LP3852ES
-2.5
LP3852ESX-3.3/NOPB
ACTIVE
DDPAK/
TO-263
KTT
5
500
Pb-Free (RoHS
Exempt)
CU SN
Level-3-245C-168 HR
-40 to 125
LP3852ES
-3.3
LP3852ESX-5.0/NOPB
ACTIVE
DDPAK/
TO-263
KTT
5
500
Pb-Free (RoHS
Exempt)
CU SN
Level-3-245C-168 HR
-40 to 125
LP3852ES
-5.0
LP3852ET-1.8/NOPB
ACTIVE
TO-220
NDH
5
45
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
-40 to 125
LP3852ET
-1.8
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
8-Oct-2015
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LP3852ET-2.5/NOPB
ACTIVE
TO-220
NDH
5
45
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
-40 to 125
LP3852ET
-2.5
LP3852ET-3.3/NOPB
ACTIVE
TO-220
NDH
5
45
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
-40 to 125
LP3852ET
-3.3
LP3852ET-5.0/NOPB
ACTIVE
TO-220
NDH
5
45
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
-40 to 125
LP3852ET
-5.0
LP3855EMP-1.8/NOPB
ACTIVE
SOT-223
NDC
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LHYB
LP3855EMP-2.5/NOPB
ACTIVE
SOT-223
NDC
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LHZB
LP3855EMP-3.3/NOPB
ACTIVE
SOT-223
NDC
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LJ1B
LP3855EMP-5.0/NOPB
ACTIVE
SOT-223
NDC
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LJ2B
LP3855EMPX-5.0/NOPB
ACTIVE
SOT-223
NDC
5
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LJ2B
LP3855ES-1.8
NRND
DDPAK/
TO-263
KTT
5
45
TBD
Call TI
Call TI
-40 to 125
LP3855ES
-1.8
LP3855ES-1.8/NOPB
ACTIVE
DDPAK/
TO-263
KTT
5
45
Pb-Free (RoHS
Exempt)
CU SN
Level-3-245C-168 HR
-40 to 125
LP3855ES
-1.8
LP3855ES-2.5/NOPB
ACTIVE
DDPAK/
TO-263
KTT
5
45
Pb-Free (RoHS
Exempt)
CU SN
Level-3-245C-168 HR
-40 to 125
LP3855ES
-2.5
LP3855ES-3.3/NOPB
ACTIVE
DDPAK/
TO-263
KTT
5
45
Pb-Free (RoHS
Exempt)
CU SN
Level-3-245C-168 HR
-40 to 125
LP3855ES
-3.3
LP3855ES-5.0/NOPB
ACTIVE
DDPAK/
TO-263
KTT
5
45
Pb-Free (RoHS
Exempt)
CU SN
Level-3-245C-168 HR
-40 to 125
LP3855ES
-5.0
LP3855ESX-1.8/NOPB
ACTIVE
DDPAK/
TO-263
KTT
5
500
Pb-Free (RoHS
Exempt)
CU SN
Level-3-245C-168 HR
-40 to 125
LP3855ES
-1.8
LP3855ESX-2.5/NOPB
ACTIVE
DDPAK/
TO-263
KTT
5
500
Pb-Free (RoHS
Exempt)
CU SN
Level-3-245C-168 HR
-40 to 125
LP3855ES
-2.5
LP3855ESX-3.3/NOPB
ACTIVE
DDPAK/
TO-263
KTT
5
500
Pb-Free (RoHS
Exempt)
CU SN
Level-3-245C-168 HR
-40 to 125
LP3855ES
-3.3
LP3855ESX-5.0/NOPB
ACTIVE
DDPAK/
TO-263
KTT
5
500
Pb-Free (RoHS
Exempt)
CU SN
Level-3-245C-168 HR
-40 to 125
LP3855ES
-5.0
LP3855ET-1.8/NOPB
ACTIVE
TO-220
NDH
5
45
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
-40 to 125
LP3855ET
-1.8
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
8-Oct-2015
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LP3855ET-2.5/NOPB
ACTIVE
TO-220
NDH
5
45
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
-40 to 125
LP3855ET
-2.5
LP3855ET-3.3/NOPB
ACTIVE
TO-220
NDH
5
45
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
-40 to 125
LP3855ET
-3.3
LP3855ET-5.0/NOPB
ACTIVE
TO-220
NDH
5
45
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
-40 to 125
LP3855ET
-5.0
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LP3852EMP-1.8
SOT-223
NDC
5
1000
330.0
16.4
7.0
7.5
2.2
12.0
16.0
Q3
LP3852EMP-1.8/NOPB
SOT-223
NDC
5
1000
330.0
LP3852EMP-2.5
SOT-223
NDC
5
1000
330.0
16.4
7.0
7.5
2.2
12.0
16.0
Q3
16.4
7.0
7.5
2.2
12.0
16.0
LP3852EMP-2.5/NOPB
SOT-223
NDC
5
1000
Q3
330.0
16.4
7.0
7.5
2.2
12.0
16.0
LP3852EMP-3.3
SOT-223
NDC
5
Q3
1000
330.0
16.4
7.0
7.5
2.2
12.0
16.0
Q3
LP3852EMP-3.3/NOPB
SOT-223
NDC
LP3852EMP-5.0/NOPB
SOT-223
NDC
5
1000
330.0
16.4
7.0
7.5
2.2
12.0
16.0
Q3
5
1000
330.0
16.4
7.0
7.5
2.2
12.0
16.0
LP3852EMPX-1.8/NOPB SOT-223
Q3
NDC
5
2000
330.0
16.4
7.0
7.5
2.2
12.0
16.0
Q3
LP3852ESX-1.8/NOPB
DDPAK/
TO-263
KTT
5
500
330.0
24.4
10.75
14.85
5.0
16.0
24.0
Q2
LP3852ESX-2.5/NOPB
DDPAK/
TO-263
KTT
5
500
330.0
24.4
10.75
14.85
5.0
16.0
24.0
Q2
LP3852ESX-3.3/NOPB
DDPAK/
TO-263
KTT
5
500
330.0
24.4
10.75
14.85
5.0
16.0
24.0
Q2
LP3852ESX-5.0/NOPB
DDPAK/
TO-263
KTT
5
500
330.0
24.4
10.75
14.85
5.0
16.0
24.0
Q2
LP3855EMP-1.8/NOPB
SOT-223
NDC
5
1000
330.0
16.4
7.0
7.5
2.2
12.0
16.0
Q3
LP3855EMP-2.5/NOPB
SOT-223
NDC
5
1000
330.0
16.4
7.0
7.5
2.2
12.0
16.0
Q3
LP3855EMP-3.3/NOPB
SOT-223
NDC
5
1000
330.0
16.4
7.0
7.5
2.2
12.0
16.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
Device
Package Package Pins
Type Drawing
SPQ
SOT-223
NDC
5
1000
330.0
16.4
LP3855EMPX-5.0/NOPB SOT-223
NDC
5
2000
330.0
16.4
LP3855EMP-5.0/NOPB
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
7.0
7.5
2.2
12.0
16.0
Q3
7.0
7.5
2.2
12.0
16.0
Q3
LP3855ESX-1.8/NOPB
DDPAK/
TO-263
KTT
5
500
330.0
24.4
10.75
14.85
5.0
16.0
24.0
Q2
LP3855ESX-2.5/NOPB
DDPAK/
TO-263
KTT
5
500
330.0
24.4
10.75
14.85
5.0
16.0
24.0
Q2
LP3855ESX-3.3/NOPB
DDPAK/
TO-263
KTT
5
500
330.0
24.4
10.75
14.85
5.0
16.0
24.0
Q2
LP3855ESX-5.0/NOPB
DDPAK/
TO-263
KTT
5
500
330.0
24.4
10.75
14.85
5.0
16.0
24.0
Q2
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP3852EMP-1.8
SOT-223
NDC
5
1000
367.0
367.0
35.0
LP3852EMP-1.8/NOPB
SOT-223
NDC
5
1000
367.0
367.0
35.0
LP3852EMP-2.5
SOT-223
NDC
5
1000
367.0
367.0
35.0
LP3852EMP-2.5/NOPB
SOT-223
NDC
5
1000
367.0
367.0
35.0
LP3852EMP-3.3
SOT-223
NDC
5
1000
367.0
367.0
35.0
LP3852EMP-3.3/NOPB
SOT-223
NDC
5
1000
367.0
367.0
35.0
LP3852EMP-5.0/NOPB
SOT-223
NDC
5
1000
367.0
367.0
35.0
LP3852EMPX-1.8/NOPB
SOT-223
NDC
5
2000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP3852ESX-1.8/NOPB
DDPAK/TO-263
KTT
5
500
367.0
367.0
45.0
LP3852ESX-2.5/NOPB
DDPAK/TO-263
KTT
5
500
367.0
367.0
45.0
LP3852ESX-3.3/NOPB
DDPAK/TO-263
KTT
5
500
367.0
367.0
45.0
LP3852ESX-5.0/NOPB
DDPAK/TO-263
KTT
5
500
367.0
367.0
45.0
LP3855EMP-1.8/NOPB
SOT-223
NDC
5
1000
367.0
367.0
35.0
LP3855EMP-2.5/NOPB
SOT-223
NDC
5
1000
367.0
367.0
35.0
LP3855EMP-3.3/NOPB
SOT-223
NDC
5
1000
367.0
367.0
35.0
LP3855EMP-5.0/NOPB
SOT-223
NDC
5
1000
367.0
367.0
35.0
LP3855EMPX-5.0/NOPB
SOT-223
NDC
5
2000
367.0
367.0
35.0
LP3855ESX-1.8/NOPB
DDPAK/TO-263
KTT
5
500
367.0
367.0
45.0
LP3855ESX-2.5/NOPB
DDPAK/TO-263
KTT
5
500
367.0
367.0
45.0
LP3855ESX-3.3/NOPB
DDPAK/TO-263
KTT
5
500
367.0
367.0
45.0
LP3855ESX-5.0/NOPB
DDPAK/TO-263
KTT
5
500
367.0
367.0
45.0
Pack Materials-Page 3
MECHANICAL DATA
NDH0005D
www.ti.com
MECHANICAL DATA
NDC0005A
www.ti.com
MECHANICAL DATA
KTT0005B
TS5B (Rev D)
BOTTOM SIDE OF PACKAGE
www.ti.com
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