REJ09B0466-0100 16 H8S/2426, H8S/2426R, H8S/2424 Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2400 Series H8S/2426 H8S/2426R H8S/2424 R4F2426 R4S2426 R4F2426R R4S2426R R4F2424 R4S2424 All information contained in this material, including products and product specifications at the time of publication of this material, is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). Rev.1.00 Revision Date: Sep. 19, 2008 Rev. 1.00 Sep. 19, 2008 Page ii of xxviii Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. 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With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev. 1.00 Sep. 19, 2008 Page iii of xxviii General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products. Rev. 1.00 Sep. 19, 2008 Page iv of xxviii How to Use This Manual 1. Objective and Target Users This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and microcomputers. This manual is organized in the following items: an overview of the product, descriptions of the CPU, system control functions, and peripheral functions, electrical characteristics of the device, and usage notes. When designing an application system that includes this LSI, take all points to note into account. Points to note are given in their contexts and at the final part of each section, and in the section giving usage notes. The list of revisions is a summary of major points of revision or addition for earlier versions. It does not cover all revised items. For details on the revised points, see the actual locations in the manual. The following documents have been prepared for the H8S/2426, H8S/2426R, H8S/2424 Group. Before using any of the documents, please visit our web site to verify that you have the most up-to-date available version of the document. Document Type Contents Document Title Document No. Data Sheet Overview of hardware and electrical characteristics Hardware Manual Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, and timing charts) and descriptions of operation H8S/2426, H8S/2426R, H8S/2424 Group Hardware Manual Software Manual Detailed descriptions of the CPU and instruction set H8S/2600 Series REJ09B0139 H8S/2000 Series Software Manual Application Note Examples of applications and sample programs The latest versions are available from our web site. Renesas Technical Update Preliminary report on the specifications of a product, document, etc. This manual Rev. 1.00 Sep. 19, 2008 Page v of xxviii 2. Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name". (2) Register notation The style "register name"_"instance number" is used in cases where there is more than one instance of the same function or similar functions. [Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0. (3) Number notation Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary), hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn. [Examples] Binary: B'11 or 11 Hexadecimal: H'EFA0 or 0xEFA0 Decimal: 1234 (4) Notation for active-low An overbar on the name indicates that a signal or pin is active-low. [Example] WDTOVF (4) (2) 14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1) CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0. 14.3 Operation 14.3.1 Interval Count Operation When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time, a f/4 clock is selected. Rev. 0.50, 10/04, page 416 of 914 (3) Note: The bit names and sentences in the above figure are examples and have nothing to do with the contents of this manual. Rev. 1.00 Sep. 19, 2008 Page vi of xxviii 3. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. (1) [Table of Bits] Bit (2) (3) (4) (5) Bit Name − − Initial Value R/W Description 0 0 R R Reserved These bits are always read as 0. 13 to 11 ASID2 to ASID0 All 0 R/W Address Identifier These bits enable or disable the pin function. 10 − 0 R Reserved This bit is always read as 0. 9 − 1 R Reserved This bit is always read as 1. − 0 15 14 Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this manual. (1) Bit Indicates the bit number or numbers. In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case of a 16-bit register, the bits are arranged in order from 15 to 0. (2) Bit name Indicates the name of the bit or bit field. When the number of bits has to be clearly indicated in the field, appropriate notation is included (e.g., ASID[3:0]). A reserved bit is indicated by "−". Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such cases, the entry under Bit Name is blank. (3) Initial value Indicates the value of each bit immediately after a power-on reset, i.e., the initial value. 0: The initial value is 0 1: The initial value is 1 −: The initial value is undefined (4) R/W For each bit and bit field, this entry indicates whether the bit or field is readable or writable, or both writing to and reading from the bit or field are impossible. The notation is as follows: R/W: The bit or field is readable and writable. R/(W): The bit or field is readable and writable. However, writing is only performed to flag clearing. R: The bit or field is readable. "R" is indicated for all reserved bits. When writing to the register, write the value under Initial Value in the bit chart to reserved bits or fields. W: The bit or field is writable. (5) Description Describes the function of the bit or field and specifies the values for writing. Rev. 1.00 Sep. 19, 2008 Page vii of xxviii 4. Description of Abbreviations The abbreviations used in this manual are listed below. • Abbreviations specific to this product Abbreviation Description BSC Bus controller CPG INT SCI TMR TPU WDT Clock pulse generator Interrupt controller Serial communication interface 8-bit timer 16-bit timer pulse unit Watchdog timer • Abbreviations other than those listed above Abbreviation Description ACIA Asynchronous communication interface adapter bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO Bits per second Cyclic redundancy check Direct memory access Direct memory access controller Global System for Mobile Communications High impedance Inter Equipment Bus (IEBus is a trademark of NEC Electronics Corporation.) Input/output Infrared Data Association Least significant bit Most significant bit No connection Phase-locked loop Pulse width modulation Special function register Subscriber Identity Module Universal asynchronous receiver/transmitter Voltage-controlled oscillator All trademarks and registered trademarks are the property of their respective owners. Rev. 1.00 Sep. 19, 2008 Page viii of xxviii Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 Features.................................................................................................................................. 1 1.1.1 Applications.............................................................................................................. 1 1.1.2 Overview of Specifications....................................................................................... 1 List of Products...................................................................................................................... 8 Block Diagrams ..................................................................................................................... 9 Pin Description .................................................................................................................... 11 1.4.1 Pin Assignments ..................................................................................................... 11 1.4.2 Pin Assignments in Each Operating Mode ............................................................. 14 1.4.3 Pin Functions .......................................................................................................... 28 Section 2 CPU......................................................................................................41 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Features................................................................................................................................ 41 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................... 42 2.1.2 Differences from H8/300 CPU ............................................................................... 43 2.1.3 Differences from H8/300H CPU ............................................................................ 44 CPU Operating Modes......................................................................................................... 45 2.2.1 Normal Mode.......................................................................................................... 45 2.2.2 Advanced Mode...................................................................................................... 47 Address Space...................................................................................................................... 49 Registers .............................................................................................................................. 50 2.4.1 General Registers.................................................................................................... 51 2.4.2 Program Counter (PC) ............................................................................................ 52 2.4.3 Extended Register (EXR) ....................................................................................... 52 2.4.4 Condition-Code Register (CCR)............................................................................. 53 2.4.5 Multiply-Accumulate Register (MAC)................................................................... 54 2.4.6 Initial Values of CPU Internal Registers................................................................. 54 Data Formats........................................................................................................................ 55 2.5.1 General Register Data Formats............................................................................... 55 2.5.2 Memory Data Formats ............................................................................................ 57 Instruction Set ...................................................................................................................... 58 2.6.1 Table of Instructions Classified by Function .......................................................... 59 2.6.2 Basic Instruction Formats ....................................................................................... 68 Addressing Modes and Effective Address Calculation........................................................ 69 2.7.1 Register Direct—Rn ............................................................................................... 70 2.7.2 Register Indirect—@ERn....................................................................................... 70 Rev. 1.00 Sep. 19, 2008 Page ix of xxviii 2.8 2.9 2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)................. 70 2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn..... 71 2.7.5 Absolute Address—@aa:8 /@aa:16 / @aa:24 /@aa:32.......................................... 71 2.7.6 Immediate—#xx:8 / #xx:16/ #xx:32....................................................................... 72 2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) ...................................... 72 2.7.8 Memory Indirect—@@aa:8 ................................................................................... 72 2.7.9 Effective Address Calculation ................................................................................ 74 Processing States.................................................................................................................. 76 Usage Note........................................................................................................................... 78 2.9.1 Usage Notes on Bit-wise Operation Instructions .................................................... 78 Section 3 MCU Operating Modes .......................................................................79 3.1 3.2 3.3 3.4 Operating Mode Selection ................................................................................................... 79 Register Descriptions ........................................................................................................... 80 3.2.1 Mode Control Register (MDCR) ............................................................................ 80 3.2.2 System Control Register (SYSCR)......................................................................... 80 Operating Mode Descriptions .............................................................................................. 82 3.3.1 Mode 1.................................................................................................................... 82 3.3.2 Mode 2.................................................................................................................... 82 3.3.3 Mode 3.................................................................................................................... 82 3.3.4 Mode 4.................................................................................................................... 83 3.3.5 Mode 7.................................................................................................................... 83 3.3.6 Pin Functions .......................................................................................................... 84 Memory Map in Each Operating Mode ............................................................................... 84 Section 4 Exception Handling ............................................................................. 91 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 Exception Handling Types and Priority............................................................................... 91 Exception Sources and Exception Vector Table .................................................................. 92 Reset .................................................................................................................................... 94 4.3.1 Reset Exception Handling ...................................................................................... 94 4.3.2 Interrupts after Reset............................................................................................... 96 4.3.3 On-Chip Peripheral Functions after Reset Release................................................. 96 Trace Exception Handling ................................................................................................... 97 Interrupt Exception Handling .............................................................................................. 97 Trap Instruction Exception Handling................................................................................... 98 Illegal Instruction Exception Handling ................................................................................ 99 Stack Status after Exception Handling............................................................................... 100 Usage Note......................................................................................................................... 101 Rev. 1.00 Sep. 19, 2008 Page x of xxviii Section 5 Interrupt Controller ............................................................................103 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Features.............................................................................................................................. 103 Input/Output Pins............................................................................................................... 105 Register Descriptions ......................................................................................................... 106 5.3.1 Interrupt Control Register (INTCR) ..................................................................... 107 5.3.2 Interrupt Priority Registers A to N (IPRA to IPRN)............................................. 108 5.3.3 IRQ Enable Register (IER) ................................................................................... 110 5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)...................................... 112 5.3.5 IRQ Status Register (ISR)..................................................................................... 118 5.3.6 IRQ Pin Select Register (ITSR)............................................................................ 119 5.3.7 Software Standby Release IRQ Enable Register (SSIER) .................................... 122 Interrupt Sources................................................................................................................ 123 5.4.1 External Interrupts ................................................................................................ 123 5.4.2 Internal Interrupts ................................................................................................. 124 Interrupt Exception Handling Vector Table....................................................................... 125 Interrupt Control Modes and Interrupt Operation .............................................................. 132 5.6.1 Interrupt Control Mode 0...................................................................................... 133 5.6.2 Interrupt Control Mode 2...................................................................................... 135 5.6.3 Interrupt Exception Handling Sequence ............................................................... 137 5.6.4 Interrupt Response Times ..................................................................................... 139 5.6.5 DTC and DMAC Activation by Interrupt ............................................................. 140 Usage Notes ....................................................................................................................... 141 5.7.1 Conflict between Interrupt Generation and Disabling .......................................... 141 5.7.2 Instructions that Disable Interrupts....................................................................... 142 5.7.3 Times when Interrupts are Disabled ..................................................................... 142 5.7.4 Interrupts during Execution of EEPMOV Instruction .......................................... 142 5.7.5 Change of IRQ Pin Select Register (ITSR) Setting .............................................. 142 5.7.6 IRQ Status Register (ISR)..................................................................................... 143 Section 6 Bus Controller (BSC).........................................................................145 6.1 6.2 6.3 Features.............................................................................................................................. 145 Input/Output Pins............................................................................................................... 148 Register Descriptions ......................................................................................................... 151 6.3.1 Bus Width Control Register (ABWCR)................................................................ 152 6.3.2 Access State Control Register (ASTCR) .............................................................. 152 6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH, and WTCRBL) ........................................... 153 6.3.4 Read Strobe Timing Control Register (RDNCR) ................................................. 159 6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL).................... 161 Rev. 1.00 Sep. 19, 2008 Page xi of xxviii 6.3.6 6.4 6.5 6.6 6.7 Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL) .............................. 163 6.3.7 Bus Control Register (BCR) ................................................................................. 164 6.3.8 Address/Data Multiplexed I/O Control Register (MPXCR) ................................. 166 6.3.9 DRAM Control Register (DRAMCR) .................................................................. 167 6.3.10 DRAM Access Control Register (DRACCR)....................................................... 175 6.3.11 Refresh Control Register (REFCR) ...................................................................... 178 6.3.12 Refresh Timer Counter (RTCNT)......................................................................... 181 6.3.13 Refresh Time Constant Register (RTCOR) .......................................................... 181 Bus Control........................................................................................................................ 182 6.4.1 Area Division........................................................................................................ 182 6.4.2 Bus Specifications ................................................................................................ 183 6.4.3 Memory Interfaces................................................................................................ 185 6.4.4 Chip Select Signals ............................................................................................... 187 Basic Bus Interface ............................................................................................................ 188 6.5.1 Data Size and Data Alignment.............................................................................. 188 6.5.2 Valid Strobes ........................................................................................................ 189 6.5.3 Basic Timing......................................................................................................... 190 6.5.4 Wait Control ......................................................................................................... 198 6.5.5 Read Strobe (RD) Timing..................................................................................... 199 6.5.6 Extension of Chip Select (CS) Assertion Period................................................... 201 Address/Data Multiplexed I/O Interface............................................................................ 202 6.6.1 Setting Address/Data Multiplexed I/O Space ....................................................... 202 6.6.2 Address/Data Multiplexing................................................................................... 202 6.6.3 Data Bus ............................................................................................................... 203 6.6.4 Address Hold Signal ............................................................................................. 203 6.6.5 Basic Timing......................................................................................................... 203 6.6.6 Wait Control ......................................................................................................... 212 6.6.7 Read Strobe (RD) Timing..................................................................................... 213 6.6.8 Extension of Chip Select (CS) Assertion Period in Data Cycle............................ 214 DRAM Interface ................................................................................................................ 216 6.7.1 Setting DRAM Space............................................................................................ 216 6.7.2 Address Multiplexing ........................................................................................... 216 6.7.3 Data Bus ............................................................................................................... 217 6.7.4 Pins Used for DRAM Interface............................................................................. 218 6.7.5 Basic Timing......................................................................................................... 219 6.7.6 Column Address Output Cycle Control ................................................................ 221 6.7.7 Row Address Output State Control....................................................................... 222 6.7.8 Precharge State Control ........................................................................................ 224 6.7.9 Wait Control ......................................................................................................... 225 Rev. 1.00 Sep. 19, 2008 Page xii of xxviii 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.7.10 Byte Access Control ............................................................................................. 228 6.7.11 Burst Operation..................................................................................................... 229 6.7.12 Refresh Control..................................................................................................... 234 6.7.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface..... 240 Synchronous DRAM Interface........................................................................................... 243 6.8.1 Setting Continuous Synchronous DRAM Space................................................... 243 6.8.2 Address Multiplexing ........................................................................................... 244 6.8.3 Data Bus ............................................................................................................... 245 6.8.4 Pins Used for Synchronous DRAM Interface....................................................... 245 6.8.5 Synchronous DRAM Clock .................................................................................. 247 6.8.6 Basic Timing......................................................................................................... 247 6.8.7 CAS Latency Control............................................................................................ 249 6.8.8 Row Address Output State Control....................................................................... 251 6.8.9 Precharge State Count........................................................................................... 252 6.8.10 Bus Cycle Control in Write Cycle ........................................................................ 254 6.8.11 Byte Access Control ............................................................................................. 255 6.8.12 Burst Operation..................................................................................................... 258 6.8.13 Refresh Control..................................................................................................... 261 6.8.14 Mode Register Setting of Synchronous DRAM.................................................... 268 6.8.15 DMAC and EXDMAC Single Address Transfer Mode and Synchronous DRAM Interface ............................................................................. 269 Burst ROM Interface.......................................................................................................... 274 6.9.1 Basic Timing......................................................................................................... 274 6.9.2 Wait Control ......................................................................................................... 276 6.9.3 Write Access......................................................................................................... 276 Idle Cycle........................................................................................................................... 277 6.10.1 Operation .............................................................................................................. 277 6.10.2 Pin States in Idle Cycle......................................................................................... 296 Write Data Buffer Function ............................................................................................... 297 Bus Release........................................................................................................................ 298 6.12.1 Operation .............................................................................................................. 298 6.12.2 Pin States in External Bus Released State ............................................................ 299 6.12.3 Transition Timing ................................................................................................. 300 Bus Arbitration .................................................................................................................. 302 6.13.1 Operation .............................................................................................................. 302 6.13.2 Bus Transfer Timing............................................................................................. 303 Bus Controller Operation in Reset ..................................................................................... 304 Usage Notes ....................................................................................................................... 305 6.15.1 External Bus Release Function and All-Module-Clocks-Stopped Mode.............. 305 6.15.2 External Bus Release Function and Software Standby ......................................... 305 Rev. 1.00 Sep. 19, 2008 Page xiii of xxviii 6.15.3 External Bus Release Function and CBR Refreshing/Auto Refreshing................ 305 6.15.4 BREQO Output Timing ........................................................................................ 306 6.15.5 Notes on Usage of the Synchronous DRAM ........................................................ 306 Section 7 DMA Controller (DMAC).................................................................307 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Features.............................................................................................................................. 307 Input/Output Pins............................................................................................................... 309 Register Descriptions ......................................................................................................... 310 7.3.1 Memory Address Registers (MARA and MARB)................................................ 312 7.3.2 I/O Address Registers (IOARA and IOARB)....................................................... 313 7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) ................................... 313 7.3.4 DMA Control Registers (DMACRA and DMACRB) .......................................... 315 7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL).............. 323 7.3.6 DMA Write Enable Register (DMAWER)........................................................... 334 7.3.7 DMA Terminal Control Register (DMATCR) ..................................................... 336 Activation Sources............................................................................................................. 337 7.4.1 Activation by Internal Interrupt Request .............................................................. 338 7.4.2 Activation by Auto-Request ................................................................................. 339 Operation ........................................................................................................................... 339 7.5.1 Transfer Modes..................................................................................................... 339 7.5.2 Sequential Mode ................................................................................................... 342 7.5.3 Idle Mode.............................................................................................................. 345 7.5.4 Repeat Mode......................................................................................................... 348 7.5.5 Single Address Mode............................................................................................ 352 7.5.6 Normal Mode........................................................................................................ 355 7.5.7 Block Transfer Mode ............................................................................................ 359 7.5.8 Basic Bus Cycles .................................................................................................. 365 7.5.9 DMA Transfer (Dual Address Mode) Bus Cycles................................................ 366 7.5.10 DMA Transfer (Single Address Mode) Bus Cycles ............................................. 374 7.5.11 Write Data Buffer Function .................................................................................. 380 7.5.12 Multi-Channel Operation...................................................................................... 381 7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles, and EXDMAC ............................................................................ 383 7.5.14 DMAC and NMI Interrupts .................................................................................. 384 7.5.15 Forced Termination of DMAC Operation ............................................................ 385 7.5.16 Clearing Full Address Mode................................................................................. 386 Interrupt Sources................................................................................................................ 387 Usage Notes ....................................................................................................................... 388 Rev. 1.00 Sep. 19, 2008 Page xiv of xxviii Section 8 EXDMA Controller (EXDMAC) ......................................................393 8.1 8.2 8.3 8.4 8.5 8.6 Features.............................................................................................................................. 393 Input/Output Pins............................................................................................................... 395 Register Descriptions ......................................................................................................... 396 8.3.1 EXDMA Source Address Register (EDSAR)....................................................... 396 8.3.2 EXDMA Destination Address Register (EDDAR)............................................... 397 8.3.3 EXDMA Transfer Count Register (EDTCR)........................................................ 397 8.3.4 EXDMA Mode Control Register (EDMDR) ........................................................ 399 8.3.5 EXDMA Address Control Register (EDACR) ..................................................... 404 Operation ........................................................................................................................... 408 8.4.1 Transfer Modes..................................................................................................... 408 8.4.2 Address Modes ..................................................................................................... 409 8.4.3 DMA Transfer Requests ....................................................................................... 413 8.4.4 Bus Modes ............................................................................................................ 414 8.4.5 Transfer Modes..................................................................................................... 416 8.4.6 Repeat Area Function ........................................................................................... 418 8.4.7 Registers during DMA Transfer Operation .......................................................... 421 8.4.8 Channel Priority Order.......................................................................................... 425 8.4.9 EXDMAC Bus Cycles (Dual Address Mode) ...................................................... 428 8.4.10 EXDMAC Bus Cycles (Single Address Mode) .................................................... 435 8.4.11 Examples of Operation Timing in Each Mode ..................................................... 440 8.4.12 Ending DMA Transfer .......................................................................................... 454 8.4.13 Relationship between EXDMAC and Other Bus Masters .................................... 455 Interrupt Sources................................................................................................................ 456 Usage Notes ....................................................................................................................... 458 Section 9 Data Transfer Controller (DTC) ........................................................461 9.1 9.2 9.3 Features.............................................................................................................................. 461 Register Descriptions ......................................................................................................... 463 9.2.1 DTC Mode Register A (MRA) ............................................................................. 463 9.2.2 DTC Mode Register B (MRB).............................................................................. 465 9.2.3 DTC Source Address Register (SAR)................................................................... 465 9.2.4 DTC Destination Address Register (DAR)........................................................... 465 9.2.5 DTC Transfer Count Register A (CRA) ............................................................... 466 9.2.6 DTC Transfer Count Register B (CRB)................................................................ 466 9.2.7 DTC Enable Registers A to I (DTCERA to DTCERI) ......................................... 467 9.2.8 DTC Vector Register (DTVECR)......................................................................... 467 9.2.9 DTC Control Register (DTCCR) .......................................................................... 468 Activation Sources............................................................................................................. 469 Rev. 1.00 Sep. 19, 2008 Page xv of xxviii 9.4 9.5 9.6 9.7 9.8 Location of Register Information and DTC Vector Table ................................................. 471 Operation ........................................................................................................................... 475 9.5.1 Normal Mode........................................................................................................ 478 9.5.2 Repeat Mode......................................................................................................... 479 9.5.3 Block Transfer Mode ............................................................................................ 480 9.5.4 Chain Transfer ...................................................................................................... 481 9.5.5 Interrupt Sources................................................................................................... 482 9.5.6 Operation Timing.................................................................................................. 482 9.5.7 Number of DTC Execution States ........................................................................ 483 Procedures for Using DTC................................................................................................. 485 9.6.1 Activation by Interrupt.......................................................................................... 485 9.6.2 Activation by Software ......................................................................................... 485 Examples of Use of the DTC ............................................................................................. 486 9.7.1 Normal Mode........................................................................................................ 486 9.7.2 Chain Transfer ...................................................................................................... 487 9.7.3 Chain Transfer when Counter = 0......................................................................... 488 9.7.4 Software Activation .............................................................................................. 490 Usage Notes ....................................................................................................................... 491 9.8.1 Module Stop Mode Setting ................................................................................... 491 9.8.2 On-Chip RAM ...................................................................................................... 491 9.8.3 DTCE Bit Setting.................................................................................................. 491 9.8.4 DMAC Transfer End Interrupt.............................................................................. 491 9.8.5 Chain Transfer ...................................................................................................... 491 Section 10 I/O Ports........................................................................................... 493 10.1 Port 1.................................................................................................................................. 502 10.1.1 Port 1 Data Direction Register (P1DDR).............................................................. 502 10.1.2 Port 1 Data Register (P1DR)................................................................................. 503 10.1.3 Port 1 Register (PORT1)....................................................................................... 503 10.1.4 Port 1 Open Drain Control Register (P1ODR) ..................................................... 504 10.1.5 Pin Functions ........................................................................................................ 504 10.2 Port 2.................................................................................................................................. 528 10.2.1 Port 2 Data Direction Register (P2DDR).............................................................. 528 10.2.2 Port 2 Data Register (P2DR)................................................................................. 529 10.2.3 Port 2 Register (PORT2)....................................................................................... 529 10.2.4 Port 2 Open Drain Control Register (P2ODR) ..................................................... 530 10.2.5 Pin Functions ........................................................................................................ 531 10.3 Port 3.................................................................................................................................. 549 10.3.1 Port 3 Data Direction Register (P3DDR).............................................................. 549 10.3.2 Port 3 Data Register (P3DR)................................................................................. 550 Rev. 1.00 Sep. 19, 2008 Page xvi of xxviii 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.3.3 Port 3 Register (PORT3)....................................................................................... 550 10.3.4 Port 3 Open Drain Control Register (P3ODR) ..................................................... 551 10.3.5 Pin Functions ........................................................................................................ 551 Port 4.................................................................................................................................. 555 10.4.1 Port 4 Register (PORT4)....................................................................................... 555 10.4.2 Pin Functions ........................................................................................................ 555 Port 5.................................................................................................................................. 557 10.5.1 Port 5 Data Direction Register (P5DDR).............................................................. 557 10.5.2 Port 5 Data Register (P5DR)................................................................................. 557 10.5.3 Port 5 Register (PORT5)....................................................................................... 558 10.5.4 Port 5 Open Drain Control Register (P5ODR) ..................................................... 558 10.5.5 Pin Functions ........................................................................................................ 559 Port 6.................................................................................................................................. 566 10.6.1 Port 6 Data Direction Register (P6DDR).............................................................. 566 10.6.2 Port 6 Data Register (P6DR)................................................................................. 567 10.6.3 Port 6 Register (PORT6)....................................................................................... 567 10.6.4 Port 6 Open Drain Control Register (P6ODR) ..................................................... 568 10.6.5 Pin Functions ........................................................................................................ 568 Port 8.................................................................................................................................. 572 10.7.1 Port 8 Data Direction Register (P8DDR).............................................................. 572 10.7.2 Port 8 Data Register (P8DR)................................................................................. 573 10.7.3 Port 8 Register (PORT8)....................................................................................... 573 10.7.4 Port 8 Open Drain Control Register (P8ODR) ..................................................... 574 10.7.5 Pin Functions ........................................................................................................ 574 Port 9.................................................................................................................................. 584 10.8.1 Port 9 Register (PORT9)....................................................................................... 584 10.8.2 Pin Functions ........................................................................................................ 585 Port A................................................................................................................................. 587 10.9.1 Port A Data Direction Register (PADDR)............................................................ 588 10.9.2 Port A Data Register (PADR)............................................................................... 589 10.9.3 Port A Register (PORTA)..................................................................................... 589 10.9.4 Port A Pull-Up MOS Control Register (PAPCR) ................................................. 590 10.9.5 Port A Open Drain Control Register (PAODR).................................................... 590 10.9.6 Pin Functions ........................................................................................................ 591 10.9.7 Port A Input Pull-Up MOS States......................................................................... 600 Port B ................................................................................................................................. 601 10.10.1 Port B Data Direction Register (PBDDR) ............................................................ 601 10.10.2 Port B Data Register (PBDR) ............................................................................... 602 10.10.3 Port B Register (PORTB) ..................................................................................... 602 10.10.4 Port B Pull-Up MOS Control Register (PBPCR) ................................................. 603 Rev. 1.00 Sep. 19, 2008 Page xvii of xxviii 10.11 10.12 10.13 10.14 10.15 10.10.5 Port B Open Drain Control Register (PBODR) .................................................... 603 10.10.6 Pin Functions ........................................................................................................ 604 10.10.7 Port B Input Pull-Up MOS States......................................................................... 612 Port C ................................................................................................................................. 613 10.11.1 Port C Data Direction Register (PCDDR) ............................................................ 613 10.11.2 Port C Data Register (PCDR) ............................................................................... 614 10.11.3 Port C Register (PORTC) ..................................................................................... 614 10.11.4 Port C Pull-Up MOS Control Register (PCPCR) ................................................. 615 10.11.5 Port C Open Drain Control Register (PCODR) .................................................... 615 10.11.6 Pin Functions ........................................................................................................ 616 10.11.7 Port C Input Pull-Up MOS States......................................................................... 624 Port D................................................................................................................................. 625 10.12.1 Port D Data Direction Register (PDDDR)............................................................ 625 10.12.2 Port D Data Register (PDDR)............................................................................... 626 10.12.3 Port D Register (PORTD)..................................................................................... 626 10.12.4 Port D Pull-Up MOS Control Register (PDPCR) ................................................. 627 10.12.5 Port D Open Drain Control Register (PDODR).................................................... 627 10.12.6 Pin Functions ........................................................................................................ 628 10.12.7 Port D Input Pull-Up MOS States......................................................................... 628 Port E ................................................................................................................................. 629 10.13.1 Port E Data Direction Register (PEDDR)............................................................. 629 10.13.2 Port E Data Register (PEDR)................................................................................ 630 10.13.3 Port E Register (PORTE)...................................................................................... 630 10.13.4 Port E Pull-Up MOS Control Register (PEPCR).................................................. 631 10.13.5 Port E Open Drain Control Register (PEODR) .................................................... 631 10.13.6 Pin Functions ........................................................................................................ 632 10.13.7 Port E Input Pull-Up MOS States ......................................................................... 632 Port F ................................................................................................................................. 633 10.14.1 Port F Data Direction Register (PFDDR) ............................................................. 634 10.14.2 Port F Data Register (PFDR) ................................................................................ 635 10.14.3 Port F Register (PORTF) ...................................................................................... 635 10.14.4 Port F Open Drain Control Register (PFODR) ..................................................... 636 10.14.5 Pin Functions ........................................................................................................ 636 Port G................................................................................................................................. 647 10.15.1 Port G Data Direction Register (PGDDR)............................................................ 647 10.15.2 Port G Data Register (PGDR)............................................................................... 648 10.15.3 Port G Register (PORTG)..................................................................................... 648 10.15.4 Port G Open Drain Control Register (PGODR).................................................... 649 10.15.5 Pin Functions ........................................................................................................ 650 Rev. 1.00 Sep. 19, 2008 Page xviii of xxviii 10.16 Port H................................................................................................................................. 654 10.16.1 Port H Data Direction Register (PHDDR)............................................................ 654 10.16.2 Port H Data Register (PHDR)............................................................................... 656 10.16.3 Port H Register (PORTH)..................................................................................... 656 10.16.4 Port H Open Drain Control Register (PHODR).................................................... 657 10.16.5 Pin Functions ........................................................................................................ 658 10.17 Port J .................................................................................................................................. 661 10.17.1 Port J Data Direction Register (PJDDR)............................................................... 661 10.17.2 Port J Data Register (PJDR) ................................................................................. 661 10.17.3 Port J Register (PORTJ) ....................................................................................... 662 10.17.4 Port J Open Drain Control Register (PJODR) ...................................................... 662 10.17.5 Pin Functions ........................................................................................................ 663 10.18 Port Function Control Registers......................................................................................... 664 10.18.1 Port Function Control Register 0 (PFCR0)........................................................... 664 10.18.2 Port Function Control Register 1 (PFCR1)........................................................... 665 10.18.3 Port Function Control Register 2 (PFCR2)........................................................... 667 10.18.4 Port Function Control Register 3 (PFCR3)........................................................... 668 10.18.5 Port Function Control Register 4 (PFCR4)........................................................... 669 10.18.6 Port Function Control Register 5 (PFCR5)........................................................... 671 Section 11 16-Bit Timer Pulse Unit (TPU) .......................................................673 11.1 Features.............................................................................................................................. 673 11.2 Input/Output Pins............................................................................................................... 680 11.3 Register Descriptions ......................................................................................................... 683 11.3.1 Timer Control Register (TCR).............................................................................. 688 11.3.2 Timer Mode Register (TMDR)............................................................................. 693 11.3.3 Timer I/O Control Register (TIOR)...................................................................... 694 11.3.4 Timer Interrupt Enable Register (TIER)............................................................... 712 11.3.5 Timer Status Register (TSR)................................................................................. 714 11.3.6 Timer Counter (TCNT)......................................................................................... 717 11.3.7 Timer General Register (TGR) ............................................................................. 717 11.3.8 Timer Start Register (TSTR) ................................................................................ 717 11.3.9 Timer Synchronous Register (TSYR)................................................................... 718 11.3.10 Timer Start Register B (TSTRB) .......................................................................... 719 11.3.11 Timer Synchronous Register B (TSYRB) ............................................................ 720 11.4 Operation ........................................................................................................................... 721 11.4.1 Basic Functions..................................................................................................... 721 11.4.2 Synchronous Operation......................................................................................... 728 11.4.3 Buffer Operation................................................................................................... 731 11.4.4 Cascaded Operation .............................................................................................. 735 Rev. 1.00 Sep. 19, 2008 Page xix of xxviii 11.5 11.6 11.7 11.8 11.9 11.10 11.4.5 PWM Modes......................................................................................................... 737 11.4.6 Phase Counting Mode......................................................................................... 743 Interrupt Sources................................................................................................................ 750 DTC Activation.................................................................................................................. 753 DMAC Activation.............................................................................................................. 753 A/D Converter Activation.................................................................................................. 754 Operation Timing............................................................................................................... 754 11.9.1 Input/Output Timing ........................................................................................... 754 11.9.2 Interrupt Signal Timing ...................................................................................... 758 Usage Notes ....................................................................................................................... 762 11.10.1 Module Stop Mode Setting ................................................................................. 762 11.10.2 Input Clock Restrictions ..................................................................................... 762 11.10.3 Caution on Cycle Setting .................................................................................... 763 11.10.4 Contention between TCNT Write and Clear Operations .................................... 763 11.10.5 Contention between TCNT Write and Increment Operations............................. 764 11.10.6 Contention between TGR Write and Compare Match ........................................ 765 11.10.7 Contention between Buffer Register Write and Compare Match ....................... 766 11.10.8 Contention between TGR Read and Input Capture............................................. 767 11.10.9 Contention between TGR Write and Input Capture............................................ 768 11.10.10 Contention between Buffer Register Write and Input Capture ........................... 769 11.10.11 Contention between Overflow/Underflow and Counter Clearing....................... 770 11.10.12 Contention between TCNT Write and Overflow/Underflow.............................. 771 11.10.13 Multiplexing of I/O Pins ..................................................................................... 771 11.10.14 Interrupts and Module Stop Mode ...................................................................... 771 Section 12 Programmable Pulse Generator (PPG) ............................................ 773 12.1 Features.............................................................................................................................. 773 12.2 Input/Output Pins............................................................................................................... 775 12.3 Register Descriptions ......................................................................................................... 775 12.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ....................................... 776 12.3.2 Output Data Registers H, L (PODRH, PODRL)................................................. 777 12.3.3 Next Data Registers H, L (NDRH, NDRL) ........................................................ 778 12.3.4 PPG Output Control Register (PCR) .................................................................. 781 12.3.5 PPG Output Mode Register (PMR) .................................................................... 782 12.4 Operation ........................................................................................................................... 784 12.4.1 Output Timing .................................................................................................... 785 12.4.2 Sample Setup Procedure for Normal Pulse Output............................................. 786 12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output)......... 787 12.4.4 Non-Overlapping Pulse Output........................................................................... 788 12.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output ............................. 790 Rev. 1.00 Sep. 19, 2008 Page xx of xxviii 12.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) .................. 791 12.4.7 Inverted Pulse Output ........................................................................................... 793 12.4.8 Pulse Output Triggered by Input Capture ............................................................. 794 12.5 Usage Notes ....................................................................................................................... 795 12.5.1 Module Stop Mode Setting ................................................................................... 795 12.5.2 Operation of Pulse Output Pins............................................................................. 795 Section 13 8-Bit Timers (TMR).........................................................................797 13.1 Features.............................................................................................................................. 797 13.2 Input/Output Pins............................................................................................................... 799 13.3 Register Descriptions ......................................................................................................... 799 13.3.1 Timer Counter (TCNT)......................................................................................... 800 13.3.2 Time Constant Register A (TCORA).................................................................... 800 13.3.3 Time Constant Register B (TCORB) .................................................................... 800 13.3.4 Timer Control Register (TCR).............................................................................. 801 13.3.5 Timer Counter Control Register (TCCR) ............................................................. 802 13.3.6 Timer Control/Status Register (TCSR)................................................................. 804 13.4 Operation ........................................................................................................................... 808 13.4.1 Pulse Output.......................................................................................................... 808 13.4.2 Reset Input ............................................................................................................ 809 13.5 Operation Timing............................................................................................................... 810 13.5.1 TCNT Incrementation Timing .............................................................................. 810 13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs .................. 811 13.5.3 Timing of Timer Output when Compare-Match Occurs....................................... 812 13.5.4 Timing of Compare Match Clear.......................................................................... 812 13.5.5 Timing of TCNT External Reset........................................................................... 813 13.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 813 13.6 Operation with Cascaded Connection................................................................................ 814 13.6.1 16-Bit Counter Mode ............................................................................................ 814 13.6.2 Compare Match Count Mode................................................................................ 814 13.7 Interrupt Sources................................................................................................................ 815 13.7.1 Interrupt Sources and DTC Activation ................................................................. 815 13.7.2 A/D Converter Activation..................................................................................... 815 13.8 Usage Notes ....................................................................................................................... 816 13.8.1 Contention between TCNT Write and Clear......................................................... 816 13.8.2 Contention between TCNT Write and Increment ................................................. 817 13.8.3 Contention between TCOR Write and Compare Match ....................................... 818 13.8.4 Contention between Compare Matches A and B .................................................. 819 13.8.5 Switching of Internal Clocks and TCNT Operation ............................................. 819 Rev. 1.00 Sep. 19, 2008 Page xxi of xxviii 13.8.6 Mode Setting with Cascaded Connection ............................................................. 821 13.8.7 Module Stop Mode Setting ................................................................................... 821 13.8.8 Interrupts in Module Stop Mode........................................................................... 821 Section 14 Watchdog Timer (WDT) ................................................................. 823 14.1 Features.............................................................................................................................. 823 14.2 Input/Output Pin ................................................................................................................ 824 14.3 Register Descriptions ......................................................................................................... 825 14.3.1 Timer Counter (TCNT)......................................................................................... 825 14.3.2 Timer Control/Status Register (TCSR)................................................................. 825 14.3.3 Reset Control/Status Register (RSTCSR)............................................................. 827 14.4 Operation ........................................................................................................................... 828 14.4.1 Watchdog Timer Mode......................................................................................... 828 14.4.2 Interval Timer Mode............................................................................................. 829 14.5 Interrupt Source ................................................................................................................. 831 14.6 Usage Notes ....................................................................................................................... 831 14.6.1 Notes on Register Access ..................................................................................... 831 14.6.2 Contention between Timer Counter (TCNT) Write and Increment ...................... 833 14.6.3 Changing Value of CKS2 to CKS0 ...................................................................... 833 14.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................. 833 14.6.5 Internal Reset in Watchdog Timer Mode.............................................................. 834 14.6.6 System Reset by WDTOVF Signal....................................................................... 834 Section 15 Serial Communication Interface (SCI, IrDA) ................................. 835 15.1 Features.............................................................................................................................. 835 15.2 Input/Output Pins............................................................................................................... 838 15.3 Register Descriptions ......................................................................................................... 839 15.3.1 Receive Shift Register (RSR) ............................................................................... 840 15.3.2 Receive Data Register (RDR)............................................................................... 840 15.3.3 Transmit Data Register (TDR).............................................................................. 841 15.3.4 Transmit Shift Register (TSR) .............................................................................. 841 15.3.5 Serial Mode Register (SMR) ................................................................................ 841 15.3.6 Serial Control Register (SCR) .............................................................................. 845 15.3.7 Serial Status Register (SSR) ................................................................................. 850 15.3.8 Smart Card Mode Register (SCMR)..................................................................... 858 15.3.9 Bit Rate Register (BRR) ....................................................................................... 859 15.3.10 IrDA Control Register (IrCR)............................................................................... 866 15.3.11 Serial Extension Mode Register (SEMR) ............................................................. 867 15.4 Operation in Asynchronous Mode ..................................................................................... 869 15.4.1 Data Transfer Format............................................................................................ 869 Rev. 1.00 Sep. 19, 2008 Page xxii of xxviii 15.5 15.6 15.7 15.8 15.9 15.10 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ............................................................................................. 871 15.4.3 Clock..................................................................................................................... 872 15.4.4 SCI Initialization (Asynchronous Mode).............................................................. 873 15.4.5 Data Transmission (Asynchronous Mode) ........................................................... 874 15.4.6 Serial Data Reception (Asynchronous Mode) ...................................................... 876 Multiprocessor Communication Function.......................................................................... 880 15.5.1 Multiprocessor Serial Data Transmission ............................................................. 881 15.5.2 Multiprocessor Serial Data Reception .................................................................. 883 Operation in Clocked Synchronous Mode ......................................................................... 887 15.6.1 Clock..................................................................................................................... 887 15.6.2 SCI Initialization (Clocked Synchronous Mode).................................................. 888 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) ..................................... 888 15.6.4 Serial Data Reception (Clocked Synchronous Mode) .......................................... 891 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) .............................................................................. 893 Operation in Smart Card Interface Mode........................................................................... 895 15.7.1 Pin Connection Example ...................................................................................... 895 15.7.2 Data Format (Except for Block Transfer Mode)................................................... 896 15.7.3 Block Transfer Mode ............................................................................................ 897 15.7.4 Receive Data Sampling Timing and Reception Margin ....................................... 898 15.7.5 Initialization.......................................................................................................... 900 15.7.6 Data Transmission (Except for Block Transfer Mode)......................................... 900 15.7.7 Serial Data Reception (Except for Block Transfer Mode).................................... 904 15.7.8 Clock Output Control............................................................................................ 906 IrDA Operation .................................................................................................................. 908 Interrupt Sources................................................................................................................ 911 15.9.1 Interrupts in Normal Serial Communication Interface Mode ............................... 911 15.9.2 Interrupts in Smart Card Interface Mode .............................................................. 913 Usage Notes ....................................................................................................................... 915 15.10.1 Module Stop Mode Setting ................................................................................... 915 15.10.2 Break Detection and Processing ........................................................................... 915 15.10.3 Mark State and Break Sending ............................................................................. 915 15.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) ..................................................................... 915 15.10.5 Relation between Writes to TDR and the TDRE Flag .......................................... 916 15.10.6 Restrictions on Use of DMAC or DTC................................................................. 916 15.10.7 Operation in Case of Mode Transition.................................................................. 917 Rev. 1.00 Sep. 19, 2008 Page xxiii of xxviii Section 16 I2C Bus Interface 2 (IIC2)................................................................921 16.1 Features.............................................................................................................................. 921 16.2 Input/Output Pins............................................................................................................... 923 16.3 Register Descriptions ......................................................................................................... 924 16.3.1 I2C Bus Control Register A (ICCRA) ................................................................... 926 16.3.2 I2C Bus Control Register B (ICCRB) ................................................................... 928 16.3.3 I2C Bus Mode Register (ICMR)............................................................................ 929 16.3.4 I2C Bus Interrupt Enable Register (ICIER)........................................................... 931 16.3.5 I2C Bus Status Register (ICSR)............................................................................. 933 16.3.6 Slave Address Register (SAR).............................................................................. 935 16.3.7 I2C Bus Transmit Data Register (ICDRT) ............................................................ 936 16.3.8 I2C Bus Receive Data Register (ICDRR).............................................................. 936 16.3.9 I2C Bus Shift Register (ICDRS)............................................................................ 936 16.4 Operation ........................................................................................................................... 937 16.4.1 I2C Bus Format...................................................................................................... 937 16.4.2 Master Transmit Operation................................................................................... 938 16.4.3 Master Receive Operation .................................................................................... 940 16.4.4 Slave Transmit Operation ..................................................................................... 942 16.4.5 Slave Receive Operation....................................................................................... 945 16.4.6 Noise Canceler...................................................................................................... 947 16.4.7 Example of Use..................................................................................................... 947 16.5 Interrupt Request................................................................................................................ 952 16.6 Bit Synchronous Circuit..................................................................................................... 953 16.7 Usage Notes ....................................................................................................................... 954 Section 17 A/D Converter .................................................................................955 17.1 Features.............................................................................................................................. 955 17.2 Input/Output Pins............................................................................................................... 958 17.3 Register Descriptions ......................................................................................................... 960 17.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 961 17.3.2 A/D Control/Status Register for Unit 0 (ADCSR_0)............................................ 963 17.3.3 A/D Control/Status Register for Unit 1 (ADCSR_1)............................................ 965 17.3.4 A/D Control Register (ADCR_0) Unit 0 .............................................................. 968 17.3.5 A/D Control Register (ADCR_1) Unit 1 .............................................................. 970 17.4 Operation ........................................................................................................................... 972 17.4.1 Single Mode.......................................................................................................... 972 17.4.2 Scan Mode ............................................................................................................ 974 17.4.3 Input Sampling and A/D Conversion Time .......................................................... 978 17.4.4 External Trigger Input Timing.............................................................................. 980 Rev. 1.00 Sep. 19, 2008 Page xxiv of xxviii 17.5 Interrupt Source ................................................................................................................. 981 17.6 A/D Conversion Accuracy Definitions .............................................................................. 982 17.7 Usage Notes ....................................................................................................................... 984 17.7.1 Module Stop Function Setting .............................................................................. 984 17.7.2 A/D Input Hold Function in Software Standby Mode .......................................... 984 17.7.3 Restarting the A/D Converter ............................................................................... 984 17.7.4 Permissible Signal Source Impedance .................................................................. 985 17.7.5 Influences on Absolute Accuracy ......................................................................... 986 17.7.6 Setting Range of Analog Power Supply and Other Pins....................................... 986 17.7.7 Notes on Board Design ......................................................................................... 987 17.7.8 Notes on Noise Countermeasures ......................................................................... 987 Section 18 D/A Converter..................................................................................989 18.1 Features.............................................................................................................................. 989 18.2 Input/Output Pins............................................................................................................... 991 18.3 Register Descriptions ......................................................................................................... 992 18.3.1 D/A Data Registers 2 and 3 (DADR2 and DADR3)............................................. 992 18.3.2 D/A Control Register 23 (DACR23) .................................................................... 992 18.4 Operation ........................................................................................................................... 995 18.5 Usage Notes ....................................................................................................................... 997 18.5.1 Setting for Module Stop Mode ............................................................................. 997 18.5.2 D/A Output Hold Function in Software Standby Mode........................................ 997 Section 19 Synchronous Serial Communication Unit (SSU) ............................999 19.1 Features.............................................................................................................................. 999 19.2 Input/Output Pins............................................................................................................. 1001 19.3 Register Descriptions ....................................................................................................... 1001 19.3.1 SS Control Register H (SSCRH) ........................................................................ 1002 19.3.2 SS Control Register L (SSCRL) ......................................................................... 1004 19.3.3 SS Mode Register (SSMR) ................................................................................. 1005 19.3.4 SS Enable Register (SSER) ................................................................................ 1006 19.3.5 SS Status Register (SSSR).................................................................................. 1007 19.3.6 SS Control Register 2 (SSCR2) .......................................................................... 1010 19.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................. 1012 19.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3).................................. 1013 19.3.9 SS Shift Register (SSTRSR)............................................................................... 1013 19.4 Operation ......................................................................................................................... 1014 19.4.1 Transfer Clock .................................................................................................... 1014 19.4.2 Relationship of Clock Phase, Polarity, and Data ................................................ 1014 19.4.3 Relationship between Data Input/Output Pins and Shift Register ...................... 1015 Rev. 1.00 Sep. 19, 2008 Page xxv of xxviii 19.4.4 Communication Modes and Pin Functions ......................................................... 1016 19.4.5 SSU Mode........................................................................................................... 1018 19.4.6 SCS Pin Control and Conflict Error.................................................................... 1029 19.4.7 Clock Synchronous Communication Mode ........................................................ 1030 19.5 Interrupt Requests ............................................................................................................ 1037 19.6 Usage Note....................................................................................................................... 1037 19.6.1 Setting of Module Stop Mode............................................................................. 1037 Section 20 RAM ..............................................................................................1039 Section 21 Flash Memory................................................................................1041 21.1 Memory Map ................................................................................................................... 1043 21.1.1 Boot Mode .......................................................................................................... 1043 21.2 Register Descriptions ....................................................................................................... 1044 21.2.1 Flash Memory Control Register 1 (FLMCR1).................................................... 1045 21.2.2 Flash Memory Data Block Protect Register (DFPR) .......................................... 1046 21.2.3 Flash Memory Status Register (FLMSTR)......................................................... 1047 21.3 On-Board Programming Mode ........................................................................................ 1048 21.3.1 SCI Boot Mode ................................................................................................... 1049 21.3.2 User Programming Mode.................................................................................... 1050 21.3.3 EW0 Mode.......................................................................................................... 1051 21.4 Notes on User Programming Mode ................................................................................. 1052 21.4.1 Prohibited Interrupts (EW0 Mode) ..................................................................... 1052 21.4.2 Access Method.................................................................................................... 1052 21.4.3 Programming (EW0 Mode) ................................................................................ 1052 21.4.4 Writing Commands or Data ................................................................................ 1052 21.4.5 Software Standby Mode...................................................................................... 1052 21.5 Software Commands........................................................................................................ 1053 21.5.1 Read Array.......................................................................................................... 1054 21.5.2 Read Status Register ........................................................................................... 1054 21.5.3 Clear Status Register........................................................................................... 1054 21.5.4 Program .............................................................................................................. 1054 21.5.5 Block Erase......................................................................................................... 1056 21.5.6 Block Blank Check ............................................................................................. 1058 21.6 Status Register ................................................................................................................. 1059 21.6.1 Sequencer Status (FMRDY Bit) ......................................................................... 1060 21.6.2 Erase Status (FMERSF Bit) ................................................................................ 1060 21.6.3 Programming Status (FMPRSF Bit) ................................................................... 1060 21.7 Full Status Check ............................................................................................................. 1061 21.8 Programmer Mode ........................................................................................................... 1063 Rev. 1.00 Sep. 19, 2008 Page xxvi of xxviii 21.9 Serial Communication Interface Specification for Boot Mode........................................ 1064 Section 22 Boundary Scan (JTAG) .................................................................1089 Section 23 Clock Pulse Generator ...................................................................1091 23.1 Register Descriptions ....................................................................................................... 1092 23.1.1 System Clock Control Register (SCKCR) .......................................................... 1092 23.1.2 PLL Control Register (PLLCR).......................................................................... 1094 23.2 Oscillator.......................................................................................................................... 1095 23.2.1 Connecting a Crystal Resonator.......................................................................... 1095 23.2.2 External Clock Input........................................................................................... 1096 23.3 System-Clock PLL Circuit and Divider........................................................................... 1098 23.4 Usage Notes ..................................................................................................................... 1099 23.4.1 Notes on Clock Pulse Generator ......................................................................... 1099 23.4.2 Notes on Resonator............................................................................................. 1099 23.4.3 Notes on Board Design ....................................................................................... 1100 Section 24 Power-Down Modes ......................................................................1101 24.1 Register Descriptions ....................................................................................................... 1105 24.1.1 Standby Control Register (SBYCR) ................................................................... 1105 24.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) .................. 1107 24.1.3 Extension Module Stop Control Registers H and L (EXMSTPCRH, EXMSTPCRL) ........................................................................ 1108 24.1.4 RAM Module Stop Control Registers H and L (RMMSTPCRH, RMMSTPCRL)....................................................................... 1109 24.2 Operation ......................................................................................................................... 1110 24.2.1 Clock Division Mode.......................................................................................... 1110 24.2.2 Sleep Mode ......................................................................................................... 1111 24.2.3 Software Standby Mode...................................................................................... 1112 24.2.4 Hardware Standby Mode .................................................................................... 1115 24.2.5 Module Stop Function ........................................................................................ 1116 24.2.6 All Module Clocks Stop Mode ........................................................................... 1117 24.3 φ Clock Output Control.................................................................................................... 1118 24.4 SDRAMφ Clock Output Control ..................................................................................... 1119 24.5 Usage Notes ..................................................................................................................... 1120 24.5.1 I/O Port Status..................................................................................................... 1120 24.5.2 Current Dissipation during Oscillation Stabilization Standby Period................. 1120 24.5.3 EXDMAC, DMAC, and DTC Module Stop....................................................... 1120 24.5.4 On-Chip Peripheral Module Interrupts ............................................................... 1120 24.5.5 Writing to MSTPCR, EXMSTPCR, and RMMSTPCR...................................... 1120 Rev. 1.00 Sep. 19, 2008 Page xxvii of xxviii 24.5.6 Notes on Clock Division Mode........................................................................... 1121 Section 25 List of Registers............................................................................. 1123 25.1 Register Addresses (Address Order)................................................................................ 1124 25.2 Register Bits..................................................................................................................... 1140 25.3 Register States in Each Operating Mode ......................................................................... 1160 Section 26 Electrical Characteristics ...............................................................1175 26.1 Electrical Characteristics for H8S/2426 Group and H8S/2426R Group .......................... 1175 26.1.1 Absolute Maximum Ratings ............................................................................... 1175 26.1.2 DC Characteristics .............................................................................................. 1176 26.1.3 AC Characteristics .............................................................................................. 1180 26.1.4 A/D Conversion Characteristics ......................................................................... 1189 26.1.5 D/A Conversion Characteristics ......................................................................... 1190 26.1.6 Flash Memory Characteristics ............................................................................ 1191 26.2 Electrical Characteristics for H8S/2424 Group................................................................ 1193 26.2.1 Absolute Maximum Ratings ............................................................................... 1193 26.2.2 DC Characteristics .............................................................................................. 1194 26.2.3 AC Characteristics .............................................................................................. 1198 26.2.4 A/D Conversion Characteristics ......................................................................... 1206 26.2.5 D/A Conversion Characteristics ......................................................................... 1207 26.2.6 Flash Memory Characteristics ............................................................................ 1208 26.3 Timing Charts .................................................................................................................. 1210 26.3.1 Clock Timing ...................................................................................................... 1210 26.3.2 Control Signal Timing ........................................................................................ 1212 26.3.3 Bus Timing ......................................................................................................... 1213 26.3.4 DMAC and EXDMAC Timing........................................................................... 1231 26.3.5 Timing of On-Chip Peripheral Modules ............................................................. 1236 Appendix A. B. C. .......................................................................................................1243 Port States in Each Processing State ................................................................................ 1243 Product Code Lineup ....................................................................................................... 1261 Package Dimensions ........................................................................................................ 1262 Index .......................................................................................................1265 Rev. 1.00 Sep. 19, 2008 Page xxviii of xxviii Section 1 Overview Section 1 Overview 1.1 Features The H8S/2426 Group, H8S/2426R Group, and H8S/2424 Group are CISC (Complex Instruction Set Computer) microprocessors that integrate an H8S/2600 CPU core, which has an internal 16-bit architecture and is upward-compatible with Renesas Technology original H8/300, H8/300H, and H8S CPUs. The on-chip peripheral functions provided for enabling system configuration at a low cost are the DMA controller, EXDMA controller*, data transfer controller, serial communication interface, I2C bus interface 2, synchronous serial communication unit, A/D converter, D/A converter, and various timers. On-chip ROM is flash memory whose size is 256 Kbytes and 128 Kbytes. Note: * Not supported by the H8S/2424 Group. 1.1.1 Applications Application field examples: PC peripheral equipment, office automation equipment, consumer equipment, etc. 1.1.2 Overview of Specifications The specifications of this LSI are summarized in table 1.1. Rev. 1.00 Sep. 19, 2008 Page 1 of 1270 REJ09B0466-0100 Section 1 Overview Table 1.1 Overview of Specifications Type Module/ Function Memory ROM Description Expanded ROM: Flash memory version, 256 Kbytes and 128 Kbytes ROM-less version CPU RAM RAM size: 64 Kbytes (in planning) and 48 Kbytes CPU • 16-bit high-speed H8S/2600 CPU (CISC type) Upward-compatible with H8/300, H8/300H, and H8S CPUs on an object level • General register mode (Sixteen 16-bit general registers) • Eight addressing modes • Address space: 4 Gbytes (program: 4 Gbytes, data: 4 Gbytes) • Number of basic instructions 69 types (arithmetic and logic, multiply and divide, bitmanipulation, and multiply-and-accumulate instructions) • Minimum instruction execution time (ns) 30.3 ns when system clock φ = 33 MHz and Vcc = 3.0 to 3.6 V (ADD instruction) Operating mode • Multiplier is included (16 × 16 → 32 bits) • Multiply-and-accumulate instructions are supported (16 × 16 + 32 → 32 bits) Advanced mode Rev. 1.00 Sep. 19, 2008 Page 2 of 1270 REJ09B0466-0100 Section 1 Overview Type CPU Interrupts (sources) Module/ Function MCU operating mode Description • Mode 1: Expanded mode with on-chip ROM disabled, 16-bit bus (MD2 and MD1 pins are low and MD0 pin is high) • Mode 2: Expanded mode with on-chip ROM disabled, 8-bit bus (MD2 pin is low, MD1 pin is high, and MD0 pin is low) • Mode 3: Boot mode (MD2 pin is low and MD1 and MD0 pins are high) • Mode 4: Expanded mode with on-chip ROM enabled, 8-bit bus (MD2 pin is high and MD1 and MD0 pins are low) • Mode 7: Single-chip mode (MD2, MD1, and MD0 pins are high) • Power-down modes (a power-down mode is entered when the SLEEP instruction is executed) Interrupt controller • External interrupt pins H8S/2426 Group, H8S/2426R Group: 33 pins (NMI, IRQ15-A to IRQ0-A, IRQ15-B to IRQ0-B) H8S/2424 Group: 17 pins (NMI, IRQ7-A to IRQ0-A, IRQ7-B to IRQ0-B) • Internal interrupt sources H8S/2426 Group, H8S/2426R Group: 102 sources H8S/2424 Group: 100 sources DMA DMA controller (DMAC) • Two interrupt control modes (specified by the interrupt control register) • Eight priority levels can be set (specified by the interrupt priority registers) • Independent vector addresses • DMA transfer is possible on four channels • Three activation sources (auto-request, on-chip module interrupt, and external request) • Byte or word can be set as the transfer unit • Short address mode or full address mode can be selected • 16-Mbyte address space can be specified directly Rev. 1.00 Sep. 19, 2008 Page 3 of 1270 REJ09B0466-0100 Section 1 Overview Type DMA Module/ Function EXDMA controller (EXDMAC) Description • DMA transfer is possible on two channels • Two activation sources (auto-request and external request) • Two transfer modes (normal mode and block transfer mode) • Dual address mode or single address mode can be selected • 16-Mbyte address space can be specified directly • Repeat area can be set Note: * EXDMAC is supported only by the H8S/2426 Group and H8S/2426R Group. Data transfer controller (DTC) External bus extension Bus controller (BSC) • Transfer is possible on any number of channels • An interrupt source can trigger data transfer (chain transfer is possible) • Three transfer modes (normal mode, repeat mode, and block transfer mode) • Byte or word can be set as the transfer unit • Activation by software is possible • External address space: 16 Mbytes • Manages the external address space divided into eight areas Chip select signals (CS0 to CS7) can be output 8-bit access or 16-bit access can be selected 2-state access or 3-state access can be selected Program wait states can be inserted Clock Clock pulse generator (CPG) • External memory interfaces (burst ROM, DRAM, synchronous DRAM*1, address/data multiplexed I/O) • Bus arbitration function (bus arbitration of the bus masters CPU, DTC, DMAC, and EXDMAC) • This LSI has a single on-chip clock pulse generator circuit • Consists of an oscillator, a system-clock PLL circuit, a divider, and the system clock frequency can be changed System clock (φ) cycle: 8 to 33 MHz • Six power-down modes Divided clock mode, sleep mode, module stop function, all module clock stop mode, software standby mode, and hardware standby mode Rev. 1.00 Sep. 19, 2008 Page 4 of 1270 REJ09B0466-0100 Section 1 Overview Type Module/ Function A/D converter A/D converter (ADC) Description • Two units • 10-bit resolution • Number of input channels H8S/2426 Group and H8S/2426R Group: 16 channels Unit 0: 8 channels Unit 1: 8 channels H8S/2424 Group: 10 channels Unit 0: 8 channels Unit 1: 2 channels D/A converter D/A converter (DAC) Timer 16-bit timer pulse unit (TPU) • Sample and hold functionality • Conversion time: 4.0 µs per channel (when A/D conversion clock is set to 10 MHz) • Two kinds of operating modes (single mode and scan mode) • Three types of A/D conversion start (software, trigger by timer (TPU or TMR), or external trigger) • Resolution (8 bits) × Number of output channels (2 channels) • Conversion time: Maximum 10 µs (with 20-pF load) • Output voltage: 0 V to Vref • 16-bit timer × 12 channels (general pulse timer unit) • Eight counter input clocks can be selected for each channel • Maximum 16-pulse input/output (when external expanded mode is set) • Maximum 32-pulse input/output (when single-chip mode is set) • Counter clear operation, simultaneous write to multiple timer counters (TCNT), simultaneous clearing by compare match and input capture, register simultaneous input/output possible by counter synchronous operation, and maximum of 15-phase PWM output by combination with synchronous operation • Buffer operation, phase counting mode (two-phase encoder input), and cascaded operation settable for channels • Input capture function • Output compare function (waveform output at compare match) Rev. 1.00 Sep. 19, 2008 Page 5 of 1270 REJ09B0466-0100 Section 1 Overview Type Module/ Function Description Timer 8-bit timer (TMR) • 8-bit timer × 2 channels (operation as a 16-bit timer is also possible) • Selection of seven clock sources: Six internal clock signals or an external clock input • Pulse output with an arbitrary duty cycle or PWM output • 16-bit pulse output • Pulse outputs are divided into four groups Programmable pulse generator (PPG) Non-overlap mode is available Inverted output can be specified Watchdog timer Serial interface Watchdog timer (WDT) Serial communication interface (SCI) Smart Card/SIM Highfunction communications • Can operate together with the data transfer controller (DTC) and DMA controller (DMAC) • 8-bit timer × 1 channel (eight counter input clocks can be selected) • Switchable between watchdog timer mode and interval timer mode • Five channels (asynchronous or clocked synchronous serial communication mode) • Full-duplex communication capability • Choice of any bit rate and choice of LSB-first or MSB-first SCI supports Smart Card (SIM) interface I2C bus interface 2 • (IIC2) • Continuous transmission/reception • Start and stop conditions generated automatically in master mode • Selection of acknowledge output levels when receiving • Automatic loading of acknowledge bit when transmitting • Bit synchronization/wait function Synchronous serial • communication • unit (SSU) • One channel Master mode or slave mode can be selected Standard mode or bidirectional mode can be selected • Full-duplex communication capability • Consecutive serial communication capability Rev. 1.00 Sep. 19, 2008 Page 6 of 1270 REJ09B0466-0100 Four channels Section 1 Overview Module/ Function Type I/O ports Package Description • Input-only pins: 18 (144-pin version), 17 (145-pinersion)*2, 11 (120-pin version) • Input/output pins: 96 (144-pin version or 145-pin version)*2, 83 (120-pin version) • Pull-up resistor pins: 40 • Open-drain pins: 91 • 144-pin QFP package (PLQP0144KA-A) (code: FP-144LV, body size: 20 × 20 mm, pin pitch: 0.50 mm) • 145-pin TLP package (PTLG0145JB-A) (body size: 9 × 9 mm, pin pitch: 0.65 mm) • 120-pin QFP package (PLQP0120LA-A) (code: FP-120BV, body size: 14 × 14 mm, pin pitch: 0.40 mm) Operating frequency/ power supply voltage Operating environment temperature (°C) Note: • Pb-free package • Operating frequency: 8 to 33 MHz • Power supply voltage: VCC = 3.0 to 3.6 V, AVCC = 3.0 to 3.6 V • Current consumption: 55 mA typ. (VCC = 3.3 V, AVCC = 3.3 V, φ = 33 MHz) −20°C to +75°C (regular specifications) 1. Supported only by the H8S/2426R Group. 2. Note that the function of 145-pin version partly differs from that of 144-pin version. Rev. 1.00 Sep. 19, 2008 Page 7 of 1270 REJ09B0466-0100 Section 1 Overview 1.2 List of Products Table 1.2 lists the products and figure 1.1 shows how to read the product type name. Table 1.2 Products Product Type Name ROM Size RAM Size Package Remarks R4F2426 256 Kbytes 64 Kbytes PLQP0144KA-A Flash memory version R4F2426R 128 Kbytes 48 Kbytes PTLG0145JB-A* R4F2424 256 Kbytes 64 Kbytes PLQP0120LA-A 128 Kbytes 48 Kbytes Note: * Flash memory version In planning Product type name R 4 F 2426 8 Indicates memory size classification: On-chip memory size Indicates "product original type number": H8S/2426 Indicates the ROM device type: F: On-chip ROM S: ROM-less Indicates the product classification: Microprocessor Indicates "Renesas semiconductor" Figure 1.1 Meaning of Product Type Name Rev. 1.00 Sep. 19, 2008 Page 8 of 1270 REJ09B0466-0100 Section 1 Overview PE7/D7/AD7 PE6/D6/AD6 PE5/D5/AD5 PE4/D4/AD4 PE3/D3/AD3 PE2/D2/AD2 PE1/D1/AD1 PE0/D0/AD0 Port D Port E Port 6 P35/OE-B/CKE-B*1/SCK1/SCL0 P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD EXDMAC WDT RAM SCI × 5 channels IIC2 × 4 channels TPU × 12 channels 8-bit D/A converter (6 channels) Port 5 10-bit A/D converter PPG SSU P53/IRQ3-A/ADTRG0-A/TRST*3 P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/TMO0-B/SCK2 P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/TMCI0-B/RxD2/SCL3 P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/TMRI0-B/TxD2/SDA3 P47/AN7_0 P46/AN6_0 P45/AN5_0 P44/AN4_0 P43/AN3_0 P42/AN2_0 P41/AN1_0 P40/AN0_0 Port 9 Port H PH3/CS7/OE-A/CKE-A*1/IRQ7-B PH2/CS6/IRQ6-B PH1/CS5/RAS5/SDRAMφ*1 PH0/CS4/RAS4/WE*1 Port 4 P97/AN15_1 P96/AN14_1 P95/AN13_1/DA3 P94/AN12_1/DA2 P93/AN11_1 P92/AN10_1 P91/AN9_1 P90/AN8_1 Port 2 Vref AVcc AVss Port 1 P20/IRQ8-B/PO0-A/TIOCA3-A P21/IRQ9-B/PO1-A/TIOCB3-A P22/IRQ10-B/PO2-A/TIOCC3-A P23/IRQ11-B/PO3-A/TIOCD3-A/TxD4-A P24/IRQ12-B/PO4-A/TIOCA4-A/RxD4-A P25/WAIT-B/IRQ13-B/PO5-A/TIOCB4-A P26/IRQ14-B/PO6/TIOCA5/SDA2/ADTRG1 P27/IRQ15-B/PO7/TIOCB5/SCL2 TMR × 2 channels P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/TIOCC0/TCLKA P13/PO11/TIOCD0/TCLKB P14/PO12/TIOCA1/SSO0-A P15/PO13/TIOCB1/TCLKC/SSI0-A P16/PO14/TIOCA2/EDRAK2/SSCK0-A P17/PO15/TIOCB2/TCLKD/EDRAK3/SCS0-A Port 8 P85/IRQ5-B/PO5-B/TIOCB4-B/TMO1-B/SCK3/EDACK3 P84/IRQ4-B/EDACK2 P83/IRQ3-B/PO3-B/TIOCD3-B/TMCI1-B/RxD3/ETEND3 P82/IRQ2-B/ETEND2 P81/IRQ1-B/PO1-B/TIOCB3-B/TMRI1-B/TxD3/EDREQ3 P80/IRQ0-B/EDREQ2 PC7/A7/TIOCB11 PC6/A6/TIOCA11 PC5/A5/TIOCB10 PC4/A4/TIOCA10 PC3/A3/TIOCD9 PC2/A2/TIOCC9 PC1/A1/TIOCB9 PC0/A0/TIOCA9 Port J PJ2*2 PJ1 PJ0 Port G P65/IRQ13-A/DACK1/TMO1-A P64/IRQ12-A/DACK0/TMO0-A P63/IRQ11-A/TEND1/TMCI1-A P62/IRQ10-A/TEND0/TMCI0-A P61/IRQ9-A/DREQ1/TMRI1-A P60/IRQ8-A/DREQ0/TMRI0-A Port A PG6/BREQ-A/TDI*3 PG5/BACK-A/TMS*3 PG4/BREQO-A/TCK*3 PG3/CS3/RAS3/CAS*1 PG2/CS2/RAS2/RAS PG1/CS1 PG0/CS0 Port B DMAC ROM (flash memory) Peripheral address bus Bus controller DTC PB7/A15/TIOCB8/TCLKH PB6/A14/TIOCA8 PB5/A13/TIOCB7/TCLKG PB4/A12/TIOCA7 PB3/A11/TIOCD6/TCLKF PB2/A10/TIOCC6/TCLKE PB1/A9/TIOCB6 PB0/A8/TIOCA6 Port C Port F Interrupt controller Peripheral data bus Internal data bus H8S/2600 CPU Clock pulse generator Internal address bus System clock PLL PA7/A23/IRQ7-A/SSO0-B PA6/A22/IRQ6-A/SSI0-B PA5/A21/IRQ5-A/SSCK0-B PA4/A20/IRQ4-A/SCS0-B PA3/A19/SCK4-B PA2/A18/RxD4-B PA1/A17/TxD4-B PA0/A16 Port 3 JTAG*3 (boundary scan) MD2 MD1 MD0 EXTAL XTAL EMLE STBY RES WDTOVF/TDO*3 NMI BSCANE*3 PF7/φ PF6/AS/AH PF5/RD PF4/HWR PF3/LWR/SSO0-C PF2/LCAS/DQML*1/IRQ15-A/SSI0-C PF1/UCAS/DQMU*1/IRQ14-A/SSCK0-C PF0/WAIT-A/ADTRG0-B/SCS0-C PD7/D15/AD15 PD6/D14/AD14 PD5/D13/AD13 PD4/D12/AD12 PD3/D11/AD11 PD2/D10/AD10 PD1/D9/AD9 PD0/D8/AD8 Block Diagrams Vcc Vcc Vcc Vcc PLLVcc PLLVss Vss Vss Vss Vss Vss Vss Vss Vss VCL 1.3 Notes: 1. Not available in the H8S/2426 Group. 2. Can be used only in FP-144LV. 3. Pins BSCANE, TD1, TMS, TCK, TRST, and TDO can be used only in TLP-145V. (under development) Figure 1.2 Block Diagram of H8S/2426 Group and H8S/2426R Group Rev. 1.00 Sep. 19, 2008 Page 9 of 1270 REJ09B0466-0100 Port 8 DMAC ROM (flash memory) Port A Port G P85/PO5-B/TIOCB4-B/TMO1-B/SCK3 P83/PO3-B/TIOCD3-B/TMCI1-B/RxD3 P81/PO1-B/TIOCB3-B/TMRI1-B/TxD3 DTC Port B Port F PG6/BREQ-A PG5/BACK-A PG4/BREQO-A/CS4 PG3/CS3/RAS3 PG2/CS2/RAS2 PG1/CS1 PG0/CS0 Interrupt controller Periheral address bus PF7/φ PF6/AS/AH PF5/RD PF4/HWR PF3/LWR/SSO0-C PF2/CS6/LCAS/SSI0-C PF1/CS5/UCAS/SSCK0-C PF0/WAIT-A/OE-A/ADTRG0-B/SCS0-C PB7/A15/TIOCB8/TCLKH PB6/A14/TIOCA8 PB5/A13/TIOCB7/TCLKG PB4/A12/TIOCA7 PB3/A11/TIOCD6/TCLKF PB2/A10/TIOCC6/TCLKE PB1/A9/TIOCB6 PB0/A8/TIOCA6 Port C Internal data bus H8S/2600 CPU Clock pulse generator PA7/A23/CS7/IRQ7-A/SSO0-B PA6/A22/IRQ6-A/SSI0-B PA5/A21/IRQ5-A/SSCK0-B PA4/A20/IRQ4-A/SCS0-B PA3/A19/SCK4-B PA2/A18/RxD4-B PA1/A17/TxD4-B PA0/A16 PC7/A7/TIOCB11 PC6/A6/TIOCA11 PC5/A5/TIOCB10 PC4/A4/TIOCA10 PC3/A3/TIOCD9 PC2/A2/TIOCC9 PC1/A1/TIOCB9 PC0/A0/TIOCA9 Port 3 System clock PLL Bus controller Port E Peripheral data bus PE7/D7/AD7 PE6/D6/AD6 PE5/D5/AD5 PE4/D4/AD4 PE3/D3/AD3 PE2/D2/AD2 PE1/D1/AD1 PE0/D0/AD0 Port D Internal address bus MD2 MD1 MD0 EXTAL XTAL EMLE STBY RES WDTOVF NMI PD7/D15/AD15 PD6/D14/AD14 PD5/D13/AD13 PD4/D12/AD12 PD3/D11/AD11 PD2/D10/AD10 PD1/D9/AD9 PD0/D8/AD8 VCC VCC VCC VCC PLLVCC PLLVSS VSS VSS VSS VSS VSS VSS VCL Section 1 Overview P35/OE-B/SCK1/SCL0 P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD WDT SCI × 5 channels RAM IIC2 × 4 channels TPU × 12 channels 8-bit D/A converter Port 5 10-bit A/D converter PPG SSU P53/IRQ3-A/ADTRG0-A P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/TMO0-B/SCK2 P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/TMCI0-B/RxD2/SCL3 P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/TMRI0-B/TxD2/SDA3 Port 9 P95/AN13_1/DA3 P94/AN12_1/DA2 P20/PO0-A/TIOCA3-A/TMRI0-A P21/PO1-A/TIOCB3-A/TMRI1-A P22/PO2-A/TIOCC3-A/TMCI0-A P23/PO3-A/TIOCD3-A/TMCI1-A/TXD4-A P24/PO4-A/TIOCA4-A/TMO0-A/RXD4-A P25/WAIT-B/PO5-A/TIOCB4-A/TMO1-A P26/PO6/TIOCA5/SDA2/ADTRG1 P27/PO7/TIOCB5/SCL2 Port 4 P47/IRQ7-B/AN7_0 P46/IRQ6-B/AN6_0 P45/IRQ5-B/AN5_0 P44/IRQ4-B/AN4_0 P43/IRQ3-B/AN3_0 P42/IRQ2-B/AN2_0 P41/IRQ1-B/AN1_0 P40/IRQ0-B/AN0_0 Port 2 Vref AVCC AVSS Port 1 P10/DREQ0/PO8/TIOCA0 P11/DREQ1/PO9/TIOCB0 P12/TEND0/PO10/TIOCC0/TCLKA P13/TEND1/PO11/TIOCD0/TCLKB P14/DACK0/PO12/TIOCA1/SSO0-A P15/DACK1/PO13/TIOCB1/TCLKC/SSI0-A P16/PO14/TIOCA2/SSCK0-A P17/PO15/TIOCB2/TCLKD/SCS0-A TMR × 2 channels Figure 1.3 Block Diagram of H8S/2424 Group Rev. 1.00 Sep. 19, 2008 Page 10 of 1270 REJ09B0466-0100 Section 1 Overview Pin Description 1.4.1 Pin Assignments H8S/2426 Group, H8S/2426R Group PLQP0144KA-A FP-144LV (Top view) 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 MD2 Vss P80/IRQ0-B/EDREQ2 Vcc PC0/A0/TIOCA9 PC1/A1/TIOCB9 PC2/A2/TIOCC9 PC3/A3/TIOCD9 PC4/A4/TIOCA10 Vss PC5/A5/TIOCB10 PC6/A6/TIOCA11 PC7/A7/TIOCB11 PB0/A8/TIOCA6 PB1/A9/TIOCB6 PB2/A10/TIOCC6/TCLKE PB3/A11/TIOCD6/TCLKF Vss PB4/A12/TIOCA7 PB5/A13/TIOCB7/TCLKG PB6/A14/TIOCA8 PB7/A15/TIOCB8/TCLKH PA0/A16 PA1/A17/TxD4-B Vss PA2/A18/RxD4-B PA3/A19/SCK4-B PA4/A20/IRQ4-A/SCS0-B PA5/A21/IRQ5-A/SSCK0-B PA6/A22/IRQ6-A/SSI0-B PA7/A23/IRQ7-A/SSO0-B EMLE*2 P81/IRQ1-B/PO1-B/TIOCB3-B/TMRI1-B/TxD3/EDREQ3 P82/IRQ2-B/ETEND2 PH0/CS4/RAS4/WE*1 PH1/CS5/RAS5/SDRAMφ*1 PG2/CS2/RAS2/RAS PG3/CS3/RAS3/CAS*1 AVcc Vref P40/AN0_0 P41/AN1_0 P42/AN2_0 P43/AN3_0 P44/AN4_0 P45/AN5_0 P46/AN6_0 P47/AN7_0 P90/AN8_1 P91/AN9_1 P92/AN10_1 P93/AN11_1 P94/AN12_1/DA2 P95/AN13_1/DA3 P96/AN14_1 P97/AN15_1 AVss PG4/BREQO-A PG5/BACK-A PG6/BREQ-A P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/TMRI0-B/TxD2/SDA3 P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/TMCI0-B/RxD2/SCL3 P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/TMO0-B/SCK2 P53/IRQ3-A/ADTRG0-A P35/OE-B/CKE-B*1/SCK1/SCL0 P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD MD0 MD1 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PG1/CS1 PG0/CS0 P65/IRQ13-A/DACK1/TMO1-A P64/IRQ12-A/DACK0/TMO0-A P63/IRQ11-A/TEND1/TMCI1-A STBY Vss PJ1 PJ0 Vcc Vcc EXTAL XTAL Vss PF7/φ PLLVss RES PLLVcc PF6/AS/AH PF5/RD PF4/HWR PF3/LWR/SSO0-C PF2/LCAS/DQML*1/IRQ15-A/SSI0-C PF1/UCAS/DQMU*1/IRQ14-A/SSCK-C PF0/WAIT-A/ADTRG0-B/SCS0-C P62/IRQ10-A/TEND0/TMCI0-A P61/IRQ9-A/DREQ1/TMRI1-A P60/IRQ8-A/DREQ0/TMRI0-A PD7/D15/AD15 PD6/D14/AD14 PD5/D13/AD13 PD4/D12/AD12 PD3/D11/AD11 PD2/D10/AD10 PD1/D9/AD9 PD0/D8/AD8 1.4 Vcc PE7/D7/AD7 Vss PE6/D6/AD6 PE5/D5/AD5 PE4/D4/AD4 PE3/D3/AD3 PE2/D2/AD2 PE1/D1/AD1 PE0/D0/AD0 PJ2 P85/IRQ5-B/PO5-B/TIOCB4-B/TMO1-B/SCK3/EDACK3 P84/IRQ4-B/EDACK2 P83/IRQ3-B/PO3-B/TIOCD3-B/TMCI1-B/RxD3/ETEND3 P27/IRQ15-B/PO7/TIOCB5/SCL2 P26/IRQ14-B/PO6/TIOCA5/SDA2/ADTRG1 P25/WAIT-B/IRQ13-B/PO5-A/TIOCB4-A P24/IRQ12-B/PO4-A/TIOCA4-A/RxD4-A P23/IRQ11-B/PO3-A/TIOCD3/TxD4-A P22/IRQ10-B/PO2-A/TIOCC3-A P21/IRQ9-B/PO1-A/TIOCB3-A P20/IRQ8-B/PO0-A/TIOCA3-A Vss P17/PO15/TIOCB2/TCLKD/EDRAK3/SCS0-A P16/PO14/TIOCA2/EDRAK2/SSCK0-A P15/PO13/TIOCB1/TCLKC/SSI0-A P14/PO12/TIOCA1/SSO0-A P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0 P10/PO8/TIOCA0 VCL*3 NMI WDTOVF PH3/CS7/OE-A/CKE-A*1/IRQ7-B PH2/CS6/IRQ6-B 41 0.1 µF (recommended value) Notes: 1. Not available in the H8S/2426 Group. 2. Emulator enable pin. In normal operating mode, this pin should be fixed low. Driving this pin high in the flash-memory version enables the on-chip emulation function. When the on-chip emulation function is in use, pins P53, PG4, PG5, PG6, and WDTOVF are used exclusively as the on-chip emulator pins. 3. The VCL pin should be connected to an external capacitor. Figure 1.4 Pin Assignments for H8S/2426 Group and H8S/2426R Group (1) Rev. 1.00 Sep. 19, 2008 Page 11 of 1270 REJ09B0466-0100 Section 1 Overview 1 2 3 4 5 6 7 8 9 10 11 12 13 A Vss MD1 MD0 P32 P35 P50 AVss P94 P90 P44 P40 PG2 PG3 B MD2 Vcc P31 P34 P51 PG4 P93 P47 P45 P42 AVcc Vref PG1 C PC0 P80 PC1 P30 P33 P52 PG5 P92 P46 P43 P41 PG0 P65 D PC4 PC2 PC3 P53 PG6 P97 P96 P95 P91 P63 PJ0 P64 STBY E PC7 Vss PC5 PB0 NC Vss Vcc PJ1 Vcc F PB3 PC6 PB1 Vss PF7 Vss XTAL EXTAL PF6 RES PF5 PLLVss H8S/2426 Group, H8S/2426R Group PTLG0145JB-A (Perspective top view) G PB6 PB2 PA0 PB4 H Vss PB7 PA3 PB5 PF2 PF4 PF1 PLLVcc J PA5 PA2 PA7 PA1 P62 PF0 P60 PF3 K EMLE PA6 P82 PA4 P15 P16 P27 P83 PE0 PE4 PD7 PD6 P61 L PH0 P81 VCL P12 P17 P20 P21 P26 BSCANE * PE3 PD4 PD2 PD5 M PH1 PH3 WDTOVF P11 P13 P22 P24 P85 PE2 PE6 Vss PD3 PD0 N NMI PH2 P10 P14 Vss P23 P25 P84 PE1 PE5 PE7 Vcc PD1 Note: Connect NC to VSS or leave it open. The VCL pin must be connected to an external capacitor (recommended value: 0.1 µF). * Boundary scan enable pin. When the boundary scan function is used, this pin should be fixed high. At this time, pins P53, PG4 to PG6, and WDTOVF are used exclusively for boundary scan. Therefore, the corresponding pin functions of those pins are not available. When the boundary scan function is not used, this pin should be fixed low. Figure 1.5 Pin Assignments for H8S/2426 Group and H8S/2426R Group (2) (LGA is in Planning) Rev. 1.00 Sep. 19, 2008 Page 12 of 1270 REJ09B0466-0100 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PG1/CS1 PG0/CS0 STBY VSS P81/PO1-B/TIOCB3-B/TMRI1-B/TxD3 P83/PO3-B/TIOCD3-B/TMCI1-B/RxD3 VCC VCC EXTAL XTAL VSS PF7/φ PLLVSS RES PLLVCC PF6/AS/AH PF5/RD PF4/HWR PF3/LWR/SSO0-C PF2/CS6/LCAS/SSI0-C PF1/CS5/UCAS/SSCK0-C PF0/WAIT-A/OE-A/ADTRG0-B/SCS0-C PD7/D15/AD15 PD6/D14/AD14 PD5/D13/AD13 PD4/D12/AD12 PD3/D11/AD11 PD2/D10/AD10 PD1/D9/AD9 PD0/D8/AD8 Section 1 Overview 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 H8S/2424 Group PLQ0120LA-A FP-120BV (Top view) VCC PE7/D7/AD7 VSS PE6/D6/AD6 PE5/D5/AD5 PE4/D4/AD4 PE3/D3/AD3 PE2/D2/AD2 PE1/D1/AD1 PE0/D0/AD0 P85/PO5-B/TIOCB4-B/TMO1-B/SCK3 P27/PO7/TIOCB5/SCL2 P26/PO6/TIOCA5/SDA2/ADTRG1 P25/WAIT-B/PO5-A/TIOCB4-A/TMO1-A P24/PO4-A/TIOCA4-A/TMO0-A/RxD4-A P23/PO3-A/TIOCD3-A/TMCI1-A/TxD4-A P22/PO2-A/TIOCC3-A/TMCI0-A P21/PO1-A/TIOCB3-A/TMRI1-A P20/PO0-A/TIOCA3-A/TMRI0-A P17/PO15/TIOCB2/TCLKD/SCS0-A P16/PO14/TIOCA2/SSCK0-A P15/DACK1/PO13/TIOCB1/TCLKC/SSI0-A P14/DACK0/PO12/TIOCA1/SSO0-A P13/TEND1/PO11/TIOCD0/TCLKB P12/TEND0/PO10/TIOCC0/TCLKA P11/DREQ1/PO9/TIOCB0 P10/DREQ0/PO8/TIOCA0 VCL*2 NMI WDTOVF MD2 VCC PC0/A0/TIOCA9 PC1/A1/TIOCB9 PC2/A2/TIOCC9 PC3/A3/TIOCD9 PC4/A4/TIOCA10 VSS PC5/A5/TIOCB10 PC6/A6/TIOCA11 PC7/A7/TIOCB11 PB0/A8/TIOCA6 PB1/A9/TIOCB6 PB2/A10/TIOCC6/TCLKE PB3/A11/TIOCD6/TCLKF PB4/A12/TIOCA7 VSS PB5/A13/TIOCB7/TCLKG PB6/A14/TIOCA8 PB7/A15/TIOCB8/TCLKH PA0/A16 VSS PA1/A17/TxD4-B PA2/A18/RxD4-B PA3/A19/SCK4-B PA4/A20/IRQ4-A/SCS0-B PA5/A21/IRQ5-A/SSCK0-B PA6/A22/IRQ6-A/SSI0-B PA7/A23/CS7/IRQ7-A/SSO0-B EMLE*1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PG2/CS2/RAS2 PG3/CS3/RAS3 AVCC Vref P40/IRQ0-B/AN0_0 P41/IRQ1-B/AN1_0 P42/IRQ2-B/AN2_0 P43/IRQ3-B/AN3_0 P44/IRQ4-B/AN4_0 P45/IRQ5-B/AN5_0 P46/IRQ6-B/AN6_0 P47/IRQ7-B/AN7_0 P94/AN12_1/DA2 P95/AN13_1/DA3 AVSS PG4/BREQO-A/CS4 PG5/BACK-A PG6/BREQ-A P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/TMRI0-B/TxD2/SDA3 P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/TMCI0-B/RxD2/SCL3 P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/TMO0-B/SCK2 P53/IRQ3-A/ADTRG0-A P35/OE-B/SCK1/SCL0 P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD MD0 MD1 33 0.1 µF (recommended value) Notes: 1. Emulator enable pin. In normal operating mode, this pin should be fixed low. Driving this pin high in the flash-memory version enables the on-chip emulation function. When the on-chip emulation function is in use, pins P53, PG4, PG5, PG6, and WDTOVF are used exclusively as the on-chip emulator pins. 2. The VCL pin should be connected to an external capacitor. Figure 1.6 Pin Assignments for H8S/2424 Group Rev. 1.00 Sep. 19, 2008 Page 13 of 1270 REJ09B0466-0100 Section 1 Overview 1.4.2 Pin Assignments in Each Operating Mode Table 1.3 Pin Assignments in Each Operating Mode of H8S/2426 Group and H8S/2426R Group Pin No. Pin Name 145-Pin*5 Mode 7 (LGA-145 in 4 144-Pin* planning) Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode 1 B1 MD2 MD2 MD2 MD2 MD2 Vss 2 A1 Vss Vss Vss Vss Vss Vss 3 C2 P80/IRQ0-B/ P80/IRQ0-B/ EDREQ2 EDREQ2 P80/IRQ0-B/ EDREQ2 P80/IRQ0-B/ EDREQ2 P80/IRQ0-B/ EDREQ2 NC 4 B2 Vcc Vcc Vcc Vcc Vcc Vcc 5 C1 A0 A0 PC0/A0 PC0/A0 PC0/TIOCA9 A0 6 C3 A1 A1 PC1/A1 PC1/A1 PC1/TIOCB9 A1 7 D2 A2 A2 PC2/A2 PC2/A2 PC2/TIOCC9 A2 8 D3 A3 A3 PC3/A3 PC3/A3 PC3/TIOCD9 A3 9 D1 A4 A4 PC4/A4 PC4/A4 PC4/TIOCA10 A4 10 E2 Vss Vss Vss Vss Vss Vss 11 E3 A5 A5 PC5/A5 PC5/A5 PC5/TIOCB10 A5 12 F2 A6 A6 PC6/A6 PC6/A6 PC6/TIOCA11 A6 13 E1 A7 A7 PC7/A7 PC7/A7 PC7/TIOCB11 A7 14 E4 A8 A8 PB0/A8 PB0/A8 PB0/TIOCA6 A8 15 F3 A9 A9 PB1/A9 PB1/A9 PB1/TIOCB6 A9 16 G2 A10 A10 PB2/A10 PB2/A10 PB2/TIOCC6/ TCLKE A10 17 F1 A11 A11 PB3/A11 PB3/A11 PB3/TIOCD6/ TCLKF A11 18 F4 Vss Vss Vss Vss Vss Vss 19 G4 A12 A12 PB4/A12 PB4/A12 PB4/TIOCA7 A12 20 H4 A13 A13 PB5/A13 PB5/A13 PB5/TIOCB7/ TCLKG A13 21 G1 A14 A14 PB6/A14 PB6/A14 PB6/TIOCA8 A14 22 H2 A15 A15 PB7/A15 PB7/A15 PB7/TIOCB8/ TCLKH A15 23 G3 A16 A16 PA0/A16 PA0/A16 PA0 A16 24 J4 A17 A17 PA1/A17/TxD4-B PA1/A17/TxD4-B PA1/TxD4-B Rev. 1.00 Sep. 19, 2008 Page 14 of 1270 REJ09B0466-0100 A17 Section 1 Overview Pin No. Pin Name 5 145-Pin* 144-Pin*4 planning) Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode 25 H1 Vss Vss Vss Vss Vss Vss 26 J2 A18 A18 PA2/A18/RxD4-B PA2/A18/RxD4-B PA2/RxD4-B A18 27 H3 A19 A19 PA3/A19/SCK4-B PA3/A19/RxD4-B PA3/SCK4-B NC 28 K4 A20/IRQ4-A A20/IRQ4-A PA4/A20/IRQ4-A/ PA4/A20/IRQ4-A/ PA4/IRQ4-A/ SCS0-B SCS0-B SCS0-B NC 29 J1 PA5/A21/ IRQ5A/SSCK0-B PA5/A21/ PA5/A21/ PA5/A21/ PA5/ NC IRQ5-A/SSCK0-B IRQ5-A/SSCK0-B IRQ5-A/SSCK0-B IRQ5-A/SSCK0-B 30 K2 PA6/A22/ PA6/A22/ IRQ6-A/SSI0- IRQ6-A/SSI0-B B PA6/A22/ IRQ6-A/SSI0-B PA6/A22/ IRQ6-A/SSI0-B PA6/ IRQ6-A/SSI0-B NC 31 J3 PA7/A23/ IRQ7A/SSO0-B PA7/A23/ IRQ7-A/SSO0-B PA7/A23/ IRQ7-A/SSO0-B PA7/A23/ IRQ7-A/SSO0-B PA7/ IRQ7-A/SSO0-B NC 32 K1 EMLE EMLE EMLE EMLE EMLE Vss 33 L2 P81/IRQ1-B/ PO1-B/ TIOCB3-B/ TMRI1B/TxD3/ EDREQ3 P81/IRQ1-B/ PO1-B/ TIOCB3-B/ TMRI1-B/TxD3/ EDREQ3 P81/IRQ1-B/ PO1-B/ TIOCB3-B/ TMRI1-B/TxD3/ EDREQ3 P81/IRQ1-B/ PO1-B/ TIOCB3-B/ TMRI1-B/TxD3/ EDREQ3 P81/IRQ1-B/ NC PO1-B/ TIOCB3-B/ TMRI1B/TxD3/EDREQ3 34 K3 P82/IRQ2-B/ P82/IRQ2-B/ ETEND2 ETEND2 P82/IRQ2-B/ ETEND2 P82/IRQ2-B/ ETEND2*3 P82/IRQ2-B NC 35 L1 PH0/CS4/ RAS4/WE*1 PH0/CS4/ RAS4/WE*1 PH0/CS4/ RAS4/WE*1 PH0 NC 36 M1 PH1/CS5/ PH1/CS5/ PH1/CS5/ PH1/CS5/ PH1/ RAS5/SDRA RAS5/SDRAM *1 RAS5/SDRAM *1 RAS5/SDRAM *1 SDRAM *1 M *1 NC 37 N2 PH2/CS6/IRQ PH2/CS6/IRQ6-B PH2/CS6/IRQ6-B PH2/CS6/IRQ6-B PH2/IRQ6-B 6-B NC 38 M2 PH3/CS7/ OE-A/CKEA*1/ IRQ7-B 39 M3 WDTOVF/TD WDTOVF/TDO*3 WDTOVF/TDO*3 WDTOVF/TDO*3 WDTOVF/TDO*3 NC O*3 40 N1 NMI NMI NMI NMI NMI Vcc 41 L3 VCL VCL VCL VCL VCL VCL Mode 7 (LGA-145 in PH0/CS4/ RAS4/WE*1 PH3/CS7/ OE-A/CKE-A*1/ IRQ7-B PH3/CS7/ OE-A/CKE-A*1/ IRQ7-B PH3/CS7/ OE-A/CKE-A*1/ IRQ7-B PH3/IRQ7-B NC Rev. 1.00 Sep. 19, 2008 Page 15 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. Pin Name 5 145-Pin* Mode 7 (LGA-145 in Flash Memory Programmer Mode 144-Pin*4 planning) Mode 1 42 N3 P10/PO8/TIO P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 NC CA0 43 M4 P11/PO9/TIO P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 NC CB0 44 L4 P12/PO10/ P12/PO10/ TIOCC0/TCL TIOCC0/TCLKA KA P12/PO10/ TIOCC0/TCLKA P12/PO10/ TIOCC0/TCLKA P12/PO10/ TIOCC0/TCLKA OE 45 M5 P13/PO11/ P13/PO11/ TIOCD0/TCL TIOCD0/TCLKB KB P13/PO11/ TIOCD0/TCLKB P13/PO11/ TIOCD0/TCLKB P13/PO11/ TIOCD0/TCLKB CE 46 N4 P14/PO12/ P14/PO12/ P14/PO12/ P14/PO12/ WE P14/PO12/ TIOCA1/SSO TIOCA1/SSO0-A TIOCA1/SSO0-A TIOCA1/SSO0-A TIOCA1/SSO0-A 0-A 47 K5 P15/PO13/ P15/PO13/ P15/PO13/ P15/PO13/ NC P15/PO13/ TIOCB1/TCL TIOCB1/TCLKC/ TIOCB1/TCLKC/ TIOCB1/TCLKC/ TIOCB1/TCLKC/ SSI0-A SSI0-A SSI0-A SSI0-A KC/ SSI0-A 48 K6 P16/PO14/ TIOCA2/ EDRAK2/ SSCK0-A 49 L5 P17/PO15/ P17/PO15/ P17/PO15/ P17/PO15/ NC P17/PO15/ TIOCB2/TCL TIOCB2/TCLKD/ TIOCB2/TCLKD/ TIOCB2/TCLKD/ TIOCB2/TCLKD/ EDRAK3/SCS0-A EDRAK3/SCS0-A EDRAK3/SCS0-A SCS0-A KD/ EDRAK3/SC S0-A 50 N5 Vss 51 L6 P20/IRQ8-B/ P20/IRQ8-B/ P20/IRQ8-B/ NC P20/IRQ8-B/ P20/IRQ8-B/ PO0-A/TIOCA3-A PO0-A/TIOCA3-A PO0-A/TIOCA3-A PO0-A/TIOCA3-A PO0A/TIOCA3-A 52 L7 P21/IRQ9-B/ P21/IRQ9-B/ P21/IRQ9-B/ P21/IRQ9-B/ P21/IRQ9-B/ Vcc PO1PO1-A/TIOCB3-A PO1-A/TIOCB3-A PO1-A/TIOCB3-A PO1-A/TIOCB3-A A/TIOCB3-A 53 M6 P22/IRQ10-B/ P22/IRQ10-B/ P22/IRQ10-B/ P22/IRQ10-B/ P22/IRQ10-B/ NC PO2PO2-A/TIOCC3-A PO2-A/TIOCC3-A PO2-A/TIOCC3-A PO2-A/TIOCC3-A A/TIOCC3-A 54 N6 P23/IRQ11-B/ P23/IRQ11-B/ PO3-A/ PO3-A/ TIOCD3-A/ TIOCD3-A/ TxD4-A TxD4-A Mode 2 P16/PO14/ TIOCA2/ EDRAK2/ SSCK0-A Vss Rev. 1.00 Sep. 19, 2008 Page 16 of 1270 REJ09B0466-0100 Mode 4 P16/PO14/ TIOCA2/ EDRAK2/ SSCK0-A Vss P23/IRQ11-B/ PO3-A/ TIOCD3-A/ TxD4-A EXPE = 1 P16/PO14/ TIOCA2/ EDRAK2/ SSCK0-A Vss P23/IRQ11-B/ PO3-A/ TIOCD3-A/ TxD4-A EXPE = 0 P16/PO14/ TIOCA2/ SSCK0-A Vss P23/IRQ11-B/ PO3-A/ TIOCD3-A/ TxD4-A NC Vss NC Section 1 Overview Pin No. Pin Name 5 145-Pin* Flash Memory Programmer Mode Mode 7 (LGA-145 in 144-Pin*4 planning) Mode 1 55 M7 P24/IRQ12-B/ P24/IRQ12-B/ PO4-A/ PO4-A/ TIOCA4-A/ TIOCA4-A/ RxD4-A RxD4-A 56 Mode 2 Mode 4 EXPE = 1 EXPE = 0 P24/IRQ12-B/ PO4-A/ TIOCA4-A/ RxD4-A P24/IRQ12-B/ PO4-A/ TIOCA4-A/ RxD4-A P24/IRQ12-B/ PO4-A/ TIOCA4-A/ RxD4-A Vss N7 P25/WAIT-B/ P25/WAIT-B/ P25/WAIT-B/ P25/WAIT-B/ IRQ13IRQ13-B/PO5-A/ IRQ13-B/PO5-A/ IRQ13-B/PO5B/PO5-A/ TIOCB4-A TIOCB4-A A/TIOCB4-A TIOCB4-A P25/IRQ13-B/ PO5-A/ TIOCB4-A NC 57 L8 P26/IRQ14-B/ P26/IRQ14-B/ PO6/TIOCA5/ PO6/TIOCA5/ SDA2/ADTR SDA2/ADTRG1 G1 P26/IRQ14-B/ PO6/TIOCA5/ SDA2/ADTRG1 P26/IRQ14-B/ PO6/TIOCA5/ SDA2/ADTRG1 P26/IRQ14-B/ PO6/TIOCA5/ SDA2/ADTRG1 NC 58 K7 P27/IRQ15-B/ P27/IRQ15-B/ PO7/TIOCB5/ PO7/TIOCB5/ SCL2 SCL2 P27/IRQ15-B/ PO7/TIOCB5/ SCL2 P27/IRQ15-B/ PO7/TIOCB5/ SCL2 P27/IRQ15-B/ PO7/TIOCB5/ SCL2 NC 59 K8 P83/IRQ3-B/ PO3-B/ TIOCD3-B/ TMCI1B/RxD3/ ETEND3 P83/IRQ3-B/ PO3-B/ TIOCD3-B/ TMCI1-B/RxD3/ ETEND3 P83/IRQ3-B/ PO3-B/ TIOCD3-B/ TMCI1-B/RxD3/ ETEND3 P83/IRQ3-B/ PO3-B/ TIOCD3-B/ TMCI1-B/RxD3 NC 60 N8 P84/IRQ4-B/ P84/IRQ4-B/ EDACK2 EDACK2 P84/IRQ4-B/ EDACK2 P84/IRQ4-B/ EDACK2 P84/IRQ4-B/ NC 61 M8 P85/IRQ5-B/ PO5-B/ TIOCB4-B/ TMO1B/SCK3/ EDACK3 P85/IRQ5-B/ PO5-B/ TIOCB4-B/ TMO1-B/SCK3/ EDACK3 P85/IRQ5-B/ PO5-B/ TIOCB4-B/ TMO1-B/SCK3/ EDACK3 P85/IRQ5-B/ PO5-B/ TIOCB4-B/ TMO1-B/SCK3/ EDACK3 P85/IRQ5-B/ PO5-B/ TIOCB4-B/ TMO1-B/SCK3 NC 62 L9 PJ2*2 PJ2*2 PJ2*2 PJ2*2 PJ2* NC 63 K9 PE0/D0 PE0/D0 PE0/D0 PE0/D0 PE0 NC 64 N9 PE1/D1 PE1/D1 PE1/D1 PE1/D1 PE1 NC 65 M9 PE2/D2 PE2/D2 PE2/D2 PE2/D2 PE2 NC 66 L10 PE3/D3 PE3/D3 PE3/D3 PE3/D3 PE3 NC 67 K10 PE4/D4 PE4/D4 PE4/D4 PE4/D4 PE4 NC 68 N10 PE5/D5 PE5/D5 PE5/D5 PE5/D5 PE5 NC 69 M10 PE6/D6 PE6/D6 PE6/D6 PE6/D6 PE6 NC 70 M11 Vss Vss Vss Vss Vss Vss 71 N11 PE7/D7 PE7/D7 PE7/D7 PE7/D7 PE7 NC P83/IRQ3-B/ PO3-B/ TIOCD3-B/ TMCI1-B/RxD3/ ETEND3 Rev. 1.00 Sep. 19, 2008 Page 17 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. Pin Name 5 145-Pin* 144-Pin*4 planning) Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode 72 N12 Vcc Vcc Vcc Vcc Vcc Vcc 73 M13 D8 D8 D8 D8 PD0 I/O0 74 N13 D9 D9 D9 D9 PD1 I/O1 75 L12 D10 D10 D10 D10 PD2 I/O2 76 M12 D11 D11 D11 D11 PD3 I/O3 77 L11 D12 D12 D12 D12 PD4 I/O4 78 L13 D13 D13 D13 D13 PD5 I/O5 79 K12 D14 D14 D14 D14 PD6 I/O6 80 K11 D15 D15 D15 D15 PD7 I/O7 81 J12 P60/IRQ8-A/ P60/IRQ8-A/ P60/IRQ8-A/ P60/IRQ8-A/ P60/IRQ8-A/ NC DREQ0/TMRI DREQ0/TMRI0-A DREQ0/TMRI0-A DREQ0/TMRI0-A DREQ0/TMRI0-A 0-A 82 K13 P61/IRQ9-A/ P61/IRQ9-A/ P61/IRQ9-A/ P61/IRQ9-A/ P61/IRQ9-A/ NC DREQ1/TMRI DREQ1/TMRI1-A DREQ1/TMRI1-A DREQ1/TMRI1-A DREQ1/TMRI1-A 1-A 83 J10 P62/IRQ10-A/ P62/IRQ10-A/ P62/IRQ10-A/ NC P62/IRQ10-A/ P62/IRQ10-A/ TEND0/TMCI TEND0/TMCI0-A TEND0/TMCI0-A TEND0/TMCI0-A TEND0/TMCI0-A 0-A 84 J11 PF0/WAIT-A/ PF0/WAIT-A/ ADTRG0-B/ ADTRG0-B/ SCS0-C SCS0-C PF0/WAIT-A/ ADTRG0-B/ SCS0-C PF0/WAIT-A/ ADTRG0-B/ SCS0-C PF0/ ADTRG0-B/ SCS0-C NC 85 H12 PF1/UCAS/ DQMU*1 /IRQ14-A/ SSCK0-C PF1/UCAS/ DQMU*1/ IRQ14-A/ SSCK0-C PF1/UCAS/ DQMU*1/ IRQ14-A/ SSCK0-C PF1/UCAS/ DQMU*1/ IRQ14-A/ SSCK0-C PF1/IRQ14-A/ SSCK0-C NC 86 H10 PF2/LCAS/ DQML*1/ IRQ15A/SSI0-C PF2/LCAS/ DQML*1/ IRQ15-A/SSI0-C PF2/LCAS/ DQML*1/ IRQ15-A/SSI0-C PF2/LCAS/ DQML*1/ IRQ15-A/SSI0-C PF2/IRQ15-A/ SSI0-C NC 87 J13 PF3/LWR/ SSO0-C PF3/LWR/ SSO0-C PF3/LWR/ SSO0-C PF3/LWR/ SSO0-C PF3/ SSO0-C NC 88 H11 HWR HWR HWR HWR PF4 NC 89 G12 RD RD RD RD PF5 NC 90 G10 PF6/AS/AH PF6/AS/AH PF6/AS/AH PF6/AS/AH PF6 NC 91 H13 PLLVcc PLLVcc PLLVcc PLLVcc PLLVcc Vcc 92 G11 RES RES RES RES RES RES 93 G13 PLLVss PLLVss PLLVss PLLVss PLLVss Vss Mode 7 (LGA-145 in Rev. 1.00 Sep. 19, 2008 Page 18 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. Pin Name 5 145-Pin* 144-Pin*4 planning) Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode 94 F10 PF7/φ PF7/φ PF7/φ PF7/φ PF7/φ NC 95 F11 Vss Vss Vss Vss Vss Vss 96 F12 XTAL XTAL XTAL XTAL XTAL XTAL 97 F13 EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL 98 E11 Vcc Vcc Vcc Vcc Vcc Vcc 99 E13 Vcc Vcc Vcc Vcc Vcc Vcc 100 D11 PJ0 PJ0 PJ0 PJ0 PJ0 NC Mode 7 (LGA-145 in 101 E12 PJ1 PJ1 PJ1 PJ1 PJ1 NC 102 E10 Vss Vss Vss Vss Vss Vss 103 D13 STBY STBY STBY STBY STBY Vcc 104 D10 P63/IRQ11-A/ P63/IRQ11-A/ P63/IRQ11-A/ NC P63/IRQ11-A/ P63/IRQ11-A/ TEND1/TMCI TEND1/TMCI1-A TEND1/TMCI1-A TEND1/TMCI1-A TEND1/TMCI1-A 1-A 105 D12 P64/IRQ12-A/ P64/IRQ12-A/ DACK0/TMO DACK0/TMO0-A 0-A P64/IRQ12-A/ DACK0/TMO0-A P64/IRQ12-A/ DACK0/TMO0-A P64/IRQ12-A/ DACK0/TMO0-A NC 106 C13 P65/IRQ13-A/ P65/IRQ13-A/ DACK1/TMO DACK1/TMO1-A 1-A P65/IRQ13-A/ DACK1/TMO1-A P65/IRQ13-A/ DACK1/TMO1-A P65/IRQ13-A/ DACK1/TMO1-A NC 107 C12 PG0/CS0 PG0/CS0 PG0/CS0 PG0/CS0 PG0 NC 108 B13 PG1/CS1 PG1/CS1 PG1/CS1 PG1/CS1 PG1 NC 109 A12 PG2/CS2/ RAS2/RAS PG2/CS2/ RAS2/RAS PG2/CS2/ RAS2/RAS PG2/CS2/ RAS2/RAS PG2 NC 110 A13 PG3/CS3/ PG3/CS3/ RAS3/CAS*1 RAS3/CAS*1 PG3/CS3/ RAS3/CAS*1 PG3/CS3/ RAS3/CAS*1 PG3 NC 111 B11 AVcc AVcc AVcc AVcc AVcc Vcc 112 B12 Vref Vref Vref Vref Vref Vcc 113 A11 P40/AN0_0 P40/AN0_0 P40/AN0_0 P40/AN0_0 P40/AN0_0 NC 114 C11 P41/AN1_0 P41/AN1_0 P41/AN1_0 P41/AN1_0 P41/AN1_0 NC 115 B10 P42/AN2_0 P42/AN2_0 P42/AN2_0 P42/AN2_0 P42/AN2_0 NC 116 C10 P43/AN3_0 P43/AN3_0 P43/AN3_0 P43/AN3_0 P43/AN3_0 Vss 117 A10 P44/AN4_0 P44/AN4_0 P44/AN4_0 P44/AN4_0 P44/AN4_0 Vcc 118 B9 P45/AN5_0 P45/AN5_0 P45/AN5_0 P45/AN5_0 P45/AN5_0 Vss 119 C9 P46/AN6_0 P46/AN6_0 P46/AN6_0 P46/AN6_0 P46/AN6_0 NC 120 B8 P47/AN7_0 P47/AN7_0 P47/AN7_0 P47/AN7_0 P47/AN7_0 NC Rev. 1.00 Sep. 19, 2008 Page 19 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. Pin Name 5 145-Pin* 144-Pin*4 planning) Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode 121 A9 P90/AN8_1 P90/AN8_1 P90/AN8_1 P90/AN8_1 P90/AN8_1 NC 122 D9 P91/AN9_1 P91/AN9_1 P91/AN9_1 P91/AN9_1 P91/AN9_1 NC 123 C8 P92/AN10_1 P92/AN10_1 P92/AN10_1 P92/AN10_1 P92/AN10_1 NC 124 B7 P93/AN11_1 P93/AN11_1 P93/AN11_1 P93/AN11_1 P93/AN11_1 NC 125 A8 P94/AN12_1/ P94/AN12_1/DA2 P94/AN12_1/DA2 P94/AN12_1/DA2 P94/AN12_1/DA2 NC DA2 126 D8 P95/AN13_1/ P95/AN13_1/DA3 P95/AN13_1/DA3 P95/AN13_1/DA3 P95/AN13_1/DA3 NC DA3 127 D7 P96/AN14_1 Mode 7 (LGA-145 in P96/AN14_1 P96/AN14_1 P96/AN14_1 P96/AN14_1 NC 128 D6 P97/AN15_1 P97/AN15_1 P97/AN15_1 P97/AN15_1 P97/AN15_1 NC 129 A7 AVss AVss AVss AVss AVss Vss 130 B6 PG4/BREQO- PG4/BREQO-A/ TCK*3 A/ TCK*3 PG4/BREQO-A/ TCK*3 PG4/BREQO-A/ TCK*3 PG4/TCK*3 NC 131 C7 PG5/ BACKA/TMS*3 PG5/BACK/ TMS*3 PG5/BACK/ TMS*3 PG5/BACK/ TMS*3 PG5/TMS*3 NC 132 D5 PG6/ BREQA/TDI*3 PG6/ BREQ-A/TDI*3 PG6/ BREQ-A/TDI*3 PG6/ BREQ-A/TDI*3 PG6/TDI*3 NC 133 A6 P50/BREQOB/ IRQ0-A/PO0B/ TIOCA3-B/ TMRI0B/TxD2/ SDA3 P50/BREQO-B/ IRQ0-A/PO0-B/ TIOCA3-B/ TMRI0-B/TxD2/ SDA3 P50/BREQO-B/ IRQ0-A/PO0-B/ TIOCA3-B/ TMRI0-B/TxD2/ SDA3 P50/BREQO-B/ IRQ0-A/PO0-B/ TIOCA3-B/ TMRI0-B/TxD2/ SDA3 P50/IRQ0-A/ PO0-B/ TIOCA3-B/ TMRI0-B/TxD2/ SDA3 Vss 134 B5 P51/BREQ-B/ IRQ1-A/PO2B/ TIOCC3-B/ TMCI0B/RxD2/ SCL3 P51/BREQ-B/ IRQ1-A/PO2-B/ TIOCC3-B/ TMCI0-B/RxD2/ SCL3 P51/BREQ-B/ IRQ1-A/PO2-B/ TIOCC3-B/ TMCI0-B/RxD2/ SCL3 P51/BREQ-B/ IRQ1-A/PO2-B/ TIOCC3-B/ TMCI0-B/RxD2/ SCL3 P51/IRQ1-A/ PO2-B/ TIOCC3-B/ TMCI0-B/RxD2/ SCL3 Vss Rev. 1.00 Sep. 19, 2008 Page 20 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. Pin Name 5 145-Pin* Flash Memory Programmer Mode Mode 7 (LGA-145 in 144-Pin*4 planning) Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 135 C6 P52/BACK-B/ IRQ2-A/PO4B/ TIOCA4-B/ TMO0B/SCK2 P52/BACK-B/ IRQ2-A/PO4-B/ TIOCA4-B/ TMO0-B/SCK2 P52/BACK-B/ IRQ2-A/PO4-B/ TIOCA4-B/ TMO0-B/SCK2 P52/BACK-B/ IRQ2-A/PO4-B/ TIOCA4-B/ TMO0-B/SCK2 P52/IRQ2-A/ PO4-B/ TIOCA4-B/ TMO0-B/SCK2 Vcc 136 D4 P53/IRQ3-A/ P53/IRQ3-A/ ADTRG0-A/ ADTRG0-A/ TRST*3 TRST*3 P53/IRQ3-A/ ADTRG0-A/ TRST*3 P53/IRQ3-A/ ADTRG0-A/ TRST*3 P53/IRQ3-A/ ADTRG0-A/ TRST*3 NC 137 A5 P35/OE-B/ CKE-B*1/ SCK1/SCL0 P35/OE-B/ CKE-B*1/ SCK1/SCL0 P35/OE-B/ CKE-B*1/ SCK1/SCL0 P35/OE-B/ CKE-B*1/ SCK1/SCL0 P35/SCK1/ SCL0 NC 138 B4 P34/SCK0/ SCK4A/SDA0 P34/SCK0/ SCK4-A/SDA0 P34/SCK0/ SCK4-A/SDA0 P34/SCK0/ SCK4-A/SDA0 P34/SCK0/ SCK4-A/SDA0 NC 139 C5 P33/RxD1/SC P33/RxD1/SCL1 L1 P33/RxD1/SCL1 P33/RxD1/SCL1 P33/RxD1/SCL1 NC 140 A4 P32/RxD0/ IrRxD/SDA1 P32/RxD0/ IrRxD/SDA1 P32/RxD0/ IrRxD/SDA1 P32/RxD0/ IrRxD/SDA1 P32/RxD0/ IrRxD/SDA1 Vcc 141 B3 P31/TxD1 P31/TxD1 P31/TxD1 P31/TxD1 P31/TxD1 NC 142 C4 P30/TxD0/IrT P30/TxD0/IrTxD xD P30/TxD0/IrTxD P30/TxD0/IrTxD P30/TxD0/IrTxD NC 143 A3 MD0 MD0 MD0 MD0 MD0 Vss 144 A2 MD1 MD1 MD1 MD1 MD1 Vss E5 NC NC NC NC NC NC Notes: 1. 2. 3. 4. 5. Not available in the H8S/2426 Group. Can be used only in FP-144LV version. Can be used only in TLP-145V version. The 144-pin code is FP-144LV. The 145-pin code is TLP-145V. Rev. 1.00 Sep. 19, 2008 Page 21 of 1270 REJ09B0466-0100 Section 1 Overview Table 1.4 Pin Assignments in Each Operating Mode of H8S/2424 Group Pin No. Pin Name 120-PIn Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode 1 MD2 MD2 MD2 MD2 MD2 Vss 2 Vcc Vcc Vcc Vcc Vcc Vcc 3 A0 A0 PC0/A0 PC0/A0 PC0/TIOCA9 A0 Mode 7 4 A1 A1 PC1/A1 PC1/A1 PC1/TIOCB9 A1 5 A2 A2 PC2/A2 PC2/A2 PC2/TIOCC9 A2 6 A3 A3 PC3/A3 PC3/A3 PC3/TIOCD9 A3 7 A4 A4 PC4/A4 PC4/A4 PC4/TIOCA10 A4 8 Vss Vss Vss Vss Vss Vss 9 A5 A5 PC5/A5 PC5/A5 PC5/TIOCB10 A5 10 A6 A6 PC6/A6 PC6/A6 PC6/TIOCA11 A6 11 A7 A7 PC7/A7 PC7/A7 PC7/TIOCB11 A7 12 A8 A8 PB0/A8 PB0/A8 PB0/TIOCA6 A8 13 A9 A9 PB1/A9 PB1/A9 PB1/TIOCB6 A9 14 A10 A10 PB2/A10 PB2/A10 PB2/TIOCC6/ TCLKE A10 15 A11 A11 PB3/A11 PB3/A11 PB3/TIOCD6/ TCLKF A11 16 A12 A12 PB4/A12 PB4/A12 PB4/TIOCA7 A12 17 Vss Vss Vss Vss Vss Vss 18 A13 A13 PB5/A13 PB5/A13 PB5/TIOCB7/ TCLKG A13 19 A14 A14 PB6/A14 PB6/A14 PB6/TIOCA8 A14 20 A15 A15 PB7/A15 PB7/A15 PB7/TIOCB8/ TCLKH A15 21 A16 A16 PA0/A16 PA0/A16 PA0 A16 22 Vss Vss Vss Vss Vss Vss 23 A17 A17 PA1/A17/TxD4-B PA1/A17/TxD4-B PA1/TxD4-B A17 24 A18 A18 PA2/A18/RxD4-B PA2/A18/RxD4-B PA2/RxD4-B A18 25 A19 A19 PA3/A19/SCK4-B PA3/A19/SCK4-B PA3/SCK4-B NC 26 A20/IRQ4-A A20/IRQ4-A PA4/A20/IRQ4-A/ SCS0-B PA4/A20/IRQ4-A/ SCS0-B PA4/IRQ4-A/ SCS0-B NC 27 PA5/A21/IRQ5-A/ PA5/A21/IRQ5-A/ SSCK0-B SSCK0-B PA5/A21/IRQ5-A/ SSCK0-B PA5/A21/IRQ5-A/ SSCK0-B PA5/IRQ5-A/ SSCK0-B NC Rev. 1.00 Sep. 19, 2008 Page 22 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. Pin Name Flash Memory Programmer Mode Mode 7 120-PIn Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 28 PA6/A22/ IRQ6-A/SSI0-B PA6/A22/ IRQ6-A/SSI0-B PA6/A22/ IRQ6-A/SSI0-B PA6/A22/ IRQ6-A/SSI0-B PA6/IRQ6-A/ SSI0-B NC 29 PA7/A23/CS7/ IRQ7-A/SSO0-B PA7/A23/CS7/ IRQ7-A/SSO0-B PA7/A23/CS7/ IRQ7-A/SSO0-B PA7/A23/CS7/ IRQ7-A/SSO0-B PA7/IRQ7-A/ SSO0-B NC 30 EMLE EMLE EMLE EMLE EMLE Vss 31 WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF NC 32 NMI NMI NMI NMI NMI Vcc 33 VCL VCL VCL VCL VCL VCL 34 P10/DREQ0/ PO8/TIOCA0 P10/DREQ0/ PO8/TIOCA0 P10/DREQ0/ PO8/TIOCA0 P10/DREQ0/ PO8/TIOCA0 P10/DREQ0/ PO8/TIOCA0 NC 35 P11/DREQ1/ PO9/TIOCB0 P11/DREQ1/ PO9/TIOCB0 P11/DREQ1/ PO9/TIOCB0 P11/DREQ1/ PO9/TIOCB0 P11/DREQ1/ PO9/TIOCB0 NC 36 P12/TEND0/ PO10/TIOCC0/ TCLKA P12/TEND0/ PO10/TIOCC0/ TCLKA P12/TEND0/ PO10/TIOCC0/ TCLKA P12/TEND0/ PO10/TIOCC0/ TCLKA P12/TEND0/ PO10/TIOCC0/ TCLKA OE 37 P13/TEND1/ PO11/TIOCD0/ TCLKB P13/TEND1/ PO11/TIOCD0/ TCLKB P13/TEND1/ PO11/TIOCD0/ TCLKB P13/TEND1/ PO11/TIOCD0/ TCLKB P13/TEND1/ PO11/TIOCD0/ TCLKB CE 38 P14/DACK0/ PO12/TIOCA1/ SSO0-A P14/DACK0/ PO12/TIOCA1/ SSO0-A P14/DACK0/ PO12/TIOCA1/ SSO0-A P14/DACK0/ PO12/TIOCA1/ SSO0-A P14/DACK0/ PO12/TIOCA1/ SSO0-A WE 39 P15/DACK1/ PO13/TIOCB1/ TCLKC/SSI0-A P15/DACK1/ PO13/TIOCB1/ TCLKC/SSI0-A P15/DACK1/ PO13/TIOCB1/ TCLKC/SSI0-A P15/DACK1/ PO13/TIOCB1/ TCLKC/SSI0-A P15/DACK1/ PO13/TIOCB1/ TCLKC/SSI0-A NC 40 P16/PO14/ TIOCA2/ SSCK0-A P16/PO14/ TIOCA2/ SSCK0-A P16/PO14/ TIOCA2/ SSCK0-A P16/PO14/ TIOCA2/ SSCK0-A P16/PO14/ TIOCA2/ SSCK0-A NC 41 P17/PO15/ TIOCB2/ TCLKD/SCS0-A P17/PO15/ TIOCB2/ TCLKD/SCS0-A P17/PO15/ TIOCB2/ TCLKD/SCS0-A P17/PO15/ TIOCB2/ TCLKD/SCS0-A P17/PO15/ TIOCB2/ TCLKD/SCS0-A NC 42 P20/PO0-A/ TIOCA3-A/ TMRI0-A P20/PO0-A/ TIOCA3-A/ TMRI0-A P20/PO0-A/ TIOCA3-A/ TMRI0-A P20/PO0-A/ TIOCA3-A/ TMRI0-A P20/PO0-A/ TIOCA3-A/ TMRI0-A NC 43 P21/PO1-A/ TIOCB3-A/ TMRI1-A P21/PO1-A/ TIOCB3-A/ TMRI1-A P21/PO1-A/ TIOCB3-A/ TMRI1-A P21/PO1-A/ TIOCB3-A/ TMRI1-A P21/PO1-A/ TIOCB3-A/ TMRI1-A Vcc 44 P22/PO2-A/ TIOCC3-A/ TMCI0-A P22/PO2-A/ TIOCC3-A/ TMCI0-A P22/PO2-A/ TIOCC3-A/ TMCI0-A P22/PO2-A/ TIOCC3-A/ TMCI0-A P22/PO2-A/ TIOCC3-A/ TMCI0-A NC Rev. 1.00 Sep. 19, 2008 Page 23 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. Pin Name Mode 7 120-PIn Mode 1 45 Mode 2 Flash Memory Programmer Mode Mode 4 EXPE = 1 EXPE = 0 P23/PO3-A/ P23/PO3-A/ TIOCD3-A/ TIOCD3-A/ TMCI1-A/TxD4-A TMCI1-A/TxD4-A P23/PO3-A/ TIOCD3-A/ TMCI1-A/TxD4-A P23/PO3-A/ TIOCD3-A/ TMCI1-A/TxD4-A P23/PO3-A/ TIOCD3-A/ TMCI1-A/TxD4-A NC 46 P24/PO4-A/ P24/PO4-A/ TIOCA4-A/ TIOCA4-A/ TMO0-A/RxD4-A TMO0-A/RxD4-A P24/PO4-A/ TIOCA4-A/ TMO0-A/RxD4-A P24/PO4-A/ TIOCA4-A/ TMO0-A/RxD4-A P24/PO4-A/ TIOCA4-A/ TMO0-A/RxD4-A Vss 47 P25/WAIT-B/ PO5-A/ TIOCB4-A/ TMO1-A P25/WAIT-B/ PO5-A/ TIOCB4-A/ TMO1-A P25/WAIT-B/ PO5-A/ TIOCB4-A/ TMO1-A P25/WAIT-B/ PO5-A/ TIOCB4-A/ TMO1-A P25/PO5-A/ NC TIOCB4-A/TMO1-A 48 P26/PO6/ TIOCA5/SDA2/ ADTRG1 P26/PO6/ TIOCA5/SDA2/ ADTRG1 P26/PO6/ TIOCA5/SDA2/ ADTRG1 P26/PO6/ TIOCA5/SDA2/ ADTRG1 P26/PO6/ TIOCA5/SDA2/ ADTRG1 NC 49 P27/PO7/ TIOCB5/SCL2 P27/PO7/ TIOCB5/SCL2 P27/PO7/ TIOCB5/SCL2 P27/PO7/ TIOCB5/SCL2 P27/PO7/ TIOCB5/SCL2 NC 50 P85/PO5-B/ TIOCB4-B/ TMO1-B/SCK3 P85/PO5-B/ TIOCB4-B/ TMO1-B/SCK3 P85/PO5-B/ TIOCB4-B/ TMO1-B/SCK3 P85/PO5-B/ TIOCB4-B/ TMO1-B/SCK3 P85/PO5-B/ TIOCB4-B/ TMO1-B/SCK3 NC 51 PE0/D0 PE0/D0 PE0/D0 PE0/D0 PE0 NC 52 PE1/D1 PE1/D1 PE1/D1 PE1/D1 PE1 NC 53 PE2/D2 PE2/D2 PE2/D2 PE2/D2 PE2 NC 54 PE3/D3 PE3/D3 PE3/D3 PE3/D3 PE3 NC 55 PE4/D4 PE4/D4 PE4/D4 PE4/D4 PE4 NC 56 PE5/D5 PE5/D5 PE5/D5 PE5/D5 PE5 NC 57 PE6/D6 PE6/D6 PE6/D6 PE6/D6 PE6 NC 58 Vss Vss Vss Vss Vss Vss 59 PE7/D7 PE7/D7 PE7/D7 PE7/D7 PE7 NC 60 Vcc Vcc Vcc Vcc Vcc Vcc 61 D8 D8 D8 D8 PD0 I/O0 62 D9 D9 D9 D9 PD1 I/O1 63 D10 D10 D10 D10 PD2 I/O2 64 D11 D11 D11 D11 PD3 I/O3 65 D12 D12 D12 D12 PD4 I/O4 66 D13 D13 D13 D13 PD5 I/O5 67 D14 D14 D14 D14 PD6 I/O6 68 D15 D15 D15 D15 PD7 I/O7 Rev. 1.00 Sep. 19, 2008 Page 24 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. Pin Name Flash Memory Programmer Mode Mode 7 120-PIn Mode 1 69 PF0/WAIT-A/ PF0/WAIT-A/ PF0/WAIT-A/ PF0/WAIT-A/ PF0/ OE-A/ADTRG0-B/ OE-A/ADTRG0-B/ OE-A/ADTRG0-B/ OE-A/ADTRG0-B/ ADTRG0-B/ SCS0-C SCS0-C SCS0-C SCS0-C SCS0-C NC 70 PF1/CS5/UCAS/ PF1/CS5/UCAS/ SSCK0-C SSCK0-C PF1/CS5/UCAS/ SSCK0-C PF1/CS5/UCAS/ SSCK0-C PF1/SSCK0-C NC 71 PF2/CS6/ LCAS/SSI0-C PF2/CS6/ LCAS/SSI0-C PF2/CS6/ LCAS/SSI0-C PF2/CS6/ LCAS/SSI0-C PF2/ SSI0-C NC 72 PF3/LWR/ SSO0-C PF3/LWR/ SSO0-C PF3/LWR/ SSO0-C PF3/LWR/ SSO0-C PF3/ SSO0-C NC 73 HWR HWR HWR HWR PF4 NC 74 RD RD RD RD PF5 NC 75 PF6/AS/AH PF6/AS/AH PF6/AS/AH PF6/AS/AH PF6 NC 76 PLLVcc PLLVcc PLLVcc PLLVcc PLLVcc Vcc 77 RES RES RES RES RES RES 78 PLLVss PLLVss PLLVss PLLVss PLLVss Vss 79 PF7/φ PF7/φ PF7/φ PF7/φ PF7/φ NC 80 Vss Vss Vss Vss Vss Vss 81 XTAL XTAL XTAL XTAL XTAL XTAL 82 EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL 83 Vcc Vcc Vcc Vcc Vcc Vcc 84 Vcc Vcc Vcc Vcc Vcc Vcc 85 P83/PO3-B/ TIOCD3-B/ TMCI1-B/RxD3 P83/PO3-B/ TIOCD3-B/ TMCI1-B/RxD3 P83/PO3-B/ TIOCD3-B/ TMCI1-B/RxD3 P83/PO3-B/ TIOCD3-B/ TMCI1-B/RxD3 P83/PO3-B/ TIOCD3-B/ TMCI1-B/RxD3 NC 86 P81/PO1-B/ TIOCB3-B/ TMRI1-B/TxD3 P81/PO1-B/ TIOCB3-B/ TMRI1-B/TxD3 P81/PO1-B/ TIOCB3-B/ TMRI1-B/TxD3 P81/PO1-B/ TIOCB3-B/ TMRI1-B/TxD3 P81/PO1-B/ TIOCB3-B/ TMRI1-B/TxD3 NC 87 Vss Vss Vss Vss Vss Vss 88 STBY STBY STBY STBY STBY Vcc 89 PG0/CS0 PG0/CS0 PG0/CS0 PG0/CS0 PG0 NC 90 PG1/CS1 PG1/CS1 PG1/CS1 PG1/CS1 PG1 NC PG2 NC 91 Mode 2 Mode 4 3 3 3 3 PG2/CS2/RAS2* PG2/CS2/RAS2* EXPE = 1 3 PG2/CS2/RAS2* 3 EXPE = 0 3 PG2/CS2/RAS2* 3 92 PG3/CS3/RAS3* PG3/CS3/RAS3* PG3/CS3/RAS3* PG3/CS3/RAS3* PG3 NC 93 AVcc AVcc AVcc AVcc AVcc Vcc 94 Vref Vref Vref Vref Vref Vcc Rev. 1.00 Sep. 19, 2008 Page 25 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. Pin Name Mode 7 Flash Memory Programmer Mode 120-PIn Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 95 P40/IRQ0-B/ AN0_0 P40/IRQ0-B/ AN0_0 P40/IRQ0-B/ AN0_0 P40/IRQ0-B/ AN0_0 P40/IRQ0-B/ AN0_0 NC 96 P41/IRQ1-B/ AN1_0 P41/IRQ1-B/ AN1_0 P41/IRQ1-B/ AN1_0 P41/IRQ1-B/ AN1_0 P41/IRQ1-B/ AN1_0 NC 97 P42/IRQ2-B/ AN2_0 P42/IRQ2-B/ AN2_0 P42/IRQ2-B/ AN2_0 P42/IRQ2-B/ AN2_0 P42/IRQ2-B/ AN2_0 NC 98 P43/IRQ3-B/ AN3_0 P43/IRQ3-B/ AN3_0 P43/IRQ3-B/ AN3_0 P43/IRQ3-B/ AN3_0 P43/IRQ3-B/ AN3_0 Vss 99 P44/IRQ4-B/ AN4_0 P44/IRQ4-B/ AN4_0 P44/IRQ4-B/ AN4_0 P44/IRQ4-B/ AN4_0 P44/IRQ4-B/ AN4_0 Vcc 100 P45/IRQ5-B/ AN5_0 P45/IRQ5-B/ AN5_0 P45/IRQ5-B/ AN5_0 P45/IRQ5-B/ AN5_0 P45/IRQ5-B/ AN5_0 Vss 101 P46/IRQ6-B/ AN6_0 P46/IRQ6-B/ AN6_0 P46/IRQ6-B/ AN6_0 P46/IRQ6-B/ AN6_0 P46/IRQ6-B/ AN6_0 NC 102 P47/IRQ7-B/ AN7_0 P47/IRQ7-B/ AN7_0 P47/IRQ7-B/ AN7_0 P47/IRQ7-B/ AN7_0 P47/IRQ7-B/ AN7_0 NC 103 P94/AN12_1/DA2 P94/AN12_1/DA2 P94/AN12_1/DA2 P94/AN12_1/DA2 P94/AN12_1/DA2 NC 104 P95/AN13_1/DA3 P95/AN13_1/DA3 P95/AN13_1/DA3 P95/AN13_1/DA3 P95/AN13_1/DA3 NC 105 AVss AVss AVss AVss AVss Vss 106 PG4/BREQO-A/ CS4 PG4/BREQO-A/ CS4 PG4/BREQO-A/ CS4 PG4/BREQO-A/ CS4 PG4 NC 107 PG5/BACK-A PG5/BACK-A PG5/BACK-A PG5/BACK-A PG5 NC 108 PG6/BREQ-A PG6/BREQ-A PG6/BREQ-A PG6/BREQ-A PG6 NC 109 P50/BREQO-B/ IRQ0-A/PO0-B/ TIOCA3-B/ TMRI0-B/ TxD2/SDA3 P50/BREQO-B/ IRQ0-A/PO0-B/ TIOCA3-B/ TMRI0-B/ TxD2/SDA3 P50/BREQO-B/ IRQ0-A/PO0-B/ TIOCA3-B/ TMRI0-B/ TxD2/SDA3 P50/BREQO-B/ IRQ0-A/PO0-B/ TIOCA3-B/ TMRI0-B/ TxD2/SDA3 P50/IRQ0-A/ PO0-B/ TIOCA3-B/ TMRI0-B/ TxD2/SDA3 Vss 110 P51/BREQ-B/ IRQ1-A/PO2-B/ TIOCC3-B/ TMCI0-B/ RxD2/SCL3 P51/BREQ-B/ IRQ1-A/PO2-B/ TIOCC3-B/ TMCI0-B/ RxD2/SCL3 P51/BREQ-B/ IRQ1-A/PO2-B/ TIOCC3-B/ TMCI0-B/ RxD2/SCL3 P51/BREQ-B/ IRQ1-A/PO2-B/ TIOCC3-B/ TMCI0-B/ RxD2/SCL3 P51/IRQ1-A/ PO2-B/ TIOCC3-B/ TMCI0-B/ RxD2/SCL3 Vss 111 P52/BACK-B/ IRQ2-A/PO4-B/ TIOCA4-B/ TMO0-B/SCK2 P52/BACK-B/ IRQ2-A/PO4-B/ TIOCA4-B/ TMO0-B/SCK2 P52/BACK-B/ IRQ2-A/PO4-B/ TIOCA4-B/ TMO0-B/SCK2 P52/BACK-B/ IRQ2-A/PO4-B/ TIOCA4-B/ TMO0-B/SCK2 P52/IRQ2-A/ PO4-B/ TIOCA4-B/ TMO0-B/SCK2 Vcc 112 P53/IRQ3-A/ ADTRG0-A P53/IRQ3-A/ ADTRG0-A P53/IRQ3-A/ ADTRG0-A P53/IRQ3-A/ ADTRG0-A P53/IRQ3-A/ ADTRG0-A NC Rev. 1.00 Sep. 19, 2008 Page 26 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. Pin Name Flash Memory Programmer Mode Mode 7 120-PIn Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 113 P35/OE-B/ SCK1/SCL0 P35/OE-B/ SCK1/SCL0 P35/OE-B/ SCK1/SCL0 P35/OE-B/ SCK1/SCL0 P35/SCK1/ SCL0 NC 114 P34/SCK0/ SCK4-A/SDA0 P34/SCK0/ SCK4-A/SDA0 P34/SCK0/ SCK4-A/SDA0 P34/SCK0/ SCK4-A/SDA0 P34/SCK0/ SCK4-A/SDA0 NC 115 P33/RxD1/SCL1 P33/RxD1/SCL1 P33/RxD1/SCL1 P33/RxD1/SCL1 P33/RxD1/SCL1 NC 116 P32/RxD0/ IrRxD/SDA1 P32/RxD0/ IrRxD/SDA1 P32/RxD0/ IrRxD/SDA1 P32/RxD0/ IrRxD/SDA1 P32/RxD0/ IrRxD/SDA1 Vcc 117 P31/TxD1 P31/TxD1 P31/TxD1 P31/TxD1 P31/TxD1 NC 118 P30/TxD0/IrTxD P30/TxD0/IrTxD P30/TxD0/IrTxD P30/TxD0/IrTxD P30/TxD0/IrTxD NC 119 MD0 MD0 MD0 MD0 MD0 Vss 120 MD1 MD1 MD1 MD1 MD1 Vss Rev. 1.00 Sep. 19, 2008 Page 27 of 1270 REJ09B0466-0100 Section 1 Overview 1.4.3 Pin Functions Table 1.5 Pin Functions Pin No. H8S/2426, H8S/2426R H8S/2424 Type Symbol FP-144LV TLP-145V FP-120BV I/O Function Power supply VCC 4, 72, 98, 99 B2, N12, E11, E13 2, 60, 83, 84 Input For connection to the power supply. VCC pins should be connected to the system power supply. VSS A1, E2, F4, H1, 2, 10, 18, 25, 50, 70, N5, M11, E10, F11 95, 102 8, 17, 22, 58, 80, 87 Input For connection to ground. VSS pins should be connected to the system power supply (0 V). PLLVCC 91 H13 76 Input Power supply pin for the onchip PLL oscillator. PLLVSS 93 G13 78 Input Ground pin for the on-chip PLL oscillator. VCL 41 L3 33 Output This pin must not be connected to the power supply and should be connected to the VSS pin via a 0.1-µF (recommended value) capacitor (place it close to pin). XTAL 96 F12 81 Input For connection to a crystal oscillator. See section 23, Clock Pulse Generator, for typical connection diagrams for a crystal resonator and external clock input. EXTAL 97 F13 82 Input For connection to a crystal oscillator. The EXTAL pin can also input an external clock. See section 23, Clock Pulse Generator, for typical connection diagrams for a crystal resonator and external clock input. φ 94 F10 79 Output Supplies the system clock to external devices. Clock Rev. 1.00 Sep. 19, 2008 Page 28 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. H8S/2426, H8S/2426R Type Symbol 1 H8S/2424 FP-144LV TLP-145V FP-120BV I/O Function 36 M1 Output When a synchronous DRAM is connected, this pin is connected to the CLK pin of the synchronous DRAM. For details, refer to section 6, Bus Controller (BSC). Input These pins set the operating mode. These pins should not be changed during operation. Clock SDRAMφ* Operating mode control MD2 1 B1 1 MD1 144 A2 120 MD0 143 A3 119 RES 92 G12 77 Input Reset pin. When this pin is driven low, the chip is reset. STBY 103 D13 88 Input When this pin is driven low, a transition is made to hardware standby mode. EMLE 32 K1 30 Input On-chip emulator enable pin. When the on-chip emulator is used, this pin should be fixed high. At this time, pins P53, PG4 to PG6, and WDTOVF are used exclusively by the on-chip emulator. Therefore, the corresponding pin functions of those pins are not available. When the on-chip emulator is not used, this pin should be fixed low. L9 Input Boundary scan enable pin. When the boundary scan function is used, this pin should be fixed high. At this time, pins P53, PG4 to PG6, and WDTOVF are used exclusively for boundary scan. Therefore, the corresponding pin functions of those pins are not available. When the boundary scan function is not used, this pin should be fixed low. System control 2 BSCANE* Rev. 1.00 Sep. 19, 2008 Page 29 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. H8S/2426, H8S/2426R H8S/2424 Type Symbol FP-144LV TLP-145V FP-120BV I/O Address bus A23 to A0 31 to 26, 24 to 19, 17 to 11, 9 to 5 J3, K2, J1, K4, H3, J2, J4, G3, H2, G1, H4, G4, F1, G2, F3, E4, E1, F2, E3, D1, D3, D2, C3, C1 29 to 23, 21 to 18, 16 to 9, 7 to 3 Output These pins output an address. Data bus D15 to D0 80 to 73, 71, 69 to 63 68 to 61, K11, K12, L13, 59, L11, M12, L12, 57 to 51 N13, M13, N11, M11, N10, L9, M10, N9, K10, L8 Bus control CS7 to CS0 38 to 35, M2, N2, M1, 110 to 107 L1, A13, A12, B13, C12 29, 71, 70, 106, 92 to 89 Output Signals that select division areas 7 to 0 in the external address space AS 90 G10 75 Output When this pin is low, it indicates that address output on the address bus is valid. AH 90 G10 75 Output Signal for holding the address when an address/data multiplexed I/O space is being accessed. RD 89 G12 74 Output When this pin is low, it indicates that the external address space is being read. Rev. 1.00 Sep. 19, 2008 Page 30 of 1270 REJ09B0466-0100 Input/ output Function These pins constitute a bidirectional data bus. When an address/data multiplexed I/O space is accessed, an address is also output. Section 1 Overview Pin No. H8S/2426, H8S/2426R H8S/2424 Type Symbol FP-144LV TLP-145V FP-120BV I/O Bus control HWR 88 H11 73 Output Strobe signal indicating that an external address space is to be written to, and the upper half (D15 to D8) of the data bus is enabled. Also functions as the write enable signal for accessing the DRAM space. LWR 87 J13 72 Output Strobe signal indicating that an external address space is to be written to, and the lower half (D7 to D0) of the data bus is enabled. BREQ-A 132 D5 108 Input BREQ-B 134 B5 110 BREQO-A 130 B6 106 BREQO-B 133 A6 109 BACK-A 131 C7 107 BACK-B 135 C6 111 UCAS 85 H12 70 Output Upper column address strobe signal for accessing the 16-bit DRAM space. Also functions as the column address strobe signal for accessing the 8-bit DRAM space. LCAS 86 H10 71 Output Lower column address strobe signal for accessing the 16-bit DRAM space. DQMU* 85 H12 Output Upper data mask enable signal for accessing the 16-bit continuous synchronous DRAM space. Also functions as the data mask enable signal for accessing the 8-bit continuous synchronous DRAM space. 1 86 H10 Output Lower-data mask enable signal for accessing the 16-bit continuous synchronous DRAM interface space. 1 DQML* Function The external bus master requests the bus to this LSI. Output External bus request signal when the internal bus master accesses an external space in the external bus release state. Output Indicates the bus is released to the external bus master. Rev. 1.00 Sep. 19, 2008 Page 31 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. H8S/2426, H8S/2426R Type Symbol Bus control FP-144LV H8S/2424 TLP-145V FP-120BV I/O Function RAS/RAS2 109 A12 91 RAS3 Output Row address strobe signal for the DRAM when the DRAM interface is set. RAS signal is a row address strobe signal when areas 2 to 5 are set as the continuous DRAM space. 110 A13 92 RAS4* 35 L1 RAS5* 36 M1 RAS* 109 A12 Output Row address strobe signal for the synchronous DRAM when the synchronous DRAM interface is set. CAS* 110 A13 Output Column address strobe signal for the synchronous DRAM when the synchronous DRAM interface is set. WE* 35 L1 Output Write enable signal for the synchronous DRAM when the synchronous DRAM interface is set. WAIT-A 84 J11 69 Input WAIT-B 56 N7 47 OE-A 38 M2 69 OE-B 137 A5 113 1 38 M2 1 137 A5 3 3 1 1 1 CKE-A* CKE-B* Rev. 1.00 Sep. 19, 2008 Page 32 of 1270 REJ09B0466-0100 Requests insertion of a wait state in the bus cycles when accessing an external 3-state address space. Output Output enable signal when accessing the DRAM space. The output pins of OE and (OE) are selected by the port function control register 2 (PFCR2) of port 3. Output Clock enable signal when the synchronous DRAM interface is set. The output pins of CKE and (CKE) are selected by the port function control register 2 (PFCR2) of port 3. Section 1 Overview Pin No. H8S/2426, H8S/2426R H8S/2424 Type Symbol FP-144LV TLP-145V FP-120BV I/O Function Interrupt signals NMI 40 N1 32 Input Nonmaskable interrupt request pin. This pin should be fixed high when not used. H10, H12, C13, IRQ15-A to 86, 85, 3 IRQ8-A* 106 to 104, D12, D10, J10, K13, J12 83 to 81 Input These pins request a maskable interrupt. IRQ7-A to IRQ0-A 29 to 26, 112 to 109 31 to 28, J3, K2, J1, K4, 136 to 133 D4, C6, B5, A6 The input pins of IRQn-A and IRQn-B are selected by the IRQ pin select register (ITSR) of the interrupt controller. IRQ15-B to 58 to 51 3 IRQ8-B* K7, L8, N7, M7, N6, M6, L7, L6, IRQ7-B to IRQ0-B 38, 37, 61 to 59, 34, 33, 3 M2, N2, M8, N8, K8, K3, L2, C2 102 to 95 DREQ1 82 K13 35 DREQ0 81 J12 34 TEND1 104 D10 37 TEND0 83 J10 36 DACK1 106 C13 39 DACK0 105 D12 38 EXDMA EDREQ3 controller EDREQ2 (EXDMAC) 3 ETEND3 * 33 L2 Input 3 C2 59 K8 ETEND2 34 K3 Output These signals indicate the end of EXDMAC data transfer. EDACK3 61 M8 EDACK2 60 N8 Output EXDMAC single address transfer acknowledge signals. EDRAK3 49 L5 EDRAK2 48 K6 Output These signals notify an external device of acceptance and start of execution of a DMA transfer request. DMA controller (DMAC) (n = 0 to 15 for the H8S/2426 Group and H8S/2426R Group, n = 0 to 7 for the H8S/2424 Group) Input These signals request DMAC activation. Output These signals indicate the end of DMAC data transfer. Output DMAC single address transfer acknowledge signals. These signals request EXDMAC activation. Rev. 1.00 Sep. 19, 2008 Page 33 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. H8S/2426, H8S/2426R Type Symbol H8S/2424 FP-144LV TLP-145V FP-120BV I/O Function 16-bit timer TCLKH pulse TCLKG unit (TPU) TCLKF 22 H2 20 Input 20 H4 18 External clock input pins of the timer. 17 F1 15 TCLKE 16 G2 14 TCLKD 49 L5 41 TCLKC 47 K5 39 TCLKB 45 M5 37 TCLKA 44 L4 36 TIOCA0 42 N3 34 TIOCB0 43 M4 35 Input/ output TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins. TIOCC0 44 L4 36 TIOCD0 45 M5 37 TIOCA1 46 N4 38 TIOCB1 47 K5 39 Input/ output TGRA_1 and TGRB_1 input capture input/output compare output/PWM output pins. TIOCA2 48 K6 40 TIOCB2 49 L5 41 Input/ output TGRA_2 and TGRB_2 input capture input/output compare output/PWM output pins. TIOCA3-A 51 L6 42 TIOCB3-A Input/ output TGRA_3 to TGRD_3 input capture input/output compare output/PWM output pins. Input/ output TGRA_4 and TGRB_4 input capture input/output compare output/PWM output pins. Input/ output TGRA_5 and TGRB_5 input capture input/output compare output/PWM output pins. 52 M7 43 TIOCC3-A 53 N6 44 TIOCD3-A 54 K6 45 TIOCA3-B 133 A6 109 TIOCB3-B 33 L2 86 TIOCC3-B 134 B5 110 TIOCD3-B 59 K8 85 TIOCA4-A 55 K7 46 TIOCB4-A 56 N7 47 TIOCA4-B 135 C6 111 TIOCB4-B 61 M8 50 TIOCA5 57 L8 48 TIOCB5 58 K7 49 Rev. 1.00 Sep. 19, 2008 Page 34 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. H8S/2426, H8S/2426R Type FP-144LV TLP-145V FP-120BV I/O Function 16-bit timer TIOCA6 pulse TIOCB6 unit (TPU) TIOCC6 14 E4 12 15 F3 13 Input/ output TGRA_6 to TGRD_6 input capture input/output compare output/PWM output pins. 16 G2 14 TIOCD6 17 F1 15 TIOCA7 19 G4 16 TIOCB7 20 H4 18 Input/ output TGRA_7 and TGRB_7 input capture input/output compare output/PWM output pins. Input/ output TGRA_8 and TGRB_8 input capture input/output compare output/PWM output pins. Input/ output TGRA_9 to TGRD_9 input capture input/output compare output/PWM output pins. Input/ output TGRA_10 and TGRB_10 input capture input/output compare output/PWM output pins. Input/ output TGRA_11 and TGRB_11 input capture input/output compare output/PWM output pins. Programmable pulse generator (PPG) Symbol H8S/2424 TIOCA8 21 G1 19 TIOCB8 22 H2 20 TIOCA9 5 C1 3 TIOCB9 6 C3 4 TIOCC9 7 D2 5 TIOCD9 8 D3 6 TIOCA10 9 D1 7 TIOCB10 11 E3 9 TIOCA11 12 F2 10 TIOCB11 13 E1 11 PO15 to PO8 49 to 42 L5, K6, K5, N4, M5, L4, M4, N3 41 to 34 PO7 58 to 51 K7, L8, N7, M7, N6, M6, L7, L6 49 to 42 PO5-B 61 M8 50 PO4-B 135 C6 111 PO3-B 59 K8 85 PO2-B 134 B5 110 PO1-B 33 L2 86 PO0-B 133 A6 109 PO6 Output Pulse output pins. PO5-A to PO0-A Rev. 1.00 Sep. 19, 2008 Page 35 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. H8S/2426, H8S/2426R H8S/2424 Type Symbol FP-144LV TLP-145V FP-120BV I/O Function 8-bit timer (TMR) TMO0-A 105 D12 46 TMO1-A 106 C13 47 Output Waveform output pins with output compare function. TMO0-B 135 C6 111 TMO1-B 61 M8 50 TMCI0-A 83 J10 44 TMCI1-A 104 D10 45 TMCI0-B 134 B5 110 TMCI1-B 59 K8 85 TMRI0-A 81 J12 42 TMRI1-A 82 K13 43 TMRI0-B 133 A6 109 Input External event input pins. Input Counter reset input pins. TMRI1-B 33 L2 86 Watchdog timer (WDT) WDTOVF 39 M3 31 Output Counter overflow signal output pin in watchdog timer mode. Serial communication interface (SCI)/ Smart Card interface (SCI_0 with IrDA function) TxD4-A 54 K6 45 Output Data output pins. TxD4-B 24 J4 23 TxD3 33 L2 86 TxD2 133 A6 109 TxD1 141 B3 117 TxD0/ IrTxD 142 C4 118 RxD4-A 55 K7 46 RxD4-B 26 J2 24 RxD3 59 K8 85 RxD2 134 C5 110 RxD1 139 A4 115 RxD0/ IrRxD 140 SCK4-A 138 B4 114 SCK4-B 27 H3 25 SCK3 61 M8 50 SCK2 135 C6 111 SCK1 137 A5 113 SCK0 138 B4 114 Data input pins. Input/ output Clock input/output pins. 116 Rev. 1.00 Sep. 19, 2008 Page 36 of 1270 REJ09B0466-0100 Input Section 1 Overview Pin No. H8S/2426, H8S/2426R Type Symbol 2 I C bus SCL3 interface 2 SCL2 (IIC2) SCL1 Synchronous serial communication unit (SSU) Boundary 2 scan* (JTAG) H8S/2424 FP-144LV TLP-145V FP-120BV I/O Function 134 B5 110 I C clock input/output pins. 58 K7 49 Input/ output 139 C5 115 Input/ output I C data input/output pins. Input/ output Data input/output pins. Input/ output Data input/output pins. Input/ output Clock input/output pins. Input/ output Chip select input/output pins. 2 SCL0 137 A5 113 SDA3 133 A6 109 SDA2 57 L8 48 SDA1 140 A4 116 SDA0 138 B4 114 SSO0-A 46 N4 38 SSO0-B 31 J3 29 SSI0-A 47 K5 39 SSI0-B 30 K2 28 SSCK0-A 48 K6 40 SSCK0-B 29 J1 27 SCS0-A 49 L5 41 SCS0-B 28 K4 26 TRST D4 Input TAP controller reset pin. TMS C7 Input Control signal input pin for boundary scan. TDO M3 Output Data output pin for boundary scan. TDI D5 Input Data input pin for boundary scan. TCK B6 Input Clock input pin for boundary scan. 2 Rev. 1.00 Sep. 19, 2008 Page 37 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. H8S/2426, H8S/2426R Type A/D converter Symbol H8S/2424 FP-144LV TLP-145V FP-120BV I/O Function 3 128 D6 Input Analog input pins. 3 AN14_1* 127 D7 AN13_1 126 D8 104 Input Analog input pins. AN12_1 125 A8 AN15_1* 103 AN11_1 to 124 to 121 B7, C8, D9, A9 3 AN8_1* Input Analog input pins. AN7_0 to AN0_0 102 to 95 Input Analog input pins. Input Pin for input of an external trigger to start A/D conversion. 120 to 113 B8, C9, B9, A10, C10, B10, C11, A11 ADTRG0-A 136 D4 112 ADTRG0-B 84 J11 69 ADTRG1 57 L8 48 D/A converter DA3 126 D8 104 DA2 125 A8 103 A/D converter, D/A converter AVCC 111 B11 93 Input Analog power-supply pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+3 V). AVSS 129 A7 105 Input Ground pin for the A/D converter and D/A converter. This pin should be connected to the system power supply (0 V). Vref 112 B12 94 Input Reference voltage input pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+3 V). Rev. 1.00 Sep. 19, 2008 Page 38 of 1270 REJ09B0466-0100 Output Analog output pins. Section 1 Overview Pin No. H8S/2426, H8S/2426R H8S/2424 Type Symbol FP-144LV TLP-145V FP-120BV I/O Function I/O ports P17 to P10 49 to 42 L5, K6, K5, N4, M5, L4, M4, N3 41 to 34 Input/ output 8-bit input/output pins. P27 to P20 58 to 51 K7, L8, N7, M7, N6, M6, L7, L6 49 to 42 Input/ output 8-bit input/output pins. P35 to P30 137 to 142 A5, B4, C5, A4, B3, C4 113 to 118 Input/ output 6-bit input/output pins. P47 to P40 120 to 113 B8, C9, B9, A10, C10, B10, C11, A11 102 to 95 Input 8-bit input pins. P53 to P50 136 to 133 D4, C6, B5, A6 112 to 109 Input/ output 4-bit input/output pins. P65 to P60 106 to 104, C13, D12, D10, 83 to 81 J10, K13, J12 Input/ output 6-bit input/output pins. P85 61 M8 50 P84* 60 N8 Input/ output 6-bit input/output pins in the H8S/2426 Group and H8S/2426R Group. P83 59 K8 85 P82* 34 K3 P81 3 3 3-bit input/output pins in the H8S/2424 Group. 33 L2 86 3 3 C2 P97* , 3 P96* , P95, P94, P93 to 3 P90* 3 128 to 121 D6, D7, D8, A8, B7, C8, D9, A9 PA7 to PA0 31 to 26, 24, 23 J3, K2, J1, K4, H3, J2, J4, G3 29 to 23, 21 Input/ output 8-bit input/output pins. PB7 to PB0 22 to 19, 17 to 14 H2, G1, H4, G4, F1, G2, F3, E4 20 to 18, 16 to 12 Input/ output 8-bit input/output pins. PC7 to PC0 13 to 11, 9 to 5 E1, F2, E3, D1, D3, D2, C3, C1 11 to 9, 7 to 3 Input/ output 8-bit input/output pins. P80* 104, 103 Input 8-bit input/output pins in the H8S/2426 Group and H8S/2426R Group. 2-bit input/output pins in the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 39 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. H8S/2426, H8S/2426R H8S/2424 Type Symbol FP-144LV TLP-145V FP-120BV I/O Function I/O ports PD7 to PD0 80 to 73 K11, K12, L13, L11, M12, L12, N13, M13 68 to 61 Input/ output 8-bit input/output pins. PE7 to PE0 71, 69 to 63 N11, M10, N10, K10, L10, M9, N9, K9 59, 57 to 51 Input/ output 8-bit input/output pins. PF7 to PF0 94, 90 to 84 F10, G10, G12, H11, J13, H10, H12, J11 79, 75 to 69 Input/ output 8-bit input/output pins. PG6 to PG0 132 to 130, D5, C7, B6, 110 to 107 A13, A12, B13, C12 108 to 106, 92 to 89 Input/ output 7-bit input/output pins. PH3 to 3 PH0* 38 to 35 M2, N2, M1, L1 Input/ output 4-bit input/output pins. 3 4 62 Input 3-bit input pins. 3 101 E12 3 100 D11 PJ2* * PJ1* PJ0* Notes: 1. 2. 3. 4. Not supported by the H8S/2426 Group or H8S/2424R Group. Can be used only in the 145-pin version. Not supported by the H8S/2424 Group. Can be used only in the 144-pin version. Rev. 1.00 Sep. 19, 2008 Page 40 of 1270 REJ09B0466-0100 Section 2 CPU Section 2 CPU The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. 2.1 Features • Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H CPUs object programs • General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers • Sixty-nine basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions Multiply-and-accumulate instruction • Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] • 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes • High-speed operation All frequently-used instructions execute in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 × 8-bit register-register multiply: 2 states Rev. 1.00 Sep. 19, 2008 Page 41 of 1270 REJ09B0466-0100 Section 2 CPU 16 ÷ 8-bit register-register divide: 12 states 16 × 16-bit register-register multiply: 4 states 32 ÷ 16-bit register-register divide: 20 states • Two CPU operating modes Normal mode* Advanced mode Note: * Normal mode is not available in this LSI. • Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. • Register configuration The MAC register is supported only by the H8S/2600 CPU. • Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. • The number of execution states of the MULXU and MULXS instructions Rev. 1.00 Sep. 19, 2008 Page 42 of 1270 REJ09B0466-0100 Section 2 CPU Execution States Instruction Mnemonic H8S/2600 H8S/2000 MULXU MULXU.B Rs, Rd 2* 12 MULXU.W Rs, ERd 2* 20 MULXS.B Rs, Rd 3* 13 MULXS.W Rs, ERd 3* 21 CLRMAC CLRMAC 1* Not supported LDMAC LDMAC ERs, MACH 1* LDMAC ERs, MACL 1* STMAC STMAC MACH, ERd 1* STMAC MACL, ERd 1* MULXS Note: 2.1.2 * The number of execution states is incremented following a MAC instruction. In addition, there are differences in address space, CCR and EXR register functions, power-down modes, etc., depending on the model. Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements. • More general registers and control registers Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added. • Expanded address space Normal mode supports the same 64-Kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. • Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. • Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. A multiply-and-accumulate instruction has been added. Two-bit shift and rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. Rev. 1.00 Sep. 19, 2008 Page 43 of 1270 REJ09B0466-0100 Section 2 CPU • Higher speed Basic instructions execute twice as fast. Note: Normal mode is not available in this LSI. 2.1.3 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements. • Additional control register One 8-bit and two 32-bit control registers have been added. • Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. A multiply-and-accumulate instruction has been added. Two-bit shift and rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. • Higher speed Basic instructions execute twice as fast. Rev. 1.00 Sep. 19, 2008 Page 44 of 1270 REJ09B0466-0100 Section 2 CPU 2.2 CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-Kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. • Address Space The H8S/2600 CPU provides linear access to a maximum 64-Kbyte address space. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@–Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. • Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. • Exception Vector Table and Memory Indirect Branch Addresses In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The exception vector table in normal mode is shown in figure 2.1. For details of the exception vector table, see section 4, Exception Handling. The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. • Stack Structure When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling. Note: Normal mode is not available in this LSI. Rev. 1.00 Sep. 19, 2008 Page 45 of 1270 REJ09B0466-0100 Section 2 CPU H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) EXR*1 SP Reserved*1 *3 (SP*2 ) CCR CCR*3 PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used, it is not stored on the stack. 2. SP when EXR is not used. 3. lgnored when returning. Figure 2.2 Stack Structure in Normal Mode Rev. 1.00 Sep. 19, 2008 Page 46 of 1270 REJ09B0466-0100 Section 2 CPU 2.2.2 Advanced Mode • Address Space Linear access is provided to a 16-Mbyte maximum address space. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. • Instruction Set All instructions and addressing modes can be used. • Exception Vector Table and Memory Indirect Branch Addresses In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Reset exception vector H'00000003 H'00000004 Reserved (Reserved for system use) H'00000007 H'00000008 Exception vector table H'0000000B (Reserved for system use) H'0000000C H'00000010 Reserved Exception vector 1 Figure 2.3 Exception Vector Table (Advanced Mode) Rev. 1.00 Sep. 19, 2008 Page 47 of 1270 REJ09B0466-0100 Section 2 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also used for the exception vector table. • Stack Structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling. EXR*1 SP SP Reserved*1 *3 Reserved PC (24 bits) (SP*2 ) (a) Subroutine Branch CCR PC (24 bits) (b) Exception Handling Notes: 1. When EXR is not used, it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. Figure 2.4 Stack Structure in Advanced Mode Rev. 1.00 Sep. 19, 2008 Page 48 of 1270 REJ09B0466-0100 Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-Kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. H'0000 H'00000000 64 Kbytes 16 Mbytes H'FFFF Program area H'00FFFFFF Data area Cannnot be used in this LSI H'FFFFFFFF (a) Normal Mode* (b) Advanced Mode Note: * Normal mode cannot be used in this LSI. Figure 2.5 Memory Map Note: Normal mode is not available in this LSI. Rev. 1.00 Sep. 19, 2008 Page 49 of 1270 REJ09B0466-0100 Section 2 CPU 2.4 Registers The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8bit extended register (EXR), an 8-bit condition code register (CCR), and a 64-bit multiplyaccumulate register (MAC). General Registers (Rn) and Extended Registers (En) 15 0 7 0 7 0 ER0 E0 R0H R0L ER1 E1 R1H R1L ER2 E2 R2H R2L ER3 E3 R3H R3L ER4 E4 R4H R4L ER5 E5 R5H R5L ER6 E6 R6H R6L ER7 (SP) E7 R7H R7L Control Registers (CR) 0 23 PC 7 6 5 4 3 2 1 0 - - - - I2 I1 I0 EXR T 7 6 5 4 3 2 1 0 CCR I UI H U N Z V C 63 41 MAC MACL 31 0 [Legend] SP: PC: EXR: T: I2 to I0: CCR: I: UI: Stack pointer Program counter Extended register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit* H: U: N: Z: V: C: MAC: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Multiply-accumulate register Note: * UI cannot be used as an interrupt mask bit in this LSI. Figure 2.6 CPU Registers Rev. 1.00 Sep. 19, 2008 Page 50 of 1270 REJ09B0466-0100 32 MACH Sign extension Section 2 CPU 2.4.1 General Registers The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. The usage of each register can be selected independently. General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the stack. • Address registers • 32-bit registers • 16-bit registers • 8-bit registers E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) RH registers (R0H to R7H) R registers (R0 to R7) RL registers (R0L to R7L) Figure 2.7 Usage of General Registers Rev. 1.00 Sep. 19, 2008 Page 51 of 1270 REJ09B0466-0100 Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) 2.4.3 Extended Register (EXR) EXR is an 8-bit register that can be manipulated by the LDC, STC, ANDC, ORC, and XORC instructions. When these instructions except for the STC instruction is executed, all interrupts including NMI will be masked for three states after execution is completed. Bit Bit Name Initial Value R/W 7 T 0 R/W Description Trace Bit When this bit is set to 1, a trace exception is started each time an instruction is executed. When this bit is cleared to 0, instructions are executed in sequence. 6 to 3 — All 1 — Reserved These bits are always read as 1. 2 I2 1 R/W 1 I1 1 R/W 0 I0 1 R/W Rev. 1.00 Sep. 19, 2008 Page 52 of 1270 REJ09B0466-0100 These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. Bit Bit Name Initial Value R/W Description 7 I 1 R/W Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 by hardware at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller. 6 UI Undefined R/W User Bit or Interrupt Mask Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit cannot be used as an interrupt mask bit in this LSI. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 U Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit of data as a sign bit. Rev. 1.00 Sep. 19, 2008 Page 53 of 1270 REJ09B0466-0100 Section 2 CPU Bit Bit Name Initial Value R/W Description 2 Z Undefined R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 V Undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: • Add instructions, to indicate a carry • Subtract instructions, to indicate a borrow • Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions. 2.4.5 Multiply-Accumulate Register (MAC) This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are a sign extension. 2.4.6 Initial Values of CPU Internal Registers When the reset exception handling loads the start address from the vector address, PC is initialized, the T bit in EXR is cleared to 0, and the I bits in EXR and CCR are set to 1. However, the general registers and the other CCR bits are not initialized. The initial value of SP (ER7) is undefined. SP should therefore be initialized by using the MOV.L instruction immediately after a reset. Rev. 1.00 Sep. 19, 2008 Page 54 of 1270 REJ09B0466-0100 Section 2 CPU 2.5 Data Formats The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.9 shows the data formats in general registers. Data Type Register Number Data Format 7 RnH 1-bit data 0 Don't care 7 6 5 4 3 2 1 0 0 7 1-bit data RnL 4-bit BCD data RnH 4-bit BCD data RnL Byte data RnH Don't care 7 7 6 5 4 3 2 1 0 4 3 Upper 0 Lower Don't care 7 Don't care 7 4 3 Upper 0 Don't care MSB LSB 7 Byte data RnL 0 Lower 0 Don't care MSB LSB Figure 2.9 General Register Data Formats (1) Rev. 1.00 Sep. 19, 2008 Page 55 of 1270 REJ09B0466-0100 Section 2 CPU Data Type Register Number Word data Rn Data Format 15 0 MSB Word data 15 0 MSB Longword data LSB En LSB ERn 31 16 15 MSB En 0 Rn Legend: ERn En Rn RnH RnL MSB LSB : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2.9 General Register Data Formats (2) Rev. 1.00 Sep. 19, 2008 Page 56 of 1270 REJ09B0466-0100 LSB Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. When SP (ER7) is used as an address register to access the stack, the operand size should be word size or longword size. Data Type Address Data Format 7 1-bit data Address L 7 Byte data Address L MSB Word data Address 2M MSB 0 6 5 4 3 2 Address 2N 0 LSB LSB Address 2M+1 Longword data 1 MSB Address 2N+1 Address 2N+2 LSB Address 2N+3 Figure 2.10 Memory Data Formats Rev. 1.00 Sep. 19, 2008 Page 57 of 1270 REJ09B0466-0100 Section 2 CPU 2.6 Instruction Set The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV 1 POP* , PUSH* 1 MOVFPE* , MOVTPE* Arithmetic operations Types B/W/L 5 W/L LDM, STM 3 Size L 3 B ADD, SUB, CMP, NEG B/W/L ADDX, SUBX, DAA, DAS B INC, DEC B/W/L ADDS, SUBS L MULXU, DIVXU, MULXS, DIVXS B/W EXTU, EXTS W/L 4 23 TAS* B MAC, LDMAC, STMAC, CLRMAC — Logic operations AND, OR, XOR, NOT B/W/L 4 Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L 8 Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR B 14 Branch Bcc*2, JMP, BSR, JSR, RTS — 5 System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP — 9 — 1 Total: 69 Block data transfer EEPMOV Legend: B: Byte W: Word L: Longword Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the general name for conditional branch instructions. Rev. 1.00 Sep. 19, 2008 Page 58 of 1270 REJ09B0466-0100 Section 2 CPU 3. Cannot be used in this LSI. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Symbol Operation Notation Description Rd General register (destination)* Rs General register (source)* Rn General register* ERn General register (32-bit register) MAC Multiply-accumulate register (32-bit register) (EAd) Destination operand (EAs) Source operand EXR Extended register CCR Condition-code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition – Subtraction × Multiplication ÷ Division ∧ Logical AND ∨ Logical OR ⊕ Logical exclusive OR Rev. 1.00 Sep. 19, 2008 Page 59 of 1270 REJ09B0466-0100 Section 2 CPU Symbol Description → Move ∼ NOT (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Table 2.3 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in this LSI. MOVTPE B Cannot be used in this LSI. POP W/L @SP+ → Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. PUSH W/L Rn → @–SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP. LDM L @SP+ → Rn (register list) Pops two or more general registers from the stack. STM L Rn (register list) → @–SP Pushes two or more general registers onto the stack. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Sep. 19, 2008 Page 60 of 1270 REJ09B0466-0100 Section 2 CPU Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function ADD B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. B Rd (decimal adjust) → Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. MULXU B/W Rd × Rs → Rd Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. MULXS B/W Rd × Rs → Rd Performs signed multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. DIVXU B/W Rd ÷ Rs → Rd Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. SUB ADDX SUBX INC DEC ADDS SUBS DAA DAS Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Sep. 19, 2008 Page 61 of 1270 REJ09B0466-0100 Section 2 CPU Table 2.4 Arithmetic Operations Instructions (2) Instruction Size*1 Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. NEG B/W/L 0 – Rd → Rd Takes the two's complement (arithmetic complement) of data in a general register. EXTU W/L Rd (zero extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. EXTS W/L Rd (sign extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. TAS*2 B @ERd – 0, 1 → (<bit 7> of @ERd) Tests memory contents, and sets the most significant bit (bit 7) to 1. MAC — (EAs) × (EAd) + MAC → MAC Performs signed multiplication on memory contents and adds the result to the multiply-accumulate register. The following operations can be performed: 16 bits × 16 bits + 32 bits → 32 bits, saturating 16 bits × 16 bits + 42 bits → 42 bits, non-saturating CLRMAC — 0 → MAC Clears the multiply-accumulate register to zero. LDMAC L Rs → MAC, MAC → Rd Transfers data between a general register and a multiply-accumulate register. STMAC Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev. 1.00 Sep. 19, 2008 Page 62 of 1270 REJ09B0466-0100 Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B/W/L ∼ (Rd) → (Rd) Takes the one's complement (logical complement) of general register contents. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Table 2.6 Shift Instructions Instruction Size* Function SHAL B/W/L Rd (shift) → Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. B/W/L Rd (shift) → Rd Performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. B/W/L Rd (rotate) → Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. B/W/L Rd (rotate) → Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Sep. 19, 2008 Page 63 of 1270 REJ09B0466-0100 Section 2 CPU Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 → (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → (<bit-No.> of <EAd>) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ~ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BTST B ~ (<bit-No.> of <EAd>) → Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BAND B C ∧ (<bit-No.> of <EAd>) → C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIAND B C ∧ [~ (<bit-No.> of <EAd>)] → C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BOR B C ∨ (<bit-No.> of <EAd>) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIOR B C ∨ [~ (<bit-No.> of <EAd>)] → C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. Note: * Size refers to the operand size. B: Byte Rev. 1.00 Sep. 19, 2008 Page 64 of 1270 REJ09B0466-0100 Section 2 CPU Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C ⊕ (<bit-No.> of <EAd>) → C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ [~ (<bit-No.> of <EAd>)] → C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (<bit-No.> of <EAd>) → C Transfers a specified bit in a general register or memory operand to the carry flag. BILD B ~ (<bit-No.> of <EAd>) → C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. BST B C → (<bit-No.> of <EAd>) Transfers the carry flag value to a specified bit in a general register or memory operand. BIST B ~ C → (<bit-No.> of <EAd>) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. Note: * Size refers to the operand size. B: Byte Rev. 1.00 Sep. 19, 2008 Page 65 of 1270 REJ09B0466-0100 Section 2 CPU Table 2.8 Branch Instructions Instruction Size Function Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never BHI High C∨Z=0 BLS Low or same C∨Z=1 BCC (BHS) Carry clear (high or same) C=0 BCS (BLO) Carry set (low) C=1 BNE Not equal Z=0 BEQ Equal Z=1 BVC Overflow clear V=0 BVS Overflow set V=1 BPL Plus N=0 BMI Minus N=1 BGE Greater or equal N⊕V=0 BLT Less than N⊕V=1 BGT Greater than Z ∨ (N ⊕ V) = 0 BLE Less or equal Z ∨ (N ⊕ V) = 1 JMP — Branches unconditionally to a specified address. BSR — Branches to a subroutine at a specified address. JSR — Branches to a subroutine at a specified address. RTS — Returns from a subroutine. Rev. 1.00 Sep. 19, 2008 Page 66 of 1270 REJ09B0466-0100 Section 2 CPU Table 2.9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves the contents of a general register or memory, or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. STC B/W CCR → (EAd), EXR → (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR Logically ANDs the CCR or EXR contents with immediate data. ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR Logically ORs the CCR or EXR contents with immediate data. XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. NOP — PC + 2 → PC Only increments the program counter. Note: * Size refers to the operand size. B: Byte W: Word Rev. 1.00 Sep. 19, 2008 Page 67 of 1270 REJ09B0466-0100 Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W — if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. 2.6.2 Basic Instruction Formats The H8S/2600 Series instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.11 shows examples of instruction formats. • Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. • Register Field Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. • Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. • Condition Field Specifies the branching condition of Bcc instructions. Rev. 1.00 Sep. 19, 2008 Page 68 of 1270 REJ09B0466-0100 Section 2 CPU (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm, etc. EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc. Figure 2.11 Instruction Formats (Examples) 2.7 Addressing Modes and Effective Address Calculation The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. The usable address modes are different in each instruction. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Rev. 1.00 Sep. 19, 2008 Page 69 of 1270 REJ09B0466-0100 Section 2 CPU Table 2.11 Addressing Modes No. Addressing Mode Symbol 1 Register direct Rn 2 Register indirect @ERn 3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn) 4 Register indirect with post-increment Register indirect with pre-decrement @ERn+ @–ERn 5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 Immediate #xx:8/#xx:16/#xx:32 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 8 Memory indirect @@aa:8 2.7.1 Register Direct—Rn The register field of the instruction code specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect—@ERn The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). 2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction code, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. Rev. 1.00 Sep. 19, 2008 Page 70 of 1270 REJ09B0466-0100 Section 2 CPU 2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn Register indirect with post-increment—@ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. Register indirect with pre-decrement—@-ERn: The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. 2.7.5 Absolute Address—@aa:8 /@aa:16 / @aa:24 /@aa:32 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). Table 2.12 indicates the accessible absolute address ranges. To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address, the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.12 Absolute Address Access Ranges Absolute Address Data address Normal Mode* Advanced Mode 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) Program instruction address Note: * H'000000 to H'FFFFFF 24 bits (@aa:24) Not available in this LSI. Rev. 1.00 Sep. 19, 2008 Page 71 of 1270 REJ09B0466-0100 Section 2 CPU 2.7.6 Immediate—#xx:8 / #xx:16/ #xx:32 The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is −126 to +128 bytes (–63 to +64 words) or −32766 to +32768 bytes (−16383 to +16384 words) from the branch instruction. The resulting value should be an even number. 2.7.8 Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) Note: Normal mode is not available in this LSI. Rev. 1.00 Sep. 19, 2008 Page 72 of 1270 REJ09B0466-0100 Section 2 CPU Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode* (a) Advanced Mode Note: * Normal mode is not available in this LSI. Figure 2.12 Branch Address Specification in Memory Indirect Mode Rev. 1.00 Sep. 19, 2008 Page 73 of 1270 REJ09B0466-0100 Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: Normal mode is not available in this LSI. Table 2.13 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct (Rn) rm Operand is general register contents. rn Register indirect (@ERn) 0 31 op 3 31 24 23 0 Don't care General register contents r Register indirect with displacement @(d:16,ERn) or @(d:32,ERn) 0 31 General register contents op r 31 disp Sign extension Register indirect with post-increment or pre-decrement • Register indirect with post-increment @ERn+ op disp 31 0 31 24 23 1, 2, or 4 31 0 General register contents 31 24 23 Don't care op r 1, 2, or 4 Operand Size Byte Word Longword Rev. 1.00 Sep. 19, 2008 Page 74 of 1270 REJ09B0466-0100 0 Don't care General register contents r • Register indirect with pre-decrement @-ERn 0 0 31 4 24 23 Don't care Offset 1 2 4 0 Section 2 CPU Table 2.13 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 31 op @aa:16 31 op 0 H'FFFF 24 23 16 15 0 Don't care Sign extension abs @aa:24 31 op 8 7 24 23 Don't care abs 24 23 0 Don't care abs @aa:32 op 31 6 Immediate #xx:8/#xx:16/#xx:32 op 7 0 24 23 Don't care abs Operand is immediate data. IMM 0 23 Program-counter relative PC contents @(d:8,PC)/@(d:16,PC) op disp 23 0 Sign extension disp 31 24 23 0 Don't care 8 Memory indirect @@aa:8 • Normal mode* 8 7 31 op abs 0 abs H'000000 15 0 31 24 23 Don't care Memory contents 16 15 0 H'00 • Advanced mode 31 op abs 8 7 H'000000 31 0 abs 0 31 24 23 Don't care 0 Memory contents Note: * Normal mode is not available in this LSI. Rev. 1.00 Sep. 19, 2008 Page 75 of 1270 REJ09B0466-0100 Section 2 CPU 2.8 Processing States The H8S/2600 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. • Reset State The CPU and on-chip peripheral modules are all initialized and stop. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. For details, refer to section 4, Exception Handling. The reset state can also be entered by a watchdog timer overflow. • Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. For further details, refer to section 4, Exception Handling. • Program Execution State In this state the CPU executes program instructions in sequence. • Bus-Released State In a product which has a bus master other than the CPU, such as a direct memory access controller (DMAC) and a data transfer controller (DTC), the bus-released state occurs when the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. • Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters hardware standby mode. For further details, refer to section 24, Power-Down Modes. Rev. 1.00 Sep. 19, 2008 Page 76 of 1270 REJ09B0466-0100 Section 2 CPU End of bus request Bus request En d En d of Re ex qu ce es pt tf ion or ha ex nd ce lin pt g ion ha nd lin g n Exception handling state Sleep mode t ues q t re rrup Inte =0 BY SS EEP tion SL truc ins Bus-released state io = 1 ruct BY nst SS EP i E SL of bu s re Bu qu sr es eq t ue st Program execution state External interrupt request Software standby mode RES = High Reset state*1 STBY = High, RES = Low Hardware standby mode*2 Reset state Power down state*3 Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever the RES pin goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. In every state, when the STBY pin becomes low, the hardware standby mode is entered. 3. For details, refer to section 24, Power-Down Modes. Figure 2.13 State Transitions Rev. 1.00 Sep. 19, 2008 Page 77 of 1270 REJ09B0466-0100 Section 2 CPU 2.9 Usage Note 2.9.1 Usage Notes on Bit-wise Operation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions are used to read data in byte-wise, operate the data in bit-wise, and write the result of the bit-wise operation in bit-wise again. Therefore, special care is necessary to use these instructions for the registers and the ports that include writeonly bit. The BCLR instruction can be used to clear the flags in the internal I/O registers to 0. In this time, if it is obvious that the flag has been set to 1 in the interrupt handler, there is no need to read the flag beforehand. Rev. 1.00 Sep. 19, 2008 Page 78 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Operating Mode Selection The H8S/2426 Group, H8S/2426R Group, and H8S/2424 Group have five operating modes (modes 1 to 4 and 7). The operating mode is selected by the setting of mode pins (MD2 to MD0). Modes 1, 2, and 4 are externally expanded modes in which the CPU can access an external memory and peripheral devices. In an externally expanded mode, the external address space can be designated as an 8-bit or 16-bit address space for each area by the bus controller at the beginning of program execution. If a 16-bit address space is designated for any one area, the 16bit bus mode is selected. If an 8-bit address space is designated for all areas, the 8-bit bus mode is selected. Mode 7 is a single-chip activation expanded mode in which the CPU can switch to access an external memory and peripheral devices at the beginning of program execution. Mode 3 is a boot mode in which the flash memory can be programmed or erased. For details on the boot mode, refer to section 21, Flash Memory. The settings for pins MD2 to MD0 should not be changed during LSI operation. Table 3.1 MCU Operating Modes MCU Operating Mode MD2 MD1 MD0 CPU Operating Mode 1* 0 0 1 Advanced 2* 0 1 0 Advanced External Data Bus On-Chip ROM Initial Value Max. Value Expanded mode with on-chip ROM disabled Disabled 16 bits 16 bits Expanded mode with on-chip ROM disabled Disabled 8 bits 16 bits Description 3 0 1 1 Advanced Boot mode Enabled 16 bits 4 1 0 0 Advanced Expanded mode with on-chip ROM enabled Enabled 8 bits 16 bits 7 1 1 1 Advanced Single-chip mode Enabled 16 bits Note: * Only modes 1 and 2 may be used in ROM-less versions. Rev. 1.00 Sep. 19, 2008 Page 79 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to operating mode setting. • • Mode control register (MDCR) System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR monitors the current operating mode of this LSI. Bit Bit Name Initial Value R/W Descriptions 7 to 3 All 0 Reserved These bits are always read as 0 and cannot be modified. 2 MDS2 * R Mode Select 2 to 0 1 MDS1 * R 0 MDS0 * R These bits indicate the input levels at mode pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to MD0, respectively. These bits are read-only bits and so they cannot be modified. The input levels of the MD2 to MD0 pins are latched into these bits when MDCR is read. These latches are canceled by a reset. Note: 3.2.2 * Determined by the settings of pins MD2 to MD0. System Control Register (SYSCR) SYSCR selects saturation operation for the MAC instruction, controls CPU access to the flash memory control registers, sets the external bus mode, and enables or disables on-chip RAM. Rev. 1.00 Sep. 19, 2008 Page 80 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes Bit Bit Name Initial Value R/W Descriptions 7, 6 All 1 R/W Reserved 5 MACS 0 R/W MAC Saturation Operation Control The initial value should not be modified. Selects either saturation operation or non-saturation operation for the MAC instruction. 0: MAC instruction performs non-saturation operation 1: MAC instruction performs saturation operation 4 0 R/W Reserved 3 FLSHE 0 R/W Flash Memory Control Register Enable The initial value should not be modified. Controls CPU access to the flash memory control registers (FLMCR1, DFPR, and FLMSTR). If this bit is set to 1, the flash memory control registers can be read from and written to. If this bit is cleared to 0, the flash memory control registers are not selected. At this time, the contents of the flash memory control registers are retained. 0 should be written to this bit in LSIs other than the flash memory version. 0: Flash memory control registers are not selected for addresses H'FFFEB0 to H'FFFEB3 1: Flash memory control registers are selected for addresses H'FFFEB0 to H'FFFEB3 2 0 Reserved 1 EXPE R/W External Bus Mode Enable This bit is always read as 0 and cannot be modified. Sets the external bus mode. In modes 1, 2, and 4, this bit is fixed at 1 and cannot be modified. In modes 3 and 7, this bit can be read from and written to. Writing 0 to this bit when its value is 1 should only be carried out when an external bus cycle is not being executed. 0: External address space is disabled 1: External address space is enabled 0 RAME 1 R/W RAM Enable Enables or disables the on-chip RAM. This bit is initialized when the reset state is canceled. 0: On-chip RAM is disabled 1: On-chip RAM is enabled Rev. 1.00 Sep. 19, 2008 Page 81 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F to H function as bus control signals. The initial bus mode immediately after a reset is 16 bits, with 16-bit access to all areas. However, if 8-bit access is designated for all areas by the bus controller, the bus mode switches to 8 bits. 3.3.2 Mode 2 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F to H function as bus control signals. The initial bus mode immediately after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access is designated for any one of the areas by the bus controller, the bus mode switches to 16 bits and port E functions as a data bus. 3.3.3 Mode 3 This mode is a boot mode of the flash memory. This mode is the same as mode 7, except for the programming and erasure of the flash memory. Mode 3 is only available in the flash memory version. Rev. 1.00 Sep. 19, 2008 Page 82 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes 3.3.4 Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. The program in the on-chip ROM connected to the first half of area 0 is executed. Ports A to C function as input ports immediately after a reset, but can be set to function as an address bus depending on each port register setting. Port D functions as a data bus and parts of ports F to H function as bus control signals. For details on function switching of ports A to C, see section 10, I/O Ports. The initial bus mode immediately after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access is designated for any one of the areas by the bus controller, the bus mode switches to 16 bits and port E functions as a data bus. In the flash memory version, user program mode is entered by setting the SWE bit in FMCMDEN to 1. 3.3.5 Mode 7 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, and the LSI starts up in single-chip mode. External address spaces cannot be used in single-chip mode. The initial mode immediately after a reset is single-chip mode, with all I/O ports available for use as input/output ports. However, setting the EXPE bit in SYSCR to 1 switches the mode to an externally expanded mode in which the external address spaces are enabled. When an externally expanded mode is selected, all areas are initially designated as a 16-bit access space. The functions of pins in ports A to H are the same as those in an externally expanded mode with on-chip ROM enabled. In the flash memory version, user program mode is entered by setting the SWE bit in FMCMDEN to 1. Rev. 1.00 Sep. 19, 2008 Page 83 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes 3.3.6 Pin Functions Table 3.2 shows the pin functions in each operating mode. Table 3.2 Pin Functions in Each Operating Mode Port Port A Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 PA7 to PA5 P*/A P*/A P*/A P*/A P*/A PA4 to PA0 A A Port B A A P*/A P*/A P*/A Port C A A P*/A P*/A P*/A Port D D D P*/D D P*/D Port E Port F Port G P/D* P*/D P*/D P*/D P*/D PF7, PF6 P/C* P/C* P*/C P/C* P*/C PF5, PF4 C C C PF3 P/C* P/C* P/C* PF2 to PF0 P*/C P*/C PG6 to PG1 P*/C P*/C PG0 P/C* P/C* P*/C P*/C Port H P*/C P*/C P*/C P*/C P*/C P*/C P*/C [Legend] P: I/O port A: Address bus output D: Data bus input/output C: Control signals, clock input/output *: Immediately after a reset Note: Port H is not supported in the H8S/2424 Group. 3.4 Memory Map in Each Operating Mode Figures 3.1 to 3.5 show memory maps in each operating mode. Rev. 1.00 Sep. 19, 2008 Page 84 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes RAM: 64 Kbytes*6/48 Kbytes ROM: 256 Kbytes RAM: 64 Kbytes*6/48 Kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) Mode 3 (Boot mode) H'000000 H'000000 On-chip ROM H'040000 Reserved area*4 H'080000 External address space External address space/ Reserved area*2*4 H'F00000 Data flash area 8 Kbytes*7 H'F02000 External address space/ Reserved area*2*4 H'FE8000 H'FEC000 H'FF0000 H'FFC000 H'FFC800 H'FE8000 Reserved area*4 Reserved area*4 On-chip RAM/External address space/ Reserved area*1*5 On-chip RAM/External address space*1 Reserved area*4 External address space H'FEC000 H'FF0000 On-chip RAM*3 H'FFC000 H'FFC800 H'FFFA00 H'FFFA00 H'FFFF00 External address space H'FFFF20 H'FFFFFF Internal I/O registers Reserved area*4 External address space/ Reserved area*2*4 Internal I/O registers Internal I/O registers H'FFFF00 On-chip RAM/Reserved area*3*5 H'FFFF20 H'FFFFFF External address space/ Reserved area*2*4 Internal I/O registers Notes: 1. 2. 3. 4. 5. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. On-chip RAM is used for flash memory programming. The RAME bit in SYSCR should not be cleared to 0. A reserved area should not be accessed. Area from H'FEC000 to H'FEFFFF in the H8S/24268, H8S/24268R, and H8S/24248 Groups is reserved and should not be accessed. 6. 64-Kbyte version (H8S/24269, H8S/24269R, and H8S/24249) is under development. 7. Data flash is in planning. Figure 3.1 Memory Map in Each Operating Mode (ROM: 256-Kbyte Version): H8S/24269, H8S/24269R, H8S/24268, H8S/24268R, H8S/24249, and H8S/24248 Rev. 1.00 Sep. 19, 2008 Page 85 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes ROM: 256 Kbytes RAM: 64 Kbytes*6 / 48 Kbytes Mode 4 (Expanded mode with on-chip ROM enabled) ROM: 256 Kbytes RAM: 64 Kbytes*6 / 48 Kbytes Mode 7 (Single-chip activation expanded mode with on-chip ROM enabled) H'000000 H'000000 On-chip ROM On-chip ROM H'040000 H'040000 Reserved area*4 Reserved area*4 H'080000 H'080000 External address space/ Reserved area*2*4 External address space H'F00000 H'F00000 Reserved area*4 Data flash area 8 Kbytes*7 H'F02000 H'F02000 External address space/ Reserved area*2*4 External address space H'FE8000 H'FE8000 Reserved area*4 H'FEC000 H'FF0000 H'FFC000 H'FFC800 On-chip RAM/External address space/ Reserved area*1*5 On-chip RAM/ External address space*1 Reserved area*4 Reserved area*4 H'FEC000 H'FF0000 H'FFC000 H'FFC800 External address space H'FFFA00 H'FFFF00 H'FFFA00 H'FFFF00 External address space H'FFFFFF H'FFFF20 Internal I/O registers On-chip RAM/ External address space*3 Reserved area*4 External address space/ Reserved area*2*4 Internal I/O registers Internal I/O registers H'FFFF20 On-chip RAM/External address space/ Reserved area*3*5 H'FFFFFF External address space/ Reserved area*2*4 Internal I/O registers Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. 2. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. 3. While EXPE = 1, this area is specified as the external address space when RAME = 0 and the on-chip RAM area when RAME = 1. While EXPE = 0, this area is specified as the on-chip RAM area. 4. A reserved area should not be accessed. 5. Area from H'FEC000 to H'FEFFFF in the H8S/24268, H8S/24268R, and H8S/24248 Groups is reserved and should not be accessed. 6. 64-Kbyte version (H8S/24269, H8S/24269R, and H8S/24249) is under development. 7. Data flash is in planning. Figure 3.2 Memory Map in Each Operating Mode (ROM: 256-Kbyte Version): H8S/24269, H8S/24269R, H8S/24249, and H8S/24248 Rev. 1.00 Sep. 19, 2008 Page 86 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes RAM: 48 Kbytes ROM: 128 Kbytes RAM: 48 Kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) Mode 3 (Boot mode) H'000000 H'000000 On-chip ROM H'020000 Reserved area*4 H'080000 External address space External address space/ Reserved area*2*4 H'F00000 Data flash area 8 Kbytes*5 H'F02000 External address space/ Reserved area*2*4 H'FE8000 H'FE8000 Reserved area*4 Reserved area*4 H'FF0000 H'FF0000 On-chip RAM/ External address space*1 H'FFC000 H'FFC800 Reserved area*4 External address space On-chip RAM*3 H'FFC000 H'FFC800 H'FFFA00 H'FFFA00 Internal I/O registers Internal I/O registers H'FFFF00 H'FFFF00 External address space H'FFFF20 H'FFFFFF Notes: 1. 2. 3. 4. 5. Internal I/O registers Reserved area*4 External address space/ Reserved area*2*4 H'FFFF20 H'FFFFFF External address space/ Reserved area*2*4 Internal I/O registers This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. On-chip RAM is used for flash memory programming. The RAME bit in SYSCR should not be cleared to 0. A reserved area should not be accessed. Data flash is in planning. Figure 3.3 Memory Map in Each Operating Mode (ROM: 128-Kbyte Version): H8S/24265, H8S/24265R, and H8S/24245 Rev. 1.00 Sep. 19, 2008 Page 87 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes ROM: 128 Kbytes RAM: 48 Kbytes Mode 7 (Single-chip activation expanded mode with on-chip ROM enabled) ROM: 128 Kbytes RAM: 48 Kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 H'000000 On-chip ROM On-chip ROM H'020000 H'020000 Reserved area*4 Reserved area*4 H'080000 H'080000 External address space/ Reserved area*2*4 External address space H'F00000 H'F00000 Reserved area*4 Data flash area 8 Kbytes*5 H'F02000 H'F02000 External address space/ Reserved area*2*4 External address space H'FE8000 H'FE8000 Reserved area*4 H'FF0000 Reserved area*4 H'FF0000 On-chip RAM/ External address space*1 H'FFC000 H'FFC800 Reserved area*4 On-chip RAM/ External address space*3 H'FFC000 H'FFC800 External address space H'FFFA00 H'FFFF00 H'FFFA00 Internal I/O registers H'FFFF00 External address space H'FFFF20 H'FFFFFF H'FFFF20 Internal I/O registers H'FFFFFF Reserved area*4 External address space/ Reserved area*2*4 Internal I/O registers External address space/ Reserved area*2*4 Internal I/O registers Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. 2. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. 3. While EXPE = 1, this area is specified as the external address space when RAME = 0 and the on-chip RAM area when RAME = 1. While EXPE = 0, this area is specified as the on-chip RAM area. 4. A reserved area should not be accessed. 5. Data flash is in planning. Figure 3.4 Memory Map in Each Operating Mode (ROM: 128-Kbyte Version): H8S/24265, H8S/24265R, and H8S/24245 Rev. 1.00 Sep. 19, 2008 Page 88 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes RAM: 64 Kbytes*4 /48 Kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 External address space H'FE8000 H'FEC000 H'FF0000 H'FFC000 H'FFC800 Reserved area*2 On-chip RAM/External address space/ Reserved area*1*3 On-chip RAM/External address space*1*3 Reserved area*2 External address space H'FFFA00 Internal I/O registers H'FFFF00 External address space H'FFFF20 H'FFFFFF Internal I/O registers Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. 2. A reserved area should not be accessed. 3. Area from H'FEC000 to H'FEFFFF in the H8S/24261, H8S/24261R, and H8S/24241 Groups is reserved and should not be accessed. 4. 64-Kbyte version (H8S/24262, H8S/24262R, and H8S/24242) is in planning. Figure 3.5 Memory Map in Each Operating Mode (ROM-Less Version): H8S/24262, H8S/24262R, H8S/24261, H8S/24261R, H8S/24242, and H8S/24241 Rev. 1.00 Sep. 19, 2008 Page 89 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes Rev. 1.00 Sep. 19, 2008 Page 90 of 1270 REJ09B0466-0100 Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, illegal instruction, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode. For details on the interrupt control mode, refer to section 5, Interrupt Controller. Table 4.1 Exception Types and Priority Priority Exception Type Start of Exception Handling High Reset Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. The CPU enters the reset state when the RES pin is low. Illegal instruction Starts when execution of an illegal instruction code is detected. Trace*1 Starts when execution of the currently executed instruction or exception handling ends, if the trace (T) bit in the EXR is set to 1. Direct transition*2 Starts when the direct transition occurs by execution of the SLEEP instruction. Interrupt Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued. *3 Trap instruction*4 Started by execution of a trap instruction (TRAPA) Low Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Not available in this LSI. 3. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 4. Trap instruction exception handling requests are accepted at all times in program execution state. Rev. 1.00 Sep. 19, 2008 Page 91 of 1270 REJ09B0466-0100 Section 4 Exception Handling 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Since the usable modes differ depending on the product, for details on each product, refer to section 3, MCU Operating Modes. Table 4.2 Exception Handling Vector Table Vector Address*1 Exception Source Vector Number Normal Mode*2 Advanced Mode Power-on reset 0 H'0000 to H'0001 H'0000 to H'0003 1 H'0002 to H'0003 H'0004 to H'0007 2 H'0004 to H'0005 H'0008 to H'000B 3 H'0006 to H'0007 H'000C to H'000F Illegal instruction 4 H'0008 to H'0019 H'0010 to H'0013 Trace 5 H'000A to H'000B H'0014 to H'0017 Interrupt (direct transition)*3 6 H'000C to H'000D H'0018 to H'001B Interrupt (NMI) 7 H'000E to H'000F H'001C to H'001F Trap instruction (#0) 8 H'0010 to H'0011 H'0020 to H'0023 (#1) 9 H'0012 to H'0013 H'0024 to H'0027 (#2) 10 H'0014 to H'0015 H'0028 to H'002B (#3) 11 H'0016 to H'0017 H'002C to H'002F 12 H'0018 to H'0019 H'0030 to H'0033 13 H'001A to H'001B H'0034 to H'0037 14 H'001C to H'001D H'0038 to H'003B 15 H'001E to H'001F H'003C to H'003F IRQ0 16 H'0020 to H'0021 H'0040 to H'0043 IRQ1 17 H'0022 to H'0023 H'0044 to H'0047 IRQ2 18 H'0024 to H'0025 H'0048 to H'004B IRQ3 19 H'0026 to H'0027 H'004C to H'004F IRQ4 20 H'0028 to H'0029 H'0050 to H'0053 IRQ5 21 H'002A to H'002B H'0054 to H'0057 IRQ6 22 H'002C to H'002D H'0058 to H'005B Manual reset* 3 Reserved for system use Reserved for system use External interrupt Rev. 1.00 Sep. 19, 2008 Page 92 of 1270 REJ09B0466-0100 Section 4 Exception Handling Vector Address*1 Exception Source External interrupt IRQ7 External interrupt IRQ8* 5 IRQ9* 5 Internal interrupt* Normal Mode*2 Advanced Mode 23 H'002E to H'002F H'005C to H'005F 24 H'0030 to H'0031 H'0060 to H'0063 25 H'0032 to H'0033 H'0064 to H'0067 IRQ10* 5 26 H'0034 to H'0035 H'0068 to H'006B IRQ11* 5 27 H'0036 to H'0037 H'006C to H'006F IRQ12* 5 28 H'0038 to H'0039 H'0070 to H'0073 IRQ13* 5 29 H'003A to H'003B H'0074 to H'0077 IRQ14*5 30 H'003C to H'003D H'0078 to H'007B 5 31 H'003E to H'003F H'007C to H'007F 32 157 H'0040 to H'0041 H'013A to H'013B H'0080 to H'0083 H'0274 to H'0277 IRQ15* 4 Vector Number Notes: 1. 2. 3. 4. Lower 16 bits of the address. Not available in this LSI. Not available in this LSI. It is reserved for system use. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling Vector Table. 5. Reserved for system use in the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 93 of 1270 REJ09B0466-0100 Section 4 Exception Handling 4.3 Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-up. To reset this LSI during operation, hold the RES pin low for at least 20 states. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. This LSI can also be reset by overflow of the watchdog timer. For details see section 14, Watchdog Timer (WDT). The interrupt control mode is 0 immediately after reset. 4.3.1 Reset Exception Handling When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4.1 and 4.2 show examples of the reset sequence. Rev. 1.00 Sep. 19, 2008 Page 94 of 1270 REJ09B0466-0100 Section 4 Exception Handling Vector fetch Prefetch of first Internal processing program instruction (1) (3) φ RES Internal address bus (5) Internal read signal Internal write signal Internal data bus High (2) (4) (6) (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled) Rev. 1.00 Sep. 19, 2008 Page 95 of 1270 REJ09B0466-0100 Section 4 Exception Handling Internal processing Vector fetch * φ * Prefetch of first program instruction * RES Address bus (1) (3) (5) RD HWR, LWR D15 to D0 High (2) (4) (6) (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Note: * Seven program wait states are inserted. Figure 4.2 Reset Sequence (Advanced Mode with On-chip ROM Disabled) 4.3.2 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 4.3.3 On-Chip Peripheral Functions after Reset Release After reset release, MSTPCR is initialized to H'0FFF, EXMSTPCR is initialized to H'FFFF, and all modules except the DMAC, EXDMAC, and DTC enter module stop mode. Consequently, on-chip peripheral module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited. Rev. 1.00 Sep. 19, 2008 Page 96 of 1270 REJ09B0466-0100 Section 4 Exception Handling 4.4 Trace Exception Handling Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.3 shows the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by clearing the T bit in EXR to 0. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Interrupts are accepted even within the trace exception handling routine. Table 4.3 Status of CCR and EXR after Trace Exception Handling CCR Interrupt Control Mode I 0 2 UI EXR I2 to I0 T Trace exception handling cannot be used. 1 — — 0 [Legend] 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution 4.5 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. The source to start interrupt exception handling and the vector address differ depending on the product. For details, refer to section 5, Interrupt Controller. The interrupt exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended register (EXR) are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. Rev. 1.00 Sep. 19, 2008 Page 97 of 1270 REJ09B0466-0100 Section 4 Exception Handling 4.6 Trap Instruction Exception Handling Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended register (EXR) are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling CCR EXR Interrupt Control Mode I UI I2 to I0 T 0 1 2 1 0 Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution Rev. 1.00 Sep. 19, 2008 Page 98 of 1270 REJ09B0466-0100 Section 4 Exception Handling 4.7 Illegal Instruction Exception Handling Illegal instruction exception handling starts when the CPU executing an illegal instruction code is detected. Illegal instruction exception handling can be executed at all times in the program execution state. The illegal instruction exception handling is as follows: 1. The values in the PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the exception is generated, the start address of the exception service routine is loaded from the vector table to the PC, and program execution starts from that address. Table 4.5 shows the status of CCR and EXR after execution of illegal instruction exception handling. Table 4.5 Status of CCR and EXR after Illegal Instruction Exception Handling CCR EXR Interrupt Control Mode I UI T I2 to I0 0 1 2 1 0 Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution Illegal instruction codes will not be searched for in the fields that do not affect instruction definitions, such as the EA extension or register fields. Instruction codes for an instruction formed with several words are detected independently, and combined instruction codes are not detected. Undefined instruction codes must not be executed. The general register contents after execution of an undefined instruction code or illegal instruction exception handling cannot be guaranteed. The stack pointer during illegal instruction exception handling and the PC value that will be saved are also not guaranteed. Rev. 1.00 Sep. 19, 2008 Page 99 of 1270 REJ09B0466-0100 Section 4 Exception Handling 4.8 Stack Status after Exception Handling Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Normal Modes*2 SP EXR Reserved*1 SP CCR CCR CCR*1 CCR*1 PC (16 bits) PC (16 bits) Interrupt control mode 0 Interrupt control mode 2 Advanced Modes SP EXR Reserved*1 SP CCR PC (24 bits) Interrupt control mode 0 CCR PC (24 bits) Interrupt control mode 2 Notes: 1. Ignored on return. 2. Normal modes are not available in this LSI. Figure 4.3 Stack Status after Exception Handling Rev. 1.00 Sep. 19, 2008 Page 100 of 1270 REJ09B0466-0100 Section 4 Exception Handling 4.9 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn (or MOV.W @SP+, Rn) POP.L ERn (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.4 shows an example of operation when the SP value is odd. Address CCR R1L SP SP H'FFFEFA H'FFFEFB PC PC H'FFFEFC H'FFFEFD H'FFFEFE SP H'FFFEFF TRAP instruction executed SP set to H'FFFEFF MOV.B R1L, @-ER7 Data saved above SP Contents of CCR lost Legend: CCR : PC : R1L : SP : Condition code register Program counter General register R1L Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4.4 Operation when SP Value Is Odd Rev. 1.00 Sep. 19, 2008 Page 101 of 1270 REJ09B0466-0100 Section 4 Exception Handling Rev. 1.00 Sep. 19, 2008 Page 102 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR). • Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times. • Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. • External interrupt pins NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQn-A and IRQn-B. Note: n = 15 to 0 for H8S/2426 Group, n = 7 to 0 for H8S/2424 Group • DTC and DMAC control DTC and DMAC activations are performed by means of interrupts. Rev. 1.00 Sep. 19, 2008 Page 103 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. CPU INTM1 INTM0 INTCR NMIEG NMI input NMI input unit IRQ input IRQ input unit ISR ITSR ISCR Interrupt request Vector number IER Priority determination Internal interrupt sources SWDTEND to SSTXI I I2 to I0 IPR Interrupt controller Legend: ISCR: IRQ sense control register IER: IRQ enable register ISR: IRQ status register IPR: Interrupt priority register INTCR: Interrupt control register ITSR: IRQ pin select register Figure 5.1 Block Diagram of Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 104 of 1270 REJ09B0466-0100 CCR EXR Section 5 Interrupt Controller 5.2 Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Pin Configuration Name I/O Function NMI Input Nonmaskable external interrupt Rising or falling edge can be selected. IRQ15-A to IRQ0-A* IRQ15-B to IRQ0-B* Note: * Input Maskable external interrupts Rising, falling, or both edges, or level sensing, can be selected. IRQ7-A to IRQ0-A and IRQ7-B to IRQ0-B in the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 105 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.3 Register Descriptions The interrupt controller has the following registers. • • • • • • • • • • • • • • • • • • • • • Interrupt control register (INTCR) IRQ sense control register H (ISCRH) IRQ sense control register L (ISCRL) IRQ enable register (IER) IRQ status register (ISR) IRQ pin select register (ITSR) Software standby release IRQ enable register (SSIER) Interrupt priority register A (IPRA) Interrupt priority register B (IPRB) Interrupt priority register C (IPRC) Interrupt priority register D (IPRD) Interrupt priority register E (IPRE) Interrupt priority register F (IPRF) Interrupt priority register G (IPRG) Interrupt priority register H (IPRH) Interrupt priority register I (IPRI) Interrupt priority register J (IPRJ) Interrupt priority register K (IPRK) Interrupt priority register L (IPRL) Interrupt priority register M (IPRM) Interrupt priority register N (IPRN) Rev. 1.00 Sep. 19, 2008 Page 106 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit Bit Name Initial Value R/W Description 7, 6 — All 0 — Reserved These bits are always read as 0 and the initial value should not be changed. 5 INTM1 0 R/W Interrupt Control Select Mode 1 and 0 4 INTM0 0 R/W These bits select either of two interrupt control modes for the interrupt controller. 00: Interrupt control mode 0 Interrupts are controlled by I bit. 01: Setting prohibited. 10: Interrupt control mode 2 Interrupts are controlled by bits I2 to I0, and IPR. 11: Setting prohibited. 3 NMIEG 0 R/W NMI Edge Select Selects the input edge for the NMI pin. 0: Interrupt request generated at falling edge of NMI input 1: Interrupt request generated at rising edge of NMI input 2 to 0 — All 0 — Reserved These bits are always read as 0 and the initial value should not be changed. Rev. 1.00 Sep. 19, 2008 Page 107 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.3.2 Interrupt Priority Registers A to N (IPRA to IPRN) IPR are eleven 16-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between interrupt sources and IPR settings is shown in table 5.2 (Interrupt Sources, Vector Addresses, and Interrupt Priorities). Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 sets the priority of the corresponding interrupt. IPR should be read in word size. Bit Bit Name Initial Value R/W 15 — 0 — Description Reserved This bit is always read as 0 and the initial value should not be changed. 14 IPR14 1 R/W 13 IPR13 1 R/W 12 IPR12 1 R/W Sets the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) 11 — 0 — Reserved This bit is always read as 0 and the initial value should not be changed. 10 IPR10 1 R/W 9 IPR9 1 R/W Sets the priority of the corresponding interrupt source. 8 IPR8 1 R/W 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) Rev. 1.00 Sep. 19, 2008 Page 108 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 7 — 0 — Reserved This bit is always read as 0 and the initial value should not be changed. 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W 3 — 0 — Sets the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) Reserved This bit is always read as 0 and the initial value should not be changed. 2 IPR2 1 R/W 1 IPR1 1 R/W Sets the priority of the corresponding interrupt source. 0 IPR0 1 R/W 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) Rev. 1.00 Sep. 19, 2008 Page 109 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.3.3 IRQ Enable Register (IER) IER controls enabling and disabling of interrupt requests IRQ15 to IRQ0. Bit Bit Name Initial Value R/W Description 15 IRQ15E 0 R/W IRQ15 Enable* The IRQ15 interrupt request is enabled when this bit is 1. 14 IRQ14E 0 R/W IRQ14 Enable* The IRQ14 interrupt request is enabled when this bit is 1. 13 IRQ13E 0 R/W IRQ13 Enable* The IRQ13 interrupt request is enabled when this bit is 1. 12 IRQ12E 0 R/W IRQ12 Enable* The IRQ12 interrupt request is enabled when this bit is 1. 11 IRQ11E 0 R/W IRQ11 Enable* The IRQ11 interrupt request is enabled when this bit is 1. 10 IRQ10E 0 R/W IRQ10 Enable* The IRQ10 interrupt request is enabled when this bit is 1. 9 IRQ9E 0 R/W IRQ9 Enable* The IRQ9 interrupt request is enabled when this bit is 1. 8 IRQ8E 0 R/W IRQ8 Enable* The IRQ8 interrupt request is enabled when this bit is 1. 7 IRQ7E 0 R/W IRQ7 Enable The IRQ7 interrupt request is enabled when this bit is 1. 6 IRQ6E 0 R/W IRQ6 Enable The IRQ6 interrupt request is enabled when this bit is 1. Rev. 1.00 Sep. 19, 2008 Page 110 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 5 IRQ5E 0 R/W IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1. 4 IRQ4E 0 R/W IRQ4 Enable The IRQ4 interrupt request is enabled when this bit is 1. 3 IRQ3E 0 R/W IRQ3 Enable The IRQ3 interrupt request is enabled when this bit is 1. 2 IRQ2E 0 R/W IRQ2 Enable The IRQ2 interrupt request is enabled when this bit is 1. 1 IRQ1E 0 R/W IRQ1 Enable The IRQ1 interrupt request is enabled when this bit is 1. 0 IRQ0E 0 R/W IRQ0 Enable The IRQ0 interrupt request is enabled when this bit is 1. Note: * These bits are reserved in the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 111 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCR select the source that generates an interrupt request at pins IRQ15 to IRQ0. • ISCRH (H8S/2426 Group only) Bit Bit Name Initial Value R/W Description 15 IRQ15SCB 0 R/W IRQ15 Sense Control B 14 IRQ15SCA 0 R/W IRQ15 Sense Control A 00: Interrupt request generated at IRQ15 input low level 01: Interrupt request generated at falling edge of IRQ15 input 10: Interrupt request generated at rising edge of IRQ15 input 11: Interrupt request generated at both falling and rising edges of IRQ15 input 13 IRQ14SCB 0 R/W IRQ14 Sense Control B 12 IRQ14SCA 0 R/W IRQ14 Sense Control A 00: Interrupt request generated at IRQ14 input low level 01: Interrupt request generated at falling edge of IRQ14 input 10: Interrupt request generated at rising edge of IRQ14 input 11: Interrupt request generated at both falling and rising edges of IRQ14 input 11 IRQ13SCB 0 R/W IRQ13 Sense Control B 10 IRQ13SCA 0 R/W IRQ13 Sense Control A 00: Interrupt request generated at IRQ13 input low level 01: Interrupt request generated at falling edge of IRQ13 input 10: Interrupt request generated at rising edge of IRQ13 input 11: Interrupt request generated at both falling and rising edges of IRQ13 input Rev. 1.00 Sep. 19, 2008 Page 112 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 9 IRQ12SCB 0 R/W IRQ12 Sense Control B 8 IRQ12SCA 0 R/W IRQ12 Sense Control A 00: Interrupt request generated at IRQ12 input low level 01: Interrupt request generated at falling edge of IRQ12 input 10: Interrupt request generated at rising edge of IRQ12 input 11: Interrupt request generated at both falling and rising edges of IRQ12 input 7 IRQ11SCB 0 R/W IRQ11 Sense Control B 6 IRQ11SCA 0 R/W IRQ11 Sense Control A 00: Interrupt request generated at IRQ11 input low level 01: Interrupt request generated at falling edge of IRQ11 input 10: Interrupt request generated at rising edge of IRQ11 input 11: Interrupt request generated at both falling and rising edges of IRQ11 input 5 IRQ10SCB 0 R/W IRQ10 Sense Control B 4 IRQ10SCA 0 R/W IRQ10 Sense Control A 00: Interrupt request generated at IRQ10 input low level 01: Interrupt request generated at falling edge of IRQ10 input 10: Interrupt request generated at rising edge of IRQ10 input 11: Interrupt request generated at both falling and rising edges of IRQ10 input Rev. 1.00 Sep. 19, 2008 Page 113 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 3 IRQ9SCB 0 R/W IRQ9 Sense Control B 2 IRQ9SCA 0 R/W IRQ9 Sense Control A 00: Interrupt request generated at IRQ9 input low level 01: Interrupt request generated at falling edge of IRQ9 input 10: Interrupt request generated at rising edge of IRQ9 input 11: Interrupt request generated at both falling and rising edges of IRQ9 input 1 IRQ8SCB 0 R/W IRQ8 Sense Control B 0 IRQ8SCA 0 R/W IRQ8 Sense Control A 00: Interrupt request generated at IRQ8 input low level 01: Interrupt request generated at falling edge of IRQ8 input 10: Interrupt request generated at rising edge of IRQ8 input 11: Interrupt request generated at both falling and rising edges of IRQ8 input Rev. 1.00 Sep. 19, 2008 Page 114 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller • ISCRL Bit Bit Name Initial Value R/W Description 15 IRQ7SCB 0 R/W IRQ7 Sense Control B 14 IRQ7SCA 0 R/W IRQ7 Sense Control A 00: Interrupt request generated at IRQ7 input low level 01: Interrupt request generated at falling edge of IRQ7 input 10: Interrupt request generated at rising edge of IRQ7 input 11: Interrupt request generated at both falling and rising edges of IRQ7 input 13 IRQ6SCB 0 R/W IRQ6 Sense Control B 12 IRQ6SCA 0 R/W IRQ6 Sense Control A 00: Interrupt request generated at IRQ6 input low level 01: Interrupt request generated at falling edge of IRQ6 input 10: Interrupt request generated at rising edge of IRQ6 input 11: Interrupt request generated at both falling and rising edges of IRQ6 input 11 IRQ5SCB 0 R/W IRQ5 Sense Control B 10 IRQ5SCA 0 R/W IRQ5 Sense Control A 00: Interrupt request generated at IRQ5 input low level 01: Interrupt request generated at falling edge of IRQ5 input 10: Interrupt request generated at rising edge of IRQ5 input 11: Interrupt request generated at both falling and rising edges of IRQ5 input Rev. 1.00 Sep. 19, 2008 Page 115 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 9 IRQ4SCB 0 R/W IRQ4 Sense Control B 8 IRQ4SCA 0 R/W IRQ4 Sense Control A 00: Interrupt request generated at IRQ4 input low level 01: Interrupt request generated at falling edge of IRQ4 input 10: Interrupt request generated at rising edge of IRQ4 input 11: Interrupt request generated at both falling and rising edges of IRQ4 input 7 IRQ3SCB 0 R/W IRQ3 Sense Control B 6 IRQ3SCA 0 R/W IRQ3 Sense Control A 00: Interrupt request generated at IRQ3 input low level 01: Interrupt request generated at falling edge of IRQ3 input 10: Interrupt request generated at rising edge of IRQ3 input 11: Interrupt request generated at both falling and rising edges of IRQ3 input 5 IRQ2SCB 0 R/W IRQ2 Sense Control B 4 IRQ2SCA 0 R/W IRQ2 Sense Control A 00: Interrupt request generated at IRQ2 input low level 01: Interrupt request generated at falling edge of IRQ2 input 10: Interrupt request generated at rising edge of IRQ2 input 11: Interrupt request generated at both falling and rising edges of IRQ2 input Rev. 1.00 Sep. 19, 2008 Page 116 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 3 IRQ1SCB 0 R/W IRQ1 Sense Control B 2 IRQ1SCA 0 R/W IRQ1 Sense Control A 00: Interrupt request generated at IRQ1 input low level 01: Interrupt request generated at falling edge of IRQ1 input 10: Interrupt request generated at rising edge of IRQ1 input 11: Interrupt request generated at both falling and rising edges of IRQ1 input 1 IRQ0SCB 0 R/W IRQ0 Sense Control B 0 IRQ0SCA 0 R/W IRQ0 Sense Control A 00: Interrupt request generated at IRQ0 input low level 01: Interrupt request generated at falling edge of IRQ0 input 10: Interrupt request generated at rising edge of IRQ0 input 11: Interrupt request generated at both falling and rising edges of IRQ0 input Rev. 1.00 Sep. 19, 2008 Page 117 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.3.5 IRQ Status Register (ISR) ISR is an IRQ15 to IRQ0 interrupt request flag register. Bit 15 Bit Name IRQ15F* 2 Initial Value 0 R/W Description [Setting condition] 1 1 When the interrupt source selected by ISCR occurs 1 [Clearing conditions] 1 • Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag • When interrupt exception handling is executed when low-level detection is set and IRQn input is high • When IRQn interrupt exception handling is executed when falling, rising, or both-edge detection is set • When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 R/(W)* 1 R/(W)* 2 0 R/(W)* IRQ11F* 0 11 2 IRQ12F* R/(W)* 12 R/(W)* 0 IRQ13F* 0 IRQ14F* 13 2 14 2 2 10 IRQ10F* 9 IRQ9F* 8 1 0 R/(W)* 2 0 R/(W)* IRQ8F* 2 0 R/(W)* 7 IRQ7F 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 1 1 1 1 1 1 1 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* 1 1 1 Notes: 1. Only 0 can be written, to clear the flag. 2. These bits are reserved in the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 118 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.3.6 IRQ Pin Select Register (ITSR) ITSR selects input pins IRQ15 to IRQ0. • H8S/2426 Group Bit Bit Name Initial Value R/W Description 15 ITS15 0 R/W Selects the IRQ15 input pin. 0: PF2/IRQ15-A selected 1: P27/IRQ15-B selected 14 ITS14 0 R/W Selects the IRQ14 input pin. 0: PF1/IRQ14-A selected 1: P26/IRQ14-B selected 13 ITS13 0 R/W Selects the IRQ13 input pin. 0: P65/IRQ13-A selected 1: P25/IRQ13-B selected 12 ITS12 0 R/W Selects the IRQ12 input pin. 0: P64/IRQ12-A selected 1: P24/IRQ12-B selected 11 ITS11 0 R/W Selects the IRQ11 input pin. 0: P63/IRQ11-A selected 1: P23/IRQ11-B selected 10 ITS10 0 R/W Selects the IRQ10 input pin. 0: P62/IRQ10-A selected 1: P22/IRQ10-B selected 9 ITS9 0 R/W Selects the IRQ9 input pin. 0: P61/IRQ9-A selected 1: P21/IRQ9-B selected 8 ITS8 0 R/W Selects the IRQ8 input pin. 0: P60/IRQ8-A selected 1: P20/IRQ8-B selected 7 ITS7 0 R/W Selects the IRQ7 input pin. 0: PA7/IRQ7-A selected 1: PH3/IRQ7-B selected Rev. 1.00 Sep. 19, 2008 Page 119 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 6 ITS6 0 R/W Selects the IRQ6 input pin. 0: PA6/IRQ6-A selected 1: PH2/IRQ6-B selected 5 ITS5 0 R/W Selects the IRQ5 input pin. 0: PA5/IRQ5-A selected 1: P85/IRQ5-B selected 4 ITS4 0 R/W Selects the IRQ4 input pin. 0: PA4/IRQ4-A selected 1: P84/IRQ4-B selected 3 ITS3 0 R/W Selects the IRQ3 input pin. 0: P53/IRQ3-A selected 1: P83/IRQ3-B selected 2 ITS2 0 R/W Selects the IRQ2 input pin. 0: P52/IRQ2-A selected 1: P82/IRQ2-B selected 1 ITS1 0 R/W Selects the IRQ1 input pin. 0: P51/IRQ1-A selected 1: P81/IRQ1-B selected 0 ITS0 0 R/W Selects the IRQ0 input pin. 0: P50/IRQ0-A selected 1: P80/IRQ0-B selected Rev. 1.00 Sep. 19, 2008 Page 120 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller • H8S/2424 Group Bit Bit Name 15 to 8 — Initial Value R/W Description All 0 Reserved R/W The initial value should not be changed. 7 ITS7 0 R/W Selects the IRQ7 input pin. 0: PA7/IRQ7-A selected 1: P47/IRQ7-B selected 6 ITS6 0 R/W Selects the IRQ6 input pin. 0: PA6/IRQ6-A selected 1: P46/IRQ6-B selected 5 ITS5 0 R/W Selects the IRQ5 input pin. 0: PA5/IRQ5-A selected 1: P45/IRQ5-B selected 4 ITS4 0 R/W Selects the IRQ4 input pin. 0: PA4/IRQ4-A selected 1: P44/IRQ4-B selected 3 ITS3 0 R/W Selects the IRQ3 input pin. 0: P53/IRQ3-A selected 1: P43/IRQ3-B selected 2 ITS2 0 R/W Selects the IRQ2 input pin. 0: P52/IRQ2-A selected 1: P42/IRQ2-B selected 1 ITS1 0 R/W Selects the IRQ1 input pin. 0: P51/IRQ1-A selected 1: P41/IRQ1-B selected 0 ITS0 0 R/W Selects the IRQ0 input pin. 0: P50/IRQ0-A selected 1: P40/IRQ0-B selected Rev. 1.00 Sep. 19, 2008 Page 121 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects the IRQ pins used to recover from the software standby state. Bit Bit Name Initial Value R/W Description 15 SSI15* 0 R/W Software Standby Release IRQ Setting 14 SSI14* 0 R/W 13 SSI13* 0 R/W These bits select the IRQn pins used to recover from the software standby state. 12 SSI12* 0 R/W 11 SSI11* 0 R/W 10 SSI10* 0 R/W 9 SSI9* 0 R/W 8 SSI8* 0 R/W 7 SSI7 0 R/W 6 SSI6 0 R/W 5 SSI5 0 R/W 4 SSI4 0 R/W 3 SSI3 0 R/W 2 SSI2 0 R/W 1 SSI1 0 R/W 0 SSI0 0 R/W Note: * 0: IRQn requests are not sampled in the software standby state (Initial value when n = 15 to 3) 1: When an IRQn request occurs in the software standby state, the chip recovers from the software standby state after the elapse of the oscillation settling time (Initial value when n = 2 to 0) These bits are reserved in the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 122 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.4 Interrupt Sources 5.4.1 External Interrupts The H8S/2426 Group and H8S/2426R Group each have seventeen external interrupts: NMI and IRQ15 to IRQ0. The H8S/2424 Group has nine external interrupts: NMI and IRQ7 to IRQ0. These interrupts can be used to restore the chip from software standby mode. NMI Interrupt: Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in INTCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. IRQn Interrupts (n = 0 to 15 for H8S/2426 Group and H8S/2426R Group, n = 0 to 7 for H8S/2424 Group): An IRQn interrupt is requested by an input signal at the IRQn pin. The IRQn interrupts have the following features: • Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at the IRQn pin. • Enabling or disabling of IRQn interrupt requests can be selected with IER. • The interrupt priority level can be set with IPR. • The status of IRQn interrupt requests is indicated in ISR. ISR flags can be cleared to 0 by software. When IRQn interrupt requests occur at low level of the IRQn pin, the corresponding IRQ pin should be held low until an interrupt handling starts. Then the corresponding IRQ pin should be set to high in the interrupt handling routine and clear the IRQnF bit in ISR to 0. Interrupts may not be executed when the corresponding IRQ pin is set to high before the interrupt handling starts. Detection of IRQn interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 and use the pin as an I/O pin for another function. Rev. 1.00 Sep. 19, 2008 Page 123 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller A block diagram of IRQn interrupts is shown in figure 5.2. IRQnE IRQnSCA, IRQnSCB IRQnF Edge/ level detection circuit IRQn input S Q IRQn interrupt request R Clear signal Note: n = 0 to 15 for H8S/2426 Group and H8S/2426R Group, n = 0 to 7 for H8S/2424 Group Figure 5.2 Block Diagram of IRQ Interrupts 5.4.2 Internal Interrupts The sources for internal interrupts from on-chip peripheral modules have the following features: • For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. They can be controlled independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt controller. • The interrupt priority level can be set by means of IPR. • The DMAC and DTC can be activated by a TPU, SCI, or other interrupt request. • When the DMAC or DTC is activated by an interrupt request, it is not affected by the interrupt control mode or CPU interrupt mask bit. Rev. 1.00 Sep. 19, 2008 Page 124 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.5 Interrupt Exception Handling Vector Table Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. When interrupt control mode 2 is set, priorities among modules can be set by means of the IPR. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. Table 5.2 Interrupt Source External pin Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector 1 Address* Origin of Interrupt Source Vector Number Advanced Mode IPR Priority DTC Activation DMAC Activation NMI 7 H'001C High IRQ0 16 H'0040 IPRA14 to IPRA12 IRQ1 17 H'0044 IPRA10 to IPRA8 IRQ2 18 H'0048 IPRA6 to IPRA4 IRQ3 19 H'004C IPRA2 to IPRA0 IRQ4 20 H'0050 IPRB14 to IPRB12 IRQ5 21 H'0054 IPRB10 to IPRB8 IRQ6 22 H'0058 IPRB6 to IPRB4 23 H'005C IPRB2 to IPRB0 24 H'0060 IPRC14 to IPRC12 IRQ7 2 IRQ8* 25 H'0064 IPRC10 to IPRC8 2 26 H'0068 IPRC6 to IPRC4 2 27 H'006C IPRC2 to IPRC0 2 28 H'0070 IPRD14 to IPRD12 2 29 H'0074 IPRD10 to IPRD8 2 30 H'0078 IPRD6 to IPRD4 2 IRQ15* 31 H'007C IPRD2 to IPRD0 DTC SWDTEND 32 H'0080 IPRE14 to IPRE12 WDT WOVI 33 H'0084 IPRE10 to IPRE8 Reserved for 34 system use H'0088 IPRE6 to IPRE4 Refresh controller CMI H'008C IPRE2 to IPRE0 2 IRQ9* IRQ10* IRQ11* IRQ12* IRQ13* IRQ14* 35 Low Rev. 1.00 Sep. 19, 2008 Page 125 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Interrupt Source A/D_0 TPU_0 TPU_1 TPU_2 TPU_3 Origin of Interrupt Source Vector 1 Address* Vector Number Advanced Mode IPR Priority DTC Activation DMAC Activation Reserved for 36 system use 37 H'0090 IPRF14 to IPRF12 High ADI0 H'0094 38 H'0098 Reserved for 39 system use H'009C IPRF10 to IPRF8 TGI0A 40 H'00A0 TGI0B 41 H'00A4 TGI0C 42 H'00A8 TGI0D 43 H'00AC TCI0V IPRF6 to IPRF4 IPRF6 to IPRF4 44 H'00B0 Reserved for 45 system use 46 H'00B4 H'00B8 47 H'00BC TGI1A 48 H'00C0 TGI1B 49 H'00C4 TCI1V 50 H'00C8 TCI1U 51 H'00CC IPRF2 to IPRF0 TGI2A 52 H'00D0 TGI2B 53 H'00D4 TCI2V 54 H'00D8 TCI2U 55 H'00DC TGI3A 56 H'00E0 TGI3B 57 H'00E4 TGI3C 58 H'00E8 TGI3D 59 H'00EC TCI3V 60 H'00F0 Reserved for 61 system use 62 H'00F4 H'00F8 63 H'00FC Rev. 1.00 Sep. 19, 2008 Page 126 of 1270 REJ09B0466-0100 IPRG14 to IPRG12 IPRG10 to IPRG8 Low Section 5 Interrupt Controller Vector 1 Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority TPU_4 TGI4A 64 H'0100 IPRG6 to IPRG4 High TGI4B 65 H'0104 TCI4V 66 H'0108 TCI4U 67 H'010C TGI5A 68 H'0110 TGI5B 69 H'0114 TCI5V 70 H'0118 TCI5U 71 H'011C CMIA0 72 H'0120 CMIB0 73 H'0124 OVI0 74 H'0128 Reserved for 75 system use H'012C IPRH14 to IPRH12 CMIA1 76 H'0130 IPRH10 to IPRH8 CMIB1 77 H'0134 OVI1 78 H'0138 Reserved for 79 system use H'013C DMTEND0A 80 H'0140 DMTEND0B 81 H'0144 DMTEND1A 82 H'0148 DMTEND1B 83 H'014C EXDMAC* Reserved for 84 system use 85 H'0150 TPU_5 TMR_0 TMR_1 DMAC DTC Activation DMAC Activation IPRG2 to IPRG0 IPRH14 to IPRH12 IPRH6 to IPRH4 IPRH0 to IPRH0 H'0154 IPRI14 to IPRI12 EXDMTEND 86 2 H'0158 IPRI10 to IPRI8 EXDMTEND 87 3 H'015C IPRI6 to IPRI4 2 Low Rev. 1.00 Sep. 19, 2008 Page 127 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Vector 1 Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority DTC Activation DMAC Activation SCI_0 ERI0 88 H'0160 IPRI2 to IPRI0 High RXI0 89 H'0164 SCI_1 SCI_2 SCI_3 SCI_4 A/D_1 TXI0 90 H'0168 TEI0 91 H'016C ERI1 92 H'0170 RXI1 93 H'0174 TXI1 94 H'0178 TEI1 95 H'017C ERI2 96 H'0180 RXI2 97 H'0184 TXI2 98 H'0188 TEI2 99 H'018C ERI3 100 H'0190 RXI3 101 H'0194 TXI3 102 H'0198 TEI3 103 H'019C ERI4 104 H'01A0 RXI4 105 TXI4 106 H'01A8 TEI4 107 H'01AC Reserved for 108 system use 109 H'01B0 ADI1 IPRJ10 to IPRJ8 IPRJ6 to IPRJ4 IPRJ2 to IPRJ0 H'01A4 H'01B4 110 H'01B8 111 H'01BC 112 H'01C0 Reserved for 113 system use 114 H'01C4 115 H'01CC IPRK14 to IPRK12 IPRK10 to IPRK8 H'01C8 Rev. 1.00 Sep. 19, 2008 Page 128 of 1270 REJ09B0466-0100 IPRJ14 to IPRJ12 Low Section 5 Interrupt Controller Vector 1 Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority DTC Activation DMAC Activation IIC2_0 IICI0 116 H'01D0 IPRK6 to IPRK4 High IIC2_1 TPU_6 TPU_7 TPU_8 TPU_9 TPU_10 Reserved for 117 system use H'01D4 IICI1 H'01D8 Reserved for 119 system use H'01DC TGI6A 120 H'01E0 TGI6B 121 H'01E4 TGI6C 122 H'01E8 TGI6D 123 H'01EC TCI6V 124 H'01F0 TGI7A 125 H'01F4 TGI7B 126 H'01F8 TCI7V 127 H'01FC TCI7U 128 H'0200 TGI8A 118 129 H'0204 IPRK2 to IPRK0 IPRL14 to IPRL12 IPRL10 to IPRL8 TGI8B 130 H'0208 TCI8V 131 H'020C TCI8U 132 H'0210 TGI9A 133 H'0214 TGI9B 134 H'0218 TGI9C 135 H'021C TGI9D 136 H'0220 TCI9V 137 H'0224 TGI10A 138 H'0228 TGI10B 139 H'022C TCI10V 140 H'0230 TCI10U 141 H'0234 IPRL6 to IPRL4 IPRL2 to IPRL0 Low Rev. 1.00 Sep. 19, 2008 Page 129 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Vector 1 Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority TPU_11 TGI11A 142 H'0238 IPRM14 to IPRM12 High TGI11B 143 H'023C TCI11V 144 H'0240 TCI11U 145 H'0244 Reserved for 146 system use 147 H'0248 H'024C 148 H'0250 149 H'0254 150 H'0258 DTC Activation DMAC Activation IPRM10 to IPRM8 IPRM6 to IPRM4 151 H'025C 152 H'0260 IPRM2 to IPRM0 IIC2_2 IICI2 153 H'0264 IIC2_3 IICI3 154 H'0268 SSU SSERI 155 H'026C SSRXI 156 H'0270 SSTXI 157 H'0274 Reserved for 158 system use 159 H'0278 H'027C 160 H'0280 161 H'0284 162 H'0288 163 H'028C 164 H'0290 165 H'0294 166 H'0298 IPRN10 to IPRN8 IPRN6 to IPRN4 IPRN2 to IPRN0 167 H'029C 168 H'02A0 169 H'02A4 Rev. 1.00 Sep. 19, 2008 Page 130 of 1270 REJ09B0466-0100 IPRN14 to IPRN12 Low Section 5 Interrupt Controller Interrupt Source Origin of Interrupt Source Vector 1 Address* Vector Number Advanced Mode IPR Priority DTC Activation DMAC Activation Reserved for 170 system use | H'02A8 High | | 255 H'03FC Low | Notes: 1. Lower 16 bits of the start address. 2. Not supported in the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 131 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 5.3 Interrupt Control Modes Interrupt Control Mode Priority Setting Registers Interrupt Mask Bits 0 Default I The priorities of interrupt sources are fixed at the default settings. Interrupt sources except for NMI is masked by the I bit. 2 IPR I2 to I0 8 priority levels except for NMI can be set with IPR. 8-level interrupt mask control is performed by bits I2 to I0. Rev. 1.00 Sep. 19, 2008 Page 132 of 1270 REJ09B0466-0100 Description Section 5 Interrupt Controller 5.6.1 Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests except for NMI are masked by the I bit of CCR in the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. If the I bit is cleared, an interrupt request is accepted. 3. Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev. 1.00 Sep. 19, 2008 Page 133 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Program execution status No Interrupt generated? Yes Yes NMI No I=0 No Hold pending Yes No IRQ0 No Yes IRQ1 Yes SSTXI Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 1.00 Sep. 19, 2008 Page 134 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.2 is selected. 3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev. 1.00 Sep. 19, 2008 Page 135 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Program execution status Interrupt generated? No Yes Yes NMI No Level 7 interrupt? No Yes Mask level 6 or below? Level 6 interrupt? No No Yes Level 1 interrupt? Yes Mask level 5 or below? No No Yes Yes Mask level 0? No Yes Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev. 1.00 Sep. 19, 2008 Page 136 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.6.3 Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev. 1.00 Sep. 19, 2008 Page 137 of 1270 REJ09B0466-0100 REJ09B0466-0100 Rev. 1.00 Sep. 19, 2008 Page 138 of 1270 Figure 5.5 Interrupt Exception Handling (1) (2) (4) (3) Internal operation Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP-2 (7) SP-4 (1) Internal data bus Internal write signal Internal read signal Internal address bus Interrupt request signal φ Interrupt level determination Instruction Wait for end of instruction prefetch Interrupt acceptance (7) (8) (10) (9) (12) (11) Internal operation (14) (13) Interrupt handling routine instruction prefetch Saved PC and saved CCR Vector address Interrupt handling routine start address (Vector address contents) Interrupt handling routine start address ((13) = (10)(12)) First instruction of interrupt handling routine (6) (6) (8) (9) (11) (10) (12) (13) (14) (5) Stack Vector fetch Section 5 Interrupt Controller Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.4 Interrupt Response Times Normal Mode*5 No. Execution Status Interrupt control mode 0 1 Interrupt priority determination*1 3 2 Number of wait states until executing 1 to 19 2 +2·SI instruction ends* Advanced Mode Interrupt control mode 2 Interrupt control mode 0 Interrupt control mode 2 3 3 3 1 to 19+2·SI 1 to 19+2·SI 1 to 19+2·SI 3 PC, CCR, EXR stack save 2·SK 3·SK 2·SK 3·SK 4 Vector fetch SI SI 2·SI 2·SI 5 Instruction fetch*3 2·SI 2·SI 2·SI 2·SI 2 2 2 2 11 to 31 12 to 32 12 to 32 13 to 33 6 Internal processing* 4 Total (using on-chip memory) Notes: 1. 2. 3. 4. 5. Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Not available in this LSI. Rev. 1.00 Sep. 19, 2008 Page 139 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8 Bit Bus 16 Bit Bus Symbol Internal Memory 2-State Access 3-State Access 2-State Access 3-State Access Instruction fetch SI 1 4 6+2m 2 3+m Branch address read SJ Stack manipulation SK Legend: m: Number of wait states in an external device access. 5.6.5 DTC and DMAC Activation by Interrupt The DTC and DMAC can be activated by an interrupt. In this case, the following options are available: • • • • Interrupt request to CPU Activation request to DTC Activation request to DMAC Selection of a number of the above For details of interrupt requests that can be used to activate the DTC and DMAC, see table 5.2 and section 9, Data Transfer Controller (DTC) and section 7, DMA Controller (DMAC). Rev. 1.00 Sep. 19, 2008 Page 140 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.7 Usage Notes 5.7.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.6 shows an example in which the TCIEV bit in the TPU’s TIER_0 register is cleared to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. TIER_0 write cycle by CPU TCIV exception handling φ Internal address bus TIER_0 address Internal write signal TCIEV TCFV TCIV interrupt signal Figure 5.6 Conflict between Interrupt Generation and Disabling Rev. 1.00 Sep. 19, 2008 Page 141 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.7.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.7.3 Times when Interrupts are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. 5.7.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the transfer is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W R4,R4 BNEL1 5.7.5 Change of IRQ Pin Select Register (ITSR) Setting When the ITSR setting is changed, an edge occurs internally and the IRQnF bit (n = 0 to 15 for H8S/2426 Group, n = 0 to 7 for H8S/2424 Group) of ISR may be set to 1 at the unintended timing if the selected pin level before the change is different from the selected pin level after the change. If the IRQn interrupt request (n = 0 to 15 for H8S/2426 Group, n = 0 to 7 for H8S/2424 Group) is enabled, the interrupt exception handling is executed. To prevent the unintended interrupt, ITSR setting should be changed while the IRQn interrupt request is disabled, then the IRQnF bit should be cleared to 0. Rev. 1.00 Sep. 19, 2008 Page 142 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.7.6 IRQ Status Register (ISR) Depending on the pin status following a reset, IRQnF may be set to 1. Therefore, always read ISR and clear it to 0 after resets. Rev. 1.00 Sep. 19, 2008 Page 143 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 144 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the bus mastershipthe CPU, DMA controller (DMAC), EXDMA controller (EXDMAC)*, and data transfer controller (DTC). A block diagram of the bus controller is shown in figure 6.1. Note: * Not supported by the H8S/2424 Group. 6.1 Features • Manages external address space in area units Manages the external address space divided into eight areas of 2 Mbytes Bus specifications can be set independently for each area Burst ROM, DRAM, synchronous DRAM*1, and address/data multiplexed I/O interfaces can be set • Basic bus interface Chip select signals (CS0 to CS7) can be output for areas 0 to 7 8-bit access or 16-bit access can be selected for each area 2-state access or 3-state access can be selected for each area Program wait cycles can be inserted for each area Extension cycles can be inserted while CS is asserted for each area Wait cycles can be inserted by the WAIT pin The negation timing of the read strobe signal (RD) can be modified • Burst ROM interface Burst ROM interface can be set independently for areas 0 and 1 • Address/data multiplexed I/O interface Address/data multiplexed I/O interface can be set for areas 6 and 7 • DRAM interface DRAM interface can be set for areas 2 to 5 • Synchronous DRAM interface*1 Continuous synchronous DRAM space can be set for areas 2 to 5 Rev. 1.00 Sep. 19, 2008 Page 145 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) • Idle cycle insertion Idle cycles can be inserted between external read cycles to different areas Idle cycles can be inserted before the write cycle after a read cycle Idle cycles can be inserted before the read cycle after a write cycle • Write buffer function External write cycles and internal accesses can be executed in parallel DMAC single address transfers and internal accesses can be executed in parallel • Bus arbitration function Includes a bus arbiter that arbitrates bus mastership between the CPU, DMAC, DTC, and EXDMAC*2 Notes: 1. Not supported by the H8S/2426 Group and H8S/2424 Group. 2. Not supported by the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 146 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) EXDMAC address bus Internal address bus Address selector CS7 to CS0 Area decoder WAIT BREQ BACK BREQO External bus controller Internal bus master bus request signal EXDMAC bus request signal Internal bus master bus acknowledge signal EXDMAC bus acknowledge signal External bus arbiter External bus control signals Internal bus control signals Internal bus controller CPU bus request signal DTC bus request signal DMAC bus request signal CPU bus acknowledge signal DTC bus acknowledge signal DMAC bus acknowledge signal Internal bus arbiter Control registers Internal data bus ABWCR ASTCR DRAMCR WTCRAH WTCRAL DRACCRH DRACCRL WTCRBH WTCRBL REFCR RTCNT RDNCR CSACRH RTCOR CSACRL BROMCRH BROMCRL BCR MPXCR Legend: ABWCR ASTCR WTCRAH, WTCRAL, WTCRBH, and WTCRBL RDNCR CSACRH and CSACRL BROMCRH BROMCRL BCR MPXCR DRAMCR DRACCRH and DRACCRL REFCR RTCNT RTCOR : Bus width control register : Access state control register : Wait control registers AH, AL, BH, and BL : Read strobe timing control register : CS assertion period control registers H and L : Area 0 burst ROM interface control register : Area 1 burst ROM interface control register : Bus control register : Address/data multiplexed I/O control register : DRAM control register : DRAM access control registers H and L : Refresh control register : Refresh timer counter : Refresh time constant register Figure 6.1 Block Diagram of Bus Controller Rev. 1.00 Sep. 19, 2008 Page 147 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.2 Input/Output Pins Table 6.1 shows the pin configuration of the bus controller. Table 6.1 Pin Configuration Name Symbol I/O Function Address strobe AS Output Strobe signal indicating that normal space is accessed and address output on address bus is enabled. Address hold AH Output Signal indicating the timing for latching the address when the address/data multiplexed I/O space is set. Read RD Output Strobe signal indicating that normal space is being read. High write/write enable HWR/WE Output Strobe signal indicating that normal space is written to, and upper half (D15 to D8) of data bus is enabled or DRAM space write enable signal. Low write LWR Output Strobe signal indicating that normal space is written to, and lower half (D7 to D0) of data bus is enabled. Chip select 0 CS0 Output Strobe signal indicating that area 0 is selected. Chip select 1 CS1 Output Strobe signal indicating that area 1 is selected Chip select 2/ row address strobe 2/ row address strobe*1 CS2/ RAS2/ RAS*1 Output Strobe signal indicating that area 2 is selected, DRAM row address strobe signal when area 2 is DRAM space or areas 2 to 5 are set as continuous DRAM space, or row address strobe signal of the synchronous DRAM when the synchronous DRAM interface is selected. Chip select 3/ row address strobe 3/ column address strobe*1 CS3/ RAS3/ CAS*1 Output Strobe signal indicating that area 3 is selected, DRAM row address strobe signal when area 3 is DRAM space, or column address strobe signal of the synchronous DRAM when the synchronous DRAM interface is selected. Rev. 1.00 Sep. 19, 2008 Page 148 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Name Symbol I/O Function Chip select 4/ row address strobe 4/ 1 write enable* CS4/ RAS4/ WE*1 Output Strobe signal indicating that area 4 is selected, DRAM row address strobe signal when area 4 is DRAM space, or write enable signal of the synchronous DRAM when the synchronous DRAM interface is selected. Chip select 5/ row address strobe 5/ 1 SDRAMφ* CS5/ Output RAS5/ SDRAMφ*1 Strobe signal indicating that area 5 is selected, DRAM row address strobe signal when area 5 is DRAM space, or dedicated clock signal for the synchronous DRAM when the synchronous DRAM interface is selected. Chip select 6 CS6 Output Strobe signal indicating that area 6 is selected. Chip select 7 CS7 Output Strobe signal indicating that area 7 is selected. Upper column address strobe/ 1 upper data mask enable* UCAS/ DQMU*1 Output 16-bit DRAM space upper column address strobe signal, 8-bit DRAM space column address strobe signal, upper data mask signal of 16-bit synchronous DRAM space, or data mask signal of 8-bit synchronous DRAM space. Lower column address strobe/ lower data mask enable*1 LCAS/ DQML*1 Output 16-bit DRAM space lower column address strobe signal or lower data mask signal for the 16-bit synchronous DRAM space. Output enable/clock enable OE/ CKE*1 Output Output enable signal for the DRAM space or clock enable signal for the synchronous DRAM space. Wait WAIT Input Wait request signal when accessing external address space. Bus request BREQ Input Request signal for release of bus to external bus master. Bus request acknowledge BACK Output Acknowledge signal indicating that bus has been released to external bus master. Bus request output BREQO Output External bus request signal used when internal bus master accesses external address space when external bus is released. Rev. 1.00 Sep. 19, 2008 Page 149 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Name Symbol I/O Function Data transfer acknowledge 1 (DMAC) DACK1 Output Data transfer acknowledge signal for single address transfer by DMAC channel 1. Data transfer acknowledge 0 (DMAC) DACK0 DACK0 Data transfer acknowledge signal for single address transfer by DMAC channel 0. Data transfer acknowledge 3*2 EDACK3*2 Output (EXDMAC) Data transfer acknowledge signal for single address transfer by EXDMAC channel 3. EDACK2*2 Output Data transfer acknowledge signal for single address transfer by EXDMAC channel 2. Data transfer acknowledge 2*2 (EXDMAC) Notes: 1. Not supported by the H8S/2426 Group and H8S/2424 Group 2. Not supported by the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 150 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3 Register Descriptions The bus controller has the following registers. • • • • • • • • • • • • • • • • • • Bus width control register (ABWCR) Access state control register (ASTCR) Wait control register AH (WTCRAH) Wait control register AL (WTCRAL) Wait control register BH (WTCRBH) Wait control register BL (WTCRBL) Read strobe timing control register (RDNCR) CS assertion period control register H (CSACRH) CS assertion period control register L (CSACRL) Area 0 burst ROM interface control register (BROMCRH) Area 1 burst ROM interface control register (BROMCRL) Bus control register (BCR) Address/data multiplexed I/O control register (MPXCR) DRAM control register (DRAMCR) DRAM access control register (DRACCR) Refresh control register (REFCR) Refresh timer counter (RTCNT) Refresh time constant register (RTCOR) Rev. 1.00 Sep. 19, 2008 Page 151 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3.1 Bus Width Control Register (ABWCR) ABWCR designates each area in the external address space as either 8-bit access space or 16-bit access space. Bit Bit Name Initial Value* R/W Description 7 ABW7 1/0 R/W Area 7 to 0 Bus Width Control 6 ABW6 1/0 R/W 5 ABW5 1/0 R/W 4 ABW4 1/0 R/W These bits select whether the corresponding area is to be designated as 8-bit access space or 16-bit access space. 3 ABW3 1/0 R/W 2 ABW2 1/0 R/W 1 ABW1 1/0 R/W 0 ABW0 1/0 R/W Note: 6.3.2 * 0: Area n is designated as 16-bit access space 1: Area n is designated as 8-bit access space (n = 7 to 0) In modes 2 and 4, ABWCR is initialized to 1. In modes 1 and 7, ABWCR is initialized to 0. Access State Control Register (ASTCR) ASTCR designates each area in the external address space as either 2-state access space or 3-state access space. Bit Bit Name Initial Value R/W Description 7 AST7 1 R/W Area 7 to 0 Access State Control 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W 3 AST3 1 R/W These bits select whether the corresponding area is to be designated as 2-state access space or 3-state access space. Wait state insertion is enabled or disabled at the same time. 2 AST2 1 R/W 1 AST1 1 R/W 0 AST0 1 R/W 0: Area n is designated as 2-state access space Wait state insertion in area n access is disabled 1: Area n is designated as 3-state access space Wait state insertion in area n access is enabled (n = 7 to 0) Rev. 1.00 Sep. 19, 2008 Page 152 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH, and WTCRBL) WTCRA and WTCRB select the number of program wait states for each area in the external address space. In addition, CAS latency is set when a synchronous DRAM is connected. • WTCRAH Bit Bit Name Initial Value R/W Description 15 — 0 R Reserved This bit is always read as 0 and cannot be modified. 14 W72 1 R/W Area 7 Wait Control 2 to 0 13 W71 1 R/W 12 W70 1 R/W These bits select the number of program wait states when accessing area 7 while AST7 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 11 — 0 R Reserved This bit is always read as 0 and cannot be modified. Rev. 1.00 Sep. 19, 2008 Page 153 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 W62 1 R/W Area 6 Wait Control 2 to 0 9 W61 1 R/W 8 W60 1 R/W These bits select the number of program wait states when accessing area 6 while AST6 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted Rev. 1.00 Sep. 19, 2008 Page 154 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) • WTCRAL Bit Bit Name Initial Value R/W Description 7 — 0 R Reserved This bit is always read as 0 and cannot be modified. 6 W52 1 R/W Area 5 Wait Control 2 to 0 5 W51 1 R/W 4 W50 1 R/W These bits select the number of program wait states when accessing area 5 while AST5 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 3 — 0 R Reserved This bit is always read as 0 and cannot be modified. 2 W42 1 R/W Area 4 Wait Control 2 to 0 1 W41 1 R/W 0 W40 1 R/W These bits select the number of program wait states when accessing area 4 while AST4 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted Rev. 1.00 Sep. 19, 2008 Page 155 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) • WTCRBH Bit Bit Name Initial Value R/W Description 15 — 0 R Reserved This bit is always read as 0 and cannot be modified. 14 W32 1 R/W Area 3 Wait Control 2 to 0 13 W31 1 R/W 12 W30 1 R/W These bits select the number of program wait states when accessing area 3 while AST3 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 11 — 0 R Reserved This bit is always read as 0 and cannot be modified. Rev. 1.00 Sep. 19, 2008 Page 156 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 W22 1 R/W Area 2 Wait Control 2 to 0 9 W21 1 R/W 8 W20 1 R/W These bits select the number of program wait states when accessing area 2 while AST2 bit in ASTCR = 1. A CAS latency is set when the synchronous DRAM* is connected. The setting of area 2 is reflected to the setting of areas 2 to 5. A CAS latency can be set regardless of whether or not an ASTCR wait state insertion is enabled. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 000: Synchronous DRAM of CAS latency 1 is connected to areas 2 to 5. 001: Synchronous DRAM of CAS latency 2 is connected to areas 2 to 5. 010: Synchronous DRAM of CAS latency 3 is connected to areas 2 to 5. 011: Synchronous DRAM of CAS latency 4 is connected to areas 2 to 5. 1XX: Setting prohibited. Legend: Note: * X: Don’t care. The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 157 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) • WTCRBL Bit Bit Name Initial Value R/W Description 7 — 0 R Reserved This bit is always read as 0 and cannot be modified. 6 W12 1 R/W Area 1 Wait Control 2 to 0 5 W11 1 R/W 4 W10 1 R/W These bits select the number of program wait states when accessing area 1 while AST1 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 3 — 0 R Reserved This bit is always read as 0 and cannot be modified. 2 W02 1 R/W Area 0 Wait Control 2 to 0 1 W01 1 R/W 0 W00 1 R/W These bits select the number of program wait states when accessing area 0 while AST0 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted Rev. 1.00 Sep. 19, 2008 Page 158 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3.4 Read Strobe Timing Control Register (RDNCR) RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access. Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 RDN7 RDN6 RDN5 RDN4 RDN3 RDN2 RDN1 RDN0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read Strobe Timing Control 7 to 0 These bits set the negation timing of the read strobe in a corresponding area read access. As shown in figure 6.2, the read strobe for an area for which the RDNn bit is set to 1 is negated one half-state earlier than that for an area for which the RDNn bit is cleared to 0. The read data setup and hold time specifications are also one half-state earlier. 0: In an area n read access, the RD is negated at the end of the read cycle 1: In an area n read access, the RD is negated one half-state before the end of the read cycle (n = 7 to 0) Rev. 1.00 Sep. 19, 2008 Page 159 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ RD RDNn = 0 Data RD RDNn = 1 Data Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space) Rev. 1.00 Sep. 19, 2008 Page 160 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL) CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip select signals (CSn) and address signals is to be extended. Extending the assertion period of the CSn and address signals allows flexible interfacing to external I/O devices. • CSACRH Bit Bit Name Initial Value R/W Description 7 6 CSXH7 CSXH6 CSXH5 CSXH4 CSXH3 CSXH2 CSXH1 CSXH0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W CS and Address Signal Assertion Period Control 1 These bits specify whether or not the Th cycle is to be inserted (see figure 6.3). When an area for which the CSXHn bit is set to 1 is accessed, a one-state Th cycle, in which only the CSn and address signals are asserted, is inserted before the normal access cycle. 0: In area n basic bus interface access, the CSn and address assertion period (Th) is not extended 1: In area n basic bus interface access, the CSn and address assertion period (Th) is extended (n = 7 to 0) 5 4 3 2 1 0 • CSACRL Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 CSXT7 CSXT6 CSXT5 CSXT4 CSXT3 CSXT2 CSXT1 CSXT0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W CS and Address Signal Assertion Period Control 2 These bits specify whether or not the Tt cycle shown in figure 6.3 is to be inserted. When an area for which the CSXTn bit is set to 1 is accessed, a one-state Tt cycle, in which only the CSn and address signals are asserted, is inserted after the normal access cycle. 0: In area n basic bus interface access, the CSn and address assertion period (Tt) is not extended 1: In area n basic bus interface access, the CSn and address assertion period (Tt) is extended (n = 7 to 0) Rev. 1.00 Sep. 19, 2008 Page 161 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bus cycle Th T1 T2 T3 φ Address CS RD Read Data HWR, LWR Write Data Figure 6.3 CS and Address Assertion Period Extension (Example of 3-State Access Space and RDNn = 0) Rev. 1.00 Sep. 19, 2008 Page 162 of 1270 REJ09B0466-0100 Tt Section 6 Bus Controller (BSC) 6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL) BROMCRH and BROMCRL are used to make burst ROM interface settings. Area 0 and area 1 burst ROM interface settings can be made independently in BROMCRH and BROMCRL, respectively. Bit Bit Name Initial Value R/W Description 7 BSRMn 0 R/W Burst ROM Interface Select Selects the basic bus interface or burst ROM interface. 0: Basic bus interface space 1: Burst ROM interface space 6 BSTSn2 0 R/W Burst Cycle Select 5 BSTSn1 0 R/W These bits select the number of burst cycle states. 4 BSTSn0 0 R/W 000: 1 state 001: 2 states 010: 3 states 011: 4 states 100: 5 states 101: 6 states 110: 7 states 111: 8 states 3 — 0 R/W Reserved 2 — 0 R/W These bits are always read as 0. The initial value should not be changed. 1 BSWDn1 0 R/W Burst Word Number Select 0 BSWDn0 0 R/W These bits select the number of words that can be burst-accessed on the burst ROM interface. 00: Maximum 4 words 01: Maximum 8 words 10: Maximum 16 words 11: Maximum 32 words (n = 1 or 0) Rev. 1.00 Sep. 19, 2008 Page 163 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3.7 Bus Control Register (BCR) BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT pin input. Bit Bit Name Initial Value R/W Description 15 BRLE 0 R/W External Bus Release Enable Enables or disables external bus release. 0: External bus release disabled BREQ, BACK, and BREQO pins can be used as I/O ports 1: External bus release enabled 14 BREQOE 0 R/W BREQO Pin Enable Controls outputting the bus request signal (BREQO) to the external bus master in the external bus released state, when an internal bus master performs an external address space access, or when a refresh request is generated. 0: BREQO output disabled BREQO pin can be used as I/O port 1: BREQO output enabled 13 — 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 12 IDLC 1 R/W Idle Cycle State Number Select Specifies the number of states in the idle cycle set by ICIS2, ICIS1, and ICIS0. 0: Idle cycle comprises 1 state 1: Idle cycle comprises 2 states 11 ICIS1 1 R/W Idle Cycle Insert 1 When consecutive external read cycles are executed in different areas, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted Rev. 1.00 Sep. 19, 2008 Page 164 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 ICIS0 1 R/W Idle Cycle Insert 0 When an external read cycle and external write cycle are performed consecutively, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted 9 WDBE 0 R/W Write Data Buffer Enable The write data buffer function can be used for an external write cycle or DMAC single address transfer cycle. 0: Write data buffer function not used 1: Write data buffer function used 8 WAITE 0 R/W WAIT Pin Enable Selects enabling or disabling of wait input by the WAIT pin. 0: Wait input by WAIT pin disabled WAIT pin can be used as I/O port 1: Wait input by WAIT pin enabled 7 to 3 — All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. 2 ICIS2 0 R/W Idle Cycle Insert 2 When an external write cycle and external read cycle are performed consecutively, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted 1, 0 — All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. Rev. 1.00 Sep. 19, 2008 Page 165 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3.8 Address/Data Multiplexed I/O Control Register (MPXCR) MPXCR is used to make address/data multiplexed I/O interface settings. Bit Bit Name Initial Value R/W Description 7 MPXE 0 R/W Address/Data Multiplexed I/O Interface Enable These bits select the bus interface for areas 6 and 7. 0: Basic bus interface 1: Address/data multiplexed I/O interface 6 to 1 All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. 0 ADDEX 0 R/W Address Output Cycle Extension Specifies whether a wait cycle is inserted for the address output cycle of the address/data multiplexed I/O interface. 0: No wait cycle inserted 1: One wait cycle inserted Rev. 1.00 Sep. 19, 2008 Page 166 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3.9 DRAM Control Register (DRAMCR) DRAMCR is used to make DRAM/synchronous DRAM interface settings. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. Bit Bit Name Initial Value R/W Description 15 OEE 0 R/W OE Output Enable The OE signal used when EDO page mode DRAM is connected can be output from the (OE) pin. The OE signal is common to all areas designated as DRAM space. When the synchronous DRAM is connected, the CKE signal can be output from the (OE) pin. The CKE signal is common to the continuous synchronous DRAM space. 0: OE/CKE signal output disabled (OE)/(CKE) pin can be used as I/O port 1: OE/CKE signal output enabled 14 RAST 0 R/W RAS Assertion Timing Select Selects whether, in DRAM access, the RAS signal is asserted from the start of the Tr cycle (rising edge of φ) or from the falling edge of φ. Figure 6.4 shows the relationship between the RAST bit setting and the RAS assertion timing. The setting of this bit applies to all areas designated as DRAM space. 0: RAS is asserted from φ falling edge in Tr cycle 1: RAS is asserted from start of Tr cycle 13 — 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. Rev. 1.00 Sep. 19, 2008 Page 167 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 12 CAST 0 R/W Column Address Output Cycle Number Select Selects whether the column address output cycle in DRAM access comprises 3 states or 2 states. The setting of this bit applies to all areas designated as DRAM space. 0: Column address output cycle comprises 2 states 1: Column address output cycle comprises 3 states 11 — 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. Rev. 1.00 Sep. 19, 2008 Page 168 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 RMTS2 0 R/W 9 RMTS1 0 R/W DRAM/Continuous Synchronous DRAM Space Select 8 RMTS0 0 R/W These bits designate DRAM/continuous synchronous DRAM space for areas 2 to 5. When continuous DRAM space is set, it is possible to connect large-capacity DRAM exceeding 2 Mbytes per area. In this case, the RAS signal is output from the CS2 pin. When continuous synchronous DRAM space is set, it is possible to connect large-capacity synchronous DRAM exceeding 2 Mbytes per area. In this case, the RAS, CAS, and WE signals are output from CS2, CS3, and CS4 pins, respectively. When synchronous DRAM mode is set, the mode registers of the synchronous DRAM can be set. 000: Normal space 001: Normal space in areas 3 to 5 DRAM space in area 2 010: Normal space in areas 4 and 5 DRAM space in areas 2 and 3 011: DRAM space in areas 2 to 5 100: Continuous synchronous DRAM space (setting possible only in H8S/2426R Group) 101: Synchronous DRAM mode setting (setting possible only in H8S/2426R Group) 110: Setting prohibited 111: Continuous DRAM space in areas 2 to 5 7 BE 0 R/W Burst Access Enable Selects enabling or disabling of burst access to areas designated as DRAM/continuous synchronous DRAM space. DRAM/continuous synchronous DRAM space burst access is performed in fast page mode. When using EDO page mode DRAM, the OE signal must be connected. 0: Full access 1: Access in fast page mode Rev. 1.00 Sep. 19, 2008 Page 169 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 6 RCDM 0 R/W RAS Down Mode When access to DRAM space is interrupted by an access to normal space, an access to an internal I/O register, etc., this bit selects whether the RAS signal is held low while waiting for the next DRAM access (RAS down mode), or is driven high again (RAS up mode). The setting of this bit is valid only when the BE bit is set to 1. If this bit is cleared to 0 when set to 1 in the RAS down state, the RAS down state is cleared at that point, and RAS goes high. When continuous synchronous DRAM space is set, reading from and writing to this bit is enabled. However, the setting does not affect the operation. 0: RAS up mode selected for DRAM space access 1: RAS down mode selected for DRAM space access 5 DDS 0 R/W DMAC Single Address Transfer Option Selects whether full access is always performed or burst access is enabled when DMAC single address transfer is performed on the DRAM/synchronous DRAM. When the BE bit is cleared to 0 in DRAMCR, disabling DRAM/synchronous DRAM burst access, DMAC single address transfer is performed in full access mode regardless of the setting of this bit. This bit has no effect on other bus master external accesses or DMAC dual address transfers. 0: Full access is always executed 1: Burst access is enabled Rev. 1.00 Sep. 19, 2008 Page 170 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 4 EDDS 0 R/W EXDMAC Single Address Transfer Option Selects whether full access is always performed or burst access is enabled when EXDMAC single address transfer is performed on the DRAM/synchronous DRAM. When the BE bit is cleared to 0 in DRAMCR, disabling DRAM/synchronous DRAM burst access, EXDMAC single address transfer is performed in full access mode regardless of the setting of this bit. This bit has no effect on other bus master external accesses or EXDMAC dual address transfers. 0: Full access is always executed 1: Burst access is enabled 3 — 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. Rev. 1.00 Sep. 19, 2008 Page 171 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 2 MXC2 0 R/W Address Multiplex Select 1 MXC1 0 R/W 0 MXC0 0 R/W These bits select the size of the shift toward the lower half of the row address in row address/column address multiplexing. In burst operation on the DRAM/synchronous DRAM interface, these bits also select the row address bits to be used for comparison. When the MXC2 bit is set to 1 while continuous synchronous DRAM space is set, the address precharge setting command (Precharge-sel) is output to the upper column address. For details, refer to sections 6.7.2 and 6.8.2, Address Multiplexing. DRAM interface 000: 8-bit shift • When 8-bit access space is designated: Row address bits A23 to A8 used for comparison • When 16-bit access space is designated: Row address bits A23 to A9 used for comparison 001: 9-bit shift • When 8-bit access space is designated: Row address bits A23 to A9 used for comparison • When 16-bit access space is designated: Row address bits A23 to A10 used for comparison 010: 10-bit shift • When 8-bit access space is designated: Row address bits A23 to A10 used for comparison • When 16-bit access space is designated: Row address bits A23 to A11 used for comparison Rev. 1.00 Sep. 19, 2008 Page 172 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 2 MXC2 0 R/W 011: 11-bit shift 1 MXC1 0 R/W • 0 MXC0 0 R/W When 8-bit access space is designated: Row address bits A23 to A11 used for comparison When 16-bit access space is designated: Row address bits A23 to A12 used for comparison Synchronous DRAM interface 100: 8-bit shift • When 8-bit access space is designated: Row address bits A23 to A8 used for comparison • When 16-bit access space is designated: Row address bits A23 to A9 used for comparison The precharge-sel is A15 to A9 of the column address. 101: 9-bit shift • When 8-bit access space is designated: Row address bits A23 to A9 used for comparison • When 16-bit access space is designated: Row address bits A23 to A10 used for comparison The precharge-sel is A15 to A10 of the column address. 110: 10-bit shift • When 8-bit access space is designated: Row address bits A23 to A10 used for comparison • When 16-bit access space is designated: Row address bits A23 to A11 used for comparison The precharge-sel is A15 to A11 of the column address. Rev. 1.00 Sep. 19, 2008 Page 173 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 2 MXC2 0 R/W 111: 11-bit shift 1 MXC1 0 R/W • 0 MXC0 0 R/W When 8-bit access space is designated: Row address bits A23 to A11 used for comparison • When 16-bit access space is designated: Row address bits A23 to A12 used for comparison The precharge-sel is A15 to A12 of the column address. Bus cycle Tr Tp Tc1 Tc2 φ Row address Address Column address RAST = 0 RAS RAST = 1 RAS UCAS, LCAS Figure 6.4 RAS Signal Assertion Timing (2-State Column Address Output Cycle, Full Access) Rev. 1.00 Sep. 19, 2008 Page 174 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3.10 DRAM Access Control Register (DRACCR) DRACCR is used to set the DRAM/synchronous DRAM interface bus specifications. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. Bit Bit Name Initial Value R/W Description 15 DRMI 0 R/W Idle Cycle Insertion An idle cycle can be inserted after a DRAM/synchronous DRAM access cycle when a continuous normal space access cycle follows a DRAM/synchronous DRAM access cycle. Idle cycle insertion conditions, setting of number of states, etc., comply with settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR register 0: Idle cycle not inserted 1: Idle cycle inserted 14 — 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 13 TPC1 0 R/W Precharge State Control 12 TPC0 0 R/W These bits select the number of states in the RAS precharge cycle in normal access and refreshing. 00: 1 state 01: 2 states 10: 3 states 11: 4 states 11 SDWCD 0* R/W CAS Latency Control Cycle Disabled during Continuous Synchronous DRAM Space Write Access Disables CAS latency control cycle (Tcl) inserted by WTCRB (H) settings during synchronous DRAM write access (see figure 6.5). 0: Enables CAS latency control cycle 1: Disables CAS latency control cycle Rev. 1.00 Sep. 19, 2008 Page 175 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 9 RCD1 0 R/W RAS-CAS Wait Control 8 RCD0 0 R/W These bits select a wait cycle to be inserted between the RAS assert cycle and CAS assert cycle. A 1- to 4-state wait cycle can be inserted. 00: Wait cycle not inserted 01: 1-state wait cycle inserted 10: 2-state wait cycle inserted 11: 3-state wait cycle inserted 7 to 4 All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. 3 CKSPE* 0 R/W Clock Suspend Enable Enables clock suspend mode for extend read data during DMAC and EXDMAC single address transfer with the synchronous DRAM interface. 0: Disables clock suspend mode 1: Enables clock suspend mode 2 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 1 RDXC1* 0 R/W Read Data Extension Cycle Number Selection 0 RDXC0* 0 R/W Selects the number of read data extension cycle (Tsp) insertion state in clock suspend mode. These bits are valid when the CKSPE bit is set to 1. 00: Inserts 1 state 01: Inserts 2 state 10: Inserts 3 state 11: Inserts 4 state Note: * Not supported by the H8S/2426 Group and H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 176 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Precharge-sel Column address Row address Row address RAS SDWCD 0 CAS WE CKE High DQMU, DQML Data bus Address bus PALL ACTV NOP WRIT Tp Tr Tc1 Tc2 Column address Precharge-sel Row address NOP Column address Row address RAS SDWCD 1 CAS WE CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT Figure 6.5 CAS Latency Control Cycle Disable Timing during Continuous Synchronous DRAM Space Write Access (for CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 177 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3.11 Refresh Control Register (REFCR) REFCR specifies DRAM/synchronous DRAM interface refresh control. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. Bit Bit Name Initial Value R/W Description 15 CMF 0 R/(W)* Compare Match Flag Status flag that indicates a match between the values of RTCNT and RTCOR. [Clearing conditions] • When 0 is written to CMF after reading CMF = 1 while the RFSHE bit is cleared to 0 • When CBR refreshing is executed while the RFSHE bit is set to 1 [Setting condition] When RTCOR = RTCNT 14 CMIE 0 R/W Compare Match Interrupt Enable Enables or disables interrupt requests (CMI) by the CMF flag when the CMF flag is set to 1. This bit is valid when refresh control is not performed. When the refresh control is performed, this bit is always cleared to 0 and cannot be modified. 0: Interrupt request by CMF flag disabled 1: Interrupt request by CMF flag enabled 13 RCW1 0 R/W CAS-RAS Wait Control 12 RCW0 0 R/W These bits select the number of wait cycles to be inserted between the CAS assert cycle and RAS assert cycle in a DRAM/synchronous DRAM refresh cycle. 00: Wait state not inserted 01: 1 wait state inserted 10: 2 wait states inserted 11: 3 wait states inserted Note: * Only 0 can be written, to clear the flag. Rev. 1.00 Sep. 19, 2008 Page 178 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 11 — 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 10 RTCK2 0 R/W Refresh Counter Clock Select 9 RTCK1 0 R/W 8 RTCK0 0 R/W These bits select the clock to be used to increment the refresh counter. When the input clock is selected with bits RTCK2 to RTCK0, the refresh counter begins counting up. 000: Count operation halted 001: Count on φ/2 010: Count on φ/8 011: Count on φ/32 100: Count on φ/128 101: Count on φ/512 110: Count on φ/2048 111: Count on φ/4096 7 RFSHE 0 R/W Refresh Control Refresh control can be performed. When refresh control is not performed, the refresh timer can be used as an interval timer. 0: Refresh control is not performed 1: Refresh control is performed 6 CBRM 0 R/W CBR Refresh Mode Selects CBR refreshing performed in parallel with other external accesses, or execution of CBR refreshing alone. When the continuous synchronous DRAM space is set, this bit can be read/written, but the setting contents do not affect operations. 0: External access during CAS-before-RAS refreshing is enabled 1: External access during CAS-before-RAS refreshing is disabled Rev. 1.00 Sep. 19, 2008 Page 179 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 5 RLW1 0 R/W Refresh Cycle Wait Control 4 RLW0 0 R/W These bits select the number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle/synchronous DRAM interface autorefresh cycle. This setting applies to all areas designated as DRAM/continuous synchronous DRAM space. 00: No wait state inserted 01: 1 wait state inserted 10: 2 wait states inserted 11: 3 wait states inserted 3 SLFRF 0 R/W Self-Refresh Enable If this bit is set to 1, DRAM/synchronous DRAM self-refresh mode is selected when a transition is made to the software standby state. This bit is valid when the RFSHE bit is set to 1, enabling refresh operations. It is cleared after recovery from software standby mode. 0: Self-refreshing is disabled 1: Self-refreshing is enabled 2 TPCS2 0 R/W Self-Refresh Precharge Cycle Control 1 TPCS1 0 R/W 0 TPCS0 0 R/W These bits select the number of states in the precharge cycle immediately after self-refreshing. The number of states in the precharge cycle immediately after self-refreshing are added to the number of states set by bits TPC1 and TPC0 in DRACCR. 000: [TPC set value] states 001: [TPC set value + 1] states 010: [TPC set value + 2] states 011: [TPC set value + 3] states 100: [TPC set value + 4] states 101: [TPC set value + 5] states 110: [TPC set value + 6] states 111: [TPC set value + 7] states Rev. 1.00 Sep. 19, 2008 Page 180 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3.12 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits RTCK2 to RTCK0 in REFCR. When RTCNT matches RTCOR (compare match), the CMF flag in REFCR is set to 1 and RTCNT is cleared to H'00. If the RFSHE bit in REFCR is set to 1 at this time, a refresh cycle is started. If the RFSHE bit is cleared to 0 and the CMIE bit in REFCR is set to 1, a compare match interrupt (CMI) is generated. RTCNT is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. 6.3.13 Refresh Time Constant Register (RTCOR) RTCOR is an 8-bit readable/writable register that sets the period for compare match operations with RTCNT. The values of RTCOR and RTCNT are constantly compared, and if they match, the CMF flag in REFCR is set to 1 and RTCNT is cleared to H'00. RTCOR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Rev. 1.00 Sep. 19, 2008 Page 181 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.4 Bus Control 6.4.1 Area Division The bus controller divides the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external address space in area units. Chip select signals (CS0 to CS7) can be output for each area. In normal mode, a part of area 0, 64-Kbyte address space, is controlled. Figure 6.6 shows an outline of the memory map. H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) H'FFFFFF Figure 6.6 Area Divisions Rev. 1.00 Sep. 19, 2008 Page 182 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.4.2 Bus Specifications The external address space bus specifications consist of five elements: bus width, number of access states, number of program wait states, read strobe timing, and chip select (CS) assertion period extension states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. (1) Bus Width A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a 16-bit access space. If all areas are designated as 8-bit access space, 8-bit bus mode is set; if any area is designated as 16-bit access space, 16-bit bus mode is set. (2) Number of Access States Two or three access states can be selected with ASTCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3-state access is selected functions as a 3-state access space. With the DRAM or synchronous DRAM interface and burst ROM interface, the number of access states may be determined without regard to the setting of ASTCR. When 2-state access space is designated, wait insertion is disabled. When 3-state access space is designated, it is possible to insert program waits by means of the WTCRA and WTCRB, and external waits by means of the WAIT pin. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. (3) Number of Program Wait States When 3-state access space is designated by ASTCR, the number of program wait states to be inserted automatically is selected with WTCRA and WTCRB. From 0 to 7 program wait states can be selected. Table 6.2 shows the bus specifications (bus width, and number of access states and program wait states) for each basic bus interface area. Rev. 1.00 Sep. 19, 2008 Page 183 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Table 6.2 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR ABWn ASTn Wn2 Wn1 Wn0 Bus Width Access States Program Wait States 0 0 16 2 0 1 0 0 0 3 0 WTCRA, WTCRB 1 1 0 1 1 1 1 0 2 1 3 0 4 1 5 0 6 1 7 0 1 0 0 0 1 1 0 1 Bus Specifications (Basic Bus Interface) 8 2 0 3 0 1 1 0 2 1 3 0 4 1 5 0 6 1 7 (n = 0 to 7) (4) Read Strobe Timing RDNCR can be used to select either of two negation timings (at the end of the read cycle or one half-state before the end of the read cycle) for the read strobe (RD) used in the basic bus interface space. (5) Chip Select (CS) Assertion Period Extension States Some external I/O devices require a setup time and hold time between address and CS signals and strobe signals such as RD, HWR, and LWR. CSACR can be used to insert states in which only the CS, AS, and address signals are asserted before and after a basic bus space access cycle. Rev. 1.00 Sep. 19, 2008 Page 184 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.4.3 Memory Interfaces The memory interfaces in this LSI comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; an address/data multiplexed I/O interface that allows direct connection of peripheral LSIs that require address/data multiplexing, a DRAM interface that allows direct connection of DRAM; a synchronous DRAM interface that allows direct connection of synchronous DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can be selected independently for each area. An area for which the basic bus interface is designated functions as normal space. An area for which the address/data multiplexed I/O interface is designated functions as address/data multiplexed I/O space, an area for which the DRAM interface is designated functions as DRAM space, an area for which the synchronous DRAM interface is designated functions as continuous synchronous DRAM space, and an area for which the burst ROM interface is designated functions as burst ROM space. The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. (1) Area 0 Area 0 includes on-chip ROM in expanded mode with on-chip ROM enabled and the space excluding on-chip ROM is external address space, and in expanded mode with on-chip ROM disabled, all of area 0 is external address space. When area 0 external space is accessed, the CS0 signal can be output. Either the basic bus interface or burst ROM interface can be selected for the memory interface of area 0. (2) Area 1 In externally expanded mode, all of area 1 is external address space. When area 1 external address space is accessed, the CS1 signal can be output. Either the basic bus interface or burst ROM interface can be selected for the memory interface of area 1. Rev. 1.00 Sep. 19, 2008 Page 185 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (3) Areas 2 to 5 In externally expanded mode, areas 2 to 5 are all external address space. When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output. The basic bus interface, DRAM interface, or synchronous DRAM interface can be selected for the memory interface of areas 2 to 5. With the DRAM interface, signals CS2 and CS5 are used as RAS signals. If areas 2 to 5 are designated as continuous DRAM space, large-capacity (e.g. 64-Mbit) DRAM can be connected. In this case, the CS2 signal is used as the RAS signal for the continuous DRAM space. If areas 2 to 5 are designated as continuous synchronous DRAM space, large-capacity (e.g. 64Mbit) synchronous DRAM can be connected. In this case, the CS2, CS3, CS4, and CS5 pins are used as the RAS, CAS, WE, and CLK signals for the continuous synchronous DRAM space. The OE pin is used as the CKE signal. (4) Area 6 In externally expanded mode, all of area 6 is external space. When area 6 external space is accessed, the CS6 signal can be output. Either the basic bus interface or address/data multiplexed I/O interface can be used for the memory interface of area 6. (5) Area 7 Area 7 includes the on-chip RAM and internal/O registers. In externally expanded mode, the space excluding the on-chip RAM and internal I/O registers is external address space. The on-chip RAM is enabled when the RAME bit is set to 1 in the system control register (SYSCR); when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are in external address space. When area 7 external address space is accessed, the CS7 signal can be output. Either the basic bus interface or address/data multiplexed I/O interface can be used for the memory interface of area 7. Rev. 1.00 Sep. 19, 2008 Page 186 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.4.4 Chip Select Signals This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when the corresponding external space area is accessed. Figure 6.7 shows an example of CS0 to CS7 signals output timing. Enabling or disabling of CS0 to CS7 signals output is set by the data direction register (DDR) bit for the port corresponding to the CS0 to CS7 pins. In expanded mode with on-chip ROM disabled, the CS0 pin is placed in the output state after a reset. Pins CS1 to CS7 are placed in the input state after a reset and so the corresponding DDR bits and PFCR0 bits should be set to 1 when outputting signals CS1 to CS7. In expanded mode with on-chip ROM enabled, pins CS0 to CS7 are all placed in the input state after a reset and so the corresponding DDR bits and PFCR0 bits should be set to 1 when outputting signals CS0 to CS7. When areas 2 to 5 are designated as DRAM space, outputs CS2 to CS5 are used as RAS signals. When areas 2 to 5 are designated as continuous synchronous DRAM space in the H8S/2426R Group, outputs CS2, CS3, CS4, and CS5 are used as RAS, CAS, WE, and CLK signals. Note: The A23E bit in PFCR1 should be cleared to 0 when CS7 signal is output in the H8S/2424 Group. Bus cycle T1 T2 T3 φ Address bus Area n external address CSn Figure 6.7 CSn Signal Output Timing (n = 0 to 7) Rev. 1.00 Sep. 19, 2008 Page 187 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.5 Basic Bus Interface The basic bus interface enables direct connection of ROM, SRAM, and so on. 6.5.1 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external address space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. (1) 8-Bit Access Space Figure 6.8 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. Upper data bus D15 Lower data bus D8 D7 D0 Byte size Word size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space) (2) 16-Bit Access Space Figure 6.9 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses. Rev. 1.00 Sep. 19, 2008 Page 188 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Upper data bus D15 Byte size • Even address Byte size • Odd address Lower data bus D8 D7 D0 Word size Longword size 1st bus cycle 2nd bus cycle Figure 6.9 Access Sizes and Data Alignment Control (16-Bit Access Space) 6.5.2 Valid Strobes Table 6.3 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.3 Data Buses Used and Valid Strobes Access Size Read/ Write Address Valid Strobe Upper Data Bus Lower Data (D15 to D8) Bus (D7 to D0) 8-bit access space Byte Read RD Valid Write HWR 16-bit access space Byte Read Even RD Write Even HWR Odd Read Write Area Hi-Z Valid Invalid Invalid Valid Valid Hi-Z LWR Hi-Z Valid RD Valid Valid HWR, LWR Valid Valid Odd Word Invalid Note: Hi-Z: High-impedance state Invalid: Input state; input value is ignored. Rev. 1.00 Sep. 19, 2008 Page 189 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.5.3 (1) Basic Timing 8-Bit, 2-State Access Space Figure 6.10 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high. Wait states can be inserted. Bus cycle T2 T1 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space Rev. 1.00 Sep. 19, 2008 Page 190 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (2) 8-Bit, 3-State Access Space Figure 6.11 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high. Wait states can be inserted. Bus cycle T1 T3 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR High LWR Write D15 to D8 D7 to D0 Valid High impedance Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.11 Bus Timing for 8-Bit, 3-State Access Space Rev. 1.00 Sep. 19, 2008 Page 191 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (3) 16-Bit, 2-State Access Space Figures 6.12 to 6.14 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states cannot be inserted. Bus cycle T2 T1 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access) Rev. 1.00 Sep. 19, 2008 Page 192 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write High impedance D15 to D8 D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access) Rev. 1.00 Sep. 19, 2008 Page 193 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space (Word Access) Rev. 1.00 Sep. 19, 2008 Page 194 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (4) 16-Bit, 3-State Access Space Figures 6.15 to 6.17 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states can be inserted. Bus cycle T1 T3 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access) Rev. 1.00 Sep. 19, 2008 Page 195 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 D7 to D0 High impedance Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access) Rev. 1.00 Sep. 19, 2008 Page 196 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space (Word Access) Rev. 1.00 Sep. 19, 2008 Page 197 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.5.4 Wait Control When accessing external space, this LSI can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. (1) Program Wait Insertion From 0 to 7 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings in WTCRA and WTCRB. (2) Pin Wait Insertion Setting the WAITE bit to 1 in BCR enables wait input by means of the WAIT pin. When external space is accessed in this state, a program wait is first inserted in accordance with the settings in WTCRA and WTCRB. If the WAIT pin is low at the falling edge of φ in the last T2 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. This is useful when inserting seven or more Tw states, or when changing the number of Tw states to be inserted for different external devices. The WAITE bit setting applies to all areas. Figure 6.18 shows an example of wait state insertion timing. The settings after a reset are: 3-state access, insertion of 7 program wait states, and WAIT input disabled. Rev. 1.00 Sep. 19, 2008 Page 198 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) By program wait T1 T2 Tw By WAIT pin Tw Tw T3 φ WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Notes: 1. Downward arrows indicate the timing of WAIT pin sampling. 2. When RDNn = 0 Figure 6.18 Example of Wait State Insertion Timing 6.5.5 Read Strobe (RD) Timing The read strobe (RD) timing can be changed for individual areas by setting bits RDN7 to RDN0 to 1 in RDNCR. Figure 6.19 shows an example of the timing when the read strobe timing is changed in basic bus 3-state access space. When the DMAC or EXDMAC is used in single address mode, note that if the RD timing is changed by setting RDNn to 1, the RD timing will change relative to the rise of DACK or EDACK. Rev. 1.00 Sep. 19, 2008 Page 199 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bus cycle T1 T2 φ Address bus CSn AS RD RDNn = 0 Data bus RD RDNn = 1 Data bus DACK, EDACK Figure 6.19 Example of Read Strobe Timing Rev. 1.00 Sep. 19, 2008 Page 200 of 1270 REJ09B0466-0100 T3 Section 6 Bus Controller (BSC) 6.5.6 Extension of Chip Select (CS) Assertion Period Some external I/O devices require a setup time and hold time between address and CS signals and strobe signals such as RD, HWR, and LWR. Settings can be made in the CSACR register to insert states in which only the CS, AS, and address signals are asserted before and after a basic bus space access cycle. Extension of the CS assertion period can be set for individual areas. With the CS assertion extension period in write access, the data setup and hold times are less stringent since the write data is output to the data bus. Figure 6.20 shows an example of the timing when the CS assertion period is extended in basic bus 3-state access space. Bus cycle Th T1 T2 T3 Tt φ Address bus CSn AS Read (when RDNn = 0) RD Data bus Read data HWR, LWR Write Data bus Write data Figure 6.20 Example of Timing when Chip Select Assertion Period Is Extended Rev. 1.00 Sep. 19, 2008 Page 201 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Both extension state Th inserted before the basic bus cycle and extension state Tt inserted after the basic bus cycle, or only one of these, can be specified for individual areas. Insertion or noninsertion can be specified for the Th state with the upper 8 bits (CSXH7 to CSXH0) in the CSACR register, and for the Tt state with the lower 8 bits (CSXT7 to CSXT0). 6.6 Address/Data Multiplexed I/O Interface If areas 6 and 7 of the external address space are specified as address/data multiplexed I/O space in this LSI, the address/data multiplexed I/O interfacing can be performed. In the address/data multiplexed I/O interface, peripheral LSIs that require address/data multiplexing can be connected directly to this LSI. 6.6.1 Setting Address/Data Multiplexed I/O Space In the address/data multiplexed I/O interface, areas 6 and 7 are designated as the address/data multiplexed I/O space by setting the MPXE bit in MPXCR to 1. 6.6.2 Address/Data Multiplexing With the address/data multiplexed I/O space, the data bus and address bus are multiplexed. Table 6.4 shows the relation between the bus width and corresponding address output. Table 6.4 Multiplexed Address/Data Data Pins Bus Width Cycle PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE7 8 bits Address A7 A6 A5 A4 A3 A2 A1 A0 Data D15 D14 D13 D12 D11 D10 D9 Address A15 A14 A13 A12 A11 A10 Data D15 D14 D13 D12 D11 D10 16 bits Rev. 1.00 Sep. 19, 2008 Page 202 of 1270 REJ09B0466-0100 PE6 PE5 PE4 PE3 PE2 PE1 PE0 D8 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Section 6 Bus Controller (BSC) 6.6.3 Data Bus The bus width of the address/data multiplexed I/O space can be specified for either 8-bit access space or 16-bit access space by the ABW7 and ABW6 bits in ABWCRA. For the 8-bit access space, D15 to D8 are valid for both address and data. For the 16-bit access space, D15 to D0 are valid for both address and data. If the address/data multiplexed I/O space is accessed, the corresponding address will be output to the address bus. For details on access size and data alignment, see section 6.5.1, Data Size and Data Alignment. 6.6.4 Address Hold Signal In the address/data multiplexed I/O space, a hold signal (AH) that indicates the timing for latching the address is output. The AH output pin is multiplexed with the AS output pin. When the external address space is specified as the address/data multiplexed I/O space, the multiplexed pin functions as the AH output pin. Note however that the multiplexed pin will function as the AS output pin until the address/data multiplexed I/O space is specified. 6.6.5 Basic Timing The bus cycle in the address/data multiplexed I/O interface consists of an address cycle and a data cycle. The data cycle is based on the basic bus interface timing specified by ABWCR, ASTCR, WTCRAH, RDNCR, and CSACR. Rev. 1.00 Sep. 19, 2008 Page 203 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (1) 8-Bit, 2-State Data Access Space Figure 6.21 shows the bus timing for an 8-bit, 2-state data access space. When an 8-bit access space is accessed, the upper halves (D15 to D8) of both the address bus and data bus are used. Wait states cannot be inserted in the data cycle. Address cycle Tma1 Tma2 Data cycle T1 T2 φ Address bus CSn AH RD Read D15 to D8 Read data Address HWR LWR Write D15 to D8 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Figure 6.21 Bus Timing for 8-Bit, 2-State Data Access Space Rev. 1.00 Sep. 19, 2008 Page 204 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (2) 8-Bit, 3-State Data Access Space Figure 6.22 shows the bus timing for an 8-bit, 3-state data access space. When an 8-bit access space is accessed, the upper halves (D15 to D8) of both the address bus and data bus are used. Wait states can be inserted in the data cycle. Address cycle Tma1 Tma2 Data cycle T1 T2 T3 φ Address bus CSn AH RD Read D15 to D8 Read data Address HWR Write LWR D15 to D8 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Figure 6.22 Bus Timing for 8-Bit, 3-State Data Access Space Rev. 1.00 Sep. 19, 2008 Page 205 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (3) 16-Bit, 2-State Data Access Space Figures 6.23 to 6.25 show bus timings for a 16-bit, 2-state data access space. When a 16-bit access space is accessed, the entire address bus (D15 to D0) is used for all addresses, and the upper half (D15 to D8) of the data bus is used for even addresses and the lower half (D7 to D0) of the data bus is used for odd addresses. Wait states cannot be inserted in the data cycle. Address cycle Tma1 Tma2 Data cycle T1 T2 φ Address bus CSn AH RD Read D15 to D8 Address D7 to D0 Address Read data HWR LWR Write D15 to D8 Address D7 to D0 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Figure 6.23 Bus Timing for 16-Bit, 2-State Data Access Space (Even Address Byte Access) Rev. 1.00 Sep. 19, 2008 Page 206 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Address cycle Tma1 Tma2 Data cycle T1 T2 φ Address bus CSn AH RD Read D15 to D8 Address D7 to D0 Address Read data HWR LWR Write D15 to D8 Address D7 to D0 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Figure 6.24 Bus Timing for 16-Bit, 2-State Data Access Space (Odd Address Byte Access) Rev. 1.00 Sep. 19, 2008 Page 207 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Address cycle Tma1 Tma2 Data cycle T1 T2 φ Address bus CSn AH RD Read D15 to D8 Address Read data D7 to D0 Address Read data HWR LWR Write D15 to D8 Address Write data D7 to D0 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Figure 6.25 Bus Timing for 16-Bit, 2-State Data Access Space (Word Access) Rev. 1.00 Sep. 19, 2008 Page 208 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (4) 16-Bit, 3-State Data Access Space Figures 6.26 to 6.28 show bus timings for a 16-bit, 3-state data access space. When a 16-bit access space is accessed, the entire address bus (D15 to D0) is used for all addresses, and the upper half (D15 to D8) of the data bus is used for even addresses and the lower half (D7 to D0) of the data bus is used for odd addresses. Wait states can be inserted in the data cycle. Address cycle Tma1 Tma2 Data cycle T1 T2 T3 φ Address bus CSn AH RD Read D15 to D8 Address D7 to D0 Address Read data HWR LWR Write D15 to D8 Address D7 to D0 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 1 Figure 6.26 Bus Timing for 16-Bit, 3-State Data Access Space (Even Address Byte Access) Rev. 1.00 Sep. 19, 2008 Page 209 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Address cycle Tma1 Tma2 Data cycle T1 T2 T3 φ Address bus CSn AH RD Read D15 to D8 Address D7 to D0 Address Read data HWR LWR Write D15 to D8 Address D7 to D0 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 1 Figure 6.27 Bus Timing for 16-Bit, 3-State Data Access Space (Odd Address Byte Access) Rev. 1.00 Sep. 19, 2008 Page 210 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Address cycle Tma1 Tma2 Data cycle T1 T2 T3 φ Address bus CSn AH RD Read D15 to D8 Address Read data D7 to D0 Address Read data HWR LWR Write D15 to D8 Address Write data D7 to D0 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 1 Figure 6.28 Bus Timing for 16-Bit, 3-State Data Access Space (Word Access) Rev. 1.00 Sep. 19, 2008 Page 211 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.6.6 (1) Wait Control Address Cycle A single address wait cycle Tmaw can be inserted between Tma1 and Tma2 cycles by setting the ADDEX bit in MPXCR to 1. Figure 6.29 shows the access timing when the address cycle is three cycles. Address cycle Tma1 Tmaw Data cycle Tma2 T1 T2 φ Address bus CSn AH RD Read D15 to D8 Address D7 to D0 Address Read data HWR LWR Write D15 to D8 Address D7 to D0 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Figure 6.29 Example of Access Timing with Address Wait Rev. 1.00 Sep. 19, 2008 Page 212 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (2) Data Cycle In the data cycle, program wait insertion and pin wait insertion by the WAIT pin are enabled in the same way as in the basic bus interface. For details, refer to section 6.5.4, Wait Control. Wait control settings do not affect the address cycles. 6.6.7 Read Strobe (RD) Timing In the address/data multiplexed I/O interface, the read strobe timing of data cycles can be modified in the same way as in the basic bus interface. For details, refer to section 6.5.5, Read Strobe (RD) Timing. Figure 6.30 shows an example when the read strobe timing is modified. Address cycle Tma1 Tma2 Data cycle T1 T2 φ Address bus CSn AH RD RDNn = 0 D15 to D8 Read data Address RD RDNn = 1 D15 to D8 Read data Address Note: n = 6, 7 Figure 6.30 Example of Read Strobe Timing Rev. 1.00 Sep. 19, 2008 Page 213 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.6.8 Extension of Chip Select (CS) Assertion Period in Data Cycle In the address/data multiplexed I/O interface, extension cycles can be inserted before and after the data cycle. For details, see section 6.5.6, Extension of Chip Select (CS) Assertion Period. Figure 6.31 shows an example of the timing when the chip select assertion period is extended in the data cycle. Address cycle Tma1 Tma2 Data cycle Th T1 T2 Tt φ Address bus CSn AH RD Read D15 to D8 Address Read data D7 to D0 Address Read data HWR LWR Write D15 to D8 Address Write data D7 to D0 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Figure 6.31 Example of Timing when Chip Select Assertion Period Is Extended in Data Cycle Rev. 1.00 Sep. 19, 2008 Page 214 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) When consecutively reading from the same area connected to a peripheral LSI whose output floating time is long, data outputs from the peripheral LSI may conflict with address outputs from this LSI. The data conflict can be avoided by inserting the CS assertion period extension cycle after the access cycle. Figure 6.32 shows an example of the operation. In the figure, both bus cycles A and B are read access cycles to the same area which is address/data multiplexed I/O space. (a) shows an example of conflict occurring between data outputs from the peripheral LSI whose output floating time is long and address outputs from this LSI because the CS assertion period extension cycle is not inserted. (b) shows an example of the data conflict being avoided by inserting the CS assertion period extension cycle. Bus cycle A Bus cycle B Bus cycle A φ φ Address bus Address bus CS CS WR WR RD RD Data bus Data bus Bus cycle B Data conflict Output floating time is long (a) Without CS assertion period extension cycle (CSXTn = 0) (b) With CS assertion period extension cycle (CSXTn = 1) Figure 6.32 Consecutive Read Accesses to Same Area (Address/Data Multiplexed I/O Space) Rev. 1.00 Sep. 19, 2008 Page 215 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.7 DRAM Interface In this LSI, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Burst operation is also possible, using fast page mode. 6.7.1 Setting DRAM Space Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR. The relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6.5. Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), four areas (areas 2 to 5), and continuous area (areas 2 to 5). Table 6.5 Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2 0 0 1 Normal space Normal space Normal space DRAM space 1 0 Normal space Normal space DRAM space DRAM space 1 DRAM space DRAM space DRAM space DRAM space 0 Continuous synchronous DRAM space* 1 0 1 Note: * 1 Mode register settings of synchronous DRAM* 0 Reserved (setting prohibited) 1 Continuous DRAM space Continuous DRAM space Continuous DRAM space Continuous DRAM space Reserved (setting prohibited) in the H8S/2426 Group and H8S/2424 Group. With continuous DRAM space, RAS2 is valid. The bus specifications (bus width, number of wait states, etc.) for continuous DRAM space conform to the settings for area 2. 6.7.2 Address Multiplexing With DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. Table 6.6 shows the relation between the settings of MXC2 to MXC0 and the shift size. The MXC2 bit should be cleared to 0 when the DRAM interface is used. Rev. 1.00 Sep. 19, 2008 Page 216 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Table 6.6 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing DRAMCR Address Pins A23 Row MXC2 MXC1 MXC0 0 0 0 Shift to Size A16 A15 A14 A13 A12 A11 A10 A9 8 bits address A8 A7 A6 A5 A4 A3 A2 A23 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A1 A0 A9 A8 A23 A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 to A16 1 9 bits to A16 1 0 10 bits A23 A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 to A16 1 11 bits A23 A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 to A16 Column 1 × × 0 × × address Reserved (setting prohibited) A23 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 to A16 1 × × Reserved (setting prohibited) Legend: ×: Don’t care. 6.7.3 Data Bus If a bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM space. In 16-bit DRAM space, ×16-bit configuration DRAM can be connected directly. In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM space both the upper and lower halves of the data bus, D15 to D0, are enabled. Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data Size and Data Alignment. Rev. 1.00 Sep. 19, 2008 Page 217 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.7.4 Pins Used for DRAM Interface Table 6.7 shows the pins used for DRAM interfacing and their functions. Since the CS2 to CS5 pins are in the input state after a reset, set the corresponding DDR to 1 when RAS2 to RAS5 signals are output. Table 6.7 DRAM Interface Pins Pin With DRAM Setting Name I/O Function HWR WE Write enable Output Write enable for DRAM space access CS2 RAS2/RAS Row address strobe 2/ row address strobe Output Row address strobe when area 2 is designated as DRAM space or row address strobe when areas 2 to 5 are designated as continuous DRAM space CS3 RAS3 Row address strobe 3 Output Row address strobe when area 3 is designated as DRAM space CS4 RAS4 Row address strobe 4 Output Row address strobe when area 4 is designated as DRAM space CS5 RAS5 Row address strobe 5 Output Row address strobe when area 5 is designated as DRAM space UCAS UCAS Upper column address strobe Output Upper column address strobe for 16-bit DRAM space access or column address strobe for 8-bit DRAM space access LCAS LCAS Lower column address strobe Output Lower column address strobe signal for 16-bit DRAM space access RD, OE OE Output enable Output Output enable signal for DRAM space access WAIT WAIT Wait Input Wait request signal A15 to A0 A15 to A0 Address pins Output Row address/column address multiplexed output D15 to D0 D15 to D0 Data pins I/O Data input/output pins Rev. 1.00 Sep. 19, 2008 Page 218 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.7.5 Basic Timing Figure 6.33 shows the basic access timing for DRAM space. The four states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address output cycle) state, and the Tc1 and two Tc2 (column address output cycle) states. Tp Tr Tc1 Tc2 φ Address bus Row address Column address RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus Note: n = 2 to 5 Figure 6.33 DRAM Basic Access Timing (RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 219 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) When DRAM space is accessed, the RD signal is output as the OE signal for DRAM. When connecting DRAM provided with an EDO page mode, the OE signal should be connected to the (OE) pin of the DRAM. Setting the OEE bit to 1 in DRAMCR enables the OE signal for DRAM space to be output from a dedicated OE pin. In this case, the OE signal for DRAM space is output from both the RD pin and the (OE) pin, but in external read cycles for other than DRAM space, the signal is output only from the RD pin. Rev. 1.00 Sep. 19, 2008 Page 220 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.7.6 Column Address Output Cycle Control The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit to 1 in DRAMCR. Use the setting that gives the optimum specification values (CAS pulse width, etc.) according to the DRAM connected and the operating frequency of this LSI. Figure 6.34 shows an example of the timing when a 3-state column address output cycle is selected. Tp Tr Tc1 Tc2 Tc3 φ Address bus Row address Column address RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus Note: n = 2 to 5 Figure 6.34 Example of Access Timing with 3-State Column Address Output Cycle (RAST = 0) Rev. 1.00 Sep. 19, 2008 Page 221 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.7.7 Row Address Output State Control If the RAST bit is set to 1 in DRAMCR, the RAS signal goes low from the beginning of the Tr state, and the row address hold time and DRAM read access time are changed relative to the fall of the RAS signal. Use the optimum setting according to the DRAM connected and the operating frequency of this LSI. Figure 6.35 shows an example of the timing when the RAS signal goes low from the beginning of the Tr state. Tp Tr Tc1 Tc2 φ Address bus Row address Column address RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus Note: n = 2 to 5 Figure 6.35 Example of Access Timing when RAS Signal Goes Low from Beginning of Tr State (CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 222 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) If a row address hold time or read access time is necessary, making a setting in bits RCD1 and RCD0 in DRACCR allows from one to three Trw states, in which row address output is maintained, to be inserted between the Tr cycle, in which the RAS signal goes low, and the Tc1 cycle, in which the column address is output. Use the setting that gives the optimum row address signal hold time relative to the falling edge of the RAS signal according to the DRAM connected and the operating frequency of this LSI. Figure 6.36 shows an example of the timing when one Trw state is set. Tp Tr Trw Tc1 Tc2 φ Address bus Row address Column address RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus Note: n = 2 to 5 Figure 6.36 Example of Timing with One Row Address Output Maintenance State (RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 223 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.7.8 Precharge State Control When DRAM is accessed, a RAS precharge time must be secured. With this LSI, one Tp state is always inserted when DRAM space is accessed. From one to four Tp states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of Tp cycles according to the DRAM connected and the operating frequency of this LSI. Figure 6.37 shows the timing when two Tp states are inserted. The setting of bits TPC1 and TPC0 is also valid for Tp states in refresh cycles. Tp1 Tp2 Tr Tc1 Tc2 φ Address bus Row address Column address RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus Note: n = 2 to 5 Figure 6.37 Example of Timing with Two-State Precharge Cycle (RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 224 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.7.9 Wait Control There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. Wait states are inserted to extend the CAS assertion period in a read access to DRAM space, and to extend the write data setup time relative to the falling edge of CAS in a write access. (1) Program Wait Insertion When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from 0 to 7 wait states can be inserted automatically between the Tc1 state and Tc2 state, according to the settings in WTCR. (2) Pin Wait Insertion When the WAITE bit in BCR is set to 1 and the ASTCR bit is set to 1, wait input by means of the WAIT pin is enabled. When DRAM space is accessed in this state, a program wait (Tw) is first inserted. If the WAIT pin is low at the falling edge of φ in the last Tc1 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. Figures 6.38 and 6.39 show examples of wait cycle insertion timing in the case of 2-state and 3state column address output cycles. Rev. 1.00 Sep. 19, 2008 Page 225 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) By program wait Tp Tr Tc1 Tw By WAIT pin Tw φ WAIT Address bus Row address Column address RASn (CSn) UCAS, LCAS Read WE (HWR) High OE (RD) Data bus UCAS, LCAS Write WE (HWR) OE (RD) High Data bus Note: Downward arrows indicate the timing of WAIT pin sampling. n = 2 to 5 Figure 6.38 Example of Wait State Insertion Timing (2-State Column Address Output) Rev. 1.00 Sep. 19, 2008 Page 226 of 1270 REJ09B0466-0100 Tc2 Section 6 Bus Controller (BSC) Tp Tr By program wait By WAIT pin Tc1 Tw Tw Tc2 Tc3 φ WAIT Address bus Row address Column address RASn (CSn) UCAS, LCAS Read WE (HWR) High OE (RD) Data bus UCAS, LCAS Write WE (HWR) OE (RD) High Data bus Note: Downward arrows indicate the timing of WAIT pin sampling. n = 2 to 5 Figure 6.39 Example of Wait State Insertion Timing (3-State Column Address Output) Rev. 1.00 Sep. 19, 2008 Page 227 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.7.10 Byte Access Control When DRAM with a ×16-bit configuration is connected, the 2-CAS access method is used for the control signals needed for byte access. Figure 6.40 shows the control timing for 2-CAS access, and figure 6.41 shows an example of 2-CAS DRAM connection. Tp Tr Tc1 Tc2 φ Address bus Row address Column address RASn (CSn) UCAS LCAS High WE (HWR) OE (RD) High Write data Upper data bus High-Z Lower data bus Note: n = 2 to 5 Figure 6.40 2-CAS Control Timing (Upper Byte Write Access: RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 228 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 2-CAS type 16-Mbit DRAM 1-Mbyte × 16-bit configuration 10-bit column address This LSI (Address shift size set to 10 bits) RASn (CSn) RAS UCAS UCAS LCAS LCAS HWR (WE) RD (OE) A10 WE OE A9 A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 D15 to D0 Row address input: A9 to A0 Column address input: A9 to A0 D15 to D0 Figure 6.41 Example of 2-CAS DRAM Connection 6.7.11 Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit to 1 in DRAMCR. (1) Burst Access (Fast Page Mode) Figures 6.42 and 6.43 show the operation timing for burst access. When there are consecutive access cycles for DRAM space, the CAS signal and column address output cycles (two states) continue as long as the row address is the same for consecutive access cycles. The row address used for the comparison is set with bits MXC2 to MXC0 in DRAMCR. Rev. 1.00 Sep. 19, 2008 Page 229 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tc2 Tc1 Tc2 φ Address bus Row address Column address 1 Column address 2 RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus Note: n = 2 to 5 Figure 6.42 Operation Timing in Fast Page Mode (RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 230 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3 φ Address bus Row address Column address 1 Column address 2 RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus Note: n = 2 to 5 Figure 6.43 Operation Timing in Fast Page Mode (RAST = 0, CAST = 1) The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion method and timing are the same as for full access. For details see section 6.7.9, Wait Control. (2) RAS Down Mode and RAS Up Mode Even when burst operation is selected, it may happen that access to DRAM space is not continuous, but is interrupted by access to another space. In this case, if the RAS signal is held low during the access to the other space, burst operation can be resumed when the same row address in DRAM space is accessed again. • RAS Down Mode To select RAS down mode, set both the RCDM bit and the BE bit to 1 in DRAMCR. If access to DRAM space is interrupted and another space is accessed, the RAS signal is held low during the access to the other space, and burst access is performed when the row address of the next DRAM space access is the same as the row address of the previous DRAM space access. Figure 6.44 shows an example of the timing in RAS down mode. Rev. 1.00 Sep. 19, 2008 Page 231 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Note, however, that the RAS signal will go high if: a refresh operation is initiated in the RAS down state self-refreshing is performed the chip enters software standby mode the external bus is released the RCDM bit or BE bit is cleared to 0 If a transition is made to the all-module-clocks-stopped mode in the RAS down state, the clock will stop with RAS low. To enter the all-module-clocks-stopped mode with RAS high, the RCDM bit must be cleared to 0 before executing the SLEEP instruction. DRAM space read Tp Tr Tc1 Tc2 Normal space read DRAM space read T1 Tc1 T2 Tc2 φ Row address Address bus Column address 1 External address Column address 2 RASn (CSn) UCAS, LCAS RD OE Data bus Note: n = 2 to 5 Figure 6.44 Example of Operation Timing in RAS Down Mode (RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 232 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) • RAS Up Mode To select RAS up mode, clear the RCDM bit to 0 in DRAMCR. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed if DRAM space is continuous. Figure 6.45 shows an example of the timing in RAS up mode. DRAM space read Tp Tr Tc1 Tc2 DRAM space read Normal space read Tc1 T1 Tc2 T2 φ Address bus Row address Column address 1 Column address 2 External address RASn (CSn) UCAS, LCAS RD OE Data bus Note: n = 2 to 5 Figure 6.45 Example of Operation Timing in RAS Up Mode (RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 233 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.7.12 Refresh Control This LSI is provided with a DRAM refresh control function. CAS-before-RAS (CBR) refreshing is used. In addition, self-refreshing can be executed when the chip enters the software standby state. Refresh control is enabled when any area is designated as DRAM space in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR. (1) CAS-before-RAS (CBR) Refreshing To select CBR refreshing, set the RFSHE bit to 1 in REFCR. With CBR refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0 in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control is performed. At the same time, RTCNT is reset and starts counting up again from H'00. Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0. Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval specification for the DRAM used. When bits RTCK2 to RTCK0 in REFCR are set, RTCNT starts counting up. RTCNT and RTCOR settings should therefore be completed before setting bits RTCK2 to RTCK0. RTCNT operation is shown in figure 6.46, compare match timing in figure 6.47, and CBR refresh timing in figure 6.48. When the CBRM bit in REFCR is cleared to 0, access to external space other than DRAM space is performed in parallel during the CBR refresh period. RTCNT RTCOR H'00 Refresh request Figure 6.46 RTCNT Operation Rev. 1.00 Sep. 19, 2008 Page 234 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) φ RTCNT N H'00 RTCOR N Refresh request signal and CMF bit setting signal Figure 6.47 Compare Match Timing TRp TRr TRc1 TRc2 φ CSn (RASn) UCAS, LCAS Figure 6.48 CBR Refresh Timing Rev. 1.00 Sep. 19, 2008 Page 235 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) A setting can be made in bits RCW1 and RCW0 in REFCR to delay RAS signal output by one to three cycles. Use bits RLW1 and RLW0 in REFCR to adjust the width of the RAS signal. The settings of bits RCW1, RCW0, RLW1, and RLW0 are valid only in refresh operations. Figure 6.49 shows the timing when bits RCW1 and RCW0 are set. TRp TRrw TRr TRc1 φ CSn (RASn) UCAS, CAS Figure 6.49 CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0) Rev. 1.00 Sep. 19, 2008 Page 236 of 1270 REJ09B0466-0100 TRc2 Section 6 Bus Controller (BSC) Depending on the DRAM used, modification of the WE signal may not be permitted during the refresh period. In this case, the CBRM bit in REFCR should be set to 1. The bus controller will then insert refresh cycles in appropriate breaks between bus cycles. Figure 6.50 shows an example of the timing when the CBRM bit is set to 1. In this case the CS signal is not controlled, and retains its value prior to the start of the refresh period. Normal space access request φ A23 to A0 CS AS RD HWR (WE) Refresh period RAS CAS Figure 6.50 Example of CBR Refresh Timing (CBRM = 1) Rev. 1.00 Sep. 19, 2008 Page 237 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (2) Self-Refreshing A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. To select self-refreshing, set the RFSHE bit and SLFRF bit to 1 in REFCR. When a SLEEP instruction is executed to enter software standby mode, the CAS and RAS signals are output and DRAM enters self-refresh mode, as shown in figure 6.51. When software standby mode is exited, the SLFRF bit is cleared to 0 and self-refresh mode is exited automatically. If a CBR refresh request occurs when making a transition to software standby mode, CBR refreshing is executed, and then self-refresh mode is entered. When using self-refresh mode, the OPE bit must not be cleared to 0 in the SBYCR register. TRp Software standby TRr φ CSn (RASn) UCAS, LCAS HWR (WE) High Note: n = 2 to 5 Figure 6.51 Self-Refresh Timing Rev. 1.00 Sep. 19, 2008 Page 238 of 1270 REJ09B0466-0100 TRc3 Section 6 Bus Controller (BSC) In some DRAMs provided with a self-refresh mode, the RAS signal precharge time immediately after self-refreshing is longer than the normal precharge time. A setting can be made in bits TPCS2 to TPCS0 in REFCR to make the precharge time immediately after self-refreshing from 1 to 7 states longer than the normal precharge time. In this case, too, normal precharging is performed according to the setting of bits TPC1 and TPC0 in DRACCR, and therefore a setting should be made to give the optimum post-self-refresh precharge time, including this time. Figure 6.52 shows an example of the timing when the precharge time immediately after self-refreshing is extended by 2 states. Software standby DRAM space write TRc3 TRp1 TRp2 Tp Tr Tc1 Tc2 φ Address bus RASn (CSn) UCAS, LCAS OE (RD) WR (HWR) Data bus Note: n = 2 to 5 Figure 6.52 Example of Timing when Precharge Time after Self-Refreshing Is Extended by 2 States Rev. 1.00 Sep. 19, 2008 Page 239 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (3) Refreshing and All-Module-Clocks-Stopped Mode In this LSI, if the ACSE bit is set to 1 in MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered, in which the bus controller and I/O port clocks are also stopped. As the bus controller clock is also stopped in this mode, CBR refreshing is not executed. If DRAM is connected externally and DRAM data is to be retained in sleep mode, the ACSE bit must be cleared to 0 in MSTPCRH. 6.7.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface When burst mode is selected on the DRAM interface, the DACK and EDACK output timing can be selected with the DDS and EDDS bits in DRAMCR. When DRAM space is accessed in DMAC or EXDMAC single address mode at the same time, these bits select whether or not burst access is to be performed. (1) When DDS = 1 or EDDS = 1 Burst access is performed by determining the address only, irrespective of the bus master. With the DRAM interface, the DACK or EDACK output goes low from the Tc1 state. Figure 6.53 shows the DACK or EDACK output timing for the DRAM interface when DDS = 1 or EDDS = 1. Rev. 1.00 Sep. 19, 2008 Page 240 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tc2 φ Address bus Row address Column address RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus DACK or EDACK Note: n = 2 to 5 Figure 6.53 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1 (RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 241 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (2) When DDS = 0 or EDDS = 0 When DRAM space is accessed in DMAC or EXDMAC single address transfer mode, full access (normal access) is always performed. With the DRAM interface, the DACK or EDACK output goes low from the Tr state. In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used when accessing DRAM space. Figure 6.54 shows the DACK or EDACK output timing for the DRAM interface when DDS = 0 or EDDS = 0. Tp Tr Tc1 Tc2 Tc3 φ Address bus Row address Column address RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus DACK or EDACK Note: n = 2 to 5 Figure 6.54 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0 (RAST = 0, CAST = 1) Rev. 1.00 Sep. 19, 2008 Page 242 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8 Synchronous DRAM Interface In the H8S/2426R Group, external address space areas 2 to 5 can be designated as continuous synchronous DRAM space, and synchronous DRAM interfacing performed. The synchronous DRAM interface allows synchronous DRAM to be directly connected to this LSI. A synchronous DRAM space of up to 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Synchronous DRAM of CAS latency 1 to 4 can be connected. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. 6.8.1 Setting Continuous Synchronous DRAM Space Areas 2 to 5 are designated as continuous synchronous DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR. The relation between the settings of bits RMTS2 to RMTS0 and synchronous DRAM space is shown in table 6.8. Possible synchronous DRAM interface settings are and continuous area (areas 2 to 5). Table 6.8 Relation between Settings of Bits RMTS2 to RMTS0 and Synchronous DRAM Space RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2 0 0 1 Normal space Normal space Normal space DRAM space 1 0 Normal space Normal space DRAM space DRAM space 1 DRAM space DRAM space DRAM space DRAM space 0 Continuous synchronous DRAM space 1 Mode settings of synchronous DRAM 0 Reserved (setting prohibited) 1 Continuous DRAM space 1 0 1 With continuous synchronous DRAM space, CS2, CS3, CS4 pins are used as RAS, CAS, WE signal. The (OE) pin of the synchronous DRAM is used as the CKE signal, and the CS5 pin is used as synchronous DRAM clock (SDRAMφ). The bus specifications for continuous synchronous DRAM space conform to the settings for area 2. The pin wait and program wait for the continuous synchronous DRAM are invalid. Commands for the synchronous DRAM can be specified by combining RAS, CAS, WE, and address-precharge-setting command (Precharge-sel) output on the upper column addresses. Rev. 1.00 Sep. 19, 2008 Page 243 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Commands that are supported by this LSI are NOP, auto-refresh (REF), self-refresh (SELF), all bank precharge (PALL), row address strobe bank-active (ACTV), read (READ), write (WRIT), and mode-register write (MRS). Commands for bank control cannot be used. 6.8.2 Address Multiplexing With continuous synchronous DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. The address-precharge-setting command (Precharge-sel) can be output on the upper column address. Table 6.9 shows the relation between the settings of MXC2 to MXC0 and the shift size. The MXC2 bit should be set to 1 when the synchronous DRAM interface is used. Table 6.9 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing DRAMCR MXC2 Row address MXC1 MXC0 A23 to A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 × × 1 0 0 8 bits A23 to A16 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 1 9 bits A23 to A16 A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 0 10 bits A23 to A16 A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 1 11 bits A23 to A16 A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 1 Column address Address Pins Shift Size Reserved (setting prohibited) 0 × × 1 0 0 A23 to A16 P P P P P P P A8 A7 A6 A5 A4 A3 A2 A1 A0 1 A23 to A16 P P P P P P A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 A23 to A16 P P P P P A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 A23 to A16 P P P P A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 Reserved (setting prohibited) Legend: ×: Don’t care. P: Precharge-sel Rev. 1.00 Sep. 19, 2008 Page 244 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8.3 Data Bus If the ABW2 bit in ABWCR corresponding to an area designated as continuous synchronous DRAM space is set to 1, areas 2 to 5 are designated as 8-bit continuous synchronous DRAM space; if the bit is cleared to 0, the areas are designated as 16-bit continuous synchronous DRAM space. In 16-bit continuous synchronous DRAM space, ×16-bit configuration synchronous DRAM can be connected directly. In 8-bit continuous synchronous DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit continuous synchronous DRAM space both the upper and lower halves of the data bus, D15 to D0, are enabled. Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data Size and Data Alignment. 6.8.4 Pins Used for Synchronous DRAM Interface Table 6.10 shows pins used for the synchronous DRAM interface and their functions. Since the CS2 to CS4 pins are in the input state after a reset, set DDR to 1 when RAS, CAS, and WE signals are output. For details, see section 10, I/O Ports. Set the OEE bit of the DRAMCR register to 1 when the CKE signal is output. Rev. 1.00 Sep. 19, 2008 Page 245 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Table 6.10 Synchronous DRAM Interface Pins Pin With Synchronous DRAM Setting Name I/O Function CS2 RAS Row address strobe Output Row address strobe when areas 2 to 5 are designated as continuous synchronous DRAM space CS3 CAS Column address strobe Output Column address strobe when areas 2 to 5 are designated as continuous synchronous DRAM space CS4 WE Write enable Output Write enable strobe when areas 2 to 5 are designated as continuous synchronous DRAM space CS5 SDRAMφ Clock Output Clock only for synchronous DRAM (OE) (CKE) Clock enable Output Clock enable signal when areas 2 to 5 are designated as continuous synchronous DRAM space UCAS DQMU Upper data mask enable Output Upper data mask enable for 16-bit continuous synchronous DRAM space access/data mask enable for 8-bit continuous synchronous DRAM space access LCAS DQML Lower data mask enable Output Lower data mask enable signal for 16-bit continuous synchronous DRAM space access A15 to A0 A15 to A0 Address pins Output Row address/column address multiplexed output pins D15 to D0 D15 to D0 Data pins I/O Data input/output pins Rev. 1.00 Sep. 19, 2008 Page 246 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8.5 Synchronous DRAM Clock The synchronous clock (SDRAMφ) is output from the CS5 pin. SDRAMφ is shifted by 90° phase from φ. Therefore, a stable margin is ensured for the synchronous DRAM that operates at the rising edge of clocks. Figure 6.55 shows the relationship between φ and SDRAMφ. Tcyc φ 1/4 Tcyc (90°) SDRAMφ Figure 6.55 Relationship between φ and SDRAMφ 6.8.6 Basic Timing The four states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address output cycle) state, and the Tc1 and two Tc2 (column address output cycle) states. When areas 2 to 5 are set for the continuous synchronous DRAM space, settings of the WAITE bit of BCR, RAST, CAST, RCDM bits of DRAMCR, and the CBRM bit of REFCR are ignored. Figure 6.56 shows the basic timing for synchronous DRAM. Rev. 1.00 Sep. 19, 2008 Page 247 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Tp Tr Column address Row address Tc1 Tc2 φ SDRAMφ Address bus Precharge-sel Column address Row address RAS CAS WE Read CKE High DQMU, DQML Data bus PALL ACTV READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT Figure 6.56 Basic Access Timing of Synchronous DRAM (CAS Latency 1) Rev. 1.00 Sep. 19, 2008 Page 248 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8.7 CAS Latency Control CAS latency is controlled by settings of the W22 to W20 bits of WTCRB. Set the CAS latency count, as shown in table 6.11, by the setting of synchronous DRAM. Depending on the setting, the CAS latency control cycle (Tc1) is inserted. WTCRB can be set regardless of the setting of the AST2 bit of ASTCR. Figure 6.57 shows the CAS latency control timing when synchronous DRAM of CAS latency 3 is connected. The initial value of W22 to W20 is H'7. Set the register according to the CAS latency of synchronous DRAM to be connected. Table 6.11 Setting CAS Latency CAS Latency Control Cycle Inserted W22 W21 W20 Description 0 0 0 Connect synchronous DRAM of CAS latency 1 0 state 1 Connect synchronous DRAM of CAS latency 2 1 state 0 Connect synchronous DRAM of CAS latency 3 2 states 1 Connect synchronous DRAM of CAS latency 4 3 states 0 Reserved (must not be used) 1 Reserved (must not be used) 0 Reserved (must not be used) 1 Reserved (must not be used) 1 1 0 1 Rev. 1.00 Sep. 19, 2008 Page 249 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl1 Tcl2 Tc2 φ SDRAMφ Address bus Column address Row address Precharge-sel Row address Column address RAS CAS WE Read CKE High DQMU, DQML Data bus PALL ACTV READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP Figure 6.57 CAS Latency Control Timing (SDWCD = 0, CAS Latency 3) Rev. 1.00 Sep. 19, 2008 Page 250 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8.8 Row Address Output State Control When the command interval specification from the ACTV command to the next READ/WRIT command cannot be satisfied, 1 to 3 states (Trw) that output the NOP command can be inserted between the Tr cycle that outputs the ACTV command and the Tc1 cycle that outputs the column address by setting the RCD1 and RCD0 bits of DRACCR. Use the optimum setting for the wait time according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.58 shows an example of the timing when the one Trw state is set. Tp Tr Trw Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Row address Column address Row address Precharge-sel RAS CAS Read WE CKE High DQMU, DQML Data bus PALL ACTV NOP READ NOP RAS CAS Write WE CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP Figure 6.58 Example of Access Timing when Row Address Output Hold State Is 1 State (RCD1 = 0, RCD0 = 1, SDWCD = 0, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 251 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8.9 Precharge State Count When the interval specification from the PALL command to the next ACTV/REF command cannot be satisfied, from one to four Tp states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of Tp cycles according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.59 shows the timing when two Tp states are inserted. Rev. 1.00 Sep. 19, 2008 Page 252 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) The setting of bits TPC1 and TPC0 is also valid for Tp states in refresh cycles. Tp1 Tp2 Tr Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Row address Column address Row address Precharge-sel RAS CAS Read WE CKE High DQMU, DQML Data bus PALL NOP ACTV READ NOP RAS CAS Write WE CKE High DQMU, DQML Data bus PALL NOP ACTV NOP WRIT NOP Figure 6.59 Example of Timing with Two-State Precharge Cycle (TPC1 = 0, TPC0 = 1, SDWCD = 0, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 253 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8.10 Bus Cycle Control in Write Cycle By setting the SDWCD bit of the DRACCR to 1, the CAS latency control cycle (Tc1) that is inserted by the WTCRB register in the write access of the synchronous DRAM can be disabled. Disabling the CAS latency control cycle can reduce the write-access cycle count as compared to synchronous DRAM read access. Figure 6.60 shows the write access timing when the CAS latency control cycle is disabled. Tp Tr Column address Row address Tc1 Tc2 φ SDRAMφ Address bus Precharge-sel Column address Row address RAS CAS WE CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT Figure 6.60 Example of Write Access Timing when CAS Latency Control Cycle Is Disabled (SDWCD = 1) Rev. 1.00 Sep. 19, 2008 Page 254 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8.11 Byte Access Control When synchronous DRAM with a ×16-bit configuration is connected, DQMU and DQML are used for the control signals needed for byte access. Figures 6.61 and 6.62 show the control timing for DQM, and figure 6.63 shows an example of connection of byte control by DQMU and DQML. Tp Tr Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Row address Precharge-sel Row address Column address RAS CAS WE CKE High DQMU DQML High Upper data bus Lower data bus High impedance PALL ACTV NOP WRIT NOP Figure 6.61 DQMU and DQML Control Timing (Upper Byte Write Access: SDWCD = 0, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 255 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Row address Precharge-sel Row address Column address RAS CAS WE CKE High DQMU High DQML Upper data bus High impedance Lower data bus PALL ACTV READ NOP Figure 6.62 DQMU and DQML Control Timing (Lower Byte Read Access: CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 256 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) This LSI (Address shift size set to 8 bits) CS2 (RAS) RAS CS3 (CAS) CAS CS4 (WE) UCAS (DQMU) LCAS (DQML) CS5 (SDRAMφ) A23 WE DQMU DQML CLK A13 (BS1) A21 A12 (BS0) A12 A11 A11 A10 A10 A9 A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 D15 to D0 DCTL 16-Mbit synchronous DRAM 1 Mword × 16 bits × 4-bank configuration 8-bit column address OE (CKE) I/O PORT Row address input: A11 to A0 Column address input: A7 to A0 Bank select address: A13/A12 DQ15 to DQ0 CKE CS Notes: 1. Bank control is not available. 2. The CKE and CS pins must be fixed to 1 when the power supply is input. 3. The CS pin must be fixed to 0 before accessing synchronous DRAM. Figure 6.63 Example of DQMU and DQML Byte Control Rev. 1.00 Sep. 19, 2008 Page 257 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8.12 Burst Operation With synchronous DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, burst access is also provided which can be used when making consecutive accesses to the same row address. This access enables fast access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit to 1 in DRAMCR. DQM has the 2-cycle latency when synchronous DRAM is read. Therefore, the DQM signal cannot be specified to the Tc2 cycle data output if the Tc1 cycle is executed for second or following column address when the CAS latency is set to 1 to issue the READ command. Do not set the BE bit to 1 when synchronous DRAM of CAS latency 1 is connected. (1) Burst Access Operation Timing Figure 6.64 shows the operation timing for burst access. When there are consecutive access cycles for continuous synchronous DRAM space, the column address output cycles continue as long as the row address is the same for consecutive access cycles. The row address used for the comparison is set with bits MXC2 to MXC0 in DRAMCR. Rev. 1.00 Sep. 19, 2008 Page 258 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Tp Tr Column address 1 Row address Tc1 Tcl Tc2 Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Column address 2 Row address Precharge-sel RAS CAS Read WE CKE High DQMU, DQML Data bus PALL ACTV READ NOP READ NOP RAS CAS Write WE CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP WRIT NOP Figure 6.64 Operation Timing of Burst Access (BE = 1, SDWCD = 0, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 259 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (2) RAS Down Mode Even when burst operation is selected, it may happen that access to continuous synchronous DRAM space is not continuous, but is interrupted by access to another space. In this case, if the row address active state is held during the access to the other space, the read or write command can be issued without ACTV command generation similarly to DRAM RAS down mode. To select RAS down mode, set the BE bit to 1 in DRAMCR regardless of the RCDM bit settings. The operation corresponding to DRAM RAS up mode is not supported by this LSI. Figure 6.65 shows an example of the timing in RAS down mode. Note, however, the next continuous synchronous DRAM space access is a full access if: • • • • • • a refresh operation is initiated in the RAS down state self-refreshing is performed the chip enters software standby mode the external bus is released the BE bit is cleared to 0 the mode register of the synchronous DRAM is set There is synchronous DRAM in which time of the active state of each bank is restricted. If it is not guaranteed that other row address are accessed in a period in which program execution ensures the value (software standby, sleep, etc.), auto refresh or self refresh must be set, and the restrictions of the maximum active state time of each bank must be satisfied. When refresh is not used, programs must be developed so that the bank is not in the active state for more than the specified time. Rev. 1.00 Sep. 19, 2008 Page 260 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Tp Tr Tc1 Tcl External space read Tc2 T1 T2 Continuous synchronous DRAM space read Tc1 Tcl Tc2 φ Address bus Column Row address address Precharge-sel Row address Column address External address Column address 2 External address RAS CAS WE CKE High DQMU, DQML Data bus PALL ACTV READ NOP READ NOP Figure 6.65 Example of Operation Timing in RAS Down Mode (BE = 1, CAS Latency 2) 6.8.13 Refresh Control This LSI is provided with a synchronous DRAM refresh control function. Auto refreshing is used. In addition, self-refreshing can be executed when the chip enters the software standby state. Refresh control is enabled when any area is designated as continuous synchronous DRAM space in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR. Rev. 1.00 Sep. 19, 2008 Page 261 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (1) Auto Refreshing To select auto refreshing, set the RFSHE bit to 1 in REFCR. With auto refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0 in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control is performed. At the same time, RTCNT is reset and starts counting up again from H'00. Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0. Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval specification for the synchronous DRAM used. When bits RTCK2 to RTCK0 are set, RTCNT starts counting up. RTCNT and RTCOR settings should therefore be completed before setting bits RTCK2 to RTCK0. Auto refresh timing is shown in figure 6.66. Since the refresh counter operation is the same as the operation in the DRAM interface, see section 6.7.12, Refresh Control. When the continuous synchronous DRAM space is set, access to external address space other than continuous synchronous DRAM space cannot be performed in parallel during the auto refresh period, since the setting of the CBRM bit of REFCR is ignored. Rev. 1.00 Sep. 19, 2008 Page 262 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) TRp TRr TRc1 TRc2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE CKE High PALL REF NOP Figure 6.66 Auto Refresh Timing When the interval specification from the PALL command to the REF command cannot be satisfied, setting the RCW1 and RCW0 bits of REFCR enables one to three wait states to be inserted after the TRp cycle that is set by the TPC1 and TPC0 bits of DRACCR. Set the optimum number of waits according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.67 shows the timing when one wait state is inserted. Since the setting of bits TPC1 and TPC0 of DRACCR is also valid in refresh cycles, the command interval can be extended by the RCW1 and RCW0 bits after the precharge cycles. Rev. 1.00 Sep. 19, 2008 Page 263 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) TRp1 TRp2 TRrw TRr TRc1 TRc2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE CKE High PALL NOP REF NOP Figure 6.67 Auto Refresh Timing (TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1) When the interval specification from the REF command to the ACTV cannot be satisfied, setting the RLW1 and RLW0 bits of REFCR enables one to three wait states to be inserted in the refresh cycle. Set the optimum number of waits according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.68 shows the timing when one wait state is inserted. Rev. 1.00 Sep. 19, 2008 Page 264 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) TRp TRr TRr1 TRcw TRc2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE CKE High PALL REF NOP Figure 6.68 Auto Refresh Timing (TPC = 0, TPC0 = 0, RLW1 = 0, RLW0 = 1) (2) Self-Refreshing A self-refresh mode (battery backup mode) is provided for synchronous DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the synchronous DRAM. To select self-refreshing, set the RFSHE bit to 1 in REFCR. When a SLEEP instruction is executed to enter software standby mode, the SELF command is issued, as shown in figure 6.69. When software standby mode is exited, the SLFRF bit in REFCR is cleared to 0 and self-refresh mode is exited automatically. If an auto refresh request occurs when making a transition to software standby mode, auto refreshing is executed, and then self-refresh mode is entered. When using self-refresh mode, the OPE bit must not be cleared to 0 in SBYCR. Rev. 1.00 Sep. 19, 2008 Page 265 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) TRp TRr PALL SELF Software standby TRc2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE CKE NOP Figure 6.69 Self-Refresh Timing (TPC1 = 1, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW1 = 0, RLW0 = 0) In some synchronous DRAMs provided with a self-refresh mode, the interval between clearing self-refreshing and the next command is specified. A setting can be made in bits TPCS2 to TPCS0 in REFCR to make the precharge time after self-refreshing from 1 to 7 states longer than the normal precharge time. In this case, too, normal precharging is performed according to the setting of bits TPC1 and TPC0 in DRACCR, and therefore a setting should be made to give the optimum post-self-refresh precharge time, including this time. Figure 6.70 shows an example of the timing when the precharge time after self-refreshing is extended by 2 states. Rev. 1.00 Sep. 19, 2008 Page 266 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Continuous synchronous DRAM space write Software standby TRc2 TRp1 TRp2 Tp Tr Column address Row address Tc1 Tcl Tc2 φ SDRAMφ Address bus Precharge-sel Column address Row address RAS CAS WE CKE DQMU, DQML Data bus NOP PALL ACTV NOP NOP NOP Figure 6.70 Example of Timing when Precharge Time after Self-Refreshing Is Extended by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2) (3) Refreshing and All-Module-Clocks-Stopped Mode In this LSI, if the ACSE bit is set to 1 in MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered, in which the bus controller and I/O port clocks are also stopped. As the bus controller clock is also stopped in this mode, auto refreshing is not executed. If synchronous DRAM is connected to the external address space and DRAM data is to be retained in sleep mode, the ACSE bit must be cleared to 0 in MSTPCR. (4) Software Standby When a transition is made to normal software standby, the PALL command is not output. If synchronous DRAM is connected and DRAM data is to be retained in software standby, selfrefreshing must be set. Rev. 1.00 Sep. 19, 2008 Page 267 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8.14 Mode Register Setting of Synchronous DRAM To use synchronous DRAM, mode must be set after power-on. To set mode, set the RMTS2 to RMTS0 bits in DRAMCR to H'5 and enable the synchronous DRAM mode register setting. After that, access the continuous synchronous DRAM space in bytes. When the value to be set in the synchronous DRAM mode register is X, value X is set in the synchronous DRAM mode register by writing to the continuous synchronous DRAM space of address H'400000 + X for 8-bit bus configuration synchronous DRAM and by writing to the continuous synchronous DRAM space of address H'400000 + 2X for 16-bit bus configuration synchronous DRAM. The value of the address signal is fetched at the issuance time of the MRS command as the setting value of the mode register in the synchronous DRAM. Mode of burst read/burst write in the synchronous DRAM is not supported by this LSI. For setting the mode register of the synchronous DRAM, set the burst read/single write with the burst length of 1. Figure 6.71 shows the setting timing of the mode in the synchronous DRAM. Tp Tr Tc1 Tc2 φ SDRAMφ Address bus Mode setting value Mode setting value Precharge-sel RAS CAS WE CKE High PALL NOP MRS NOP Figure 6.71 Synchronous DRAM Mode Setting Timing Rev. 1.00 Sep. 19, 2008 Page 268 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8.15 DMAC and EXDMAC Single Address Transfer Mode and Synchronous DRAM Interface When burst mode is selected on the synchronous DRAM interface, the DACK and EDACK output timing can be selected with the DDS and EDDS bits in DRAMCR. When continuous synchronous DRAM space is accessed in DMAC/EXDMAC single address mode at the same time, these bits select whether or not burst access is to be performed. The establishment time for the read data can be extended in the clock suspend mode irrespective of the settings of the DDS and EDDS bits. (1) Output Timing of DACK or EDACK When DDS = 1 or EDDS = 1: Burst access is performed by determining the address only, irrespective of the bus master. With the synchronous DRAM interface, the DACK or EDACK output goes low from the Tc1 state. Figure 6.72 shows the DACK or EDACK output timing for the synchronous DRAM interface when DDS = 1 or EDDS = 1. Rev. 1.00 Sep. 19, 2008 Page 269 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Tp Tr Column address Row address Tc1 Tcl Tc2 φ SDRAMφ Address bus Precharge-sel Column address Row address RAS CAS WE Read CKE High DQMU, DQML Data bus PALL ACTV READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP DACK or EDACK Figure 6.72 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1 Rev. 1.00 Sep. 19, 2008 Page 270 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) When DDS = 0 or EDDS = 0: When continuous synchronous DRAM space is accessed in DMAC or EXDMAC single address transfer mode, full access (normal access) is always performed. With the synchronous DRAM interface, the DACK or EDACK output goes low from the Tr state. In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used when accessing continuous synchronous DRAM space. Figure 6.73 shows the DACK or EDACK output timing for connecting the synchronous DRAM interface when DDS = 0 or EDDS = 0. Rev. 1.00 Sep. 19, 2008 Page 271 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Row address Precharge-sel Row address Column address RAS CAS WE Read CKE High DQMU, DQML Data bus PALL ACTV READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP DACK or RDACK Figure 6.73 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0 Rev. 1.00 Sep. 19, 2008 Page 272 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (2) Read Data Extension If the CKSPE bit is set to 1 in DRACCR when the continuous synchronous DRAM space is readaccessed in DMAC/EXDMAC single address mode, the establishment time for the read data can be extended by clock suspend mode. The number of states for insertion of the read data extension cycle (Tsp) is set in bits RDXC1 and RDXC0 in DRACCR. Be sure to set the OEE bit to 1 in DRAMCR when the read data will be extended. The extension of the read data is not in accordance with the bits DDS and EDDS. Figure 6.74 shows the timing chart when the read data is extended by two cycles. Tp Tr Tc1 Tcl Tc2 Tsp1 Tsp2 φ SDRAMφ Address bus Row Column address address Precharge-sel Row address Column address RAS CAS WE CKE DQMU, DQML Data bus DACK or EDACK PALL ACTV READ NOP Figure 6.74 Example of Timing when the Read Data Is Extended by Two States (DDS = 1, or EDDS = 1, RDXC1 = 0, RDXC0 = 1, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 273 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.9 Burst ROM Interface In this LSI, external address space areas 0 and 1 can be designated as burst ROM space, and burst ROM interfacing performed. The burst ROM space enables ROM with burst access capability to be accessed at high speed. Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in BROMCR. Continuous burst accesses of 4, 8, 16, or 32 words can be performed, according to the setting of the BSWD11 and BSWD10 bits in BROMCR. From 1 to 8 states can be selected for burst access. Settings can be made independently for area 0 and area 1. In burst ROM space, burst access covers only CPU read accesses. 6.9.1 Basic Timing The number of access states in the initial cycle (full access) on the burst ROM interface is determined by the basic bus interface settings in ASTCR, ABWCR, WTCRA, WTCRB, and CSACRH. When area 0 or area 1 is designated as burst ROM space, the settings in RDNCR and CSACRL are ignored. From 1 to 8 states can be selected for the burst cycle, according to the settings of bits BSTS02 to BSTS00 and BSTS12 to BSTS10 in BROMCR. Wait states cannot be inserted. Burst access of up to 32 words is performed, according to the settings of bits BSTS01, BSTS00, BSTS11, and BSTS10 in BROMCR. The basic access timing for burst ROM space is shown in figures 6.75 and 6.76. Rev. 1.00 Sep. 19, 2008 Page 274 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Full access T1 T2 Burst access T3 T1 T2 T1 T2 φ Upper address bus Lower address bus CSn AS RD Data bus Note: n = 1 and 0 Figure 6.75 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle) Rev. 1.00 Sep. 19, 2008 Page 275 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Full access T1 T2 Burst access T1 T1 φ Upper address bus Lower address bus CSn AS RD Data bus Note: n = 1 and 0 Figure 6.76 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle) 6.9.2 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) on the burst ROM interface. See section 6.5.4, Wait Control. Wait states cannot be inserted in a burst cycle. 6.9.3 Write Access When a write access to burst ROM space is executed, burst access is interrupted at that point and the write access is executed in line with the basic bus interface settings. Write accesses are not performed in burst mode even though burst ROM space is designated. Rev. 1.00 Sep. 19, 2008 Page 276 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.10 Idle Cycle 6.10.1 Operation When this LSI accesses external address space, it can insert an idle cycle (Ti) between bus cycles in the following three cases: (1) when read accesses in different areas occur consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs immediately after a write cycle. Insertion of a 1-state or 2-state idle cycle can be selected with the IDLC bit in BCR. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, etc., with a long output floating time, and high-speed memory, I/O interfaces, and so on. (1) Consecutive Reads in Different Areas If consecutive reads in different areas occur while the ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle. Figure 6.77 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A T1 T2 T3 Bus cycle B T1 Bus cycle A T2 T1 φ φ Address bus Address bus CS (area A) CS (area A) CS (area B) CS (area B) RD RD Data bus Data bus Long output floating time (a) No idle cycle insertion (ICIS1 = 0) T2 T3 Data collision Bus cycle B Ti T1 T2 Idle cycle (b) Idle cycle insertion (ICIS1 = 1, initial value) Figure 6.77 Example of Idle Cycle Operation (Consecutive Reads in Different Areas) Rev. 1.00 Sep. 19, 2008 Page 277 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (2) Write after Read If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.78 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A T1 T2 T3 Bus cycle B T1 Bus cycle A T1 T2 φ φ Address bus Address bus CS (area A) CS (area A) CS (area B) CS (area B) RD RD HWR HWR Data bus Data bus Long output floating time (a) No idle cycle insertion (ICIS0 = 0) Data collision T2 T3 Bus cycle B Ti T1 Idle cycle (b) Idle cycle insertion (ICIS0 = 1, initial value) Figure 6.78 Example of Idle Cycle Operation (Write after Read) Rev. 1.00 Sep. 19, 2008 Page 278 of 1270 REJ09B0466-0100 T2 Section 6 Bus Controller (BSC) (3) Read after Write If an external read occurs after an external write while the ICIS2 bit is set to 1 in BCR, an idle cycle is inserted at the start of the read cycle. Figure 6.79 shows an example of the operation in this case. In this example, bus cycle A is a CPU write cycle and bus cycle B is a read cycle from an external device. In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the CPU write data and read data from an external device. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A T1 T2 T3 Bus cycle B T1 Bus cycle A T2 T1 φ φ Address bus Address bus CS (area A) CS (area A) CS (area B) CS (area B) RD RD HWR, LWR HWR Data bus Data bus Long output floating time (a) No idle cycle insertion (ICIS2 = 0) Data collision T2 T3 Bus cycle B Ti T1 T2 Idle cycle (b) Idle cycle insertion (ICIS2 = 1, initial value) Figure 6.79 Example of Idle Cycle Operation (Read after Write) Rev. 1.00 Sep. 19, 2008 Page 279 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (4) Relationship between Chip Select (CS) Signal and Read (RD) Signal Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6.80. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the initial state after reset release, idle cycle insertion (b) is set. Bus cycle A T1 T2 T3 Bus cycle B T1 Bus cycle A T1 T2 φ φ Address bus Address bus CS (area A) CS (area A) CS (area B) CS (area B) RD RD Overlap period between CS (area B) and RD may occur (a) No idle cycle insertion (ICIS1 = 0) T2 T3 Bus cycle B Ti T1 Idle cycle (b) Idle cycle insertion (ICIS1 = 1, initial value) Figure 6.80 Relationship between Chip Select (CS) and Read (RD) Rev. 1.00 Sep. 19, 2008 Page 280 of 1270 REJ09B0466-0100 T2 Section 6 Bus Controller (BSC) (5) Idle Cycle in Case of DRAM Space Access after Normal Space Access In a DRAM space access following a normal space access, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in different areas, for example, if the second read is a full access to DRAM space, only a Tp cycle is inserted, and a Ti cycle is not. The timing in this case is shown in figure 6.81. External read T1 T2 T3 DRAM space read Tp Tr Tc1 Tc2 φ Address bus RD Data bus Figure 6.81 Example of DRAM Full Access after External Read (CAST = 0) In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid and an idle cycle is inserted. The timing in this case is illustrated in figures 6.82 and 6.83. Rev. 1.00 Sep. 19, 2008 Page 281 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) DRAM space read Tp Tr Tc1 External read Tc2 T1 T2 T3 DRAM space read Ti Tc1 Tc2 φ Address bus RD RAS UCAS, LCAS Data bus Idle cycle Figure 6.82 Example of Idle Cycle Operation in RAS Down Mode (Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) External read DRAM space read Tp Tr Tc1 Tc2 T1 T2 T3 DRAM space write Ti Tc1 Tc2 φ Address bus RD HWR RAS UCAS, LCAS Data bus Idle cycle Figure 6.83 Example of Idle Cycle Operation in RAS Down Mode (Write after Read) (IDLC = 0, RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 282 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (6) Idle Cycle in Case of Continuous Synchronous DRAM Space Access after Normal Space Access In a continuous synchronous DRAM space access following a normal space access, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in different areas, for example, if the second read is a full access to continuous synchronous DRAM space, only Tp cycle is inserted, and Ti cycle is not. The timing in this case is shown in figure 6.84. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. External space read T1 T2 T3 Synchronous DRAM space read Tp Tr Tc1 Tcl Tc2 φ Address bus Row Column address address Precharge-sel Row address Column address RAS CAS WE CKE DQMU, DQML RD Data bus NOP PALL ACTV READ NOP Figure 6.84 Example of Synchronous DRAM Full Access after External Read (CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 283 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid and an idle cycle is inserted. However, in read access, note that the timings of DQMU and DQML differ according to the settings of the IDLC bit. The timing in this case is illustrated in figures 6.85 and 6.86. In write access, DQMU and DQML are not in accordance with the settings of the IDLC bit. The timing in this case is illustrated in figure 6.87. Continuous synchronous DRAM space read Tp Tr Tc1 Tcl External space read Tc2 T1 T2 T3 Continuous synchronous DRAM space read Ti Tc1 TCl φ Address bus Row Column address address Precharge-sel Row address Column address 1 External address Column address 2 External address RAS CAS WE CKE High DQMU, DQML RD HWR, LWR High Data bus PALL ACTV READ NOP READ Idle cycle Figure 6.85 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area) (IDLC = 0, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 284 of 1270 REJ09B0466-0100 NOP Tc2 Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Tp Tr Tc1 Tcl Continuous synchronous DRAM space read External space read Tc2 T1 T2 T3 Ti Ti Tc1 TCl Tc2 φ Address bus Row Column address address Precharge-sel Row address Column address 1 External address Column address 2 External address RAS CAS WE CKE High DQMU, DQML RD HWR, LWR High Data bus PALL ACTV READ NOP READ NOP Idle cycle Figure 6.86 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area) (IDLC = 1, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 285 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Tp Tr Tc1 Tcl External space read Tc2 T1 T2 T3 Continuous synchronous DRAM space write Ti Tc1 Tc2 TCl φ Address bus Row Column address address Precharge-sel Row address Column address 1 External address Column address 2 External address RAS CAS WE CKE High DQMU, DQML RD HWR, LWR High Data bus PALL ACTV READ NOP WRIT Idle cycle Figure 6.87 Example of Idle Cycle Operation in RAS Down Mode (Write after Read) (IDLC = 0, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 286 of 1270 REJ09B0466-0100 NOP Section 6 Bus Controller (BSC) (7) Idle Cycle in Case of Normal Space Access after DRAM Space Access (a) Normal space access after DRAM space read access While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access is disabled. Idle cycle insertion after DRAM space access can be enabled by setting the DRMI bit to 1. The conditions and number of states of the idle cycle to be inserted are in accordance with the settings of bits ICIS1, ICIS0, and IDLC in BCR are valid. Figures 6.88 and 6.89 show examples of idle cycle operation when the DRMI bit is set to 1. When the DRMI bit is cleared to 0, an idle cycle is not inserted after DRAM space access even if bits ICIS1 and ICIS0 are set to 1. DRAM space read Tp Tr Tc1 External address space read Tc2 Ti T1 T2 T3 DRAM space read Ti Tc1 Tc2 φ Address bus RD RAS UCAS, LCAS Data bus Idle cycle Figure 6.88 Example of Idle Cycle Operation after DRAM Access (Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 287 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) DRAM space read Tp Tr Tc1 External address space write DRAM space read Tc2 Ti T1 T2 T3 Tc1 Tc2 φ Address bus RD HWR, LWR RAS UCAS, LCAS Data bus Idle cycle Figure 6.89 Example of Idle Cycle Operation after DRAM Access (Write after Read) (IDLC = 0, RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 288 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (b) Normal space access after DRAM space write access While the ICIS2 bit is set to 1 in BCR and a normal space read access occurs after DRAM space write access, idle cycle is inserted in the first read cycle. The number of states of the idle cycle to be inserted is in accordance with the setting of the IDLC bit. It does not depend on the DRMI bit in DRACCR. Figure 6.90 shows an example of idle cycle operation when the ICIS2 bit is set to 1. External space read DRAM space read Tp Tr Tc1 Tc2 Ti T1 T2 DRAM space read T3 Tc1 Tc2 φ Address bus RD HWR, LWR RAS UCAS, LCAS Data bus Idle cycle Figure 6.90 Example of Idle Cycle Operation after DRAM Write Access (IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0) (8) Idle Cycle in Case of Normal Space Access after Continuous Synchronous DRAM Space Access: Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 289 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (a) Normal space access after a continuous synchronous DRAM space read access While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after continuous synchronous DRAM space read access is disabled. Idle cycle insertion after continuous synchronous DRAM space read access can be enabled by setting the DRMI bit to 1. The conditions and number of states of the idle cycle to be inserted are in accordance with the settings of bits ICIS1, ICIS0, and IDLC in RCR. Figure 6.91 shows an example of idle cycle operation when the DRMI bit is set to 1. When the DRMI bit is cleared to 0, an idle cycle is not inserted after continuous synchronous DRAM space read access even if bits ICIS1 and ICIS0 are set to 1. Continuous synchronous DRAM space read Tp Tr Tc1 Tcl Continuous synchronous DRAM space read External space read Tc2 Ti T1 T2 T3 Ti Tc1 TCl Tc2 φ Address bus Row Column address address Precharge-sel Row address Column address 1 External address Column address 2 External address RAS CAS WE CKE High DQMU, DQML RD Data bus PALL ACTV READ NOP READ NOP Idle cycle Figure 6.91 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 290 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (b) Normal space access after a continuous synchronous DRAM space write access If a normal space read cycle occurs after a continuous synchronous DRAM space write access while the ICIS2 bit is set to 1 in BCR, idle cycle is inserted at the start of the read cycle. The number of states of the idle cycle to be inserted is in accordance with the setting of bit IDLC. It is not in accordance with the DRMI bit in DRACCR. Figure 6.92 shows an example of idle cycle operation when the ICIS2 bit is set to 1. Continuous synchronous DRAM space write φ Tp Tr Address bus Row Column address address Precharge-sel Row address Tc1 Tc2 Synchronous External address space read DRAM space read Ti Column address T1 T2 External address T3 Tc1 TCl Tc2 Column address 2 External address RAS CAS WE CKE High DQMU, DQML RD HWR, LWR Data bus PALL ACTV NOP WRIT NOP READ NOP Idle cycle Figure 6.92 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 291 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Table 6.12 shows whether there is an idle cycle insertion or not in the case of mixed accesses to normal space and DRAM space/continuous synchronous DRAM space. Table 6.12 Idle Cycles in Mixed Accesses to Normal Space and DRAM Continuous Synchronous DRAM Space Previous Access Next Access ICIS2 ICIS1 ICIS0 DRMI IDLC Idle cycle Normal space read Normal space read (different area) 0 Disabled 1 0 1 state inserted 1 2 states inserted DRAM*/continuous synchronous DRAM space read 0 Disabled 1 Normal space write DRAM*/continuous synchronous DRAM space write DRAM/continuous synchronous DRAM* space read Normal space read DRAM*/continuous synchronous DRAM space read Normal space write DRAM*/continuous synchronous DRAM space write Rev. 1.00 Sep. 19, 2008 Page 292 of 1270 REJ09B0466-0100 0 1 0 1 0 1 0 1 0 1 0 1 0 1 state inserted 1 2 states inserted Disabled 0 1 state inserted 1 2 states inserted Disabled 0 1 state inserted 1 2 states inserted Disabled 0 Disabled 1 0 1 state inserted 1 2 states inserted Disabled 0 Disabled 1 0 1 state inserted 1 2 states inserted Disabled 0 Disabled 1 0 1 state inserted 1 2 states inserted Disabled 0 Disabled 1 0 1 state inserted 1 2 states inserted Section 6 Bus Controller (BSC) Previous Access Next Access ICIS2 ICIS1 ICIS0 DRMI IDLC Idle cycle Normal space write Normal space read 0 Disabled 1 0 1 state inserted 1 2 states inserted DRAM/continuous synchronous DRAM* space write DRAM*/continuous synchronous DRAM space read 0 Disabled 1 0 1 state inserted 1 2 states inserted Normal space read 0 Disabled 1 0 1 state inserted 1 2 states inserted DRAM*/continuous synchronous DRAM space read Note: * 0 Disabled 1 0 1 state inserted 1 2 states inserted Not supported by the H8S/2426 Group and H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 293 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Setting the DRMI bit in DRACCR to 1 enables an idle cycle to be inserted in the case of consecutive read and write operations in DRAM/continuous synchronous DRAM space burst access. Figures 6.93 and 6.94 show an example of the timing for idle cycle insertion in the case of consecutive read and write accesses to DRAM/continuous synchronous DRAM space. DRAM space read φ Tp Tr Tc1 DRAM space write Tc2 Ti Tc1 Tc2 Address bus RASn (CSn) UCAS, LCAS WE (HWR) OE (RD) Data bus Note: n = 2 to 5 Idle cycle Figure 6.93 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to DRAM Space in RAS Down Mode Rev. 1.00 Sep. 19, 2008 Page 294 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Tp Tr Tc1 Tcl Continuous synchronous DRAM space write Tc2 Ti Tc1 Tc2 φ Address bus Column Row address address Precharge-sel Row address Column address External address RAS CAS WE CKE High DQMU, DQML Data bus PALL ACTV READ NOP WRIT Idle cycle Figure 6.94 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to Continuous Synchronous DRAM Space in RAS Down Mode (SDWCD = 1, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 295 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.10.2 Pin States in Idle Cycle Table 6.13 shows the pin states in an idle cycle. Table 6.13 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of following bus cycle D15 to D0 High impedance CSn (n = 7 to 0) High*1 *2 UCAS, LCAS High*2 AS/AH High RD High OE High HWR, LWR High DACKn (n = 1, 0) High EDACKn (n = 3 to 0) High Notes: 1. Remains low in DRAM space RAS down mode. 2. Remains low in a DRAM space refresh cycle. Rev. 1.00 Sep. 19, 2008 Page 296 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.11 Write Data Buffer Function This LSI has a write data buffer function for the external data bus. Using the write data buffer function enables external writes and DMA single address mode transfers to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit to 1 in BCR. Figure 6.95 shows an example of the timing when the write data buffer function is used. When this function is used, if an external address space write or DMA single address mode transfer continues for two states or longer, and there is an internal access next, an external write only is executed in the first state, but from the next state onward an internal access (on-chip memory or internal I/O register read/write) is executed in parallel with the external address space write rather than waiting until it ends. On-chip memory read Internal I/O register read External write cycle T1 T2 TW TW T3 φ Internal address bus Internal memory Internal I/O register address Internal read signal A23 to A0 External address CSn External space write HWR, LWR D15 to D0 Figure 6.95 Example of Timing when Write Data Buffer Function Is Used Rev. 1.00 Sep. 19, 2008 Page 297 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.12 Bus Release This LSI can release the external bus in response to a bus request from an external device. In the external bus released state, internal bus masters except the EXDMAC* continue to operate as long as there is no external access. If any of the following requests are issued in the external bus released state, the BREQO signal can be driven low to output a bus request externally. • When an internal bus master wants to perform an external access • When a refresh request is generated • When a SLEEP instruction is executed to place the chip in software standby mode or allmodule-clocks-stopped mode Note: * Not supported by the H8S/2424 Group. 6.12.1 Operation In externally expanded mode, the bus can be released to an external device by setting the BRLE bit to 1 in BCR. Driving the BREQ pin low issues an external bus request to this LSI. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus released state. In the external bus released state, internal bus masters except the EXDMAC can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers initiation of the bus cycle, and waits for the bus request from the external bus master to be canceled. If a refresh request is generated in the external bus released state, or if a SLEEP instruction is executed to place the chip in software standby mode or all-module-clocksstopped mode, refresh control and software standby or all-module-clocks-stopped control is deferred until the bus request from the external bus master is canceled. If the BREQOE bit is set to 1 in BCR, the BREQO pin can be driven low when any of the following requests are issued, to request cancellation of the bus request externally. • When an internal bus master wants to perform an external access • When a refresh request is generated • When a SLEEP instruction is executed to place the chip in software standby mode or allmodule-clocks-stopped mode Rev. 1.00 Sep. 19, 2008 Page 298 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the external bus released state is terminated. If an external bus release request and external access occur simultaneously, the order of priority is as follows: (High) External bus release > External access by internal bus master (Low) If a refresh request and external bus release request occur simultaneously, the order of priority is as follows: (High) Refresh > External bus release (Low) 6.12.2 Pin States in External Bus Released State Table 6.14 shows pin states in the external bus released state. Table 6.14 Pin States in Bus Released State Pins Pin State A23 to A0 High impedance D15 to D0 High impedance CSn (n = 7 to 0) High impedance UCAS, LCAS High impedance AS/AH High impedance RD High impedance OE High impedance HWR, LWR High impedance DACKn (n = 1, 0) High EDACKn (n = 3, 2) High Rev. 1.00 Sep. 19, 2008 Page 299 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.12.3 Transition Timing Figure 6.96 shows the timing for transition to the bus released state. External space access cycle CPU cycle External bus released state T1 T2 φ High impedance Address bus High impedance Data bus High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK BREQO [1] [2] [3] [4] [5] [6] [1] Low level of BREQ signal is sampled at rise of φ. [2] Bus control signal returns to be high at end of external space access cycle. At least one state from sampling of BREQ signal. [3] BACK signal is driven low, releasing bus to external bus master. [4] BREQ signal state is also sampled in external bus released state. [5] High level of BREQ signal is sampled. [6] BACK signal is driven high, ending external bus release cycle. [7] When there is external access or refresh request of internal bus master during external bus release while BREQOE bit is set to 1, BREQO signal goes low. [8] Normally BREQO signal goes high 1.5 states after rising edge of BACK signal. Figure 6.96 Bus Released State Transition Timing Rev. 1.00 Sep. 19, 2008 Page 300 of 1270 REJ09B0466-0100 [7] [8] Section 6 Bus Controller (BSC) Figure 6.97 shows the timing for transition to the bus released state with the synchronous DRAM interface. External space read CPU cycle External bus released state T2 T1 φ SDRAMφ High impedance Address bus High impedance Data bus Row address Precharge-sel High impedance High impedance RAS High impedance CAS High impedance WE High impedance CKE High impedance DQMU, DQML BREQ BACK BREQO NOP PALL [1] [2] NOP [3] NOP [4] [5] [8] [6] [7] [9] [1] Low level of BREQ signal is sampled at rise of φ. [2] PALL command is issued. [3] Bus control signal returns to be high at end of external space access cycle. At least one state from sampling of BREQ signal. [4] BACK signal is driven low, releasing bus to external bus master.. [5] BREQ signal state is also sampled in external bus released state. [6] High level of BREQ signal is sampled. [7] BACK signal is driven high, ending external bus release cycle. [8] When there is external access or refresh request of internal bus master during external bus release while the BREQOE bit is set to 1, BREQO signal goes low. [9] BREQO signal goes high 1.5 states after rising edge of BACK signal. If BREQO signal is asserted because of auto-refreshing request, it retains low until auto-refresh cycle starts up. Figure 6.97 Bus Release State Transition Timing when Synchronous DRAM Interface Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 301 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.13 Bus Arbitration This LSI has a bus arbiter that arbitrates bus mastership operations (bus arbitration). There are four bus mastersthe CPU, DTC, DMAC, and EXDMAC*that perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation. Note: * The EXDMAC is not supported by the H8S/2424 Group. 6.13.1 Operation The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus mastership is as follows: (High) EXDMAC* > DMAC > DTC > CPU (Low) An internal bus access by internal bus masters except the EXDMAC* and external bus release, a refresh when the CBRM bit is 0, and an external bus access by the EXDMAC* can be executed in parallel. If an external bus release request, a refresh request, and an external access by an internal bus master occur simultaneously, the order of priority is as follows: (High) Refresh > EXDMAC* > External bus release (Low) (High) External bus release > External access by internal bus master except EXDMAC* (Low) As a refresh when the CBRM bit in REFCR is cleared to 0 and an external access other than to DRAM space by an internal bus master can be executed simultaneously, there is no relative order of priority for these two operations. Note: * The EXDMAC is not supported by the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 302 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.13.2 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific timings at which each bus master can relinquish the bus. (1) CPU The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, DMAC, or EXDMAC*, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: • The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the component operations. • With bit manipulation instructions such as BSET and BCLR, the sequence of operations is: data read (read), relevant bit manipulation operation (modify), write-back (write). The bus is not transferred during this read-modify-write cycle, which is executed as a series of bus cycles. • If the CPU is in sleep mode, the bus is transferred immediately. Note: * The EXDMAC is not supported by the H8S/2424 Group. (2) DTC The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). (3) DMAC The DMAC sends the bus arbiter a request for the bus when an activation request is generated. In the case of an external request in short address mode or normal mode, and in cycle steal mode, the DMAC releases the bus after a single transfer. In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after completion of the transfer. However, in the event of an EXDMAC or external bus release request, which have a higher priority than the DMAC, the bus may be transferred to the bus master even if block or burst transfer is in progress. Rev. 1.00 Sep. 19, 2008 Page 303 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (4) EXDMAC The EXDMAC sends the bus arbiter a request for the bus when an activation request is generated. As the EXDMAC is used exclusively for transfers to and from the external bus, if the bus is transferred to the EXDMAC, internal accesses by other internal bus masters are still executed in parallel. In normal transfer mode or cycle steal transfer mode, the EXDMAC releases the bus after a single transfer. In block transfer mode, it releases the bus after transfer of one block, and in burst transfer mode, after completion of the transfer. By setting the BGUP bit to 1 in EDMDR, it is possible to specify temporary release of the bus in the event of an external access request from an internal bus master. For details see section 8, EXDMA Controller (EXDMAC). Note: The EXDMAC is not supported by the H8S/2424 Group. (5) External Bus Release When the BREQ pin goes low and an external bus release request is issued while the BRLE bit is set to 1 in BCR, a bus request is sent to the bus arbiter. External bus release can be performed on completion of an external bus cycle. 6.14 Bus Controller Operation in Reset In a reset, this LSI, including the bus controller, enters the reset state immediately, and any executing bus cycle is aborted. Rev. 1.00 Sep. 19, 2008 Page 304 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.15 Usage Notes 6.15.1 External Bus Release Function and All-Module-Clocks-Stopped Mode In this LSI, if the ACSE bit is set to 1 in MSTPCR, and then a SLEEP instruction is executed with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered in which the clock is also stopped for the bus controller and I/O ports. In this state, the external bus release function is halted. To use the external bus release function in sleep mode, the ACSE bit in MSTPCR must be cleared to 0. Conversely, if a SLEEP instruction to place the chip in allmodule-clocks-stopped mode is executed in the external bus released state, the transition to allmodule-clocks-stopped mode is deferred and performed until after the bus is recovered. 6.15.2 External Bus Release Function and Software Standby In this LSI, internal bus master operation does not stop even while the bus is released, as long as the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP instruction to place the chip in software standby mode is executed while the external bus is released, the transition to software standby mode is deferred and performed after the bus is recovered. Also, since clock oscillation halts in software standby mode, if BREQ goes low in this mode, indicating an external bus release request, the request cannot be answered until the chip has recovered from the software standby state. 6.15.3 External Bus Release Function and CBR Refreshing/Auto Refreshing CBR refreshing/auto refreshing cannot be executed while the external bus is released. Setting the BREQOE bit to 1 in BCR beforehand enables the BREQO signal to be output when a CBR refresh/auto refresh request is issued. Note: The auto refresh control function is not supported by the H8S/2426 Group and H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 305 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.15.4 BREQO Output Timing When the BREQOE bit is set to 1 and the BREQO signal is output, BREQO may go low before the BACK signal. This will occur if the next external access request or CBR refresh request occurs while internal bus arbitration is in progress after the chip samples a low level of BREQ. 6.15.5 (1) Notes on Usage of the Synchronous DRAM Connection Clock Be sure to set the clock to be connected to the synchronous DRAM to SDRAMφ. (2) WAIT Pin In the continuous synchronous DRAM space, insertion of the wait state by the WAIT pin is disabled regardless of the setting of the WAITE bit in BCR. (3) Bank Control This LSI cannot carry out the bank control of the synchronous DRAM. All banks are selected. (4) Burst Access The burst read/burst write mode of the synchronous DRAM is not supported. When setting the mode register of the synchronous DRAM, set to the burst read/single write and set the burst length to 1. (5) CAS Latency When connecting a synchronous DRAM having CAS latency of 1, set the BE bit to 0 in the DRAMCR. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 306 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Section 7 DMA Controller (DMAC) This LSI has a built-in DMA controller (DMAC), which can carry out data transfer on up to 4 channels. 7.1 Features • Selectable as short address mode or full address mode Short address mode Maximum of 4 channels can be used Dual address mode or single address mode can be selected In dual address mode, one of the two addresses, transfer source and transfer destination, is specified as 24 bits and the other as 16 bits In single address mode, transfer source or transfer destination address only is specified as 24 bits In single address mode, transfer can be performed in one bus cycle Choice of sequential mode, idle mode, or repeat mode for dual address mode and single address mode Full address mode Maximum of 2 channels can be used Transfer source and transfer destination addresses as specified as 24 bits Choice of normal mode or block transfer mode • 16-Mbyte address space can be specified directly • Byte or word can be set as the transfer unit • Activation sources: internal interrupt, external request, auto-request (depending on transfer mode) Six compare match/input capture interrupts of 16-bit timer-pulse unit (TPU0 to 5). Transmission complete interrupt and reception complete interrupt of serial communication interface (SCI_0, SCI_1) External request Auto-request • Module stop mode can be set Rev. 1.00 Sep. 19, 2008 Page 307 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) A block diagram of the DMAC is shown in figure 7.1. Internal address bus Address buffer Processor DMAWER DMACR_0A DMACR_0B DMACR_1A DMACR_1B DMABCR Channel 1 DMATCR MAR_0AH ETCR_0A MAR_0BH ETCR_0B MAR_1AH ETCR_1A MAR_1BH : DMA write enable register : DMA terminal control register : DMA band control register (for all channels) : DMA control register : Memory address register : I/O address register : Execute transfer count register Figure 7.1 Block Diagram of DMAC REJ09B0466-0100 MAR_1AL IOAR_1A Internal data bus Rev. 1.00 Sep. 19, 2008 Page 308 of 1270 MAR_0BL IOAR_0B Data buffer Legend: DMAWER DMATCR DMABCR DMACR MAR IOAR ETCR MAR_0AL IOAR_0A MAR_1BL IOAR_1B ETCR_1B Module data bus Channel 0 Control logic Channel 1B Channel 1A Channel 0B Channel 0A Internal interrupts TGI0A TGI1A TGI2A TGI3A TGI4A TGI5A TXI0 RXI0 TXI1 RXI1 ADI ADI0 External pins DREQ0 DREQ1 TEND0 TEND1 DACK0 DACK1 Interrupt signals DMTEND0A DMTEND0B DMTEND1A DMTEND1B Section 7 DMA Controller (DMAC) 7.2 Input/Output Pins Table 7.1 shows the pin configuration of the interrupt controller. Table 7.1 Pin Configuration Channel Pin Name Symbol I/O Function 0 DMA request 0 DREQ0 Input Channel 0 external request DMA transfer acknowledge 0 DACK0 Output Channel 0 single address transfer acknowledge DMA transfer end 0 TEND0 Output Channel 0 transfer end DMA request 1 DREQ1 Input Channel 1 external request DMA transfer acknowledge 1 DACK1 Output Channel 1 single address transfer acknowledge DMA transfer end 1 TEND1 Output Channel 1 transfer end 1 Rev. 1.00 Sep. 19, 2008 Page 309 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.3 • • • • • • • • • • • • • • • • • • • • • • • • Register Descriptions Memory address register_0AH (MAR_0AH) Memory address register_0AL (MAR_0AL) I/O address register_0A (IOAR_0A) Transfer count register_0A (ECTR_0A) Memory address register_0BH (MAR_0BH) Memory address register_0BL (MAR_0BL) I/O address register_0B (IOAR_0B) Transfer count register_0B (ECTR_0B) Memory address register_1AH (MAR_1AH) Memory address register_1AL (MAR_1AL) I/O address register_1A (IOAR_1A) Transfer count register_1A (ETCR_1A) Memory address register_1BH (MAR_1BH) Memory address register_1BL (MAR_1BL) I/O address register_1B (IOAR_1B) Transfer count register_1B (ETCR_1B) DMA control register_0A (DMACR_0A) DMA control register_0B (DMACR_0B) DMA control register_1A (DMACR_1A) DMA control register_1B (DMACR_1B) DMA band control register H (DMABCRH) DMA band control register L (DMABCRL) DMA write enable register (DMAWER) DMA terminal control register (DMATCR) The functions of MAR, IOAR, ETCR, DMACR, and DMABCR differ according to the transfer mode (short address mode or full address mode). The transfer mode can be selected by means of the FAE1 and FAE0 bits in DMABCRH. The register configurations for short address mode and full address mode of channel 0 are shown in table 7.2. Rev. 1.00 Sep. 19, 2008 Page 310 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Table 7.2 Short Address Mode and Full Address Mode (Channel 0) 0 Short address mode specified (channels 0A and 0B operate independently) MAR_0AH MAR_0BH MAR_0AL Specifies transfer source/transfer destination address IOAR_0A Specifies transfer destination/transfer source address ETCR_0A Specifies number of transfers DMACR_0A MAR_0BL Specifies transfer size, mode, activation source. Specifies transfer source/transfer destination address IOAR_0B Specifies transfer destination/transfer source address ETCR_0B Specifies number of transfers DMACR_0B Specifies transfer size, mode, activation source. Full address mode specified (channels 0A and 0B operate in combination as channel 0) Channel 0 1 Channel 0A Description Channel 0B FAE0 MAR_0AH MAR_0AL Specifies transfer source address MAR_0BH MAR_0BL Specifies transfer destination address IOAR_0A IOAR_0B ETCR_0A ETCR_0B DMACR_0A DMACR_0B Not used Not used Specifies number of transfers Specifies number of transfers (used in block transfer mode only) Specifies transfer size, mode, activation source, etc. Rev. 1.00 Sep. 19, 2008 Page 311 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.3.1 Memory Address Registers (MARA and MARB) MAR is a 32-bit readable/writable register that specifies the source address (transfer source address) or destination address (transfer destination address). MAR consists of two 16-bit registers MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and cannot be modified. The DMA has four MAR registers: MAR_0A in channel 0 (channel 0A), MAR_0B in channel 0 (channel 0B), MAR_1A in channel 1 (channel 1A), and MAR_1B in channel 1 (channel 1B). MAR is not initialized by a reset or in standby mode. Short Address Mode: In short address mode, MARA and MARB operate independently. Whether MAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. MAR is incremented or decremented each time a byte or word transfer is executed, so that the address specified by MAR is constantly updated. Full Address Mode: In full address mode, MARA functions as the source address register, and MARB as the destination address register. MAR is incremented or decremented each time a byte or word transfer is executed, so that the source or destination address is constantly updated. Rev. 1.00 Sep. 19, 2008 Page 312 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.3.2 I/O Address Registers (IOARA and IOARB) IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the source address (transfer source address) or destination address (transfer destination address). The upper 8 bits of the transfer address are automatically set to H'FF. The DMA has four IOAR registers: IOAR_0A in channel 0 (channel 0A), IOAR_0B in channel 0 (channel 0B), IOAR_1A in channel 1 (channel 1A), and IOAR_1B in channel 1 (channel 1B). Whether IOAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. IOAR is not incremented or decremented each time a data transfer is executed, so the address specified by IOAR is fixed. IOAR is not initialized by a reset or in standby mode. IOAR can be used in short address mode but not in full address mode. 7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The DMA has four ETCR registers: ETCR_0A in channel 0 (channel 0A), ETCR_0B in channel 0 (channel 0B), ETCR_1A in channel 1 (channel 1A), and ETCR_1B in channel 1 (channel 1B). ETCR is not initialized by a reset or in standby mode. Rev. 1.00 Sep. 19, 2008 Page 313 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) (1) Short Address Mode The function of ETCR in sequential mode and idle mode differs from that in repeat mode. In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter. ETCR is decremented by 1 each time a transfer is performed, and when the count reaches H'00, the DTE bit in DMABCRL is cleared, and transfer ends. In repeat mode, ETCRL functions as an 8-bit transfer counter and ETCRH functions as a transfer count holding register. ETCRL is decremented by 1 each time a transfer is performed, and when the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this point, MAR is automatically restored to the value it had when the count was started. The DTE bit in DMABCRL is not cleared, and so transfers can be performed repeatedly until the DTE bit is cleared by the user. (2) Full Address Mode The function of ETCR in normal mode differs from that in block transfer mode. In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each time a data transfer is performed, and transfer ends when the count reaches H'0000. ETCRB is not used in normal mode. In block transfer mode, ETCRA functions as an 8-bit block size counter (ETCRAL) and ETCRAH functions as a block size holding register. ETCRAL is decremented by 1 each time a 1-byte or 1word transfer is performed, and when the count reaches H'00, ETCRAL is loaded with the value in ETCRAH. So by setting the block size in ETCRAH and ETCRAL, it is possible to repeatedly transfer blocks consisting of any desired number of bytes or words. In block transfer mode, ETCRB functions as a 16-bit block transfer counter. ETCRB is decremented by 1 each time a block is transferred, and transfer ends when the count reaches H'0000. Rev. 1.00 Sep. 19, 2008 Page 314 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.3.4 DMA Control Registers (DMACRA and DMACRB) DMACR controls the operation of each DMAC channel. The DMA has four DMACR registers: DMACR_0A in channel 0 (channel 0A), DMACR_0B in channel 0 (channel 0B), DMACR_1A in channel 1 (channel 1A), and DMACR_1B in channel 1 (channel 1B). In short address mode, channels A and B operate independently, and in full address mode, channels A and B operate together. The bit functions in the DMACR registers differ according to the transfer mode. (1) Short Address Mode: • DMACR_0A, DMACR_0B, DMACR_1A, and DMARC_1B Bit Bit Name Initial Value R/W Description 7 DTSZ 0 R/W Data Transfer Size Selects the size of data to be transferred at one time. 0: Byte-size transfer 1: Word-size transfer 6 DTID 0 R/W Data Transfer Increment/Decrement Selects incrementing or decrementing of MAR after every data transfer in sequential mode or repeat mode. In idle mode, MAR is neither incremented nor decremented. 0: MAR is incremented after a data transfer (Initial value) • When DTSZ = 0, MAR is incremented by 1 • When DTSZ = 1, MAR is incremented by 2 1: MAR is decremented after a data transfer • When DTSZ = 0, MAR is decremented by 1 • When DTSZ = 1, MAR is decremented by 2 Rev. 1.00 Sep. 19, 2008 Page 315 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 5 RPE 0 R/W Repeat Enable Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed. • When DTIE = 0 (no transfer end interrupt) 0: Transfer in sequential mode 1: Transfer in repeat mode • When DTIE = 1 (with transfer end interrupt) 0: Transfer in sequential mode 1: Transfer in idle mode 4 DTDIR 0 R/W Data Transfer Direction Used in combination with the SAE bit in DMABCR to specify the data transfer direction (source or destination). The function of this bit is therefore different in dual address mode and single address mode. • When SAE = 0 0: Transfer with MAR as source address and IOAR as destination address 1: Transfer with IOAR as source address and MAR as destination address • When SAE = 1 0: Transfer with MAR as source address and DACK pin as write strobe 1: Transfer with DACK pin as read strobe and MAR as destination address Rev. 1.00 Sep. 19, 2008 Page 316 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W Data Transfer Factor 3 to 0 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W These bits select the data transfer factor (activation source). There are some differences in activation sources for channel A and channel B. • Channel A 0000: Setting prohibited 0001: Activated by A/D converter conversion end interrupt 0010: Setting prohibited 0011: Setting prohibited 0100: Activated by SCI channel 0 transmission complete interrupt 0101: Activated by SCI channel 0 reception complete interrupt 0110: Activated by SCI channel 1 transmission complete interrupt 0111: Activated by SCI channel 1 reception complete interrupt 1000: Activated by TPU channel 0 compare match/input capture A interrupt 1001: Activated by TPU channel 1 compare match/input capture A interrupt 1010: Activated by TPU channel 2 compare match/input capture A interrupt 1011: Activated by TPU channel 3 compare match/input capture A interrupt 1100: Activated by TPU channel 4 compare match/input capture A interrupt 1101: Activated by TPU channel 5 compare match/input capture A interrupt 1110: Setting prohibited 1111: Setting prohibited Rev. 1.00 Sep. 19, 2008 Page 317 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W • 2 DTF2 0 R/W 0000: Setting prohibited 1 DTF1 0 R/W 0 DTF0 0 R/W 0001: Activated by A/D converter conversion end interrupt Channel B 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled)* 0011: Activated by DREQ pin low-level input* 0100: Activated by SCI channel 0 transmission complete interrupt 0101: Activated by SCI channel 0 reception complete interrupt 0110: Activated by SCI channel 1 transmission complete interrupt 0111: Activated by SCI channel 1 reception complete interrupt 1000: Activated by TPU channel 0 compare match/input capture A interrupt 1001: Activated by TPU channel 1 compare match/input capture A interrupt 1010: Activated by TPU channel 2 compare match/input capture A interrupt 1011: Activated by TPU channel 3 compare match/input capture A interrupt 1100: Activated by TPU channel 4 compare match/input capture A interrupt 1101: Activated by TPU channel 5 compare match/input capture A interrupt 1110: Setting prohibited 1111: Setting prohibited The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.12, Multi-Channel Operation. Rev. 1.00 Sep. 19, 2008 Page 318 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) (2) Full Address Mode • DMACR_0A and DMACR_1A Bit Bit Name Initial Value R/W Description 15 DTSZ 0 R/W Data Transfer Size Selects the size of data to be transferred at one time. 0: Byte-size transfer 1: Word-size transfer 14 SAID 0 R/W Source Address Increment/Decrement 13 SAIDE 0 R/W Source Address Increment/Decrement Enable These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data transfer is performed. 00: MARA is fixed 01: MARA is incremented after a data transfer • When DTSZ = 0, MARA is incremented by 1 • When DTSZ = 1, MARA is incremented by 2 10: MARA is fixed 11: MARA is decremented after a data transfer • When DTSZ = 0, MARA is decremented by 1 • When DTSZ = 1, MARA is decremented by 2 12 BLKDIR 0 R/W Block Direction 11 BLKE 0 R/W Block Enable These bits specify whether normal mode or block transfer mode is to be used for data transfer. If block transfer mode is specified, the BLKDIR bit specifies whether the source side or the destination side is to be the block area. x0: Transfer in normal mode 01: Transfer in block transfer mode (destination side is block area) 11: Transfer in block transfer mode (source side is block area) Rev. 1.00 Sep. 19, 2008 Page 319 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 10 to 8 All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. Legend: x: Don’t care • DMACR_0B and DMACR_1B Bit Bit Name Initial Value R/W Description 7 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 6 DAID 0 R/W Destination Address Increment/Decrement 5 DAIDE 0 R/W Destination Address Increment/Decrement Enable These bits specify whether destination address register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed. 00: MARB is fixed 01: MARB is incremented after a data transfer • When DTSZ = 0, MARB is incremented by 1 • When DTSZ = 1, MARB is incremented by 2 10: MARB is fixed 11: MARB is decremented after a data transfer 4 — 0 R/W • When DTSZ = 0, MARB is decremented by 1 • When DTSZ = 1, MARB is decremented by 2 Reserved This bit can be read from or written to. However, the write value should always be 0. Rev. 1.00 Sep. 19, 2008 Page 320 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W Data Transfer Factor 3 to 0 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W These bits select the data transfer factor (activation source). The factors that can be specified differ between normal mode and block transfer mode. • Normal Mode 0000: Setting prohibited 0001: Setting prohibited 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled)* 0011: Setting prohibited 010x: Setting prohibited 0110: Auto-request (cycle steal) 0111: Auto-request (burst) 1×××: Setting prohibited Rev. 1.00 Sep. 19, 2008 Page 321 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W • 2 DTF2 0 R/W 0000: Setting prohibited 1 DTF1 0 R/W 0 DTF0 0 R/W 0001: Activated by A/D converter conversion end interrupt Block Transfer Mode 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled) 0011: Activated by DREQ pin low-level input 0100: Activated by SCI channel 0 transmission complete interrupt 0101: Activated by SCI channel 0 reception complete interrupt 0110: Activated by SCI channel 1 transmission complete interrupt 0111: Activated by SCI channel 1 reception complete interrupt 1000: Activated by TPU channel 0 compare match/input capture A interrupt 1001: Activated by TPU channel 1 compare match/input capture A interrupt 1010: Activated by TPU channel 2 compare match/input capture A interrupt 1011: Activated by TPU channel 3 compare match/input capture A interrupt 1100: Activated by TPU channel 4 compare match/input capture A interrupt 1101: Activated by TPU channel 5 compare match/input capture A interrupt 1110: Setting prohibited 1111: Setting prohibited The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.12, Multi-Channel Operation. Legend: ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 322 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL) DMABCR controls the operation of each DMAC channel. The bit functions in the DMABCR registers differ according to the transfer mode. (1) Short Address Mode: • DMABCRH Bit Bit Name Initial Value R/W Description 15 FAE1 0 R/W Full Address Enable 1 Specifies whether channel 1 is to be used in short address mode or full address mode. In short address mode, channels 1A and 1B can be used as independent channels. 0: Short address mode 1: Full address mode 14 FAE0 0 R/W Full Address Enable 0 Specifies whether channel 0 is to be used in short address mode or full address mode. In short address mode, channels 0A and 0B can be used as independent channels. 0: Short address mode 1: Full address mode 13 SAE1 0 R/W Single Address Enable 1 Specifies whether channel 1B is to be used for transfer in dual address mode or single address mode. This bit is invalid in full address mode. 0: Dual address mode 1: Single address mode 12 SAE0 0 R/W Single Address Enable 0 Specifies whether channel 0B is to be used for transfer in dual address mode or single address mode. This bit is invalid in full address mode. 0: Dual address mode 1: Single address mode Rev. 1.00 Sep. 19, 2008 Page 323 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 11 DTA1B 0 R/W Data Transfer Acknowledge 1B 10 DTA1A 0 R/W Data Transfer Acknowledge 1A 9 DTA0B 0 R/W Data Transfer Acknowledge 0B 8 DTA0A 0 R/W Data Transfer Acknowledge 0A These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR. If the DTA bit is set to 1 when DTE = 1, the internal interrupt source is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source does not issue an interrupt request to the CPU or DTC. If the DTA bit is cleared to 0 when DTE = 1, the internal interrupt source is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE = 0, the internal interrupt source issues an interrupt request to the CPU or DTC regardless of the DTA bit setting. Rev. 1.00 Sep. 19, 2008 Page 324 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) • DMABCRL Bit Bit Name Initial Value R/W Description 7 DTE1B 0 R/W Data Transfer Enable 1B 6 DTE1A 0 R/W Data Transfer Enable 1A 5 DTE0B 0 R/W Data Transfer Enable 0B 4 DTE0A 0 R/W Data Transfer Enable 0A If the DTE bit is cleared to 0 when DTIE = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. When DTE = 0, data transfer is disabled and the DMAC ignores the activation source selected by the DTF3 to DTF0 bits in DMACR. When DTE = 1, data transfer is enabled and the DMAC waits for a request by the activation source selected by the DTF3 to DTF0 bits in DMACR. When a request is issued by the activation source, DMA transfer is executed. [Clearing conditions] • When initialization is performed • When the specified number of transfers have been completed in a transfer mode other than repeat mode • When 0 is written to the DTE bit to forcibly suspend the transfer, or for a similar reason [Setting condition] When 1 is written to the DTE bit after reading DTE =0 Rev. 1.00 Sep. 19, 2008 Page 325 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTIE1B 0 R/W Data Transfer End Interrupt Enable 1B 2 DTIE1A 0 R/W Data Transfer End Interrupt Enable 1A 1 DTIE0B 0 R/W Data Transfer End Interrupt Enable 0B 0 DTIE0A 0 R/W Data Transfer End Interrupt Enable 0A These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIE bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE bit to 1. (2) Full Address Mode: • DMABCRH Bit Bit Name Initial Value R/W Description 15 FAE1 0 R/W Full Address Enable 1 Specifies whether channel 1 is to be used in short address mode or full address mode. In full address mode, channels 1A and 1B are used together as channel 1. 0: Short address mode 1: Full address mode 14 FAE0 0 R/W Full Address Enable 0 Specifies whether channel 0 is to be used in short address mode or full address mode. In full address mode, channels 0A and 0B are used together as channel 0. 0: Short address mode 1: Full address mode Rev. 1.00 Sep. 19, 2008 Page 326 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 13, 12 — All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. 11 DTA1 0 R/W Data Transfer Acknowledge 1 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 1. It the DTA1 bit is set to 1 when DTE1 = 1, the internal interrupt source is cleared automatically by DMA transfer. When DTE1 = 1 and DTA1 = 1, the internal interrupt source does not issue an interrupt request to the CPU or DTC. It the DTA1 bit is cleared to 0 when DTE1 = 1, the internal interrupt source is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE1 = 0, the internal interrupt source issues an interrupt request to the CPU or DTC regardless of the DTA1 bit setting. The state of the DTME1 bit does not affect the above operations. 10 — 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. Rev. 1.00 Sep. 19, 2008 Page 327 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 9 DTA0 0 R/W Data Transfer Acknowledge 0 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 0. It the DTA0 bit is set to 1 when DTE0 = 1, the internal interrupt source is cleared automatically by DMA transfer. When DTE0 = 1 and DTA0 = 1, the internal interrupt source does not issue an interrupt request to the CPU or DTC. It the DTA0 bit is cleared to 0 when DTE0 = 1, the internal interrupt source is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE0 = 0, the internal interrupt source issues an interrupt request to the CPU or DTC regardless of the DTA0 bit setting. The state of the DTME0 bit does not affect the above operations. 8 — 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. Rev. 1.00 Sep. 19, 2008 Page 328 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) • DMABCRL Bit Bit Name Initial Value R/W Description 7 DTME1 0 R/W Data Transfer Master Enable 1 Together with the DTE1 bit, this bit controls enabling or disabling of data transfer on channel 1. When both the DTME1 bit and DTE1 bit are set to 1, transfer is enabled for channel 1. If channel 1 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME1 bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU. When the DTME1 bit is subsequently set to 1 again, the interrupted transfer is resumed. In block transfer mode, however, the DTME1 bit is not cleared by an NMI interrupt, and transfer is not interrupted. [Clearing conditions] • When initialization is performed • When NMI is input in burst mode • When 0 is written to the DTME1 bit [Setting condition] When 1 is written to DTME1 after reading DTME1 =0 Rev. 1.00 Sep. 19, 2008 Page 329 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 6 DTE1 0 R/W Data Transfer Enable 1 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 1. When DTE1 = 0, data transfer is disabled and the activation source is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTE1 bit is cleared to 0 when DTIE1 = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU. When DTE1 = 1 and DTME1 = 1, data transfer is enabled and the DMAC waits for a request by the activation source. When a request is issued by the activation source, DMA transfer is executed. [Clearing conditions] • When initialization is performed • When the specified number of transfers have been completed • When 0 is written to the DTE1 bit to forcibly suspend the transfer, or for a similar reason [Setting condition] When 1 is written to the DTE1 bit after reading DTE1 = 0 Rev. 1.00 Sep. 19, 2008 Page 330 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 5 DTME0 0 R/W Data Transfer Master Enable 0 Together with the DTE0 bit, this bit controls enabling or disabling of data transfer on channel 0. When both the DTME0 bit and DTE0 bit are set to 1, transfer is enabled for channel 0. If channel 0 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME0 bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU. When the DTME0 bit is subsequently set to 1 again, the interrupted transfer is resumed. In block transfer mode, however, the DTME0 bit is not cleared by an NMI interrupt, and transfer is not interrupted. [Clearing conditions] • When initialization is performed • When NMI is input in burst mode • When 0 is written to the DTME0 bit [Setting condition] When 1 is written to DTME0 after reading DTME0 =0 Rev. 1.00 Sep. 19, 2008 Page 331 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 4 DTE0 0 R/W Data Transfer Enable 0 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 0. When DTE0 = 0, data transfer is disabled and the activation source is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTE0 bit is cleared to 0 when DTIE0 = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU. When DTE0 = 1 and DTME0 = 1, data transfer is enabled and the DMAC waits for a request by the activation source. When a request is issued by the activation source, DMA transfer is executed. [Clearing conditions] • When initialization is performed • When the specified number of transfers have been completed • When 0 is written to the DTE0 bit to forcibly suspend the transfer, or for a similar reason [Setting condition] When 1 is written to the DTE0 bit after reading DTE0 = 0 3 DTIE1B 0 R/W Data Transfer Interrupt Enable 1B Enables or disables an interrupt to the CPU or DTC when transfer on channel 1 is interrupted. If the DTME1 bit is cleared to 0 when DTIE1B = 1, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU or DTC. A transfer break interrupt can be canceled either by clearing the DTIE1B bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the DTME1 bit to 1. Rev. 1.00 Sep. 19, 2008 Page 332 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 2 DTIE1A 0 R/W Data Transfer End Interrupt Enable 1A Enables or disables an interrupt to the CPU or DTC when transfer ends. If the DTE1 bit is cleared to 1 when DTIE1A = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIE1A bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE1 bit to 1. 1 DTIE0B 0 R/W Data Transfer Interrupt Enable 0B Enables or disables an interrupt to the CPU or DTC when transfer on channel 1 is interrupted. If the DTME0 bit is cleared to 0 when DTIE0B = 1, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU or DTC. A transfer break interrupt can be canceled either by clearing the DTIE0B bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the DTME0 bit to 1. 0 DTIE0A 0 R/W Data Transfer End Interrupt Enable 0A Enables or disables an interrupt to the CPU or DTC when transfer ends. If the DTE0 bit is cleared to 0 when DTIE0A = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIE0A bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE0 bit to 1. Rev. 1.00 Sep. 19, 2008 Page 333 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.3.6 DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for the specific channel, to prevent inadvertent rewriting of registers other than those for the channel concerned. The restrictions applied by DMAWER are valid for the DTC. Bit Bit Name Initial Value R/W Description 7 to 4 All 0 — Reserved These bits are always read as 0 and cannot be modified. 3 WE1B 0 R/W Write Enable 1B Enables or disables writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR. 0: Writes are disabled 1: Writes are enabled 2 WE1A 0 R/W Write Enable 1A Enables or disables writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR. 0: Writes are disabled 1: Writes are enabled 1 WE0B 0 R/W Write Enable 0B Enables or disables writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR. 0: Writes are disabled 1: Writes are enabled 0 WE0A 0 R/W Write Enable 0A Enables or disables writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR. 0: Writes are disabled 1: Writes are enabled Rev. 1.00 Sep. 19, 2008 Page 334 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt request, and reactivating channel 0A. The address register and count register areas are set again during the first DTC transfer, then the control register area is set again during the second DTC chain transfer. When re-setting the control register area, perform masking by setting bits in DMAWER to prevent modification of the contents of other channels. MAR_0AH First transfer area MAR_0AL IOAR_0A ETCR_0A MAR_0BH MAR_0BL IOAR_0B ETCR_0B MAR_1AH MAR_1AL DTC IOAR_1A ETCR_1A MAR_1BH MAR_1BL IOAR_1B ETCR_1B Second transfer area using chain transfer DMAWER DMATCR DMACR_0A DMACR_0B DMACR_1A DMACR_1B DMABCR Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A) Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the DMAWER settings. These bits should be changed, if necessary, by CPU processing. In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0. To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable B for the channel to be reactivated. Rev. 1.00 Sep. 19, 2008 Page 335 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) MAR, IOAR, and ETCR can always be written to regardless of the DMAWER settings. When modifying these registers, the channel to be modified should be halted. 7.3.7 DMA Terminal Control Register (DMATCR) DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. The TEND pin is available only for channel B in short address mode. Except for the block transfer mode, a transfer end signal asserts in the transfer cycle in which the transfer counter contents reaches 0 regardless of the activation source. In the block transfer mode, a transfer end signal asserts in the transfer cycle in which the block counter contents reaches 0. Bit Bit Name Initial Value R/W Description 7, 6 All 0 Reserved These bits are always read as 0 and cannot be modified. 5 TEE1 0 R/W Transfer End Enable 1 Enables or disables transfer end pin 1 (TEND1) output. 0: TEND1 pin output disabled 1: TEND1 pin output enabled 4 TEE0 0 R/W Transfer End Enable 0 Enables or disables transfer end pin 0 (TEND0) output. 0: TEND0 pin output disabled 1: TEND0 pin output enabled 3 to 0 All 0 Reserved These bits are always read as 0 and cannot be modified. Rev. 1.00 Sep. 19, 2008 Page 336 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.4 Activation Sources DMAC activation sources consist of internal interrupt requests, external requests, and autorequests. The DMAC activation sources that can be specified depend on the transfer mode and channel, as shown in table 7.3. Table 7.3 DMAC Activation Sources Short Address Mode Activation Source Internal interrupts External requests Channels 0A and 1A Channels 0B and 1B Full Address Mode Normal Mode ADI0 × TXI0 × RXI0 × TXI1 × RXI1 × TGI0A × TGI1A × TGI2A × TGI3A × TGI4A × TGI5A × DREQ pin falling edge input × DREQ pin low-level input × Auto-request × × Block Transfer Mode × Legend: : Can be specified ×: Cannot be specified Rev. 1.00 Sep. 19, 2008 Page 337 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.4.1 Activation by Internal Interrupt Request An interrupt request selected as a DMAC activation source can also simultaneously generate an interrupt request for the CPU or DTC. For details, see section 5, Interrupt Controller. With activation by an internal interrupt request, the DMAC accepts the interrupt request independently of the interrupt controller. Consequently, interrupt controller priority settings are irrelevant. If the DMAC is activated by a CPU interrupt source or an interrupt request that is not used as a DTC activation source (DTA = 1), the interrupt request flag is cleared automatically by the DMA transfer. With ADI, TXI, and RXI interrupts, however, the interrupt source flag is not cleared unless the relevant register is accessed in a DMA transfer. If the same interrupt is used as an activation source for more than one channel, the interrupt request flag is cleared when the highestpriority channel is activated. Transfer requests for other channels are held pending in the DMAC, and activation is carried out in order of priority. When DTE = 0 after completion of a transfer, an interrupt request from the selected activation source is not sent to the DMAC, regardless of the DTA bit setting. In this case, the relevant interrupt request is sent to the CPU or DTC. When an interrupt request signal for DMAC activation is also used for an interrupt request to the CPU or DTC activation (DTA = 0), the interrupt request flag is not cleared by the DMAC. Rev. 1.00 Sep. 19, 2008 Page 338 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Activation by External Request If an external request (DREQ pin) is specified as a DMAC activation source, the relevant port should be set to input mode in advance*. Level sensing or edge sensing can be used for external requests. External request operation in normal mode of short address mode or full address mode is described below. When edge sensing is selected, a byte or word is transferred each time a high-to-low transition is detected on the DREQ pin. The next data transfer may not be performed if the next edge is input before data transfer is completed. When level sensing is selected, the DMAC stands by for a transfer request while the DREQ pin is held high. While the DREQ pin is held low, transfers continue in succession, with the bus being released each time a byte or word is transferred. If the DREQ pin goes high in the middle of a transfer, the transfer is interrupted and the DMAC stands by for a transfer request. Note: * If the relevant port is set as an output pin for another function, DMA transfers using the channel in question cannot be guaranteed. 7.4.2 Activation by Auto-Request Auto-request is activated by register setting only, and transfer continues to the end. With autorequest activation, cycle steal mode or burst mode can be selected. In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is transferred. DMA and CPU cycles are usually repeated alternately. In burst mode, the DMAC keeps possession of the bus until the end of the transfer so that transfer is performed continuously. 7.5 Operation 7.5.1 Transfer Modes Table 7.4 lists the DMAC transfer modes. Rev. 1.00 Sep. 19, 2008 Page 339 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Table 7.4 DMAC Transfer Modes Transfer Mode Transfer Source Remarks Short address mode • TPU channel 0 to 5 compare match/input capture A interrupt • Up to 4 channels can operate independently Dual address mode • 1-byte or 1-word transfer for a single transfer request • Specify source and destination addresses to transfer data in two bus cycles. (1) Sequential mode • Memory address incremented or decremented by 1 or 2 • SCI transmission complete interrupt • SCI reception complete interrupt • A/D converter conversion end interrupt • External request • Number of transfers: 1 to 65,536 (2) Idle mode • Memory address fixed • Number of transfers: 1 to 65,536 (3) Repeat mode • Memory address incremented or decremented by 1 or 2 • Continues transfer after sending number of transfers (1 to 256) and restoring the initial value Single address mode • 1-byte or 1-word transfer for a single transfer request • 1-bus cycle transfer by means of DACK pin instead of using address for specifying I/O • Sequential mode, idle mode, or repeat mode can be specified Rev. 1.00 Sep. 19, 2008 Page 340 of 1270 REJ09B0466-0100 • External request • External request applies to channel B only • Single address mode applies to channel B only Section 7 DMA Controller (DMAC) Transfer Mode Transfer Source Remarks Full address mode • Auto-request • Max. 2-channel operation, combining channels A and B Normal mode (1) Auto-request • Transfer request is internally held • Number of transfers (1 to 65,536) is continuously sent • Burst/cycle steal transfer can be selected (2) External request • External request • 1-byte or 1-word transfer for a single transfer request • Number of transfers: 1 to 65,536 Block transfer mode • Transfer of 1-block, size selected for a single transfer request • Number of transfers: 1 to 65,536 • Source or destination can be selected as block area • Block size: 1 to 256 bytes or word • TPU channel 0 to 5 compare match/input capture A interrupt • SCI transmission complete interrupt • SCI reception complete interrupt • A/D converter conversion end interrupt • External request Rev. 1.00 Sep. 19, 2008 Page 341 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.5 summarizes register functions in sequential mode. Table 7.5 Register Functions in Sequential Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting 23 Source address register 0 Destination Source address address register register Start address of Fixed transfer source or transfer destination Transfer counter Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 MAR 23 15 H'FF IOAR 15 0 Operation 0 ETCR Destination Start address of Incremented/ address transfer destination decremented every register or transfer source transfer MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. Rev. 1.00 Sep. 19, 2008 Page 342 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.3 illustrates operation in sequential mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N – 1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.3 Operation in Sequential Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a data transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536. Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can only be specified for channel B. Rev. 1.00 Sep. 19, 2008 Page 343 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.4 shows an example of the setting procedure for sequential mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Sequential mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] [4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Clear the RPE bit to 0 to select sequential mode. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. Read DMABCRL [5] Set DMABCRL [6] [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts with the DTIE bit. • Set the DTE bit to 1 to enable transfer. Sequential mode Figure 7.4 Example of Sequential Mode Setting Procedure Rev. 1.00 Sep. 19, 2008 Page 344 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.3 Idle Mode Idle mode can be specified by setting the RPE bit in DMACR and DTIE bit in DMABCRL to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6 summarizes register functions in idle mode. Table 7.6 Register Functions in Idle Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting 23 0 Source address register 0 Destination Source address address register register Start address of Fixed transfer source or transfer destination Transfer counter Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 MAR 23 15 H'FF IOAR 15 0 ETCR Operation Destination Start address of Fixed address transfer destination register or transfer source MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is neither incremented nor decremented by a data transfer. IOAR specifies the lower 16 bits of the other address. The upper 8 bits of IOAR have a value of H'FF. Rev. 1.00 Sep. 19, 2008 Page 345 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.5 illustrates operation in idle mode. Transfer MAR IOAR 1 byte or word transfer performed in response to 1 transfer request Figure 7.5 Operation in Idle Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536. Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can only be specified for channel B. Rev. 1.00 Sep. 19, 2008 Page 346 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.6 shows an example of the setting procedure for idle mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Idle mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] [4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Set the RPE bit to 1. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. • Set the DTIE bit to 1. • Set the DTE bit to 1 to enable transfer. Read DMABCRL [5] Set DMABCRL [6] Idle mode Figure 7.6 Example of Idle Mode Setting Procedure Rev. 1.00 Sep. 19, 2008 Page 347 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.4 Repeat Mode Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit in DMABCRL to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRL. On completion of the specified number of transfers, MAR and ETCRL are automatically restored to their original settings and operation continues. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.7 summarizes register functions in repeat mode. Table 7.7 Register Functions in Repeat Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting 23 Source address register 0 Destination Source address address register register Start address of Fixed transfer source or transfer destination Holds number of transfers Number of transfers Fixed Transfer counter Number of transfers Decremented every transfer. Loaded with ETCRH value when the value reaches H'00 MAR 23 15 H'FF IOAR 7 0 ETCRAH 7 0 ETCRAL Rev. 1.00 Sep. 19, 2008 Page 348 of 1270 REJ09B0466-0100 Operation 0 Destination Start address of Incremented/ address transfer destination decremented every register or transfer source transfer. Initial setting is restored when the value reaches H'0000 Section 7 DMA Controller (DMAC) MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The upper 8 bits of IOAR have a value of H'FF. The number of transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when H'00 is set in both ETCRH and ETCRL, is 256. In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number of transfers. ETCRL is decremented by 1 each time a data transfer is executed, and when its value reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR restoration operation is as shown below. MAR = MAR – (–1)DTID · 2DTSZ · ETCRH The same value should be set in ETCRH and ETCRL. In repeat mode, operation continues until the DTE bit in DMABCRL is cleared. To end the transfer operation, therefore, the DTE bit should be cleared to 0. A transfer end interrupt request is not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the transfer after that terminated when the DTE bit was cleared. Rev. 1.00 Sep. 19, 2008 Page 349 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.7 illustrates operation in repeat mode. Transfer Address T IOAR 1 byte or word transfer performed in response to 1 transfer request Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N – 1)) Where : L = Value set in MAR N = Value set in ETCR Address B Figure 7.7 Operation in Repeat mode Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can only be specified for channel B. Rev. 1.00 Sep. 19, 2008 Page 350 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.8 shows an example of the setting procedure for repeat mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Repeat mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in both ETCRH and ETCRL. Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] [4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Set the RPE bit to 1. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. Read DMABCRL [5] Set DMABCRL [6] [6] Set each bit in DMABCRL. • Clear the DTIE bit to 0. • Set the DTE bit to 1 to enable transfer. Repeat mode Figure 7.8 Example of Repeat Mode Setting Procedure Rev. 1.00 Sep. 19, 2008 Page 351 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.5 Single Address Mode Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCRH to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.8 summarizes register functions in single address mode. Table 7.8 Register Functions in Single Address Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting 23 0 MAR DACK pin 15 0 Operation Source address register Destination Start address of See sections 7.5.2, address transfer destination Sequential Mode, register or transfer source 7.5.3, Idle Mode, and 7.5.4, Repeat Mode. Write strobe Read strobe Transfer counter ETCR (Set automatically by SAE bit in DMABCRH; IOAR is invalid) Strobe for external device Number of transfers See sections 7.5.2, Sequential Mode, 7.5.3, Idle Mode, and 7.5.4, Repeat Mode. MAR specifies the start address of the transfer source or transfer destination as 24 bits. IOAR is invalid; in its place the strobe for external devices (DACK) is output. Rev. 1.00 Sep. 19, 2008 Page 352 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.9 illustrates operation in single address mode (when sequential mode is specified). Address T DACK Transfer 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N – 1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.9 Operation in Single Address Mode (When Sequential Mode Is Specified) Rev. 1.00 Sep. 19, 2008 Page 353 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.10 shows an example of the setting procedure for single address mode (when sequential mode is specified). Single address mode setting Set DMABCRH Set transfer source and transfer destination addresses [1] [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Set the SAE bit to 1 to select single address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [2] Set the transfer source address/transfer destination address in MAR. [2] Set number of transfers [3] Set DMACR [4] [3] Set the number of transfers in ETCR. [4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Clear the RPE bit to 0 to select sequential mode. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. Read DMABCRL [5] Set DMABCRL [6] [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts with the DTIE bit. • Set the DTE bit to 1 to enable transfer. Single address mode Figure 7.10 Example of Single Address Mode Setting Procedure (When Sequential Mode Is Specified) Rev. 1.00 Sep. 19, 2008 Page 354 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.6 Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCRH to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after data transfer of a byte or word in response to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB. Table 7.9 summarizes register functions in normal mode. Table 7.9 Register Functions in Normal Mode Register 23 Function Initial Setting Operation 0 Source address register Start address of transfer source Incremented/decremented every transfer, or fixed 0 Destination address register Start address of Incremented/decremented transfer destination every transfer, or fixed MARA 23 MARB 15 0 ETCRA Transfer counter Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented by 1 each time a transfer is performed, and when its value reaches H'0000 the DTE bit in DMABCRL is cleared and transfer ends. If the DTIE bit in DMABCRL is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536. Rev. 1.00 Sep. 19, 2008 Page 355 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.11 illustrates operation in normal mode. Transfer Address TA Address BB Address BA Legend: Address Address Address Address Where : TA TB BA BB LA LB N Address TB = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (N – 1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (N – 1)) = Value set in MARA = Value set in MARB = Value set in ETCRA Figure 7.11 Operation in Normal Mode Rev. 1.00 Sep. 19, 2008 Page 356 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Transfer requests (activation sources) are external requests and auto-requests. With auto-requests, the DMAC is only activated by register setting, and the specified number of transfers are performed automatically. With auto-requests, cycle steal mode or burst mode can be selected. In cycle steal mode, the bus is released to another bus master each time a transfer is performed. In burst mode, the bus is held continuously until transfer ends. Rev. 1.00 Sep. 19, 2008 Page 357 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.12 shows an example of the setting procedure for normal mode. [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Normal mode setting Set DMABCRH [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the number of transfers in ETCRA. Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] [4] Set each bit in DMACRA and DMACRB. • Set the transfer data size with the DTSZ bit. • Specify whether MARA is to be incremented, decremented, or fixed, with the SAID and SAIDE bits. • Clear the BLKE bit to 0 to select normal mode. • Specify whether MARB is to be incremented, decremented, or fixed, with the DAID and DAIDE bits. • Select the activation source with bits DTF3 to DTF0. [5] Read DTE = 0 and DTME = 0 in DMABCRL. Read DMABCRL [5] Set DMABCRL [6] [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts with the DTIE bit. • Set both the DTME bit and the DTE bit to 1 to enable transfer. Normal mode Figure 7.12 Example of Normal Mode Setting Procedure Rev. 1.00 Sep. 19, 2008 Page 358 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.7 Block Transfer Mode In block transfer mode, data transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCRH and the BLKE bit in DMACRA to 1. In block transfer mode, a data transfer of the specified block size is carried out in response to a single transfer request, and this is executed for the number of times specified in ETCRB. The transfer source is specified by MARA, and the transfer destination by MARB. Either the transfer source or the transfer destination can be selected as a block area (an area composed of a number of bytes or words). Table 7.10 summarizes register functions in block transfer mode. Table 7.10 Register Functions in Block Transfer Mode Register 23 Function Initial Setting Operation 0 Source address register Start address of transfer source Incremented/decremented every transfer, or fixed 0 Destination address register Start address of Incremented/decremented transfer destination every transfer, or fixed Holds block size Block size Fixed Block size counter Block size Decremented every transfer; ETCRAH value copied when count reaches H'00 Block transfer counter Number of block transfers Decremented every block transfer; transfer ends when count reaches H'0000 MARA 23 MARB 7 0 ETCRAH 7 0 ETCRAL 15 0 ETCRB MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. Whether a block is to be designated for MARA or for MARB is specified by the BLKDIR bit in DMACRA. To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL, and N in ETCRB. Rev. 1.00 Sep. 19, 2008 Page 359 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.13 illustrates operation in block transfer mode when MARB is designated as a block area. Address TB Address TA 1st block 2nd block Transfer Block area Consecutive transfer of M bytes or words is performed in response to one request Nth block Address BA Legend: Address Address Address Address Where : TA TB BA BB LA LB N M = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (M·N – 1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (N – 1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0) Rev. 1.00 Sep. 19, 2008 Page 360 of 1270 REJ09B0466-0100 Address BB Section 7 DMA Controller (DMAC) Figure 7.14 illustrates operation in block transfer mode when MARA is designated as a block area. Address TA Address TB Block area Transfer 1st block Consecutive transfer of M bytes or words is performed in response to one request Address BA 2nd block Nth block Address BB Legend: Address Address Address Address Where : TA TB BA BB LA LB N M = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (N – 1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (M·N – 1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1) Rev. 1.00 Sep. 19, 2008 Page 361 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00. ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA is restored in accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR. ETCRB is decremented by 1 after every block transfer, and when the count reaches H'0000 the DTE bit in DMABCRL is cleared and transfer ends. If the DTIE bit in DMABCRL is set to 1 at this point, an interrupt request is sent to the CPU or DTC. Rev. 1.00 Sep. 19, 2008 Page 362 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.15 shows the operation flow in block transfer mode. Start (DTE = DTME = 1) No Transfer request? Yes Acquire bus Read address specified by MARA MARA = MARA + SAIDE·(–1)SAID·2DTSZ Write to address specified by MARB MARB = MARB + DAIDE·(–1)DAID ·2DTSZ ETCRAL = ETCRAL – 1 ETCRAL = H'00 No Yes Release bus ETCRAL = ETCRAH BLKDIR = 0 No Yes MARB = MARB – DAIDE·(–1)DAID·2DTSZ·ETCRAH MARA = MARA – SAIDE·(–1)SAID·2DTSZ·ETCRAH ETCRB = ETCRB – 1 No ETCRB = H'0000 Yes Clear DTE bit to 0 to end transfer Figure 7.15 Operation Flow in Block Transfer Mode Rev. 1.00 Sep. 19, 2008 Page 363 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. Figure 7.16 shows an example of the setting procedure for block transfer mode. [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Block transfer mode setting Set DMABCRH Set transfer source and transfer destination addresses [1] [2] Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the block size in both ETCRAH and ETCRAL. Set the number of transfers in ETCRB. [4] Set each bit in DMACRA and DMACRB. • Set the transfer data size with the DTSZ bit. • Specify whether MARA is to be incremented, decremented, or fixed, with the SAID and SAIDE bits. • Set the BLKE bit to 1 to select block transfer mode. • Specify whether the transfer source or the transfer destination is a block area with the BLKDIR bit. • Specify whether MARB is to be incremented, decremented, or fixed, with the DAID and DAIDE bits. • Select the activation source with bits DTF3 to DTF0. [5] Read DTE = 0 and DTME = 0 in DMABCRL. Block transfer mode [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts to the CPU with the DTIE bit. • Set both the DTME bit and the DTE bit to 1 to enable transfer. Figure 7.16 Example of Block Transfer Mode Setting Procedure Rev. 1.00 Sep. 19, 2008 Page 364 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.8 Basic Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 7.17. In this example, wordsize transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations. As like CPU cycles, DMA cycles conform to the bus controller settings. The address is not output to the external address bus in an access to on-chip memory or an internal I/O register. CPU cycle CPU cycle DMAC cycle (1-word transfer) T1 T2 T1 T2 T3 T1 T2 T3 φ Source address Destination address Address bus RD HWR LWR Figure 7.17 Example of DMA Transfer Bus Timing Rev. 1.00 Sep. 19, 2008 Page 365 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.9 (1) DMA Transfer (Dual Address Mode) Bus Cycles Short Address Mode Figure 7.18 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.18 Example of Short Address Mode Transfer A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. In repeat mode, when TEND output is enabled, TEND output goes low in the transfer end cycle. Rev. 1.00 Sep. 19, 2008 Page 366 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) (2) Full Address Mode (Cycle Steal Mode) Figure 7.19 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Bus release Bus release Bus release Bus release Last transfer cycle Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal) A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one bus cycle is executed by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. Rev. 1.00 Sep. 19, 2008 Page 367 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) (3) Full Address Mode (Burst Mode) Figure 7.20 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (burst mode) is performed from external 16-bit, 2-state access space to external 16bit, 2-state access space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Last transfer cycle Bus release Bus release Burst transfer Figure 7.20 Example of Full Address Mode Transfer (Burst Mode) In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. If a request from another higher-priority channel is generated after burst transfer starts, that channel has to wait until the burst transfer ends. If an NMI interrupt is generated while a channel designated for burst transfer is in the transfer enabled state, the DTME bit in DMABCRL is cleared and the channel is placed in the transfer disabled state. If burst transfer has already been activated inside the DMAC, the bus is released on completion of a one-byte or one-word transfer within the burst transfer, and burst transfer is suspended. If the last transfer cycle of the burst transfer has already been activated inside the DMAC, execution continues to the end of the transfer even if the DTME bit is cleared. Rev. 1.00 Sep. 19, 2008 Page 368 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) (4) Full Address Mode (Block Transfer Mode) Figure 7.21 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space. DMA read DMA write DMA read DMA write DMA dead DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Bus release Block transfer Bus release Bus release Last block transfer Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode) A one-block transfer is performed for a single transfer request, and after the transfer the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC. In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a onestate DMA dead cycle is inserted after the DMA write cycle. Even if an NMI interrupt is generated during data transfer, block transfer operation is not affected until data transfer for one block has ended. (5) DREQ Pin Falling Edge Activation Timing Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.22 shows an example of normal mode transfer activated by the DREQ pin falling edge. Rev. 1.00 Sep. 19, 2008 Page 369 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) DMA read Bus release DMA write Bus release DMA read DMA write Bus release Transfer source Transfer destination φ DREQ Address bus DMA control Transfer source Transfer destination Idle Read Channel Write Idle Read Request clear period Request [1] [2] Idle Request clear period Request Minimum of 2 cycles Write Minimum of 2 cycles [3] [4] [5] Acceptance resumes [6] [7] Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the write cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.22 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA write cycle ends, acceptance resumes after the end of the write cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Figure 7.23 shows an example of block transfer mode transfer activated by the DREQ pin falling edge. Rev. 1.00 Sep. 19, 2008 Page 370 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 1 block transfer DMA read Bus release 1 block transfer DMA write DMA Bus dead release DMA read DMA write DMA dead Bus release φ DREQ Address bus DMA control Channel Transfer source Idle Read Request Transfer destination Dead Write Request clear period Idle [2] Read Write Transfer destination Dead Idle Request clear period Request Minimum of 2 cycles [1] Transfer source Minimum of 2 cycles [3] [4] [5] [6] Acceptance resumes [7] Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the dead cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.23 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA dead cycle ends, acceptance resumes after the end of the dead cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev. 1.00 Sep. 19, 2008 Page 371 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) DREQ Pin Low Level Activation Timing (Normal Mode) (6) Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.24 shows an example of normal mode transfer activated by the DREQ pin low level. DMA read DMA write Transfer source Transfer destination Bus release DMA read DMA write Transfer source Transfer destination Bus release Bus release φ DREQ Address bus DMA control Idle Read Channel Request Write Idle Read Request clear period [1] [2] Idle Request clear period Request Minimum of 2 cycles Write Minimum of 2 cycles [3] [4] [5] Acceptance resumes [6] [7] Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMA cycle is started. [4] [7] Acceptance is resumed after the write cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.24 Example of DREQ Pin Low Level Activated Normal Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the write cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev. 1.00 Sep. 19, 2008 Page 372 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.25 shows an example of block transfer mode transfer activated by DREQ pin low level. 1 block transfer DMA read Bus release 1 block transfer DMA write DMA Bus dead release DMA read DMA write DMA dead Bus release φ DREQ Address bus DMA control Channel Transfer source Read Idle Dead Write Request clear period Request Idle [2] Read Write Transfer destination Dead Idle Request clear period Request Minimum of 2 cycles [1] Transfer source Transfer destination Minimum of 2 cycles [3] [4] [5] [6] [7] Acceptance resumes Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMA cycle is started. [4] [7] Acceptance is resumed after the dead cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.25 Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev. 1.00 Sep. 19, 2008 Page 373 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.10 (1) DMA Transfer (Single Address Mode) Bus Cycles Single Address Mode (Read) Figure 7.26 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read DMA read DMA read DMA DMA read dead φ Address bus RD DACK TEND Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 7.26 Example of Single Address Mode Transfer (Byte Read) Figure 7.27 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. Rev. 1.00 Sep. 19, 2008 Page 374 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) DMA read DMA read DMA dead DMA read φ Address bus RD DACK TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.27 Example of Single Address Mode (Word Read) Transfer A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. Rev. 1.00 Sep. 19, 2008 Page 375 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) (2) Single Address Mode (Write) Figure 7.28 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write DMA write DMA write DMA DMA write dead φ Address bus HWR LWR DACK TEND Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 7.28 Example of Single Address Mode Transfer (Byte Write) Figure 7.29 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. Rev. 1.00 Sep. 19, 2008 Page 376 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) DMA write DMA write DMA dead DMA write φ Address bus HWR LWR DACK TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.29 Example of Single Address Mode Transfer (Word Write) A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. (3) DREQ Pin Falling Edge Activation Timing Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.30 shows an example of single address mode transfer activated by the DREQ pin falling edge. Rev. 1.00 Sep. 19, 2008 Page 377 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bus release DMA single Bus release DMA single Bus release φ DREQ Transfer source/ destination Address bus Transfer source/ destination DACK DMA control Channel Single Idle Request clear period Request Single Idle [1] [2] Request clear period Request Minimum of 2 cycles Idle Minimum of 2 cycles [3] [4] [5] Acceptance resumes [6] [7] Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the single cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.30 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA single cycle ends, acceptance resumes after the end of the single cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev. 1.00 Sep. 19, 2008 Page 378 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) DREQ Pin Low Level Activation Timing (4) Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.31 shows an example of single address mode transfer activated by the DREQ pin low level. Bus release DMA single Bus release Bus release DMA single φ DREQ Transfer source/ destination Address bus Transfer source/ destination DACK DMA control Single Idle Channel Single Idle Request clear period Request [1] [2] Request clear period Request Minimum of 2 cycles Idle Minimum of 2 cycles [3] [4] [5] Acceptance resumes [6] [7] Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMAC cycle is started. [4] [7] Acceptance is resumed after the single cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.31 Example of DREQ Pin Low Level Activated Single Address Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. Rev. 1.00 Sep. 19, 2008 Page 379 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. 7.5.11 Write Data Buffer Function DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved. When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfer and internal accesses (on-chip memory or internal I/O registers) are executed in parallel. Internal accesses are independent of the bus mastership, and DMAC dead cycles are regarded as internal accesses. A low level can always be output from the TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an external bus cycle. However, a low level is not output from the TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an internal bus cycle, and an external write cycle is executed in parallel with this cycle. Figure 7.32 shows an example of dual address transfer using the write data buffer function. The data is transferred from on-chip RAM to external memory. DMA read DMA write DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Internal address Internal read signal External address HWR, LWR TEND Figure 7.32 Example of Dual Address Transfer Using Write Data Buffer Function Rev. 1.00 Sep. 19, 2008 Page 380 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.33 shows an example of single address transfer using the write data buffer function. In this example, the CPU program area is in on-chip memory. DMA read DMA single CPU read DMA single CPU read φ Internal address Internal read signal External address RD DACK Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function When the write data buffer function is activated, the DMAC recognizes that the bus cycle concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one state after the start of the DMA write cycle or single address transfer. 7.5.12 Multi-Channel Operation The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table 7.11 summarizes the priority order for DMAC channels. Table 7.11 DMAC Channel Priority Order Short Address Mode Full Address Mode Priority Channel 0A Channel 0 High Channel 0B Channel 1A Channel 1B Channel 1 Low Rev. 1.00 Sep. 19, 2008 Page 381 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released, the DMAC selects the highest-priority channel from among those issuing a request according to the priority order shown in table 7.11. During burst transfer, or when one block is being transferred in block transfer, the channel will not be changed until the end of the transfer. Figure 7.34 shows a transfer example in which transfer requests are issued simultaneously for channels 0A, 0B, and 1. DMA read DMA write DMA read DMA write DMA read DMA DMA write read φ Address bus RD HWR LWR DMA control Idle Read Channel 0A Write Idle Read Write Idle Read Write Read Request clear Channel 0B Request hold Selection Channel 1 Request hold Nonselection Bus release Channel 0A transfer Request clear Request hold Bus release Selection Channel 0B transfer Request clear Bus release Figure 7.34 Example of Multi-Channel Transfer Rev. 1.00 Sep. 19, 2008 Page 382 of 1270 REJ09B0466-0100 Channel 1 transfer Section 7 DMA Controller (DMAC) 7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles, and EXDMAC When the DMAC accesses external space, contention with a refresh cycle, EXDMAC cycle, or external bus release cycle may arise. In this case, the bus controller will suspend the transfer and insert a refresh cycle, EXDMAC cycle, or external bus release cycle, in accordance with the external bus priority order, even if the DMAC is executing a burst transfer or block transfer. (An external access by the DTC or CPU, which has a lower priority than the DMAC, is not executed until the DMAC releases the external bus.) When the DMAC transfer mode is dual address mode, the DMAC releases the external bus after an external write cycle. The external read cycle and external write cycle are inseparable, and so the bus cannot be released between these two cycles. When the DMAC accesses internal space (on-chip memory or an internal I/O register), the DMAC cycle may be executed at the same time as a refresh cycle, EXDMAC cycle, or external bus release cycle. Rev. 1.00 Sep. 19, 2008 Page 383 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.14 DMAC and NMI Interrupts When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and DTME bit in DMABCRLare set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested. If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the CPU. The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again. Figure 7.35 shows the procedure for continuing transfer when it has been interrupted by an NMI interrupt on a channel designated for burst mode transfer. Resumption of transfer on interrupted channel DTE bit = 1 DTME bit = 0 [1] Check that DTE = 1 and DTME = 0 in DMABCRL. [2] Write 1 to the DTME bit. [1] No Yes Set DTME bit to 1 [2] Transfer continues Transfer ends Figure 7.35 Example of Procedure for Continuing Transfer on Channel Interrupted by NMI Interrupt Rev. 1.00 Sep. 19, 2008 Page 384 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.15 Forced Termination of DMAC Operation If the DTE bit in DMABCRL is cleared to 0 for the channel currently operating, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit in DMABCRL. Figure 7.36 shows the procedure for forcibly terminating DMAC operation by software. [1] Forced termination of DMAC Clear DTE bit to 0 Clear the DTE bit in DMABCRL to 0. To prevent interrupt generation after forced termination of DMAC operation, clear the DTIE bit to 0 at the same time. [1] Forced termination Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation Rev. 1.00 Sep. 19, 2008 Page 385 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.16 Clearing Full Address Mode Figure 7.37 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure. [1] Clear both the DTE bit and DTME bit in DMABCRL to 0, or wait until the transfer ends and the DTE bit is cleared to 0, then clear the DTME bit to 0. Also clear the corresponding DTIE bit to 0 at the same time. Clearing full address mode Stop the channel [1] [2] Clear all bits in DMACRA and DMACRB to 0. [3] Clear the FAE bit in DMABCRH to 0 Initialize DMACR [2] Clear FAE bit to 0 [3] Initialization; operation halted Figure 7.37 Example of Procedure for Clearing Full Address Mode Rev. 1.00 Sep. 19, 2008 Page 386 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.6 Interrupt Sources The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.12 shows the interrupt sources and their priority order. Table 7.12 Interrupt Sources and Priority Order Interrupt Source Interrupt Name Short Address Mode Full Address Mode DMTEND0A Interrupt due to end of transfer on channel 0A Interrupt due to end of transfer on channel 0 DMTEND0B Interrupt due to end of transfer on channel 0B Interrupt due to break in transfer on channel 0 DMTEND1A Interrupt due to end of transfer on channel 1A Interrupt due to end of transfer on channel 1 DMTEND1B Interrupt due to end of transfer on channel 1B Interrupt due to break in transfer on channel 1 Interrupt Priority Order High Low Enabling or disabling of each interrupt source is set by means of the DTIE bit in DMABCRL for the corresponding channel in DMABCRL, and interrupts from each source are sent to the interrupt controller independently. The priority of transfer end interrupts on each channel is decided by the interrupt controller, as shown in table 7.12. Figure 7.38 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is always generated when the DTIE bit is set to 1 while the DTE bit in DMABCRL is cleared to 0. DTE/ DTME Transfer end/transfer break interrupt DTIE Figure 7.38 Block Diagram of Transfer End/Transfer Break Interrupt In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to 0 while the DTIE bit is set to 1. In both short address mode and full address mode, DMABCR should be set so as to prevent the occurrence of a combination that constitutes a condition for interrupt generation during setting. Rev. 1.00 Sep. 19, 2008 Page 387 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.7 (1) Usage Notes DMAC Register Access during Operation Except for forced termination of the DMAC, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, DMAC registers should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below. • DMAC control starts one cycle before the bus cycle, with output of the internal address. Consequently, MAR is updated in the bus cycle before DMA transfer. Figure 7.39 shows an example of the update timing for DMAC registers in dual address transfer mode. DMA last transfer cycle DMA transfer cycle DMA read DMA read DMA write DMA write DMA dead φ DMA Internal address DMA control Idle DMA register operation [1] Transfer source Transfer destination Read Write [2] Transfer destination Transfer source Read Idle [1] Write [2'] Dead Idle [3] [1] Transfer source address register MAR operation (incremented/decremented/fixed) Transfer counter ETCR operation (decremented) Block size counter ETCR operation (decremented in block transfer mode) [2] Transfer destination address register MAR operation (incremented/decremented/fixed) [2']Transfer destination address register MAR operation (incremented/decremented/fixed) Block transfer counter ETCR operation (decremented, in last transfer cycle of a block in block transfer mode) [3] Transfer address register MAR restore operation (in block or repeat transfer mode) Transfer counter ETCR restore (in repeat transfer mode) Block size counter ETCR restore (in block transfer mode) Note: In single address transfer mode, the update timing is the same as [1]. The MAR operation is post-incrementing/decrementing of the DMA internal address value. Figure 7.39 DMAC Register Update Timing Rev. 1.00 Sep. 19, 2008 Page 388 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) • If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC register is read as shown in figure 7.40. DMA transfer cycle CPU longword read MAR upper word read MAR lower word read DMA read DMA write φ DMA internal address DMA control DMA register operation Idle [1] Transfe source Transfer destination Read Write Idle [2] Note: The lower word of MAR is the updated value after the operation in [1]. Figure 7.40 Contention between DMAC Register Update and CPU Read (2) Module Stop When the MSTP13 bit in MSTPCRH is set to 1, the DMAC clock stops, and the module stop state is entered. However, 1 cannot be written to the MSTP13 bit if any of the DMAC channels is enabled. This setting should therefore be made when DMAC operation is stopped. When the DMAC clock stops, DMAC register accesses can no longer be made. Since the following DMAC register settings are valid even in the module stop state, they should be invalidated, if necessary, before a module stop. • Transfer end/break interrupt (DTE = 0 and DTIE = 1) • TEND pin enable (TEE = 1) • DACK pin enable (FAE = 0 and SAE = 1) Rev. 1.00 Sep. 19, 2008 Page 389 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) (3) Write Data Buffer Function When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel. • Write data buffer function and DMAC register setting If the setting of a register that controls external accesses is changed during execution of an external access by means of the write data buffer function, the external access may not be performed normally. Registers that control external accesses should only be manipulated when external reads, etc., are used with DMAC operation disabled, and the operation is not performed in parallel with external access. • Write data buffer function and next DMAC operation The DMAC can start its next operation during external access using the write data buffer function. Consequently, the DREQ pin sampling timing, TEND output timing, etc., are different from the case in which the write data buffer function is disabled. Also, internal bus cycles maybe hidden, and not visible. (4) TEND Output If the last transfer cycle is for an internal address, note that even if low-level output at the TEND pin has been set, a low level may not be output at the TEND pin under the following external bus conditions since the last transfer cycle (internal bus cycle) and the external bus cycle are executed in parallel. 1. 2. 3. 4. 5. EXDMAC cycle Write cycle with write buffer mode enabled DMAC single address cycle for a different channel with write buffer mode enabled Bus release cycle CBR refresh cycle Figure 7.41 shows an example in which a low level is not output from the TEND pin in case 2 above. If the last transfer cycle is an external address cycle, a low level is output at the TEND pin in synchronization with the bus cycle. However, if the last transfer cycle and a CBR refresh occur simultaneously, note that although the CBR refresh and the last transfer cycle may be executed consecutively, TEND may also go low in this case for the refresh cycle. Rev. 1.00 Sep. 19, 2008 Page 390 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) DMA write DMA read φ Internal address Internal read signal Internal write signal External address HWR, LWR TEND Not output External write by CPU, etc. Figure 7.41 Example in which Low Level Is Not Output at TEND Pin (5) Activation by Falling Edge on DREQ Pin DREQ pin falling edge detection is performed in synchronization with DMAC internal operations. The operation is as follows: [1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and switches to [2]. [2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3]. [3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and switches to [1]. After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is enabled is performed on detection of a low level. Rev. 1.00 Sep. 19, 2008 Page 391 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) (6) Activation Source Acceptance At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low level that occurs before write to DMABCRL to enable transfer. When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ pin low level remaining from the end of the previous transfer, etc. (7) Internal Interrupt after End of Transfer When the DTE bit in DMABCRL is cleared to 0 at the end of a transfer or by a forcible termination, the selected internal interrupt request will be sent to the CPU or DTC even if the DTA bit in DMABCRH is set to 1. Also, if internal DMAC activation has already been initiated when operation is forcibly terminated, the transfer is executed but flag clearing is not performed for the selected internal interrupt even if the DTA bit is set to 1. An internal interrupt request following the end of transfer or a forcible termination should be handled by the CPU as necessary. (8) Channel Re-Setting To reactivate a number of channels when multiple channels are enabled, use exclusive handling of transfer end interrupts, and perform DMABCR control bit operations exclusively. Note, in particular, that in cases where multiple interrupts are generated between reading and writing of DMABCR, and a DMABCR operation is performed during new interrupt handling, the DMABCR write data in the original interrupt handling routine will be incorrect, and the write may invalidate the results of the operations by the multiple interrupts. Ensure that overlapping DMABCR operations are not performed by multiple interrupts, and that there is no separation between read and write operations by the use of a bit-manipulation instruction. Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must first be read while cleared to 0 before the CPU can write 1 to them. Rev. 1.00 Sep. 19, 2008 Page 392 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Section 8 EXDMA Controller (EXDMAC) This LSI has a built-in dual-channel external bus transfer DMA controller (EXDMAC). The EXDMAC can carry out high-speed data transfer, in place of the CPU, to and from external devices and external memory with a DACK (DMA transfer notification) facility. Note: This EXDMAC is not supported by the H8S/2424 Group. 8.1 Features • • • • • • • • • • • Direct specification of 16-Mbyte address space Selection of byte or word transfer data length Maximum number of transfers: 16M (16,777,215)/infinite (free-running) Selection of dual address mode or single address mode Selection of cycle steal mode or burst mode as bus mode Selection of normal mode or block transfer mode as transfer mode Two kinds of transfer requests: external request and auto-request An interrupt request can be sent to the CPU at the end of the specified number of transfers. Repeat area designation function: Operation in parallel with internal bus master: Acceptance of a transfer request and the start of transfer processing can be reported to an external device via the EDRAK pin. • Module stop mode can be set. Rev. 1.00 Sep. 19, 2008 Page 393 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Figure 8.1 shows a block diagram of the EXDMAC. Bus controller Data buffer Control logic EDRAK Address buffer Processor ETEND EDACK EDSAR Interrupt request signals to CPU for individual channels EDDAR EDMDR EDACR EDTCR Internal data bus Legend: EDSAR: EDDAR: EDTCR: EDMDR: EDACR: EXDMA source address register EXDMA destination address register EXDMA transfer count register EXDMA mode control register EXDMA address control register Figure 8.1 Block Diagram of EXDMAC Rev. 1.00 Sep. 19, 2008 Page 394 of 1270 REJ09B0466-0100 Module data bus External pins EDREQ Section 8 EXDMA Controller (EXDMAC) 8.2 Input/Output Pins Table 8.1 shows the pin configuration of the EXDMAC. Table 8.1 Pin Configuration Channel Name Abbreviation I/O Function 2 EXDMA transfer request 2 EDREQ2 Input Channel 2 external request EXDMA transfer acknowledge 2 EDACK2 Output Channel 2 single address transfer acknowledge EXDMA transfer end 2 ETEND2 Output Channel 2 transfer end EDREQ2 acceptance acknowledge EDRAK2 Output Notification to external device of channel 2 external request acceptance and start of transfer processing EXDMA transfer request 3 EDREQ3 Input Channel 3 external request EXDMA transfer acknowledge 3 EDACK3 Output Channel 3 single address transfer acknowledge EXDMA transfer end 3 ETEND3 Output Channel 3 transfer end EDREQ3 acceptance acknowledge EDRAK3 Output Notification to external device of channel 3 external request acceptance and start of transfer processing 3 Rev. 1.00 Sep. 19, 2008 Page 395 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.3 Register Descriptions The EXDMAC has the following registers. • • • • • • • • • • EXDMA source address register_2 (EDSAR_2) EXDMA destination address register_2 (EDDAR_2) EXDMA transfer count register_2 (EDTCR_2) EXDMA mode control register_2 (EDMDR_2) EXDMA address control register_2 (EDACR_2) EXDMA source address register_3 (EDSAR_3) EXDMA destination address register_3 (EDDAR_3) EXDMA transfer count register_3 (EDTCR_3) EXDMA mode control register_3 (EDMDR_3) EXDMA address control register_3 (EDACR_3) 8.3.1 EXDMA Source Address Register (EDSAR) EDSAR is a 32-bit readable/writable register that specifies the transfer source address. An address update function is provided that updates the register contents to the next transfer source address each time transfer processing is performed. In single address mode, the EDSAR value is ignored when a device with DACK is specified as the transfer source. The upper 8 bits of EDSAR are reserved; they are always read as 0 and cannot be modified. Only 0 should be written to these bits. EDSAR can be read at all times by the CPU. When reading EDSAR for a channel on which EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write to EDSAR for a channel on which EXDMA transfer is in progress. The initial values of EDSAR are undefined. Rev. 1.00 Sep. 19, 2008 Page 396 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.3.2 EXDMA Destination Address Register (EDDAR) EDDAR is a 32-bit readable/writable register that specifies the transfer destination address. An address update function is provided that updates the register contents to the next transfer destination address each time transfer processing is performed. In single address mode, the EDDAR value is ignored when a device with DACK is specified as the transfer destination. The upper 8 bits of EDDAR are reserved; they are always read as 0 and cannot be modified. Only 0 should be written to these bits. EDDAR can be read at all times by the CPU. When reading EDDAR for a channel on which EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write to EDDAR for a channel on which EXDMA transfer is in progress. The initial values of EDDAR are undefined. 8.3.3 EXDMA Transfer Count Register (EDTCR) EDTCR specifies the number of transfers. The function differs according to the transfer mode. Do not write to EDTCR for a channel on which EXDMA transfer is in progress. (1) Normal Transfer Mode Bit Bit Name Initial Value R/W 31 to 24 — All 0 — Description Reserved These bits are always read as 0 and cannot be modified. 23 to 0 All 0 R/W 24-Bit Transfer Counter These bits specify the number of transfers. Setting H'000001 specifies one transfer. Setting H'000000 means no specification for the number of transfers, and the transfer counter function is halted. In this case, there is no transfer end interrupt by the transfer counter. Setting H'FFFFFF specifies the maximum number of transfers, that is 16,777,215. During EXDMA transfer, this counter shows the remaining number of transfers. This counter can be read at all times. When reading EDTCR for a channel on which EXDMA transfer processing is in progress, a longword-size read must be executed. Rev. 1.00 Sep. 19, 2008 Page 397 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (2) Block Transfer Mode Bit Bit Name Initial Value R/W Description 31 to 24 — All 0 — Reserved These bits are always read as 0 and cannot be modified. 23 to 16 Undefined R/W Block Size These bits specify the block size (number of bytes or number of words) for block transfer. Setting H'01 specifies one as the block, while setting H'00 specifies the maximum block size, that is 256. The register value always indicates the specified block size. 15 to 0 Undefined R/W 16-Bit Transfer Counter These bits specify the number of block transfers. Setting H'0001 specifies one block transfer. Setting H'0000 means no specification for the number of transfers, and the transfer counter function is halted. In this case, there is no transfer end interrupt by the transfer counter. Setting H'FFFF specifies the maximum number of block transfers, that is 65,535. During EXDMA transfer, this counter shows the remaining number of block transfers. Rev. 1.00 Sep. 19, 2008 Page 398 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.3.4 EXDMA Mode Control Register (EDMDR) EDMDR controls EXDMAC operations. Bit Bit Name Initial Value R/W Description 15 EDA 0 R/(W) EXDMA Active Enables or disables data transfer on the corresponding channel. When this bit is set to 1, this indicates that an EXDMA operation is in progress. When auto request mode is specified (by bits MDS1 and MDS0), transfer processing begins when this bit is set to 1. With external requests, transfer processing begins when a transfer request is issued after this bit has been set to 1. When this bit is cleared to 0 during an EXDMA operation, transfer is halted. If this bit is cleared to 0 during an EXDMA operation in block transfer mode, transfer processing is continued for the currently executing one-block transfer, and the bit is cleared on completion of the currently executing one-block transfer. If an external source that ends (aborts) transfer occurs, this bit is automatically cleared to 0 and transfer is terminated. Do not change the operating mode, transfer method, or other parameters while this bit is set to 1. 0: Data transfer disabled on corresponding channel [Clearing conditions] • When the specified number of transfers end • When operation is halted by a repeat area overflow interrupt • When 0 is written to EDA while EDA = 1 (In block transfer mode, write is effective after end of one-block transfer) • Reset, NMI interrupt, hardware standby mode 1: Data transfer enabled on corresponding channel Note: The value written in the EDA bit may not be effective immediately. Rev. 1.00 Sep. 19, 2008 Page 399 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 14 BEF 0 R/(W)* Block Transfer Error Flag Flag that indicates the occurrence of an error during block transfer. If an NMI interrupt is generated during block transfer, the EXDMAC immediately terminates the EXDMA operation and sets this bit to 1. The address registers indicate the next transfer addresses, but the data for which transfer has been performed within the block size is lost. 0: No block transfer error [Clearing condition] Writing 0 to BEF after reading BEF = 1 1: Block transfer error [Setting condition] NMI interrupt during block transfer 13 EDRAKE 0 R/W EDRAK Pin Output Enable Enables output from the EDREQ acknowledge/transfer processing start (EDRAK) pin. 0: EDRAK pin output disabled 1: EDRAK pin output enabled 12 ETENDE 0 R/W ETEND Pin Output Enable Enables output from the EXDMA transfer end (ETEND) pin. 0: ETEND pin output disabled 1: ETEND pin output enabled 11 EDREQS 0 R/W EDREQ Select Specifies low level sensing or falling edge sensing as the sampling method for the EDREQ pin used in external request mode. 0: Low level sensing (Low level sensing is used for the first transfer after transfer is enabled.) 1: Falling edge sensing Rev. 1.00 Sep. 19, 2008 Page 400 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 10 AMS 0 R/W Address Mode Select Selects single address mode or dual address mode. When single address mode is selected, the EDACK pin is valid. 0: Dual address mode 1: Single address mode 9 MDS1 0 R/W Mode Select 1 and 0 8 MDS0 0 R/W These bits specify the activation source, bus mode, and transfer mode. 00: Auto request, cycle steal mode, normal transfer mode 01: Auto request, burst mode, normal transfer mode 10: External request, cycle steal mode, normal transfer mode 11: External request, cycle steal mode, block transfer mode 7 EDIE 0 R/W EXDMA Interrupt Enable Enables or disables interrupt requests. When this bit is set to 1, an interrupt is requested when the IRF bit is set to 1. The interrupt request is cleared by clearing this bit or the IRF bit to 0. 0: Interrupt request is not generated 1: Interrupt request is generated Rev. 1.00 Sep. 19, 2008 Page 401 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 6 IRF 0 R/(W)* Interrupt Request Flag Flag indicating that an interrupt request has occurred and transfer has ended. 0: No interrupt request [Clearing conditions] • Writing 1 to the EDA bit • Writing 0 to IRF after reading IRF = 1 1: Interrupt request occurrence [Setting conditions] 5 TCEIE 0 R/W • Transfer end interrupt request generated by transfer counter • Source address repeat area overflow interrupt request • Destination address repeat area overflow interrupt request Transfer Counter End Interrupt Enable Enables or disables transfer end interrupt requests by the transfer counter. When transfer ends according to the transfer counter while this bit is set to 1, the IRF bit is set to 1, indicating that an interrupt request has occurred. 0: Transfer end interrupt requests by transfer counter are disabled 1: Transfer end interrupt requests by transfer counter are enabled 4 SDIR 0 R/W Single Address Direction Specifies the data transfer direction in single address mode. In dual address mode, the specification by this bit is ignored. 0: Transfer direction: EDSAR → external device with DACK 1: Transfer direction: External device with DACK→ EDDAR Rev. 1.00 Sep. 19, 2008 Page 402 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 3 DTSIZE 0 R/W Data Transmit Size Specifies the size of data to be transferred. 0: Byte-size 1: Word-size 2 BGUP 0 R/W Bus Give-Up When this bit is set to 1, the bus can be transferred to an internal bus master in burst mode or block transfer mode. This setting is ignored in normal mode and cycle steal mode. 0: Bus is not released 1: Bus is transferred if requested by an internal bus master 1 — 0 R/W Reserved 0 — 0 R/W These bits are always read as 0. The initial values should not be modified. Note: * Only 0 can be written, to clear the flag. Rev. 1.00 Sep. 19, 2008 Page 403 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.3.5 EXDMA Address Control Register (EDACR) EDACR specifies address register incrementing/decrementing and use of the repeat area function. Bit Bit Name Initial Value R/W Description 15 SAT1 0 R/W Source Address Update Mode 14 SAT0 0 R/W These bits specify incrementing/decrementing of the transfer source address (EDSAR). When an external device with DACK is designated as the transfer source in single address mode, the specification by these bits is ignored. 0×: Fixed 10: Incremented (+1 in byte transfer, +2 in word transfer) 11: Decremented (–1 in byte transfer, –2 in word transfer) 13 SARIE 0 R/W Source Address Repeat Interrupt Enable When this bit is set to 1, in the event of source address repeat area overflow, the IRF bit is set to 1 and the EDA bit cleared to 0 in EDMDR, and transfer is terminated. If the EDIE bit in EDMDR is 1 when the IRF bit in EDMDR is set to 1, an interrupt request is sent to the CPU. When used together with block transfer mode, a source address repeat interrupt is requested at the end of a block-size transfer. If the EDA bit is set to 1 in EDMDR for the channel on which transfer is terminated by a source address repeat interrupt, transfer can be resumed from the state in which it ended. If a source address repeat area has not been designated, this bit is ignored. 0: Source address repeat interrupt is not requested 1: When source address repeat area overflow occurs, the IRF bit in EDMDR is set to 1 and an interrupt is requested Rev. 1.00 Sep. 19, 2008 Page 404 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 12 SARA4 0 R/W Source Address Repeat Area 11 SARA3 0 R/W 10 SARA2 0 R/W 9 SARA1 0 R/W 8 SARA0 0 R/W These bits specify the source address (EDSAR) repeat area. The repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. A repeat area size of 2 bytes to 8 Mbytes can be specified. The setting interval is a power-of-two number of bytes. When repeat area overflow results from incrementing or decrementing an address, the lower address is the start address of the repeat area in the case of address incrementing, or the last address of the repeat area in the case of address decrementing. If the SARIE bit is set to 1, an interrupt can be requested when repeat area overflow occurs. 00000: Not designated as repeat area 00001: Lower 1 bit (2-byte area) designated as repeat area 00010: Lower 2 bits (4-byte area) designated as repeat area 00011: Lower 3 bits (8-byte area) designated as repeat area 00100: Lower 4 bits (16-byte area) designated as repeat area : : 10011: Lower 19 bits (512-Kbyte area) designated as repeat area 10100: Lower 20 bits (1-Mbyte area) designated as repeat area 10101: Lower 21 bits (2-Mbyte area) designated as repeat area 10110: Lower 22 bits (4-Mbyte area) designated as repeat area 10111: Lower 23 bits (8-Mbyte area) designated as repeat area 11×××: Setting prohibited Rev. 1.00 Sep. 19, 2008 Page 405 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 7 DAT1 0 R/W Destination Address Update Mode 6 DAT0 0 R/W These bits specify incrementing/decrementing of the transfer destination address (EDDAR). When an external device with DACK is designated as the transfer destination in single address mode, the specification by these bits is ignored. 0×: Fixed 10: Incremented (+1 in byte transfer, +2 in word transfer) 11: Decremented (–1 in byte transfer, –2 in word transfer) 5 DARIE 0 R/W Destination Address Repeat Interrupt Enable When this bit is set to 1, in the event of destination address repeat area overflow the IRF bit is set to 1 and the EDA bit cleared to 0 in EDMDR, and transfer is terminated. If the EDIE bit in EDMDR is 1 when the IRF bit in EDMDR is set to 1, an interrupt request is sent to the CPU. When used together with block transfer mode, a destination address repeat interrupt is requested at the end of a block-size transfer. If the EDA bit is set to 1 in EDMDR for the channel on which transfer is terminated by a destination address repeat interrupt, transfer can be resumed from the state in which it ended. If a destination address repeat area has not been designated, this bit is ignored. 0: Destination address repeat interrupt is not requested 1: When destination address repeat area overflow occurs, the IRF bit in EDMDR is set to 1 and an interrupt is requested Rev. 1.00 Sep. 19, 2008 Page 406 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 4 DARA4 0 R/W Destination Address Repeat Area 3 DARA3 0 R/W 2 DARA2 0 R/W 1 DARA1 0 R/W 0 DARA0 0 R/W These bits specify the destination address (EDDAR) repeat area. The repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. A repeat area size of 2 bytes to 8 Mbytes can be specified. The setting interval is a powerof-two number of bytes. When repeat area overflow results from incrementing or decrementing an address, the lower address is the start address of the repeat area in the case of address incrementing, or the last address of the repeat area in the case of address decrementing. If the DARIE bit is set to 1, an interrupt can be requested when repeat area overflow occurs. 00000: Not designated as repeat area 00001: Lower 1 bit (2-byte area) designated as repeat area 00010: Lower 2 bits (4-byte area) designated as repeat area 00011: Lower 3 bits (8-byte area) designated as repeat area 00100: Lower 4 bits (16-byte area) designated as repeat area : : 10011: Lower 19 bits (512-Kbyte area) designated as repeat area 10100: Lower 20 bits (1-Mbyte area) designated as repeat area 10101: Lower 21 bits (2-Mbyte area) designated as repeat area 10110: Lower 22 bits (4-Mbyte area) designated as repeat area 10111: Lower 23 bits (8-Mbyte area) designated as repeat area 11×××: Setting prohibited Legend: ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 407 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.4 Operation 8.4.1 Transfer Modes The transfer modes of the EXDMAC are summarized in table 8.2. Table 8.2 EXDMAC Transfer Modes Transfer Mode Dual address mode Normal transfer mode Auto request mode • Burst/cycle steal mode External request mode Address Registers Transfer Origin Number of Transfers Auto request 1 to EDSAR 16,777,215 or no specification Source Destination EDDAR External request • Cycle steal mode Block transfer mode External request mode External request • Burst transfer of specified block size for a single transfer request 1 to 65,535 or no specification • Block size: 1 to 256 bytes or words Single address mode • Direct data transfer to/from external device using EDACK pin instead of source or destination address register EDSAR/ EDACK EDACK/ EDDAR • Above transfer mode can be specified in addition to address register setting • One transfer possible in one bus cycle (Transfer mode variations are the same as in dual address mode.) The transfer mode can be set independently for each channel. In normal transfer mode, a one-byte or one-word transfer is executed in response to one transfer request. With auto requests, burst or cycle steal transfer mode can be set. In burst transfer mode, continuous, high-speed transfer can be performed until the specified number of transfers have been executed or the transfer enable bit is cleared to 0. Rev. 1.00 Sep. 19, 2008 Page 408 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) In block transfer mode, a transfer of the specified block size is executed in response to one transfer request. The block size can be from 1 to 256 bytes or words. Within a block, transfer can be performed at the same high speed as in block transfer mode. When the “no specification” setting (EDTCR = H'000000) is made for the number of transfers, the transfer counter is halted and there is no limit on the number of transfers, allowing transfer to be performed endlessly. Incrementing or decrementing the memory address by 1 or 2, or leaving the address unchanged, can be specified independently for each address register. In all transfer modes, it is possible to set a repeat area comprising a power-of-two number of bytes. 8.4.2 (1) Address Modes Dual Address Mode In dual address mode, both the transfer source and transfer destination are specified by registers in the EXDMAC, and one transfer is executed in two bus cycles. The transfer source address is set in the source address register (EDSAR), and the transfer destination address is set in the transfer destination address register (EDDAR). In a transfer operation, the value in external memory specified by the transfer source address is read in the first bus cycle, and is written to the external memory specified by the transfer destination address in the next bus cycle. These consecutive read and write cycles are indivisible: another bus cycle (external access by an internal bus master, refresh cycle, or external bus release cycle) does not occur between these two cycles. ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND is output for two consecutive bus cycles. The EDACK signal is not output. Figure 8.2 shows an example of the timing in dual address mode. Rev. 1.00 Sep. 19, 2008 Page 409 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) EXDMA read cycle EXDMA write cycle φ Address bus EDSAR EDDAR RD WR ETEND Figure 8.2 Example of Timing in Dual Address Mode (2) Single Address Mode In single address mode, the EDACK signal is used instead of the source or destination address register to transfer data directly between an external device and external memory. In this mode, the EXDMAC accesses the transfer source or transfer destination external device by outputting the external I/O strobe signal (EDACK), and at the same time accesses the other external device in the transfer by outputting an address. In this way, DMA transfer can be executed in one bus cycle. In the example of transfer between external memory and an external device with DACK shown in figure 8.3, data is output to the data bus by the external device and written to external memory in the same bus cycle. The transfer direction, that is whether the external device with DACK is the transfer source or transfer destination, can be specified with the SDIR bit in EDMDR. Transfer is performed from the external memory (EDSAR) to the external device with DACK when SDIR = 0, and from the external device with DACK to the external memory (EDDAR) when SDIR = 1. The setting in the source or destination address register not used in the transfer is ignored. The EDACK pin becomes valid automatically when single address mode is selected. The EDACK pin is active-low. ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND is output for one bus cycle. Rev. 1.00 Sep. 19, 2008 Page 410 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Figure 8.3 shows the data flow in single address mode, and figure 8.4 shows an example of the timing. External address bus External data bus Microcomputer External memory EXDMAC External device with DACK EDACK EDREQ Data flow Figure 8.3 Data Flow in Single Address Mode Rev. 1.00 Sep. 19, 2008 Page 411 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Transfer from external memory to external device with DACK EXDMA cycle φ Address bus EDSAR RD Address to external memory space RD signal to external memory space WR EDACK Data output from external memory Data bus ETEND Transfer from external device with DACK to external memory EXDMA cycle φ Address bus EDDAR Address to external memory space RD WR WR signal to external memory space EDACK Data output from external device with DACK Data bus ETEND Figure 8.4 Example of Timing in Single Address Mode Rev. 1.00 Sep. 19, 2008 Page 412 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.4.3 (1) DMA Transfer Requests Auto Request Mode In auto request mode, transfer request signals are automatically generated within the EXDMAC in cases where a transfer request signal is not issued from outside, such as in transfer between two memories, or between a peripheral module that is not capable of generating transfer requests and memory. In auto request mode, transfer is started when the EDA bit is set to 1 in EDMDR. In auto request mode, either cycle steal mode or burst mode can be selected as the bus mode. Block transfer mode cannot be used. (2) External Request Mode In external request mode, transfer is started by a transfer request signal (EDREQ) from a device external to this LSI. DMA transfer is started when EDREQ is input while DMA transfer is enabled (EDA = 1). The transfer request source need not be the data transfer source or data transfer destination. The transfer request signal is accepted via the EDREQ pin. Either falling edge sensing or low level sensing can be selected for the EDREQ pin by means of the EDREQS bit in EDMDR (low level sensing when EDREQS = 0, falling edge sensing when EDREQS = 1). Setting the EDRAKE bit to 1 in EDMDR enables a signal confirming transfer request acceptance to be output from the EDRAK pin. The EDRAK signal is output when acceptance and transfer processing has been started in response to a single external request. The EDRAK signal enables the external device to determine the timing of EDREQ signal negation, and makes it possible to provide handshaking between the transfer request source and the EXDMAC. In external request mode, block transfer mode can be used instead of burst mode. Block transfer mode allows continuous execution (burst operation) of the specified number of transfers (the block size) in response to a single transfer request. In block transfer mode, the EDRAK signal is output only once for a one-block transfer, since the transfer request via the EDREQ pin is for a block unit. Rev. 1.00 Sep. 19, 2008 Page 413 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.4.4 Bus Modes There are two bus modes: cycle steal mode and burst mode. When the activation source is an auto request, either cycle steal mode or burst mode can be selected. When the activation source is an external request, cycle steal mode is used. (1) Cycle Steal Mode In cycle steal mode, the EXDMAC releases the bus at the end of each transfer of a transfer unit (byte, word, or block). If there is a subsequent transfer request, the EXDMAC takes back the bus, performs another transfer-unit transfer, and then releases the bus again. This procedure is repeated until the transfer end condition is satisfied. If a transfer request occurs in another channel during DMA transfer, the bus is temporarily released, then transfer is performed on the channel for which the transfer request was issued. If there is no external space bus request from another bus master, a one-cycle bus release interval is inserted. For details on the operation when there are requests for a number of channels, see section 8.4.8, Channel Priority Order. Figure 8.5 shows an example of the timing in cycle steal mode. EDREQ EDRAK Bus cycle CPU CPU EXDMAC CPU CPU EXDMAC Bus returned temporarily to CPU Transfer conditions: · Single address mode, normal transfer mode · EDREQ low level sensing · CPU internal bus master is operating in external space Figure 8.5 Example of Timing in Cycle Steal Mode Rev. 1.00 Sep. 19, 2008 Page 414 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (2) Burst Mode In burst mode, once the EXDMAC acquires the bus it continues transferring data, without releasing the bus, until the transfer end condition is satisfied. There is no burst mode in external request mode. In burst mode, once transfer is started it is not interrupted even if there is a transfer request from another channel with higher priority. When the burst mode channel finishes its transfer, it releases the bus in the next cycle in the same way as in cycle steal mode. When the EDA bit is cleared to 0 in EDMDR, DMA transfer is halted. However, DMA transfer is executed for all transfer requests generated within the EXDMAC up until the EDA bit was cleared to 0. If a repeat area overflow interrupt is generated, the EDA bit is cleared to 0 and transfer is terminated. When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another bus master during burst transfer. If there is no bus request, burst transfer is executed even if the BGUP bit is set to 1. Figure 8.6 shows examples of the timing in burst mode. Bus cycle CPU CPU EXDMAC EXDMAC EXDMAC CPU CPU CPU cycle not generated Transfer conditions: Auto request mode, BGUP = 0 Bus cycle CPU EXDMAC CPU EXDMAC CPU EXDMAC CPU EXDMAC operates alternately with CPU Transfer conditions: Auto request mode, BGUP = 1 Figure 8.6 Examples of Timing in Burst Mode Rev. 1.00 Sep. 19, 2008 Page 415 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.4.5 Transfer Modes There are two transfer modes: normal transfer mode and block transfer mode. When the activation source is an external request, either normal transfer mode or block transfer mode can be selected. When the activation source is an auto request, normal transfer mode is used. (1) Normal Transfer Mode In normal transfer mode, transfer of one transfer unit is processed in response to one transfer request. EDTCR functions as a 24-bit transfer counter. The ETEND signal is output only for the last DMA transfer. The EDRAK signal is output each time a transfer request is accepted and transfer processing is started. Figure 8.7 shows examples of DMA transfer timing in normal transfer mode. Bus cycle EXDMA transfer cycle Last EXDMA transfer cycle Read Read Write Write ETEND Transfer conditions: Dual address mode, auto request mode EDREQ EDRAK Bus cycle EXDMA EXDMA EDACK Transfer conditions: Single address mode, external request mode Figure 8.7 Examples of Timing in Normal Transfer Mode Rev. 1.00 Sep. 19, 2008 Page 416 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (2) Block Transfer Mode In block transfer mode, the number of bytes or words specified by the block size is transferred in response to one transfer request. The upper 8 bits of EDTCR specify the block size, and the lower 16 bits function as a 16-bit transfer counter. A block size of 1 to 256 can be specified. During transfer of a block, transfer requests for other higher-priority channels are held pending. When transfer of one block is completed, the bus is released in the next cycle. When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another bus master during block transfer. Address register values are updated in the same way as in normal mode. There is no function for restoring the initial address register values after each block transfer. The ETEND signal is output for each block transfer in the DMA transfer cycle in which the block ends. The EDRAK signal is output once for one transfer request (for transfer of one block). Caution is required when setting the repeat area overflow interrupt of the repeat area function in block transfer mode. See section 8.4.6, Repeat Area Function, for details. Block transfer is aborted if an NMI interrupt is generated. See section 8.4.12, Ending DMA Transfer, for details. Figure 8.8 shows an example of DMA transfer timing in block transfer mode. EDREQ EDRAK One-block transfer cycle Bus cycle CPU CPU CPU EXDMAC EXDMAC EXDMAC CPU CPU cycle not generated ETEND Transfer conditions: · Single address mode · BGUP = 0 · Block size (EDTCR[23:16]) = 3 Figure 8.8 Example of Timing in Block Transfer Mode Rev. 1.00 Sep. 19, 2008 Page 417 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.4.6 Repeat Area Function The EXDMAC has a function for designating a repeat area for source addresses and/or destination addresses. When a repeat area is designated, the address register values repeat within the range specified as the repeat area. Normally, when a ring buffer is involved in a transfer, an operation is required to restore the address register value to the buffer start address each time the address register value is the last address in the buffer (i.e. when ring buffer address overflow occurs), but if the repeat area function is used, the operation that restores the address register value to the buffer start address is performed automatically within the EXDMAC. The repeat area function can be set independently for the source address register and the destination address register. The source address repeat area is specified by bits SARA4 to SARA0 in EDACR, and the destination address repeat area by bits DARA4 to DARA0 in EDACR. The size of each repeat area can be specified independently. When the address register value is the last address in the repeat area and repeat area overflow occurs, DMA transfer can be temporarily halted and an interrupt request sent to the CPU. If the SARIE bit in EDACR is set to 1, when the source address register overflows the repeat area, the IRF bit is set to 1 and the EDA bit cleared to 0 in EDMDR, and transfer is terminated. If EDIE = 1 in EDMDR, an interrupt is requested. If the DARIE bit in EDACR is set to 1, the above applies to the destination address register. Rev. 1.00 Sep. 19, 2008 Page 418 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) If the EDA bit in EDMDR is set to 1 during interrupt generation, transfer is resumed. Figure 8.9 illustrates the operation of the repeat area function. When lower 3 bits (8-byte area) of EDSAR are designated as repeat area (SARA4 to SARA0 = 3) External memory : Range of EDSAR values H'23FFFE H'23FFFF H'240000 H'240000 H'240001 H'240001 H'240002 H'240002 H'240003 H'240003 H'240004 H'240004 H'240005 H'240005 H'240006 H'240006 H'240007 H'240007 H'240008 H'240009 Repeated Repeat area overflow interrupt can be requested : Figure 8.9 Example of Repeat Area Function Operation Caution is required when the repeat area overflow interrupt function is used together with block transfer mode. If transfer is always terminated when repeat area overflow occurs in block transfer mode, the block size must be a power of two, or alternatively, the address register value must be set so that the end of a block coincides with the end of the repeat area range. Rev. 1.00 Sep. 19, 2008 Page 419 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) If repeat area overflow occurs while a block is being transferred in block transfer mode, the repeat interrupt request is held pending until the end of the block, and transfer overrun will occur. Figure 8.10 shows an example in which block transfer mode is used together with the repeat area function. When lower 3 bits (8-byte area) of EDSAR are designated as repeat area (SARA4 to SARA0 = 3), and block size of 5 (EDTCR[23–16] = 5) is set in block transfer mode External memory Range of EDSAR values First block transfer Second block transfer H'240000 H'240000 H'240000 H'240000 H'240001 H'240001 H'240001 H'240001 H'240002 H'240002 H'240002 H'240003 H'240003 H'240003 H'240004 H'240004 H'240004 H'240005 H'240005 H'240005 H'240006 H'240006 H'240006 H'240007 H'240007 H'240007 : H'23FFFE H'23FFFF H'240008 Interrupt requested Block transfer in progress H'240009 : Figure 8.10 Example of Repeat Area Function Operation in Block Transfer Mode Rev. 1.00 Sep. 19, 2008 Page 420 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.4.7 Registers during DMA Transfer Operation EXDMAC register values are updated as DMA transfer processing is performed. The updated values depend on various settings and the transfer status. The following registers and bits are updated: EDSAR, EDDAR, EDTCR, and bits EDA, BEF, and IRF in EDMDR, (1) EXDMA Source Address Register (EDSAR) When the EDSAR address is accessed as the transfer source, after the EDSAR value is output, EDSAR is updated with the address to be accessed next. Bits SAT1 and SAT0 in EDACR specify incrementing or decrementing. The address is fixed when SAT1 = 0, incremented when SAT1 = 1 and SAT0 = 0, and decremented when SAT1 = 1 and SAT0 = 1. The size of the increment or decrement is determined by the size of the data transferred. When the DTSIZE bit in EDMDR = 0, the data is byte-size and the address is incremented or decremented by 1; when DTSIZE = 1, the data is word-size and the address is incremented or decremented by 2. When a repeat area setting is made, the operation conforms to that setting. The upper part of the address set for the repeat area function is fixed, and is not affected by address updating. When EDSAR is read during a transfer operation, a longword access must be used. During a transfer operation, EDSAR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. In a longword access, the EXDMAC buffers the EDSAR value to ensure that the correct value is output. Do not write to EDSAR for a channel on which a transfer operation is in progress. (2) EXDMA Destination Address Register (EDDAR) When the EDDAR address is accessed as the transfer destination, after the EDDAR value is output, EDDAR is updated with the address to be accessed next. Bits DAT1 and DAT0 in EDACR specify incrementing or decrementing. The address is fixed when DAT1 = 0, incremented when DAT1 = 1 and DAT0 = 0, and decremented when DAT1 = 1 and DAT0 = 1. The size of the increment or decrement is determined by the size of the data transferred. When the DTSIZE bit in EDMDR = 0, the data is byte-size and the address is incremented or decremented by 1; when DTSIZE = 1, the data is word-size and the address is incremented or decremented by 2. When a repeat area setting is made, the operation conforms to that setting. The upper part of the address set for the repeat area function is fixed, and is not affected by address updating. Rev. 1.00 Sep. 19, 2008 Page 421 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) When EDDAR is read during a transfer operation, a longword access must be used. During a transfer operation, EDDAR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. In a longword access, the EXDMAC buffers the EDDAR value to ensure that the correct value is output. Do not write to EDDAR for a channel on which a transfer operation is in progress. (3) EXDMA Transfer Count Register (EDTCR) When a DMA transfer is performed, the value in EDTCR is decremented by 1. However, when the EDTCR value is 0, transfers are not counted and the EDTCR value does not change. EDTCR functions differently in block transfer mode. The upper 8 bits, EDTCR[23:16], are used to specify the block size, and their value does not change. The lower 16 bits, EDTCR[15:0], function as a transfer counter, the value of which is decremented by 1 when a DMA transfer is performed. However, when the EDTCR[15:0] value is 0, transfers are not counted and the EDTCR[15:0] value does not change. In normal transfer mode, all of the lower 24 bits of EDTCR may change, so when EDTCR is read by the CPU during DMA transfer, a longword access must be used. During a transfer operation, EDTCR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. In a longword access, the EXDMAC buffers the EDTCR value to ensure that the correct value is output. In block transfer mode, the upper 8 bits are never updated, so there is no problem with using word access. Do not write to EDTCR for a channel on which a transfer operation is in progress. If there is contention between an address update associated with DMA transfer and a write by the CPU, the CPU write has priority. In the event of contention between an EDTCR update from 1 to 0 and a write (of a nonzero value) by the CPU, the CPU write value has priority as the EDTCR value, but transfer is terminated. Transfer does not end if the CPU writes 0 to EDTCR. Rev. 1.00 Sep. 19, 2008 Page 422 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Figure 8.11 shows EDTCR update operations in normal transfer mode and block transfer mode. EDTCR in normal transfer mode After update Before update 23 0 EDTCR 0 0 23 EDTCR Fixed 23 0 0 –1 1 to H'FFFFFF 23 0 0 to H'FFFFFE EDTCR in block transfer mode EDTCR Before update 23 16 15 Block 0 size EDTCR 23 16 15 Block 1 to H'FFFF size 0 0 Fixed –1 After update 23 16 15 Block 0 size 23 16 15 Block 0 to H'FFFE size 0 0 Figure 8.11 EDTCR Update Operations in Normal Transfer Mode and Block Transfer Mode (4) EDA Bit in EDMDR The EDA bit in EDMDR is written to by the CPU to control enabling and disabling of data transfer, but may be cleared automatically by the EXDMAC due to the DMA transfer status. There are also periods during transfer when a 0-write to the EDA bit by the CPU is not immediately effective. Conditions for EDA bit clearing by the EXDMAC include the following: • • • • • • When the EDTCR value changes from 1 to 0, and transfer ends When a repeat area overflow interrupt is requested, and transfer ends When an NMI interrupt is generated, and transfer halts A reset Hardware standby mode When 0 is written to the EDA bit, and transfer halts Rev. 1.00 Sep. 19, 2008 Page 423 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) When transfer is halted by writing 0 to the EDA bit, the EDA bit remains at 1 during the DMA transfer period. In block transfer mode, since a block-size transfer is carried out without interruption, the EDA bit remains at 1 from the time 0 is written to it until the end of the current block-size transfer. In burst mode, transfer is halted for up to three DMA transfers following the bus cycle in which 0 is written to the EDA bit. The EDA bit remains set to 1 from the time of the 0-write until the end of the last DMA cycle. Writes (except to the EDA bit) are prohibited to registers of a channel for which the EDA bit is set to 1. When changing register settings after a 0-write to the EDA bit, it is necessary to confirm that the EDA bit has been cleared to 0. Figure 8.12 shows the procedure for changing register settings in an operating channel. [1] Write 0 to the EDA bit in EDMDR. Changing register settings in operating channel Write 0 to EDA bit [2] Read the EDA bit. [1] [3] Confirm that EDA = 0. If EDA = 1, this indicates that DMA transfer is in progress. [4] Write the required set values to the registers. Read EDA bit [2] EDA bit = 0? [3] No Yes Change register settings [4] Register setting changes completed Figure 8.12 Procedure for Changing Register Settings in Operating Channel Rev. 1.00 Sep. 19, 2008 Page 424 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (5) BEF Bit in EDMDR In block transfer mode, the specified number of transfers (equivalent to the block size) is performed in response to a single transfer request. To ensure that the correct number of transfers is carried out, a block-size transfer is always executed, except in the event of a reset, transition to standby mode, or generation of an NMI interrupt. If an NMI interrupt is generated during block transfer, operation is halted midway through a block-size transfer and the EDA bit is cleared to 0, terminating the transfer operation. In this case the BEF bit, which indicates the occurrence of an error during block transfer, is set to 1. (6) IRF Bit in EDMDR The IRF bit in EDMDR is set to 1 when an interrupt request source occurs. If the EDIE bit in EDMDR is 1 at this time, an interrupt is requested. The timing for setting the IRF bit to 1 is when the EDA bit in EDMDR is cleared to 0 and transfer ends following the end of the DMA transfer bus cycle in which the source generating the interrupt occurred. If the EDA bit is set to 1 and transfer is resumed during interrupt handling, the IRF bit is automatically cleared to 0 and the interrupt request is cleared. For details on interrupts, see section 8.5, Interrupt Sources. 8.4.8 Channel Priority Order The priority order of the EXDMAC channels is: channel 2 > channel 3. Table 8.3 shows the EXDMAC channel priority order. Table 8.3 Channel EXDMAC Channel Priority Order Channel 2 Priority High Channel 3 Low If transfer requests occur simultaneously for a number of channels, the highest-priority channel according to the priority order in table 8.3 is selected for transfer. Rev. 1.00 Sep. 19, 2008 Page 425 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (1) Transfer Requests from Multiple Channels (Except Auto Request Cycle Steal Mode) If transfer requests for different channels are issued during a transfer operation, the highestpriority channel (excluding the currently transferring channel) is selected. The selected channel begins transfer after the currently transferring channel releases the bus. If there is a bus request from a bus master other than the EXDMAC at this time, a cycle for the other bus master is initiated. If there is no other bus request, the bus is released for one cycle. Channel switching does not take place during a burst transfer or a block transfer of a single block. Figure 8.13 shows a case in which transfer requests for channels 2 and 3 are issued simultaneously. The example shown in the figure illustrates the handling of external requests in the cycle steal mode. Channel 2 transfer Channel 3 transfer φ Channel 2 Address bus EXDMA control Idle Channel 2 Channel 2 Request cleared Channel 3 Request Selected held Bus release Channel 3 Bus release Channel 3 Request cleared Figure 8.13 Example of Channel Priority Timing (2) Transfer Requests from Multiple Channels in Auto Request Cycle Steal Mode If transfer requests for different channels are issued during a transfer in auto request cycle steal mode, the operation depends on the channel priority. If the channel that made the transfer request is of higher priority than the channel currently performing transfer, the channel that made the transfer request is selected. If the channel that made the transfer request is of lower priority than the channel currently performing transfer, that channel’s transfer request is held pending, and the currently transferring channel remains selected. Rev. 1.00 Sep. 19, 2008 Page 426 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) The selected channel begins transfer after the currently transferring channel releases the bus. If there is a bus request from a bus master other than the EXDMAC at this time, a cycle for the other bus master is initiated. If there is no other bus request, the bus is released for one cycle. Figure 8.14 shows examples of transfer timing in cases that include auto request cycle steal mode. Conditions (1) Channel 2: Auto request, cycle steal mode Channel 3: External request, cycle steal mode, low level activation Bus Channel 2 * Channel 2 * Channel 2 * Channel 3 * * Channel 3 Channel 2 EDA bit Channel 3/ EDREQ3 pin Conditions (2) Channel 2: External request, cycle steal mode, low level activation Channel 3: Auto request, cycle steal mode Bus Channel 3 * Channel 3 * Channel 2 * Channel 3 * Channel 2 * Channel 2 * Channel 2 * Channel 3 * Channel 2 Channel 2/ EDREQ2 pin Channel 2 EDA bit Conditions (3) Channel 2: Auto request, cycle steal mode Channel 3: Auto request, cycle steal mode Bus Channel 3 * Channel 3 * Channel 2 EDA bit Channel 3 EDA bit *: Bus release Figure 8.14 Examples of Channel Priority Timing Rev. 1.00 Sep. 19, 2008 Page 427 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.4.9 (1) EXDMAC Bus Cycles (Dual Address Mode) Normal Transfer Mode (Cycle Steal Mode) Figure 8.15 shows an example of transfer when ETEND output is enabled, and word-size, normal transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. After one byte or word has been transferred, the bus is released. While the bus is released, one CPU, DMAC, or DTC bus cycle is initiated. DMA read DMA write DMA read DMA write DMA read DMA write φ Address bus RD HWR LWR ETEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 8.15 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer Rev. 1.00 Sep. 19, 2008 Page 428 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (2) Normal Transfer Mode (Burst Mode) Figure 8.16 shows an example of transfer when ETEND output is enabled, and word-size, normal transfer mode (burst mode) is performed from external 16-bit, 2-state access space to external 16bit, 2-state access space. In burst mode, one-byte or one-word transfers are executed continuously until transfer ends. Once burst transfer starts, requests from other channels, even of higher priority, are held pending until transfer ends. DMA read DMA write DMA read DMA write DMA read DMA write φ Address bus RD HWR LWR ETEND Bus release Last transfer cycle Burst transfer Bus release Figure 8.16 Example of Normal Transfer Mode (Burst Mode) Transfer If an NMI interrupt is generated while a channel designated for burst transfer is enabled for transfer, the EDA bit is cleared and transfer is disabled. If a block transfer has already been initiated within the EXDMAC, the bus is released on completion of the currently executing byte or word transfer, and burst transfer is aborted. If the last transfer cycle in burst transfer has been initiated within the EXDMAC, transfer is executed to the end even if the EDA bit is cleared. Rev. 1.00 Sep. 19, 2008 Page 429 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (3) Block Transfer Mode (Cycle Steal Mode) Figure 8.17 shows an example of transfer when ETEND output is enabled, and word-size, block transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. One block is transferred in response to one transfer request, and after the transfer, the bus is released. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated. DMA read DMA write DMA read DMA write DMA read DMA write DMA read DMA write φ Address bus RD HWR LWR ETEND Bus release Block transfer Bus release Last block transfer Figure 8.17 Example of Block Transfer Mode (Cycle Steal Mode) Transfer Rev. 1.00 Sep. 19, 2008 Page 430 of 1270 REJ09B0466-0100 Bus release Section 8 EXDMA Controller (EXDMAC) (4) EDREQ Pin Falling Edge Activation Timing Figure 8.18 shows an example of normal mode transfer activated by the EDREQ pin falling edge. DMA read DMA write Transfer source Transfer destination Write Idle Bus release DMA read Bus release DMA write Bus release φ EDREQ Address bus DMA control Read Idle Channel Transfer source Read Request clearance period Request [1] [2] [3] Minimum 3 cycles [4] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Idle Request clearance period Request Minimum 3 cycles Write Transfer destination [5] [6] [7] Acceptance resumed Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held. Request is cleared at end of next bus cycle, and activation is started in EXDMAC. DMA cycle start; EDREQ pin high level sampling is started at rise of φ. When EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle. (As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.) Figure 8.18 Example of Normal Mode Transfer Activated by EDREQ Pin Falling Edge EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the EDMDR write cycle for setting the transfer-enabled state. When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ pin high level sampling is completed by the end of the DMA write cycle, acceptance resumes after the end of the write cycle, and EDREQ pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer. Figure 8.19 shows an example of block transfer mode transfer activated by the EDREQ pin falling edge. Rev. 1.00 Sep. 19, 2008 Page 431 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) One block transfer One block transfer Bus release DMA read DMA write Transfer source Transfer destination Bus release DMA read DMA write Bus release φ EDREQ Address bus DMA control Idle Read Channel Write Idle Read Write Request clearance period Request Minimum 3 cycles [1] Transfer source [2] [3] Idle Request clearance period Request Minimum 3 cycles [4] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Transfer destination [5] [6] [7] Acceptance resumed Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held. Request is cleared at end of next bus cycle, and activation is started in EXDMAC. DMA cycle start; EDREQ pin high level sampling is started at rise of φ. When EDREQ pin high level has been sampled, acceptance is resumed after completion of dead cycle. (As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.) Figure 8.19 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Falling Edge EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the EDMDR write cycle for setting the transfer-enabled state. When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ pin high level sampling is completed by the end of the DMA write cycle, acceptance resumes after the end of the write cycle, and EDREQ pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer. Rev. 1.00 Sep. 19, 2008 Page 432 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (5) EDREQ Pin Low Level Activation Timing Figure 8.20 shows an example of normal mode transfer activated by the EDREQ pin low level. Bus release DMA read DMA write Transfer source Transfer destination Bus release DMA read DMA write Bus release φ EDREQ Address bus DMA control Idle Channel Read Write Idle Request clearance period Request Minimum 3 cycles [1] [2] [3] Transfer source Read Idle Request clearance period Request Minimum 3 cycles [4] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Write Transfer destination [5] [6] [7] Acceptance resumed Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held. Request is cleared at end of next bus cycle, and activation is started in EXDMAC. DMA cycle is started. Acceptance is resumed after completion of write cycle. (As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.) Figure 8.20 Example of Normal Mode Transfer Activated by EDREQ Pin Low Level EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the EDMDR write cycle for setting the transfer-enabled state. When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared. At the end of the write cycle, acceptance resumes and EDREQ pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer. Figure 8.21 shows an example of block transfer mode transfer activated by the EDREQ pin low level. Rev. 1.00 Sep. 19, 2008 Page 433 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) One block transfer Bus release One block transfer DMA read DMA write Transfer source Transfer destination Bus release DMA read DMA write Bus release φ EDREQ Address bus DMA control Read Idle Channel Write Transfer source Read Write Idle Request clearance period Request [2] [3] Minimum 3 cycles [4] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Idle Request clearance period Request Minimum 3 cycles [1] Transfer destination [5] [6] [7] Acceptance resumed Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held. Request is cleared at end of next bus cycle, and activation is started in EXDMAC. DMA cycle is started. Acceptance is resumed after completion of dead cycle. (As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.) Figure 8.21 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Low Level EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the EDMDR write cycle for setting the transfer-enabled state. When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared. At the end of the write cycle, acceptance resumes and EDREQ pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer. Rev. 1.00 Sep. 19, 2008 Page 434 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.4.10 (1) EXDMAC Bus Cycles (Single Address Mode) Single Address Mode (Read) Figure 8.22 shows an example of transfer when ETEND output is enabled, and byte-size, single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read DMA read DMA read DMA read φ Address bus RD EDACK ETEND Bus release Bus release Bus release Bus release Bus release Last transfer cycle Figure 8.22 Example of Single Address Mode (Byte Read) Transfer Figure 8.23 shows an example of transfer when ETEND output is enabled, and word-size, single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read DMA read DMA read φ Address bus RD EDACK ETEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 8.23 Example of Single Address Mode (Word Read) Transfer Rev. 1.00 Sep. 19, 2008 Page 435 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) After one byte or word has been transferred in response to one transfer request, the bus is released. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated. (2) Single Address Mode (Write) Figure 8.24 shows an example of transfer when ETEND output is enabled, and byte-size, single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write DMA write DMA write DMA write φ Address bus HWR LWR EDACK ETEND Bus release Bus release Bus release Bus release Last Bus release transfer cycle Figure 8.24 Example of Single Address Mode (Byte Write) Transfer Rev. 1.00 Sep. 19, 2008 Page 436 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Figure 8.25 shows an example of transfer when ETEND output is enabled, and word-size, single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write DMA write DMA write φ Address bus HWR LWR EDACK ETEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 8.25 Example of Single Address Mode (Word Write) Transfer After one byte or word has been transferred in response to one transfer request, the bus is released. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated. Rev. 1.00 Sep. 19, 2008 Page 437 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (3) EDREQ Pin Falling Edge Activation Timing Figure 8.26 shows an example of single address mode transfer activated by the EDREQ pin falling edge. DMA single Bus release DMA single Bus release Bus release φ EDREQ Transfer source/ destination Address bus Transfer source/ destination EDACK DMA control Idle Single Channel Request Minimum 3 cycles [1] Idle Single Request clearance period [2] [3] Request Minimum 3 cycles [4] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Idle Request clearance period [5] [6] [7] Acceptance resumed Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held. Request is cleared at end of next bus cycle, and activation is started in EXDMAC. DMA cycle start; EDREQ pin high level sampling is started at rise of φ. When EDREQ pin high level has been sampled, acceptance is resumed after completion of single cycle. (As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.) Figure 8.26 Example of Single Address Mode Transfer Activated by EDREQ Pin Falling Edge EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the EDMDR write cycle for setting the transfer-enabled state. When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ pin high level sampling is completed by the end of the DMA single cycle, acceptance resumes after the end of the single cycle, and EDREQ pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer. Rev. 1.00 Sep. 19, 2008 Page 438 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (4) EDREQ Pin Low Level Activation Timing Figure 8.27 shows an example of single address mode transfer activated by the EDREQ pin low level. DMA single Bus release DMA single Bus release Bus release φ EDREQ Transfer source/ destination Address bus Transfer source/ destination EDACK DMA control Idle Single Channel Request Minimum 3 cycles [1] Idle Single Request clearance period [2] [3] Request Minimum 3 cycles [4] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Idle Request clearance period [5] [6] [7] Acceptance resumed Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held. Request is cleared at end of next bus cycle, and activation is started in EXDMAC. DMA cycle is started. Acceptance is resumed after completion of single cycle. (As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.) Figure 8.27 Example of Single Address Mode Transfer Activated by EDREQ Pin Low Level EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the EDMDR write cycle for setting the transfer-enabled state. When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared. At the end of the single cycle, acceptance resumes and EDREQ pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer. Rev. 1.00 Sep. 19, 2008 Page 439 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.4.11 (1) Examples of Operation Timing in Each Mode Auto Request/Cycle Steal Mode/Normal Transfer Mode When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. There is a one-cycle bus release interval between the end of a one-transfer-unit EXDMA cycle and the start of the next transfer. If there is a transfer request for another channel of higher priority, the transfer request by the original channel is held pending, and transfer is performed on the higher-priority channel from the next transfer. Transfer on the original channel is resumed on completion of the higher-priority channel transfer. Figures 8.28 to 8.30 show operation timing examples for various conditions. φ pin 1 cycle 3 cycles Bus release Bus cycle EXDMA read EXDMA write EXDMA read Bus release CPU operation EDA = 1 write Last transfer cycle EXDMA write EXDMA read EXDMA write Bus release Internal bus space cycles ETEND EDA bit 0 1 Figure 8.28 Auto Request/Cycle Steal Mode/Normal Transfer Mode (No Contention/Dual Address Mode) Rev. 1.00 Sep. 19, 2008 Page 440 of 1270 REJ09B0466-0100 0 Section 8 EXDMA Controller (EXDMAC) φ pin 1 bus cycle Bus cycle CPU cycle CPU operation External space EXDMA single transfer cycle CPU cycle External space Last transfer cycle EXDMA single transfer cycle CPU cycle EXDMA single transfer cycle External space CPU cycle External space EDACK ETEND Figure 8.29 Auto Request/Cycle Steal Mode/Normal Transfer Mode (CPU Cycles/Single Address Mode) φ pin 1 cycle Bus cycle EXDMA single cycle EXDMA single cycle Bus release 1 cycle 1 cycle EXDMA single cycle Bus release EXDMA single cycle Higher-priority channel EXDMA cycle Bus release Bus release Bus release Current channel EDACK Other channel transfer request (EDREQ) Figure 8.30 Auto Request/Cycle Steal Mode/Normal Transfer Mode (Contention with Another Channel/Single Address Mode) Rev. 1.00 Sep. 19, 2008 Page 441 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (2) Auto Request/Burst Mode/Normal Transfer Mode When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. Once transfer is started, it continues (as a burst) until the transfer end condition is satisfied. If the BGUP bit is 1 in EDMDR, the bus is transferred in the event of a bus request from another bus master. Transfer requests for other channels are held pending until the end of transfer on the current channel. Figures 8.31 to 8.34 show operation timing examples for various conditions. φ pin Last transfer cycle Bus cycle CPU operation CPU cycle CPU cycle External space External space EXDMA read EXDMA write EXDMA read EXDMA write Repeated EXDMA read EXDMA write CPU cycle External space ETEND EDA bit 1 0 Figure 8.31 Auto Request/Burst Mode/Normal Transfer Mode (CPU Cycles/Dual Address Mode/BGUP = 0) Rev. 1.00 Sep. 19, 2008 Page 442 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) φ pin 1 bus cycle Bus cycle CPU operation CPU cycle CPU cycle External space External space EXDMA read EXDMA write CPU cycle External space 1 bus cycle EXDMA read EXDMA write CPU cycle EXDMA read EXDMA write External space Figure 8.32 Auto Request/Burst Mode/Normal Transfer Mode (CPU Cycles/Dual Address Mode/BGUP = 1) φ pin Last transfer cycle 1 bus cycle Bus cycle CPU operation EXDMA EXDMA EXDMA EXDMA EXDMA CPU cycle CPU cycle single cycle single cycle CPU cycle single cycle single cycle CPU cycle single cycle CPU cycle External space External space External space External space External space EDACK ETEND Figure 8.33 Auto Request/Burst Mode/Normal Transfer Mode (CPU Cycles/Single Address Mode/BGUP = 1) Rev. 1.00 Sep. 19, 2008 Page 443 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) φ pin Last transfer cycle Bus cycle Bus release EXDMA single transfer cycle EXDMA single transfer cycle 1 cycle EXDMA single transfer cycle Other channel EXDMA cycle Bus release Original channel EDACK Original channel ETEND Other channel transfer request (EDREQ) Figure 8.34 Auto Request/Burst Mode/Normal Transfer Mode (Contention with Another Channel/Single Address Mode) Rev. 1.00 Sep. 19, 2008 Page 444 of 1270 REJ09B0466-0100 Bus release Section 8 EXDMA Controller (EXDMAC) (3) External Request/Cycle Steal Mode/Normal Transfer Mode In external request mode, an EXDMA transfer cycle is started a minimum of three cycles after a transfer request is accepted. The next transfer request is accepted after the end of a one-transferunit EXDMA cycle. For external bus space CPU cycles, at least two bus cycles are generated before the next EXDMA cycle. If a transfer request is generated for another channel, an EXDMA cycle for the other channel is generated before the next EXDMA cycle. The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The same applies to transfer request acceptance and transfer start timing. Figures 8.35 to 8.38 show operation timing examples for various conditions. φ pin EDREQ EDRAK 3 cycles Bus release Bus cycle EXDMA read EXDMA write Last transfer cycle Bus release EXDMA read EXDMA write Bus release ETEND EDA bit 1 0 Figure 8.35 External Request/Cycle Steal Mode/Normal Transfer Mode (No Contention/Dual Address Mode/Low Level Sensing) Rev. 1.00 Sep. 19, 2008 Page 445 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) φ pin EDREQ EDRAK 2 bus cycles Bus cycle CPU cycle CPU cycle CPU cycle External space CPU operation External space External space EXDMA single transfer cycle Last transfer cycle CPU cycle CPU cycle External space External space EXDMA single transfer cycle CPU cycle External space EDACK ETEND Figure 8.36 External Request/Cycle Steal Mode/Normal Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing) φ pin EDREQ EDRAK EDREQ acceptance internal processing state Edge confirmation Start of transfer processing Start of high level sensing Bus cycle Bus release EXDMA single transfer cycle Edge confirmation Start of transfer processing Bus release Start of high level sensing EXDMA single transfer cycle Edge confirmation Start of transfer processing Bus release Start of high level sensing EXDMA single transfer cycle EDACK Figure 8.37 External Request/Cycle Steal Mode/Normal Transfer Mode (No Contention/Single Address Mode/Falling Edge Sensing) Rev. 1.00 Sep. 19, 2008 Page 446 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) φ pin Original channel EDREQ Original channel EDRAK 1 cycle 3 cycles Bus cycle EXDMA transfer cycle Bus release EXDMA read 1 cycle Other channel transfer cycle EXDMA write Bus release EXDMA read EXDMA write Bus release Other channel EDREQ Other channel EDRAK Figure 8.38 External Request/Cycle Steal Mode/Normal Transfer Mode Contention with Another Channel/Dual Address Mode/Low Level Sensing (4) External Request/Cycle Steal Mode/Block Transfer Mode In block transfer mode, transfer of one block is performed continuously in the same way as in burst mode. The timing of the start of the next block transfer is the same as in normal transfer mode. If a transfer request is generated for another channel, an EXDMA cycle for the other channel is generated before the next block transfer. The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The same applies to transfer request acceptance and transfer start timing. Figures 8.39 to 8.44 show operation timing examples for various conditions. Rev. 1.00 Sep. 19, 2008 Page 447 of 1270 REJ09B0466-0100 REJ09B0466-0100 Rev. 1.00 Sep. 19, 2008 Page 448 of 1270 EDA bit ETEND Bus cycle EDRAK EDREQ φ pin 1 Bus release EXDMA read EXDMA write EXDMA read EXDMA write EXDMA read EXDMA write Last transfer in block Repeated 1-block-size transfer period Bus release 3 cycles EXDMA read EXDMA write Repeated EXDMA read 0 EXDMA write Bus release Last transfer cycle Last block Section 8 EXDMA Controller (EXDMAC) Figure 8.39 External Request/Cycle Steal Mode/Block Transfer Mode (No Contention/Dual Address Mode/Low Level Sensing/BGUP = 0) ETEND EDACK Bus cycle EDRAK EDREQ φ pin Bus release EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle Last transfer in block Repeated 1-block-size transfer period Bus release 3 cycles EXDMA single transfer cycle Repeated EXDMA single transfer cycle Bus release Last transfer cycle Last block Section 8 EXDMA Controller (EXDMAC) Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode (No Contention/Single Address Mode/Falling Edge Sensing/BGUP = 0) Rev. 1.00 Sep. 19, 2008 Page 449 of 1270 REJ09B0466-0100 REJ09B0466-0100 Rev. 1.00 Sep. 19, 2008 Page 450 of 1270 External space CPU operation ETEND EDACK CPU cycle Bus cycle EDRAK EDREQ φ pin External space CPU cycle External space CPU cycle External space EXDMA single transfer cycle Repeated EXDMA single transfer cycle Last transfer in block 1-block-size transfer period CPU cycle External space CPU cycle 2 bus cycles External space EXDMA single transfer cycle Repeated EXDMA single transfer cycle Last transfer in block 1-block-size transfer period CPU cycle Section 8 EXDMA Controller (EXDMAC) Figure 8.41 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 0) ETEND CPU operation Bus cycle EDRAK EDREQ φ pin External space CPU cycle External space CPU cycle External space CPU cycle External space EXDMA read EXDMA write CPU cycle 1 bus cycle External space EXDMA read EXDMA write CPU cycle 1 bus cycle External space CPU cycle 1 bus cycle Repeated EXDMA read 1-block-size transfer period External space EXDMA read EXDMA write Last transfer in block CPU cycle External space CPU cycle Section 8 EXDMA Controller (EXDMAC) Figure 8.42 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Dual Address Mode/Low Level Sensing/BGUP = 1) Rev. 1.00 Sep. 19, 2008 Page 451 of 1270 REJ09B0466-0100 REJ09B0466-0100 Rev. 1.00 Sep. 19, 2008 Page 452 of 1270 External space External space CPU operation ETEND EDACK CPU cycle CPU cycle Bus cycle EDRAK EDREQ φ pin External space CPU cycle External space EXDMA EXDMA transfer cycle transfer cycle CPU cycle 1 bus cycle External space EXDMA EXDMA transfer cycle transfer cycle CPU cycle 1 bus cycle External space Repeated EXDMA transfer cycle 1-block-size transfer period CPU cycle 1 bus cycle External space EXDMA EXDMA transfer cycle transfer cycle Last transfer in block CPU cycle External space CPU cycle Section 8 EXDMA Controller (EXDMAC) Figure 8.43 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 1) Other channel EDRAK Other channel EDREQ ETEND Bus cycle EDRAK EDREQ φ pin Bus release EXDMA read EXDMA write Repeated EXDMA read EXDMA write Last transfer in block 1-block-size transfer period Bus release Other channel EXDMA cycle Bus release EXDMA read EXDMA write Repeated EXDMA read EXDMA write Last transfer in block 1-block-size transfer period Section 8 EXDMA Controller (EXDMAC) Figure 8.44 External Request/Cycle Steal Mode/Block Transfer Mode (Contention with Another Channel/Dual Address Mode/Low Level Sensing) Rev. 1.00 Sep. 19, 2008 Page 453 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.4.12 Ending DMA Transfer The operation for ending DMA transfer depends on the transfer end conditions. When DMA transfer ends, the EDA bit in EDMDR changes from 1 to 0, indicating that DMA transfer has ended. (1) Transfer End by 1 → 0 Transition of EDTCR When the value of EDTCR changes from 1 to 0, DMA transfer ends on the corresponding channel and the EDA bit in EDMDR is cleared to 0. If the TCEIE bit in EDMDR is set at this time, a transfer end interrupt request is generated by the transfer counter and the IRF bit in EDMDR is set to 1. In block transfer mode, DMA transfer ends when the value of bits 15 to 0 in EDTCR changes from 1 to 0. DMA transfer does not end if the EDTCR value has been 0 since before the start of transfer. (2) Transfer End by Repeat Area Overflow Interrupt If an address overflows the repeat area when a repeat area specification has been made and repeat interrupts have been enabled (with the SARIE or DARIE bit in EDACR), a repeat area overflow interrupt is requested. DMA transfer ends, the EDA bit in EDMDR is cleared to 0, and the IRF bit in EDMDR is set to 1. In dual address mode, if a repeat area overflow interrupt is requested during a read cycle, the following write cycle processing is still executed. In block transfer mode, if a repeat area overflow interrupt is requested during transfer of a block, transfer continues to the end of the block. Transfer end by means of a repeat area overflow interrupt occurs between block-size transfers. (3) Transfer End by 0-Write to EDA Bit in EDMDR When 0 is written to the EDA bit in EDMDR by the CPU, etc., transfer ends after completion of the DMA cycle in which transfer is in progress or a transfer request was accepted. In block transfer mode, DMA transfer halts after completion of one-block-size transfer. The EDA bit in EDMDR is not cleared to 0 until all transfer processing has ended. Up to that point, the value of the EDA bit will be read as 1. Rev. 1.00 Sep. 19, 2008 Page 454 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (4) Transfer Abort by NMI Interrupt DMA transfer is aborted when an NMI interrupt is generated. The EDA bit is cleared to 0 in all channels. In external request mode, DMA transfer is performed for all transfer requests for which EDRAK has been output. In dual address mode, processing is executed for the write cycle following the read cycle. In block transfer mode, operation is aborted even in the middle of a block-size transfer. As the transfer is halted midway through a block, the BEF bit in EDMDR is set to 1 to indicate that the block transfer was not carried out normally. When transfer is aborted, register values are retained, and as the address registers indicate the next transfer addresses, transfer can be resumed by setting the EDA bit to 1 in EDMDR. If the BEF bit is 1 in EDMDR, transfer can be resumed from midway through a block. (5) Hardware Standby Mode and Reset Input The EXDMAC is initialized in hardware standby mode and by a reset. DMA transfer is not guaranteed in these cases. 8.4.13 Relationship between EXDMAC and Other Bus Masters The read and write operations in a DMA transfer cycle are indivisible, and a refresh cycle, external bus release cycle, or internal bus master (CPU, DTC, or DMAC) external space access cycle never occurs between the two. When read and write cycles occur consecutively, as in burst transfer or block transfer, a refresh or external bus release state may be inserted after the write cycle. As the internal bus masters are of lower priority than the EXDMAC, external space accesses by internal bus masters are not executed until the EXDMAC releases the bus. The EXDMAC releases the bus in the following cases: 1. 2. 3. 4. 5. When DMA transfer is performed in cycle steal mode When switching to a different channel When transfer ends in burst transfer mode When transfer of one block ends in block transfer mode When burst transfer or block transfer is performed with the BGUP bit in EDMDR set to 1 (however, the bus is not released between read and write cycles) Rev. 1.00 Sep. 19, 2008 Page 455 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.5 Interrupt Sources EXDMAC interrupt sources are a transfer end indicated by the transfer counter, and repeat area overflow interrupts. Table 8.4 shows the interrupt sources and their priority order. Table 8.4 Interrupt Sources and Priority Order Interrupt Interrupt source Interrupt Priority EXDMTEND2 Transfer end indicated by channel 2 transfer counter High Channel 2 source address repeat area overflow Channel 2 destination address repeat area overflow EXDMTEND3 Transfer end indicated by channel 3 transfer counter Channel 3 source address repeat area overflow Channel 3 destination address repeat area overflow Low Interrupt sources can be enabled or disabled by means of the EDIE bit in EDMDR for the relevant channel, and can be sent to the interrupt controller independently. The relative priority order of the channels is determined by the interrupt controller (see table 8.4). Figure 8.45 shows the transfer end interrupt logic. A transfer end interrupt is generated whenever the EDIE bit is set to 1 while the IRF bit is set to 1 in EDMDR. IRF bit Transfer end interrupt EDIE bit Figure 8.45 Transfer End Interrupt Logic Interrupt source settings are made individually with the interrupt enable bits in the registers for the relevant channels. The transfer counter’s transfer end interrupt is enabled or disabled by means of the TCEIE bit in EDMDR, the source address register repeat area overflow interrupt by means of the SARIE bit in EDACR, and the destination address register repeat area overflow interrupt by means of the DARIE bit in EDACR. When an interrupt source occurs while the corresponding interrupt enable bit is set to 1, the IRF bit in EDMDR is set to 1. The IRF bit is set by all interrupt sources indiscriminately. Rev. 1.00 Sep. 19, 2008 Page 456 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) The transfer end interrupt can be cleared either by clearing the IRF bit to 0 in EDMDR within the interrupt handling routine, or by re-setting the transfer counter and address registers and then setting the EDA bit to 1 in EDMDR to perform transfer continuation processing. An example of the procedure for clearing the transfer end interrupt and restarting transfer is shown in figure 8.46. Transfer end interrupt exception handling routine Transfer restart after end of interrupt handling routine Transfer continuation processing Change register settings [1] Clear IRF bit to 0 [4] Write 1 to EDA bit [2] End of interrupt handling routine [5] End of interrupt handling routine (RTE instruction execution) [3] Change register settings [6] Write 1 to EDA bit [7] End of transfer restart processing End of transfer restart processing [1] Write set values to the registers (transfer counter, address registers, etc.). [2] Write 1 to the EDA bit in EDMDR to restart EXDMA operation. When 1 is written to the EDA bit, the IRF bit in EDMDR is automatically cleared to 0 and the interrupt source is cleared. [3] The interrupt handling routine is ended with an RTE instruction, etc. [4] Clear the IRF bit to 0 in EDMDR by first reading 1 from it, then writing 0. [5] After the interrupt handling routine is ended with an RTE instruction, etc., interrupt masking is cleared. [6] Write set values to the registers (transfer counter, address registers, etc.). [7] Write 1 to the EDA bit in EDMDR to restart EXDMA operation. Figure 8.46 Example of Procedure for Restarting Transfer on Channel in which Transfer End Interrupt Occurred Rev. 1.00 Sep. 19, 2008 Page 457 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.6 (1) Usage Notes EXDMAC Register Access during Operation Except for clearing the EDA bit to 0 in EDMDR, settings should not be changed for a channel in operation (including the transfer standby state). Transfer must be disabled before changing a setting for an operational channel. (2) Module Stop State When the MSTP14 bit is set to 1 in MSTPCRH, the EXDMAC clock stops and the EXDMAC enters the module stop state. However, 1 cannot be written to the MSTP14 bit when any of the EXDMAC’s channels is enabled for transfer, or when an interrupt is being requested. Before setting the MSTP14 bit, first clear the EDA bit in EDMDR to 0, then clear the IRF or EDIE bit in EDMDR to 0. When the EXDMAC clock stops, EXDMAC registers can no longer be accessed. The following EXDMAC register settings remain valid in the module stop state, and so should be changed, if necessary, before making the module stop transition. • ETENDE = 1 in EDMDR (ETEND pin enable) • EDRAKE = 1 in EDMDR (EDRAK pin enable) • AMS = 1 in EDMDR (EDACK pin enable) (3) EDREQ Pin Falling Edge Activation Falling edge sensing on the EDREQ pin is performed in synchronization with EXDMAC internal operations, as indicated below. [1] Activation request standby state: Waits for low level sensing on EDREQ pin, then goes to [2]. [2] Transfer standby state: Waits for EXDMAC data transfer to become possible, then goes to [3]. [3] Activation request disabled state: Waits for high level sensing on EDREQ pin, then goes to [1]. After EXDMAC transfer is enabled, the EXDMAC goes to state [1], so low level sensing is used for the initial activation after transfer is enabled. Rev. 1.00 Sep. 19, 2008 Page 458 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (4) Activation Source Acceptance At the start of activation source acceptance, low level sensing is used for both falling edge sensing and low level sensing on the EDREQ pin. Therefore, a request is accepted in the case of a low level at the EDREQ pin that occurs before execution of the EDMDR write for setting the transferenabled state. When the EXDMAC is activated, make sure, if necessary, that a low level does not remain at the EDREQ pin from the previous end of transfer, etc. (5) Enabling Interrupt Requests when IRF = 1 in EDMDR When transfer is started while the IRF bit is set to 1 in EDMDR, if the EDIE bit is set to 1 in EDMDR together with the EDA bit in EDMDR, enabling interrupt requests, an interrupt will be requested since EDIE = 1 and IRF = 1. To prevent the occurrence of an erroneous interrupt request when transfer starts, ensure that the IRF bit is cleared to 0 before the EDIE bit is set to 1. (6) ETEND Pin and CBR Refresh Cycle If the last EXDMAC transfer cycle and a CBR refresh cycle occur simultaneously, note that although the CBR refresh and the last transfer cycle may be executed consecutively, ETEND may also go low in this case for the refresh cycle. Rev. 1.00 Sep. 19, 2008 Page 459 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 460 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) Section 9 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 9.1 shows a block diagram of the DTC. 9.1 Features • Transfer possible over any number of channels • Three transfer modes 1. Normal mode One operation transfers one byte or one word of data. Memory address is incremented or decremented by 1 or 2. From 1 to 65,536 transfers can be specified. 2. Repeat mode One operation transfers one byte or one word of data. Memory address is incremented or decremented by 1 or 2. Once the specified number of transfers (1 to 256) has ended, the initial state is restored, and transfer is repeated. 3. Block transfer mode One operation transfers one block of data. The block size is 1 to 256 bytes or words. From 1 to 65,536 transfers can be specified. Either the transfer source or the transfer destination is designated as a block area. • One activation source can trigger a number of data transfers (chain transfer) • Direct specification of 16-Mbyte address space possible • Activation by software is possible • Transfer can be set in byte or word units • A CPU interrupt can be requested for the interrupt that activated the DTC • Module stop mode can be set Rev. 1.00 Sep. 19, 2008 Page 461 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) The DTC's register information is stored in the on-chip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to the on-chip RAM (1 Kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. Internal address bus Internal data bus CPU interrupt request Legend: MRA, MRB CRA, CRB SAR DAR DTCERA to DTCERI DTVECR DTCCR : DTC mode registers A and B : DTC transfer count registers A and B : DTC source address register : DTC destination address register : DTC enable registers A to I : DTC vector register : DTC control register Figure 9.1 Block Diagram of DTC Rev. 1.00 Sep. 19, 2008 Page 462 of 1270 REJ09B0466-0100 Register information MRA MRB CRA CRB DAR SAR DTC activation request On-chip RAM Control logic DTC DTCCR Interrupt request DTVECR DTCERA to DTCERI Interrupt controller Section 9 Data Transfer Controller (DTC) 9.2 Register Descriptions DTC has the following registers. • • • • • • DTC mode register A (MRA) DTC mode register B (MRB) DTC source address register (SAR) DTC destination address register (DAR) DTC transfer count register A (CRA) DTC transfer count register B (CRB) These six registers cannot be directly accessed from the CPU. When activated, the DTC reads a set of register information that is stored in an on-chip RAM to the corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated register information back to the RAM. • DTC enable registers A to I (DTCERA to DTCERI) • DTC vector register (DTVECR) • DTC control register (DTCCR) 9.2.1 DTC Mode Register A (MRA) MRA selects the DTC operating mode. Bit Bit Name Initial Value R/W Description 7 SM1 Undefined — Source Address Mode 1 and 0 6 SM0 Undefined — These bits specify an SAR operation after a data transfer. 0×: SAR is fixed 10: SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 11: SAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) Rev. 1.00 Sep. 19, 2008 Page 463 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) Bit Bit Name Initial Value R/W Description 5 DM1 Undefined — Destination Address Mode 1 and 0 4 DM0 Undefined — These bits specify a DAR operation after a data transfer. 0×: DAR is fixed 10: DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 11: DAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) 3 MD1 Undefined — DTC Mode 2 MD0 Undefined — These bits specify the DTC transfer mode. 00: Normal mode 01: Repeat mode 10: Block transfer mode 11: Setting prohibited 1 DTS Undefined — DTC Transfer Mode Select Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. 0: Destination side is repeat area or block area 1: Source side is repeat area or block area 0 Sz Undefined — DTC Data Transfer Size Specifies the size of data to be transferred. 0: Byte-size transfer 1: Word-size transfer Legend: × : Don't care Rev. 1.00 Sep. 19, 2008 Page 464 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.2.2 DTC Mode Register B (MRB) MRB selects the DTC operating mode. Bit Bit Name Initial Value R/W Description 7 CHNE Undefined — DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, refer to section 9.5.4, Chain Transfer. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the activation source flag, and clearing of DTCER is not performed. 6 DISEL Undefined — DTC Interrupt Select When this bit is set to 1, a CPU interrupt request is generated every time after a data transfer ends. When this bit is set to 0, a CPU interrupt request is generated at the time when the specified number of data transfer ends. 5 CHNS Undefined — DTC Chain Transfer Select Specifies the chain transfer condition. 0: Chain transfer every time 1: Chain transfer only when transfer counter = 0 4 to 0 — Undefined — Reserved These bits have no effect on DTC operation, and should always be written with 0. 9.2.3 DTC Source Address Register (SAR) SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 9.2.4 DTC Destination Address Register (DAR) DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. Rev. 1.00 Sep. 19, 2008 Page 465 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.2.5 DTC Transfer Count Register A (CRA) CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. 9.2.6 DTC Transfer Count Register B (CRB) CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. The CRB is not available in normal and repeat modes. Rev. 1.00 Sep. 19, 2008 Page 466 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.2.7 DTC Enable Registers A to I (DTCERA to DTCERI) DTCER which is comprised of registers, DTCERA to DTCERI, is a register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is shown in table 9.2. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. Bit Bit Name Initial Value R/W Description 7 DTCE7 0 R/W DTC Activation Enable 6 DTCE6 0 R/W 5 DTCE5 0 R/W Setting this bit to 1 specifies a relevant interrupt source to a DTC activation source. 4 DTCE4 0 R/W 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTCE0 0 R/W [Clearing conditions] • When the DISEL bit is 1 and the data transfer has ended • When the specified number of transfers have ended These bits are not automatically cleared when the DISEL bit is 0 and the specified number of transfers have not ended • 9.2.8 When 0 is written to DTCE after reading DTCE = 1 DTC Vector Register (DTVECR) DTVECR sets a vector number for the software activation interrupt. Bit Bit Name Initial Value R/W Description 7 DTVEC7 0 R/W DTC Software Activation Vectors 7 to 0 6 DTVEC6 0 R/W 5 DTVEC5 0 R/W These bits specify a vector number for DTC software activation. 4 DTVEC4 0 R/W 3 DTVEC3 0 R/W 2 DTVEC2 0 R/W 1 DTVEC1 0 R/W 0 DTVEC0 0 R/W The vector address is expressed as H'0400 + (vector number × 2). For example, when DTVEC7 to DTVEC0 = H'10, the vector address is H'0420. These bits can be written to only when the SWDTE bit is 0. Rev. 1.00 Sep. 19, 2008 Page 467 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.2.9 DTC Control Register (DTCCR) DTCCR enables or disables DTC activation by software. Bit Bit Name Initial Value R/W Description 7 SWDTE 0 R/W DTC Software Activation Enable Setting this bit to 1 activates the DTC. Only 1 can be written to this bit. [Clearing conditions] • When the DISEL bit is 0 and the specified number of transfers have not ended • When 0 is written to the DISEL bit after a software-activated data transfer end interrupt (SWDTEND) request has been sent to the CPU. When the DISEL bit is 1 and data transfer has ended or when the specified number of transfers have ended, this bit will not be cleared. 6 to 0 — All 0 R Reserved These bits are always read as 0 and cannot be modified. Rev. 1.00 Sep. 19, 2008 Page 468 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.3 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR or DTCCR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared. The activation source flag, in the case of RXI0, for example, is the RDRF flag of SCI_0. When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities. Table 9.1 shows a relationship between activation sources and DTCER clear conditions. Figure 9.2 shows a block diagram of activation source control. For details see section 5, Interrupt Controller. Table 9.1 Relationship between Activation Sources and DTCER Clearing Activation Source DISEL = 0 and Specified Number of Transfers Has Not Ended DISEL = 1 or Specified Number of Transfers Has Ended Activation by software SWDTE bit is cleared to 0 • SWDTE bit remains set to 1 • Interrupt request to CPU Activation by an interrupt • Corresponding DTCER bit remains set to 1. • Corresponding DTCER bit is cleared to 0. • Activation source flag is cleared to 0. • Activation source flag remains set to 1. • Interrupt that became the activation source is requested to the CPU. Rev. 1.00 Sep. 19, 2008 Page 469 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) Source flag cleared Clear controller Clear DTCER On-chip peripheral modules IRQ interrupt Interrupt request Selection circuit Select DTVECR DTCCR Clear request DTC CPU Interrupt controller Interrupt mask Figure 9.2 Block Diagram of DTC Activation Source Control Rev. 1.00 Sep. 19, 2008 Page 470 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.4 Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'FFBC00 to H'FFBFFF). Register information should be located at the address that is multiple of four within the range. Locating the register information in address space is shown in figure 9.3. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information. In the case of chain transfer, register information should be located in consecutive areas as shown in figure 9.3 and the register information start address should be located at the corresponding vector address to the activation source. Figure 9.4 shows correspondences between the DTC vector address and register information. The DTC reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[7:0] × 2). For example, if DTVECR is H'10, the vector address is H'0420. The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte unit being used in both cases. These two bytes specify the lower bits of the register information start address. Note: * Not available in this LSI. Lower addresses 0 Start address of register information 1 2 MRA SAR MRB DAR 3 Register information CRB CRA Chain transfer MRA SAR MRB DAR CRB CRA Register information for second transfer in case of chain transfer Four bytes Figure 9.3 Correspondence between DTC Vector Address and Register Information Rev. 1.00 Sep. 19, 2008 Page 471 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) DTC vector address Register information start address Register information Chain transfer Figure 9.4 Correspondence between DTC Vector Address and Register Information Table 9.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Activation Source Activation Source Vector Number DTC Vector Address Software Write to DTVECR DTVECR H'0400 + (DTVECR[7:0] × 2) — External pin IRQ0 16 H'0420 DTCEA7 IRQ1 17 H'0422 DTCEA6 IRQ2 18 H'0424 DTCEA5 IRQ3 19 H'0426 DTCEA4 IRQ4 20 H'0428 DTCEA3 IRQ5 21 H'042A DTCEA2 IRQ6 22 H'042C DTCEA1 IRQ7 23 H'042E DTCEA0 IRQ8*2 24 H'0430 DTCEB7 2 IRQ9* 25 H'0432 DTCEB6 26 H'0434 DTCEB5 2 17 H'0436 DTCEB4 2 18 H'0438 DTCEB3 2 19 H'043A DTCEB2 2 30 H'043C DTCEB1 IRQ11* IRQ12* IRQ13* IRQ14* 2 IRQ15* 31 H'043E DTCEB0 ADI0 38 H'044C DTCEC6 Rev. 1.00 Sep. 19, 2008 Page 472 of 1270 REJ09B0466-0100 1 2 IRQ10* A/D_0 DTCE* Priority High Low Section 9 Data Transfer Controller (DTC) Origin of Activation Source Activation Source Vector Number DTC Vector Address DTCE* TPU_0 TGI0A 40 H'0450 DTCEC5 TGI0B 41 H'0452 DTCEC4 TGI0C 42 H'0454 DTCEC3 TGI0D 43 H'0456 DTCEC2 TGI1A 48 H'0460 DTCEC1 TGI1B 49 H'0462 DTCEC0 TGI2A 52 H'0468 DTCED7 TGI2B 53 H'046A DTCED6 TGI3A 56 H'0470 DTCED5 TGI3B 57 H'0472 DTCED4 TGI3C 58 H'0474 DTCED3 TGI3D 59 H'0476 DTCED2 TGI4A 64 H'0480 DTCED1 TGI4B 65 H'0482 DTCED0 TGI5A 68 H'0488 DTCEE7 TGI5B 69 H'048A DTCEE6 CMIA0 72 H'0490 DTCEE3 CMIB0 73 H'0492 DTCEE2 CMIA1 76 H'0498 DTCEE1 CMIB1 77 H'049A DTCEE0 DMTEND0A 80 H'04A0 DTCEF7 DMTEND0B 81 H'04A2 DTCEF6 DMTEND1A 82 H'04A4 DTCEF5 DMTEND1B 83 H'04A6 DTCEF4 RXI0 89 H'04B2 DTCEF3 TXI0 90 H'04B4 DTCEF2 TPU_1 TPU_2 TPU_3 TPU_4 TPU_5 TMR_0 TMR_1 DMAC SCI_0 SCI_1 SCI_2 1 RXI1 93 H'04BA DTCEF1 TXI1 94 H'04BC DTCEF0 RXI2 97 H'04C2 DTCEG7 TXI2 98 H'04C4 DTCEG6 Priority High Low Rev. 1.00 Sep. 19, 2008 Page 473 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) Origin of Activation Source Activation Source Vector Number DTC Vector Address DTCE* SCI_3 RXI3 101 H'04CA DTCEF5 TXI3 102 H'04CC DTCEF4 SCI_4 1 RXI4 105 H'04D2 DTCEG3 TXI4 106 H'04D4 DTCEG2 A/D_1 ADI1 112 H'04E0 DTCEG1 TPU_6 TGI6A 120 H'04F0 DTCEG0 TGI6B 121 H'04F2 DTCEH7 TGI6C 122 H'04F4 DTCEH6 TGI6D 123 H'04F6 DTCEH5 TPU_7 TGI7A 125 H'04FA DTCEH4 TGI7B 126 H'04FC DTCEH3 TPU_8 TGI8A 129 H'0502 DTCEH2 TGI8B 130 H'0504 DTCEH1 TGI9A 133 H'050A DTCEH0 TGI9B 134 H'050C DTCEI7 TGI9C 135 H'050E DTCEI6 TGI9D 136 H'0510 DTCEI5 TGI10A 138 H'0514 DTCEI4 TGI10B 139 H'0516 DTCEI3 TGI11A 142 H'051C DTCEI2 TGI11B 143 H'051E DTCEI1 TPU_9 TPU_10 TPU_11 Priority High Low Notes: 1. DTCE bits with no corresponding interrupt are reserved, and 0 should be written to. When clearing the software standby state or all-module-clocks-stop mode with an interrupt, write 0 to the corresponding DTCE bit. 2. Not supported by the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 474 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.5 Operation The DTC stores register information in the on-chip RAM. When activated, the DTC reads register information that is already stored in the on-chip RAM and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to the onchip RAM. Pre-storage of register information in the on-chip RAM makes it possible to transfer data over any required number of channels. There are three transfer modes: normal mode, repeat mode, and block transfer mode. Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single activation (chain transfer). A setting can also be made to have chain transfer performed only when the transfer counter value is 0. This enables DTC re-setting to be performed by the DTC itself. The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed. Figure 9.5 shows a flowchart of DTC operation, and table 9.3 summarizes the chain transfer conditions (combinations for performing the second and third transfers are omitted). Rev. 1.00 Sep. 19, 2008 Page 475 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE = 1? Yes No CHNS = 0? Yes Transfer counter = 0 or DISEL = 1? No Yes No Transfer counter = 0? Yes No DISEL = 1? Yes No Clear activation flag Clear DTCER End Interrupt exception handling Figure 9.5 Flowchart of DTC Operation Rev. 1.00 Sep. 19, 2008 Page 476 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) Table 9.3 Chain Transfer Conditions 1st Transfer 2nd Transfer CHNE CHNS DISEL CR CHNE CHNS DISEL CR DTC Transfer 0 — 0 Not 0 — — — — Ends at 1st transfer 0 — 0 0 — — — — Ends at 1st transfer 0 — 1 — — — — — Interrupt request to CPU 1 0 — — 0 — 0 Not 0 Ends at 2nd transfer 0 — 0 0 Ends at 2nd transfer 0 — 1 — Interrupt request to CPU 1 1 0 Not 0 — — — — Ends at 1st transfer 1 1 — 0 0 — 0 Not 0 Ends at 2nd transfer 0 — 0 0 Ends at 2nd transfer 0 — 1 — Interrupt request to CPU — — — — Ends at 1st transfer 1 1 1 Not 0 Interrupt request to CPU Rev. 1.00 Sep. 19, 2008 Page 477 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.5.1 Normal Mode In normal mode, one operation transfers one byte or one word of data. Table 9.4 lists the register function in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has ended, a CPU interrupt can be requested. Table 9.4 Register Function in Normal Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination address DTC transfer count register A CRA Designates transfer count DTC transfer count register B CRB Not used SAR DAR Transfer Figure 9.6 Memory Mapping in Normal Mode Rev. 1.00 Sep. 19, 2008 Page 478 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.5.2 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. Table 9.5 lists the register function in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers has ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 9.5 Register Function in Repeat Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination address DTC transfer count register AH CRAH Holds number of transfers DTC transfer count register AL CRAL Designates transfer count DTC transfer count register B CRB Not used SAR or DAR DAR or SAR Repeat area Transfer Figure 9.7 Memory Mapping in Repeat Mode Rev. 1.00 Sep. 19, 2008 Page 479 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.5.3 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 9.6 lists the register function in block transfer mode. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has ended, a CPU interrupt is requested. Table 9.6 Register Function in Block Transfer Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination address DTC transfer count register AH CRAH Holds block size DTC transfer count register AL CRAL Designates block size count DTC transfer count register B CRB Designates transfer count First block SAR or DAR Block area Transfer Nth block Figure 9.8 Memory Mapping in Block Transfer Mode Rev. 1.00 Sep. 19, 2008 Page 480 of 1270 REJ09B0466-0100 DAR or SAR Section 9 Data Transfer Controller (DTC) 9.5.4 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 9.9 shows the operation of chain transfer. When activated, the DTC reads the register information start address stored at the vector address, and then reads the first register information at that start address. The CHNE bit in MRB is checked after the end of data transfer, if the value is 1, the next register information, which is located consecutively, is read and transfer is performed. This operation is repeated until the end of data transfer of register information with CHNE = 0. It is also possible, by setting both the CHNE bit and CHNS bit to 1, to specify execution of chain transfer only when the transfer counter value is 0. In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected. Source Destination Register information CHNE=1 DTC vector address Register information start address Register information CHNE=0 Source Destination Figure 9.9 Operation of Chain Transfer Rev. 1.00 Sep. 19, 2008 Page 481 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.5.5 Interrupt Sources An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control. In the case of activation by software, a software activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers has ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine should clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1. 9.5.6 Operation Timing φ DTC activation request DTC request Vector read Data transfer Address Read Write Transfer information read Transfer information write Figure 9.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) Rev. 1.00 Sep. 19, 2008 Page 482 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) φ DTC activation request DTC request Data transfer Vector read Read Write Read Write Address Transfer information read Transfer information write Figure 9.11 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) φ DTC activation request DTC request Data transfer Data transfer Read Write Read Write Vector read Address Transfer information read Transfer information write Transfer information read Transfer information write Figure 9.12 DTC Operation Timing (Example of Chain Transfer) 9.5.7 Number of DTC Execution States Table 9.7 lists execution status for a single DTC data transfer, and table 9.8 shows the number of states required for each execution status. Rev. 1.00 Sep. 19, 2008 Page 483 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) Table 9.7 DTC Execution Status Mode Vector Read I Register Information Read/Write Data Read J K Data Write L Internal Operations M Normal 1 6 1 1 3 Repeat 1 6 1 1 3 Block transfer 1 6 N N 3 Legend: N: Block size (initial setting of CRAH and CRAL) Table 9.8 Number of States Required for Each Execution Status OnChip RAM Object to be Accessed OnChip On-Chip I/O ROM Registers Bus width 32 16 8 16 Access states 1 1 2 2 Execution status Vector read External Devices 8 16 2 3 2 3 SI — 1 — — 4 6+2m 2 3+m Register information read/write SJ 1 — — — — — — — Byte data read SK 1 1 2 2 2 3+m 2 3+m Word data read SK 1 1 4 2 4 6+2m 2 3+m Byte data write SL 1 1 2 2 2 3+m 2 3+m Word data write SL 1 1 4 2 4 6+2m 2 3+m Internal operation SM 1 The number of execution states is calculated from the formula below. Note that Σ means the sum of all transfers activated by one activation event (the number in which the CHNE bit is set to 1, plus 1). Number of execution states = I · SI + Σ (J · SJ + K · SK + L · SL) + M · SM For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from the on-chip ROM to an internal I/O register, the time required for the DTC operation is 13 states. The time from activation to the end of the data write is 10 states. Rev. 1.00 Sep. 19, 2008 Page 484 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.6 Procedures for Using DTC 9.6.1 Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. 2. 3. 4. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. Set the start address of the register information in the DTC vector address. Set the corresponding bit in DTCER to 1. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. 5. After the end of one data transfer, or after the specified number of data transfers have ended, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. 9.6.2 Activation by Software The procedure for using the DTC with software activation is as follows: 1. 2. 3. 4. 5. 6. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. Set the start address of the register information in the DTC vector address. Check that the SWDTE bit is 0. Write 1 to SWDTE bit and the vector number to DTVECR. Check the vector number written to DTVECR. After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the SWDTE bit is held at 1 and a CPU interrupt is requested. Rev. 1.00 Sep. 19, 2008 Page 485 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.7 Examples of Use of the DTC 9.7.1 Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the SCI RDR address in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. 2. Set the start address of the register information at the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine should perform wrap-up processing. Rev. 1.00 Sep. 19, 2008 Page 486 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.7.2 Chain Transfer An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to NDR of the PPG is performed in the first half of the chain transfer, and normal mode transfer to the TPU's TGR in the second half. This is because clearing of the activation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the chain transfer (transfer when CHNE = 0). 1. Perform settings for transfer to NDR of the PPG. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0, MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value. 2. Perform settings for transfer to the TPU's TGR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0 = 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address in DAR, and the data table size in CRA. CRB can be set to any value. 3. Locate the TPU transfer register information consecutively after the NDR transfer register information. 4. Set the start address of the NDR transfer register information to the DTC vector address. 5. Set the bit corresponding to TGIA in DTCER to 1. 6. Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA interrupt with TIER. 7. Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to be used as the output trigger. 8. Set the CST bit in TSTR to 1, and start the TCNT count operation. 9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the set value of the next output trigger period is transferred to TGRA. The activation source TGFA flag is cleared. 10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the CPU. Termination processing should be performed in the interrupt handling routine. Rev. 1.00 Sep. 19, 2008 Page 487 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.7.3 Chain Transfer when Counter = 0 By executing a second data transfer, and performing re-setting of the first data transfer, only when the counter value is 0, it is possible to perform 256 or more repeat transfers. An example is shown in which a 128-Kbyte input buffer is configured. The input buffer is assumed to have been set to start at lower address H'0000. Figure 9.13 shows the chain transfer when the counter value is 0. 1. For the first transfer, set the normal mode for input data. Set fixed transfer source address (G/A, etc.), CRA = H'0000 (65,536 times), and CHNE = 1, CHNS = 1, and DISEL = 0. 2. Prepare the upper 8-bit addresses of the start addresses for each of the 65,536 transfer start addresses for the first data transfer in a separate area (in ROM, etc.). For example, if the input buffer comprises H'200000 to H'21FFFF, prepare H'21 and H'20. 3. For the second transfer, set repeat mode (with the source side as the repeat area) for re-setting the transfer destination address for the first data transfer. Use the upper 8 bits of DAR in the first register information area as the transfer destination. Set CHNE = DISEL = 0. If the above input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2. 4. Execute the first data transfer 65,536 times by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of the transfer source address for the first data transfer to H'21. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 5. Next, execute the first data transfer the 65,536 times specified for the first data transfer by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of the transfer source address for the first data transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer, an interrupt request is not sent to the CPU. Rev. 1.00 Sep. 19, 2008 Page 488 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) Input circuit Input buffer First data transfer register information Chain transfer (counter = 0) Second data transfer register information Upper 8 bits of DAR Figure 9.13 Chain Transfer when Counter = 0 Rev. 1.00 Sep. 19, 2008 Page 489 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.7.4 Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. 2. Set the start address of the register information at the DTC vector address (H'04C0). 3. Check that the SWDTE bit in DTCCR is 0. Check that there is currently no transfer activated by software. 4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'60. 5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. 6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. 7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform other wrap-up processing. Rev. 1.00 Sep. 19, 2008 Page 490 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.8 Usage Notes 9.8.1 Module Stop Mode Setting DTC operation can be disabled or enabled using the module stop control register. The initial setting is for DTC operation to be enabled. Register access is disabled by setting module stop mode. Module stop mode cannot be set while the DTC is activated. For details, refer to section 24, Power-Down Modes. 9.8.2 On-Chip RAM The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0. 9.8.3 DTCE Bit Setting For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are disabled, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. 9.8.4 DMAC Transfer End Interrupt When DTC transfer is activated by a DMAC transfer end interrupt, regardless of the transfer counter and DISEL bit, the DMAC's DTE bit is not subject to DTC control, and the write data has priority. Consequently, an interrupt request may not be sent to the CPU when the DTC transfer counter reaches 0. 9.8.5 Chain Transfer When chain transfer is used, clearing of the activation source or DTCER is performed when the last of the chain of data transfers is executed. SCI and high-speed A/D converter interrupt/activation sources, on the other hand, are cleared when the DTC reads or writes to the prescribed register. Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the relevant register is not included in the last chained data transfer, the interrupt or activation source will be retained. Rev. 1.00 Sep. 19, 2008 Page 491 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 492 of 1270 REJ09B0466-0100 Section 10 I/O Ports Section 10 I/O Ports Table 10.1 summarizes the port functions of the H8S/2426 Group and H8S/2426R Group. Table 10.2 summarizes the port functions of the H8S/2424 Group. The pins of each port also have other functions such as input/output or external interrupt input pins of on-chip peripheral modules. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, a port register (PORT) used to read the pin states, and a port function control register (PFCR) used to set input/output destination. Before enabling each input/output pins, select the input/output destination by PFCR. The input-only ports do not have a DR or DDR register. Ports A to E have a built-in pull-up MOS function and a pull-up MOS control register (PCR) to control the on/off state of the input pull-up MOS. Ports 1 to 3, 5 to 8, and A to J include an open-drain control register (ODR) that controls the on/off state of the output buffer PMOS. Ports 1 to 3, 5 (P50 to P53), 6, and 8 can drive a single TTL load and 30-pF capacitive load. Ports A to H can drive a single TTL load and 50-pF capacitive load. All of the I/O ports can drive a Darlington transistor when outputting data. Ports 1 and 2 are Schmitt-triggered inputs. • H8S/2426 Group and H8S/2426R Group Ports 5 (P50 to P52), 8 (P81, P83, and P85), B, and C are Schmitt-triggered inputs when used as TPU inputs. Ports 2, 5, 6, 8, A (PA4 to PA7), F (PF1 and PF2), and H (PH2 and PH3) are Schmitt-triggered inputs when used as IRQ inputs. Ports 3 (P32 to P35) and 5 (P50 and P51) are Schmitt-triggered inputs when used as I2C inputs. Ports 5 (P50 and P51), 6 (P60 to P63), and 8 (P81 and P83) are Schmitt-triggered inputs when used as 8-bit timer inputs. • H8S/2424 Group Ports 5 (P50 to P52), 8 (P81, P83, and P85), B, and C are Schmitt-triggered inputs when used as TPU inputs. Ports 4, 5, 8, and A (PA4 to PA7) are Schmitt-triggered inputs when used as IRQ inputs. Ports 3 (P32 to P35) and 5 (P50 and P51) are Schmitt-triggered inputs when used as I2C inputs. Ports 2 (P20 to P23), 5 (P50 and P51), and 8 (P81 and P83) are Schmitt-triggered inputs when used as 8-bit timer inputs. Rev. 1.00 Sep. 19, 2008 Page 493 of 1270 REJ09B0466-0100 Section 10 I/O Ports Table 10.1 Port Functions of H8S/2426 Group and H8S/2426R Group Mode 7 Port Description Port 1 General I/O port also functioning as PPG outputs, TPU I/Os, EXDMAC outputs, and SSU I/Os Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 P17/PO15/TIOCB2/TCLKD/EDRAK3/SCS0-A P17/PO15/TIOCB2/ TCLKD/SCS0-A P16/PO14/TIOCA2/EDRAK2/SSCK0-A P16/PO14/TIOCA2/ SSCK0-A P15/PO13/TIOCB1/TCLKC/SSI0-A Input/ Output Type Schmitt-triggered inputs when used as general input port and TPU inputs. Open-drain output capability. P14/PO12/TIOCA1/SSO0-A P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0 P10/PO8/TIOCA0 Port 2 General I/O port also functioning as PPG outputs, TPU I/Os, interrupt inputs, SCI I/Os, I2C I/Os, A/D converter inputs, and bus control signal I/Os P27/IRQ15-B/PO7/TIOCB5/SCL2 P26/IRQ14-B/PO6/TIOCA5/SDA2/ADTRG1 P25/WAIT-B/IRQ13-B/PO5-A/TIOCB4-A P25/IRQ13-B/PO5-A/ TIOCB4-A P24/IRQ12-B/PO4-A/TIOCA4-A/RxD4-A Schmitt-triggered inputs when used as general input port, TPU inputs, interrupt inputs, and I2C inputs. Open-drain output capability. P23/IRQ11-B/PO3-A/TIOCD3-A/TxD4-A P22/IRQ10-B/PO2-A/TIOCC3-A 5-V tolerance. P21/IRQ9-B/PO1-A/TIOCB3-A P20/IRQ8-B/PO0-A/TIOCA3-A Port 3 General I/O port also functioning as SCI I/Os, I2C I/Os, and bus control signal I/Os P35/OE-B/CKE-B*1/SCK1/SCL0 P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD P35/SCK1/SCL0 Open-drain output capability. Only P32 to P35 are Schmitttriggered inputs when used as I2C inputs. P32 to P35 have 5-V tolerance. Port 4 General I/O port also functioning as A/D converter analog inputs P47/AN7_0 P46/AN6_0 P45/AN5_0 P44/AN4_0 P43/AN3_0 P42/AN2_0 P41/AN1_0 P40/AN0_0 Rev. 1.00 Sep. 19, 2008 Page 494 of 1270 REJ09B0466-0100 Section 10 I/O Ports Mode 7 Port Description Port 5 General I/O port also functioning as interrupt inputs, A/D converter inputs, SCI I/Os, PPG outputs, TPU I/Os, TMR I/Os, I2C I/Os, bus control signal I/Os, and JTAG inputs Port 6 General I/O port also functioning as interrupt inputs, TMR I/Os, and DMAC I/Os Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 P53/IRQ3-A/ADTRG0-A/TRST*3 P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/ TMO0-B/SCK2 P52/IRQ2-A/PO4-B/ TIOCA4-B/TMO0-B/ SCK2 P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/ TMCI0-B/RxD2/SCL3 P51/IRQ1-A/PO2-B/ TIOCC3-B/TMCI0-B/ RxD2/SCL3 P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/ TMRI0-B/TxD2/SDA3 P50/IRQ0-A/PO0-B/ TIOCA3-B/TMRI0-B/ TxD2/SDA3 Schmitt-triggered inputs when used as IRQ inputs. Only P50 and P51 are Schmitttriggered inputs when used as I2C inputs. Open-drain output capability. Only P50 to P52 are Schmitttriggered inputs when used as TPU inputs. Only P50 and P51 are Schmitttriggered inputs when used as 8bit timer inputs. P50 and P51 have 5-V tolerance. Schmitt-triggered inputs when used as IRQ inputs. Open-drain output capability. Only P60 to P63 are Schmitttriggered inputs when used as 8bit timer inputs. P65/IRQ13-A/DACK1/TMO1-A P64/IRQ12-A/DACK0/TMO0-A P63/IRQ11-A/TEND1/TMCI1-A P62/IRQ10-A/TEND0/TMCI0-A P61/IRQ9-A/DREQ1/TMRI1-A P60/IRQ8-A/DREQ0/TMRI0-A Port 8 General I/O port also functioning as EXDMAC I/Os, PPG outputs, TPU I/Os, TMR I/Os, SCI I/Os and interrupt inputs Input/ Output Type P85/IRQ5-B /PO5-B/TIOCB4-B/TMO1-B/SCK3/ EDACK3 P85/IRQ5-B/PO5-B/ TIOCB4-B/TMO1-B/ SCK3 P84/IRQ4-B/EDACK2 P84/IRQ4-B P83/IRQ3-B/PO3-B/TIOCD3-B/TMCI1-B/RxD3/ ETEND3 P83/IRQ3-B/PO3-B/ TIOCD3-B/TMCI1-B/ RxD3 P82/IRQ2-B/ETEND2 P82/IRQ2-B P81/IRQ1-B/PO1-B/TIOCB3-B/ TMRI1-B/TxD3/ EDREQ3 P81/IRQ1-B/PO1-B/ TIOCB3-B/TMRI1-B/ TxD3 P80/IRQ0-B/EDREQ2 P80/IRQ0-B Schmitt-triggered inputs when used as IRQ inputs. Open-drain output capability. Only P81, P83, and P85 are Schmitt-triggered inputs when used as TPU inputs. Rev. 1.00 Sep. 19, 2008 Page 495 of 1270 REJ09B0466-0100 Section 10 I/O Ports Mode 7 Port Description Port 9 Dedicated input port also functioning as A/D converter analog inputs and D/A converter analog outputs Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Input/ Output Type P97/AN15_1 P96/AN14_1 P95/AN13_1/DA3 P94/AN12_1/DA2 P93/AN11_1 P92/AN10_1 P91/AN9_1 P90/AN8_1 Port A General I/O port also functioning as address outputs, interrupt inputs, SSU I/Os, and SCI I/Os A20/IRQ4-A PA2/A18/RxD4-B A19 PA1/A17/TxD4-B Only PA4 to PA7 are Schmitttriggered inputs PA5/IRQ5-A/SSCK0-B when used as PA4/IRQ4-A/SCS0-B IRQ inputs. Built-in input pullPA3/SCK4-B up MOS. PA2/RxD4-B Open-drain output PA1/TxD4-B capability. A18 PA0/A16 PA0 A15 PB7/A15 PB7/TIOCB8/TCLKH A14 PB6/A14 PB6/TIOCA8 A13 PB5/A13 PB5/TIOCB7/TCLKG A12 PB4/A12 PB4/TIOCA7 A11 PB3/A11 PB3/TIOCD6/TCLKF A10 PB2/A10 PB2/TIOCC6/TCLKE A9 PB1/A9 PB1/TIOCB6 A8 PB0/A8 PB0/TIOCA6 A7 PC7/A7 PC7/TIOCB11 A6 PC6/A6 PC6/TIOCA11 A5 PC5/A5 PC5/TIOCB10 A4 PC4/A4 PC4/TIOCA10 A3 PC3/A3 PC3/TIOCD9 A2 PC2/A2 PC2/TIOCC9 A1 PC1/A1 PC1/TIOCB9 A0 PC0/A0 PC0/TIOCA9 PA7/A23/IRQ7-A/ SSO0-B PA7/A23/IRQ7-A/SSO0-B PA7/IRQ7-A/SSO0-B PA6/A22/IRQ6-A/SSI0-B PA6/IRQ6-A/SSI0-B PA6/A22/IRQ6-A/ SSI0-B PA5/A21/IRQ5-A/SSCK0-B PA5/A21/IRQ5-A/ SSCK0-B PA3/A19/SCK4-B PA4/A20/IRQ4-A/SCS0-B A17 A16 Port B General I/O port also functioning as address outputs and TPU I/Os Port C General I/O port also functioning as address outputs and TPU I/Os Rev. 1.00 Sep. 19, 2008 Page 496 of 1270 REJ09B0466-0100 Built-in input pullup MOS. Schmitt-triggered inputs when used as TPU inputs. Open-drain output capability. Built-in input pullup MOS. Schmitt-triggered inputs when used as TPU inputs. Open-drain output capability. Section 10 I/O Ports Mode 7 Port Description Port D General I/O port also functioning as data I/Os Mode 1 Mode 2 Mode 4 EXPE = 1 D15 PD7 D14 PD6 D13 PD5 D12 PD4 D11 PD3 D10 PD2 D9 PD1 D8 Port E General I/O port also functioning as data I/Os Port F General I/O port also functioning as interrupt inputs, bus control signal I/Os, SSU I/Os, and A/D converter inputs Input/ Output Type EXPE = 0 Built-in input pullup MOS. Open-drain output capability. PD0 PE7/D7 PE7/D7 PE7 PE6/D6 PE6/D6 PE6 PE5/D5 PE5/D5 PE5 PE4/D4 PE4/D4 PE4 PE3/D3 PE3/D3 PE3 PE2/D2 PE2/D2 PE2 PE1/D1 PE1/D1 PE1 PE0/D0 PE0/D0 PE0 PF7/φ PF7/φ PF6/AS/AH PF6 RD PF5 HWR PF4 PF3/LWR/SSO0-C PF3/SSO0-C Built-in input pullup MOS. Open-drain output capability. PF2/LCAS/DQML/IRQ15-A/SSI0-C PF2/IRQ15-A/SSI0-C PF1/UCAS/DQMU/IRQ14-A/SSCK0-C PF1/IRQ14-A/ SSCK0-C PF0/WAIT-A/ADTRG0-B/SCS0-C Only PF1 and PF2 are Schmitttriggered inputs when used as IRQ inputs. Open-drain output capability. PF0/ADTRG0-B/ SCS0-C Port G General I/O port also functioning as bus control signal I/Os and JTAG inputs Port H General I/O port also functioning as interrupt inputs and bus control signal I/Os Port J General I/O port PG6/BREQ-A/TDI*3 PG6/TDI*3 3 PG5/TMS*3 PG5/BACK-A/TMS* PG4/BREQO-A/TCK*3 PG4/TCK*3 1 PG3/CS3/RAS3/CAS* PG3 PG2/CS2/RAS2/RAS*1 PG2 PG1/CS1 PG1 PG0/CS0 PG0 PH3/CS7/OE-A/CKE-A*1/IRQ7-B PH3/IRQ7-B PH2/CS6/IRQ6-B PH2/IRQ6-B PH1/CS5/RAS5/SDRAMφ*1 1 PH0/CS4/RAS4/WE* PJ2*2 PJ1 PJ0 Open-drain output capability. PH1/SDRAMφ*1 PH0 Only PH2 and PH3 are Schmitttriggered inputs when used as IRQ inputs. Open-drain output capability. Open-drain output capability for only PJ0 and PJ1. 5-V tolerance. Rev. 1.00 Sep. 19, 2008 Page 497 of 1270 REJ09B0466-0100 Section 10 I/O Ports Notes: 1. Not supported in the H8S/2426 Group. 2. Not supported in the 145-pin package. 3. Supported only in the 145-pin package. Table 10.2 Port Functions of H8S/2424 Group Mode 7 Port Description Port 1 General I/O port also functioning as PPG outputs, TPU I/Os, DMAC I/Os, and SSU I/Os Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Input/ Output Type Schmitt-triggered inputs. Open-drain output capability. P17/PO15/TIOCB2/TCLKD/SCS0-A P16/PO14/TIOCA2/SSCK0-A P15/DACK1/PO13/TIOCB1/TCLKC/SSI0-A P14/DACK0/PO12/TIOCA1/SSO0-A P13/TEND1/PO11/TIOCD0/TCLKB P12/TEND0/PO10/TIOCC0/TCLKA P11/DREQ1/PO9/TIOCB0 P10/DREQ0/PO8/TIOCA0 Port 2 General I/O port also functioning as PPG outputs, TPU I/Os, SCI I/Os, TMR I/Os, I2C I/Os, A/D converter inputs, and bus control signal I/Os P27/PO7/TIOCB5/SCL2 P26/PO6/TIOCA5/SDA2/ADTRG1 P25/WAIT-B/PO5-A/TIOCB4-A/TMO1-A Schmitt-triggered inputs. Open-drain output P25/PO5-A/TIOCB4-A/ capability. TMO1-A 5-V tolerance. P24/PO4-A/TIOCA4-A/TMO0-A/RxD4-A P23/PO3-A/TIOCD3-A/TMCI1-A/TxD4-A P22/PO2-A/TIOCC3-A/TMCI0-A P21/PO1-A/TIOCB3-A/TMRI1-A P20/PO0-A/TIOCA3-A/TMRI0 Port 3 General I/O port also functioning as SCI I/Os, I2C I/Os, and bus control signal I/Os P35/OE-B/SCK1/SCL0 P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD Port 4 General I/O port also functioning as A/D converter analog inputs and interrupt inputs P47/IRQ7-B/AN7_0 P46/IRQ6-B/AN6_0 P45/IRQ5-B/AN5_0 P44/IRQ4-B/AN4_0 P43/IRQ3-B/AN3_0 P42/IRQ2-B/AN2_0 P41/IRQ1-B/AN1_0 P40/IRQ0-B/AN0_0 Rev. 1.00 Sep. 19, 2008 Page 498 of 1270 REJ09B0466-0100 P35/SCK1/SCL0 Open-drain output capability. Only P32 to P35 are Schmitttriggered inputs when used as I2C inputs. P32 to P35 have 5-V tolerance. Schmitt-triggered inputs when used as IRQ inputs. Section 10 I/O Ports Mode 7 Port Description Port 5 General I/O port also functioning as interrupt inputs, A/D converter inputs, SCI I/Os, PPG outputs, TPU I/Os, TMR I/Os, I2C I/Os, and bus control signal I/Os Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 P53/IRQ3-A /ADTRG0-A P52/BACK-B/IRQ2-A /PO4-B/TIOCA4-B/TMO0-B/ SCK2 P52/IRQ2-A/PO4-B/ TIOCA4-B/TMO0-B/ SCK2 P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/TMCI0-B/ RxD2/SCL3 P51/IRQ1-A/PO2-B/ TIOCC3-B/TMCI0-B/ RxD2/SCL3 P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/TMRI0-B/ P50/IRQ0-A/PO0-B/ TxD2/SDA3 TIOCA3-B/TMRI0-B/ TxD2/SDA3 Port 8 General I/O port also P85/PO5-B/TIOCB4-B/TMO1-B/SCK3 functioning as PPG P83/PO3-B/TIOCD3-B/ TMCI1-B/RxD3 outputs, P81/PO1-B/TIOCB3-B/ TMRI1-B/TxD3 TPU I/Os, TMR I/Os, and SCI I/Os Port 9 Dedicated input port also functioning as A/D converter analog inputs and D/A converter analog outputs Input/ Output Type Schmitt-triggered inputs when used as IRQ inputs. Only P50 and P51 are Schmitttriggered inputs when used as I2C inputs. Open-drain output capability. Only P50 to P52 are Schmitttriggered inputs when used as TPU inputs. Only P50 and P51 are Schmitttriggered inputs when used as 8bit timer inputs. P50 and P51 have 5-V tolerance. Open-drain output capability. Only P81, P83, and P85 are Schmitt-triggered inputs when used as TPU inputs. Only P81 and P83 are Schmitttriggered inputs when used as 8bit timer inputs. P81 and P83 have 5-V tolerance. P95/AN13_1/DA3 P94/AN12_1/DA2 Rev. 1.00 Sep. 19, 2008 Page 499 of 1270 REJ09B0466-0100 Section 10 I/O Ports Mode 7 Port Description Port A General I/O port also functioning as address outputs, SSU I/Os, SCI I/Os, and bus control signal outputs Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Input/ Output Type PA7/A23/CS7/ IRQ7-A/SSO0-B PA7/A23/CS7/IRQ7A/ SSO0-B PA6/A22/IRQ6-A/ SSI0-B PA6/A22/IRQ6-A/SSI0-B PA5/A21/IRQ5-A/ SSCK0-B PA5/A21/IRQ5-A/SSCK0-B A20/IRQ4-A PA4/A20/IRQ4-A/SCS0-B A19 PA3/A19/SCK4-B Only PA4 to PA7 are Schmitttriggered inputs PA6/IRQ6-A/SSI0-B when used as IRQ inputs. PA5/IRQ5-A/SSCK0-B Built-in input pullup MOS. Open-drain output PA4/IRQ4-A/SCS0-B capability. PA3/SCK4-B A18 PA2/A18/RxD4-B PA2/RxD4-B A17 PA1/A17/TxD4-B PA1/TxD4-B A16 PA0/A16 PA0 Port B General I/O port also A15 functioning as A14 address outputs and A13 TPU I/Os A12 PB7/A15 PB7/TIOCB8/TCLKH PB6/A14 PB6/TIOCA8 PB5/A13 PB5/TIOCB7/TCLKG PB4/A12 PB4/TIOCA7 A11 PB3/A11 PB3/TIOCD6/TCLKF A10 PB2/A10 PB2/TIOCC6/TCLKE A9 PB1/A9 PB1/TIOCB6 A8 PB0/A8 PB0/TIOCA6 Port C General I/O port also A7 functioning as A6 address outputs and A5 TPU I/Os A4 PC7/A7 PC7/TIOCB11 PC6/A6 PC6/TIOCA11 PC5/A5 PC5/TIOCB10 PC4/A4 PC4/TIOCA10 A3 PC3/A3 PC3/TIOCD9 A2 PC2/A2 PC2/TIOCC9 A1 PC1/A1 PC1/TIOCB9 A0 PC0/A0 PA7/IRQ7-A/SSO0-B PD7 D12 PD4 D11 PD3 D10 PD2 D9 PD1 D8 PD0 REJ09B0466-0100 Built-in input pullup MOS. Schmitt-triggered inputs when used as TPU inputs. Open-drain output capability. PC0/TIOCA9 Port D General I/O port also D15 functioning as data D14 I/Os D13 Rev. 1.00 Sep. 19, 2008 Page 500 of 1270 Built-in input pullup MOS. Schmitt-triggered inputs when used as TPU inputs. Open-drain output capability. PD6 PD5 Built-in input pullup MOS. Open-drain output capability. Section 10 I/O Ports Mode 7 Port Description Mode 1 Mode 2 Port E General I/O port also PE7/D7 functioning as data PE6/D6 I/Os PE5/D5 PE7/D7 PE7 PE6/D6 PE6 PE5/D5 PE5 PE4/D4 PE4/D4 PE4 PE3/D3 PE3/D3 PE3 PE2/D2 PE2/D2 PE2 PE1/D1 PE1/D1 PE1 PE0/D0 PE0/D0 PE0 Port F General I/O port also functioning as bus control signal I/Os, SSU I/Os, and A/D converter inputs Mode 4 EXPE = 1 EXPE = 0 PF7/φ PF7/φ PF6/AS/AH PF6 RD PF5 HWR PF4 PF3/LWR/SSO0-C PF3/SSO0-C PF2/CS6/LCAS/SSI0-C PF2/SSI0-C PF1/CS5/UCAS/SSCK0-C PF1/SSCK0-C PF0/WAIT-A/OE-A/ADTRG0-B/SCS0-C PF0/ADTRG0-B/ SCS0-C Port G General I/O port also PG6/BREQ-A functioning as bus PG5/BACK-A control signal I/Os PG4/BREQO-A/CS4 PG6 PG5 Input/ Output Type Built-in input pullup MOS. Open-drain output capability. Open-drain output capability. Open-drain output capability. PG4 PG3/CS3/RAS3 PG3 PG2/CS2/RAS2 PG2 PG1/CS1 PG1 PG0/CS0 PG0 Rev. 1.00 Sep. 19, 2008 Page 501 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.1 Port 1 Port 1 is an 8-bit I/O port that also has other functions. Port 1 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. • • • • • Port 1 data direction register (P1DDR) Port 1 data register (P1DR) Port 1 register (PORT1) Port 1 open drain control register (P1ODR) Port function control register 5 (PFCR5) 10.1.1 Port 1 Data Direction Register (P1DDR) The individual bits of P1DDR specify input or output for the pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 P17DDR 0 W 6 P16DDR 0 W 5 P15DDR 0 W When a pin function is specified as a general purpose I/O, setting this bit to 1 makes the corresponding pin an output port, while clearing this bit to 0 makes the corresponding pin an input port. 4 P14DDR 0 W 3 P13DDR 0 W 2 P12DDR 0 W 1 P11DDR 0 W 0 P10DDR 0 W Rev. 1.00 Sep. 19, 2008 Page 502 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.1.2 Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit Bit Name Initial Value R/W Description 7 P17DR 0 R/W 6 P16DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W 10.1.3 Port 1 Register (PORT1) PORT1 shows the pin states of port 1. PORT1 cannot be modified. Bit Bit Name Initial Value R/W Description 7 P17 * R 6 P16 * R 5 P15 * R If this register is read while a P1DDR bit is set to 1, the corresponding P1DR value is read. If this register is read while a P1DDR bit is cleared to 0, the corresponding pin state is read. 4 P14 * R 3 P13 * R 2 P12 * R 1 P11 * R 0 P10 * R Note: * Determined by the states of pins P17 to P10. Rev. 1.00 Sep. 19, 2008 Page 503 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.1.4 Port 1 Open Drain Control Register (P1ODR) P1ODR specifies the output type of each port 1 pin. Bit Bit Name Initial Value R/W Description 7 P17ODR 0 R/W 6 P16ODR 0 R/W 5 P15ODR 0 R/W Setting a P1ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P1ODR bit to 0 makes the corresponding pin a CMOS output pin. 4 P14ODR 0 R/W 3 P13ODR 0 R/W 2 P12ODR 0 R/W 1 P11ODR 0 R/W 0 P10ODR 0 R/W 10.1.5 Pin Functions Port 1 pins also function as the pins for PPG outputs, TPU I/Os, EXDMAC I/Os (H8S/2426, H8S/2426R), SSU I/Os, and DMAC I/Os (H8S/2424). The correspondence between the register specification and the pin functions is shown below. (1) Pin Functions of H8S/2426 Group and H8S/2426R Group • P17/PO15/TIOCB2/TCLKD/EDRAK3/SCS0-A The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bits TPSC2 to TPSC0 in TCR_0 and TCR_5, bit NDER15 in NDERH of the PPG, bit EDRAKE in EDMDR_3 of the EXDMAC, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of the SSU, bits SCS0S1 and SCS0S0 in PFCR5, and bit P17DDR. Rev. 1.00 Sep. 19, 2008 Page 504 of 1270 REJ09B0466-0100 Section 10 I/O Ports • Modes 1, 2, 4, and 7 (EXPE = 1) SSU settings Can be used as I/O port EDRAKE Input state Output state 0 TPU channel 2 (1) in table settings below (2) in table below 1 P17DDR 0 1 1 NDER15 0 1 PO15 output EDRAK3 output Pin function TIOCB2 output P17 input P17 output TIOCB2 input* 0 SCS0-A input*3 SCS0-A output*4 1 2 TCLKD input* • Mode 7 (EXPE = 0) SSU settings Can be used as I/O port EDRAKE TPU channel 2 settings P17DDR NDER15 Pin function Input state 0 (1) in table below (2) in table below 0 TIOCB2 output P17 input Output state 1 1 0 1 P17 output PO15 output TIOCB2 input* 1 0 SCS0-A input*3 SCS0-A output*4 2 TCLKD input* Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01×× and IOB3 = 1. 2. TCLKD input when the setting for either TCR_0 or TCR_5 is TPSC2 to TPSC0 = B'111. TCLKD input when channels 2 and 4 are set to phase counting mode. 3. SCSO-A input when SCS0S1 and SCS0S0 = B'00 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'00××, B'0101, or B'0110. Do not set up for TPU or EXDMAC outputs with SCSO-A input. 4. SCSO-A output when SCS0S1 and SCS0S0 = B'00 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'011×. Rev. 1.00 Sep. 19, 2008 Page 505 of 1270 REJ09B0466-0100 Section 10 I/O Ports TPU channel 2 settings MD3 to MD0 (2) (1) (2) B'0000, B'01×× (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR1, CCLR0 Other than B'10 B'10 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Other than B'××00 SCS pin settings SSUMS 0 1 × MSS 0 CSS1 × CSS0 × 0 1 0 1 × Input Input Automatic I/O Output Pin state 1 0 Legend: ×: Don’t care : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 506 of 1270 REJ09B0466-0100 × 1 Section 10 I/O Ports • P16/PO14/TIOCA2/EDRAK2/SSCK0-A The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOA3 to IOA0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bit NDER14 in NDERH of the PPG, bit EDRAKE in EDMDR_2 of the EXDMAC, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of the SSU, bits SSCK0S1 and SSCK0S0 in PFCR5, and bit P16DDR. • Modes 1, 2, 4, and 7 (EXPE = 1) SSU settings Can be used as I/O port EDRAKE Input state Output state 0 TPU channel 2 (1) in table settings below (2) in table below 1 P16DDR 0 1 1 NDER14 0 1 Pin function TIOCA2 output P16 input P16 output PO14 output TIOCA2 input* 0 EDRAK2 SSCK0-A input*3 output SSCK0-A output*4 1 • Mode 7 (EXPE = 0) SSU settings Can be used as I/O port EDRAKE TPU channel 2 settings Input state 0 (1) in table below (2) in table below P16DDR 0 1 1 NDER14 0 1 TIOCA2 output P16 input P16 output PO14 output Pin function Output state TIOCA2 input* 0 SSCK0-A input*3 SSCK0-A output*4 1 Rev. 1.00 Sep. 19, 2008 Page 507 of 1270 REJ09B0466-0100 Section 10 I/O Ports TPU channel 2 settings (2) MD3 to MD0 IOA3 to IOA0 (1) B'0000, B'01×× (2) (1) B'001× B'0010 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR1, CCLR0 Output function Output compare output (1) (2) B'0011 Other than B'××00 Other than B'01 B'01 PWM*2 mode PWM mode 1 output 2 output Legend: ×: Don’t care Notes: 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01×× and IOA3 = 1. 2. TIOCB2 output disabled. 3. SSCK0-A input when SSCK0S1 and SSCK0S0 = B'00 in PFCR5, and SSUMS, MSS, and SCKS = B'001 or B'101. Do not set up for TPU or EXDMAC outputs with SSCK0-A input. 4. SSCK0-A output when SSCK0S1 and SSCK0S0 = B'00 in PFCR5, and SSUMS, MSS, and SCKS = B'×11. SSCK pin settings SSUMS 0 MSS 1 0 1 0 1 SCKS 0 1 0 1 0 1 0 1 Pin state Input Output Input Output Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 508 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P15/PO13/TIOCB1/TCLKC/SSI0-A The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOB3 to IOB0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in TCR_0, TCR_2, TCR_4, and TCR_5, bit NDER13 in NDERH of the PPG, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits SSI0S1 and SSI0S0 in PFCR5, and bit P15DDR. SSU settings TPU channel 1 settings Can be used as I/O port (1) in table below Input state (2) in table below P15DDR 0 1 1 NDER13 0 1 TIOCB1 output P15 input P15 output PO13 output Pin function TIOCB1 input* TCLKC input* Output state 0 SSI0-A input*3 SSI0-A output*4 1 2 Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01×× and IOB3 to IOB0 = B'10××. 2. TCLKC input when the setting for either TCR_0 or TCR_2 is TPSC2 to TPSC0 = B'111, or when the setting for either TCR_4 or TCR_5 is TPSC2 to TPSC0 = B'101. TCLKC input when phase counting mode is set for channels 2 and 4. 3. SSI0-A input when SSI0S1 and SSI0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'001×1 or B'10××1. Do not set up for TPU output with SSI0-A input. 4. SSI0-A output when SSI0S1 and SSI0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0001×. TPU channel 1 settings MD3 to MD0 (2) (1) B'0000, B'01×× (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR1, CCLR0 Other than B'10 B'10 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Other than B'××00 Legend: ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 509 of 1270 REJ09B0466-0100 Section 10 I/O Ports SSI pin settings SSUMS 0 0 1 BIDE 0 1 0 MSS 0 TE 0 RE 1 Pin state 1 1 0 1 0 1 0 1 0 Output Output Input 1 REJ09B0466-0100 0 0 1 0 1 0 1 0 1 0 1 Input Input Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 510 of 1270 1 0 1 1 0 1 1 1 0 Input Input 1 Input Section 10 I/O Ports • P14/PO12/TIOCA1/SSO0-A The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bit NDER12 in NDERH of the PPG, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits SSO0S1 and SSO0S0 in PFCR5, and bit P14DDR. SSU settings TPU channel 1 settings Can be used as I/O port (1) in table below Input state (2) in table below P14DDR 0 1 1 NDER12 0 1 TIOCA1 output P14 input P14 output PO12 output Pin function TIOCA1 input* TPU channel 1 settings MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01×× Output state 0 SSO0-A input*3 SSO0-A output*4 1 (2) (1) B'001× B'0010 B'0011 Other than B'××00 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 CCLR1, CCLR0 Output function Output compare output (1) (2) Other than B'01 PWM*2 mode PWM mode 1 output 2 output B'01 Legend: ×: Don’t care Notes: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01×× and IOA3 to IOA0 = B'10××. 2. TIOCB1 output disabled. 3. SSO0-A input when SSO0S1 and SSO0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'000×1 or B'01×01. Do not set up for TPU output with SSO0-A input. 4. SSO0-A output when SSO0S1 and SSO0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0011×, B'01×10, or B'10×1×. Rev. 1.00 Sep. 19, 2008 Page 511 of 1270 REJ09B0466-0100 Section 10 I/O Ports SSO pin settings SSUMS 0 0 1 BIDE 0 1 0 MSS 0 TE 0 RE 1 1 1 0 Pin state Input 1 0 1 Input 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 Output Output Input Output Input Output Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 512 of 1270 REJ09B0466-0100 0 1 1 0 1 0 1 Output Output 1 0 1 Output Output Section 10 I/O Ports • P13/PO11/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOD3 to IOD0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, bit NDER11 in NDERH of the PPG, and bit P13DDR. TPU channel 0 settings (1) in table below (2) in table below P13DDR 0 NDER11 0 TIOCD0 output P13 input P13 output Pin function 1 1 PO11 output TIOCD0 input* 1 2 TCLKB input* Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10××. 2. TCLKB input when the setting for any of TCR_0 to TCR_2 is TPSC2 to TPSC0 = B'101. TCLKB input when phase counting mode is set for channels 1 and 5. TPU channel 0 settings (2) MD3 to MD0 (1) B'0000 (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR2 to CCLR0 Other than B'110 B'110 Output function Output compare output PWM mode 2 output IOD3 to IOD0 Other than B'××00 Legend: ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 513 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P12/PO10/TIOCC0/TCLKA The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_5, bit NDER10 in NDERH of the PPG, and bit P12DDR. TPU channel 0 settings (1) in table below (2) in table below P12DDR 0 NDER10 0 TIOCC0 output P12 input P12 output Pin function 1 1 PO10 output TIOCC0 input* 1 2 TCLKA input* TPU channel 0 settings (2) MD3 to MD0 IOC3 to IOC0 (1) B'0000 (2) (1) B'001× B'0010 B'0011 Other than B'××00 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 CCLR2 to CCLR0 Output function Output compare output (1) (2) Other than B'101 PWM*3 mode PWM mode 1 output 2 output B'101 Legend: ×: Don’t care Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10××. 2. TCLKA input when the setting for any of TCR_0 to TCR_5 is TPSC2 to TPSC0 = B'100. TCLKA input when phase counting mode is set for channels 1 and 5. 3. TIOCD0 output disabled. Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_0. Rev. 1.00 Sep. 19, 2008 Page 514 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P11/PO9/TIOCB0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOB3 to IOB0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER9 in NDERH of the PPG, and bit P11DDR. TPU channel 0 settings (1) in table below (2) in table below P11DDR 0 NDER9 0 1 TIOCB0 output P11 input P11 output PO9 output Pin function 1 TIOCB0 input* Note: * TIOCB0 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10××. TPU channel 0 settings (2) MD3 to MD0 (1) B'0000 (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR2 to CCLR0 Other than B'010 B'010 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Other than B'××00 Legend: ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 515 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P10/PO8/TIOCA0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOA3 to IOA0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER8 in NDERH of the PPG, and bit P10DDR. TPU channel 0 settings (1) in table below (2) in table below P10DDR 0 NDER8 0 TIOCA0 output P10 input P10 output Pin function 1 1 TIOCA0 input* TPU channel 0 settings (2) MD3 to MD0 IOA3 to IOA0 (1) B'0000 PO8 output 1 (2) (1) B'001× B'0010 B'0011 Other than B'××00 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 CCLR2 to CCLR0 Output function Output compare output (1) (2) Other than B'001 PWM*2 mode PWM mode 1 output 2 output Legend: ×: Don’t care Notes: 1. TIOCA0 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10××. 2. TIOCB0 output disabled. Rev. 1.00 Sep. 19, 2008 Page 516 of 1270 REJ09B0466-0100 B'001 Section 10 I/O Ports (2) Pin Functions of H8S/2424 Group • P17/PO15/TIOCB2/TCLKD/SCS0-A The pin function is switched as shown below according to the combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bits TPSC2 to TPSC0 in TCR_0 and TCR_5, bit NDER15 in NDERH of the PPG, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of the SSU, bits SCS0S1 and SCS0S0 in PFCR5, and bit P17DDR. SSU settings TPU channel 2 settings Can be used as I/O port (1) in table below Input state (2) in table below P17DDR 0 1 1 NDER15 0 1 TIOCB2 output P17 input P17 output PO15 output Pin function TIOCB2 input* Output state 0 SCS0-A input*3 SCS0-A output*4 1 2 TCLKD input* Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01×× and IOB3 = 1. 2. TCLKD input when the setting for either TCR_0 or TCR_5 is TPSC2 to TPSC0 = B'111. TCLKD input when channels 2 and 4 are set to phase counting mode. 3. SCS0-A input when SCS0S1 and SCS0S0 = B'00 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'00××, B'0101, or B'0110. Do not set up for TPU output with SCS0-A input. 4. SCS0-A output when SCS0S1 and SCS0S0 = B'00 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'011×. TPU channel 2 settings MD3 to MD0 (2) (1) B'0000, B'01×× (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR1, CCLR0 Other than B'10 B'10 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Other than B'××00 Rev. 1.00 Sep. 19, 2008 Page 517 of 1270 REJ09B0466-0100 Section 10 I/O Ports SCS pin settings SSUMS 0 1 × MSS 0 CSS1 × CSS0 × 0 1 0 1 × Input Input Automatic I/O Output Pin state 1 0 × 1 Legend: ×: Don’t care : Pin is not used by the SSU (can be used as I/O port) • P16/PO14/TIOCA2/SSCK0-A The pin function is switched as shown below according to the combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOA3 to IOA0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bit NDER14 in NDERH of the PPG, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of the SSU, bits SSCK0S1 and SSCK0S0 in PFCR5, and bit P16DDR. SSU settings Can be used as I/O port TPU channel 2 (1) in table settings below Input state (2) in table below P16DDR 0 1 1 NDER14 0 1 TIOCA2 output P16 input P16 output Pin function Rev. 1.00 Sep. 19, 2008 Page 518 of 1270 REJ09B0466-0100 TIOCA2 input* PO14 output 1 Output state 0 SSCK0-A input*3 SSCK0-A output*4 Section 10 I/O Ports TPU channel 2 settings (2) MD3 to MD0 IOA3 to IOA0 (1) B'0000, B'01×× (2) (1) B'001× B'0010 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR1, CCLR0 Output function Output compare output (1) (2) B'0011 Other than B'××00 Other than B'01 B'01 PWM*2 mode PWM mode 1 output 2 output Legend: ×: Don’t care Notes: 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01×× and IOA3 = 1. 2. TIOCB2 output disabled. 3. SSCK0-A input when SSCK0S1 and SSCK0S0 = B'00 in PFCR5, and SSUMS, MSS, and SCKS = B'001 or B'101. Do not set up for TPU output with SSCK0-A input. 4. SSCK0-A output when SSCK0S1 and SSCK0S0 = B'00 in PFCR5, and SSUMS, MSS, and SCKS = B'×11. SSCK pin settings SSUMS 0 MSS 1 0 1 0 1 SCKS 0 1 0 1 0 1 0 1 Pin state Input Output Input Output Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 519 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P15/DACK1/PO13/TIOCB1/TCLKC/SSI0-A The pin function is switched as shown below according to the combination of bit SAE1 in DMABCRH of the DMAC, TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOB3 to IOB0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in TCR_0, TCR_2, TCR_4, and TCR_5, bit NDER13 in NDERH of the PPG, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits SSI0S1 and SSI0S0 in PFCR5, and bit P15DDR. SSU settings Can be used as I/O port SAE1 Input state Output state 0 TPU channel 1 (1) in table settings below (2) in table below 1 P15DDR 0 1 1 NDER13 0 1 TIOCB1 output P15 input P15 output PO13 output DACK1 output Pin function TIOCB1 input* TCLKC input* 0 SSI0-A input*3 SSI0-A output*4 1 2 Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01×× and IOB3 to IOB0 = B'10××. 2. TCLKC input when the setting for either TCR_0 or TCR_2 is TPSC2 to TPSC0 = B'111, or when the setting for either TCR_4 or TCR_5 is TPSC2 to TPSC0 = B'101. TCLKC input when phase counting mode is set for channels 2 and 4. 3. SSI0-A input when SSI0S1 and SSI0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'001×1 or B'10××1. Do not set up for TPU or DMAC output with SSI0-A input. 4. SSI0-A output when SSI0S1 and SSI0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0001×. Rev. 1.00 Sep. 19, 2008 Page 520 of 1270 REJ09B0466-0100 Section 10 I/O Ports TPU channel 1 settings (2) MD3 to MD0 (1) (2) B'0000, B'01×× (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR1, CCLR0 Other than B'10 B'10 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Other than B'××00 Legend: ×: Don’t care SSI pin settings SSUMS 0 0 1 BIDE 0 1 0 MSS 0 TE 0 RE 1 Pin state 1 1 0 0 1 1 Output Output Input 0 1 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 0 Input Input 0 1 1 Input Input 1 0 1 Input Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 521 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P14/DACK0/PO12/TIOCA1/SSO0-A The pin function is switched as shown below according to the combination of bit SAE0 in DMABCRH of the DMAC, TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bit NDER12 in NDERH of the PPG, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits SSO0S1 and SSO0S0 in PFCR5, and bit P14DDR. SSU settings Can be used as I/O port SAE0 Input state Output state 0 TPU channel 1 (1) in table settings below (2) in table below 1 P14DDR 0 1 1 NDER12 0 1 TIOCA1 output P14 input P14 output PO12 output DACK0 output Pin function TIOCA1 input* TPU channel 1 settings MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01×× 0 SSO0-A input*3 SSO0-A output*4 1 (2) (1) B'001× B'0010 B'0011 Other than B'××00 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 CCLR1, CCLR0 Output function Output compare output (1) (2) Other than B'01 PWM*2 mode PWM mode 1 output 2 output B'01 Legend: ×: Don’t care Notes: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01×× and IOA3 to IOA0 = B'10××. 2. TIOCB1 output disabled. 3. SSO0-A input when SSO0S1 and SSO0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'000×1 or B'01×01. Do not set up for TPU or DMAC output with SSO0-A input. 4. SSO0-A output when SSO0S1 and SSO0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0011×, B'01×10, or B'10×1×. Rev. 1.00 Sep. 19, 2008 Page 522 of 1270 REJ09B0466-0100 Section 10 I/O Ports SSO pin settings SSUMS 0 0 1 BIDE 0 1 0 MSS 0 1 TE 0 1 RE 1 0 Pin state Input Input 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 1 0 1 0 1 0 Output Output Input Output Input Output 1 1 0 1 1 0 1 Output Output Output Output Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 523 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P13/TEND1/PO11/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of bit TEE1 in DMATCR of the DMAC, TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOD3 to IOD0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, bit NDER11 in NDERH of the PPG, and bit P13DDR. TEE1 TPU channel 0 settings (1) in table below 0 1 (2) in table below P13DDR 0 1 1 NDER11 0 1 TIOCD0 output P13 input P13 output PO11 output TEND1 output Pin function TIOCD0 input* 1 2 TCLKB input* Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10××. 2. TCLKB input when the setting for any of TCR_0 to TCR_2 is TPSC2 to TPSC0 = B'101. TCLKB input when phase counting mode is set for channels 1 and 5. TPU channel 0 settings (2) MD3 to MD0 (1) B'0000 (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR2 to CCLR0 Other than B'110 B'110 Output function Output compare output PWM mode 2 output IOD3 to IOD0 Legend: ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 524 of 1270 REJ09B0466-0100 Other than B'××00 Section 10 I/O Ports • P12/TEND0/PO10/TIOCC0/TCLKA The pin function is switched as shown below according to the combination of bit TEE0 in DMATCR of the DMAC, TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_5, bit NDER10 in NDERH of the PPG, and bit P12DDR. TEE0 TPU channel 0 settings (1) in table below 0 1 (2) in table below P12DDR 0 1 1 NDER10 0 1 TIOCC0 output P12 input P12 output PO10 output TEND0 output Pin function TIOCC0 input* 1 2 TCLKA input* TPU channel 0 settings (2) MD3 to MD0 IOC3 to IOC0 (1) B'0000 (2) (1) B'001× B'0010 B'0011 Other than B'××00 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 CCLR2 to CCLR0 Output function Output compare output (1) (2) Other than B'101 PWM*3 mode PWM mode 1 output 2 output B'101 Legend: ×: Don’t care Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10××. 2. TCLKA input when the setting for any of TCR_0 to TCR_5 is TPSC2 to TPSC0 = B'100. TCLKA input when phase counting mode is set for channels 1 and 5. 3. TIOCD0 output disabled. Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_0. Rev. 1.00 Sep. 19, 2008 Page 525 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P11/DREQ1/PO9/TIOCB0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOB3 to IOB0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER9 in NDERH of the PPG, and bit P11DDR. TPU channel 0 settings (1) in table below (2) in table below P11DDR 0 NDER9 0 1 TIOCB0 output P11 input P11 output PO9 output Pin function 1 TIOCB0 input* DREQ1 input Note: * TIOCB0 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10××. TPU channel 0 settings (2) MD3 to MD0 (1) B'0000 (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR2 to CCLR0 Other than B'010 B'010 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Legend: ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 526 of 1270 REJ09B0466-0100 Other than B'××00 Section 10 I/O Ports • P10/DREQ0/PO8/TIOCA0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOA3 to IOA0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER8 in NDERH of the PPG, and bit P10DDR. TPU channel 0 settings (1) in table below (2) in table below P10DDR 0 NDER8 0 TIOCA0 output P10 input P10 output Pin function 1 1 PO8 output TIOCA0 input* 1 DREQ0 input TPU channel 0 settings (2) MD3 to MD0 IOA3 to IOA0 (1) B'0000 (2) (1) B'001× B'0010 B'0011 Other than B'××00 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 CCLR2 to CCLR0 Output function Output compare output (1) (2) Other than B'001 PWM*2 mode PWM mode 1 output 2 output B'001 Legend: ×: Don’t care Notes: 1. TIOCA0 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10××. 2. TIOCB0 output disabled. Rev. 1.00 Sep. 19, 2008 Page 527 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.2 Port 2 Port 2 is an 8-bit I/O port that also has other functions. Port 2 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. • • • • • Port 2 data direction register (P2DDR) Port 2 data register (P2DR) Port 2 register (PORT2) Port 2 open drain control register (P2ODR) Port function control register 3 (PFCR3) 10.2.1 Port 2 Data Direction Register (P2DDR) The individual bits of P2DDR specify input or output for the pins of port 2. P2DDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 P27DDR 0 W 6 P26DDR 0 W 5 P25DDR 0 W When a pin function is specified as a general purpose I/O, setting this bit to 1 makes the corresponding pin an output port, while clearing this bit to 0 makes the corresponding pin an input port. 4 P24DDR 0 W 3 P23DDR 0 W 2 P22DDR 0 W 1 P21DDR 0 W 0 P20DDR 0 W Rev. 1.00 Sep. 19, 2008 Page 528 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.2.2 Port 2 Data Register (P2DR) P2DR stores output data for the port 2 pins. Bit Bit Name Initial Value R/W Description 7 P27DR 0 R/W 6 P26DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 P25DR 0 R/W 4 P24DR 0 R/W 3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W 0 P20DR 0 R/W 10.2.3 Port 2 Register (PORT2) PORT2 shows the pin states of port 2. PORT2 cannot be modified. Bit Bit Name Initial Value R/W Description 7 P27 * R 6 P26 * R 5 P25 * R If this register is read while a P2DDR bit is set to 1, the corresponding P2DR value is read. If this register is read while a P2DDR bit is cleared to 0, the corresponding pin state is read. 4 P24 * R 3 P23 * R 2 P22 * R 1 P21 * R 0 P20 * R Note: * Determined by the states of pins P27 to P20. Rev. 1.00 Sep. 19, 2008 Page 529 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.2.4 Port 2 Open Drain Control Register (P2ODR) P2ODR specifies the output type of each port 2 pin. Bit Bit Name Initial Value R/W Description 7 P27ODR 0 R/W 6 P26ODR 0 R/W 5 P25ODR 0 R/W Setting a P2ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P2ODR bit to 0 makes the corresponding pin a CMOS output pin. 4 P24ODR 0 R/W 3 P23ODR 0 R/W 2 P22ODR 0 R/W 1 P21ODR 0 R/W 0 P20ODR 0 R/W Rev. 1.00 Sep. 19, 2008 Page 530 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.2.5 Pin Functions Port 2 pins also function as the pins for PPG outputs, TPU I/Os, interrupt inputs (H8S/2426, H8S/2426R), 8-bit timer I/Os (H8S/2424), I2C I/Os, and bus control signal inputs. The correspondence between the register specification and the pin functions is shown below. (1) Pin Functions of H8S/2426 Group and H8S/2426R Group • P27/PO7/TIOCB5/IRQ15-B/SCL2 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOB3 to IOB0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER7 in NDERL of the PPG, bit ICE in ICCRA_2 of the I2C, bit P27DDR, and bit ITS15 in ITSR of the interrupt controller. ICE TPU channel 5 settings (1) in table below 0 1 (2) in table below P27DDR 0 1 1 NDER7 0 1 TIOCB5 output P27 input P27 output PO7 output SCL2 I/O Pin function TIOCB5 input* 1 IRQ15-B interrupt input*2 Notes: 1. TIOCB5 input when MD3 to MD0 = B'0000 or B'01×× and IOB3 = 1. 2. IRQ15-B input when the ITS15 bit in ITSR is 1. Rev. 1.00 Sep. 19, 2008 Page 531 of 1270 REJ09B0466-0100 Section 10 I/O Ports TPU channel 5 settings MD3 to MD0 (2) (1) (2) B'0000, B'01×× (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR1, CCLR0 Other than B'10 B'10 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Other than B'××00 Legend: ×: Don’t care • P26/PO6/TIOCA5/IRQ14-B/SDA2/ADTRG1 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER6 in NDERL of the PPG, bits TRGS1, TRGS0, and EXTRGS in ADCR_1 of the ADC, bit ICE in ICCRA_2 of the I2C, bit P26DDR, and bit ITS14 in ITSR of the interrupt controller. ICE TPU channel 5 settings (1) in table below 0 1 (2) in table below P26DDR 0 1 1 NDER6 0 1 TIOCA5 output P26 input P26 output PO6 output SDA2 I/O Pin function TIOCA5 input* 1 IRQ14-B interrupt input*2 ADTRG1 input* 4 Rev. 1.00 Sep. 19, 2008 Page 532 of 1270 REJ09B0466-0100 Section 10 I/O Ports TPU channel 5 settings MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01×× (2) (2) (1) B'001× B'0010 B'0011 Other than B'××00 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 CCLR1, CCLR0 Output function Output compare output (2) Other than B'01 B'01 PWM*3 mode PWM mode 1 output 2 output Legend: ×: Don’t care Notes: 1. TIOCA5 input when MD3 to MD0 = B'0000 or B'01×× and IOA3 = 1. 2. IRQ14-B input when the ITS14 bit in ITSR is 1. 3. TIOCB5 output disabled. 4. ADTRG1 input when EXTRGS = 0 and TRGS1 = TRGS0 = 1. • P25/PO5-A/TIOCB4-A/IRQ13-B/WAIT-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit WAITE in BCR of the bus controller, TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bit NDER5 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, bit WAITS in PFCR4, bit P25DDR, and bit ITS13 in ITSR of the interrupt controller. • Modes 1, 2, 4, and 7 (EXPE = 1) WAITE TPU channel 4 settings (1) in table below 0 1 (2) in table below P25DDR 0 1 1 NDER5 0 1 Pin function TIOCB4-A output*4 P25 input P25 output PO5-A output* WAIT-B input*5 3 TIOCB4-A input*1*4 IRQ13-B interrupt input* 2 Rev. 1.00 Sep. 19, 2008 Page 533 of 1270 REJ09B0466-0100 Section 10 I/O Ports • Mode 7 (EXPE = 0) WAITE TPU channel 4 settings (1) in table below (2) in table below P25DDR 0 1 0 TIOCB4-A output*4 P25 input P25 output PO5-A output*3 NDER5 Pin function 0 TIOCB4-A input*1*4 IRQ13-B interrupt input* 2 Notes: 1. 2. 3. 4. 5. TIOCB4-A input when MD3 to MD0 = B'0000 or B'01×× and IOB3 to IOB0 = B'10××. IRQ13-B input when the ITS13 bit in ITSR is 1. PO5-A output when the PPGS bit in PFCR3 is 0. TIOCB4-A input/output when the TPUS bit in PFCR3 is 0. WAIT-B input when the WAITS bit in PFCR4 is 1. TPU channel 4 settings MD3 to MD0 (2) (1) B'0000, B'01×× (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR1, CCLR0 Other than B'10 B'10 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Legend: ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 534 of 1270 REJ09B0466-0100 Other than B'××00 Section 10 I/O Ports • P24/IRQ12-B/PO4-A/TIOCA4-A/RxD4-A The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOA3 to IOA0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bit NDER4 in NDERL of the PPG, bit RE in SCR_4 of the SCI, bits PPGS and TPUS in PFCR3, bit RXD4S in PFCR4, bit P24DDR, and bit ITS12 in ITSR of the interrupt controller TPU channel 4 settings (1) in table below (2) in table below RE P24DDR 0 NDER4 Pin function TIOCA4-A 5 output* 0 1 1 0 P24 input 1 P24 output PO4-A output* 4 RxD4-A 6 input* TIOCA4-A input*1*5 IRQ12-B interrupt input* 2 TPU channel 4 settings MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01×× (2) (1) B'001× B'0010 B'0011 Other than B'××00 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 CCLR1, CCLR0 Output function Output compare output (1) (2) Other than B'01 PWM*3 mode PWM mode 1 output 2 output B'01 Legend: ×: Don’t care Notes: 1. TIOCA4-A input when MD3 to MD0 = B'0000 or B'01×× and IOA3 to IOA0 = B'10××. 2. IRQ12-B input when the ITS12 bit in ITSR is 1. 3. TIOCB4 output disabled. 4. PO4-A output when the PPGS bit in PFCR3 is 0. 5. TIOCA4-A input/output when the TPUS bit in PFCR3 is 0. 6. RxD4-A input when the RXD4S bit in PFCR4 is 0. Rev. 1.00 Sep. 19, 2008 Page 535 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P23/IRQ11-B/PO3-A/TIOCD3-A/TxD4-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL of the PPG, bit TE in SCR_4 of the SCI, bits PPGS and TPUS in PFCR3, bit TXD4S in PFCR4, bit P23DDR, and bit ITS11 in ITSR of the interrupt controller. TPU channel 3 settings (1) in table below (2) in table below TE P23DDR 0 NDER3 Pin function 0 TIOCD3-A 4 output* 1 1 0 P23 input P23 output 1 PO3-A output* 3 TxD4-A 5 output* TIOCD3-A input*1*4 IRQ11-B interrupt input* 2 Notes: 1. 2. 3. 4. 5. TIOCD3-A input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10××. IRQ11-B input when the ITS11 bit in ITSR is 1. PO3-A output when the PPGS bit in PFCR3 is 0. TIOCD3-A input/output when the TPUS bit in PFCR3 is 0. TxD4-A output when the TXD4S bit in PFCR4 is 0. TPU channel 3 settings (2) MD3 to MD0 (1) B'0000 (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR2 to CCLR0 Other than B'110 B'110 Output function Output compare output PWM mode 2 output IOD3 to IOD0 Legend: ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 536 of 1270 REJ09B0466-0100 Other than B'××00 Section 10 I/O Ports • P22/IRQ10-B /PO2-A/TIOCC3-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOC3 to IOC0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER2 in NDERL of the PPG, bits PPGS and TPUS in PFCR3, bit P22DDR, and bit ITS10 in ITSR of the interrupt controller. TPU channel 3 settings (1) in table below P22DDR NDER2 Pin function (2) in table below 0 5 TIOCC3-A output* 1 0 1 P22 input P22 output PO2-A output*4 1 5 TIOCC3-A input* * IRQ10-B interrupt input* 2 TPU channel 3 settings (2) MD3 to MD0 IOC3 to IOC0 (1) B'0000 (2) (1) B'001× B'0010 B'0011 Other than B'××00 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 CCLR2 to CCLR0 Output function Output compare output (1) (2) Other than B'101 PWM*3 mode PWM mode 1 output 2 output B'101 Legend: ×: Don’t care Notes: 1. TIOCC3-A input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10××. 2. IRQ10-B input when the ITS10 bit in ITSR is 1. 3. TIOCD3 output disabled. Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_3. 4. PO2-A output when the PPGS bit in PFCR3 is 0. 5. TIOCC3-A input/output when the TPUS bit in PFCR3 is 0. Rev. 1.00 Sep. 19, 2008 Page 537 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P21/IRQ9-B/PO1-A/TIOCB3-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL of the PPG, bits PPGS and TPUS in PFCR3, bit P21DDR, and bit ITS9 in ITSR of the interrupt controller. TPU channel 3 settings (1) in table below (2) in table below P21DDR 0 NDER1 0 1 TIOCB3-A 4 output* P21 input P21 output PO1-A output*3 Pin function 1 TIOCB3-A input*1*4 IRQ9-B interrupt input* 2 Notes: 1. 2. 3. 4. TIOCB3-A input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10××. IRQ9-B input when the ITS9 bit in ITSR is 1. PO1-A output when the PPGS bit in PFCR3 is 0. TIOCB3-A input/output when the TPUS bit in PFCR3 is 0. TPU channel 3 settings (2) MD3 to MD0 (1) B'0000 (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR2 to CCLR0 Other than B'010 B'010 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Legend: ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 538 of 1270 REJ09B0466-0100 Other than B'××00 Section 10 I/O Ports • P20/PO0-A/TIOCA3-A/IRQ8-B*2 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER0 in NDERL of the PPG, bits PPGS and TPUS in PFCR3, bit P20DDR, and bit ITS8 in ITSR of the interrupt controller. TPU channel 3 settings (1) in table below (2) in table below P20DDR 0 NDER0 0 1 TIOCA3-A 5 output* P20 input P20 output PO0-A output*4 Pin function 1 TIOCA3-A input*1*5 IRQ8-B interrupt input* 2 TPU channel 3 settings (2) MD3 to MD0 IOA3 to IOA0 (1) B'0000 (2) (1) B'001× B'0010 B'0011 Other than B'××00 B'0000, B'0100, B'1××× B'0001 to B'0011 B'0101 to B'0111 B'××00 Other than B'××00 CCLR2 to CCLR0 Output function Output compare output (1) (2) Other than B'001 PWM*3 mode PWM mode 1 output 2 output B'001 Legend: ×: Don’t care Notes: 1. TIOCA3-A input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10××. 2. IRQ8-B input when the ITS8 bit in ITSR is 1. 3. TIOCB3 output disabled. 4. PO0-A output when the PPGS bit in PFCR3 is 0. 5. TIOCA3-A input/output when the TPUS bit in PFCR3 is 0. Rev. 1.00 Sep. 19, 2008 Page 539 of 1270 REJ09B0466-0100 Section 10 I/O Ports (2) Pin Functions of H8S/2424 Group • P27/PO7/TIOCB5/SCL2 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOB3 to IOB0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER7 in NDERL of the PPG, bit ICE in ICCRA_2 of the I2C, and bit P27DDR. ICE TPU channel 5 settings (1) in table below 0 1 (2) in table below P27DDR 0 1 1 NDER7 0 1 TIOCB5 output P27 input P27 output PO7 output SCL2 I/O Pin function Note: * TIOCB5 input* TIOCB5 input when MD3 to MD0 = B'0000 or B'01×× and IOB3 = 1. TPU channel 5 settings MD3 to MD0 (2) (1) B'0000, B'01×× (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR1, CCLR0 Other than B'10 B'10 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Legend: ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 540 of 1270 REJ09B0466-0100 Other than B'××00 Section 10 I/O Ports • P26/PO6/TIOCA5/SDA2/ADTRG1 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER6 in NDERL of the PPG, bits TRGS1, TRGS0, and EXTRGS in ADCR_1 of the ADC, bit ICE in ICCRA_2 of the I2C, and bit P26DDR. ICE TPU channel 5 settings (1) in table below 0 1 (2) in table below P26DDR 0 1 1 NDER6 0 1 TIOCA5 output P26 input P26 output PO6 output SDA2 I/O Pin function TIOCA5 input* 1 ADTRG1 input* 3 TPU channel 5 settings MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01×× (2) (2) B'001× B'0010 B'0011 Other than B'××00 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 CCLR1, CCLR0 Output function Output compare output (1) (2) Other than B'01 PWM*2 mode PWM mode 1 output 2 output B'01 Legend: ×: Don’t care Notes: 1. TIOCA5 input when MD3 to MD0 = B'0000 or B'01×× and IOA3 = 1. 2. TIOCB5 output disabled. 3. ADTRG1 input when EXTRGS = 0 and TRGS1 = TRGS0 = 1. Rev. 1.00 Sep. 19, 2008 Page 541 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P25/WAIT-B/PO5-A/TIOCB4-A/TMO1-A The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit WAITE in BCR of the bus controller, TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bits OS3 to OS0*8 in TCSR_1 of the 8-bit timer, bit NDER5 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, bit WAITS in PFCR4, and bit P25DDR. • Modes 1, 2, 4, and 7 (EXPE = 1) WAITE 0 TPU channel 4 settings 1 (1) in table below OS3 to OS0 P25DDR 0 1 NDER5 TIOCB4-A output*3 P25 input Pin function (2) in table below Not all 0 1 0 1 P25 output PO5-A output*2 TMO1-A output*4 WAIT-B input*5 All 0 1 3 TIOCB4-A input* * • Mode 7 (EXPE = 0) WAITE TPU channel 4 settings (1) in table below (2) in table below OS3 to OS0 P25DDR 0 0 1 NDER5 0 Pin function Notes: 1. 2. 3. 4. 5. TIOCB4-A output*3 All 0 P25 input P25 output Not all 0 PO5-A output* 1 1 2 TIO1-A output*4 TIOCB4-A input*1*3 TIOCB4-A input when MD3 to MD0 = B'0000 or B'01×× and IOB3 to IOB0 = B'10××. PO5-A output when the PPGS bit in PFCR3 is 0. TIOCB4-A input/output when the TPUS bit in PFCR3 is 0. TMO1-A output when the TMRS bit in PFCR3 is 0. WAIT-B input when the WAITS bit in PFCR4 is 1. Rev. 1.00 Sep. 19, 2008 Page 542 of 1270 REJ09B0466-0100 Section 10 I/O Ports TPU channel 4 settings MD3 to MD0 (2) (1) B'0000, B'01×× (2) (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR1, CCLR0 Other than B'10 B'10 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Other than B'××00 Legend: ×: Don’t care • P24/PO4-A/TIOCA4-A/TMO0-A/RxD4-A The pin function is switched as shown below according to the combination of bits OS3 to OS0 in TCSR_0 of the 8-bit timer, TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOA3 to IOA0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bit NDER4 in NDERL of the PPG, bit RE in SCR_4 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, bit RXD4S in PFCR4, and bit P24DDR. TPU channel 4 settings (1) in table below (2) in table below OS3 to OS0 RE P24DDR 0 1 NDER4 TIOCA4-A output*4 P24 input Pin function All 0 Not all 0 1 1 0 1 P24 output PO4-A output*3 RxD4-A input*6 TMO0-A output*5 0 TIOCA4-A input*1*4 Rev. 1.00 Sep. 19, 2008 Page 543 of 1270 REJ09B0466-0100 Section 10 I/O Ports TPU channel 4 settings MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01×× (2) (1) B'001× B'0010 B'0011 Other than B'××00 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 CCLR1, CCLR0 Output function Output compare output (1) (2) Other than B'01 PWM*2 mode PWM mode 1 output 2 output B'01 Legend: ×: Don’t care Notes: 1. TIOCA4-A input when MD3 to MD0 = B'0000 or B'01×× and IOA3 to IOA0 = B'10××. 2. TIOCB4 output disabled. 3. PO4-A output when the PPGS bit in PFCR3 is 0. 4. TIOCA4-A input/output when the TPUS bit in PFCR3 is 0. 5. TMO0-A output when the TMRS bit in PFCR3 is 0. 6. RxD4-A input when the RXD4S bit in PFCR4 is 0. Rev. 1.00 Sep. 19, 2008 Page 544 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P23/PO3-A/TIOCD3-A/TMCI1-A/TxD4-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL of the PPG, bit TE in SCR_4 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, bit TXD4S in PFCR4, and bit P23DDR. TPU channel 3 settings (1) in table below (2) in table below TE P23DDR 0 NDER3 Pin function 0 TIOCD3-A output*3 P23 input 1 1 0 1 P23 output PO3-A output* 1 2 TxD4-A output*5 3 TIOCD3-A input* * 4 TMCI1-A input* Notes: 1. 2. 3. 4. 5. TIOCD3-A input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10××. PO3-A output when the PPGS bit in PFCR3 is 0. TIOCD3-A input/output when the TPUS bit in PFCR3 is 0. TMCI1-A input when the TMRS bit in PFCR3 is 0. TxD4-A output when the TXD4S bit in PFCR4 is 0. TPU channel 3 settings (2) MD3 to MD0 (1) B'0000 (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR2 to CCLR0 Other than B'110 B'110 Output function Output compare output PWM mode 2 output IOD3 to IOD0 Other than B'××00 Legend: ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 545 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P22/PO2-A/TIOCC3-A/TMCI0-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOC3 to IOC0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER2 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, and bit P22DDR. TPU channel 3 settings (1) in table below P22DDR NDER2 Pin function (2) in table below 0 4 TIOCC3-A output* 1 0 1 P22 input P22 output PO2-A output*3 1 4 TIOCC3-A input* * 5 TMCI0-A input* TPU channel 3 settings (2) MD3 to MD0 IOC3 to IOC0 (1) B'0000 (2) (1) B'001× B'0010 B'0011 Other than B'××00 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 CCLR2 to CCLR0 Output function Output compare output (1) (2) Other than B'101 PWM*2 mode PWM mode 1 output 2 output B'101 Legend: ×: Don’t care Notes: 1. TIOCC3-A input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10××. 2. TIOCD3 output disabled. Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_3. 3. PO2-A output when the PPGS bit in PFCR3 is 0. 4. TIOCC3-A input/output when the TPUS bit in PFCR3 is 0. 5. TMCI0-A input when the TMRS bit in PFCR3 is 0. Rev. 1.00 Sep. 19, 2008 Page 546 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P21/PO1-A/TIOCB3-A/TMRI1-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, and bit P21DDR. TPU channel 3 settings (1) in table below (2) in table below P21DDR 0 NDER1 0 1 TIOCB3-A 3 output* P21 input P21 output PO1-A output*2 Pin function 1 TIOCB3-A input*1*3 4 TMRI1-A input* Notes: 1. 2. 3. 4. TIOCB3-A input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10××. PO1-A output when the PPGS bit in PFCR3 is 0. TIOCB3-A input/output when the TPUS bit in PFCR3 is 0. TMRI1-A input when the TMRS bit in PFCR3 is 0. TPU channel 3 settings (2) MD3 to MD0 (1) B'0000 (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR2 to CCLR0 Other than B'010 B'010 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Other than B'××00 Legend: ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 547 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P20/PO0-A/TIOCA3-A/TMRI0-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER0 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, and bit P20DDR. TPU channel 3 settings (1) in table below (2) in table below P20DDR 0 NDER0 0 1 TIOCA3-A 4 output* P20 input P20 output PO0-A output*3 Pin function 1 TIOCA3-A input*1*4 5 TMRI0-A input* TPU channel 3 settings (2) MD3 to MD0 IOA3 to IOA0 (1) B'0000 (2) (1) B'001× B'0010 B'0011 Other than B'××00 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 CCLR2 to CCLR0 Output function Output compare output (1) (2) Other than B'001 PWM*2 mode PWM mode 1 output 2 output Legend: ×: Don’t care Notes: 1. TIOCA3-A input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10××. 2. TIOCB3 output disabled. 3. PO0-A output when the PPGS bit in PFCR3 is 0. 4. TIOCA3-A input/output when the TPUS bit in PFCR3 is 0. 5. TMRI0-A input when the TMRS bit in PFCR3 is 0. Rev. 1.00 Sep. 19, 2008 Page 548 of 1270 REJ09B0466-0100 B'001 Section 10 I/O Ports 10.3 Port 3 Port 3 is a 6-bit I/O port that also has other functions. Port 3 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. • • • • • Port 3 data direction register (P3DDR) Port 3 data register (P3DR) Port 3 register (PORT3) Port 3 open drain control register (P3ODR) Port function control register 2 (PFCR2) 10.3.1 Port 3 Data Direction Register (P3DDR) The individual bits of P3DDR specify input or output for the pins of port 3. P3DDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7, 6 5 P35DDR All 0 Reserved 0 W When a pin function is specified as a general purpose I/O, setting this bit to 1 makes the corresponding pin an output port, while clearing this bit to 0 makes the corresponding pin an input port. 4 P34DDR 0 W 3 P33DDR 0 W 2 P32DDR 0 W 1 P31DDR 0 W 0 P30DDR 0 W Rev. 1.00 Sep. 19, 2008 Page 549 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.3.2 Port 3 Data Register (P3DR) P3DR stores output data for the port 3 pins. Bit Bit Name Initial Value R/W Description 7, 6 All 0 Reserved These bits are always read as 0 and cannot be modified. 5 P35DR 0 R/W 4 P34DR 0 R/W 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 P30DR 0 R/W 10.3.3 Output data for a pin is stored when the pin function is specified as a general purpose I/O. Port 3 Register (PORT3) PORT3 shows the pin states of port 3. PORT3 cannot be modified. Bit Bit Name Initial Value R/W Description 7, 6 Undefined Reserved If these bits are read, they will return an undefined value. 5 P35 * R 4 P34 * R 3 P33 * R 2 P32 * R 1 P31 * R 0 P30 * R Note: * If this register is read while a P3DDR bit is set to 1, the corresponding P3DR value is read. If this register is read while a P3DDR bit is cleared to 0, the corresponding pin state is read. Determined by the states of pins P35 to P30. Rev. 1.00 Sep. 19, 2008 Page 550 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.3.4 Port 3 Open Drain Control Register (P3ODR) P3ODR specifies the output type of each port 3 pin. Bit Bit Name Initial Value R/W Description 7, 6 All 0 Reserved These bits are always read as 0. Only the initial values should be written to these bits. 5 P35ODR 0 R/W 4 P34ODR 0 R/W 3 P33ODR 0 R/W 2 P32ODR 0 R/W 1 P31ODR 0 R/W 0 P30ODR 0 R/W 10.3.5 When OE-B/CKE-B output is not selected, setting a P3ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P3ODR bit to 0 makes the corresponding pin a CMOS output pin. Pin Functions Port 3 pins also function as the pins for SCI I/Os, I2C I/Os, and bus control signal outputs. The correspondence between the register specification and the pin functions is shown below. • P35/OE-B/CKE-B*4/SCK1/SCL0 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit ICE in ICCRA_0 of the I2C, bit C/A in SMR_1 and bits CKE0 and CKE1 in SCR_1 of the SCI, bits OEE and RMTS2 to RMTS0 in DRAMCR of the bus controller, bit OES in PFCR2, and bit P35DDR. Rev. 1.00 Sep. 19, 2008 Page 551 of 1270 REJ09B0466-0100 Section 10 I/O Ports • Modes 1, 2, 4, and 7 (EXPE = 1) OEE 0 1 OES 1 RMTS2 0 Areas 2 Areas 2 to to 5 are to 5 are RMTS0 DRAM continu- space ous SDRAM space ICE 0 CKE1 C/A 1 1 0 CKE0 0 1 1 1 1 1 P35 SCK1 SCK1 1 1 0 0 0 0 0 0 1 Pin P35 P35 SCK1 function input output*1 output*1 output*1 input I/O*2 input output*1 output*1 output*1 input P35DDR 0 SCK1 SCK1 SCL0 P35 SCK1 SCL0 OE-B CKE-B I/O*2 output*3 output*3*4 • Mode 7 (EXPE = 0) OEE 0 OES RMTS2 to RMTS0 ICE 0 CKE1 C/A 1 1 0 CKE0 0 P35DDR Pin function Notes: 1. 2. 3. 4. 1 1 0 0 1 P35 input P35 output*1 SCK1 output*1 SCK1 output*1 SCK1 input SCL0 I/O*2 NMOS open-drain output when P35ODR = 1. NMOS open-drain output regardless of P35ODR. OE-B/CKE-B output when the OES bit in PFCR2 is 0. Not supported in the H8S/2426 Group and H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 552 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P34/SCK0/SCK4-A/SDA0 The pin function is switched as shown below according to the combination of bit ICE in ICCRA_0 of the I2C, bit C/A in SMR_0 and bits CKE0 and CKE1 in SCR_0 and SCR_4 of the SCI, and bit P34DDR. ICE 0 CKE1 1 1 1 0 C/A 0 CKE0 0 P34DDR 0 Pin function Notes: 1. 2. 3. 4. 1 1 P34 input P34 SCK0/SCK4-A SCK0/SCK4-A SCK0/SCK4-A output*1 output*1*3*4 output*1*3*4 input*4 SDA0 I/O*2 NMOS open-drain output when P34ODR = 1. NMOS open-drain output regardless of P34ODR. Simultaneous output of SCK0 and SCK4 cannot be set. SCK4-A input/output when the SCK4S bit in PFCR4 is 0. • P33/RxD1/SCL1 The pin function is switched as shown below according to the combination of bit ICE in ICCRA_1 of the I2C, bit RE in SCR_1 of the SCI, and bit P33DDR. ICE 0 RE P33DDR Pin function 1 0 0 P33 input 1 1 P33 output* 1 RxD1 input SCL1 I/O*2 Notes: 1. NMOS open-drain output when P33ODR = 1. 2. NMOS open-drain output regardless of P33ODR. Rev. 1.00 Sep. 19, 2008 Page 553 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P32/RxD0/IrRxD/SDA1 The pin function is switched as shown below according to the combination of bit ICE in ICCRA_1 of the I2C, bit RE in SCR_0 of the SCI, and bit P32DDR. ICE 0 RE 1 1 RxD0/IrRxD input SDA1 I/O*2 0 P32DDR 0 Pin function 1 P32 input 1 P32 output* Notes: 1. NMOS open-drain output when P32ODR = 1. 2. NMOS open-drain output regardless of P32ODR. • P31/TxD1 The pin function is switched as shown below according to the combination of bit TE in SCR_1 of the SCI and bit P31DDR. TE 0 P31DDR Pin function Note: * 1 0 1 P31 input P31 output* TxD1 output* NMOS open-drain output when P31ODR = 1. • P30/TxD0/IrTxD The pin function is switched as shown below according to the combination of bit TE in SCR_0 of the SCI and bit P30DDR. TE 0 P30DDR Pin function Note: * 1 0 1 P30 input P30 output* TxD0/IrTxD output* NMOS open-drain output when P30ODR = 1. Rev. 1.00 Sep. 19, 2008 Page 554 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.4 Port 4 Port 4 is an 8-bit input-only port that also has other functions, such as analog input pins. Port 4 has the following register. • Port 4 register (PORT4) 10.4.1 Port 4 Register (PORT4) PORT4 is an 8-bit read-only register that shows the pin states of port 4. PORT4 cannot be modified. Bit Bit Name Initial Value R/W Description 7 P47 * R The pin states are always read from this register. 6 P46 * R 5 P45 * R 4 P44 * R 3 P43 * R 2 P42 * R 1 P41 * R 0 P40 * R Note: * 10.4.2 Determined by the states of pins P47 to P40. Pin Functions Port 4 also functions as the pins for A/D converter analog inputs and interrupt inputs (the H8S/2424 Group). The correspondence between pins is as follows. (1) Pin Functions of H8S/2426 Group and H8S/2426R Group • P40/AN0_0, P41/AN1_0, P42/AN2_0, P43/AN3_0, P44/AN4_0, P45/AN5_0, P46/AN6_0, P47/AN7_0 Pin function ANn_0 input Legend: n = 7 to 0 Rev. 1.00 Sep. 19, 2008 Page 555 of 1270 REJ09B0466-0100 Section 10 I/O Ports (2) Pin Functions of H8S/2424 Group • P47/IRQ7-B/AN7_0 Pin function AN7_0 input IRQ7-B interrupt input* • P46/IRQ6-B/AN6_0 Pin function AN6_0 input IRQ6-B interrupt input* • P45/IRQ5-B/AN5_0 Pin function AN5_0 input IRQ5-B interrupt input* • P44/IRQ4-B/AN4_0 Pin function AN4_0 input IRQ4-B interrupt input* • P43/IRQ3-B/AN3_0 Pin function AN3_0 input IRQ3-B interrupt input* • P42/IRQ2-B/AN2_0 Pin function AN2_0 input IRQ2-B interrupt input* • P41/IRQ1-B/AN1_0 Pin function AN1_0 input IRQ1-B interrupt input* • P40/IRQ0-B/AN0_0 Pin function AN0_0 input IRQ0-B interrupt input* Note: * IRQn input when the ITSn bit in ITSR is 1. (n = 7 to 0) Rev. 1.00 Sep. 19, 2008 Page 556 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.5 Port 5 Port 5 is a 4-bit I/O port. Port 5 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. • • • • • Port 5 data direction register (P5DDR) Port 5 data register (P5DR) Port 5 register (PORT5) Port 5 open drain control register (P5ODR) Port function control register 4 (PFCR4) 10.5.1 Port 5 Data Direction Register (P5DDR) The individual bits of P5DDR specify input or output for the pins of port 5. P5DDR cannot be read; if it is, an undefined value will be read. Bit Initial Value R/W Description 7 to 4 All 0 Reserved 3 P53DDR 0 W 2 P52DDR 0 W 1 P51DDR 0 W When a pin function is specified as a general purpose I/O, setting this bit to 1 makes the corresponding pin an output port, while clearing this bit to 0 makes the corresponding pin an input port. 0 P50DDR 0 W 10.5.2 Bit Name Port 5 Data Register (P5DR) P5DR stores output data for the port 5 pins. Bit Bit Name Initial Value R/W Description 7 to 4 All 0 Reserved These bits are always read as 0 and cannot be modified. 3 P53DR 0 R/W 2 P52DR 0 R/W 1 P51DR 0 R/W 0 P50DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. Rev. 1.00 Sep. 19, 2008 Page 557 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.5.3 Port 5 Register (PORT5) PORT5 shows the pin states of port 5. PORT5 cannot be modified. Bit Bit Name Initial Value R/W Description 7 to 4 Undefined R Reserved If these bits are read, they will return an undefined value. 3 P53 * R 2 P52 * R 1 P51 * R 0 P50 * R Note: * 10.5.4 If the P53 to P50 bits are read while a P5DDR bit is set to 1, the corresponding P5DR value is read. If this register is read while a P5DDR bit is cleared to 0, the corresponding pin state is read. Determined by the states of pins P53 to P50. Port 5 Open Drain Control Register (P5ODR) P5ODR specifies the output type of each port 5 pin. Bit Bit Name Initial Value R/W Description 7 to 4 All 0 Reserved These bits are always read as 0. Only the initial values should be written to these bits. 3 P53ODR 0 R/W 2 P52ODR 0 R/W 1 P51ODR 0 R/W 0 P50ODR 0 R/W Rev. 1.00 Sep. 19, 2008 Page 558 of 1270 REJ09B0466-0100 When BACK-B/BREQO-B output is not selected, setting a P5ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P5ODR bit to 0 makes the corresponding pin a CMOS output pin. Section 10 I/O Ports 10.5.5 Pin Functions Port 5 pins also function as the pins for SCI I/Os, A/D converter inputs, interrupt inputs, I2C I/Os, bus control signal I/Os, JTAG inputs, PPG outputs, TPU I/Os, and 8-bit timer I/Os. The correspondence between the register specification and the pin functions is shown below. • P53/IRQ3-A/ADTRG0-A/TRST*3 The pin function is switched as shown below according to the combination of bits TRGS1, TRGS0, and EXTRGS in ADCR_0 of the ADC, bit P53DDR, and bit ITS3 in ITSR of the interrupt controller. P53DDR Pin function 0 1 P53 input P53 output ADTRG0-A input* 1 IRQ3-A interrupt input*2 TRST input* 3 Notes: 1. ADTRG0-A input when the EXTRGS bit in ADCR0 is 0, and TRGS1 = TRGS0 = 1. 2. IRQ3-A input when the ITS3 bit in ITSR is 0. 3. TRST input when BSCANE pin = 1 and EMLE = 0 in the 145-pin package. Rev. 1.00 Sep. 19, 2008 Page 559 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P52/SCK2/IRQ2-A/BACK-B/PO4-B/TIOCA4-B/TMO0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bits OS3 to OS0 in TCSR0 of 8-bit timer, bits MD3 to MD0 in TMDR_4 of TPU, bits IOA3 to IOA0 in TIOR_4, TPU channel 4 settings by bits CCLR1 and CCLR0 in TCR_4, bit NDER4 in NDERL of PPG, bit C/A in SMR_2 and bits CKE0 and CKE1 in SCR_2 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, bit BACKS in PFCR4, bit P52DDR, bit NDER4 in NDERL of the PPG, and bit ITS2 in ITSR of the interrupt controller. • Modes 1, 2, 4, and 7 (EXPE = 1) BRLE BACKS BRLE = 0 or BRLE = 1 and BACKS = 0 TPU channel (1) in table 4 settings below OS3 to OS0 CKE1 C/A CKE0 P52DDR (2) in table below Not all 0 1 1 1 All 0 0 0 0 0 1 1 0 1 TIOCA4-B 3 output* P52 input P52 output PO4-B 2 output* SCK2 output SCK2 output SCK2 input TMO0-B 4 output* BACK-B output NDER4 Pin function BRLE = 1 and BACKS = 1 TIOCA4-B input* IRQ2-A interrupt input* 1 Rev. 1.00 Sep. 19, 2008 Page 560 of 1270 REJ09B0466-0100 3 Section 10 I/O Ports • Mode 7 (EXPE = 0) BRLE BACKS TPU channel (1) in table 4 settings below (2) in table below OS3 to OS0 CKE1 C/A CKE0 P52DDR 0 1 NDER4 0 TIOCA4-B 3 output* P52 input P52 output Pin function All 0 Not all 0 1 1 1 1 1 PO4-B 2 output* SCK2 output SCK2 output SCK2 input TMO0-B 4 output* 0 0 0 TIOCA4-B input* 3 IRQ2-A interrupt input* 1 Notes: 1. 2. 3. 4. IRQ2-A input when the ITS2 bit in ITSR is 0. PO4-B output when the PPGS bit in PFCR3 is 1. TIOCA4-B input/output when the TPUS bit in PFCR3 is 1. TMO0-B output when the TMRS bit in PFCR3 is 1. TPU channel 4 settings MD3 to MD0 IOB3 to IOB0 (2) (1) B'0000, B'01×× (1) (2) (1) (2) B'0010 B'001x B'0011 Other than B'××00 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 Other than B'××00 B'××00 CCLR1, CCLR0 Other than B'10 B'10 Output function Output compare output PWM mode 1 output PWM mode 2 output Legend: ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 561 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P51/RxD2/IRQ1-A/SCL3/BREQ-B/PO2-B/TIOCC3-B/TMCI0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bit ICE in ICCRA_3 of the I2C, bits MD3 to MD0 in TMDR_3 of TPU, bits IOC3 to IOC0 in TIORL_3, TPU channel 3 settings by bits CCLR2 to CCLR0 in TCR_3, bit NDER2 in NDERL of PPG, bit RE in SCR_2 of the SCI, bit P51DDR, and bit ITS1 in ITSR of the interrupt controller. • Modes 1, 2, 4, and 7 (EXPE = 1) BRLE BREQS BRLE = 0 or BRLE = 1 and BREQS = 0 ICE TPU channel 3 settings BRLE = 1 and BREQS = 1 0 (1) in table below (2) in table below 1 RE 1 P51DDR 0 1 1 NDER2 0 1 TIOCC3-B 3 output* P51 input P51 output PO2-B 2 output* RxD2 input SCL3 I/O BREQ-B input Pin function 0 TIOCC3-B input* IRQ1-A interrupt input* 1 4 TMCI0-B input* Rev. 1.00 Sep. 19, 2008 Page 562 of 1270 REJ09B0466-0100 3 Section 10 I/O Ports • Mode 7 (EXPE = 0) BRLE BREQS ICE TPU channel 3 settings (1) in table below 0 1 (2) in table below RE P51DDR 0 1 NDER2 TIOCC3-B output*3 P51 input Pin function 1 1 0 1 P51 output PO2-B output*2 RxD2 input SCL3 I/O 0 3 TIOCC3-B input* IRQ1-A interrupt input*1 4 TMCI0-B input* TPU channel 3 settings (2) MD3 to MD0 IOC3 to IOC0 (1) B'0000 (2) (1) B'001× B'0010 B'0011 Other than B'××00 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 CCLR2 to CCLR0 Output function Output compare output (1) (2) Other than B'101 PWM*3 mode PWM mode 1 output 2 output B'101 Legend: ×: Don’t care Notes: 1. IRQ1-A input when the ITS1 bit in ITSR is 0. 2. PO2-B output when the PPGS bit in PFCR3 is 1. 3. TIOCC3-B input/output when the TPUS bit in PFCR3 is 1. 4. TMCI0-B input when the TMRS bit in PFCR3 is 1. Rev. 1.00 Sep. 19, 2008 Page 563 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P50/TxD2/IRQ0-A/SDA3/BREQO-B*2/PO0-B/TIOCA3-B/TMRI0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bit ICE in ICCRA_3 of the I2C, bits MD3 to MD0 in TMDR_3 of TPU, bits IOA3 to IOA0 in TIORH_3, TPU channel 3 settings by bits CCLR2 to CCLR0 in TCR_3, bit NDER0 in NDERL of PPG, bit TE in SCR_2 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, bit BREQOS in PFCR4, bit P50DDR, and bit ITS0 in ITSR of the interrupt controller. • Modes 1, 2, 4, and 7 (EXPE = 1) BRLE 0 1 BREQOE BREQOS BREQOE = 0 or BREQOE = 1 and BREQOS = 0 BREQOE = 1 and BREQOS = 1 ICE TPU channel 3 settings 0 (1) in table below 1 (2) in table below 0 (1) in table below (2) in table below 1 TE 1 1 P50DDR 0 1 1 0 1 1 NDER0 0 1 0 1 Pin function 0 0 TIOCA3-B P50 P50 PO0-B TxD2 SDA3 TIOCA3-B P50 P50 PO0-B TxD2 SDA3 output*3 input output output*2 output I/O output*3 input output output*2 output I/O TIOCA3-B input*3 TIOCA3-B input*3 IRQ0-A interrupt input* 1 TMRI0-B input*4 Rev. 1.00 Sep. 19, 2008 Page 564 of 1270 REJ09B0466-0100 BREQO-B output Section 10 I/O Ports • Mode 7 (EXPE = 0) BRLE BREQOE BREQOS ICE TPU channel 3 settings (1) in table below 0 1 (2) in table below TE P50DDR 0 1 NDER0 TIOCA3-B output*3 P50 input Pin function 1 1 0 1 P50 output PO0-B output*2 TxD2 output SDA3 I/O 0 TIOCA3-B input* 3 IRQ0-A interrupt input*1 TMRI0-B input*4 TPU channel 3 settings (2) MD3 to MD0 IOA3 to IOA0 (1) B'0000 (2) (1) B'001× B'0010 B'0011 Other than B'××00 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 CCLR2 to CCLR0 Output function Output compare output (1) (2) Other than B'001 PWM*3 mode PWM mode 1 output 2 output B'001 Legend: ×: Don’t care Notes: 1. IRQ0-A input when the ITS0 bit in ITSR is 0. 2. PO0-B output when the PPGS bit in PFCR3 is 1. 3. TIOCA3-B input/output when the TPUS bit in PFCR3 is 1. 4. TMRI0-B input when the TMRS bit in PFCR3 is 1. Rev. 1.00 Sep. 19, 2008 Page 565 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.6 Port 6 Note: Port 6 is not supported in the H8S/2424 Group. Port 6 is a 6-bit I/O port that also has other functions. Port 6 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. • • • • • Port 6 data direction register (P6DDR) Port 6 data register (P6DR) Port 6 register (PORT6) Port 6 open drain control register (P6ODR) Port function control register 3 (PFCR3) 10.6.1 Port 6 Data Direction Register (P6DDR) The individual bits of P6DDR specify input or output for the pins of port 6. P6DDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7, 6 All 0 Reserved 5 P65DDR 0 W 4 P64DDR 0 W 3 P63DDR 0 W When a pin function is specified as a general purpose I/O, setting this bit to 1 makes the corresponding pin an output port, while clearing this bit to 0 makes the corresponding pin an input port. 2 P62DDR 0 W 1 P61DDR 0 W 0 P60DDR 0 W Rev. 1.00 Sep. 19, 2008 Page 566 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.6.2 Port 6 Data Register (P6DR) P6DR stores output data for the port 6 pins. Bit Bit Name Initial Value R/W Description 7, 6 All 0 Reserved These bits are always read as 0 and cannot be modified. 5 P65DR 0 R/W 4 P64DR 0 R/W 3 P63DR 0 R/W 2 P62DR 0 R/W 1 P61DR 0 R/W 0 P60DR 0 R/W 10.6.3 Output data for a pin is stored when the pin function is specified as a general purpose I/O. Port 6 Register (PORT6) PORT6 shows the pin states of port 6. PORT6 cannot be modified. Bit Bit Name Initial Value R/W Description 7, 6 Undefined Reserved If these bits are read, they will return an undefined value. 5 P65 * R 4 P64 * R 3 P63 * R 2 P62 * R 1 P61 * R 0 P60 * R Note: * If this register is read while a P6DDR bit is set to 1, the corresponding P6DR value is read. If this register is read while a P6DDR bit is cleared to 0, the corresponding pin state is read. Determined by the states of pins P65 to P60. Rev. 1.00 Sep. 19, 2008 Page 567 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.6.4 Port 6 Open Drain Control Register (P6ODR) P6ODR specifies the output type of each port 6 pin. Bit Bit Name Initial Value R/W Description 7, 6 All 0 Reserved These bits are always read as 0. Only the initial values should be written to these bits. 5 P65ODR 0 R/W 4 P64ODR 0 R/W 3 P63ODR 0 R/W 2 P62ODR 0 R/W 1 P61ODR 0 R/W 0 P60ODR 0 R/W 10.6.5 Setting a P6ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P6ODR bit to 0 makes the corresponding pin a CMOS output pin. Pin Functions Port 6 pins also function as 8-bit timer I/Os, interrupt inputs, and DMAC I/Os. The correspondence between the register specification and the pin functions is shown below. • P65/IRQ13-A/DACK1/TMO1-A The pin function is switched as shown below according to the combination of bit SAE1 in DMABCRH of the DMAC, bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit TMRS in PFCR3, bit P65DDR, and bit ITS13 in ITSR of the interrupt controller. SAE1 0 OS3 to OS0 P65DDR Pin function All 0 0 P65 input 1 Not all 0 1 P65 output DACK1 output 2 TMO1-A output* IRQ13-A interrupt input* 1 Notes: 1. IRQ13-A input when the ITS13 bit in ITSR is 0. 2. TMO1-A output when the TMRS bit in PFCR3 is 0. Rev. 1.00 Sep. 19, 2008 Page 568 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P64/IRQ12-A/DACK0/TMO0-A The pin function is switched as shown below according to the combination of bit SAE0 in DMABCRH of the DMAC, bits OS3 to OS0 in TCSR_0 of the 8-bit timer, bit TMRS in PFCR3, bit P64DDR, and bit ITS12 in ITSR of the interrupt controller. SAE0 0 OS3 to OS0 P64DDR Pin function All 0 0 Not all 0 1 P64 input 1 P64 output DACK0 output 2 TMO0-A output* IRQ12-A interrupt input* 1 Notes: 1. IRQ12-A input when the ITS12 bit in ITSR is 0. 2. TMO0-A output when the TMRS bit in PFCR3 is 0. • P63/IRQ11-A/TEND1/TMCI1-A The pin function is switched as shown below according to the combination of bit TEE1 in DMATCR of the DMAC, bit TMRS in PFCR3, bit P63DDR, and bit ITS11 in ITSR of the interrupt controller. TEE1 P63DDR Pin function 0 1 0 1 P63 input P63 output TEND1 output IRQ11-A interrupt input* 1 2 3 TMCI1-A input* * Notes: 1. IRQ11-A input when the ITS11 bit in ITSR is 0. 2. When used as the external clock input pin for the TMR, its pin function should be specified to the external clock input by the CKS2 to CKS0 bits in TCR_1. 3. TMCI1-A input when the TMRS bit in PFCR3 is 0. Rev. 1.00 Sep. 19, 2008 Page 569 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P62/IRQ10-A/TEND0/TMCI0-A The pin function is switched as shown below according to the combination of bit TEE0 in DMATCR of the DMAC, bit TMRS in PFCR3, bit P62DDR, and bit ITS10 in ITSR of the interrupt controller. TEE0 P62DDR Pin function 0 1 0 1 P62 input P62 output TEND0 output IRQ10-A interrupt input* 1 2 3 TMCI0-A input* * Notes: 1. IRQ10-A input when the ITS10 bit in ITSR is 0. 2. When used as the external clock input pin for the TMR, its pin function should be specified to the external clock input by the CKS2 to CKS0 bits in TCR_0. 3. TMCI0-A input when the TMRS bit in PFCR3 is 0. • P61/IRQ9-A/DREQ1/TMRI1-A The pin function is switched as shown below according to the combination of bit TMRS in PFCR3, bit P61DDR, and bit ITS9 in ITSR of the interrupt controller. P61DDR Pin function 0 1 P61 input P61 output 1 3 TMRI1-A input* * DREQ1 input IRQ9-A interrupt input* 2 Notes: 1. When used as the counter reset input pin for the TMR, both the CCLR1 and CCLR0 bits in TCR_1 should be set to 1. 2. IRQ9-A input when the ITS9 bit in ITSR is 0. 3. TMRI1-A input when the TMRS bit in PFCR3 is 0. Rev. 1.00 Sep. 19, 2008 Page 570 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P60/IRQ8-A/DREQ0/TMRI0-A The pin function is switched as shown below according to the combination of bit TMRS in PFCR3, bit P60DDR, and bit ITS8 in ITSR of the interrupt controller. P60DDR Pin function 0 1 P60 input P60 output 1 3. TMRI0-A input* * DREQ0 input IRQ8-A interrupt input* 2 Notes: 1. When used as the counter reset input pin for the TMR, both the CCLR1 and CCLR0 bits in TCR_0 should be set to 1. 2. IRQ8-A input when the ITS8 bit in ITSR is 0. 3. TMRI0-A input when the TMRS bit in PFCR3 is 0. Rev. 1.00 Sep. 19, 2008 Page 571 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.7 Port 8 Port 8 is a 6-bit I/O port that also has other functions. Port 8 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. • • • • • Port 8 data direction register (P8DDR) Port 8 data register (P8DR) Port 8 register (PORT8) Port 8 open drain control register (P8ODR) Port function control register 3 (PFCR3) 10.7.1 Port 8 Data Direction Register (P8DDR) The individual bits of P8DDR specify input or output for the pins of port 8. P8DDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7, 6 5 P85DDR All 0 Reserved 0 W When a pin function is specified as a general purpose I/O, setting this bit to 1 makes the corresponding pin an output port, while clearing this bit to 0 makes the corresponding pin an input port. 4 P84DDR 0 W 3 P83DDR 0 W 2 P82DDR 0 W 1 P81DDR 0 W 0 P80DDR 0 W Rev. 1.00 Sep. 19, 2008 Page 572 of 1270 REJ09B0466-0100 Bits 4, 2, and 0 are reserved in the H8S/2424 Group. Section 10 I/O Ports 10.7.2 Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins. Bit Bit Name Initial Value R/W Description 7, 6 All 0 Reserved These bits are always read as 0 and cannot be modified. 5 P85DR 0 R/W 4 P84DR 0 R/W 3 P83DR 0 R/W 2 P82DR 0 R/W 1 P81DR 0 R/W 0 P80DR 0 R/W 10.7.3 Output data for a pin is stored when the pin function is specified as a general purpose I/O. Bits 4, 2, and 0 are reserved in the H8S/2424 Group. Port 8 Register (PORT8) PORT8 shows the pin states of port 8. PORT8 cannot be modified. Bit Bit Name Initial Value R/W Description 7, 6 Undefined Reserved If these bits are read, they will return an undefined value. 5 P85 * R 4 P84 * R 3 P83 * R 2 P82 * R 1 P81 * R 0 P80 * R Note: * If this register is read while a P8DDR bit is set to 1, the corresponding P8DR value is read. If this register is read while a P8DDR bit is cleared to 0, the corresponding pin state is read. Bits 4, 2, and 0 are reserved in the H8S/2424 Group. Determined by the states of pins P85 to P80. Rev. 1.00 Sep. 19, 2008 Page 573 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.7.4 Port 8 Open Drain Control Register (P8ODR) P8ODR specifies the output type of each port 8 pin. Bit Bit Name Initial Value R/W Description 7, 6 All 0 Reserved These bits are always read as 0. Only the initial values should be written to these bits. 5 P85ODR 0 R/W 4 P84ODR 0 R/W 3 P83ODR 0 R/W 2 P82ODR 0 R/W 1 P81ODR 0 R/W 0 P80ODR 0 R/W 10.7.5 Setting a P8ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P8ODR bit to 0 makes the corresponding pin a CMOS output pin. Bits 4, 2, and 0 are reserved in the H8S/2424 Group. Pin Functions Port 8 pins also function as SCI I/Os, interrupt inputs, EXDMAC I/Os, PPG outputs, TPU I/Os, and 8-bit timer I/Os. The correspondence between the register specification and the pin functions is shown below. (1) Pin Functions of H8S/2426 Group and H8S/2426R Group • P85/EDACK3/IRQ5-B/SCK3/PO5-B/TIOCB4-B/TMO1-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit NDER5 in NDERL of the PPG, bit AMS in EDMDR_3 of the EXDMAC, bit C/A in SMR_3 and bits CKE0 and CKE1 in SCR_3 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, bit P85DDR, and bit ITS5 in ITSR of the interrupt controller. Rev. 1.00 Sep. 19, 2008 Page 574 of 1270 REJ09B0466-0100 Section 10 I/O Ports • Modes 1, 2, 4, and 7 (EXPE = 1) TPU channel 4 settings (1) in table below OS3 to OS0 AMS CKE1 C/A CKE0 P85DDR 0 1 NDER5 Pin function (2) in table below All 0 Not all 0 0 1 1 1 1 0 1 P85 output PO5-B 2 output* SCK3 output SCK3 output SCK3 input 0 0 0 TIOCB4-B P85 input 3 output* 1 TIOCB4-B input* EDACK3 TMO1-B 4 output output* 3 IRQ5-B interrupt input* 1 • Mode 7 (EXPE = 0) TPU channel 4 settings (1) in table below OS3 to OS0 All 0 Not all 0 AMS CKE1 C/A CKE0 P85DDR 0 1 NDER5 TIOCB4-B 3 output* P85 input Pin function (2) in table below 1 1 1 1 0 1 P85 output PO5-B 2 output* SCK3 output SCK3 output SCK3 input TMO1-B 4 output* 0 0 0 TIOCB4-B input* 3 IRQ5-B interrupt input* 1 Notes: 1. 2. 3. 4. IRQ5-B input when the ITS5 bit in ITSR is 1. PO5-B output when the PPGS bit in PFCR3 is 1. TIOCB4-B input/output when the TPUS bit in PFCR3 is 1. TMO1-B output when the TMRS bit in PFCR3 is 1. Rev. 1.00 Sep. 19, 2008 Page 575 of 1270 REJ09B0466-0100 Section 10 I/O Ports TPU channel 4 settings MD3 to MD0 (2) (1) (2) B'0000, B'01×× (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR1, CCLR0 Other than B'10 B'10 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Other than B'××00 Legend: ×: Don’t care • P84/IRQ4-B/EDACK2 The pin function is switched as shown below according to the combination of bit AMS in EDMDR_2 of the EXDMAC, bit P84DDR, and bit ITS4 in ITSR of the interrupt controller. Operating mode 1, 2, 4, 7 (EXPE = 1) AMS 0 P84DDR Pin function 7 (EXPE = 0) 1 0 1 0 1 P84 input P84 output EDACK2 output P84 input P84 output IRQ4-B interrupt input* Note: * IRQ4-B input when the ITS4 bit in ITSR is 1. Rev. 1.00 Sep. 19, 2008 Page 576 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P83/ETEND3*5/IRQ3-B*5/RxD3/PO3-B/TIOCD3-B/TMCI1-B The pin function is switched as shown below according to the combination of bit ETENDE in EDMDR_3 of the EXDMAC, bit RE in SCR_3 of the SCI, TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, bit P83DDR, and bit ITS3 in ITSR of the interrupt controller. • Modes 1, 2, 4, and 7 (EXPE = 1) TPU channel 3 settings (1) in table below (2) in table below ETENDE RE P83DDR 0 1 NDER3 TIOCD3-B output*3 P83 input Pin function 0 1 1 1 0 1 P83 output PO3-B output*2 RxD3 input ETEND3 output 0 3 TIOCD3-B input* IRQ3-B interrupt input*1 4 TMCI1-B input* Rev. 1.00 Sep. 19, 2008 Page 577 of 1270 REJ09B0466-0100 Section 10 I/O Ports • Mode 7 (EXPE = 0) TPU channel 3 settings (1) in table below (2) in table below ETENDE RE P83DDR 0 NDER3 Pin function 0 1 0 TIOCD3-B output*3 P83 input 1 1 0 1 P83 output PO3-B output* TIOCD3-B input* 2 RxD3 input 3 IRQ3-B interrupt input*1 4 TMCI1-B input* Notes: 1. 2. 3. 4. IRQ3-B input when the ITS3 bit in ITSR is 1. PO3-B output when the PPGS bit in PFCR3 is 1. TIOCD3-B input/output when the TPUS bit in PFCR3 is 1. TMCI1-B input when the TMRS bit in PFCR3 is 1. TPU channel 3 settings (2) MD3 to MD0 (1) B'0000 (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR2 to CCLR0 Other than B'110 B'110 Output function Output compare output PWM mode 2 output IOD3 to IOD0 Legend: ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 578 of 1270 REJ09B0466-0100 Other than B'××00 Section 10 I/O Ports • P82/IRQ2-B/ETEND2 The pin function is switched as shown below according to the combination of bit ETENDE in EDMDR_2 of the EXDMAC, bit P82DDR, and bit ITS2 in ITSR of the interrupt controller. Operating mode 1, 2, 4, 7 (EXPE = 1) ETENDE 0 P82DDR Pin function 7 (EXPE = 0) 1 0 1 0 1 P82 input P82 output ETEND2 output P82 input P82 output IRQ2-B interrupt input* Note: * IRQ2-B input when the ITS2 bit in ITSR is 1. • P81/EDREQ3/IRQ1-B/TxD3/PO1-B/TIOCB3-B/TMRI1-B The pin function is switched as shown below according to the combination of bit TE in SCR_3 of the SCI, TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, bit P81DDR, and bit ITS1 in ITSR of the interrupt controller. TPU channel 3 settings (1) in table below TE P81DDR NDER1 Pin function (2) in table below 0 0 1 1 1 0 1 TIOCB3-B output*3 P81 input P81 output PO1-B output*2 TxD3 output 3 TIOCB3-B input* EDREQ3 input IRQ1-B interrupt input*1 TMRI1-B input*4 Notes: 1. 2. 3. 4. IRQ1-B input when the ITS1 bit in ITSR is 1. PO1-B output when the PPGS bit in PFCR3 is 1. TIOCB3-B input/output when the TPUS bit in PFCR3 is 1. TMRI1-B input when the TMRS bit in PFCR3 is 1. Rev. 1.00 Sep. 19, 2008 Page 579 of 1270 REJ09B0466-0100 Section 10 I/O Ports TPU channel 3 settings (2) MD3 to MD0 (1) B'0000 (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR2 to CCLR0 Other than B'010 B'010 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Other than B'××00 Legend: ×: Don’t care • P80/IRQ0-B/EDREQ2 The pin function is switched as shown below according to the combination of bit P80DDR and bit ITS0 in ITSR of the interrupt controller. P80DDR Pin function 0 1 P80 input P80 output EDREQ2 input IRQ0-B interrupt input* Note: * IRQ0-B input when the ITS0 bit in ITSR is 1. Rev. 1.00 Sep. 19, 2008 Page 580 of 1270 REJ09B0466-0100 Section 10 I/O Ports (2) Pin Functions of H8S/2424 Group • P85/SCK3/PO5-B/TIOCB4-B/TMO1-B The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit NDER5 in NDERL of the PPG, bit C/A in SMR_3 and bits CKE0 and CKE1 in SCR_3 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, and bit P85DDR. TPU channel 4 settings (1) in table below OS3 to OS0 CKE1 C/A CKE0 P85DDR 0 1 NDER5 TIOCB4-B 3 output* P85 input Pin function (2) in table below All 0 Not all 0 1 1 1 1 0 1 P85 output PO5-B 1 output* SCK3 output SCK3 output SCK3 input TMO1-B 3 output* 0 0 0 TIOCB4-B input* 2 Notes: 1. PO5-B output when the PPGS bit in PFCR3 is 1. 2. TIOCB4-B input/output when the TPUS bit in PFCR3 is 1. 3. TMO1-B output when the TMRS bit in PFCR3 is 1. TPU channel 4 settings MD3 to MD0 (2) (1) B'0000, B'01×× (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR1, CCLR0 Other than B'10 B'10 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Other than B'××00 Legend: ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 581 of 1270 REJ09B0466-0100 Section 10 I/O Ports • P83/PO3-B/TIOCD3-B/TMCI1-B/RxD3 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL of the PPG, bit RE in SCR_3 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, and bit P83DDR. TPU channel 3 settings (1) in table below (2) in table below RE P83DDR 0 NDER3 Pin function 0 TIOCD3-B output*2 1 1 0 P83 input 1 P83 output PO3-B output* TIOCD3-B input* 1 RxD3 input 2 3 TMCI1-B input* Notes: 1. PO3-B output when the PPGS bit in PFCR3 is 1. 2. TIOCD3-B input/output when the TPUS bit in PFCR3 is 1. 3. TMCI1-B input when the TMRS bit in PFCR3 is 1. TPU channel 3 settings (2) MD3 to MD0 (1) B'0000 (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR2 to CCLR0 Other than B'110 B'110 Output function Output compare output PWM mode 2 output IOD3 to IOD0 Legend: ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 582 of 1270 REJ09B0466-0100 Other than B'××00 Section 10 I/O Ports • P81/PO1-B/TIOCB3-B/TMRI1-B/TxD3 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL of the PPG, bit TE in SCR_3 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, and bit P81DDR. TPU channel 3 settings (1) in table below (2) in table below TE 0 P81DDR 0 NDER1 Pin function TIOCB3-B output*2 1 1 0 P81 input 1 P81 output PO1-B output* TIOCB3-B input* 1 TxD3 output 2 3 TMRI1-B input* Notes: 1. PO1-B output when the PPGS bit in PFCR3 is 1. 2. TIOCB3-B input/output when the TPUS bit in PFCR3 is 1. 3. TMRI1-B input when the TMRS bit in PFCR3 is 1. TPU channel 3 settings (2) MD3 to MD0 (1) B'0000 (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR2 to CCLR0 Other than B'010 B'010 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Other than B'××00 Legend: ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 583 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.8 Port 9 Port 9 is an 8-bit input-only port that also has other functions. Port 9 has the following register. • Port 9 register (PORT9) 10.8.1 Port 9 Register (PORT9) PORT9 is an 8-bit read-only register that shows the pin states of port 9. PORT9 cannot be modified. Bit Bit Name Initial Value R/W Description 7 P97 * R 6 P96 * R 5 P95 * The pin states are always read from this register. Bits 7, 6, and 3 to0 are reserved in the H8S/2424 Group. R 4 P99 * R 3 P93 * R 2 P92 * R 1 P91 * R 0 P90 * R Note: * Determined by the states of pins P97 to P90. Rev. 1.00 Sep. 19, 2008 Page 584 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.8.2 Pin Functions Port 9 also functions as the pins for A/D converter analog inputs and D/A converter analog outputs. The correspondence between pins is as follows. (1) Pin Functions of H8S/2426 Group and H8S/2426R Group • P97/AN15_1 Pin function AN15_1 input • P96/AN14_1 Pin function AN14_1 input • P95/AN13_1/DA3 Pin function AN13_1 input DA3 output • P94/AN12_1/DA2 Pin function AN12_1 input DA2 output • P93/AN11_1 Pin function AN11_1 input • P92/AN10_1 Pin function AN10_1 input • P91/AN9_1 Pin function AN9_1 input • P90/AN8_1 Pin function AN8_1 input Rev. 1.00 Sep. 19, 2008 Page 585 of 1270 REJ09B0466-0100 Section 10 I/O Ports (2) Pin Functions of H8S/2424 Group • P95/AN13_1/DA3 Pin function AN13_1 input DA3 output • P94/AN12_1/DA2 Pin function AN12_1 input DA2 output Rev. 1.00 Sep. 19, 2008 Page 586 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.9 Port A Port A is an 8-bit I/O port that also has other functions. Port A has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. • • • • • • • • • Port A data direction register (PADDR) Port A data register (PADR) Port A register (PORTA) Port A pull-up MOS control register (PAPCR) Port A open-drain control register (PAODR) Port function control register 0 (PFCR0)(the H8S/2424 Group) Port function control register 1 (PFCR1) Port function control register 4 (PFCR4) Port function control register 5 (PFCR5) Rev. 1.00 Sep. 19, 2008 Page 587 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.9.1 Port A Data Direction Register (PADDR) The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 PA7DDR 0 W • 6 PA6DDR 0 W Pins PA4 to PA0 are address outputs. 5 PA5DDR 0 W 4 PA4DDR 0 W 3 PA3DDR 0 W 2 PA2DDR 0 W 1 PA1DDR 0 W 0 PA0DDR 0 W For pins PA7 to PA5, when the corresponding bit of A23E to A21E is set to 1, setting a PADDR bit to 1 makes the corresponding pin an address output, while clearing the bit to 0 makes the corresponding pin an input port. Clearing one of bits A23E to A21E to 0 makes the corresponding pin an I/O port, and its function can be switched with PADDR. • Modes 1 and 2 Modes 7 (when EXPE = 1) and 4 When the corresponding bit of A23E to A16E is set to 1, setting a PADDR bit to 1 makes the corresponding pin an address output, while clearing the bit to 0 makes the corresponding pin an input port. Clearing one of bits A23E to A16E to 0 makes the corresponding pin an I/O port, and its function can be switched with PADDR. • Mode 7 (when EXPE = 0) Port A is an I/O port, and its pin functions can be switched with PADDR. Rev. 1.00 Sep. 19, 2008 Page 588 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.9.2 Port A Data Register (PADR) PADR stores output data for the port A pins. Bit Bit Name Initial Value R/W Description 7 PA7DR 0 R/W 6 PA6DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 PA5DR 0 R/W 4 PA4DR 0 R/W 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W 0 PA0DR 0 R/W 10.9.3 Port A Register (PORTA) PORTA shows the pin states of port A. PORTA cannot be modified. Bit Bit Name Initial Value R/W Description 7 PA7 * R 6 PA6 * R 5 PA5 * R If this register is read while a PADDR bit is set to 1, the corresponding PADR value is read. If this register is read while a PADDR bit is cleared to 0, the corresponding pin state is read. 4 PA4 * R 3 PA3 * R 2 PA2 * R 1 PA1 * R 0 PA0 * R Note: * Determined by the states of pins PA7 to PA0. Rev. 1.00 Sep. 19, 2008 Page 589 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.9.4 Port A Pull-Up MOS Control Register (PAPCR) PAPCR controls on/off of the input pull-up MOS for port A. Bits 7 to 5 are valid in modes 1 and 2 and all the bits are valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description 7 PA7PCR 0 R/W 6 PA6PCR 0 R/W When in an input port state, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. 5 PA5PCR 0 R/W 4 PA4PCR 0 R/W 3 PA3PCR 0 R/W 2 PA2PCR 0 R/W 1 PA1PCR 0 R/W 0 PA0PCR 0 R/W 10.9.5 Port A Open Drain Control Register (PAODR) PAODR specifies the output type of each port A pin. Bit Bit Name Initial Value R/W Description 7 PA7ODR 0 R/W 6 PA6ODR 0 R/W 5 PA5ODR 0 R/W 4 PA4ODR 0 R/W When not specified for address output or CS7 output*, setting a PAODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PAODR bit to 0 makes the corresponding pin a CMOS output pin. 3 PA3ODR 0 R/W 2 PA2ODR 0 R/W 1 PA1ODR 0 R/W 0 PA0ODR 0 R/W Note: * Not supported by the H8S/2426 Group and the H8S/2426R Group Rev. 1.00 Sep. 19, 2008 Page 590 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.9.6 Pin Functions Port A pins also function as the pins for address outputs, interrupt inputs, SSU I/Os, SCI I/Os, and bus control signal outputs. The correspondence between the register specification and the pin functions is shown below. • PA7/A23/CS7*4/IRQ7-A/SSO0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits SSO0S1 and SSO0S0 in PFCR5, bit CS7E in PFCR0 (the H8S/2424 Group), bit A23E in PFCR1, bit PA7DDR, and bit ITS7 in ITSR of the interrupt controller. • Modes 1, 2, and 4 A23E 0 4 CS7E* SSU settings PA7DDR Pin function 1 0 Can be used as I/O port Input state Output state 1 0 1 0 0 1 0 1 PA7 input PA7 output SSO0-B 2 input* SSO0-B 3 output* PA7 input CS7 4 output* PA7 input A23 output IRQ7-A interrupt input* 1 • Mode 7 (EXPE = 1) A23E 0 4 CS7E* SSU settings PA7DDR Pin function 1 1 0 Can be used as I/O port 0 1 PA7 input PA7 output Input state Output state 0 0 1 SSO0-B 2 input* SSO0-B 3 output* PA7 input CS7 4 output* 0 1 PA7 input A23 output IRQ7-A interrupt input* 1 Rev. 1.00 Sep. 19, 2008 Page 591 of 1270 REJ09B0466-0100 Section 10 I/O Ports • Mode 7 (EXPE = 0) A23E 4 CS7E* 0 SSU settings Can be used as I/O port Output state 0 1 0 PA7 input PA7 output SSO0-B input*2 SSO0-B output*3 PA7DDR Pin function Input state IRQ7-A interrupt input*1 Notes: 1. IRQ7-A input when the ITS7 bit in ITSR is 0. 2. SSO0-B input when SSO0S1 and SSO0S0 = B'01 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'000×1 or B'01×01. 3. SSO0-B output when SSO0S1 and SSO0S0 = B'01 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'001××, B'0101×, or B'10×1×. 4. Supported only by the H8S/2424 Group and not supported by the H8S/2426 and H8S/2426R Groups. SSO pin settings SSUMS 0 0 1 BIDE 0 1 0 MSS 0 1 TE 0 RE 1 0 1 1 Input Input Pin state 1 0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 Output Output Input Output Input Output Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 592 of 1270 REJ09B0466-0100 0 1 1 0 0 1 1 Output Output 1 0 1 Output Output Section 10 I/O Ports • PA6/A22/IRQ6-A/SSI0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of SSU, bit A22E in PFCR1, bits SSI0S1 and SSI0S0 in PFCR5, bit PA6DDR, and bit ITS6 in ITSR of the interrupt controller. • Modes 1, 2, and 4 A22E SSU settings Can be used as I/O port Output state 0 1 0 0 1 PA6 input PA6 output SSI0-B input*2 SSI0-B output*3 PA6 input A22 output PA6DDR Pin function Input state IRQ6-A interrupt input* 1 • Mode 7 EXPE 1 A22E 0 SSU settings Can be used as I/O port PA6DDR Pin function 0 0 PA6 input 1 1 Input state Output state 0 0 Can be used as I/O port 1 PA6 SSI0-B SSI0-B PA6 A22 output input*2 output*3 input output 0 PA6 input 1 Input state Output state 0 PA6 SSI0-B SSI0-B output input*2 output*3 IRQ6-A interrupt input* 1 Notes: 1. IRQ6-A input when the ITS6 bit in ITSR is 0. 2. SSI0-B input when SSI0S1 and SSI0S0 = B'01 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'001×1 or B'10××1. 3. SSI0-B output when SSI0S1 and SSI0S0 = B'01 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0001×. Rev. 1.00 Sep. 19, 2008 Page 593 of 1270 REJ09B0466-0100 Section 10 I/O Ports SSI pin settings SSUMS 0 0 1 BIDE 0 1 0 MSS 0 TE 0 RE 1 Pin state 1 1 0 0 1 1 Output Output Input 0 1 1 0 0 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 0 1 1 0 1 Input Input Input Input Input Legend: : Pin is not used by the SSU (can be used as I/O port) • PA5/A21/IRQ5-A/SSCK0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of the SSU, bit A21E in PFCR1, bits SSCK0S1 and SSCK0S0 in PFCR5, bit PA5DDR, and bit ITS5 in ITSR of the interrupt controller • Modes 1, 2, and 4 A21E SSU settings PA5DDR Pin function 0 Can be used as I/O port 1 Input state Output state 0 1 0 0 1 PA5 input PA5 output SSCK0-B input*2 SSCK0-B output*3 PA5 input A21 output IRQ5-A interrupt input*1 2 SSCK0-B input* Rev. 1.00 Sep. 19, 2008 Page 594 of 1270 REJ09B0466-0100 Section 10 I/O Ports • Mode 7 EXPE 1 A21E SSU settings PA5DDR Pin function 0 0 Can be used as I/O port 0 PA5 input Input state Output state 0 1 1 0 PA5 SSCK0-B SSCK0-B 2 3 output input* output* Can be used as I/O port 1 0 PA5 A21 input output 1 PA5 input Input state Output state 0 PA5 SSCK0-B SSCK0-B 2 3 output input* output* IRQ5-A interrupt input* 1 2 SSCK0-B input* Notes: 1. IRQ5-A input when the ITS5 bit in ITSR is 0. 2. SSCK0-B input when SSCK0S1 and SSCK0S0 = B'00 in PFCR5, and SSUMS, MSS, and SCKS = B'001 or B'101. 3. SSCK0-B output when SSCK0S1 and SSCK0S0 = B'00 in PFCR5, and SSUMS, MSS, and SCKS = B'×11. SSCK pin settings SSUMS 0 MSS 1 0 1 0 1 SCKS 0 1 0 1 0 1 0 1 Pin state Input Output Input Output Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 595 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PA4/A20/IRQ4-A/SCS0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of the SSU, bit A20E in PFCR1, bit PA4DDR, and bit ITS4 in ITSR of the interrupt controller. Operating mode 1, 2 4 EXPE A20E SSU settings PA4DDR Pin function 0 1 Can be used as I/O port 0 Input state Output state 0 SCS0-B input*2 SCS0-B output*3 1 A20 output PA4 input PA4 output IRQ4-A interrupt input* Operating mode 0 A20E Can be used as I/O port PA4DDR Pin function 0 1 PA4 input A20 output 1 7 EXPE SSU settings 0 1 PA4 input PA4 output 1 0 Input state Output state 0 SCS0-B SCS0-B 2 3 input* output* 1 Can be used as I/O port 0 1 PA4 input PA4 output Input state Output state 0 SCS0-B SCS0-B 2 3 input* output* 0 1 PA4 input A20 output IRQ4-A interrupt input* 1 Notes: 1. IRQ4-A input when the ITS4 bit in ITSR is 0. 2. SCSO-B input when SCS0S1 and SCS0S0 = B'01 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'00××, B'0101, or B'0110. 3. SCSO-B output when SCS0S1 and SCS0S0 = B'01 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'011×. Rev. 1.00 Sep. 19, 2008 Page 596 of 1270 REJ09B0466-0100 Section 10 I/O Ports SCS pin settings SSUMS 0 1 × MSS 0 CSS1 × CSS0 × 0 1 0 1 × Input Input Automatic I/O Output Pin state 1 0 × 1 Legend: ×: Don’t care : Pin is not used by the SSU (can be used as I/O port) • PA3/A19/SCK4-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit C/A in SMR_4 and bits CKE0 and CKE1 in SCR_4 of the SCI, bit A19E in PFCR1, bit SCK4S in PFCR4, and bit PA3DDR. Operating mode 1, 2 4 EXPE A19E CKE1 C/A CKE0 PA3DDR 0 A19 output PA3 input Pin function 0 1 0 1 1 1 1 0 1 PA3 output SCK4-B output* SCK4-B output* SCK4-B input* PA3 input A19 output 0 0 Rev. 1.00 Sep. 19, 2008 Page 597 of 1270 REJ09B0466-0100 Section 10 I/O Ports Operating 7 mode EXPE 0 A19E CKE1 0 0 C/A 1 0 PA3DDR 0 Pin function * 1 PA3 PA3 input output 1 1 1 0 1 1 0 CKE0 Note: 1 0 1 1 0 0 0 1 SCK4-B SCK4-B SCK4-B PA3 PA3 SCK4-B SCK4-B SCK4-B PA3 A19 output* output* input output output* output* input output input* input* SCK4-B input/output when the SCK4S bit in PFCR4 is 1. • PA2/A18/RxD4-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit RE in SCR_4 of the SCI, bit A18E in PFCR1, bit RXD4S in PFCR4, and bit PA2DDR. Operating 1, 2 4 EXPE A18E RE PA2DDR 7 mode Pin function Note: * 0 0 0 0 1 1 1 0 0 1 0 1 A18 PA2 PA2 RxD4-B PA2 A18 PA2 PA2 input output input* input output input output RxD4-B input when the RXD4S bit in PFCR4 is 1. REJ09B0466-0100 0 1 output Rev. 1.00 Sep. 19, 2008 Page 598 of 1270 1 0 0 RxD4-B PA2 input* 1 1 1 PA2 input output 0 RxD4-B PA2 input* 1 A18 input output Section 10 I/O Ports • PA1/A17/TxD4-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit TE in SCR_4 of the SCI, bit A17E in PFCR1, bit TXD4S in PFCR4, and bit PA1DDR. Operating 1, 2 4 EXPE A17E TE PA1DDR 7 mode Pin function Note: * 0 0 0 A17 PA1 output input 1 0 1 1 0 0 1 PA1 TxD4-B PA1 A17 PA1 output output* input output input 0 1 1 0 1 PA1 1 0 0 TxD4-B PA1 1 1 PA1 0 1 TxD4-B PA1 A17 output output* input output output* input output TxD4-A output when the TXD4S bit in PFCR4 is 1. • PA0/A16 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit A16E in PFCR1, and bit PA0DDR. Operating mode 1, 2 4 EXPE A16E PA0DDR Pin function 7 0 0 0 1 1 0 1 1 0 0 1 0 1 1 0 1 A16 PA0 PA0 PA0 A16 PA0 PA0 PA0 PA0 PA0 A16 output input output input output input output input output input output Rev. 1.00 Sep. 19, 2008 Page 599 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.9.7 Port A Input Pull-Up MOS States Port A has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used by pins PA7 to PA5 in modes 1 and 2, and by all pins in modes 4 and 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. Table 10.3 summarizes the input pull-up MOS states. Table 10.3 Input Pull-Up MOS States for Port A Mode Reset Hardware Standby Mode Software Standby Mode In Other Operations Off Off On/Off On/Off 4 or 7 PA7 to PA0 1 or 2 PA7 to PA5 On/Off On/Off PA4 to PA0 Off Off Legend: Off: Input pull-up MOS is always off. On/Off: Input pull-up MOS is on when in input port register state* and PAPCR = 1; otherwise off. Note: * Not available with SSU/SCI input Rev. 1.00 Sep. 19, 2008 Page 600 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.10 Port B Port B is an 8-bit I/O port that also has other functions. Port B has the following registers. • • • • • Port B data direction register (PBDDR) Port B data register (PBDR) Port B register (PORTB) Port B pull-up MOS control register (PBPCR) Port B open drain control register (PBODR) 10.10.1 Port B Data Direction Register (PBDDR) The individual bits of PBDDR specify input or output for the pins of port B. PBDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 PB7DDR 0 W • 6 PB6DDR 0 W 5 PB5DDR 0 W 4 PB4DDR 0 W 3 PB3DDR 0 W 2 PB2DDR 0 W 1 PB1DDR 0 W 0 PB0DDR 0 W Modes 1 and 2 Port B pins are address outputs regardless of the PBDDR settings. • Modes 7 (when EXPE = 1) and 4 Setting a PBDDR bit to 1 makes the corresponding pin an address output, while clearing a PBDDR bit to 0 makes the corresponding pin an input port. • Mode 7 (when EXPE = 0) Port B is an I/O port, and its pin functions can be switched with PBDDR. Rev. 1.00 Sep. 19, 2008 Page 601 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.10.2 Port B Data Register (PBDR) PBDR stores output data for the port B pins. Bit Bit Name Initial Value R/W Description 7 PB7DR 0 R/W 6 PB6DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 PB5DR 0 R/W 4 PB4DR 0 R/W 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W 0 PB0DR 0 R/W 10.10.3 Port B Register (PORTB) PORTB shows the pin states of port B. PORTB cannot be modified. Bit Bit Name Initial Value R/W Description 7 PB7 * R 6 PB6 * R 5 PB5 * R If this register is read while a PBDDR bit is set to 1, the corresponding PBDR value is read. If this register is read while a PBDDR bit is cleared to 0, the corresponding pin state is read. 4 PB4 * R 3 PB3 * R 2 PB2 * R 1 PB1 * R 0 PB0 * R Note: * Determined by the states of pins PB7 to PB0. Rev. 1.00 Sep. 19, 2008 Page 602 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.10.4 Port B Pull-Up MOS Control Register (PBPCR) PBPCR controls on/off of the input pull-up MOS for port B. PBPCR is valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description 7 PB7PCR 0 R/W 6 PB6PCR 0 R/W When in a input port register state, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. 5 PB5PCR 0 R/W 4 PB4PCR 0 R/W 3 PB3PCR 0 R/W 2 PB2PCR 0 R/W 1 PB1PCR 0 R/W 0 PB0PCR 0 R/W 10.10.5 Port B Open Drain Control Register (PBODR) PBODR specifies the output type of each port B pin. Bit Bit Name Initial Value R/W Description 7 PB7ODR 0 R/W 6 PB6ODR 0 R/W 5 PB5ODR 0 R/W 4 PB4ODR 0 R/W When not specified for address output, setting a PBODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PBODR bit to 0 makes the corresponding pin a CMOS output pin. 3 PB3ODR 0 R/W 2 PB2ODR 0 R/W 1 PB1ODR 0 R/W 0 PB0ODR 0 R/W Rev. 1.00 Sep. 19, 2008 Page 603 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.10.6 Pin Functions Port B pins also function as the pins for TPU I/Os and address outputs. The correspondence between the register specification and the pin functions is shown below. • PB7/A15/TIOCB8/TCLKH The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 8 settings (by bits MD3 to MD0 in TMDR_8, bits IOB3 to IOB0 in TIOR_8, and bits CCLR1 and CCLR0 in TCR_8), bits TPSC2 to TPSC0 in TCR_6 and TCR_11, and bit PB7DDR. Operating mode 1, 2 4, 7 (EXPE = 1) TPU channel 8 settings PB7DDR 0 1 0 1 A15 output PB7 input A15 output TIOCB8 output PB7 input PB7 output Pin function 7 (EXPE = 0) (1) in table below (2) in table below TIOCB8 input*1 TCLKH input*2 TPU channel 8 settings MD3 to MD0 (2) (1) B'0000, B'01×× (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR1, CCLR0 Other than B'10 B'10 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Other than B'××00 Legend: ×: Don’t care Notes: 1. TIOCB8 input when MD3 to MD0 = B'0000 or B'01×× and IOB3 = 1. 2. TCLKH input when the setting for either TCR_6 or TCR_11 is TPSC2 to TPSC0 = B'111. TCLKH input when phase counting mode is set for channels 8 and 10. Rev. 1.00 Sep. 19, 2008 Page 604 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PB6/A14/TIOCA8 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 8 settings (by bits MD3 to MD0 in TMDR_8, bits IOA3 to IOA0 in TIOR_8, and bits CCLR1 and CCLR0 in TCR_8), and bit PB6DDR. Operating mode 1, 2 4, 7 (EXPE = 1) TPU channel 8 settings PB6DDR 0 1 0 1 A14 output PB6 input A14 output TIOCA8 output PB6 input PB6 output Pin function TPU channel 8 settings MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01×× 7 (EXPE = 0) (1) in table below (2) (1) B'001× B'0010 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR1, CCLR0 Output function Output compare output (2) in table below TIOCA8 input* (1) 1 (2) B'0011 Other than B'××00 Other than B'01 PWM*2 mode PWM mode 1 output 2 output B'01 Legend: ×: Don’t care Notes: 1. TIOCA8 input when MD3 to MD0 = B'0000 or B'01×× and IOA3 = 1. 2. TIOCB8 output disabled. Rev. 1.00 Sep. 19, 2008 Page 605 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PB5/A13/TIOCB7/TCLKG The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 7 settings (by bits MD3 to MD0 in TMDR_7, bits IOB3 to IOB0 in TIOR_7, and bits CCLR1 and CCLR0 in TCR_7), bits TPSC2 to TPSC0 in TCR_6, TCR_8, TCR_10, and TCR_11, and bit PB5DDR. Operating mode 1, 2 4, 7 (EXPE = 1) TPU channel 7 settings PB5DDR 0 1 0 1 A13 output PB5 input A13 output TIOCB7 output PB5 input PB5 output Pin function 7 (EXPE = 0) (1) in table below (2) in table below TIOCB7 input*1 TCLKG input* TPU channel 7 settings MD3 to MD0 (2) (1) B'0000, B'01×× (2) (2) B'0010 (1) 2 (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR1, CCLR0 Other than B'10 B'10 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Other than B'××00 Legend: ×: Don’t care Notes: 1. TIOCB7 input when MD3 to MD0 = B'0000 or B'01×× and IOB3 to IOB0 = B'10××. 2. TCLKG input when the setting for either TCR_6 or TCR_8 is TPSC2 to TPSC0 = B'111, or when the setting for either TCR_10 or TCR_11 is TPSC2 to TPSC0 = B'101. TCLKG input when phase counting mode is set for channels 8 and 10. Rev. 1.00 Sep. 19, 2008 Page 606 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PB4/A12/TIOCA7 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 7 settings (by bits MD3 to MD0 in TMDR_7, bits IOA3 to IOA0 in TIOR_7, and bits CCLR1 and CCLR0 in TCR_7), and bit PB4DDR. Operating mode 1, 2 4, 7 (EXPE = 1) TPU channel 7 settings PB4DDR 0 1 0 1 A12 output PB4 input A12 output TIOCA7 output PB4 input PB4 output Pin function TPU channel 7 settings MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01×× 7 (EXPE = 0) (1) in table below (2) (1) B'001× B'0010 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR1, CCLR0 Output function Output compare output (2) in table below TIOCA7 input* (1) 1 (2) B'0011 Other than B'××00 Other than B'01 PWM*2 mode PWM mode 1 output 2 output B'01 Legend: ×: Don’t care Notes: 1. TIOCA7 input when MD3 to MD0 = B'0000 or B'01×× and IOA3 to IOA0 = B'10××. 2. TIOCB7 output disabled. Rev. 1.00 Sep. 19, 2008 Page 607 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PB3/A11/TIOCD6/TCLKF The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOD3 to IOD0 in TIORL_6, and bits CCLR2 to CCLR0 in TCR_6), bits TPSC2 to TPSC0 in TCR_6 to TCR_8, and bit PB3DDR. Operating mode 1, 2 4, 7 (EXPE = 1) TPU channel 6 settings PB3DDR 0 1 0 1 A11 output PB3 input A11 output TIOCD6 output PB3 input PB3 output Pin function 7 (EXPE = 0) (1) in table below (2) in table below TIOCD6 input*1 2 TCLKF input* TPU channel 6 settings (2) MD3 to MD0 (1) B'0000 (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR2 to CCLR0 Other than B'110 B'110 Output function Output compare output PWM mode 2 output IOD3 to IOD0 Other than B'××00 Legend: ×: Don’t care Notes: 1. TIOCD6 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10××. 2. TCLKF input when the setting for any of TCR_6 to TCR_8 is TPSC2 to TPSC0 = B'101. TCLKF input when phase counting mode is set for channels 7 and 11. Rev. 1.00 Sep. 19, 2008 Page 608 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PB2/A10/TIOCC6/TCLKE The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOC3 to IOC0 in TIORL_6, and bits CCLR2 to CCLR0 in TCR_6), bits TPSC2 to TPSC0 in TCR_6 to TCR_11, and bit PB2DDR. Operating mode 1, 2 4, 7 (EXPE = 1) TPU channel 6 settings PB2DDR 0 1 0 1 A10 output PB2 input A10 output TIOCC6 output PB2 input PB2 output Pin function 7 (EXPE = 0) (1) in table below (2) in table below TIOCC6 input*1 2 TCLKE input* TPU channel 6 settings (2) MD3 to MD0 IOC3 to IOC0 (1) B'0000 (2) (1) B'001× B'0010 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR2 to CCLR0 Output function Output compare output (1) (2) B'0011 Other than B'××00 Other than B'101 PWM*3 mode PWM mode 1 output 2 output B'101 Legend: ×: Don’t care Notes: 1. TIOCC6 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10××. 2. TCLKE input when the setting for any of TCR_6 to TCR_11 is TPSC2 to TPSC0 = B'100. TCLKE input when phase counting mode is set for channels 7 and 11. 3. TIOCD6 output disabled. Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_6. Rev. 1.00 Sep. 19, 2008 Page 609 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PB1/A9/TIOCB6 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOB3 to IOB0 in TIORH_6, and bits CCLR2 to CCLR0 in TCR_6), and bit PB1DDR. Operating mode 1, 2 4, 7 (EXPE = 1) TPU channel 6 settings PB1DDR 0 1 0 1 A9 output PB1 input A9 output TIOCB6 output PB1 input PB1 output Pin function TPU channel 6 settings (2) MD3 to MD0 (1) B'0000 7 (EXPE = 0) (1) in table below (2) (2) B'0010 (2) in table below TIOCB6 input* (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR2 to CCLR0 Other than B'010 B'010 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Other than B'××00 Legend: ×: Don’t care Note: * TIOCB6 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10××. Rev. 1.00 Sep. 19, 2008 Page 610 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PB0/A8/TIOCA6 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOA3 to IOA0 in TIORH_6, and bits CCLR2 to CCLR0 in TCR_6), and bit PB0DDR. Operating mode 1, 2 4, 7 (EXPE = 1) TPU channel 6 settings PB0DDR 0 1 0 1 A8 output PB0 input A8 output TIOCA6 output PB0 input PB0 output Pin function TPU channel 6 settings (2) MD3 to MD0 IOA3 to IOA0 (1) B'0000 7 (EXPE = 0) (1) in table below (2) (1) B'001× B'0010 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR2 to CCLR0 Output function Output compare output (2) in table below TIOCA6 input* (1) 1 (2) B'0011 Other than B'××00 Other than B'001 PWM*2 mode PWM mode 1 output 2 output B'001 Legend: ×: Don’t care Notes: 1. TIOCA6 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10××. 2. TIOCB6 output disabled. Rev. 1.00 Sep. 19, 2008 Page 611 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.10.7 Port B Input Pull-Up MOS States Port B has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in modes 4 and 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. In modes 4 and 7, when a PBDDR bit is cleared to 0, setting the corresponding PBPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.4 summarizes the input pull-up MOS states. Table 10.4 Input Pull-Up MOS States for Port B Mode Reset Hardware Standby Mode Software Standby Mode In Other Operations 1 or 2 Off Off Off Off On/Off On/Off 4 or 7 Legend: Off: Input pull-up MOS is always off. On/Off: Input pull-up MOS is on when in an input port state 0 and PBPCR = 1; otherwise off. Rev. 1.00 Sep. 19, 2008 Page 612 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.11 Port C Port C is an 8-bit I/O port that also has other functions. Port C has the following registers. • • • • • Port C data direction register (PCDDR) Port C data register (PCDR) Port C register (PORTC) Port C pull-up MOS control register (PCPCR) Port C open drain control register (PCODR) 10.11.1 Port C Data Direction Register (PCDDR) The individual bits of PCDDR specify input or output for the pins of port C. PCDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 PC7DDR 0 W • 6 PC6DDR 0 W 5 PC5DDR 0 W 4 PC4DDR 0 W 3 PC3DDR 0 W 2 PC2DDR 0 W 1 PC1DDR 0 W 0 PC0DDR 0 W Modes 1 and 2 Port C pins are address outputs regardless of the PCDDR settings. • Modes 7 (when EXPE = 1) and 4 Setting a PCDDR bit to 1 makes the corresponding pin an address output, while clearing a PCDDR to 0 makes the corresponding pin an input port. • Mode 7 (when EXPE = 0) Port C is an I/O port, and its pin functions can be switched with PCDDR. Rev. 1.00 Sep. 19, 2008 Page 613 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.11.2 Port C Data Register (PCDR) PCDR stores output data for the port C pins. Bit Bit Name Initial Value R/W Description 7 PC7DR 0 R/W 6 PC6DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 PC5DR 0 R/W 4 PC4DR 0 R/W 3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W 0 PC0DR 0 R/W 10.11.3 Port C Register (PORTC) PORTC shows the pin states of port C. PORTC cannot be modified. Bit Bit Name Initial Value R/W Description 7 PC7 * R 6 PC6 * R 5 PC5 * R If this register is read while a PCDDR bit is set to 1, the corresponding PCDR value is read. If this register is read while a PCDDR bit is cleared to 0, the corresponding pin state is read. 4 PC4 * R 3 PC3 * R 2 PC2 * R 1 PC1 * R 0 PC0 * R Note: * Determined by the states of pins PC7 to PC0. Rev. 1.00 Sep. 19, 2008 Page 614 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.11.4 Port C Pull-Up MOS Control Register (PCPCR) PCPCR controls on/off of the input pull-up MOS for port C. PCPCR is valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description 7 PC7PCR 0 R/W 6 PC6PCR 0 R/W When in a input port state, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. 5 PC5PCR 0 R/W 4 PC4PCR 0 R/W 3 PC3PCR 0 R/W 2 PC2PCR 0 R/W 1 PC1PCR 0 R/W 0 PC0PCR 0 R/W 10.11.5 Port C Open Drain Control Register (PCODR) PCODR specifies the output type of each port C pin. Bit Bit Name Initial Value R/W Description 7 PC7ODR 0 R/W 6 PC6ODR 0 R/W 5 PC5ODR 0 R/W 4 PC4ODR 0 R/W When not specified for address output, setting a PCODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PCODR bit to 0 makes the corresponding pin a CMOS output pin. 3 PC3ODR 0 R/W 2 PC2ODR 0 R/W 1 PC1ODR 0 R/W 0 PC0ODR 0 R/W Rev. 1.00 Sep. 19, 2008 Page 615 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.11.6 Pin Functions Port C pins also function as the pins for TPU I/Os and address outputs. The correspondence between the register specification and the pin functions is shown below. • PC7/A7/TIOCB11 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 11 settings (by bits MD3 to MD0 in TMDR_11, bits IOB3 to IOB0 in TIOR_11, and bits CCLR1 and CCLR0 in TCR_11), and bit PC7DDR. Operating mode 1, 2 4, 7 (EXPE = 1) TPU channel 11 settings PC7DDR 0 1 0 1 A7 output PC7 input A7 output TIOCB11 output PC7 input PC7 output Pin function TPU channel 11 settings (2) MD3 to MD0 (1) B'0000 7 (EXPE = 0) (1) in table below (2) (2) B'0010 (2) in table below TIOCB11 input* (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR1, CCLR0 Other than B'10 B'10 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Other than B'××00 Legend: ×: Don’t care Note: * TIOCB11 input when MD3 to MD0 = B'0000 or B'01×× and IOB3 = 1. Rev. 1.00 Sep. 19, 2008 Page 616 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PC6/A6/TIOCA11 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 11 settings (by bits MD3 to MD0 in TMDR_11, bits IOA3 to IOA0 in TIOR_11, and bits CCLR1 and CCLR0 in TCR_11), and bit PC6DDR. Operating mode 1, 2 4, 7 (EXPE = 1) TPU channel 11 settings PC6DDR 0 1 0 1 A6 output PC6 input A6 output TIOCA11 output PC6 input PC6 output Pin function TPU channel 11 settings MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01×× 7 (EXPE = 0) (1) in table below (2) (2) B'001× B'0010 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR1, CCLR0 Output function Output compare output (2) in table below 1 TIOCA11 input* (1) (2) B'0011 Other than B'××00 Other than B'01 PWM*2 mode PWM mode 1 output 2 output B'01 Legend: ×: Don’t care Notes: 1. TIOCA11 input when MD3 to MD0 = B'0000 or B'01×× and IOA3 = 1. 2. TIOCB11 output disabled. Rev. 1.00 Sep. 19, 2008 Page 617 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PC5/A5/TIOCB10 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 10 settings (by bits MD3 to MD0 in TMDR_10, bits IOB3 to IOB0 in TIOR_10, and bits CCLR1 and CCLR0 in TCR_10), and bit PC5DDR. Operating mode 1, 2 4, 7 (EXPE = 1) TPU channel 10 settings PC5DDR 0 1 0 1 A5 output PC5 input A5 output TIOCB10 output PC5 input PC5 output Pin function TPU channel 10 settings MD3 to MD0 (2) (1) B'0000, B'01×× 7 (EXPE = 0) (1) in table below (2) (2) B'0010 (2) in table below TIOCB10 input* (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR1, CCLR0 Other than B'10 B'10 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Other than B'××00 Legend: ×: Don’t care Note: * TIOCB10 input when MD3 to MD0 = B'0000 or B'01×× and IOB3 to IOB0 = B'10××. Rev. 1.00 Sep. 19, 2008 Page 618 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PC4/A4/TIOCA10 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 10 settings (by bits MD3 to MD0 in TMDR_10, bits IOA3 to IOA0 in TIOR_10, and bits CCLR1 and CCLR0 in TCR_10), and bit PC4DDR. Operating mode 1, 2 4, 7 (EXPE = 1) TPU channel 10 settings PC4DDR 0 1 0 1 A4 output PC4 input A4 output TIOCA10 output PC4 input PC4 output (2) (1) (1) B'001× B'0010 Pin function TPU channel 10 settings MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01×× 7 (EXPE = 0) (1) in table below B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR1, CCLR0 Output function Output compare output (2) in table below 1 TIOCA10 input* (2) B'0011 Other than B'××00 Other than B'01 PWM*2 mode PWM mode 1 output 2 output B'01 Legend: ×: Don’t care Notes: 1. TIOCA10 input when MD3 to MD0 = B'0000 or B'01×× and IOA3 to IOA0 = B'10××. 2. TIOCB10 output disabled. Rev. 1.00 Sep. 19, 2008 Page 619 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PC3/A3/TIOCD9 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOD3 to IOD0 in TIORL_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC3DDR. Operating mode 1, 2 4, 7 (EXPE = 1) TPU channel 9 settings PC3DDR 0 1 0 1 A3 output PC3 input A3 output TIOCD9 output PC3 input PC3 output Pin function TPU channel 9 settings (2) MD3 to MD0 (1) B'0000 7 (EXPE = 0) (1) in table below (2) (2) B'0010 (2) in table below TIOCD9 input* (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR2 to CCLR0 Other than B'110 B'110 Output function Output compare output PWM mode 2 output IOD3 to IOD0 Other than B'××00 Legend: ×: Don’t care Note: * TIOCD9 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10××. Rev. 1.00 Sep. 19, 2008 Page 620 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PC2/A2/TIOCC9 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOC3 to IOC0 in TIORL_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC2DDR. Operating mode 1, 2 4, 7 (EXPE = 1) TPU channel 9 settings PC2DDR 0 1 0 1 A2 output PC2 input A2 output TIOCC9 output PC2 input PC2 output Pin function TPU channel 9 settings (2) MD3 to MD0 IOC3 to IOC0 (1) B'0000 7 (EXPE = 0) (1) in table below (2) (1) B'001× B'0010 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR2 to CCLR0 Output function Output compare output (2) in table below TIOCC9 input* (1) 1 (2) B'0011 Other than B'××00 Other than B'101 PWM*2 mode PWM mode 1 output 2 output B'101 Legend: ×: Don’t care Notes: 1. TIOCC9 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10××. 2. TIOCD9 output disabled. Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_9. Rev. 1.00 Sep. 19, 2008 Page 621 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PC1/A1/TIOCB9 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOB3 to IOB0 in TIORH_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC1DDR. Operating mode 1, 2 4, 7 (EXPE = 1) TPU channel 9 settings PC1DDR 0 1 0 1 A1 output PC1 input A1 output TIOCB9 output PC1 input PC1 output Pin function TPU channel 9 settings (2) MD3 to MD0 (1) B'0000 7 (EXPE = 0) (1) in table below (2) (2) B'0010 (2) in table below TIOCB9 input* (1) (2) B'0011 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR2 to CCLR0 Other than B'010 B'010 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Other than B'××00 Legend: ×: Don’t care Note: * TIOCB9 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10××. Rev. 1.00 Sep. 19, 2008 Page 622 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PC0/A0/TIOCA9 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOA3 to IOA0 in TIORH_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC0DDR. Operating mode 1, 2 4, 7 (EXPE = 1) TPU channel 9 settings PC0DDR 0 1 0 1 A0 output PC0 input A0 output TIOCA9 output PC0 input PC0 output Pin function TPU channel 9 settings (2) MD3 to MD0 IOA3 to IOA0 (1) B'0000 7 (EXPE = 0) (1) in table below (2) (1) B'001× B'0010 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 CCLR2 to CCLR0 Output function Output compare output (2) in table below TIOCA9 input* (1) 1 (2) B'0011 Other than B'××00 Other than B'001 PWM*2 mode PWM mode 1 output 2 output B'001 Legend: ×: Don’t care Notes: 1. TIOCA9 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10××. 2. TIOCB9 output disabled. Rev. 1.00 Sep. 19, 2008 Page 623 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.11.7 Port C Input Pull-Up MOS States Port C has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in modes 4 and 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. In modes 4 and 7, when a PCDDR bit is cleared to 0, setting the corresponding PCPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.5 summarizes the input pull-up MOS states. Table 10.5 Input Pull-Up MOS States for Port C Mode Reset Hardware Standby Mode Software Standby Mode In Other Operations 1 or 2 Off Off Off Off On/Off On/Off 4 or 7 Legend: Off: Input pull-up MOS is always off. On/Off: Input pull-up MOS is on when in an input port state and PCPCR = 1; otherwise off. Rev. 1.00 Sep. 19, 2008 Page 624 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.12 Port D Port D is an 8-bit I/O port that also has other functions. Port D has the following registers. • • • • • Port D data direction register (PDDDR) Port D data register (PDDR) Port D register (PORTD) Port D pull-up MOS control register (PDPCR) Port D open drain control register (PDODR) 10.12.1 Port D Data Direction Register (PDDDR) The individual bits of PDDDR specify input or output for the pins of port D. PDDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 PD7DDR 0 W • 6 PD6DDR 0 W 5 PD5DDR 0 W 4 PD4DDR 0 W 3 PD3DDR 0 W 2 PD2DDR 0 W 1 PD1DDR 0 W 0 PD0DDR 0 W Modes 7 (when EXPE = 1), 1, 2, and 4 Port D is automatically designated for data input/output. • Mode 7 (when EXPE = 0) Port D is an I/O port, and its pin functions can be switched with PDDDR. Rev. 1.00 Sep. 19, 2008 Page 625 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.12.2 Port D Data Register (PDDR) PDDR stores output data for the port D pins. Bit Bit Name Initial Value R/W Description 7 PD7DR 0 R/W 6 PD6DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 PD5DR 0 R/W 4 PD4DR 0 R/W 3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W 0 PD0DR 0 R/W 10.12.3 Port D Register (PORTD) PORTD shows the pin states of port D. PORTD cannot be modified. Bit Bit Name Initial Value R/W Description 7 PD7 * R 6 PD6 * R 5 PD5 * R If this register is read while a PDDDR bit is set to 1, the corresponding PDDR value is read. If this register is read while a PDDDR bit is cleared to 0, the corresponding pin state is read. 4 PD4 * R 3 PD3 * R 2 PD2 * R 1 PD1 * R 0 PD0 * R Note: * Determined by the states of pins PD7 to PD0. Rev. 1.00 Sep. 19, 2008 Page 626 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.12.4 Port D Pull-Up MOS Control Register (PDPCR) PDPCR controls on/off of the input pull-up MOS for port D. PDPCR is valid in mode 7. Bit Bit Name Initial Value R/W Description 7 PD7PCR 0 R/W 6 PD6PCR 0 R/W When PDDDR = 0 (input port), setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. 5 PD5PCR 0 R/W 4 PD4PCR 0 R/W 3 PD3PCR 0 R/W 2 PD2PCR 0 R/W 1 PD1PCR 0 R/W 0 PD0PCR 0 R/W 10.12.5 Port D Open Drain Control Register (PDODR) PDODR specifies the output type of each port D pin. Bit Bit Name Initial Value R/W Description 7 PD7ODR 0 R/W 6 PD6ODR 0 R/W 5 PD5ODR 0 R/W 4 PD4ODR 0 R/W When not specified for data output, setting a PDODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PDODR bit to 0 makes the corresponding pin a CMOS output pin. 3 PD3ODR 0 R/W 2 PD2ODR 0 R/W 1 PD1ODR 0 R/W 0 PD0ODR 0 R/W Rev. 1.00 Sep. 19, 2008 Page 627 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.12.6 Pin Functions Port D pins also function as the pins for data I/Os. The correspondence between the register specification and the pin functions is shown below. • PD7/D15, PD6/D14, PD5/D13, PD4/D12, PD3/D11, PD2/D10, PD1/D9, PD0/D8 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, and bit PDnDDR. Operating mode 1, 2, 4 7 EXPE PDnDDR 0 1 Data I/O PDn input PDn output Data I/O Pin function 0 1 Legend: n = 7 to 0 10.12.7 Port D Input Pull-Up MOS States Port D has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in mode 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. In mode 7, when a PDDDR bit is cleared to 0, setting the corresponding PDPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.6 summarizes the input pull-up MOS states. Table 10.6 Input Pull-Up MOS States for Port D Mode Reset Hardware Standby Mode Software Standby Mode In Other Operations 1, 2, or 4 Off Off Off Off On/Off On/Off 7 Legend: Off: Input pull-up MOS is always off. On/Off: Input pull-up MOS is on when PDDDR = 0 and PDPCR = 1; otherwise off. Rev. 1.00 Sep. 19, 2008 Page 628 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.13 Port E Port E is an 8-bit I/O port that also has other functions. Port E has the following registers. • • • • • Port E data direction register (PEDDR) Port E data register (PEDR) Port E register (PORTE) Port E pull-up MOS control register (PEPCR) Port E open drain control register (PEODR) 10.13.1 Port E Data Direction Register (PEDDR) The individual bits of PEDDR specify input or output for the pins of port E. PEDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 PE7DDR 0 W • 6 PE6DDR 0 W 5 PE5DDR 0 W 4 PE4DDR 0 W 3 PE3DDR 0 W 2 PE2DDR 0 W 1 PE1DDR 0 W 0 PE0DDR 0 W Modes 1, 2, and 4 When 8-bit bus mode is selected, port E is an I/O port, and its pin functions can be switched with PEDDR. When 16-bit bus mode is selected, port E is designated for data input/output. For details on 8-bit and 16-bit bus modes, see section 6, Bus Controller (BSC). • Mode 7 (when EXPE = 1) When 8-bit bus mode is selected, port E is an I/O port. Setting a PEDDR bit to 1 makes the corresponding pin an output port, while clearing a PEDDR bit to 0 makes the corresponding pin an input port. When 16-bit bus mode is selected, port E is designated for data input/output. • Mode 7 (when EXPE = 0) Port E is an I/O port, and its pin functions can be switched with PEDDR. Rev. 1.00 Sep. 19, 2008 Page 629 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.13.2 Port E Data Register (PEDR) PEDR stores output data for the port E pins. Bit Bit Name Initial Value R/W Description 7 PE7DR 0 R/W 6 PE6DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 PE5DR 0 R/W 4 PE4DR 0 R/W 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W 0 PE0DR 0 R/W 10.13.3 Port E Register (PORTE) PORTE shows the pin states of port E. PORTE cannot be modified. Bit Bit Name Initial Value R/W Description 7 PE7 * R 6 PE6 * R 5 PE5 * R If this register is read while a PEDDR bit is set to 1, the corresponding PEDR value is read. If this register is read while a PEDDR bit is cleared to 0, the corresponding pin state is read. 4 PE4 * R 3 PE3 * R 2 PE2 * R 1 PE1 * R 0 PE0 * R Note: * Determined by the states of pins PE7 to PE0. Rev. 1.00 Sep. 19, 2008 Page 630 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.13.4 Port E Pull-Up MOS Control Register (PEPCR) PEPCR controls on/off of the input pull-up MOS for port E. PEPCR is valid in 8-bit bus mode. Bit Bit Name Initial Value R/W Description 7 PE7PCR 0 R/W 6 PE6PCR 0 R/W When PEDDR = 0 (input port), setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. 5 PE5PCR 0 R/W 4 PE4PCR 0 R/W 3 PE3PCR 0 R/W 2 PE2PCR 0 R/W 1 PE1PCR 0 R/W 0 PE0PCR 0 R/W 10.13.5 Port E Open Drain Control Register (PEODR) PEODR specifies the output type of each port E pin. Bit Bit Name Initial Value R/W Description 7 PE7ODR 0 R/W 6 PE6ODR 0 R/W 5 PE5ODR 0 R/W 4 PE4ODR 0 R/W When not specified for data output, setting a PEODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PEODR bit to 0 makes the corresponding pin a CMOS output pin. 3 PE3ODR 0 R/W 2 PE2ODR 0 R/W 1 PE1ODR 0 R/W 0 PE0ODR 0 R/W Rev. 1.00 Sep. 19, 2008 Page 631 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.13.6 Pin Functions Port E pins also function as the pins for data I/Os. The correspondence between the register specification and the pin functions is shown below. • PE7/D7, PE6/D6, PE5/D5, PE4/D4, PE3/D3, PE2/D2, PE1/D1, PE0/D0 The pin function is switched as shown below according to the combination of the operating mode, bus mode, bit EXPE, and bit PEnDDR. Operating mode Bus mode 1, 2, 4 All areas are 8-bit space At least one area is 16-bit space All areas are 8-bit space At least one area is 16-bit space 0 1 1 EXPE 0 1 0 1 0 1 PEn input PEn output Data I/O PEn input PEn output PEn input PEn output Data I/O PEnDDR Pin function 7 Legend: n = 7 to 0 10.13.7 Port E Input Pull-Up MOS States Port E has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in 8-bit bus mode. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. In 8-bit bus mode, when a PEDDR bit is cleared to 0, setting the corresponding PEPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.7 summarizes the input pull-up MOS states. Table 10.7 Input Pull-Up MOS States for Port E Mode 1, 2, or 4 8-bit bus Reset Hardware Standby Mode Software Standby Mode In Other Operations Off Off On/Off On/Off Off Off 16-bit bus Legend: Off: Input pull-up MOS is always off. On/Off: Input pull-up MOS is on when PEDDR = 0 and PEPCR = 1; otherwise off. Rev. 1.00 Sep. 19, 2008 Page 632 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.14 Port F Port F is an 8-bit I/O port that also has other functions. Port F has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. • • • • • • • • Port F data direction register (PFDDR) Port F data register (PFDR) Port F register (PORTF) Port function control register 0 (PFCR0) Port function control register 2 (PFCR2) Port function control register 4 (PFCR4) Port function control register 5 (PFCR5) Port F open drain control register (PFODR) Rev. 1.00 Sep. 19, 2008 Page 633 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.14.1 Port F Data Direction Register (PFDDR) The individual bits of PFDDR specify input or output for the pins of port F. PFDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 PF7DDR 1/0* W • 6 PF6DDR 0 W 5 PF5DDR 0 W 4 PF4DDR 0 W 3 PF3DDR 0 W 2 PF2DDR 0 W 1 PF1DDR 0 W 0 PF0DDR 0 W Modes 7 (when EXPE = 1), 1, 2, and 4 Pin PF7 functions as the φ output pin when the corresponding PFDDR bit is set to 1, and as an input port when the bit is cleared to 0. Pin PF6 functions as the AS output pin when the ASOE bit is set to 1. When the ASOE bit is cleared to 0, pin PF6 is an I/O port and its function can be switched with PF6DDR. Pins PF5 and PF4 are automatically designated as bus control outputs (RD and HWR). Pin PF3 functions as the LWR output pin when the LWROE bit is set to 1. When the LWROE bit is cleared to 0, pin PF3 is an I/O port and its function can be switched with PF3DDR. Pins PF2 to PF0 function as bus control input/output pins (LCAS, UCAS, and WAIT) when the appropriate bus controller settings are made. Otherwise, these pins are output ports when the corresponding PFDDR bits are set to 1 and are input ports when the bits are cleared to 0. • Mode 7 (when EXPE = 0) Pin PF7 functions as the φ output pin when the corresponding PFDDR bit is set to 1, and as an input port when the bit is cleared to 0. Pins PF6 to PF0 are I/O ports, and their functions can be switched with PFDDR. Rev. 1.00 Sep. 19, 2008 Page 634 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.14.2 Port F Data Register (PFDR) PFDR stores output data for the port F pins. Bit Bit Name Initial Value R/W Description 7 PF7DR 0 R/W 6 PF6DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 PF5DR 0 R/W 4 PF4DR 0 R/W 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W 0 PF0DR 0 R/W 10.14.3 Port F Register (PORTF) PORTF shows the pin states of port F. PORTF cannot be modified. Bit Bit Name Initial Value R/W Description 7 PF7 * R 6 PF6 * R 5 PF5 * R If this register is read while a PFDDR bit is set to 1, the corresponding PFDR value is read. If this register is read while a PFDDR bit is cleared to 0, the corresponding pin state is read. 4 PF4 * R 3 PF3 * R 2 PF2 * R 1 PF1 * R 0 PF0 * R Note: * Determined by the states of pins PF7 to PF0. Rev. 1.00 Sep. 19, 2008 Page 635 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.14.4 Port F Open Drain Control Register (PFODR) PFODR specifies the output type of each port F pin. Bit Bit Name Initial Value R/W Description 7 PF7ODR 0 R/W 6 PF6ODR 0 R/W 5 PF5ODR 0 R/W 4 PF4ODR 0 R/W 3 PF3ODR 0 R/W When not specified for φ, AS, AH, RD, HWR, LWR, LCAS, UCAS, DQML, DQMU, CS5, CS6, or OE-A output, setting a PFODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PFODR bit to 0 makes the corresponding pin a CMOS output pin. 2 PF2ODR 0 R/W 1 PF1ODR 0 R/W 0 PF0ODR 0 R/W 10.14.5 Pin Functions Port F pins also function as the pins for SSU I/Os, A/D converter inputs, interrupt inputs, bus control signal I/Os, and system clock outputs. The correspondence between the register specification and the pin functions is shown below. • PF7/φ The pin function is switched as shown below according to bit PF7DDR. Operating mode PF7DDR Pin function 1, 2, 4, 7 0 1 PF7 input φ output Rev. 1.00 Sep. 19, 2008 Page 636 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PF6/AS/AH The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit MPXE in MPXCR of the bus controller, bit ASOE in PFCR2, and bit PF6DDR. Operating mode 1, 2, 4 7 EXPE 0 1 ASOE 1 PF6DDR 0 1 0 1 0 1 AS/AH* output PF6 input PF6 output PF6 input PF6 output AS/AH* output PF6 input PF6 output Pin function Note: * 0 1 0 AH output when MPXE = 1, and AS output when MPXE = 0. • PF5/RD The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, and bit PF5DDR. Operating mode 1, 2, 4 7 EXPE PF5DDR 0 1 RD output PF5 input PF5 output RD output Pin function 0 1 • PF4/HWR The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, and bit PF4DDR. Operating mode EXPE PF4DDR Pin function 1, 2, 4 7 0 1 0 1 HWR output PF4 input PF4 output HWR output Rev. 1.00 Sep. 19, 2008 Page 637 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PF3/LWR/SSO0-C The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bit LWROE in PFCR2, bits SSOS1 and SSOS0 in PFCR5, and bit PF3DDR. Operating mode 1, 2, 4, 7 (EXPE = 1) LWROE 1 SSU settings PF3DDR 0 1 LWR output PF3 input PF3 output Pin function 7 (EXPE = 0) 0 Can be used as I/O port 0 Input state Output state 0 Can be used as I/O port 0 SSO0-C SSO0-C input*1 output*2 Input state Output state 0 1 PF3 input PF3 SSO0-C SSO0-C output input*1 output*2 Notes: 1. SSO0-C input when SSO0S1 and SSO0S0 = B'10 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'000×1 or B'01×01. 2. SSO0-C output when SSO0S1 and SSO0S0 = B'10 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0011×, B'01×10, or B'10×1×. SSO pin settings SSUMS 0 0 1 BIDE 0 1 0 MSS TE RE Pin state 0 0 1 1 0 1 0 1 1 Input Input 0 1 0 1 1 0 1 0 1 1 0 1 0 Output Output Input Output Input Output Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 638 of 1270 REJ09B0466-0100 0 0 1 1 1 0 0 1 Output Output 1 1 0 1 Output Output Section 10 I/O Ports • PF2/LCAS/DQML/IRQ15-A/SSI0-C (H8S/2426 Group and H8S/2426R Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bits SSI0S1 and SSI0S0 in PFCR5, bits ABW5 to ABW2 in ABWCR, and bit PF2DDR. • Modes 1, 2, 4, and 7 (EXPE = 1) Areas 2 to 5 Any DRAM/ synchronous DRAM space area is 16-bit bus space SSU settings PF2DDR Pin function LCAS output 3 DQML* output All DRAM/synchronous DRAM space areas are 8-bit bus space, or areas 2 to 5 are all normal space Can be used as I/O port 0 PF2 input Input state 1 Output state 0 2 PF2 output SSI0-C input* SSI0-C output*3 IRQ15-A interrupt input* 1 • Mode 7 (EXPE = 0) Areas 2 to 5 SSU settings Can be used as I/O port PF2DDR 0 Pin function PF2 input 1 Input state Output state 0 PF2 output 2 SSI0-C input* SSI0-C output*3 IRQ15-A interrupt input* 1 Notes: 1. IRQ15 input when the ITS15 bit in ITSR is 0. 2. SSI0-C input when SSI0S1 and SSI0S0 = B'10 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'001×1 or B'10××1. 3. SSI0-C output when SSI0S1 and SSI0S0 = B'10 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0001×. Rev. 1.00 Sep. 19, 2008 Page 639 of 1270 REJ09B0466-0100 Section 10 I/O Ports SSI pin settings SSUMS 0 0 1 BIDE 0 1 0 MSS 0 TE 0 RE 1 Pin state 1 1 0 0 1 1 Output Output Input 0 1 1 0 0 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 0 1 1 0 1 Input Input Input Input Input Legend: : Pin is not used by the SSU (can be used as I/O port) • PF2/CS6/LCAS/SSI0-C (H8S/2424 Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS6E in PFCR0, bits SSI0S1 and SSI0S0 in PFCR5, bits ABW5 to ABW2 in ABWCR, and bit PF2DDR. • Modes 1, 2, 4, and 7 (EXPE = 1) Areas 2 to 5 Any DRAM/ synchronous DRAM space area is 16-bit bus space All DRAM/synchronous DRAM space areas are 8-bit bus space, or areas 2 to 5 are all normal space CS6E SSU settings PF2DDR 0 LCAS output PF2 input Pin function Rev. 1.00 Sep. 19, 2008 Page 640 of 1270 REJ09B0466-0100 0 Can be used as I/O port 1 Input state Output state 1 0 0 1 PF2 output SSI0-C input*1 SSI0-C output*2 PF2 input CS6 output Section 10 I/O Ports • Mode 7 (EXPE = 0) Areas 2 to 5 CS6E SSU settings Can be used as I/O port PF2DDR 0 Pin function Input state 1 PF2 input Output state 0 1 PF2 output SSI0-C output*2 SSI0-C input* Notes: 1. SSI0-C input when SSI0S1 and SSI0S0 = B'10 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'001×1 or B'10××1. 2. SSI0-C output when SSI0S1 and SSI0S0 = B'10 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0001×. SSI pin settings SSUMS 0 0 1 BIDE 0 1 0 MSS 0 TE 0 RE 1 Pin state 1 1 0 0 1 1 Output Output Input 0 1 1 0 0 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 0 1 1 0 1 Input Input Input Input Input Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 641 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PF1/UCAS/DQMU/IRQ14-A/SSCK0-C (H8S/2426 Group and H8S/2426R Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of the SSU, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bits SSCK0S1 and SSCK0S0 in PFCR5, and bit PF1DDR. • Modes 1, 2, 4, and 7 (EXPE = 1) Areas 2 to 5 Any of areas 2 to 5 is DRAM/synchronous DRAM space SSU settings PF1DDR 0 UCAS output DQMU*3 output PF1 input Pin function Areas 2 to 5 are all normal space Can be used as I/O port Input state Output state 1 0 PF1 output SSCK0-C input*2 SSCK0-C output*3 IRQ14-A interrupt input* 1 • Mode 7 (EXPE = 0) Areas 2 to 5 SSU settings Can be used as I/O port PF1DDR Pin function 0 Input state 1 PF1 input Output state 0 PF1 output SSCK0-C input* 2 SSCK0-C output*3 IRQ14-A interrupt input*1 Notes: 1. IRQ14 input when the ITS14 bit in ITSR is 0. 2. SSCK0-C input when SSCK0S1 and SSCK0S0 = B'10 in PFCR5, and SSUMS, MSS, and SCKS = B'001 or B'101. 3. SSCK0-C output when SSCK0S1 and SSCK0S0 = B'10 in PFCR5, and SSUMS, MSS, and SCKS = B'×11. SSCK pin settings SSUMS 0 MSS 1 0 1 0 1 SCKS 0 1 0 1 0 1 0 1 Pin state Input Output Input Output Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 642 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PF1/CS5/UCAS/SSCK0-C (H8S/2424 Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of the SSU, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS5E in PFCR0, bits SSCK0S1 and SSCK0S0 in PFCR5, and bit PF1DDR. • Modes 2, 4, and 7 (EXPE = 1) Areas 2 to 5 Any of areas 2 to 5 is DRAM space CS5E SSU settings 0 Can be used as I/O port 1 Input state Output state 0 1 0 0 1 UCAS output PF1 input PF1 output SSCK0-C 1 input* SSCK0-C output*2 PF1 input CS5 output PF1DDR Pin function Areas 2 to 5 are all normal space • Mode 7 (EXPE = 0) Areas 2 to 5 CS5E SSU settings Can be used as I/O port PF1DDR Pin function 0 Input state 1 PF1 input Output state 0 PF1 output 1 SSCK0-C output*2 SSCK0-C input* Notes: 1. SSCK0-C input when SSCK0S1 and SSCK0S0 = B'10 in PFCR5, and SSUMS, MSS, and SCKS = B'001 or B'101. 2. SSCK0-C output when SSCK0S1 and SSCK0S0 = B'10 in PFCR5, and SSUMS, MSS, and SCKS = B'×11. SSCK pin settings SSUMS 0 MSS 1 0 1 0 1 SCKS 0 1 0 1 0 1 0 1 Pin state Input Output Input Output Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 643 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PF0/WAIT-A/ADTRG0-B/SCS0-C (H8S/2426 Group and H8S/2426R Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit WAITE in BCR of the bus controller, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of the SSU, bits TRGS1, TRGS0, and EXTRGS in ADCR_0 of the ADC, bits ADTRG0S and WAITS in PFCR4, bits SCS0S1 and SCS0S0 in PFCR5, and bit PF0DDR. • Modes 1, 2, 4, and 7 (EXPE = 1) WAITE SSU settings PF0DDR Pin function 0 Can be used as I/O port Input state Output state 1 0 PF0 output SCS0-C input* 0 PF0 input 1 3 SCS0-C output* 4 ADTRG0-B input* WAIT-A input*2 1 • Mode 7 (EXPE = 0) WAITE SSU settings PF0DDR Pin function Can be used as I/O port 0 PF0 input Input state 1 0 PF0 output SCS0-C input* Output state 3 SCS0-C output*4 ADTRG0-B input*1 Notes: 1. ADTRG0-B input when the ADTRG0S bit in PFCR4 is 1, TRGS1 = TRGS0 = 0, and EXTRGS = 1 2. WAIT-A input when the WAITS bit in PFCR4 is 0. 3. SCSO-C input when SCS0S1 and SCS0S0 = B'10 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'00××, B'0101, or B'0110. 4. SCSO-C output when SCS0S1 and SCS0S0 = B'10 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'011×. Rev. 1.00 Sep. 19, 2008 Page 644 of 1270 REJ09B0466-0100 Section 10 I/O Ports SCS pin settings SSUMS 0 1 × MSS 0 CSS1 × CSS0 × 0 1 0 1 × Input Input Automatic I/O Output Pin state 1 0 × 1 Legend: ×: Don’t care : Pin is not used by the SSU (can be used as I/O port) • PF0/WAIT-A/ADTRG0-B/SCS0-C/OE-A (H8S/2424 Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit WAITE in BCR of the bus controller, bit OEE in DRAMCR, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of the SSU, bits TRGS1, TRGS0, and EXTRGS in ADCR_0 of the ADC, bit OES in PFCR2, bits ADTRG0S and WAITS in PFCR4, bits SCS0S1 and SCS0S0 in PFCR5, and bit PF0DDR. • Modes 1, 2, 4, and 7 (EXPE = 1) OEE 0 RMTS2 to 1 Areas 2 RMTS0 to 5 are DRAM space WAITE SSU settings PF0DDR Pin function 0 1 Can be used as Input Output I/O port state state 0 0 1 PF0 PF0 input output 0 SCS0-C SCS0-C WAIT-A input*2 output*4 input*3 Can be used as Input Output I/O port state state 0 0 1 PF0 PF0 input output 1 SCS0-C SCS0-C WAIT-A input*2 output*4 input*3 OE-A output ADTRG0-B input*1 Rev. 1.00 Sep. 19, 2008 Page 645 of 1270 REJ09B0466-0100 Section 10 I/O Ports • Mode 7 (EXPE = 0) OEE Area 2 WAITE SSU settings PF0DDR Pin function Input state 0 PF0 input Output state 1 0 PF0 output SCS0-C input* SCS0-C output*4 2 ADTRG0-B input*1 Notes: 1. ADTRG0-B input when the ADTRG0S bit in PFCR4 is 1, TRGS1 = TRGS0 = 0, and EXTRGS = 1 2. WAIT-A input when the WAITS bit in PFCR4 is 0. 3. SCSO-C input when SCS0S1 and SCS0S0 = B'10 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'00××, B'0101, or B'0110. 4. SCSO-C output when SCS0S1 and SCS0S0 = B'10 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'011×. SCS pin settings SSUMS 0 1 × MSS 0 CSS1 × CSS0 × 0 1 0 1 × Input Input Automatic I/O Output Pin state 1 0 Legend: ×: Don’t care : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 646 of 1270 REJ09B0466-0100 × 1 Section 10 I/O Ports 10.15 Port G Port G is a 7-bit I/O port that also has other functions. Port G has the following registers. • • • • • • Port G data direction register (PGDDR) Port G data register (PGDR) Port G register (PORTG) Port function control register 0 (PFCR0) Port function control register 4 (PFCR4) Port G open drain control register (PGODR) 10.15.1 Port G Data Direction Register (PGDDR) The individual bits of PGDDR specify input or output for the pins of port G. PGDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 0 Reserved 6 PG6DDR 0 W • 5 PG5DDR 0 W 4 PG4DDR 0 W 3 PG3DDR 0 W 2 PG2DDR 0 W 1 PG1DDR 0 W 0 PG0DDR 1/0* W Modes 7 (when EXPE = 1), 1, 2, and 4 Pins PG6 to PG4 function as bus control input/output pins (BREQO, BACK, and BREQ) when the appropriate bus controller settings are made. Otherwise, these pins are I/O ports, and their functions can be switched with PGDDR. When the CS output enable bits (CS3E to CS0E) are set to 1, pins PG3 to PG0 function as CS output pins when the corresponding PGDDR bit is set to 1, and as input ports when the bit is cleared to 0. When the CS output enable bits (CS3E to CS0E) are cleared to 0, pins PG3 to PG0 are I/O ports, and their functions can be switched with PGDDR. • Mode 7 (when EXPE = 0) Pins PG6 to PG0 are I/O ports, and their functions can be switched with PGDDR. Note: * PG0DDR is initialized to 1 in modes 1 and 2, and to 0 in modes 4 and 7. Rev. 1.00 Sep. 19, 2008 Page 647 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.15.2 Port G Data Register (PGDR) PGDR stores output data for the port G pins. Bit Bit Name Initial Value R/W Description 7 0 Reserved This bit is always read as 0, and cannot be modified. 6 PG6DR 0 R/W 5 PG5DR 0 R/W 4 PG4DR 0 R/W 3 PG3DR 0 R/W 2 PG2DR 0 R/W 1 PG1DR 0 R/W 0 PG0DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 10.15.3 Port G Register (PORTG) PORTG shows the pin states of port G. PORTG cannot be modified. Bit Bit Name Initial Value R/W Description 7 Undefined Reserved If this bit is read, it will return an undefined value. 6 PG6 * R 5 PG5 * R 4 PG4 * R 3 PG3 * R 2 PG2 * R 1 PG1 * R 0 PG0 * R Note: * If this register is read while a PGDDR bit is set to 1, the corresponding PGDR value is read. If this register is read while a PGDDR bit is cleared to 0, the corresponding pin state is read. Determined by the states of pins PG6 to PG0. Rev. 1.00 Sep. 19, 2008 Page 648 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.15.4 Port G Open Drain Control Register (PGODR) PGODR specifies the output type of each port G pin. Bit Bit Name Initial Value R/W Description 7 0 Reserved This bit is always read as 0. Only the initial value should be written to this bit. 6 PG6ODR 0 R/W 5 PG5ODR 0 R/W 4 PG4ODR 0 R/W 3 PG3ODR 0 R/W 2 PG2ODR 0 R/W 1 PG1ODR 0 R/W 0 PG0ODR 0 R/W When not specified for BACK-A, BREQO-A, CS0, CS1, CS2, CS3, CS4, RAS2, RAS3, RAS, or CAS output, setting a PGODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PGODR bit to 0 makes the corresponding pin a CMOS output pin. Rev. 1.00 Sep. 19, 2008 Page 649 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.15.5 Pin Functions Port G pins also function as the pins for JTAG inputs and bus control signal I/Os. The correspondence between the register specification and the pin functions is shown below. • PG6/BREQ-A/TDI*1 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bit BREQS in PFCR4, and bit PG6DDR. Operating mode 1, 2, 4 EXPE BRLE BREQS PG6DDR Pin function 7 BRLE = 0 or BRLE = 1 and BREQS = 1 BRLE = 1 and BREQS = 0 0 1 BRLE = 0 or BRLE = 1 and BREQS = 1 BRLE = 1 and BREQS = 0 0 1 0 1 0 1 PG6 input PG6 output BREQ-A input PG6 input PG6 output PG6 input PG6 output BREQ-A input TDI input*2 Notes: 1. Supported only in the 145-pin package. 2. TDI input when BSCANE pin = 1 in the 145-pin package. Rev. 1.00 Sep. 19, 2008 Page 650 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PG5/BACK-A/TMS*1 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bit BACKS in PFCR4, and bit PG5DDR. Operating mode 1, 2, 4 EXPE BRLE BACKS PG5DDR Pin function 7 BRLE = 0 or BRLE = 1 and BACKS = 1 BRLE = 1 and BACKS = 0 0 1 BRLE = 0 or BRLE = 1 and BACKS = 1 BRLE = 1 and BACKS = 0 0 1 0 1 0 1 PG5 input PG5 output BACK-A output PG5 input PG5 output PG5 input PG5 output BACK-A output TMS input* 2 Notes: 1. Supported only in the 145-pin package. 2. TMS input when BSCANE pin = 1 in the 145-pin package. • PG4/BREQO-A/CS4*1/TCK*2 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bit BREQOE, bit BREQOS in PFCR4, and bit PG4DDR. • Modes 1, 2, 4, and 7 (EXPE = 1) BRLE 0 BREQOE BREQOS CS4E PG4DDR Pin function 0 1 BREQOE = 0 or BREQOE = 1 and BREQOS = 1 1 0 BREQO = 1 and BREQOS = 0 1 0 1 0 1 PG4 input PG4 output CS4 output*1 PG4 input PG4 output CS4 output*1 BREQO-A output 3 TCK input* Rev. 1.00 Sep. 19, 2008 Page 651 of 1270 REJ09B0466-0100 Section 10 I/O Ports • Mode 7 (EXPE = 0) BRLE BREQOE BREQOS CS4E 0 0 1 PG4 input PG4 output CS4 output*1 PG4DDR Pin function 1 TCK input*3 Notes: 1. Not supported in the H8S/2426 Group and H8S/2426R Group. 2. Supported only in the 145-pin package. 3. TCK input when BSCANE pin = 1 in the 145-pin package. • PG3/CS3/RAS3/CAS* The pin function is switched as shown below according to the combination of the operating mode, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS3E in PFCR0, and bit PG3DDR. Operating 1, 2, 4 7 mode EXPE CS3E 0 RMTS2 to 0 1 Area 3 is in RMTS0 normal space Area 3 Areas 2 to 5 is in 1 0 1 Area 3 is in Area 3 Areas 2 to 5 are in normal DRAM synchronous space space DRAM* is in space space PG3DDR 0 1 0 1 Pin PG3 PG3 PG3 CS3 function input output input output Note: * DRAM* space 0 1 0 1 0 1 PG3 PG3 PG3 PG3 CS3 RAS3 CAS* PG3 RAS3 CAS* output output input output input output input output output output Not supported in the H8S/2426 Group and H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 652 of 1270 REJ09B0466-0100 are in DRAM synchronous Section 10 I/O Ports • PG2/CS2/RAS2/RAS* The pin function is switched as shown below according to the combination of the operating mode, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS2E in PFCR0, and bit PG2DDR. Operating 1, 2, 4 7 mode EXPE CS2E 0 RMTS2 0 1 Area 2 is in to normal RMTS0 space Area 2 Areas 2 to 5 is in 1 0 1 Area 2 is in Area 2 Areas 2 to 5 are in normal DRAM synchronous space is in space are in DRAM synchronous DRAM* space DRAM* space 0 1 0 1 Pin PG2 PG2 PG2 CS2 RAS2 function input output input output output PG2DDR Note: * space 0 1 0 1 0 1 RAS* PG2 PG2 PG2 PG2 PG2 CS2 RAS2 RAS* output input output input output input output output output Not supported in the H8S/2426 Group and H8S/2424 Group. • PG1/CS1, PG0/CS0 The pin function is switched as shown below according to the combination of the operating mode, bit CSnE in PFCR0, and bit PGnDDR. Operating mode 1, 2, 4 EXPE CSnE PGnDDR Pin function 7 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 PGn input PGn output PGn input CSn output PGn input PGn output PGn input PGn output PGn input CSn output Legend: n = 1 or 0 Rev. 1.00 Sep. 19, 2008 Page 653 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.16 Port H Note: Port H is not supported in the H8S/2424 Group. Port H is a 4-bit I/O port that also has other functions. Port H has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. • • • • • • Port H data direction register (PHDDR) Port H data register (PHDR) Port H register (PORTH) Port function control register 0 (PFCR0) Port function control register 2 (PFCR2) Port H open drain control register (PHODR) 10.16.1 Port H Data Direction Register (PHDDR) The individual bits of PHDDR specify input or output for the pins of port H. PHDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 to 4 All 0 Reserved 3 PH3DDR 0 W • 2 PH2DDR 0 W 1 PH1DDR 0 W 0 PH0DDR 0 W Modes 7 (when EXPE = 1), 1, 2, and 4 When the OE output enable bit (OEE) and OE output select bit (OES) are set to 1, pin PH3 functions as the OE output pin. Otherwise, when bit CS7E is set to 1, pin PH3 functions as the CS7 output pin when bit PH3DDR is set to 1, and as an input port when the bit is cleared to 0. When bit CS7E is cleared to 0, pin PH3 is an I/O port, and its function can be switched with bit PH3DDR. When areas 2 to 5 are specified as continuous SDRAM space*, OE output is CKE output. When bit CS6E is set to 1, setting bit PH2DDR to 1 makes pin PH2 function as the CS6 output pin, and clearing the bit to 0 makes the pin function as an I/O port. When bit CS6E is cleared to 0, pin PH2 is an I/O port, and its function can be switched with bit PH2DDR. Rev. 1.00 Sep. 19, 2008 Page 654 of 1270 REJ09B0466-0100 Section 10 I/O Ports Bit Bit Name Initial Value R/W 0 PH0DDR 0 W Description Pin PH1 functions as the SDRAMφ* output pin when the SDPSTP bit is 0 in a product supporting the SDRAM interface. In a product not supporting the SDRAM interface or when the SDPSTP bit is 1, if bit CS5E is set to 1 while area 5 is specified as normal space, pin PH1 functions as the CS5 output pin when bit PH1DDR is set to 1, and functions as an I/O port when the bit is cleared to 0. When bit CS5E is cleared to 0, pin PH1 is an I/O port, and its function can be switched with bit PH1DDR. When area 5 is specified as DRAM space and bit CS5E is set to 1, pin PH1 functions as the RAS5 output pin and as an I/O port when the bit is cleared to 0. Pin PH0 functions as the CS4 output pin when area 4 is specified as normal space and bit PH0DDR is set to 1. If bit PH0DDR is cleared to 0, pin PH0 functions as an I/O port. When bit CS4E is cleared to 0, pin PH0 is an I/O port, and its function can be switched with bit PH0DDR. When area 4 is specified as DRAM space and bit CS4E is set to 1, pin PH0 functions as the RAS4 output pin and as an I/O port when the bit is cleared to 0. When areas 2 to 5 are specified as continuous SDRAM space*, pin PH0 functions as the WE output pin when bit CS4E is set to 1, and as an I/O port when the bit is cleared to 0. • Mode 7 (when EXPE = 0) Pins PH3 to PH0 are I/O ports, and their functions can be switched with PHDDR. Pin PH1 functions as the SDRAMφ output pin when the SDPSTP bit is 0 in a product supporting the SDRAM interface. In a product not supporting the SDRAM interface or when the SDPSTP bit is 1, pin PH1 is an I/O port and its function can be switched with PHDDR. Note: * Not supported in the H8S/2426 Group. Rev. 1.00 Sep. 19, 2008 Page 655 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.16.2 Port H Data Register (PHDR) PHDR stores output data for the port H pins. Bit Bit Name Initial Value R/W Description 7 to 4 All 0 Reserved These bits are always read as 0 and cannot be modified. 3 PH3DR 0 R/W 2 PH2DR 0 R/W 1 PH1DR 0 R/W 0 PH0DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 10.16.3 Port H Register (PORTH) PORTH shows the pin states of port H. PORTH cannot be modified. Bit Bit Name Initial Value R/W Description 7 to 4 Undefined Reserved If these bits are read, they will return an undefined value. 3 PH3 * R 2 PH2 * R 1 PH1 * R 0 PH0 * R Note: * If this register is read while a PHDDR bit is set to 1, the corresponding PHDR value is read. If this register is read while a PHDDR bit is cleared to 0, the corresponding pin state is read. Determined by the states of pins PH3 to PH0. Rev. 1.00 Sep. 19, 2008 Page 656 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.16.4 Port H Open Drain Control Register (PHODR) PHODR specifies the output type of each port H pin. Bit Bit Name 7 to 4 Initial Value R/W Description All 0 Reserved These bits are always read as 0. Only the initial values should be written to these bits. 3 PH3ODR 0 R/W 2 PH2ODR 0 R/W 1 PH1ODR 0 R/W 0 PH0ODR 0 R/W Note: * When not specified for CS4, CS5, CS6, CS7, OEA, CKE-A, RAS4, RAS5, WE, or SDRAMφ* output, setting a PHODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PHODR bit to 0 makes the corresponding pin a CMOS output pin. Not supported in the H8S/2426 Group. Rev. 1.00 Sep. 19, 2008 Page 657 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.16.5 Pin Functions Port H pins also function as bus control signal I/Os and interrupt inputs. The correspondence between the register specification and the pin functions is shown below. • PH3/CS7/OE-A/CKE-A/IRQ7-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit OEE in DRAMCR of the bus controller, bit OES in PFCR2, bit CS7E in PFCR0, and bit PH3DDR. • Modes 1, 2, 4, and 7 (EXPE = 1) OEE 0 OES 0 0 1 RMTS2 to RMTS0 Areas 2 to Areas 2 to 5 are 5 are synDRAM chronous space DRAM 3 space* 0 1 0 1 0 1 0 1 PH3 input PH3 output PH3 input CS7 output PH3 input PH3 output PH3 input CS7 output OE-A output*2 CKE-A*3 output*2 CS7E PH3DDR Pin function 1 0 1 0 1 IRQ7-B input*1 • Mode 7 (EXPE = 0) OEE OES RMTS2 to RMTS0 CS7E PH3DDR Pin function 0 1 PH3 input PH3 output IRQ7-B input* Notes: 1. IRQ7-B input when the ITS7 bit in ITSR is 1. 2. OE-A/CKE-A output when the OES bit in PFCR2 is 1. 3. Not supported in the H8S/2426 Group. Rev. 1.00 Sep. 19, 2008 Page 658 of 1270 REJ09B0466-0100 1 Section 10 I/O Ports • PH2/CS6/IRQ6-B The pin function is switched as shown below according to the combination of the operating mode, bit CS6E in PFCR0, and bit PH2DDR. Operating mode 1, 2, 4 7 EXPE CS6E 0 0 PH2DDR Pin function 1 1 0 1 0 1 0 1 0 1 0 1 0 1 PH2 input PH2 output PH2 input CS6 output PH2 input PH2 output PH2 input PH2 output PH2 input CS6 output IRQ6-B interrupt input* Note: * IRQ6-B input when the ITS6 bit in ITSR is 1. • PH1/CS5/RAS5/SDRAMφ* The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit SDPSTP in SCKCR of the clock pulse generator, bit CS5E in PFCR0 and bit PH1DDR. SDPSTP 1 Operating 0 1, 2, 4 7 mode EXPE 0 1 OEE 0 1 0 1 OES 0 0 Area 5 is normal space Area 5 is DRAM Area 5 is normal space Area 5 is DRAM RMTS2 to RMTS0 space CS5E 0 PH1DDR 1 0 1 0 1 0 1 Pin PH1 PH1 PH1 CS5 PH1 PH1 function input output input output input output * 1 0 Note: space 0 1 0 1 0 1 0 1 0 1 0 1 RAS5 PH1 PH1 PH1 PH1 PH1 CS5 PH1 PH1 output input output input output input output input output output RAS5 SDRAMφ output* Not supported in the H8S/2426 Group. Rev. 1.00 Sep. 19, 2008 Page 659 of 1270 REJ09B0466-0100 Section 10 I/O Ports • PH0/CS4/RAS4/WE* The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS4E in PFCR0, and bit PH0DDR. Operating 1, 2, 4 7 mode EXPE CS4E 0 RMTS2 to 0 1 RMTS0 1 0 1 Area 4 is Area 4 Areas 2 Area 4 is Area 4 Areas 2 normal space is to 5 are normal is to 5 are DRAM syn- space DRAM syn- space chronous space chronous DRAM* DRAM* space PH0DDR 0 1 0 1 Pin PH0 PH0 PH0 CS4 function input output input output Note: * RAS4 WE* output output Not supported in the H8S/2426 Group. Rev. 1.00 Sep. 19, 2008 Page 660 of 1270 REJ09B0466-0100 space 0 1 0 1 0 1 PH0 PH0 PH0 PH0 PH0 CS4 RAS4 input output input output input output output WE* output Section 10 I/O Ports 10.17 Port J Note: Port J is not supported in the H8S/2424 Group and in the 145-pin package. Port J is a 3-bit I/O port. Port J has the following registers. • • • • Port J data direction register (PJDDR) Port J data register (PJDR) Port J register (PORT3) Port J open drain control register (PJODR) 10.17.1 Port J Data Direction Register (PJDDR) The individual bits of PJDDR specify input or output for the pins of port J. PJDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 to 2 All 0 Reserved 1 PJ1DDR 0 W 0 PJ0DDR 0 W When a pin function is specified as a general purpose I/O, setting this bit to 1 makes the corresponding pin an output port, while clearing this bit to 0 makes the corresponding pin an input port. 10.17.2 Port J Data Register (PJDR) PJDR stores output data for the port J pins. Bit Bit Name Initial Value R/W Description 7 to 2 All 0 Reserved These bits are always read as 0 and cannot be modified. 1 PJ1DR 0 R/W 0 PJ0DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. Rev. 1.00 Sep. 19, 2008 Page 661 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.17.3 Port J Register (PORTJ) PORTJ shows the pin states of port J. PORTJ cannot be modified. Bit Bit Name Initial Value R/W Description 7 to 3 Undefined Reserved If these bits are read, they will return an undefined value. 2 PJ2 * R The pin state is always read from this register. Bit 2 is reserved for the 145-pin version. 1 PJ1 * R 0 PJ0 * R If this register is read, the PJDR values are read for the bits with the corresponding PJDDR bits set to 1. For the bits with the corresponding PJDDR bits cleared to 0, the pin states are read. Note: * Determined by the state of pins PJ0 to PJ2. 10.17.4 Port J Open Drain Control Register (PJODR) PJODR specifies the output type of each port J pin. Bit Bit Name 7 to 2 Initial Value R/W Description All 0 Reserved These bits are always read as 0. Only the initial values should be written to these bits. 1 PJ1ODR 0 R/W 0 PJ0ODR 0 R/W Rev. 1.00 Sep. 19, 2008 Page 662 of 1270 REJ09B0466-0100 Setting a PJODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PJODR bit to 0 makes the corresponding pin a CMOS output pin. Section 10 I/O Ports 10.17.5 Pin Functions Port J pins function only as I/O ports. The correspondence between the register specification and the pin functions is shown below. • PJ2* The PJ2 pin is an input-only pin. Pin function Note: * PJ2 input Not supported in the 145-pin package. • PJ1, PJ0 The pin function is switched as shown below according to bit PJnDDR. PJnDDR Pin function 0 1 PJn input PJn output Legend: n = 1 or 0 Rev. 1.00 Sep. 19, 2008 Page 663 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.18 Port Function Control Registers The port function controller performs I/O port control. The setting of input or output for each pin should be enabled only after the input or output destination has been selected. The port function controller has the following registers. • • • • • • Port function control register 0 (PFCR0) Port function control register 1 (PFCR1) Port function control register 2 (PFCR2) Port function control register 3 (PFCR3) Port function control register 4 (PFCR4) Port function control register 5 (PFCR5) 10.18.1 Port Function Control Register 0 (PFCR0) PFCR0 switches the functions of the chip select output pins. Bit Bit Name Initial Value R/W Description 7 CS7E 1 R/W CS7 to CS0 Enable 6 CS6E 1 R/W 5 CS5E 1 R/W These bits enable or disable the corresponding CSn output. 4 CS4E 1 R/W 3 CS3E 1 R/W 2 CS2E 1 R/W 1 CS1E 1 R/W 0 CS0E 1 R/W Rev. 1.00 Sep. 19, 2008 Page 664 of 1270 REJ09B0466-0100 0: Pin is designated as I/O port 1: Pin is designated as CSn output pin (n = 7 to 0) Section 10 I/O Ports 10.18.2 Port Function Control Register 1 (PFCR1) PFCR1 enables or disables address output (A23 to A16). Bits 7 to 5 are valid in modes 1 and 2 and all the bits are valid in modes 4 and 7. Bit Bit Name Initial Value R/W 7 A23E 1 R/W Description Address 23 Enable Enables or disables output for address output 23 (A23). 0: DR output when PA7DDR = 1 1: A23 output when PA7DDR = 1 6 A22E 1 R/W Address 22 Enable Enables or disables output for address output 22 (A22). 0: DR output when PA6DDR = 1 1: A22 output when PA6DDR = 1 5 A21E 1 R/W Address 21 Enable Enables or disables output for address output 21 (A21). 0: DR output when PA5DDR = 1 1: A21 output when PA5DDR = 1 4 A20E 1 R/W Address 20 Enable Enables or disables output for address output 20 (A20). 0: DR output when PA4DDR = 1 1: A20 output when PA4DDR = 1 3 A19E 1 R/W Address 19 Enable Enables or disables output for address output 19 (A19). 0: DR output when PA3DDR = 1 1: A19 output when PA3DDR = 1 2 A18E 1 R/W Address 18 Enable Enables or disables output for address output 18 (A18). 0: DR output when PA2DDR = 1 1: A18 output when PA2DDR = 1 Rev. 1.00 Sep. 19, 2008 Page 665 of 1270 REJ09B0466-0100 Section 10 I/O Ports Bit Bit Name Initial Value R/W Description 1 A17E 1 R/W Address 17 Enable Enables or disables output for address output 17 (A17). 0: DR output when PA1DDR = 1 1: A17 output when PA1DDR = 1 0 A16E 1 R/W Address 16 Enable Enables or disables output for address output 16 (A16). 0: DR output when PA0DDR = 1 1: A16 output when PA0DDR = 1 Rev. 1.00 Sep. 19, 2008 Page 666 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.18.3 Port Function Control Register 2 (PFCR2) PFCR2 enables or disables AS output, LWR output, and OE output. Bit Bit Name Initial Value R/W Description 7 to 4 All 0 Reserved These bits are always read as 0 and cannot be modified. 3 ASOE 1 R/W AS Output Enable Enables or disables the AS output pin. 0: PF6 is designated as I/O port 1: PF6 is designated as AS output pin 2 LWROE 1 R/W LWR Output Enable Enables or disables the LWR output pin. 0: PF3 is designated as I/O port 1: PF3 is designated as LWR output pin 1 OES 1 R/W OE Output Select 1 Selects the OE/CKE* output pin port when the OEE bit in DRAMCR is set to 1 (enabling OE/CKE*1 output). 1 0: P35 is designated as OE-B/CKE-B* output pin. 2 1 1: PH3* is designated as OE-A/CKE-A* output pin. 0 0 Reserved This bit is always read as 0. Only the initial value should be written to this bit. Notes: 1. Not supported in the H8S/2424 Group. 2. PH3 becomes PF0 in the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 667 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.18.4 Port Function Control Register 3 (PFCR3) PFCR3 switches the functions of the PPG output pin, TPU input/output pin, and TMR input/output pin. Bit Bit Name Initial Value R/W Description 7 1 Reserved This bit is always read as 1. Only the initial value should be written to this bit. 6 PPGS 0 R/W PPG Pin Select Selects the output pins of PO5 to PO0. 0: P25/PO5-A, P24/PO4-A, P23/PO3-A, P22/PO2A, P21/PO1-A, and P20/PO0-A are selected 1: P85/PO5-B, P52/PO4-B, P83/PO3-B, P51/PO2B, P81/PO1-B, and P50/PO0-B are selected 5 TPUS 0 R/W TPU Pin Select Selects the output pins of TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, and TIOCB4. 0: P25/TIOCB4-A, P24/TIOCA4-A, P23/TIOCD3-A, P22/TIOCC3-A, P21/TIOCB3-A, and P20/TIOCA3-A are selected 1: P85/TIOCB4-B, P52/TIOCA4-B, P83/TIOCD3-B, P51/TIOCC3-B, P81/TIOCB3-B, and P50/TIOCA3-B are selected Rev. 1.00 Sep. 19, 2008 Page 668 of 1270 REJ09B0466-0100 Section 10 I/O Ports Bit Bit Name Initial Value R/W Description 4 TMRS 0 R/W TMR Pin Select Selects the output pins of TMO1 and TMO0 and input pins of TMCI1, TMCI0, TMRI1, and TMRI0. 0: [For H8S/2424] P25/TMO1-A, P24/TMO0-A, P23/TMCI1-A, P22/TMCI0-A, P21/TMRI1-A, and P20/TMRI0-A are selected [For H8S/2426, H8S/2426R] P65/TMO1-A, P64/TMO0-A, P63/TMCI1-A, P62/TMCI0-A, P61/TMRI1-A, and P60/TMRI0-A are selected 1: P85/TMO1-B , P52/TMO0-B, P83/TMCI1-B, P51/TMCI0-B, P81/TMRI1-B, and P50/TMRI0-B are selected 3 to 1 All 0 Reserved These bits are always read as 0. Only the initial values should be written to these bits. 0 1 Reserved This bit is always read as 1. Only the initial value should be written to this bit. 10.18.5 Port Function Control Register 4 (PFCR4) PFCR4 switches the functions of the WAIT input pin, BREQ input pin, BACK output pin, BREQO output pin, TxD4 output pin, RxD4 input pin, and SCK4 input/output pin. Bit Bit Name Initial Value R/W Description 7 WAITS 0 R/W WAIT Pin Select Selects the WAIT input pin. 0: PF0/WAIT-A is selected 1: P25/WAIT-B is selected 6 BREQS 0 R/W BREQ Pin Select Selects the BREQ input pin. 0: PG6/BREQ-A is selected 1: P51/BREQ-B is selected Rev. 1.00 Sep. 19, 2008 Page 669 of 1270 REJ09B0466-0100 Section 10 I/O Ports Bit Bit Name Initial Value R/W Description 5 BACKS 0 R/W BACK Pin Select Selects the BACK output pin. 0: PG5/BACK-A is selected 1: P52/BACK-B is selected 4 BREQOS 0 R/W BREQO Pin Select Selects the BREQO output pin. 0: PG4/BREQO-A is selected 1: P50/BREQO-B is selected 3 0 Reserved This bit is always read as 0. Only the initial value should be written to this bit. 2 TXD4S 0 R/W TxD4 Pin Select Selects the TxD4 output pin. 0: P23/TxD4-A is selected 1: PA1/TxD4-B is selected 1 RXD4S 0 R/W RxD4 Pin Select Selects the RxD4 input pin. 0: P24/RxD4-A is selected 1: PA2/RxD4-B is selected 0 SCK4S 0 R/W SCK4 Pin Select Selects the SCK4 input/output pin. 0: P34/SCK4-A is selected 1: PA3/SCK4-B is selected Rev. 1.00 Sep. 19, 2008 Page 670 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.18.6 Port Function Control Register 5 (PFCR5) PFCR5 switches the functions of the SSU input/output pins. Bit Bit Name Initial Value R/W Description 7 SSO0S1 0 R/W SSO0 Pin Select 6 SSO0S0 0 R/W Selects the SSO0 input/output pin. 00: P14/SSO0-A is selected 01: PA7/SSO0-B is selected 10: PF3/SSO0-C is selected 11: Setting prohibited 5 SSI0S1 0 R/W SSI0 Pin Select 4 SSI0S0 0 R/W Selects the SSI0 input/output pin. 00: P15/SSI0-A is selected 01: PA6/SSI0-B is selected 10: PF2/SSI0-C is selected 11: Setting prohibited 3 SSCK0S1 0 R/W SSCK0 Pin Select 2 SSCK0S0 0 R/W Selects the SSCK0 input/output pin. 00: P16/SSCK0-A is selected 01: PA5/SSCK0-B is selected 10: PF1/SSCK0-C is selected 11: Setting prohibited 1 SCS0S1 0 R/W SCS0 Pin Select 0 SCS0S0 0 R/W Selects the SCS0 input/output pin. 00: P17/SCS0-A is selected 01: PA4/SCS0-B is selected 10: PF0/SCS0-C is selected 11: Setting prohibited Rev. 1.00 Sep. 19, 2008 Page 671 of 1270 REJ09B0466-0100 Section 10 I/O Ports Rev. 1.00 Sep. 19, 2008 Page 672 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Section 11 16-Bit Timer Pulse Unit (TPU) This LSI has two on-chip 16-bit timer pulse units (TPU: unit 0 and unit 1) which each comprises six 16-bit timer channels, resulting in a total of 12 channels. The functions of unit 0 are listed in table 11.1, and the functions of unit 1 are listed in table 11.2. The block diagram of unit 0 is shown in figure 11.1 and the block diagram of unit 1 is shown in figure 11.2. The descriptions in this section refer to unit 0. 11.1 Features • Maximum 16-pulse input/output • Selection of 8 counter input clocks for each channel • The following operations can be set for each channel: Waveform output at compare match Input capture function Counter clear operation Synchronous operations: Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture possible Register simultaneous input/output possible by counter synchronous operation Maximum of 15-phase PWM output possible by combination with synchronous operation • Buffer operation settable for channels 0 and 3 • Phase counting mode settable independently for each of channels 1, 2, 4, and 5 • Cascaded operation • Fast access via internal 16-bit bus • 26 interrupt sources • Automatic transfer of register data • Programmable pulse generator (PPG) output trigger can be generated • A/D converter conversion start trigger can be generated • Module stop mode can be set Rev. 1.00 Sep. 19, 2008 Page 673 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.1 TPU (Unit 0) Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Count clock φ/1 φ/4 φ/16 φ/64 TCLKA TCLKB TCLKC TCLKD φ/1 φ/4 φ/16 φ/64 φ/256 TCLKA TCLKB φ/1 φ/4 φ/16 φ/64 φ/1024 TCLKA TCLKB TCLKC φ/1 φ/4 φ/16 φ/64 φ/256 φ/1024 φ/4096 TCLKA φ/1 φ/4 φ/16 φ/64 φ/1024 TCLKA TCLKC φ/1 φ/4 φ/16 φ/64 φ/256 TCLKA TCLKC TCLKD General registers (TGR) TGRA_0 TGRB_0 TGRA_1 TGRB_1 TGRA_2 TGRB_2 TGRA_3 TGRB_3 TGRA_4 TGRB_4 TGRA_5 TGRB_5 General registers/ buffer registers TGRC_0 TGRD_0 TGRC_3 TGRD_3 I/O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture Compare 0 output match 1 output output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation Rev. 1.00 Sep. 19, 2008 Page 674 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 DTC TGR activation compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture DMAC TGRA_0 activation compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match or input capture TGRA_5 compare match or input capture A/D TGRA_0 converter compare trigger match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match or input capture TGRA_5 compare match or input capture PPG trigger TGRA_0/ TGRB_0 compare match or input capture TGRA_1/ TGRB_1 compare match or input capture TGRA_2/ TGRB_2 compare match or input capture TGRA_3/ TGRB_3 compare match or input capture Interrupt sources 5 sources 4 sources 4 sources 5 sources • • • • • • Compare match or input capture 0A Compare match or input capture 0B Compare match or input capture 0C Compare match or input capture 0D Overflow • • • Compare • match or input capture 1A Compare • match or input capture 1B Overflow • Underflow • Compare • match or input capture 2A Compare • match or input capture 2B Overflow • Underflow • • Compare match or input capture 3A Compare match or input capture 3B Compare match or input capture 3C Compare match or input capture 3D Overflow 4 sources 4 sources • • • • • Compare match or input capture 4A Compare match or input capture 4B Overflow Underflow • • • Compare match or input capture 5A Compare match or input capture 5B Overflow Underflow [Legend] : Possible •: Not possible Rev. 1.00 Sep. 19, 2008 Page 675 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.2 TPU (Unit 1) Functions Channel Channel 6 Channel 7 Channel 8 Channel 9 10 Channel 11 Count clock φ/1 φ/4 φ/16 φ/64 TCLKE TCLKF TCLKG TCLKH φ/1 φ/4 φ/16 φ/64 φ/256 TCLKE TCLKF φ/1 φ/4 φ/16 φ/64 φ/1024 TCLKE TCLKF TCLKG φ/1 φ/4 φ/16 φ/64 φ/256 φ/1024 φ/4096 TCLKE φ/1 φ/4 φ/16 φ/64 φ/1024 TCLKE TCLKG φ/1 φ/4 φ/16 φ/64 φ/256 TCLKE TCLKG TCLKH General registers (TGR) TGRA_6 TGRB_6 TGRA_7 TGRB_7 TGRA_8 TGRB_8 TGRA_9 TGRB_9 TGRA_10 TGRB_10 TGRA_11 TGRB_11 General registers/ buffer registers TGRC_6 TGRD_6 TGRC_9 TGRD_9 I/O pins TIOCA6 TIOCB6 TIOCC6 TIOCD6 TIOCA7 TIOCB7 TIOCA8 TIOCB8 TIOCA9 TIOCB9 TIOCC9 TIOCD9 TIOCA10 TIOCB10 TIOCA11 TIOCB11 Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture Item Compare 0 output match 1 output output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation Rev. 1.00 Sep. 19, 2008 Page 676 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Item Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 DTC TGR activation compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture DMAC activation A/D TGRA_6 converter compare trigger match or input capture TGRA_7 compare match or input capture TGRA_8 compare match or input capture TGRA_9 compare match or input capture TGRA_10 compare match or input capture TGRA_11 compare match or input capture PPG trigger TGRA_6/ TGRB_6 compare match or input capture TGRA_7/ TGRB_7 compare match or input capture TGRA_8/ TGRB_8 compare match or input capture TGRA_9/ TGRB_9 compare match or input capture Interrupt sources 5 sources 4 sources 4 sources 5 sources 4 sources 4 sources • Compare • match or input capture 6A Compare • match or input capture 7A Compare • match or input capture 8A Compare • match or input capture 9A Compare • match or input capture 10A Compare match or input capture 11A • Compare • match or input capture 6B Compare • match or input capture 7B Compare • match or input capture 8B Compare • match or input capture 9B Compare • match or input capture 10B Compare match or input capture 11B • Compare • match or • input capture 6C Overflow • Compare • match or • input capture 9C Overflow • Overflow • Underflow • Overflow Underflow • Compare match or input capture 6D • Compare match or input capture 9D • Overflow • Overflow Underflow • Underflow [Legend] : Possible : Not possible Rev. 1.00 Sep. 19, 2008 Page 677 of 1270 REJ09B0466-0100 TGRD TGRB TGRC TGRB Interrupt request signals Channel 3: TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4: TGI4A TGI4B TCI4V TCI4U Channel 5: TGI5A TGI5B TCI5V TCI5U Internal data bus A/D conversion start request signal TGRD TGRB TGRB TGRB PPG output trigger signal TGRC TCNT TCNT TGRA TCNT TGRA Bus interface TGRB TCNT TCNT TGRA TCNT TGRA Module data bus TGRA TSR TSR TIER TIER TSR TIOR TIORH TIORL TIER: TSR: TGR (A, B, C, D): TCNT: TGRA TSR TIER TSR TSTR TSYR TIER TSR TIER TIOR TIOR TIOR TIER TMDR TIORH TIORL TCR TMDR Channel 4 TCR TMDR Channel 5 TCR Control logic TMDR TCR TMDR Channel 1 Channel 0 TCR Common Timer start register Timer synchronous register Timer control register Timer mode register Timer I/O control registers (H, L) TMDR Channel 2 Legend: TSTR: TSYR: TCR: TMDR: TIOR (H, L): Control logic for channels 0 to 2 Input/output pins TIOCA0 Channel 0: TIOCB0 TIOCC0 TIOCD0 TIOCA1 Channel 1: TIOCB1 TIOCA2 Channel 2: TIOCB2 TCR Clock input Internal clock: φ/1 φ/4 φ/16 φ/64 φ/256 φ/1024 φ/4096 External clock: TCLKA TCLKB TCLKC TCLKD Control logic for channels 3 to 5 Input/output pins TIOCA3 Channel 3: TIOCB3 TIOCC3 TIOCD3 TIOCA4 Channel 4: TIOCB4 TIOCA5 Channel 5: TIOCB5 Channel 3 Section 11 16-Bit Timer Pulse Unit (TPU) Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U Timer interrupt enable register Timer status register Timer general registers (A, B, C, D) Timer counter Figure 11.1 Block Diagram of TPU (Unit 0) Rev. 1.00 Sep. 19, 2008 Page 678 of 1270 REJ09B0466-0100 TGRD TGRB TGRC TGRB Interrupt request signals Channel 9: TGI9A TGI9B TGI9C TGI9D TCI9V Channel 10: TGI10A TGI10B TCI10V TCI10U Channel 11: TGI11A TGI11B TCI11V TCI11U Internal data bus A/D conversion start request signal TGRD TGRB TGRB TGRB PPG output trigger signal TGRC TCNT TCNT TGRA TCNT TGRA Bus interface TGRB TCNT TCNT TGRA TCNT TGRA Module data bus TGRA TSR TSR TIER TIER TSR TIOR TIORH TIORL TIER: TSR: TGR (A, B, C, D): TCNT: TGRA TSR TIER TSR TSTR TSYR TIER TSR TIER TIOR TIOR TIOR TIER TMDR TIORH TIORL TCR TMDR Channel 10 TCR TMDR Channel 11 TCR Control logic TMDR TCR TMDR Channel 7 Channel 8 TCR Common Timer start register Timer synchronous register Timer control register Timer mode register Timer I/O control registers (H, L) TMDR Channel 6 Legend: TSTR: TSYR: TCR: TMDR: TIOR (H, L): Control logic for channels 6 to 8 Input/output pins TIOCA6 Channel 6: TIOCB6 TIOCC6 TIOCD6 TIOCA7 Channel 7: TIOCB7 TIOCA8 Channel 8: TIOCB8 TCR Clock input Internal clock: φ/1 φ/4 φ/16 φ/64 φ/256 φ/1024 φ/4096 External clock: TCLKE TCLKF TCLKG TCLKH Control logic for channels 9 to 11 Input/output pins TIOCA9 Channel 9: TIOCB9 TIOCC9 TIOCD9 Channel 10: TIOCA10 TIOCB10 Channel 11: TIOCA11 TIOCB11 Channel 9 Section 11 16-Bit Timer Pulse Unit (TPU) Interrupt request signals Channel 6: TGI6A TGI6B TGI6C TGI6D TCI6V Channel 7: TGI7A TGI7B TCI7V TCI7U Channel 8: TGI8A TGI8B TCI8V TCI8U Timer interrupt enable register Timer status register Timer general registers (A, B, C, D) Timer counter Figure 11.2 Block Diagram of TPU (Unit 1) Rev. 1.00 Sep. 19, 2008 Page 679 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.2 Input/Output Pins Table 11.3 Pin Configuration Unit Channel Symbol I/O Function 0 All TCLKA Input External clock A input pin (Channel 1 and 5 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 and 5 phase counting mode B phase input) TCLKC Input External clock C input pin (Channel 2 and 4 phase counting mode A phase input) TCLKD Input External clock D input pin (Channel 2 and 4 phase counting mode B phase input) TIOCA0 I/O TGRA_0 input capture input/output compare output/PWM output pin TIOCB0 I/O TGRB_0 input capture input/output compare output/PWM output pin TIOCC0 I/O TGRC_0 input capture input/output compare output/PWM output pin TIOCD0 I/O TGRD_0 input capture input/output compare output/PWM output pin TIOCA1 I/O TGRA_1 input capture input/output compare output/PWM output pin TIOCB1 I/O TGRB_1 input capture input/output compare output/PWM output pin TIOCA2 I/O TGRA_2 input capture input/output compare output/PWM output pin TIOCB2 I/O TGRB_2 input capture input/output compare output/PWM output pin TIOCA3 I/O TGRA_3 input capture input/output compare output/PWM output pin TIOCB3 I/O TGRB_3 input capture input/output compare output/PWM output pin TIOCC3 I/O TGRC_3 input capture input/output compare output/PWM output pin TIOCD3 I/O TGRD_3 input capture input/output compare output/PWM output pin 0 1 2 3 Rev. 1.00 Sep. 19, 2008 Page 680 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Unit Channel Symbol I/O Function 0 4 TIOCA4 I/O TGRA_4 input capture input/output compare output/PWM output pin TIOCB4 I/O TGRB_4 input capture input/output compare output/PWM output pin TIOCA5 I/O TGRA_5 input capture input/output compare output/PWM output pin TIOCB5 I/O TGRB_5 input capture input/output compare output/PWM output pin TCLKE Input External clock E input pin (Channel 7 and 11 phase counting mode A phase input) TCLKF Input External clock F input pin (Channel 7 and 11 phase counting mode B phase input) TCLKG Input External clock G input pin (Channel 8 and 10 phase counting mode A phase input) TCLKH Input External clock H input pin (Channel 8 and 10 phase counting mode B phase input) TIOCA6 I/O TGRA_6 input capture input/output compare output/PWM output pin TIOCB6 I/O TGRB_6 input capture input/output compare output/PWM output pin TIOCC6 I/O TGRC_6 input capture input/output compare output/PWM output pin TIOCD6 I/O TGRD_6 input capture input/output compare output/PWM output pin TIOCA7 I/O TGRA_7 input capture input/output compare output/PWM output pin TIOCB7 I/O TGRB_7 input capture input/output compare output/PWM output pin TIOCA8 I/O TGRA_8 input capture input/output compare output/PWM output pin TIOCB8 I/O TGRB_8 input capture input/output compare output/PWM output pin 5 1 All 6 7 8 Rev. 1.00 Sep. 19, 2008 Page 681 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Unit Channel Symbol I/O Function 1 9 TIOCA9 I/O TGRA_9 input capture input/output compare output/PWM output pin TIOCB9 I/O TGRB_9 input capture input/output compare output/PWM output pin TIOCC9 I/O TGRC_9 input capture input/output compare output/PWM output pin TIOCD9 I/O TGRD_9 input capture input/output compare output/PWM output pin TIOCA10 I/O TGRA_10 input capture input/output compare output/PWM output pin TIOCB10 I/O TGRB_10 input capture input/output compare output/PWM output pin TIOCA11 I/O TGRA_11 input capture input/output compare output/PWM output pin TIOCB11 I/O TGRB_11 input capture input/output compare output/PWM output pin 10 11 Rev. 1.00 Sep. 19, 2008 Page 682 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3 Register Descriptions The TPU has the following registers in each channel. The descriptions in this section refer to the registers of unit 0. Unit 0: Channel 0 • Timer control register_0 (TCR_0) • Timer mode register_0 (TMDR_0) • Timer I/O control register H_0 (TIORH_0) • Timer I/O control register L_0 (TIORL_0) • Timer interrupt enable register_0 (TIER_0) • Timer status register_0 (TSR_0) • Timer counter_0 (TCNT_0) • Timer general register A_0 (TGRA_0) • Timer general register B_0 (TGRB_0) • Timer general register C_0 (TGRC_0) • Timer general register D_0 (TGRD_0) Channel 1 • Timer control register_1 (TCR_1) • Timer mode register_1 (TMDR_1) • Timer I/O control register_1 (TIOR_1) • Timer interrupt enable register_1 (TIER_1) • Timer status register_1 (TSR_1) • Timer counter_1 (TCNT_1) • Timer general register A_1 (TGRA_1) • Timer general register B_1 (TGRB_1) Rev. 1.00 Sep. 19, 2008 Page 683 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Channel 2 • Timer control register_2 (TCR_2) • Timer mode register_2 (TMDR_2) • Timer I/O control register_2 (TIOR_2) • Timer interrupt enable register_2 (TIER_2) • Timer status register_2 (TSR_2) • Timer counter_2 (TCNT_2) • Timer general register A_2 (TGRA_2) • Timer general register B_2 (TGRB_2) Channel 3 • Timer control register_3 (TCR_3) • Timer mode register_3 (TMDR_3) • Timer I/O control register H_3 (TIORH_3) • Timer I/O control register L_3 (TIORL_3) • Timer interrupt enable register_3 (TIER_3) • Timer status register_3 (TSR_3) • Timer counter_3 (TCNT_3) • Timer general register A_3 (TGRA_3) • Timer general register B_3 (TGRB_3) • Timer general register C_3 (TGRC_3) • Timer general register D_3 (TGRD_3) Channel 4 • Timer control register_4 (TCR_4) • Timer mode register_4 (TMDR_4) • Timer I/O control register_4 (TIOR_4) • Timer interrupt enable register_4 (TIER_4) • Timer status register_4 (TSR_4) • Timer counter_4 (TCNT_4) • Timer general register A_4 (TGRA_4) • Timer general register B_4 (TGRB_4) Rev. 1.00 Sep. 19, 2008 Page 684 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Channel 5 • Timer control register_5 (TCR_5) • Timer mode register_5 (TMDR_5) • Timer I/O control register_5 (TIOR_5) • Timer interrupt enable register_5 (TIER_5) • Timer status register_5 (TSR_5) • Timer counter_5 (TCNT_5) • Timer general register A_5 (TGRA_5) • Timer general register B_5 (TGRB_5) Common Registers of Unit 0 • Timer start register (TSTR) • Timer synchronous register (TSYR) Unit 1: Channel 6 • Timer control register_6 (TCR_6) • Timer mode register_6 (TMDR_6) • Timer I/O control register H_6 (TIORH_6) • Timer I/O control register L_6 (TIORL_6) • Timer interrupt enable register_6 (TIER_6) • Timer status register_6 (TSR_6) • Timer counter_6 (TCNT_6) • Timer general register A_6 (TGRA_6) • Timer general register B_6 (TGRB_6) • Timer general register C_6 (TGRC_6) • Timer general register D_6 (TGRD_6) Rev. 1.00 Sep. 19, 2008 Page 685 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Channel 7 • Timer control register_7 (TCR_7) • Timer mode register_7 (TMDR_7) • Timer I/O control register_7 (TIOR_7) • Timer interrupt enable register_7 (TIER_7) • Timer status register_7 (TSR_7) • Timer counter_7 (TCNT_7) • Timer general register A_7 (TGRA_7) • Timer general register B_7 (TGRB_7) Channel 8 • Timer control register_8 (TCR_8) • Timer mode register_8 (TMDR_8) • Timer I/O control register_8 (TIOR_8) • Timer interrupt enable register_8 (TIER_8) • Timer status register_8 (TSR_8) • Timer counter_8 (TCNT_8) • Timer general register A_8 (TGRA_8) • Timer general register B_8 (TGRB_8) Channel 9 • Timer control register_9 (TCR_9) • Timer mode register_9 (TMDR_9) • Timer I/O control register H_9 (TIORH_9) • Timer I/O control register L_9 (TIORL_9) • Timer interrupt enable register_9 (TIER_9) • Timer status register_9 (TSR_9) • Timer counter_9 (TCNT_9) • Timer general register A_9 (TGRA_9) • Timer general register B_9 (TGRB_9) • Timer general register C_9 (TGRC_9) • Timer general register D_9 (TGRD_9) Rev. 1.00 Sep. 19, 2008 Page 686 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Channel 10 • Timer control register_10 (TCR_10) • Timer mode register_10 (TMDR_10) • Timer I/O control register_10 (TIOR_10) • Timer interrupt enable register_10 (TIER_10) • Timer status register_10 (TSR_10) • Timer counter_10 (TCNT_10) • Timer general register A_10 (TGRA_10) • Timer general register B_10 (TGRB_10) Channel 11 • Timer control register_11 (TCR_11) • Timer mode register_11 (TMDR_11) • Timer I/O control register_11 (TIOR_11) • Timer interrupt enable register_11 (TIER_11) • Timer status register_11 (TSR_11) • Timer counter_11 (TCNT_11) • Timer general register A_11 (TGRA_11) • Timer general register B_11 (TGRB_11) Common Registers of Unit 1 • Timer start register B (TSTRB) • Timer synchronous register B (TSYRB) Rev. 1.00 Sep. 19, 2008 Page 687 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.1 Timer Control Register (TCR) The TCR registers control the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel. TCR register settings should be made only when TCNT operation is stopped. Bit Bit Name Initial Value R/W Description 7 CCLR2 0 R/W Counter Clear 2 to 0 6 CCLR1 0 R/W 5 CCLR0 0 R/W These bits select the TCNT counter clearing source. See tables 11.4 and 11.5 for details. 4 CKEG1 0 R/W Clock Edge 1 and 0 3 CKEG0 0 R/W These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. φ/4 both edges = φ/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is φ/4 or slower. This setting is ignored if the input clock is φ/1, or when overflow/underflow of another channel is selected. 00: Count at rising edge 01: Count at falling edge 1×: Count at both edges 2 TPSC2 0 R/W Time Prescaler 2 to 0 1 TPSC1 0 R/W 0 TPSC0 0 R/W These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 11.6 to 11.11 for details. [Legend] ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 688 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.4 CCLR2 to CCLR0 (Channels 0 and 3) Channel Bit 7 CCLR2 Bit 6 CCLR1 Bit 5 CCLR0 Description 0, 3 0 0 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 0 TCNT clearing disabled 1 TCNT cleared by TGRC compare match/input 2 capture* 0 TCNT cleared by TGRD compare match/input capture*2 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation*1 1 1 0 1 Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 11.5 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5) Channel Bit 7 Reserved*2 Bit 6 CCLR1 Bit 5 CCLR0 Description 1, 2, 4, 5 0 0 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation*1 1 Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be modified. Rev. 1.00 Sep. 19, 2008 Page 689 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.6 TPSC2 to TPSC0 (Channel 0) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 1 1 0 1 0 External clock: counts on TCLKC pin input 1 External clock: counts on TCLKD pin input Table 11.7 TPSC2 to TPSC0 (Channel 1) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 1 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 Internal clock: counts on φ/256 1 Counts on TCNT2 overflow/underflow 1 1 0 1 Note: This setting is ignored when channel 1 is in phase counting mode. Rev. 1.00 Sep. 19, 2008 Page 690 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.8 TPSC2 to TPSC0 (Channel 2) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 2 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 1 1 0 1 0 External clock: counts on TCLKC pin input 1 Internal clock: counts on φ/1024 Note: This setting is ignored when channel 2 is in phase counting mode. Table 11.9 TPSC2 to TPSC0 (Channel 3) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 3 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 Internal clock: counts on φ/1024 0 Internal clock: counts on φ/256 1 Internal clock: counts on φ/4096 1 1 0 1 Rev. 1.00 Sep. 19, 2008 Page 691 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.10 TPSC2 to TPSC0 (Channel 4) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 4 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKC pin input 1 1 0 1 0 Internal clock: counts on φ/1024 1 Counts on TCNT5 overflow/underflow Note: This setting is ignored when channel 4 is in phase counting mode. Table 11.11 TPSC2 to TPSC0 (Channel 5) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 5 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKC pin input 0 Internal clock: counts on φ/256 1 External clock: counts on TCLKD pin input 1 1 0 1 Note: This setting is ignored when channel 5 is in phase counting mode. Rev. 1.00 Sep. 19, 2008 Page 692 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.2 Timer Mode Register (TMDR) TMDR registers are used to set the operating mode for each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be made only when TCNT operation is stopped. Bit Bit Name Initial Value R/W Description 7 — 1 — Reserved 6 — 1 — These bits are always read as 1 and cannot be modified. 5 BFB 0 R/W Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB operates normally 1: TGRB and TGRD used together for buffer operation 4 BFA 0 R/W Buffer Operation A Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA operates normally 1: TGRA and TGRC used together for buffer operation 3 MD3 0 R/W Modes 3 to 0 2 MD2 0 R/W 1 MD1 0 R/W These bits are used to set the timer operating mode. 0 MD0 0 R/W MD3 is a reserved bit. The write value should always be 0. See table 11.12 for details. Rev. 1.00 Sep. 19, 2008 Page 693 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.12 MD3 to MD0 Bit 3 1 MD3* Bit 2 MD2*2 Bit 1 MD1 Bit 0 MD0 Description 0 0 0 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 1 1 0 1 1 × × 0 Phase counting mode 3 1 Phase counting mode 4 × [Legend] ×: Don’t care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. 11.3.3 Timer I/O Control Register (TIOR) TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. Rev. 1.00 Sep. 19, 2008 Page 694 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 Bit Bit Name Initial Value R/W Description 7 IOB3 0 R/W I/O Control B3 to B0 6 IOB2 0 R/W Specify the function of TGRB. 5 IOB1 0 R/W 4 IOB0 0 R/W For details, see tables 11.13, 11.15, 11.16, 11.17, 11.19, and 11.20. 3 IOA3 0 R/W I/O Control A3 to A0 2 IOA2 0 R/W Specify the function of TGRA. 1 IOA1 0 R/W 0 IOA0 0 R/W For details, see tables 11.21, 11.23, 11.24, 11.25, 11.27, and 11.28. TIORL_0, TIORL_3 Bit Bit Name Initial Value R/W Description 7 IOD3 0 R/W I/O Control D3 to D0 6 IOD2 0 R/W Specify the function of TGRD. 5 IOD1 0 R/W For details, see tables 11.14 and 11.18. 4 IOD0 0 R/W 3 IOC3 0 R/W I/O Control C3 to C0 2 IOC2 0 R/W Specify the function of TGRC. 1 IOC1 0 R/W For details, see tables 11.22 and 11.26. 0 IOC0 0 R/W Rev. 1.00 Sep. 19, 2008 Page 695 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.13 TIORH_0 Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_0 Function 0 0 0 0 Output compare register 1 TIOCB0 Pin Function Output disabled Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match 1 Initial output is 0 output Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 Input capture register 1 Capture input source is TIOCB0 pin Input capture at rising edge Capture input source is TIOCB0 pin Input capture at falling edge 1 × Capture input source is TIOCB0 pin Input capture at both edges 1 × × Capture input source is channel 1/count clock Input capture at TCNT_1 count- up/count-down* [Legend] ×: Don’t care Note: * When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. Rev. 1.00 Sep. 19, 2008 Page 696 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.14 TIORL_0 Description Bit 7 IOD3 Bit 6 IOD2 Bit 5 IOD1 Bit 4 IOD0 TGRD_0 Function 0 0 0 0 Output compare 2 register* 1 TIOCD0 Pin Function Output disabled Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match 1 Initial output is 0 output Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 1 Input capture register*2 Capture input source is TIOCD0 pin Input capture at rising edge Capture input source is TIOCD0 pin Input capture at falling edge 1 × Capture input source is TIOCD0 pin Input capture at both edges 1 × × Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* 1 [Legend] ×: Don’t care Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 1.00 Sep. 19, 2008 Page 697 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.15 TIOR_1 Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_1 Function 0 0 0 0 Output compare register 1 TIOCB1 Pin Function Output disabled Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match 1 Initial output is 0 output Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 Input capture register 1 Capture input source is TIOCB1 pin Input capture at rising edge Capture input source is TIOCB1 pin Input capture at falling edge 1 × Capture input source is TIOCB1 pin Input capture at both edges 1 × × TGRC_0 compare match/input capture Input capture at generation of TGRC_0 compare match/input capture [Legend] ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 698 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.16 TIOR_2 Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_2 Function 0 0 0 0 Output compare register 1 TIOCB2 Pin Function Output disabled Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match 1 Initial output is 0 output Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 × 0 0 1 Input capture register Capture input source is TIOCB2 pin Input capture at rising edge Capture input source is TIOCB2 pin Input capture at falling edge 1 × Capture input source is TIOCB2 pin Input capture at both edges [Legend] ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 699 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.17 TIORH_3 Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_3 Function 0 0 0 0 Output compare register 1 TIOCB3 Pin Function Output disabled Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match 1 Initial output is 0 output Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 Input capture register 1 Capture input source is TIOCB3 pin Input capture at rising edge Capture input source is TIOCB3 pin Input capture at falling edge 1 × Capture input source is TIOCB3 pin Input capture at both edges 1 × × Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* [Legend] ×: Don’t care Note: * When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and φ/1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. Rev. 1.00 Sep. 19, 2008 Page 700 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.18 TIORL_3 Description Bit 7 IOD3 Bit 6 IOD2 Bit 5 IOD1 Bit 4 IOD0 TGRD_3 Function 0 0 0 0 Output compare 2 register* 1 TIOCD3 Pin Function Output disabled Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match 1 Initial output is 0 output Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 1 Input capture register*2 Capture input source is TIOCD3 pin Input capture at rising edge Capture input source is TIOCD3 pin Input capture at falling edge 1 × Capture input source is TIOCD3 pin Input capture at both edges 1 × × Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* 1 [Legend] ×: Don’t care Notes: 1. When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and φ/1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 1.00 Sep. 19, 2008 Page 701 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.19 TIOR_4 Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_4 Function 0 0 0 0 Output compare register 1 TIOCB4 Pin Function Output disabled Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match 1 Initial output is 0 output Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 Input capture register 1 Capture input source is TIOCB4 pin Input capture at rising edge Capture input source is TIOCB4 pin Input capture at falling edge 1 × Capture input source is TIOCB4 pin Input capture at both edges 1 × × Capture input source is TGRC_3 compare match/input capture Input capture at generation of TGRC_3 compare match/input capture [Legend] ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 702 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.20 TIOR_5 Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_5 Function 0 0 0 0 Output compare register 1 TIOCB5 Pin Function Output disabled Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match 1 Initial output is 0 output Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 × 0 0 1 Input capture register Capture input source is TIOCB5 pin Input capture at rising edge Capture input source is TIOCB5 pin Input capture at falling edge 1 × Capture input source is TIOCB5 pin Input capture at both edges [Legend] ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 703 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.21 TIORH_0 Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_0 Function 0 0 0 0 Output compare register 1 TIOCA0 Pin Function Output disabled Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match 1 Initial output is 0 output Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 Input capture register 1 Capture input source is TIOCA0 pin Input capture at rising edge Capture input source is TIOCA0 pin Input capture at falling edge 1 × Capture input source is TIOCA0 pin Input capture at both edges 1 × × Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 704 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.22 TIORL_0 Description Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 TGRC_0 Function 0 0 0 0 Output compare register* 1 TIOCC0 Pin Function Output disabled Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match 1 Initial output is 0 output Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 1 Input capture register* Capture input source is TIOCC0 pin Input capture at rising edge Capture input source is TIOCC0 pin Input capture at falling edge 1 × Capture input source is TIOCC0 pin Input capture at both edges 1 × × Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] ×: Don’t care Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 1.00 Sep. 19, 2008 Page 705 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.23 TIOR_1 Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_1 Function 0 0 0 0 Output compare register 1 TIOCA1 Pin Function Output disabled Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match 1 Initial output is 0 output Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 Input capture register 1 Capture input source is TIOCA1 pin Input capture at rising edge Capture input source is TIOCA1 pin Input capture at falling edge 1 × Capture input source is TIOCA1 pin Input capture at both edges 1 × × Capture input source is TGRA_0 compare match/input capture Input capture at generation of channel 0/TGRA_0 compare match/input capture [Legend] ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 706 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.24 TIOR_2 Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_2 Function 0 0 0 0 Output compare register 1 TIOCA2 Pin Function Output disabled Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match 1 Initial output is 0 output Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 × 0 0 1 Input capture register Capture input source is TIOCA2 pin Input capture at rising edge Capture input source is TIOCA2 pin Input capture at falling edge 1 × Capture input source is TIOCA2 pin Input capture at both edges [Legend] ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 707 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.25 TIORH_3 Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_3 Function 0 0 0 0 Output compare register 1 TIOCA3 Pin Function Output disabled Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match 1 Initial output is 0 output Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 Input capture register 1 Capture input source is TIOCA3 pin Input capture at rising edge Capture input source is TIOCA3 pin Input capture at falling edge 1 × Capture input source is TIOCA3 pin Input capture at both edges 1 × × Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down [Legend] ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 708 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.26 TIORL_3 Description Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 TGRC_3 Function 0 0 0 0 Output compare register* 1 TIOCC3 Pin Function Output disabled Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match 1 Initial output is 0 output Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 1 Input capture register* Capture input source is TIOCC3 pin Input capture at rising edge Capture input source is TIOCC3 pin Input capture at falling edge 1 × Capture input source is TIOCC3 pin Input capture at both edges 1 × × Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down [Legend] ×: Don’t care Note: * When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 1.00 Sep. 19, 2008 Page 709 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.27 TIOR_4 Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_4 Function 0 0 0 0 Output compare register 1 TIOCA4 Pin Function Output disabled Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match 1 Initial output is 0 output Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 Input capture register 1 Capture input source is TIOCA4 pin Input capture at rising edge Capture input source is TIOCA4 pin Input capture at falling edge 1 × Capture input source is TIOCA4 pin Input capture at both edges 1 × × Capture input source is TGRA_3 compare match/input capture Input capture at generation of TGRA_3 compare match/input capture [Legend] ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 710 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.28 TIOR_5 Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_5 Function 0 0 0 0 Output compare register 1 TIOCA5 Pin Function Output disabled Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match 1 Initial output is 0 output Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 × 0 0 1 Input capture register Input capture source is TIOCA5 pin Input capture at rising edge Input capture source is TIOCA5 pin Input capture at falling edge 1 × Input capture source is TIOCA5 pin Input capture at both edges [Legend] ×: Don’t care Rev. 1.00 Sep. 19, 2008 Page 711 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.4 Timer Interrupt Enable Register (TIER) TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. Bit Bit Name Initial value R/W Description 7 TTGE 0 R/W A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled 6 — 1 — Reserved This bit is always read as 1 and cannot be modified. 5 TCIEU 0 R/W Underflow Interrupt Enable Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled 4 TCIEV 0 R/W Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled 3 TGIED 0 R/W TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled Rev. 1.00 Sep. 19, 2008 Page 712 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W Description 2 TGIEC 0 R/W TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled 1 TGIEB 0 R/W TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled Rev. 1.00 Sep. 19, 2008 Page 713 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.5 Timer Status Register (TSR) TSR registers indicate the status of each channel. The TPU has six TSR registers, one for each channel. Bit Bit Name Initial value R/W Description 7 TCFD 1 R Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified. 0: TCNT counts down 1: TCNT counts up 6 — 1 — Reserved This bit is always read as 1 and cannot be modified. 5 TCFU 0 R/(W)* Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 4 TCFV 0 R/(W)* Overflow Flag Status flag that indicates that TCNT overflow has occurred. [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 Rev. 1.00 Sep. 19, 2008 Page 714 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W Description 3 TGFD 0 R/(W)* Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] • When TCNT = TGRD while TGRD is functioning as output compare register • When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register [Clearing conditions] 2 TGFC 0 R/(W)* • When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFD after reading TGFD =1 Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] • When TCNT = TGRC while TGRC is functioning as output compare register • When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register [Clearing conditions] • When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFC after reading TGFC =1 Rev. 1.00 Sep. 19, 2008 Page 715 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W Description 1 TGFB 0 R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register [Clearing conditions] 0 TGFA 0 R/(W)* • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB =1 Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. [Setting conditions] When TCNT = TGRA while TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register [Clearing conditions] Note: * • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTE bit of DMABCR in DTC is 0 • When 0 is written to TGFA after reading TGFA =1 Only 0 can be written, for flag clearing. Rev. 1.00 Sep. 19, 2008 Page 716 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.6 Timer Counter (TCNT) The TCNT registers are 16-bit readable/writable counters. The TPU has six TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, or in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 11.3.7 Timer General Register (TGR) The TGR registers are 16-bit readable/writable registers with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. TGR buffer register combinations are TGRA–TGRC and TGRB–TGRD. 11.3.8 Timer Start Register (TSTR) TSTR selects operation/stoppage for channels 0 to 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit Bit Name Initial value R/W Description 7 — 0 — Reserved 6 — 0 — The write value should always be 0. 5 CST5 0 R/W Counter Start 5 to 0 4 CST4 0 R/W These bits select operation or stoppage for TCNT. 3 CST3 0 R/W 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_5 to TCNT_0 count operation is stopped 1: TCNT_5 to TCNT_0 performs count operation Rev. 1.00 Sep. 19, 2008 Page 717 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.9 Timer Synchronous Register (TSYR) TSYR selects independent operation or synchronous operation for the TCNT counters of channels 0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit Bit Name Initial value R/W Description 7 — 0 — Reserved 6 — 0 — The write value should always be 0. 5 SYNC5 0 R/W Timer Synchronization 5 to 0 4 SYNC4 0 R/W 3 SYNC3 0 R/W These bits select whether operation is independent of or synchronized with other channels. 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W When synchronous operation is selected, synchronous presetting of multiple channels, and synchronous clearing through counter clearing on another channel are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. 0: TCNT_5 to TCNT_0 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_5 to TCNT_0 performs synchronous operation (TCNT synchronous presetting/ synchronous clearing is possible) Rev. 1.00 Sep. 19, 2008 Page 718 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.10 Timer Start Register B (TSTRB) TSTRB selects operation/stoppage for channels 6 to 11. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit Bit Name Initial value R/W Description 7 — 0 — Reserved 6 — 0 — The write value should always be 0. 5 CST11 0 R/W Counter Start 11 to 6 4 CST10 0 R/W These bits select operation or stoppage for TCNT. 3 CST9 0 R/W 2 CST8 0 R/W 1 CST7 0 R/W 0 CST6 0 R/W If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_11 to TCNT_6 count operation is stopped 1: TCNT_11 to TCNT_6 performs count operation Rev. 1.00 Sep. 19, 2008 Page 719 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.11 Timer Synchronous Register B (TSYRB) TSYRB selects independent operation or synchronous operation for the TCNT counters of channels 6 to 11. A channel performs synchronous operation when the corresponding bit in TSYRB is set to 1. Bit Bit Name Initial value R/W Description 7 — 0 — Reserved 6 — 0 — The write value should always be 0. 5 SYNC11 0 R/W Timer Synchronization 11 to 6 4 SYNC10 0 R/W 3 SYNC9 0 R/W These bits select whether operation is independent of or synchronized with other channels. 2 SYNC8 0 R/W 1 SYNC7 0 R/W 0 SYNC6 0 R/W When synchronous operation is selected, synchronous presetting of multiple channels, and synchronous clearing through counter clearing on another channel are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. 0: TCNT_11 to TCNT_6 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_11 to TCNT_6 performs synchronous operation (TCNT synchronous presetting/ synchronous clearing is possible) Rev. 1.00 Sep. 19, 2008 Page 720 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.4 Operation 11.4.1 Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. (1) Counter Operation When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. (a) Example of count operation setting procedure Figure 11.3 shows an example of the count operation setting procedure. Rev. 1.00 Sep. 19, 2008 Page 721 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. Operation selection Select counter clock [1] Periodic counter [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. Free-running counter Select counter clearing source [2] Select output compare register [3] Set period [4] Start count [5] <Periodic counter> [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. Start count <Free-running counter> [5] [5] Set the CST bit in TSTR to 1 to start the counter operation. Figure 11.3 Example of Counter Operation Setting Procedure Rev. 1.00 Sep. 19, 2008 Page 722 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (b) Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (changes from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 11.4 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 11.4 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts count-up operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Rev. 1.00 Sep. 19, 2008 Page 723 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.5 illustrates periodic counter operation. Counter cleared by TGR compare match TCNT value TGR H'0000 Time CST bit Flag cleared by software or DTC activation TGF Figure 11.5 Periodic Counter Operation Rev. 1.00 Sep. 19, 2008 Page 724 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (2) Waveform Output by Compare Match The TPU can perform 0, 1, or toggle output from the corresponding output pin using a compare match. (a) Example of setting procedure for waveform output by compare match Figure 11.6 shows an example of the setting procedure for waveform output by a compare match. Output selection Select waveform output mode [1] [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. Set output timing [2] Start count [3] [3] Set the CST bit in TSTR to 1 to start the count operation. <Waveform output> Figure 11.6 Example of Setting Procedure for Waveform Output by Compare Match Rev. 1.00 Sep. 19, 2008 Page 725 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (b) Examples of waveform output operation Figure 11.7 shows an example of 0 output/1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change. TCNT value H'FFFF TGRA TGRB Time H'0000 No change No change 1 output TIOCA No change TIOCB No change 0 output Figure 11.7 Example of 0 Output/1 Output Operation Figure 11.8 shows an example of toggle output. In this example TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA Time H'0000 Toggle output TIOCB Toggle output TIOCA Figure 11.8 Example of Toggle Output Operation Rev. 1.00 Sep. 19, 2008 Page 726 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (3) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3, 4, 6, 7, 9, and 10 it is also possible to specify another channel’s counter input clock or compare match signal as the input capture source. Note: When another channel’s counter input clock is used as the input capture input for channels 0, 3, 6, and 9, φ/1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if φ/1 is selected. (a) Example of setting procedure for input capture operation Figure 11.9 shows an example of the setting procedure for input capture operation. [1] Designate TGR as an input capture register by means of TIOR, and select the input capture source and input signal edge (rising edge, falling edge, or both edges). Input selection Select input capture input [1] Start count [2] [2] Set the CST bit in TSTR to 1 to start the count operation. <Input capture operation> Figure 11.9 Example of Setting Procedure for Input Capture Operation Rev. 1.00 Sep. 19, 2008 Page 727 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (b) Example of input capture operation Figure 11.10 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 Time H'0000 TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 11.10 Example of Input Capture Operation 11.4.2 Synchronous Operation In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously (synchronous presetting). Also, multiple of TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in TCR. Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 and 6 to 11 can all be designated for synchronous operation. Rev. 1.00 Sep. 19, 2008 Page 728 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (1) Example of Synchronous Operation Setting Procedure Figure 11.11 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Set TCNT Synchronous clearing [2] Clearing source generation channel? No Yes <Synchronous presetting> Select counter clearing source [3] Set synchronous counter clearing [4] Start count [5] Start count [5] <Counter clearing> <Synchronous clearing> [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Figure 11.11 Example of Synchronous Operation Setting Procedure Rev. 1.00 Sep. 19, 2008 Page 729 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (2) Example of Synchronous Operation Figure 11.12 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2. At this time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, is performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details on PWM modes, see section 11.4.5, PWM Modes. Synchronous clearing by TGRB_0 compare match TCNT0 to TCNT2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 Time H'0000 TIOCA_0 TIOCA_1 TIOCA_2 Figure 11.12 Example of Synchronous Operation Rev. 1.00 Sep. 19, 2008 Page 730 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.3 Buffer Operation Buffer operation, provided for channels 0, 3, 6, and 9, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or a compare match register. Table 11.29 shows the register combinations used in buffer operation. Table 11.29 Register Combinations in Buffer Operation Unit Channel Timer General Register Buffer Register 0 0 TGRA_0 TGRC_0 TGRB_0 TGRD_0 TGRA_3 TGRC_3 TGRB_3 TGRD_3 3 1 6 9 TGRA_6 TGRC_6 TGRB_6 TGRD_6 TGRA_9 TGRC_9 TGRB_9 TGRD_9 • When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 11.13. Compare match signal Buffer register Timer general register Comparator TCNT Figure 11.13 Compare Match Buffer Operation Rev. 1.00 Sep. 19, 2008 Page 731 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 11.14. Input capture signal Timer general register Buffer register TCNT Figure 11.14 Input Capture Buffer Operation (1) Example of Buffer Operation Setting Procedure Figure 11.15 shows an example of the buffer operation setting procedure. [1] Designate TGR as an input capture register or output compare register by means of TIOR. Buffer operation [1] [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. Set buffer operation [2] [3] Set the CST bit in TSTR to 1 to start the count operation. Start count [3] Select TGR function <Buffer operation> Figure 11.15 Example of Buffer Operation Setting Procedure Rev. 1.00 Sep. 19, 2008 Page 732 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (2) Examples of Buffer Operation (a) When TGR is an output compare register Figure 11.16 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare match A occurs. For details on PWM modes, see section 11.4.5, PWM Modes. TCNT value TGRB_0 H'0520 H'0450 H'0200 TGRA_0 Time H'0000 H'0450 TGRC_0 H'0200 H'0520 Transfer TGRA_0 H'0200 H'0450 TIOCA Figure 11.16 Example of Buffer Operation (1) Rev. 1.00 Sep. 19, 2008 Page 733 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (b) When TGR is an input capture register Figure 11.17 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 TGRC H'0F07 H'09FB H'0532 H'0F07 Figure 11.17 Example of Buffer Operation (2) Rev. 1.00 Sep. 19, 2008 Page 734 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4, channel 7, or channel 10) counter clock at overflow/underflow of TCNT_2 (TCNT_5, TCNT_8, or TCNT_11) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 11.30 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. Table 11.30 Cascaded Combinations Combination Upper 16 Bits Lower 16 Bits Channels 1 and 2 TCNT_1 TCNT_2 Channels 4 and 5 TCNT_4 TCNT_5 Channels 7 and 8 TCNT_7 TCNT_8 Channels 10 and 11 TCNT_10 TCNT_11 (1) Example of Cascaded Operation Setting Procedure Figure 11.18 shows an example of the setting procedure for cascaded operation. Cascaded operation Set cascading [1] Start count [2] [1] Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B'1111 to select TCNT_2 (TCNT_5) overflow/underflow counting. [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. <Cascaded operation> Figure 11.18 Cascaded Operation Setting Procedure Rev. 1.00 Sep. 19, 2008 Page 735 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (2) Examples of Cascaded Operation Figure 11.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been designated as input capture registers, and the TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2. TCNT_1 clock TCNT_1 H'03A1 H'03A2 TCNT_2 clock TCNT_2 H'FFFF H'0001 H'0000 TIOCA1, TIOCA2 TGRA_1 H'03A2 TGRA_2 H'0000 Figure 11.19 Example of Cascaded Operation (1) Figure 11.20 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow. TCLKC TCLKD TCNT_2 TCNT_1 FFFD FFFE FFFF 0000 0000 0001 0002 0001 0000 0001 Figure 11.20 Example of Cascaded Operation (2) Rev. 1.00 Sep. 19, 2008 Page 736 of 1270 REJ09B0466-0100 FFFF 0000 Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0–% to 100–% duty cycle. Designating TGR compare match as the counter clearing source enables the cycle to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. • PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The outputs specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR are output from the TIOCA and TIOCC pins at compare matches A and C, respectively. The outputs specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR are output at compare matches B and D, respectively. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. • PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty cycle registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 11.31. Rev. 1.00 Sep. 19, 2008 Page 737 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.31 PWM Output Registers and Output Pins Output Pins Unit Channel Registers PWM Mode 1 PWM Mode 2 0 0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TGRA_1 TGRB_1 TGRA_2 TGRB_2 TGRA_3 TGRB_3 TGRC_3 TGRD_3 TGRA_4 TIOCA0 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 1 2 3 4 5 1 6 7 8 9 10 11 TGRB_4 TGRA_5 TGRB_5 TGRA_6 TGRB_6 TGRC_6 TGRD_6 TGRA_7 TGRB_7 TGRA_8 TGRB_8 TGRA_9 TGRB_9 TGRC_9 TGRD_9 TGRA_10 TGRB_10 TGRA_11 TGRB_11 TIOCC0 TIOCA1 TIOCA2 TIOCA3 TIOCC3 TIOCA4 TIOCA5 TIOCA6 TIOCC6 TIOCA7 TIOCA8 TIOCA9 TIOCC9 TIOCA10 TIOCA11 TIOCB4 TIOCA5 TIOCB5 TIOCA6 TIOCB6 TIOCC6 TIOCD6 TIOCA7 TIOCB7 TIOCA8 TIOCB8 TIOCA9 TIOCB9 TIOCC9 TIOCD9 TIOCA10 TIOCB10 TIOCA11 TIOCB11 Note: In PWM mode 2, PWM output is not possible for the TGR register in which the cycle is set. Rev. 1.00 Sep. 19, 2008 Page 738 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (1) Example of PWM Mode Setting Procedure Figure 11.21 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. Select counter clearing source Select waveform output level Set TGR [2] [3] [4] [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other TGRs. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. Set PWM mode [5] Start count [6] [6] Set the CST bit in TSTR to 1 to start the count operation. <PWM mode> Figure 11.21 Example of PWM Mode Setting Procedure Rev. 1.00 Sep. 19, 2008 Page 739 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (2) Examples of PWM Mode Operation Figure 11.22 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the cycle, and the values set in TGRB registers as the duty cycle. TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 11.22 Example of PWM Mode Operation (1) Rev. 1.00 Sep. 19, 2008 Page 740 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.23 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs as the duty cycle. TCNT value Counter cleared by TGRB_1 compare match TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000 Time TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 Figure 11.23 Example of PWM Mode Operation (2) Rev. 1.00 Sep. 19, 2008 Page 741 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.24 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB rewritten TGRB H'0000 Time 100% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB TGRB rewritten Time H'0000 100% duty TIOCA 0% duty Figure 11.24 Example of PWM Mode Operation (3) Rev. 1.00 Sep. 19, 2008 Page 742 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, 5, 7, 8, 10, and 11. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 11.32 shows the correspondence between external clock pins and channels. Table 11.32 Clock Input Pins in Phase Counting Mode External Clock Pins Unit Channels A-Phase B-Phase 0 When channel 1 or 5 is set to phase counting mode TCLKA TCLKB When channel 2 or 4 is set to phase counting mode TCLKC TCLKD When channel 7 or 11 is set to phase counting mode TCLKE TCLKF When channel 8 or 10 is set to phase counting mode TCLKG TCLKH 1 Rev. 1.00 Sep. 19, 2008 Page 743 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (1) Example of Phase Counting Mode Setting Procedure Figure 11.25 shows an example of the phase counting mode setting procedure. [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Phase counting mode Select phase counting mode [1] Start count [2] <Phase counting mode> Figure 11.25 Example of Phase Counting Mode Setting Procedure (2) Examples of Phase Counting Mode Operation In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. a. Phase counting mode 1 Figure 11.26 shows an example of phase counting mode 1 operation, and table 11.33 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 11.26 Example of Phase Counting Mode 1 Operation Rev. 1.00 Sep. 19, 2008 Page 744 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.33 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKE (Channels 7 and 11) TCLKG (Channels 8 and 10) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) TCLKF (Channels 7 and 11) TCLKH (Channels 8 and 10) Operation Up-count High level Low level Low level High level High level Down-count Low level High level Low level [Legend] : Rising edge : Falling edge Rev. 1.00 Sep. 19, 2008 Page 745 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) b. Phase counting mode 2 Figure 11.27 shows an example of phase counting mode 2 operation, and table 11.34 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 11.27 Example of Phase Counting Mode 2 Operation Table 11.34 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKE (Channels 7 and 11) TCLKG (Channels 8 and 10) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) TCLKF (Channels 7 and 11) TCLKH (Channels 8 and 10) Operation Don't care High level Low level Don't care Low level Don't care High level Up-count High level Don't care Low level Don't care High level Don't care Low level Down-count [Legend] : Rising edge : Falling edge Rev. 1.00 Sep. 19, 2008 Page 746 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) c. Phase counting mode 3 Figure 11.28 shows an example of phase counting mode 3 operation, and table 11.35 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count Time Figure 11.28 Example of Phase Counting Mode 3 Operation Table 11.35 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKE (Channels 7 and 11) TCLKG (Channels 8 and 10) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) TCLKF (Channels 7 and 11) TCLKH (Channels 8 and 10) Operation High level Don't care Low level Don't care Low level Don't care High level Up-count High level Down-count Low level Don't care [Legend] : : High level Don't care Low level Don't care Rising edge Falling edge Rev. 1.00 Sep. 19, 2008 Page 747 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) d. Phase counting mode 4 Figure 11.29 shows an example of phase counting mode 4 operation, and table 11.36 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count Time Figure 11.29 Example of Phase Counting Mode 4 Operation Table 11.36 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKE (Channels 7 and 11) TCLKG (Channels 8 and 10) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) TCLKF (Channels 7 and 11) TCLKH (Channels 8 and 10) Operation Up-count High level Low level Low level Don’t care High level High level Down-count Low level High level Low level [Legend] : Rising edge : Falling edge Rev. 1.00 Sep. 19, 2008 Page 748 of 1270 REJ09B0466-0100 Don’t care Section 11 16-Bit Timer Pulse Unit (TPU) (3) Phase Counting Mode Application Example Figure 11.30 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function, and are set with the speed control cycle and position control cycle. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source, and the up/down-counter values for the control cycles are stored. This procedure enables accurate position/speed detection to be achieved. Rev. 1.00 Sep. 19, 2008 Page 749 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed cycle capture) TGRB_1 (position cycle capture) TCNT_0 TGRA_0 (speed control cycle) + - TGRC_0 (position control cycle) + - TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 11.30 Phase Counting Mode Application Example 11.5 Interrupt Sources There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. For details, see section 5, Interrupt Controller. Table 11.37 lists the TPU interrupt sources. Rev. 1.00 Sep. 19, 2008 Page 750 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.37 TPU Interrupts Unit Channel Name Interrupt Source Interrupt Flag DTC Activation DMAC Activation 0 TGI0A TGRA_0 input capture/compare match TGFA_0 Possible Possible TGI0B TGRB_0 input capture/compare match TGFB_0 Possible Not possible TGI0C TGRC_0 input capture/compare match TGFC_0 Possible Not possible TGI0D TGRD_0 input capture/compare match TGFD_0 Possible Not possible TCI0V TCNT_0 overflow TCFV_0 Not possible Not possible TGI1A TGRA_1 input capture/compare match TGFA_1 Possible Possible 0 1 2 3 4 5 TGI1B TGRB_1 input capture/compare match TGFB_1 Possible Not possible TCI1V TCNT_1 overflow TCFV_1 Not possible Not possible TCI1U TCNT_1 underflow TCFU_1 Not possible Not possible TGI2A TGRA_2 input capture/compare match TGFA_2 Possible Possible TGI2B TGRB_2 input capture/compare match TGFB_2 Possible Not possible TCI2V TCNT_2 overflow TCFV_2 Not possible Not possible TCI2U TCNT_2 underflow TCFU_2 Not possible Not possible TGI3A TGRA_3 input capture/compare match TGFA_3 Possible Possible TGI3B TGRB_3 input capture/compare match TGFB_3 Possible Not possible TGI3C TGRC_3 input capture/compare match TGFC_3 Possible Not possible TGI3D TGRD_3 input capture/compare match TGFD_3 Possible Not possible TCI3V TCNT_3 overflow TCFV_3 Not possible Not possible TGI4A TGRA_4 input capture/compare match TGFA_4 Possible Possible TGI4B TGRB_4 input capture/compare match TGFB_4 Possible Not possible TCI4V TCNT_4 overflow TCFV_4 Not possible Not possible TCI4U TCNT_4 underflow TCFU_4 Not possible Not possible TGI5A TGRA_5 input capture/compare match TGFA_5 Possible Possible TGI5B TGRB_5 input capture/compare match TGFB_5 Possible Not possible TCI5V TCNT_5 overflow TCFV_5 Not possible Not possible TCI5U TCNT_5 underflow TCFU_5 Not possible Not possible Rev. 1.00 Sep. 19, 2008 Page 751 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Unit Channel Name Interrupt Source Interrupt Flag DTC Activation DMAC Activation 1 TGI6A TGRA_6 input capture/compare match TGFA_6 Possible Not possible TGI6B TGRB_6 input capture/compare match TGFB_6 Possible Not possible TGI6C TGRC_6 input capture/compare match TGFC_6 Possible Not possible TGI6D TGRD_6 input capture/compare match TGFD_6 Possible Not possible 6 7 8 9 10 11 Note: TCI6V TCNT_6 overflow TCFV_6 Not possible Not possible TGI7A TGRA_7 input capture/compare match TGFA_7 Possible Not possible TGI7B TGRB_7 input capture/compare match TGFB_7 Possible Not possible TCI7V TCNT_7 overflow TCFV_7 Not possible Not possible TCI7U TCNT_7 underflow TCFU_7 Not possible Not possible TGI8A TGRA_8 input capture/compare match TGFA_8 Possible Not possible TGI8B TGRB_8 input capture/compare match TGFB_8 Possible Not possible TCI8V TCNT_8 overflow TCFV_8 Not possible Not possible TCI8U TCNT_8 underflow TCFU_8 Not possible Not possible TGI9A TGRA_9 input capture/compare match TGFA_9 Possible Not possible TGI9B TGRB_9 input capture/compare match TGFB_9 Possible Not possible TGI9C TGRC_9 input capture/compare match TGFC_9 Possible Not possible TGI9D TGRD_9 input capture/compare match TGFD_9 Possible Not possible TCI9V TCNT_9 overflow TCFV_9 Not possible Not possible TGI10A TGRA_10 input capture/compare match TGFA_10 Possible Not possible TGI10B TGRB_10 input capture/compare match TGFB_10 Possible Not possible TCI10V TCNT_10 overflow TCFV_10 Not possible Not possible TCI10U TCNT_10 underflow TCFU_10 Not possible Not possible TGI11A TGRA_11 input capture/compare match TGFA_11 Possible Not possible TGI11B TGRB_11 input capture/compare match TGFB_11 Possible Not possible TCI11V TCNT_11 overflow TCFV_11 Not possible Not possible TCI11U TCNT_11 underflow TCFU_11 Not possible Not possible This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. Rev. 1.00 Sep. 19, 2008 Page 752 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (1) Input Capture/Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 32 input capture/compare match interrupts, four each for channels 0, 3, 6, and 9, and two each for channels 1, 2, 4, 5, 7, 8, 10, and 11. (2) Overflow Interrupt An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has 12 overflow interrupts, one for each channel. (3) Underflow Interrupt An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has eight underflow interrupts, one each for channels 1, 2, 4, 5, 7, 8, 10, and 11. 11.6 DTC Activation The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 9, Data Transfer Controller (DTC). A total of 32 TPU input capture/compare match interrupts can be used as DTC activation sources, four each for channels 0, 3, 6, and 9, and two each for channels 1, 2, 4, 5, 7, 8, 10, and 11. 11.7 DMAC Activation In unit 0 of the TPU, the DMAC can be activated by the TGRA input capture/compare match interrupt for a channel. For details, see section 7, DMA Controller (DMAC). (The DMAC cannot be activated by unit 1.) In unit 0 of the TPU, a total of six TGRA input capture/compare match interrupts can be used as DMAC activation sources, one for each channel. Rev. 1.00 Sep. 19, 2008 Page 753 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.8 A/D Converter Activation The A/D converter can be activated by the TGRA input capture/compare match for a channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. In the TPU, a total of 12 TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. 11.9 Operation Timing 11.9.1 Input/Output Timing (1) TCNT Count Timing Figure 11.31 shows TCNT count timing in internal clock operation, and figure 11.32 shows TCNT count timing in external clock operation. φ Internal clock Falling edge Rising edge TCNT input clock TCNT N–1 N N+1 Figure 11.31 Count Timing in Internal Clock Operation Rev. 1.00 Sep. 19, 2008 Page 754 of 1270 REJ09B0466-0100 N+2 Section 11 16-Bit Timer Pulse Unit (TPU) φ External clock Falling edge Rising edge Falling edge TCNT input clock TCNT N–1 N N+1 N+2 Figure 11.32 Count Timing in External Clock Operation (2) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the (TIOC pin) TCNT input clock is generated. Figure 11.33 shows output compare output timing. φ TCNT input clock TCNT TGR N N+1 N Compare match signal TIOC pin Figure 11.33 Output Compare Output Timing Rev. 1.00 Sep. 19, 2008 Page 755 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (3) Input Capture Signal Timing Figure 11.34 shows input capture signal timing. φ Input capture input Input capture signal TCNT N+1 N N+2 N TGR N+2 Figure 11.34 Input Capture Input Signal Timing (4) Timing for Counter Clearing by Compare Match/Input Capture Figure 11.35 shows the timing when counter clearing by compare match occurrence is specified, and figure 11.36 shows the timing when counter clearing by input capture occurrence is specified. φ Compare match signal Counter clear signal TCNT N TGR N H'0000 Figure 11.35 Counter Clear Timing (Compare Match) Rev. 1.00 Sep. 19, 2008 Page 756 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) φ Input capture signal Counter clear signal H'0000 N TCNT N TGR Figure 11.36 Counter Clear Timing (Input Capture) (5) Buffer Operation Timing Figures 11.37 and 11.38 show the timings in buffer operation. φ TCNT n n+1 Compare match signal TGRA, TGRB n TGRC, TGRD N N Figure 11.37 Buffer Operation Timing (Compare Match) Rev. 1.00 Sep. 19, 2008 Page 757 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) φ Input capture signal TCNT N TGRA, TGRB n N+1 TGRC, TGRD N N+1 n N Figure 11.38 Buffer Operation Timing (Input Capture) 11.9.2 (1) Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match Figure 11.39 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal timing. φ TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 11.39 TGI Interrupt Timing (Compare Match) Rev. 1.00 Sep. 19, 2008 Page 758 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (2) TGF Flag Setting Timing in Case of Input Capture Figure 11.40 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and the TGI interrupt request signal timing. φ Input capture signal TCNT TGR N N TGF flag TGI interrupt Figure 11.40 TGI Interrupt Timing (Input Capture) Rev. 1.00 Sep. 19, 2008 Page 759 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (3) TCFV Flag/TCFU Flag Setting Timing Figure 11.41 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and the TCIV interrupt request signal timing. Figure 11.42 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and the TCIU interrupt request signal timing. φ TCNT input clock TCNT (overflow) H'FFFF H'0000 Overflow signal TCFV flag TCIV interrupt Figure 11.41 TCIV Interrupt Setting Timing φ TCNT input clock TCNT (underflow) H'0000 H'FFFF Underflow signal TCFU flag TCIU interrupt Figure 11.42 TCIU Interrupt Setting Timing Rev. 1.00 Sep. 19, 2008 Page 760 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (4) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 11.43 shows the timing for status flag clearing by the CPU, and figure 11.44 shows the timing for status flag clearing by the DTC or DMAC. TSR write cycle T2 T1 φ Address TSR address Write signal Status flag Interrupt request signal Figure 11.43 Timing for Status Flag Clearing by CPU DTC/DMAC read cycle T1 T2 DTC/DMAC write cycle T1 T2 φ Address Source address Destination address Status flag Interrupt request signal Figure 11.44 Timing for Status Flag Clearing by DTC/DMAC Activation Rev. 1.00 Sep. 19, 2008 Page 761 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10 Usage Notes 11.10.1 Module Stop Mode Setting TPU operation can be disabled or enabled using the module stop control register. The initial setting is for TPU operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 24, Power-Down Modes. 11.10.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 11.45 shows the input clock conditions in phase counting mode. Overlap Phase Phase diffediffeOverlap rence rence Pulse width Pulse width TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more Figure 11.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Rev. 1.00 Sep. 19, 2008 Page 762 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.3 Caution on Cycle Setting When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: φ f= (N + 1) Where f: Counter frequency φ: Operating frequency N: TGR set value 11.10.4 Contention between TCNT Write and Clear Operations If the counter clearing signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 11.46 shows the timing in this case. TCNT write cycle T1 T2 φ TCNT address Address Write signal Counter clearing signal TCNT N H'0000 Figure 11.46 Contention between TCNT Write and Clear Operations Rev. 1.00 Sep. 19, 2008 Page 763 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 11.47 shows the timing in this case. TCNT write cycle T2 T1 φ TCNT address Address Write signal TCNT input clock TCNT N M TCNT write data Figure 11.47 Contention between TCNT Write and Increment Operations Rev. 1.00 Sep. 19, 2008 Page 764 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.6 Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written. Figure 11.48 shows the timing in this case. TGR write cycle T2 T1 φ TGR address Address Write signal Compare match signal Disabled TCNT N N+1 TGR N M TGR write data Figure 11.48 Contention between TGR Write and Compare Match Rev. 1.00 Sep. 19, 2008 Page 765 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.7 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 11.49 shows the timing in this case. TGR write cycle T2 T1 φ Buffer register address Address Write signal Compare match signal Buffer register write data Buffer register TGR N M N Figure 11.49 Contention between Buffer Register Write and Compare Match Rev. 1.00 Sep. 19, 2008 Page 766 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.8 Contention between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 11.50 shows the timing in this case. TGR read cycle T1 T2 φ TGR address Address Read signal Input capture signal TGR X Internal data bus M M Figure 11.50 Contention between TGR Read and Input Capture Rev. 1.00 Sep. 19, 2008 Page 767 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.9 Contention between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 11.51 shows the timing in this case. TGR write cycle T1 T2 φ Address TGR address Write signal Input capture signal TCNT M M TGR Figure 11.51 Contention between TGR Write and Input Capture Rev. 1.00 Sep. 19, 2008 Page 768 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.10 Contention between Buffer Register Write and Input Capture If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 11.52 shows the timing in this case. Buffer register write cycle T1 T2 φ Buffer register address Address Write signal Input capture signal TCNT TGR Buffer register N M N M Figure 11.52 Contention between Buffer Register Write and Input Capture Rev. 1.00 Sep. 19, 2008 Page 769 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.11 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 11.53 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. φ TCNT input clock TCNT H'FFFF H'0000 Counter clearing signal TGF Disabled TCFV Figure 11.53 Contention between Overflow and Counter Clearing Rev. 1.00 Sep. 19, 2008 Page 770 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.12 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, when overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 11.54 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T2 T1 φ TCNT address Address Write signal TCNT TCNT write data H'FFFF M TCFV flag Figure 11.54 Contention between TCNT Write and Overflow 11.10.13 Multiplexing of I/O Pins In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. 11.10.14 Interrupts and Module Stop Mode If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Rev. 1.00 Sep. 19, 2008 Page 771 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 772 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) Section 12 Programmable Pulse Generator (PPG) The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 to 0) that can operate both simultaneously and independently. The block diagram of PPG is shown in figure 12.1. 12.1 • • • • • • • Features 16-bit output data Four output groups Selectable output trigger signals Non-overlap mode Can operate together with the data transfer controller (DTC) and the DMA controller (DMAC) Settable inverted output Module stop mode can be set Rev. 1.00 Sep. 19, 2008 Page 773 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) Compare match signals Control logic PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 Legend: PMR PCR NDERH NDERL NDRH NDRL PODRH PODRL NDERH NDERL PMR PCR Pulse output pins, group 3 PODRH NDRH (NDRHH, NDRHL) PODRL NDRL (NDRLH, NDRLL) Pulse output pins, group 2 Pulse output pins, group 1 Pulse output pins, group 0 : PPG output mode register : PPG output control register : Next data enable register H : Next data enable register L : Next data register H : Next data register L : Output data register H : Output data register L Figure 12.1 Block Diagram of PPG Rev. 1.00 Sep. 19, 2008 Page 774 of 1270 REJ09B0466-0100 Internal data bus Section 12 Programmable Pulse Generator (PPG) 12.2 Input/Output Pins Table 12.1 shows the PPG pin configuration. Table 12.1 Pin Configuration Pin Name I/O Function PO15 Output Group 3 pulse output PO14 Output PO13 Output PO12 Output PO11 Output PO10 Output PO9 Output PO8 Output PO7 Output PO6 Output PO5 Output PO4 Output PO3 Output PO2 Output PO1 Output PO0 Output 12.3 Group 2 pulse output Group 1 pulse output Group 0 pulse output Register Descriptions The PPG has the following registers. • • • • • • • • Next data enable register H (NDERH) Next data enable register L (NDERL) Output data register H (PODRH) Output data register L (PODRL) Next data register H (NDRH) Next data register L (NDRL) PPG output control register (PCR) PPG output mode register (PMR) Rev. 1.00 Sep. 19, 2008 Page 775 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.3.1 Next Data Enable Registers H, L (NDERH, NDERL) NDERH, NDERL enable or disable pulse output on a bit-by-bit basis. For outputting pulse by the PPG, set the corresponding DDR to 1. • NDERH Bit Bit Name Initial Value R/W Description 7 NDER15 0 R/W Next Data Enable 15 to 8 6 NDER14 0 R/W 5 NDER13 0 R/W 4 NDER12 0 R/W 3 NDER11 0 R/W When a bit is set to 1, the value in the corresponding NDRH bit is transferred to the PODRH bit by the selected output trigger. Values are not transferred from NDRH to PODRH for cleared bits. 2 NDER10 0 R/W 1 NDER9 0 R/W 0 NDER8 0 R/W • NDERL Bit Bit Name Initial Value R/W Description 7 NDER7 0 R/W Next Data Enable 7 to 0 6 NDER6 0 R/W 5 NDER5 0 R/W 4 NDER4 0 R/W 3 NDER3 0 R/W When a bit is set to 1, the value in the corresponding NDRL bit is transferred to the PODRL bit by the selected output trigger. Values are not transferred from NDRL to PODRL for cleared bits. 2 NDER2 0 R/W 1 NDER1 0 R/W 0 NDER0 0 R/W Rev. 1.00 Sep. 19, 2008 Page 776 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.3.2 Output Data Registers H, L (PODRH, PODRL) PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified. • PODRH Bit Bit Name Initial Value R/W Description 7 POD15 0 R/W Output Data Register 15 to 8 6 POD14 0 R/W 5 POD13 0 R/W 4 POD12 0 R/W 3 POD11 0 R/W 2 POD10 0 R/W For bits which have been set to pulse output by NDERH, the output trigger transfers NDRH values to this register during PPG operation. While NDERH is set to 1, the CPU cannot write to this register. While NDERH is cleared, the initial output value of the pulse can be set. 1 POD9 0 R/W 0 POD8 0 R/W • PODRL Bit Bit Name Initial Value R/W Description 7 POD7 0 R/W Output Data Register 7 to 0 6 POD6 0 R/W 5 POD5 0 R/W 4 POD4 0 R/W 3 POD3 0 R/W 2 POD2 0 R/W For bits which have been set to pulse output by NDERL, the output trigger transfers NDRL values to this register during PPG operation. While NDERL is set to 1, the CPU cannot write to this register. While NDERL is cleared, the initial output value of the pulse can be set. 1 POD1 0 R/W 0 POD0 0 R/W Rev. 1.00 Sep. 19, 2008 Page 777 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.3.3 Next Data Registers H, L (NDRH, NDRL) NDRH, NDRL store the next data for pulse output. The NDR addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. • NDRH (NDRHH, NDRHL)* If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Note: * When pulse output groups 2 and 3 have the same output trigger by PCR settings, the NDRH address is H′FF4C. When they have different output triggers, the NDRH addresses corresponding to the groups 2 and 3 are NDRHH (H′FF4E) and NDRHL (H′FF4C), respectively. Also, when pulse output groups 0 and 1 have the same output trigger by PCR settings, the NDRL address is NDRLH (H′FF4D). When they have different output triggers, the NDRL addresses corresponding to the groups 0 and 1 are NDRLL (H′FF4F) and H′FF4D, respectively. Bit Bit Name Initial Value R/W Description 7 NDR15 0 R/W Next Data Register 15 to 8 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W If pulse output groups 2 and 3 have different output triggers, upper 4 bits and lower 4 bits are mapped to the different addresses as shown below. Bit Bit Name Initial Value R/W Description 7 NDR15 0 R/W Next Data Register 15 to 12 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. 3 to 0 — All 1 — Reserved 1 is always read and write is disabled. Rev. 1.00 Sep. 19, 2008 Page 778 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) Bit Bit Name Initial Value R/W Description 7 to 4 — All 1 — Reserved 1 is always read and write is disabled. 3 NDR11 0 R/W Next Data Register 11 to 8 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. • NDRL (NDRLH, NDRLL)* If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Note: * When pulse output groups 2 and 3 have the same output trigger by PCR settings, the NDRH address is H¢FF4C. When they have different output triggers, the NDRH addresses corresponding to the groups 2 and 3 are NDRHH (H¢FF4E) and NDRHL (H¢FF4C), respectively. Also, when pulse output groups 0 and 1 have the same output trigger by PCR settings, the NDRL address is NDRLH (H¢FF4D). When they have different output triggers, the NDRL addresses corresponding to the groups 0 and 1 are NDRLL (H¢FF4F) and H¢FF4D, respectively. Bit Bit Name Initial Value R/W Description 7 NDR7 0 R/W Next Data Register 7 to 0 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Rev. 1.00 Sep. 19, 2008 Page 779 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) If pulse output groups 0 and 1 have different output triggers, upper 4 bits and lower 4 bits are mapped to the different addresses as shown below. Bit Bit Name Initial Value R/W Description 7 NDR7 0 R/W Next Data Register 7 to 4 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. 3 to 0 — All 1 — Reserved 1 is always read and write is disabled. Bit Bit Name Initial Value R/W Description 7 to 4 — All 1 — Reserved 1 is always read and write is disabled. 3 NDR3 0 R/W Next Data Register 3 to 0 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. Rev. 1.00 Sep. 19, 2008 Page 780 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.3.4 PPG Output Control Register (PCR) PCR selects output trigger signals on a group-by-group basis. For details on output trigger selection, refer to section 12.3.5, PPG Output Mode Register (PMR). Bit Bit Name Initial Value R/W Description 7 G3CMS1 1 R/W Group 3 Compare Match Select 1 and 0 6 G3CMS0 1 R/W Select output trigger of pulse output group 3. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 5 G2CMS1 1 R/W Group 2 Compare Match Select 1 and 0 4 G2CMS0 1 R/W Select output trigger of pulse output group 2. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 3 G1CMS1 1 R/W Group 1 Compare Match Select 1 and 0 2 G1CMS0 1 R/W Select output trigger of pulse output group 1. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 1 G0CMS1 1 R/W Group 0 Compare Match Select 1 and 0 0 G0CMS0 1 R/W Select output trigger of pulse output group 0. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 Rev. 1.00 Sep. 19, 2008 Page 781 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.3.5 PPG Output Mode Register (PMR) PMR selects the pulse output mode of the PPG for each group. If inverted output is selected, a low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0. If non-overlapping operation is selected, PPG updates its output values at compare match A or B of the TPU that becomes the output trigger. For details, refer to section 12.4.4, Non-Overlapping Pulse Output. Bit Bit Name Initial Value R/W Description 7 G3INV 1 R/W Group 3 Inversion Selects direct output or inverted output for pulse output group 3. 0: Inverted output 1: Direct output 6 G2INV 1 R/W Group 2 Inversion Selects direct output or inverted output for pulse output group 2. 0: Inverted output 1: Direct output 5 G1INV 1 R/W Group 1 Inversion Selects direct output or inverted output for pulse output group 1. 0: Inverted output 1: Direct output 4 G0INV 1 R/W Group 0 Inversion Selects direct output or inverted output for pulse output group 0. 0: Inverted output 1: Direct output Rev. 1.00 Sep. 19, 2008 Page 782 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) Bit Bit Name Initial Value R/W Description 3 G3NOV 0 R/W Group 3 Non-Overlap Selects normal or non-overlapping operation for pulse output group 3. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) 2 G2NOV 0 R/W Group 2 Non-Overlap Selects normal or non-overlapping operation for pulse output group 2. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) 1 G1NOV 0 R/W Group 1 Non-Overlap Selects normal or non-overlapping operation for pulse output group 1. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) 0 G0NOV 0 R/W Group 0 Non-Overlap Selects normal or non-overlapping operation for pulse output group 0. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) Rev. 1.00 Sep. 19, 2008 Page 783 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.4 Operation Figure 12.2 shows an overview diagram of the PPG. PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. Sequential output of data of up to 16 bits is possible by writing new output data to NDR before the next compare match. DDR NDER Q Output trigger signal C Q PODR D Q NDR D Pulse output pin Normal output/inverted output Figure 12.2 Overview Diagram of PPG Rev. 1.00 Sep. 19, 2008 Page 784 of 1270 REJ09B0466-0100 Internal data bus Section 12 Programmable Pulse Generator (PPG) 12.4.1 Output Timing If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 12.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. φ N TCNT TGRA N+1 N Compare match A signal n NDRH PODRH PO8 to PO15 m n m n Figure 12.3 Timing of Transfer and Output of NDR Contents (Example) Rev. 1.00 Sep. 19, 2008 Page 785 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.4.2 Sample Setup Procedure for Normal Pulse Output Figure 12.4 shows a sample procedure for setting up normal pulse output. Normal PPG output Select TGR functions [1] Set TGRA value [2] Set counting operation [3] Select interrupt request [4] Set initial output data [5] Enable pulse output [6] Select output trigger [7] [1] Set TIOR to make TGRA an output compare register (with output disabled). [2] Set the PPG output trigger period. TPU setup Port and PPG setup TPU setup Set next pulse output data [8] Start counter [9] Compare match? No [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR2 to CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the output trigger in PCR. [8] Set the next pulse output values in NDR. Yes Set next pulse output data [10] [9] Set the CST bit in TSTR to 1 to start the TCNT counter. [10] At each TGIA interrupt, set the next output values in NDR. Figure 12.4 Setup Procedure for Normal Pulse Output (Example) Rev. 1.00 Sep. 19, 2008 Page 786 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output) Figure 12.5 shows an example in which pulse output is used for cyclic five-phase pulse output. TCNT value Compare match TCNT TGRA H'0000 Time 80 NDRH PODRH 00 C0 80 40 C0 60 40 20 60 30 20 10 30 18 10 08 18 88 08 80 88 C0 80 40 C0 PO15 PO14 PO13 PO12 PO11 Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output) 1. Set up TGRA in TPU which is used as the output trigger to be an output compare register. Set a cycle in TGRA so that the counter will be cleared by compare match A. Set the TGIEA bit in TIER to 1 to enable the compare match/input capture A (TGIA) interrupt. 2. Write H'F8 in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Write output data H'80 in NDRH. 3. The timer counter in the TPU channel starts. When compare match A occurs, the NDRH contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the next output data (H'C0) in NDRH. 4. Five-phase pulse output (one or two phases active at a time) can be obtained subsequently by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive TGIA interrupts. If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained without imposing a load on the CPU. Rev. 1.00 Sep. 19, 2008 Page 787 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.4.4 Non-Overlapping Pulse Output During non-overlapping operation, transfer from NDR to PODR is performed as follows: • NDR bits are always transferred to PODR bits at compare match A. • At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 12.6 illustrates the non-overlapping pulse output operation. DDR NDER Q Compare match A Compare match B C Q PODR D Pulse output pin Q NDR D Internal data bus Normal output/inverted output Figure 12.6 Non-Overlapping Pulse Output Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the TGIA interrupt activate the DTC or DMAC. Note, however, that the next data must be written before the next compare match B occurs. Rev. 1.00 Sep. 19, 2008 Page 788 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) Figure 12.7 shows the timing of this operation. Compare match A Compare match B Write to NDR Write to NDR NDR PODR 0 output 0/1 output Write to NDR Do not write here to NDR here 0 output 0/1 output Do not write to NDR here Write to NDR here Figure 12.7 Non-Overlapping Operation and NDR Write Timing Rev. 1.00 Sep. 19, 2008 Page 789 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output Figure 12.8 shows a sample procedure for setting up non-overlapping pulse output. Non-overlapping pulse output Select TGR functions [1] Set TGR values [2] Set counting operation [3] Select interrupt request [4] Set initial output data [5] Enable pulse output [6] Select output trigger [7] Set non-overlapping groups [8] Set next pulse output data [9] Start counter [10] TPU setup PPG setup TPU setup Compare match A? [2] Set the pulse output trigger period in TGRB and the non-overlap period in TGRA. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR2 to CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the pulse output trigger in PCR. No [8] In PMR, select the groups that will operate in non-overlap mode. Yes Set next pulse output data [1] Set TIOR to make TGRA and TGRB an output compare registers (with output disabled). [11] [9] Set the next pulse output values in NDR. [10] Set the CST bit in TSTR to 1 to start the TCNT counter. [11] At each TGIA interrupt, set the next output values in NDR. Figure 12.8 Setup Procedure for Non-Overlapping Pulse Output (Example) Rev. 1.00 Sep. 19, 2008 Page 790 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) Figure 12.9 shows an example in which pulse output is used for four-phase complementary nonoverlapping pulse output. TCNT value TGRB TCNT TGRA H'0000 NDRH PODRH Time 65 95 00 95 59 05 65 56 41 59 95 50 56 65 14 95 05 65 Non-overlap margin PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary) Rev. 1.00 Sep. 19, 2008 Page 791 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt. 2. Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output. Write output data H'95 in NDRH. 3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs, outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt handling routine writes the next output data (H'65) in NDRH. 4. Four-phase complementary non-overlapping pulse output can be obtained subsequently by writing H'59, H'56, H'95... at successive TGIA interrupts. If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained without imposing a load on the CPU. Rev. 1.00 Sep. 19, 2008 Page 792 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.4.7 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 12.10 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 12.9. TCNT value TGRB TCNT TGRA H'0000 NDRH PODRL Time 65 95 00 95 59 05 65 56 41 59 95 50 56 65 14 95 05 65 PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 12.10 Inverted Pulse Output (Example) Rev. 1.00 Sep. 19, 2008 Page 793 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.4.8 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 12.11 shows the timing of this output. φ TIOC pin Input capture signal NDR N PODR M PO M N N Figure 12.11 Pulse Output Triggered by Input Capture (Example) Rev. 1.00 Sep. 19, 2008 Page 794 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.5 Usage Notes 12.5.1 Module Stop Mode Setting PPG operation can be disabled or enabled using the module stop control register. The initial value is for PPG operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 24, Power-Down Modes. 12.5.2 Operation of Pulse Output Pins Pins PO0 to PO15 are also used for other peripheral functions such as the TPU. When output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins. Pin functions should be changed only under conditions in which the output trigger event will not occur. Rev. 1.00 Sep. 19, 2008 Page 795 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) Rev. 1.00 Sep. 19, 2008 Page 796 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) Section 13 8-Bit Timers (TMR) This LSI has an on-chip 8-bit timer module with two channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used to count external events and be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers. 13.1 Features • Selection of seven clock sources The counters can be driven by one of six internal clock signals (φ/8, φ/64, φ/8192, φ/2, φ/32, or φ/1024) or an external clock input • Selection of three ways to clear the counters The counters can be cleared on compare match A or B, or by an external reset signal • Timer output control by a combination of two compare match signals The timer output signal in each channel is controlled by a combination of two independent compare match signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or PWM output • Provision for cascading of two channels (TMR_0 and TMR_1) Operation as a 16-bit timer is possible, using TMR_0 for the upper 8 bits and TMR_1 for the lower 8 bits (16-bit count mode) TMR_1 can be used to count TMR_0 compare matches (compare match count mode) • Three independent interrupts Compare match A and B and overflow interrupts can be requested independently • A/D converter conversion start trigger can be generated Figure 13.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1). Rev. 1.00 Sep. 19, 2008 Page 797 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) Internal clock sources φ/8 φ/64 φ/8192 φ/2 φ/32 φ/1024 Clock select Compare match A1 Compare match A0 Overflow 1 Overflow 0 TMO0 TMRI0 TCORA_0 TCORA_1 Comparator A_0 Comparator A_1 TCNT_0 TCNT_1 Comparator B_0 Comparator B_1 TCORB_0 TCORB_1 TCSR_0 TCSR_1 TCR_0 TCR_1 TCCR_0 TCCR_1 Channel 0 (TMR_0) Channel 1 (TMR_1) Counter clear 0 Counter clear 1 TMO1 TMRI1 Control logic Compare match B1 Compare match B0 A/D conversion start request signal CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Interrupt signals Legend: TCORA_0 TCNT_0 TCORB_0 TCSR_0 TCR_0 TCCR_0 : Time constant register A_0 : Timer counter_0 : Time constant register B_0 : Timer control/status register_0 : Timer control register_0 : Timer counter control register_0 TCORA_1 TCNT_1 TCORB_1 TCSR_1 TCR_1 TCCR_1 : Time constant register A_1 : Timer counter_1 : Time constant register B_1 : Timer control/status register_1 : Timer control register_1 : Timer counter control register_1 Figure 13.1 Block Diagram of 8-Bit Timer Module Rev. 1.00 Sep. 19, 2008 Page 798 of 1270 REJ09B0466-0100 Internal bus TMCI0 TMCI1 Counter clock 1 Counter clock 0 Section 13 8-Bit Timers (TMR) 13.2 Input/Output Pins Table 13.1 shows the pin configuration of the 8-bit timer module. Table 13.1 Pin Configuration Channel 0 1 13.3 Name Symbol I/O Function Timer output pin TMO0 Output Outputs at compare match Timer clock input pin TMCI0 Input Inputs external clock for counter Timer reset input pin TMRI0 Input Inputs external reset to counter Timer output pin TMO1 Output Outputs at compare match Timer clock input pin TMCI1 Input Inputs external clock for counter Timer reset input pin TMRI1 Input Inputs external reset to counter Register Descriptions The 8-bit timer module has the following registers. For details on the module stop control register, refer to section 24.1.2, Module Stop Control Registers H and L (MSTPCRH, MSTPCRL). • • • • • • • • • • • • Timer counter_0 (TCNT_0) Time constant register A_0 (TCORA_0) Time constant register B_0 (TCORB_0) Timer control register_0 (TCR_0) Timer control/status register_0 (TCSR_0) Timer counter control register_0 (TCCR_0) Timer counter_1 (TCNT_1) Time constant register A_1 (TCORA_1) Time constant register B_1 (TCORB_1) Timer control register_1 (TCR_1) Timer control/status register_1 (TCSR_1) Timer counter control register_1 (TCCR_1) Rev. 1.00 Sep. 19, 2008 Page 799 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) 13.3.1 Timer Counter (TCNT) TCNT is 8-bit up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. Bits CKS2 to CKS0 in TCR are used to select a clock. TCNT can be cleared by an external reset input or by a compare match signal A or B. Which signal is to be used for clearing is selected by bits CCLR1 and CCLR0 in TCR. When TCNT overflows from H'FF to H'00, OVF in TCSR is set to 1. TCNT is initialized to H'00. 13.3.2 Time Constant Register A (TCORA) TCORA is 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. The value in TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding CMFA flag in TCSR is set to 1. Note, however, that comparison is disabled during the T2 state of a TCORA write cycle. The timer output from the TMO pin can be freely controlled by this compare match signal (compare match A) and the settings of bits OS1 and OS0 in TCSR. TCORA is initialized to H'FF. 13.3.3 Time Constant Register B (TCORB) TCORB is 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding CMFB flag in TCSR is set to 1. Note, however, that comparison is disabled during the T2 state of a TCOBR write cycle. The timer output from the TMO pin can be freely controlled by this compare match signal (compare match B) and the settings of bits OS3 and OS2 in TCSR. TCORB is initialized to H'FF. Rev. 1.00 Sep. 19, 2008 Page 800 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) 13.3.4 Timer Control Register (TCR) TCR selects the clock source and the time at which TCNT is cleared, and controls interrupts. Bit Bit Name Initial Value R/W Description 7 CMIEB 0 R/W Compare Match Interrupt Enable B Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag in TCSR is set to 1. 0: CMFB interrupt requests (CMIB) are disabled 1: CMFB interrupt requests (CMIB) are enabled 6 CMIEA 0 R/W Compare Match Interrupt Enable A Selects whether CMFA interrupt requests (CMIA) are enabled or disabled when the CMFA flag in TCSR is set to 1. 0: CMFA interrupt requests (CMIA) are disabled 1: CMFA interrupt requests (CMIA) are enabled 5 OVIE 0 R/W Timer Overflow Interrupt Enable Selects whether OVF interrupt requests (OVI) are enabled or disabled when the OVF flag in TCSR is set to 1. 0: OVF interrupt requests (OVI) are disabled 1: OVF interrupt requests (OVI) are enabled 4 CCLR1 0 R/W Counter Clear 1 and 0 3 CCLR0 0 R/W These bits select the method by which TCNT is cleared, in combination with the TMRIS bit in TCCR. See table 13.2. 2 CKS2 0 R/W Clock Select 2 to 0 1 CKS1 0 R/W 0 CKS0 0 R/W These bits select the clock input to TCNT and the count condition, in combination with the ICKS1 and ICKS0 bits in TCCR. See table 13.3. Rev. 1.00 Sep. 19, 2008 Page 801 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) 13.3.5 Timer Counter Control Register (TCCR) TCCR selects the TCNT internal clock source and controls the external reset input. Bit Bit Name Initial Value R/W Description 7 to 4 — All 0 R Reserved These bits are always read as 0 and cannot be modified. 3 TMRIS 0 R/W Timer Reset Input Select Selects the external reset input, in combination with the CCLR1 and CCLR0 bits in TCR. See table 13.2. 2 — 0 R Reserved This bit is always read as 0 and cannot be modified. 1 ICKS1 0 R/W Internal Clock Select 1, 0 0 ICKS0 0 R/W These bits select the internal clock source, in combination with the CKS2 to CKS0 bits in TCR. See table 13.3. Table 13.2 Reset Input to TCNT and Clearing Condition TCR TCCR Bit 1 CCLR1 Bit 0 CCLR0 Bit 3 TMRIS Description 0 0 0 Clearing is disabled 0 1 0 Clear by compare match A 1 0 0 Clear by compare match B 1 1 0 Clear by rising edge of external reset input 0 0 1 Clear by both rising and falling edges of external reset input 0 1 1 Clear by falling edge of external reset input 1 0 1 Clear by low level of external reset input 1 1 1 Clear by high level of external reset input Rev. 1.00 Sep. 19, 2008 Page 802 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) Table 13.3 Clock Input to TCNT and Count Condition TCR TCCR Channel Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Bit 1 ICKS1 Bit 0 ICKS0 Description TMR_0 0 0 0 Clock input disabled 0 0 1 0 0 Internal clock, counted at rising edge of φ/8 0 1 Internal clock, counted at rising edge of φ/2 1 0 Internal clock, counted at falling edge of φ/8 1 1 Internal clock, counted at falling edge of φ/2 0 0 Internal clock, counted at rising edge of φ/64 0 1 Internal clock, counted at rising edge of φ/32 1 0 Internal clock, counted at falling edge of φ/64 1 1 Internal clock, counted at falling edge of φ/32 0 0 Internal clock, counted at rising edge of φ/8192 0 1 Internal clock, counted at rising edge of φ/1024 1 0 Internal clock, counted at falling edge of φ/8192 1 1 Internal clock, counted at falling edge of φ/1024 Counted at TCNT_1 overflow signal* 0 0 1 TMR_1 1 1 0 0 1 0 0 0 0 Clock input disabled 0 0 1 0 0 Internal clock, counted at rising edge of φ/8 0 1 Internal clock, counted at rising edge of φ/2 1 0 Internal clock, counted at falling edge of φ/8 1 1 Internal clock, counted at falling edge of φ/2 0 0 Internal clock, counted at rising edge of φ/64 0 1 Internal clock, counted at rising edge of φ/32 1 0 Internal clock, counted at falling edge of φ/64 0 0 1 1 1 0 0 1 0 1 1 Internal clock, counted at falling edge of φ/32 0 0 Internal clock, counted at rising edge of φ/8192 0 1 Internal clock, counted at rising edge of φ/1024 1 0 Internal clock, counted at falling edge of φ/8192 1 1 Internal clock, counted at falling edge of φ/1024 Counted at TCNT_0 compare match A* Rev. 1.00 Sep. 19, 2008 Page 803 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) TCR TCCR Channel Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Bit 1 ICKS1 Bit 0 ICKS0 Description All 1 0 1 External clock, counted at rising edge 1 0 External clock, counted at falling edge 1 1 External clock, counted at both rising and falling edges Note: 13.3.6 * If the count input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the TCNT_0 compare match signal, no incrementing clock is generated. Do not use this setting. Timer Control/Status Register (TCSR) TCSR displays status flags, and controls compare match output. • TCSR_0 Bit Bit Name Initial Value R/W Description 7 CMFB 0 R/(W)* Compare Match Flag B [Setting condition] • Set when TCNT matches TCORB [Clearing conditions] 6 CMFA 0 R/(W)* • Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB • When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 Compare Match Flag A [Setting condition] • Set when TCNT matches TCORA [Clearing conditions] Rev. 1.00 Sep. 19, 2008 Page 804 of 1270 REJ09B0466-0100 • Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA • When DTC is activated by CMIA interrupt while DISEL bit of MRB in DTC is 0 Section 13 8-Bit Timers (TMR) Bit Bit Name Initial Value R/W Description 5 OVF 0 R/(W)* Timer Overflow Flag [Setting condition] Set when TCNT overflows from H'FF to H'00 [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 to OVF 4 ADTE 0 R/W A/D Trigger Enable Selects enabling or disabling of A/D converter start requests by compare match A. 0: A/D converter start requests by compare match A are disabled 1: A/D converter start requests by compare match A are enabled 3 OS3 0 R/W Output Select 3 and 2 2 OS2 0 R/W These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs. 00: No change when compare match B occurs 01: 0 is output when compare match B occurs 10: 1 is output when compare match B occurs 11: Output is inverted when compare match B occurs (toggle output) 1 OS1 0 R/W Output Select 1 and 0 0 OS0 0 R/W These bits select a method of TMO pin output when compare match A of TCORA and TCNT occurs. 00: No change when compare match A occurs 01: 0 is output when compare match A occurs 10: 1 is output when compare match A occurs 11: Output is inverted when compare match A occurs (toggle output) Note: Only 0 can be written to, to clear these flags. Rev. 1.00 Sep. 19, 2008 Page 805 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) • TCSR_1 Bit Bit Name Initial Value R/W Description 7 CMFB 0 R/(W)* Compare Match Flag B [Setting condition] • Set when TCNT matches TCORB [Clearing conditions] 6 CMFA 0 R/(W)* • Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB • When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 Compare Match Flag A [Setting condition] • Set when TCNT matches TCORA [Clearing conditions] 5 OVF 0 R/(W)* • Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA • When DTC is activated by CMIA interrupt while DISEL bit of MRB in DTC is 0 Timer Overflow Flag [Setting condition] • Set when TCNT overflows from H'FF to H'00 [Clearing condition] • 4 — 1 R Cleared by reading OVF when OVF = 1, then writing 0 to OVF Reserved This bit is always read as 1 and cannot be modified. Rev. 1.00 Sep. 19, 2008 Page 806 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) Bit Bit Name Initial Value R/W Description 3 OS3 0 R/W Output Select 3 and 2 2 OS2 0