TI1 OPA207 Low-power, high-precision, low-noise, rail-to-rail output operational amplifier Datasheet

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OPA207
SBOS826 – DECEMBER 2017
OPA207 Low-Power, High-Precision, Low-Noise, Rail-to-Rail Output
Operational Amplifier
1 Features
3 Description
•
•
•
•
•
•
The OPA207 precision operational amplifier (op amp)
replaces the industry standard OP-07, OP-77 and
OP–177 amplifiers. The OPA207 offers improved
noise, wider output voltage swing, and is twice as fast
with half the quiescent current of the industry
standard alternatives. Features include ultra-low input
offset voltage and drift, low input bias current, high
common-mode rejection ratio, and high power supply
rejection ratio.
1
•
•
•
•
•
Ultra-Low Offset Voltage: 150 μV (Maximum)
Ultra-Low Drift: ±1 μV/°C (Maximum)
Gain Bandwidth: 1 MHz (Typical)
Slew Rate: 3.6 V/μs (Typical)
High Open-Loop Gain: 130 dB (Minimum)
High Common-Mode Rejection: 115 dB
(Minimum)
High Power-Supply Rejection: 5µV/V (Maximum)
Low Bias Current: 2.8 nA (Maximum)
Wide Supply Range: ±2.25 V to ±18 V
Low Quiescent Current: 375 μA (Maximum)
Replaces OP-07, OP-77, and OP-177
2 Applications
•
•
•
•
•
•
•
Factory Automation and Control - Analog I/O
Test and Measurement - Battery Testers
Data Acquisition - Transducer Amplifiers
Bridge Amplifiers
Temperature Measurements
Strain Gage Amplifiers
Battery-Powered Instruments
The OPA207 op amp operates over a wide powersupply-voltage range, from ±2.25 V to ±18 V, with
excellent performance. High performance is
maintained as the amplifiers swing to their specified
limits.
The OPA207 operational amplifier is easy to use and
free from phase inversion and the overload problems
found in some other operational amplifiers. The
OPA207 is stable in unity gain and provide excellent
dynamic behavior over a wide range of load
conditions.
Device Information(1)
PART NUMBER
OPA207
PACKAGE
SOIC (8)
BODY SIZE (NOM)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
space
space
Input Referred Voltage Noise (100 nV/div)
Ultra-Low 0.1-Hz to 10-Hz Noise
Time (1 s/div)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA207
SBOS826 – DECEMBER 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
8
8.1 Application Information............................................ 20
8.2 Typical Application ................................................. 20
8.3 Other Applications .................................................. 21
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 24
11 Device and Documentation Support ................. 25
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description ............................................ 13
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Application and Implementation ........................ 20
13
13
13
19
Device Support ....................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
25
25
25
25
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
2
DATE
REVISION
NOTES
December 2017
*
Initial release
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5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
NC
—
2
–In
I
No internal connection (can be left floating or connected to ground)
Inverting input
3
+In
I
Non-inverting input
4
V–
—
Negative (lowest) power supply
5
NC
—
No internal connection (can be left floating or connected to ground)
6
OUT
O
Output
7
V+
—
Positive (highest) power supply
8
NC
—
No internal connection (can be left floating or connected to ground)
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
36
V
(V–) -0.7
(V+) +0.7
V
–1
1
V
Supply voltage, Vs = (V+) – (V–)
Input voltage - Common-mode
(2)
Input voltage - Differential
Output short-circuit (3)
Continuous
Operating temperature
–55
125
°C
Specified temperature
–40
125
°C
150
°C
150
°C
Junction temperature
Storage temperature, Tstg
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input current must be limited to 10 mA.
Short circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vs = (V+) – (V–)
Specified temperature
MIN
NOM
MAX
4.5 (±2.25)
30 (±15)
36 (±18)
V
+125
°C
–40
UNIT
6.4 Thermal Information
OPA207
THERMAL METRIC (1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
121.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
64.3
°C/W
RθJB
Junction-to-board thermal resistance
65.0
°C/W
ψJT
Junction-to-top characterization parameter
18.2
°C/W
ψJB
Junction-to-board characterization parameter
64.3
°C/W
(1)
4
For more information about traditional and new thermal metrics, seethe Semiconductor and IC Package ThermalMetrics application
report.
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6.5 Electrical Characteristics
at VS = ±15 V, TA = 25°C, RL = 2 kΩ connected to VS / 2, VCM = VS / 2, and VO UT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
15
±100
μV
±150
µV
OFFSET VOLTAGE
VOS
Input offset voltage
TA = –40°C to 85°C
TA = –40°C to 125°C
dVOS/dT
PSRR
Input offset voltage drift
Input offset voltage versus
power supply
±200
µV
TA = –40°C to 85°C
±0.2
±.8
μV/°C
TA = –40°C to 125°C
±0.2
±.8
μV/°C
VS = ±2.25 V to ±18 V
±0.5
±3
μV/V
±4.2
μV/V
±5
μV/V
VS = ±2.25 V to ±18 V, TA = –40°C to 85°C
VS = ±2.25 V to ±18 V, TA = –40°C to 125°C
INPUT BIAS CURRENT
±0.2
IB
Input bias current
±1.5
nA
TA = –40°C to 85°C
±2
nA
TA = –40°C to 125°C
±7
nA
±1.5
nA
TA = –40°C to 85°C
±2
nA
TA = –40°C to 125°C
±7
nA
±0.13
IOS
Input offset current
NOISE
Input voltage noise
eN
Input voltage noise density
iN
Input current noise
f = 0.1 Hz to 10 Hz
0.16
μVPP
0.024
µVRMS
f = 1 Hz
9.5
f = 10 Hz
7.5
f = 100 Hz
7.5
f = 1 kHz
7.5
f = 1 kHz
0.18
nV/√Hz
pA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage
range
CMRR
Common-mode rejection
ratio
(V–) + 1.25
(V+) – 1.25
V
(V–) + 1.25 V < VCM < (V+) – 1.25 V
120
140
dB
(V–) + 1.25 V < VCM < (V+) – 1.25 V, TA = –40°C to
125°C
115
140
dB
INPUT CAPACITANCE
ZID
Differential
ZICM
Common-mode
3 || 14
MΩ || pF
1 || 1
GΩ || pF
140
dB
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 200 mV < VO <
(V+) – 200 mV, RL = 10 kΩ TA = –40°C to 125°C
130
(V–) + 200 mV < VO <
(V+) – 200 mV, RL = 2 kΩ
120
TA = –40°C to 125°C
126
dB
140
114
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Electrical Characteristics (continued)
at VS = ±15 V, TA = 25°C, RL = 2 kΩ connected to VS / 2, VCM = VS / 2, and VO UT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
tS
1.3
MHz
10-V step, G = 1
2.7
V/μs
To 0.1%, 10-V step , G = 1
4.8
μs
To 0.01%, 10-V step , G = 1
5.4
μs
To 0.001%, 10-V step , G = 1
8.1
μs
Overload recovery time
VIN × gain > VS
1.1
μs
Total harmonic distortion +
noise (THD+N)
VO = 3 VRMS, G = 1, f = 1 kHz, RL = 10 kΩ
–114
dB
Settling time
OUTPUT
Voltage output swing from
rail
ISC
Short-circuit current
CLOAD
Capacitive load drive
RO
Open-loop output
impedance
TA = 25°C, no load
15
30
mV
TA = 25°C, RL = 10 kΩ
40
50
mV
TA = 25°C, RL = 2 kΩ
80
125
mV
TA = –40°C to 125°C, RL = 10 kΩ
75
200
mV
Sinking
Sourcing
f = 1 MHz
–40
mA
40
mA
200
pf
45
Ω
POWER SUPPLY
VS
IQ
Specified voltage range
Single supply
Dual supply
Quiescent current per
amplifier
IO = 0 A
Turnon time
At TA = 25°C, VS = 36 V, VS ramp rate > 0.3 V/µs
4.5
36
±2.25
±18
V
375
μA
450
μA
350
IO = 0 A, TA = –40°C to 125°C
27
V
μs
TEMPERATURE
6
Specified range
–40
125
°C
Operating range
–40
150
°C
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6.6 Typical Characteristics
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
25
20
15
Amplifiers (%)
15
10
10
5
5
1
0.9
Input Offset Voltage Drift (µV/ƒC)
Offset Voltage (µV)
C001
C002
Figure 1. Input Referred Offset Voltage Distribution
140
300
120
Gain
Phase 250
Figure 2. Input Referred Offset Voltage Drift Distribution
30
G= +1
G= –1
G= +11
200
80
150
60
100
40
50
20
0
Phase (°)
100
Gain (dB)
20
Gain (dB)
0.8
0.7
0.6
0.5
0.4
0.3
0
100
60
20
-20
-60
-100
0.2
0
0
0.1
Amplifiers (%)
20
10
0
-10
0
-50
-20
100m
1
10
100
1k
10k
Frequency (Hz)
100k
1M
-20
100
-100
10M
Figure 3. Open-Loop Gain and Phase vs Frequency
10k
100k
Frequency (Hz)
1M
10M
Figure 4. Closed Loop Gain vs Frequency
140
100
PSRR–
PSRR+
CMRR
120
80
70
60
100
Impedance (:)
Rejection Ratio (dB)
1k
80
60
40
50
40
30
20
20
0
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
10
100
Figure 5. Power Supply Rejection Ratio and Common-Mode
Rejection Ratio vs Frequency
1k
10k
100k
Frequency (Hz)
1M
10M
Open
Figure 6. Open-Loop Output Impedance vs Frequency
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
40
Output Voltage (VPP)
35
30
25
20
15
10
5
Voltage Noise Density (nV/—Hz)
20
Vs=±18 V
Vs=±15 V
Vs=±2.25 V
15
10
5
0
1
10
100
1k
10k
Frequency (Hz)
100k
1M
0
100m
1
10
100
1k
Frequency (Hz)
100k
1M
OPA2
Figure 8. Input Voltage Noise Spectral Density vs Frequency
Figure 7. Full Power Bandwidth
Current Noise Density (pA/√Hz)
Input Referred Voltage Noise (100 nV/div)
10
1
0.1
100m
1
10
Time (1 s/div)
G = –1 V/V, RL = 2 kΩ
G = –1 V/V, RL = 10 kΩ
0.05 0.1
G = 1 V/V, RL = 2 kΩ
G = 1 V/V, RL = 10 kΩ
0.20.3 0.5 1
2 3 4 5 7 10
Output Amplitude (VPP)
Total Harmonic Distortion + Noise (dB)
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-115
-120
-125
0.02
100
1k
Frequency (Hz)
10k
100k
Figure 10. Input Current Noise vs Frequency
Figure 9. 0.1-Hz to 10-Hz Noise Voltage
Total Harmonic Distortion + Noise (dB)
10k
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-115
-120
-125
20 30 50
G = –1 V/V, RL = 2 kΩ
G = –1 V/V, RL = 10 kΩ
20
50
100
200
G = 1 V/V, RL = 2 kΩ
G = 1 V/V, RL = 10 kΩ
500 1k
2k
Frequency (Hz)
5k
10k 20k
VOUT = 3 VRMS
Figure 11. Total Harmonic Distortion + Noise vs Output
Amplitude
8
Figure 12. Total Harmonic Distortion + Noise vs Frequency
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
80
40
RISO = 0 Ω
RISO = 25 Ω
RISO = 50 Ω
60
30
Overshoot (%)
Overshoot (%)
RISO = 0 :
RISO = 25 :
RISO = 50 :
35
40
25
20
15
20
10
5
0
20
30 40 50
70 100
200 300
Capacitive Load (pF)
500 700 1000
0
20
30 40 50
G = +1 V/V
70 100
200 300
Capacitive Load (pF)
500 700 1000
OPA2
G = –1 V/V
Figure 14. Overshoot vs Capacitive Load
Figure 13. Overshoot vs Capacitive Load
Vin
Cload = 10 pF
Cload = 100 pF
Cload = 200 pF
Cload = 400 pF
Voltage (5 V/div)
Voltage (5 mV/div)
Vin
Cload = 10 pF
Cload = 100 pF
Cload = 200 pF
Cload = 400 pF
Time (1 Ps/div)
Time (2 Ps/div)
Smal
Larg
G = +1 V/V
G = +1 V/V
Figure 15. Small-Signal Step Response
Voltage (5 V/div)
Voltage (5 mV/div)
Figure 16. Large-Signal Step Response
Vin
Cload = 10 pF
Cload = 100 pF
Cload = 200 pF
Vin
Cload = 10 pF
Cload = 400 pF
Time (1 Ps/div)
Cload = 100 pF
Cload = 200 pF
Cload = 400 pF
Time (2 Ps/div)
Smal
G = –1 V/V
Larg
G = –1 V/V
Figure 17. Small-Signal Step Response
Figure 18. Large-Signal Step Response
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
Voltage (5 V/div)
Voltage (5 V/div)
VOUT
VIN
VOUT
VIN
Time (2 Ps/div)
Time (2 Ps/div)
Figure 19. Overload Recovery From Positive Overload
Figure 20. Overload Recovery from Negative Overload
Vin (V)
Vout (V)
Voltage (5 V/div)
Output (1 mV/div)
Rising
Falling
Time (5 Ps/div)
Time (100 ms/div)
Sett
VOUT = 3 VRMS
VOUT = 3 VRMS
Figure 22. No Phase Reversal
Figure 21. Settling Time
2
60
1
VCM = 13.75 V
VCM = ± 13.75 V
Input Bias Current (nA)
Input-referred Offset Voltage ( V)
80
40
20
0
±20
±40
0
±1
±1
±2
±60
±80
±2
±15
±10
±5
0
5
Input Common-mode Voltage (V)
10
15
±20
±15
±10
±5
0
5
10
Input Common-mode Voltage (V)
C003
Figure 23. Input Offset Voltage vs Input Common-mode
Voltage
10
1
15
20
C001
Figure 24. Input Bias Current vs Input Common-mode
Voltage
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
400
Input-referred Offset Voltage ( V)
100.0
Quiescent Current ( A)
350
300
250
200
VS = 4.5 V
150
100
50
0
75.0
50.0
25.0
0.0
±25.0
±50.0
VS = 4.5 V
±75.0
±100.0
0
9
18
27
36
Supply Voltage (V)
0
9
18
Figure 25. Quiescent Current vs Power Supply Voltage
27
36
Supply Voltage (V)
C001
C001
Figure 26. Input Offset Voltage vs Power Supply Voltage
15
-10
±40°C
14
-11
13
-12
125°C
VO (V)
VO (V)
125°C
25°C
12
85°C
-13
25°C
85°C
11
-14
±40°C
-15
10
0
5
10
15
20
25
30
35
40
45
0
50
5
10
15
20
25
30
35
40
45
IO (mA)
C001
50
C001
Figure 27. Output Voltage vs Output Current (Sourcing)
Figure 28. Output Voltage vs Output Current (Sinking)
100
2.0
75
1.0
Input Current (nA)
Input-referred Offset Voltage ( V)
IO (mA)
50
25
IBP
IBN
IOS
0.0
±1.0
0
±2.0
±3.0
±25
±50
±4.0
±75
±5.0
±6.0
±100
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±75
Figure 29. Input Offset Voltage vs Temperature
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C001
150
C001
Figure 30. Input Bias Current vs Temperature
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
180
0.001
Common-Mode Rejection Ratio (dB)
Open-loop Gain (dB)
150
VS = ± 18 V
140
0.1
Open-loop Gain (µV/V)
0.01
130
VS = ± 2.25 V
120
±25
0
25
50
75
100
150
0.1
130
120
Quiescent Current ( A)
Power Supply Rejection Ratio (dB)
0.01
140
100
125
50
75
100 125 150
C001
400
VS = ± 18 V
VS = ± 2.25 V
350
300
250
1
75
25
450
Power Supply Rejection Ratio (µV/V)
160
50
1
0
Figure 32. Common-Mode Rejection Ratio vs Temperature
170
25
130
Temperature (ƒC)
0.001
0
0.1
±75 ±50 ±25
Figure 31. Open Loop Gain vs Temperature
±25
140
C001
180
±50
150
125
Temperature (ƒC)
±75
0.01
160
120
1
±50
170
Common-mode Rejection Ratio (µV/V)
170
160
0.001
180
±75
150
Temperature (ƒC)
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C001
150
C001
Figure 34. Quiescent Current vs Temperature
Figure 33. Power Supply Rejection Ratio vs Temperature
Short Circuit Current (mA)
45
Sinking
40
35
Sourcing
30
25
±75
±50
±25
0
25
50
75
Temperature (ƒC)
100
125
150
C001
Figure 35. Output Short Circuit Current vs Temperature
12
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7 Detailed Description
7.1 Overview
The OPA207 precision operational amplifier replaces the industry standard OP-177. The OPA207 offers
improved noise, wider output voltage swing, has twice the bandwidth, ten times the slew rate and consumes only
half the quiescent current as the OP-177. Additional features include ultralow offset voltage and drift, low bias
current, high common-mode rejection, and high power supply rejection.
7.2 Functional Block Diagram
V+
+IN
gm1
_
gm3
gm2
OUT
IN
V_
Copyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
The OPA207 is unity-gain stable and free from unexpected output phase reversal, making it easy to use in a
wide range of applications. Applications with noisy or high-impedance power supplies may require decoupling
capacitors close to the device pins. In most cases 0.1-μF capacitors are adequate.
7.3.1 Operating Voltage
The OPA207 operates from ±2.25 V to ±18 V supplies with excellent performance. Key parameters are assured
over the specified temperature range, –40°C to 125°C. Most behavior remains unchanged through the full
operating voltage range (±2.25 V to ±18 V). Parameters which vary significantly with operating voltage or
temperature are shown in Typical Characteristics.
7.3.2 Input Protection
The input stage of the OPA207 is internally protected with resistors in series with diode clamps as shown in
Figure 36. The inputs can withstand ±10 V differential inputs without damage and the maximum input current
should be limited to 10 mA or less.. The protection diodes conduct current when the inputs are over-driven such
as when the opamp output is slewing. This may disturb the slewing behavior of unity-gain follower applications,
but will not damage the operational amplifier.
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Feature Description (continued)
500
+IN
+
OUT
±
-IN
500
Copyright © 2017, Texas Instruments Incorporated
Figure 36. Simplified OPA207 Input Protection Circuit
7.3.3 ESD Protection
The OPA207 is internally protected against ESD events that can occur during manufacturing, handling, or
printed-circuit-board assembly. The internal ESD protection diodes are not intended to protect the OPA207
during normal operation when the device is operating under power. In cases where the inputs or output can be
driven above the positive power supply or below the negative power supply care must be taken to limit the
current through the internal diodes to 10 mA or less. In harsh electrical environments external protection circuitry
may be required and is dependant upon the application requirements and environmental conditions.
V+
+IN
+
-IN
±
OUT
VCopyright © 2017, Texas Instruments Incorporated
Figure 37. Simplified OPA207 ESD Protection Circuit
7.3.4 Input Stage Linearization
The OPA207 uses linearization techniques to reduce the total harmonic distortion. Figure 38 illustrates the
linearization concept, and Figure 38 illustrates the total harmonic distortion performance of the OPA207.
14
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Feature Description (continued)
-IN
+IN
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Total Harmonic Distortion + Noise (dB)
Figure 38. Simplified Input Stage Linearization Circuit
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-115
-120
-125
G = –1 V/V, RL = 2 kΩ
G = –1 V/V, RL = 10 kΩ
20
50
100
200
G = 1 V/V, RL = 2 kΩ
G = 1 V/V, RL = 10 kΩ
500 1k
2k
Frequency (Hz)
5k
10k 20k
Figure 39. Total Harmonic Distortion
7.3.5 Rail-to-Rail Output
The OPA207 uses a rail-to-rail output stage capable of swinging within a few millivolts from either power supply
rail while maintaining high open-loop gain. Figure 40 shows a simplified drawing of the output stage circuit.
Resistors connected in series with each output transistor ensure a consistent output current limit. Limiting the
output current in this way ensures reliable operation of the OPA207 under short circuited conditions and protects
sensitive loads from being damaged by excessive current. Figure 41 and Figure 42 illustrate the maximum output
current available from the OPA207 at various temperatures.
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Feature Description (continued)
V+
OUT
VCopyright © 2017, Texas Instruments Incorporated
Figure 40. Simplified Rail-to-Rail Output Stage Circuit
15
±40°C
VO (V)
14
13
125°C
25°C
12
85°C
11
10
0
5
10
15
20
25
30
35
IO (mA)
40
45
50
C001
Figure 41. Output Swing to Rail While Sourcing Current
16
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Feature Description (continued)
-10
-11
VO (V)
125°C
-12
85°C
-13
25°C
-14
±40°C
-15
0
5
10
15
20
25
30
35
40
45
IO (mA)
50
C001
Figure 42. Output Swing to Rail While Sinking Current
7.3.6 Low Input Bias Current
The OPA207 uses super-beta bipolar transistors and employs an input bias current cancellation technique. This
combination results in very low input bias currents that remain low over the full specified temperature range from
–40°C to + 125°C unlike CMOS or JFET amplifiers whose input bias currents typically double every 10°C and
can be extremely high at 125°C. Figure 43 illustrates the comparison between the OPA207 and typical CMOS or
JFET amplifiers.
6000
Input Bias Current (pA)
5000
OPA207
Typical CMOS/JFET
4000
3000
2000
1000
0
-1000
-50
-25
0
25
50
Temperature (qC)
75
100
125
OPA2
Figure 43. Input Bias Current vs Temperature
It is common practice to place a bias current cancellation resistor as illustrated in Figure 42. This approach works
well with amplifiers that do not employ an internal input bias current cancellation technique. Because the
OPA207 uses an internal bias current cancellation technique, TI does not recommend the bias cancellation
resistor.
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Feature Description (continued)
R2
R1
IBN
±
+
+
IBN ~ IBP = IB
IBN ± IBP = IOS << IB
IBP
±
Bias Current Cancellation Resistor = R1//R2
Not recommended
GND
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 44. Bias Current Cancellation Resistor — Not Recommended
7.3.7 Slew Boost
The OPA207 uses a novel internal slew-boost technique. This method allows the OPA207 to consume very low
power yet still achieve a high slew rate of 3.6 V/µs. This makes the OPA207 ideal for applications that require
low noise and high out voltage swings where the high slew rate is necessary to achieve fast settling times.
40
Vs=±18 V
Vs=±15 V
Vs=±2.25 V
Output Voltage (VPP)
35
30
25
20
15
10
5
0
1
10
100
1k
10k
Frequency (Hz)
100k
1M
Figure 45. Full Power Bandwidth
7.3.8 EMI Rejection Ratio (EMIRR)
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many operational amplifiers is a change in the offset voltage as a
result of RF signal rectification. An operational amplifier that is more efficient at rejecting this change in offset as
a result of EMI has a higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in
many ways, but this report provides the EMIRR IN+, which specifically describes the EMIRR performance when
the RF signal is applied to the noninverting input pin of the operational amplifier. In general, only the noninverting
input is tested for EMIRR for the following three reasons:
1. Operational amplifier input pins are known to be the most sensitive to EMI, and typically rectify RF signals
better than the supply or output pins.
2. The noninverting and inverting operational amplifier inputs have symmetrical physical layouts and exhibit
nearly matching EMIRR performance.
3. EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input terminal
can be isolated on a printed circuit board (PCB). This isolation allows the RF signal to be applied directly to
the noninverting input terminal with no complex interactions from other components or connecting PCB
traces.
A more formal discussion of the EMIRR IN+ definition and test method is provided in TI Application Report EMI
Rejection Ratio of Operational Amplifiers, available for download at www.ti.com. The EMIRR IN+ of the OPA207
is plotted versus frequency as shown in Figure 46.
18
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Feature Description (continued)
120
EMIRR IN+ (dB)
100
80
60
40
20
10M
100M
1G
Frequency (Hz)
10G
Figure 46. OPA207 EMIRR IN+ vs Frequency
If available, any dual and quad operational amplifier device versions have nearly similar EMIRR IN+
performance. The OPA207 unity-gain bandwidth is 1 MHz. EMIRR performance below this frequency denotes
interfering signals that fall within the operational amplifier bandwidth.
Table 1 shows the EMIRR IN+ values for the OPA207 at particular frequencies commonly encountered in realworld applications. Applications listed in Table 1 may be centered on or operated near the particular frequency
shown. This information may be of special interest to designers working with these types of applications, or
working in other fields likely to encounter RF interference from broad sources, such as the industrial, scientific,
and medical (ISM) radio band.
Table 1. OPA207 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION/ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite/space operation, weather, radar, UHF
72 dB
900 MHz
GSM, radio com/nav./GPS (to 1.6 GHz), ISM, aeronautical mobile, UHF
83 dB
1.8 GHz
GSM, mobile personal comm. broadband, satellite, L-band
95 dB
®
2.4 GHz
802.11b/g/n, Bluetooth , mobile personal comm., ISM, amateur
radio/satellite, S-band
94 dB
3.6 GHz
Radiolocation, aero comm./nav., satellite, mobile, S-band
103 dB
5 GHz
802.11a/n, aero comm./nav., mobile comm., space/satellite operation, Cband
102 dB
7.4 Device Functional Modes
The OPA207 has a single functional mode and is operational when the power-supply voltage is greater than 4.5
V (± 2.25 V). The maximum power supply voltage for the OPA207 is 36 V (±18 V).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Low-pass filters are commonly employed in signal processing applications to reduce noise and prevent aliasing.
The OPA207 is designed to construct high-precision active filters. Figure 47 shows a second-order, low-pass
filter commonly encountered in signal processing applications.
8.2 Typical Application
R4
2.94 k
C5
1 nF
R1
590
R3
499
Input
±
Output
+
C2
39 nF
Copyright © 2016, Texas Instruments Incorporated
Figure 47. Typical OPA207 Application Schematic
8.2.1 Design Requirements
Use the following parameters for this design example:
• Gain = 5 V/V (inverting gain)
• Low-pass cutoff frequency = 25 kHz
• Second-order Chebyshev filter response with 3-dB gain peaking in the passband
8.2.2 Detailed Design Procedure
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in Figure 47. Use Equation 1
to calculate the voltage transfer function.
-1/ R1R3C2C5
Output
(s) = 2
Input
s + (s / C2 )(1/ R1 + 1/ R3 + 1/ R 4 ) + 1/ R3R 4C2C5
(1)
This circuit produces a signal inversion. For this circuit, the gain at dc and the low-pass cutoff frequency are
calculated by Equation 2:
R
Gain = 4
R1
fc =
1
(1/ R3R 4C2C5 )
2p
(2)
Software tools are readily available to simplify filter design. WEBENCH® Filter Designer is a simple, powerful,
and easy-to-use active filter design program. The WEBENCH Filter Designer lets designers create optimized
filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows to
design, optimize, and simulate complete multi-stage active filter solutions within minutes.
20
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Typical Application (continued)
8.2.3 Application Curve
20
Gain (db)
0
-20
-40
-60
100
1k
10k
Frequency (Hz)
100k
1M
Figure 48. Low-Pass Filter Transfer Function
8.3 Other Applications
8.3.1 Precision Low-Side Current Sensing
With low offset voltage and low offset voltage drift over time and temperature the OPA207 is works well for
precision low-side current sensing applications as shown in Figure 49
Load
VOUT = (ISHUNT x RSHUNT) x (1 + RF/RG)
+
±
+
Load
Current
OUT
RSHUNT
RG
GND
±
RF
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 49. Precision Low-Side Current Sensing
8.3.2 Precision Buffer With Increased Output Current
The OPA207 can be configured as illustrated in Figure 50 to drive low impedance loads. In Figure 50, the
OPA207 is configured in a gain of +10 V/V, and the output current is boosted by the NPN (2N2904) and PNP
(2N2906) bipolar transistors. For low output voltages the OPA207 supplies the load current directly through the
100-Ω resistor. The bipolar transistors begin to supply current when the voltage drop across the 100-Ω resistor
exceeds approximately 500 mV. Figure 50 illustrates the results for a 50-Ω load resistor driven with a 10-V step
at the output. This results in a 200-mA current supplied by the circuit.
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Other Applications (continued)
V+
VIN
100Ÿ
+
VOUT
±
Load
V1NŸ
9NŸ
GND
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 50. Precision Buffer (G = 10 V/V) With High Output Drive Capability
RLOAD = 50 :
Output (2.5 V/Div)
Load current = 200 mA
Time (7.5 Ps/Div)
Prec
Figure 51. 50-Ω Load Driven With a 10-V Step
22
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9 Power Supply Recommendations
The OPA207 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 36 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
Guidelines.
10 Layout
10.1 Layout Guidelines
The OPA207 series has low offset voltage and drift. To achieve highest performance, optimize the circuit layout
and mechanical conditions. Offset voltage and drift can be degraded by small thermoelectric potentials at the op
amp inputs. Connections of dissimilar metals generate thermal potential, which can degrade the ultimate
performance of the OPA207. These thermal potentials can be made to cancel by assuring that they are equal in
both input terminals.
• Keep the thermal mass of the connections to the two input terminals similar.
• Locate heat sources as far as possible from the critical input circuitry.
• Shield operational amplifier and input circuitry from air currents, such as cooling fans.
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1–µF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
• Place the external components as close as possible to the device. As shown in Layout Example, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• For best performance, TI recommends cleaning the PCB following board assembly.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, TI recommends baking the PCB assembly to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, postcleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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10.2 Layout Example
RF
C1
V+
RG
±
INPUT
OUTPUT
+
C2
V-
V+
INPUT
RG
RF
1
1
2
OUTPUT
2
1
8
2
7
3
6
4
5
2
1
2
C2
1
C1
Ground
plane
VCopyright © 2017, Texas Instruments Incorporated
Figure 52. OPA207 Layout Example for the Inverting Configuration
24
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Webench Filter Designer Tool
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
11.1.1.2 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.3 TI Precision Designs
The OPA207 is featured in several TI Precision Designs, available online at
http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s
precision analog applications experts and offer the theory of operation, component selection, simulation,
complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• EMI Rejection Ratio of Operational Amplifiers
• Circuit Board Layout Techniques, SLOA089
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
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11.5 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc..
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Dec-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA207ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA207
OPA207IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA207
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Dec-2017
Addendum-Page 2
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