Sample & Buy Product Folder Support & Community Tools & Software Technical Documents Reference Design LP5907-Q1 SNVSA34A – SEPTEMBER 2014 – REVISED JUNE 2016 LP5907-Q1 250-mA Ultra-Low-Noise LDO for RF and Analog Circuits - Requires No Bypass Capacitor 1 Features 3 Description • • The LP5907-Q1 is an LDO capable of supplying 250mA output current. Designed to meet the requirements of RF and analog circuits, the LP5907Q1 device provides low noise, high PSRR, low quiescent current, and low line or load transient response figures. Using new innovative design techniques, the LP5907-Q1 offers class-leading noise performance without a noise bypass capacitor and the ability for remote output capacitor placement. 1 • • • • • • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to +125°C Input Voltage Range: 2.2 V to 5.5 V Output Voltage Range: 1.2 V to 4.5 V Stable with 1-µF Ceramic Input and Output Capacitors No Noise Bypass Capacitor Required Remote Output Capacitor Placement Thermal-Overload and Short-Circuit Protection Output Current: 250 mA Low Output Voltage Noise: < 10 µVRMS PSRR: 82 dB at 1 kHz Output Voltage Tolerance: ±2% Virtually Zero IQ (Disabled): < 1 µA Very Low IQ (Enabled): 12 µA Start-up Time: 80 µs Low Dropout: 120 mV (typical) –40°C to 125°C Junction Temperature Range for Operation The device is designed to work with a 1-µF input and a 1-µF output ceramic capacitor (no separate noise bypass capacitor is required). This device is available with fixed output voltages from 1.2 V to 4.5 V in 25-mV steps. Contact Texas Instruments Sales for specific voltage option needs. Device Information(1) PART NUMBER PACKAGE LP5907-Q1 SOT-23 (5) BODY SIZE (NOM) 2.90 mm × 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • • • Infotainment Instrumentation Body Electronics Simplified Schematic INPUT IN 1 PF ENABLE OUT LP5907-Q1 OUTPUT 1 PF EN GND GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP5907-Q1 SNVSA34A – SEPTEMBER 2014 – REVISED JUNE 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 4 4 4 4 5 6 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Output and Input Capacitors ..................................... Typical Characteristics .............................................. Detailed Description ............................................ 10 8.1 Overview ................................................................. 10 8.2 Functional Block Diagram ....................................... 10 8.3 Feature Description................................................. 10 8.4 Device Functional Modes........................................ 11 9 Applications and Implementation ...................... 12 9.1 Application Information............................................ 12 9.2 Typical Application .................................................. 12 10 Power Supply Recommendations ..................... 15 11 Layout................................................................... 15 11.1 Layout Guidelines ................................................. 15 11.2 Layout Example .................................................... 15 12 Device and Documentation Support ................. 16 12.1 12.2 12.3 12.4 12.5 Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 16 16 16 16 16 13 Mechanical, Packaging, and Orderable Information ........................................................... 16 4 Revision History Changes from Original (September 2014) to Revision A Page • Added Features bullets re: automotive .................................................................................................................................. 1 • Added top navigator icon for TI Designs ................................................................................................................................ 1 • Changed " linear regulator" to "LDO" ..................................................................................................................................... 1 • Changed storage temperature from Handling Ratings to Abs Max table; replaced Handling Ratings with ESD Ratings per new format ......................................................................................................................................................... 4 2 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LP5907-Q1 LP5907-Q1 www.ti.com SNVSA34A – SEPTEMBER 2014 – REVISED JUNE 2016 5 Device Comparison Table SOT-23 PACKAGE ORDER NUMBER VOLTAGE OPTION (V) LP5907QMFX-1.2Q1 1.2 LP5907QMFX-1.8Q1 1.8 LP5907QMFX-2.5Q1 2.5 LP5907QMFX-2.8Q1 2.8 LP5907QMFX-3.0Q1 3.0 LP5907QMFX-3.3Q1 3.3 LP5907QMFX-3.8Q1 3.8 LP5907QMFX-4.5Q1 4.5 6 Pin Configuration and Functions DBV Package 5-Pin SOT-23 (Top View) IN 1 GND 2 EN 3 5 OUT 4 N/C Pin Functions PIN NUMBER NAME I/O DESCRIPTION 1 IN I Input voltage supply. Connect a 1-µF capacitor at this input. 2 GND – Common ground 3 EN I Enable input. A low voltage (< VIL) on this pin turns the regulator off and discharges the output pin to GND through an internal 230-Ω pulldown resistor. A high voltage (> VIH) on this pin enables the regulator output. This pin has an internal 1-MΩ pulldown resistor to hold the regulator off by default. 4 N/C – No internal electrical connection. 5 OUT O Regulated output voltage. A minimum 1-µF low-ESR capacitor should be connected to this pin. Connect this output to the load circuit. An internal 230-Ω (typical) pulldown resistor prevents a charge remaining on VOUT when the regulator is in the shutdown mode (VEN low). Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LP5907-Q1 3 LP5907-Q1 SNVSA34A – SEPTEMBER 2014 – REVISED JUNE 2016 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX VIN Input voltage –0.3 6 VOUT Output voltage –0.3 See VEN Enable input voltage –0.3 6 Continuous power dissipation (4) TJMAX Junction temperature Tstg Storage temperature (1) (2) (3) (4) UNIT (3) V Internally Limited W –65 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the GND pin. Abs Max VOUT is the lessor of VIN + 0.3 V, or 6 V. Internal thermal shutdown circuitry protects the device from permanent damage. 7.2 ESD Ratings VALUE Human-body model (HBM), per AEC Q100-002 (1) V(ESD) (1) Electrostatic discharge Charged-device model (CDM), per AEC Q100-011 All pins ±2000 Corner pins (1,3,4,5) ±1000 Other pin (2) ±1000 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT VIN Input supply voltage 2.2 5.5 VEN Enable input voltage 0 5.5 IOUT Output current 0 250 mA –40 125 °C TJ-MAX-OP (1) (2) (3) Operating junction temperature (3) V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the GND pin. TJ-MAX-OP = (TA(MAX) + (PD(MAX) × RθJA )). 7.4 Thermal Information (1) THERMAL METRIC (2) SOT-23 (DBV) 5 PINS UNIT RθJA Junction-to-ambient thermal resistance 193.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 102.1 °C/W RθJB Junction-to-board thermal resistance 45.8 °C/W ψJT Junction-to-top characterization parameter 8.4 °C/W ψJB Junction-to-board characterization parameter 45.3 °C/W (1) (2) 4 Thermal performance is based on the JEDEC standard: JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LP5907-Q1 LP5907-Q1 www.ti.com SNVSA34A – SEPTEMBER 2014 – REVISED JUNE 2016 7.5 Electrical Characteristics VIN = VOUT(NOM) + 1 V, VEN = 1.2 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, unless otherwise stated (1) (2) (3). PARAMETER VIN Input voltage Output voltage tolerance ΔVOUT ILOAD TEST CONDITIONS MIN 2.2 5.5 VIN = (VOUT(NOM) + 1 V) to 5.5 V, IOUT = 1 mA to 250 mA, VOUT ≥ 1.8 V –2 2 VIN = (VOUT(NOM) + 1 V) to 5.5 V, IOUT = 1 mA to 250 mA, VOUT < 1.8 V –3 3 VIN = (VOUT(NOM) + 1 V) to 5.5 V, IOUT = 1 mA Load regulation IOUT = 1 mA to 250 mA Output load current IG Ground current (5) VDO Dropout voltage (6) ISC Short circuit current limit PSRR Power supply rejection ratio (8) V 0.02 %/V 0.001 %/mA 0 250 12 25 VEN = 1.2 V, IOUT = 250 mA 250 425 VEN = 0.3 V (Disabled) 0.2 1 VEN = 1.2 V, IOUT = 0 mA 14 IOUT = 100 mA 50 IOUT = 250 mA mA µA µA mV 250 TA = 25°C (7) 250 500 f = 100 Hz, IOUT = 20 mA 90 f = 1 kHz, IOUT = 20 mA 82 f = 10 kHz, IOUT = 20 mA 65 f = 100 kHz, IOUT = 20 mA mA dB 60 IOUT = 1 mA 10 IOUT = 250 mA 6.5 eN Output noise voltage (8) BW = 10 Hz to 100 kHz RAD Output automatic discharge pulldown resistance VEN < VIL (output disabled) 230 Thermal shutdown TJ rising 160 Thermal hysteresis TJ falling from shutdown TSD UNIT %VOUT VEN = 1.2 V, IOUT = 0 mA Quiescent current (4) MAX TA = 25°C Line regulation IQ TYP µVRMS Ω °C 15 LOGIC INPUT THRESHOLDS VIL Low input threshold VIN = 2.2 V to 5.5 V VEN falling until the output is disabled VIH High input threshold VIN = 2.2 V to 5.5 V VEN rising until the output is enabled IEN Input current at EN pin (9) (1) (2) (3) (4) (5) (6) (7) (8) (9) VEN = 5.5 V and VIN = 5.5 V VEN = 0 V and VIN = 5.5 V 0.4 1.2 V V 5.5 0.001 µA All voltages are with respect to the device GND terminal, unless otherwise stated. Minimum and maximum limits are ensured through test, design, or statistical correlation over the junction temperature (TJ) range of –40°C to 125°C, unless otherwise stated. Typical values represent the most likely parametric norm at TA = 25°C, and are provided for reference purposes only. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX). See Applications and Implementation. Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT. Ground current is defined here as the total current flowing to ground as a result of all input voltages applied to the device. Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value. Short-circuit current (ISC) for the LP5907-Q1 is equivalent to current limit. To minimize thermal effects during testing, ISC is measured with VOUT pulled to 100 mV below its nominal voltage. This specification is verified by design. There is a 1-MΩ resistor between EN and ground on the device. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LP5907-Q1 5 LP5907-Q1 SNVSA34A – SEPTEMBER 2014 – REVISED JUNE 2016 www.ti.com Electrical Characteristics (continued) VIN = VOUT(NOM) + 1 V, VEN = 1.2 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, unless otherwise stated(1)(2)(3). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TRANSIENT CHARACTERISTICS Line transient VIN = (VOUT(NOM) + 1 V) to (VOUT(NOM) + 1.6 V) in 30 µs (8) mV VIN = (VOUT(NOM) + 1.6 V) to (VOUT(NOM) + 1.6 V) in 30 µs ΔVOUT 1 IOUT = 1 mA to 250 mA in 10 µs Load transient (8) tON –1 –40 IOUT = 250 mA to 1mA in 10 µs mV 40 Overshoot on start-up (8) Stated as a percentage of VOUT(NOM) Turnon time From VEN > VIH to VOUT = 95% of VOUT(NOM) TA = 25°C 5% 80 150 µs 7.6 Output and Input Capacitors over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS (2) CIN Input capacitance COUT Output capacitance (2) ESR Output/Input capacitance (2) (1) (2) Capacitance for stability MIN (1) TYP 0.7 1 0.7 1 MAX 10 5 500 UNIT µF mΩ The minimum capacitance should be greater than 0.5 μF over the full range of operating conditions. The capacitor tolerance should be 30% or better over the full temperature range. The full range of operating conditions for the capacitor in the application should be considered during device selection to ensure this minimum capacitance specification is met. X7R capacitors are recommended however capacitor types X5R, Y5V and Z5U may be used with consideration of the application and conditions. This specification is verified by design. 7.7 Typical Characteristics Unless otherwise stated: VIN = 3.7 V, VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TA = 25°C 1 16 14 0.9 10 VEN (V) IQ( A) 12 8 6 0.8 0.7 4 0.6 2 VIH Rising VIL Falling 0 2.3 2.8 3.3 3.8 4.3 VIN(V) 4.8 5.3 5.8 0.5 2 2.5 SVA-30180569 Figure 1. Quiescent Current vs Input Voltage 6 Submit Documentation Feedback 3 3.5 4 VIN (V) 4.5 5 5.5 6 D001 Figure 2. VEN Thresholds vs VIN Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LP5907-Q1 LP5907-Q1 www.ti.com SNVSA34A – SEPTEMBER 2014 – REVISED JUNE 2016 Typical Characteristics (continued) Unless otherwise stated: VIN = 3.7 V, VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TA = 25°C 5 1.4 4.5 1.2 4 3.5 VOUT (V) VOUT (V) 1 0.8 0.6 3 2.5 2 1.5 0.4 1 0.2 RLOAD = 1.2 k: RLOAD = 4.8 : RLOAD = 4.5 k: RLOAD = 18 : 0.5 0 0 0 0.5 1 1.5 2 2.5 VIN (V) VOUT = 1.2V 0 1 2 D002 VEN = VIN VOUT = 4.5V 4 5 6 D003 VEN = VIN Figure 3. VOUT vs VIN Figure 4. VOUT vs VIN 350 2.900 300 2.875 250 2.850 VIN= 3.6V 2.825 VOUT(V) GROUND CURRENT ( A) 3 VIN (V) 200 2.800 150 2.775 100 2.750 VIN = 3.0V VIN = 3.8V VIN = 4.2V VIN = 5.5V 50 0 0 50 100 150 200 IOUT(mA) 250 -40°C 90°C 25°C 2.725 2.700 300 0 50 100 150 LOAD (mA) 200 250 SVA-30180567 SVA-30180571 Figure 6. Load Regulation Figure 5. Ground Current vs Output Current 2.900 2V/DIV Load = 10 mA 2.875 VOUT 2.850 2V/DIV VOUT(V) 2.825 2.800 VIN = VEN 2.775 2.750 -40°C 90°C 25°C 2.725 2.700 3.0 1A/DIV IIN 2 ms/DIV 3.5 4.0 4.5 VIN(V) 5.0 5.5 SVA-30180568 Figure 7. Line Regulation SVA-30180509 Figure 8. Inrush Current Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LP5907-Q1 7 LP5907-Q1 SNVSA34A – SEPTEMBER 2014 – REVISED JUNE 2016 www.ti.com Typical Characteristics (continued) Unless otherwise stated: VIN = 3.7 V, VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TA = 25°C VOUT (AC Coupled) 10 mV/ DIV VOUT (AC Coupled) 10 mV/ DIV VIN 1V/DIV VIN 1V/DIV 10 s/DIV 10 s/DIV SVA-30180510 VIN = 3.2 V ↔ 4.2 V Load = 1 mA SVA-30180511 VIN = 3.2 V ↔ 4.2 V Load = 250 mA Figure 10. Line Transient Figure 9. Line Transient VOUT 100 mV/DIV VOUT 100 mV/DIV LOAD 200 mA/DIV LOAD 200 mA/DIV 100 s/DIV 100 s/DIV SVA-30180512 Load = 0 mA ↔ 250 mA -40°C SVA-30180513 Load = 0 mA ↔ 250 mA 90°C Figure 12. Load Transient Figure 11. Load Transient 1V/DIV 100 mV/DIV VOUT VOUT LOAD 1V/DIV 200 mA/DIV EN 100 s/DIV 20 s/DIV SVA-30180515 SVA-30180514 Load = 0 mA ↔ 250 mA 0 mA 25°C Figure 14. Start-Up Figure 13. Load Transient 8 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LP5907-Q1 LP5907-Q1 www.ti.com SNVSA34A – SEPTEMBER 2014 – REVISED JUNE 2016 Typical Characteristics (continued) Unless otherwise stated: VIN = 3.7 V, VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TA = 25°C 1V/DIV VOUT 1V/DIV EN 20 s/DIV SVA-30180516 250 mA Figure 15. Start-Up Figure 16. Noise Density Test 0 120 250 mA 200 mA 150 mA 100 mA 50 mA 20 mA -20 100 -40 PSRR (dB) DROPOUT VOLTAGE (mV) 140 80 60 40 -60 -80 Dropout Voltage 20 -100 0 0 50 100 150 200 LOAD CURRENT (mA) -120 0.1 250 1 10 FREQUENCY (kHz) SVA-30180573 Figure 17. Dropout Voltage vs Load Current 100 D004 Figure 18. PSRR Loads Averaged 100 Hz To 100 KHz 0 -20 PSRR (dB) -40 -60 250 mA 200 mA 150 mA 100 mA 50 mA 20 mA -80 -100 -120 0.01 0.1 1 10 100 FREQUENCY (kHz) 1000 10000 D005 Figure 19. PSRR Loads Averaged 10 Hz To 10 MHz Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LP5907-Q1 9 LP5907-Q1 SNVSA34A – SEPTEMBER 2014 – REVISED JUNE 2016 www.ti.com 8 Detailed Description 8.1 Overview Designed to meet the needs of sensitive RF and analog circuits, the LP5907-Q1 provides low noise, high PSRR, low quiescent current, as well as low line and load transient response figures. Using new innovative design techniques, the LP5907-Q1 offers class leading noise performance without the need for a separate noise filter capacitor. The LP5907-Q1 is designed to perform with a single 1-µF input capacitor and a single 1-µF ceramic output capacitor. With a reasonable PCB layout, the single 1-µF ceramic output capacitor can be placed up to 10 cm away from the LP5907-Q1 package. 8.2 Functional Block Diagram OUT IN POR EN EN + RF CF + VBG 1.20V RAD EN + EN EN 1M VIH GND Copyright © 2016, Texas Instruments Incorporated 8.3 Feature Description 8.3.1 Enable (EN) The LP5907-Q1 EN pin is internally held low by a 1-MΩ resistor to GND. The EN pin voltage must be higher than the VIH threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage must be lower than the VIL threshold to ensure that the device is fully disabled and the automatic output discharge is activated. 8.3.2 Low Output Noise Any internal noise at the LP5907-Q1 reference voltage is reduced by a first order low-pass RC filter before it is passed to the output buffer stage. The low-pass RC filter has a –3 dB cut-off frequency of approximately 0.1 Hz. 10 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LP5907-Q1 LP5907-Q1 www.ti.com SNVSA34A – SEPTEMBER 2014 – REVISED JUNE 2016 Feature Description (continued) 8.3.3 Output Automatic Discharge The LP5907-Q1 output employs an internal 230-Ω (typical) pulldown resistance to discharge the output when the EN pin is low, and the device is disabled. 8.3.4 Remote Output Capacitor Placement The LP5907-Q1 requires at least a 1-µF capacitor at the OUT pin, but there are no strict requirements about the location of the capacitor in regards the OUT pin. In practical designs, the output capacitor may be located up to 10 cm away from the LDO. 8.3.5 Thermal Overload Protection (TSD) Thermal shutdown disables the output when the junction temperature rises to approximately 160°C which allows the device to cool. When the junction temperature cools to approximately 145°C, the output circuitry enables. Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a result of overheating. The thermal shutdown circuitry of the LP5907-Q1 has been designed to protect against temporary thermal overload conditions. The thermal shutdown circuitry was not intended to replace proper heat-sinking. Continuously running the LP5907-Q1 device into thermal shutdown may degrade device reliability. 8.4 Device Functional Modes 8.4.1 Enable (EN) The LP5907-Q1 Enable (EN) pin is internally held low by a 1-MΩ resistor to GND. The EN pin voltage must be higher than the VIH threshold to ensure that the device is fully enabled under all operating conditions. When the EN pin is pulled low, and the output is disabled, the output automatic discharge circuitry is activated. Any charge on the OUT pin is discharged to GND through the internal 230-Ω (typical) pull-down resistance. 8.4.2 Minimum Operating Input Voltage (VIN) The LP5907-Q1 does not include any dedicated undervoltage lockout circuitry. The LP5907-Q1 internal circuitry is not fully functional until VIN is at least 2.2 V. The output voltage is not regulated until VIN has reached at least the greater of 2.2 V or (VOUT + VDO). Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LP5907-Q1 11 LP5907-Q1 SNVSA34A – SEPTEMBER 2014 – REVISED JUNE 2016 www.ti.com 9 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information Figure 20 shows the typical application circuit for the LP5907-Q1. Input and output capacitances may need to be increased above the 1 µF minimum for some applications. 9.2 Typical Application INPUT IN 1 PF ENABLE OUT LP5907-Q1 OUTPUT 1 PF EN GND GND Figure 20. LP5907-Q1 Typical Application 9.2.1 Design Requirements DESIGN PARAMETER EXAMPLE VALUE Input voltage range 2.2 to 5.5 V Output voltage 1.8 V Output current 200 mA Output capacitor range 0.7 to 10 µF Input/output capacitor ESR range 5 to 500 mΩ 9.2.2 Detailed Design Procedure To • • • • begin the design process, determine the following: Available input voltage range Output voltage needed Output current needed Input and Output capacitors 9.2.2.1 Power Dissipation and Device Operation The permissible power dissipation for any package is a measure of the capability of the device to pass heat from the power source, the junctions of the device, to the ultimate heat sink, the ambient environment. Thus, the power dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces between the die junction and ambient air. The maximum allowable power dissipation for the device in a given package can be calculated using Equation 1: 12 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LP5907-Q1 LP5907-Q1 www.ti.com SNVSA34A – SEPTEMBER 2014 – REVISED JUNE 2016 PD-MAX = ((TJ-MAX – TA) / RθJA) (1) The actual power being dissipated in the device can be represented by Equation 2: PD = (VIN - VOUT) × IOUT (2) Equation 1 and Equation 2 establish the relationship between the maximum power dissipation allowed due to thermal consideration, the voltage drop across the device, and the continuous current capability of the device. These two equations should be used to determine the optimum operating conditions for the device in the application. In applications where lower power dissipation (PD) and/or excellent package thermal resistance (RθJA) is present, the maximum ambient temperature (TA-MAX) may be increased. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature (TA-MAX) may have to be derated. TA-MAX is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum allowable power dissipation in the device package in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA), as given by Equation 3: TA-MAX = (TJ-MAX-OP – (RθJA × PD-MAX)) (3) Alternately, if TA-MAX can not be derated, the PD value must be reduced. This can be accomplished by reducing VIN in the VIN – VOUT term as long as the minimum VIN is met, or by reducing the IOUT term, or by some combination of the two. 9.2.2.2 External Capacitors Like most LDOs, the LP5907-Q1 requires external capacitors for regulator stability. The device is specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. 9.2.2.3 Input Capacitor An input capacitor is required for stability. The input capacitor should be at least equal to, or greater than, the output capacitor for good load transient performance. At least a 1-µF capacitor has to be connected between the LP5907-Q1 input pin and ground for stable operation over full load current range. Basically, it is acceptable to have more output capacitance than input, as long as the input is at least 1 µF. The input capacitor must be located a distance of not more than 1 cm from the IN pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Important: To ensure stable operation it is essential that good PCB practices are employed to minimize ground impedance and keep input inductance low. If these conditions cannot be met, or if long leads are to be used to connect the battery or other power source to the LP5907-Q1, TI recommends increasing the input capacitor to at least 10 µF. Also, tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be verified by the manufacturer to have a surge current rating sufficient for the application. The initial tolerance, applied voltage de-rating, and temperature coefficient must all be considered when selecting the input capacitor to ensure the actual capacitance is never less than 0.7 µF over the entire operating range. 9.2.2.4 Output Capacitor The LP5907-Q1 is designed specifically to work with a very small ceramic output capacitor, typically 1 µF. A ceramic capacitor (dielectric types X5R or X7R) in the 1-µF to 10-µF range, and with equivalent series resistance (ESR) between 5 mΩ to 500 mΩ, is suitable in the LP5907-Q1 application circuit. For this device connect the output capacitor between the OUT pin and a good connection back to the GND pin. It may also be possible to use tantalum or film capacitors at the device output, VOUT, but these are not as attractive for reasons of size and cost (see Capacitor Characteristics). The output capacitor must meet the requirement for the minimum value of capacitance and have an ESR value that is within the range 5 mΩ to 500 mΩ for stability. Like the input capacitor, the initial tolerance, applied voltage de-rating, and temperature coefficient must all be considered when selecting the input capacitor to ensure the actual capacitance is never less than 0.7 µF over the entire operating range. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LP5907-Q1 13 LP5907-Q1 SNVSA34A – SEPTEMBER 2014 – REVISED JUNE 2016 www.ti.com 9.2.2.5 Capacitor Characteristics The LP5907-Q1 is designed to work with ceramic capacitors on the input and output to take advantage of the benefits they offer. For capacitance values in the range of 1 µF to 10 µF, ceramic capacitors are the smallest, least expensive, and have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for stability for the LP5907-Q1. A better choice for temperature coefficient in a ceramic capacitor is X7R. This type of capacitor is the most stable and holds the capacitance within ±15% over the temperature range. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 1 µF to 10 µF range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. The ESR of a typical tantalum increases about 2:1 as the temperature goes from 25°C down to –40°C, so some guard band must be allowed. 9.2.2.6 Remote Capacitor Operation The LP5907-Q1 requires at least a 1-µF capacitor at the OUT pin, but there are no strict requirements about the location of the capacitor in regards to the pin. In practical designs the output capacitor may be located up to 10 cm away from the LDO. This means that there is no need to have a special capacitor close to the output pin if there is already respective capacitors in the system (like a capacitor at the input of supplied part). The remote capacitor feature helps user to minimize the number of capacitors in the system. As a good design practice, keep the wiring parasitic inductance at a minimum, which means to use as wide as possible traces from the LDO output to the capacitors, keeping the LDO output trace layer as close as possible to ground layer and avoiding vias on the path. If there is a need to use vias, implement as many as possible vias between the connection layers. The recommendation is to keep parasitic wiring inductance less than 35 nH. For the applications with fast load transients, it is recommended to use an input capacitor equal to or larger to the sum of the capacitance at the output node for the best load transient performance. 9.2.2.7 No-Load Stability The LP5907-Q1 remains stable, and in regulation, with no external load. 9.2.2.8 Enable Control The LP5907-Q1 may be switched ON or OFF by a logic input at the EN pin. A voltage on this pin greater than VIH turns the device on, while a voltage less than VIL turns the device off. When the EN pin is low, the regulator output is off and the device typically consumes less than 1 µA. Additionally, an output pulldown circuit is activated which ensures that any charge stored on COUT is discharged to ground. If the application does not require the use of the shutdown feature, the EN pin can be tied directly to the IN pin to keep the regulator output permanently on. An internal 1-MΩ pulldown resistor ties the EN input to ground, ensuring that the device remains off if the EN pin is left open circuit. To ensure proper operation, the signal source used to drive the EN pin must be able to swing above and below the specified turnon or turnoff voltage thresholds listed in the Electrical Characteristics under VIL and VIH. 14 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LP5907-Q1 LP5907-Q1 www.ti.com SNVSA34A – SEPTEMBER 2014 – REVISED JUNE 2016 9.2.3 Application Curves 1V/DIV VOUT 100 mV/DIV LOAD 200 mA/DIV VOUT 1V/DIV EN 100 s/DIV 20 s/DIV SVA-30180514 SVA-30180515 Figure 22. Load Transient Response Figure 21. Start-Up 10 Power Supply Recommendations This device is designed to operate from an input supply voltage range of 2.2 V to 5.5 V. The input supply must be well regulated and free of spurious noise. To ensure that the LP5907-Q1 output voltage is well regulated and dynamic performance is optimum, the input supply must be at least VOUT + 1 V. A minimum capacitor value of 1 µF is required to be within 1 cm of the IN pin. 11 Layout 11.1 Layout Guidelines The dynamic performance of the LP5907-Q1 is dependant on the layout of the PCB. PCB layout practices that are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5907-Q1. Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5907-Q1, and as close as is practical to the package. The ground connections for CIN and COUT must be back to the LP5907-Q1 ground pin using as wide and short copper traces as are practical. Avoid connections using long trace lengths, narrow trace widths, and/or connections through vias. These add parasitic inductances and resistance that results in inferior performance especially during transient conditions 11.2 Layout Example VIN VOUT CIN 1 IN 2 GND 3 EN OUT 5 GND Enable COUT GND N/C 4 Figure 23. LP5907MF-x.x (SOT-23) Typical Layout Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LP5907-Q1 15 LP5907-Q1 SNVSA34A – SEPTEMBER 2014 – REVISED JUNE 2016 www.ti.com 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 16 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LP5907-Q1 PACKAGE OPTION ADDENDUM www.ti.com 22-Jun-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP5907QMFX-1.2Q1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 RAFQ LP5907QMFX-1.8Q1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 RAGQ LP5907QMFX-2.5Q1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 RAJQ LP5907QMFX-2.8Q1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 RAKQ LP5907QMFX-3.0Q1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 RALQ LP5907QMFX-3.3Q1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 RAHQ LP5907QMFX-3.8Q1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 RAMQ LP5907QMFX-4.5Q1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 RAIQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 22-Jun-2016 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LP5907-Q1 : • Catalog: LP5907 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 22-Jun-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LP5907QMFX-1.2Q1 SOT-23 DBV 5 3000 178.0 8.4 LP5907QMFX-1.8Q1 SOT-23 DBV 5 3000 178.0 LP5907QMFX-2.5Q1 SOT-23 DBV 5 3000 178.0 LP5907QMFX-2.8Q1 SOT-23 DBV 5 3000 LP5907QMFX-3.0Q1 SOT-23 DBV 5 LP5907QMFX-3.3Q1 SOT-23 DBV LP5907QMFX-3.8Q1 SOT-23 DBV LP5907QMFX-4.5Q1 SOT-23 DBV 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 22-Jun-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP5907QMFX-1.2Q1 SOT-23 DBV 5 3000 210.0 185.0 35.0 LP5907QMFX-1.8Q1 SOT-23 DBV 5 3000 210.0 185.0 35.0 LP5907QMFX-2.5Q1 SOT-23 DBV 5 3000 210.0 185.0 35.0 LP5907QMFX-2.8Q1 SOT-23 DBV 5 3000 210.0 185.0 35.0 LP5907QMFX-3.0Q1 SOT-23 DBV 5 3000 210.0 185.0 35.0 LP5907QMFX-3.3Q1 SOT-23 DBV 5 3000 210.0 185.0 35.0 LP5907QMFX-3.8Q1 SOT-23 DBV 5 3000 210.0 185.0 35.0 LP5907QMFX-4.5Q1 SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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