Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design LP3981 SNVS159H – OCTOBER 2001 – REVISED JULY 2015 LP3981 Micropower, 300-mA Ultra-Low-Dropout CMOS Voltage Regulator 1 Features 3 Description • • • • • Performance of the LP3981 device is optimized for battery-powered systems to deliver ultra-low-noise, extremely low dropout voltage, and low quiescent current. Regulator ground current increases only slightly in dropout, further prolonging the battery life. 1 • • • • • • 2.5-V to 6-V Input Range 300-mA Output Current 60-dB PSRR at 1 kHz ≤ 1-μA Quiescent Current When Shut Down Fast Turnon Time: 120 μs (typical) with CBYPASS = 0.01 µF 132-mV Typical Dropout with 300-mA Load 35-μVrms Output Noise Over 10 Hz to 100 kHz Logic Controlled Enable Stable With Ceramic and High-Quality Tantalum Capacitors Thermal Shutdown and Short-Circuit Current Limit Low Thermal Resistance in WSON-6 Package Gives Excellent Power Capability Power supply rejection is better than 60 dB at low frequencies. This high power supply rejection is maintained down to lower input voltage levels common to battery-operated circuits. The device is ideal for mobile phone and similar battery-powered wireless applications. It provides up to 300 mA, from a 2.5-V to 6-V input, consuming less than 1 µA in disable mode. The LP3981 is available in 8-pin VSSOP-8 and 6-pin WSON packages. Performance is specified for −40°C to +125°C temperature range. The device available in the following output voltages: 2.5 V, 2.7 V, 2.8 V, 2.83 V, 3 V, 3.03 V and 3.3 V as standard. Other output options can be made available; contact your local TI sales office for more information. 2 Applications • • • • CDMA Cellular Handsets Wideband CDMA Cellular Handsets GSM Cellular Handsets Portable Information Appliances Device Information(1) PART NUMBER LP3981 PACKAGE BODY SIZE (NOM) WSON (6) 4.00 mm x 3.00 mm VSSOP (8) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit 2(2) IN 2.2 µF OUT 1(1) 2.2 µF LP3981 OUT-SENSE 7(6) BYPASS EN 4(3) 6(5) 5(4) Note: Pin numbers in parenthesis indicate WSON package. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP3981 SNVS159H – OCTOBER 2001 – REVISED JULY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Typical Characteristics .............................................. Parameter Measurement Information .................. 9 Detailed Description ............................................ 10 8.1 Overview ................................................................. 10 8.2 Functional Block Diagram ....................................... 10 8.3 Feature Description................................................. 10 8.4 Device Functional Modes........................................ 11 9 Application and Implementation ........................ 12 9.1 Application Information............................................ 12 9.2 Typical Application ................................................. 12 10 Power Supply Recommendations ..................... 15 11 Layout................................................................... 15 11.1 Layout Guidelines ................................................. 15 11.2 Layout Example .................................................... 15 12 Device and Documentation Support ................. 16 12.1 12.2 12.3 12.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 16 16 16 16 13 Mechanical, Packaging, and Orderable Information ........................................................... 16 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (May 2013) to Revision H Page • Added Device Information and Pin Configuration and Functions sections, ESD Rating table, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support , and Mechanical, Packaging, and Orderable Information sections ................................................ 1 • Update pin names to TI nomenclature .................................................................................................................................. 1 • Deleted Ordering Information table - duplicative of POA ....................................................................................................... 1 • Deleted Lead temperature spec from Abs Max table - it is in POA. ..................................................................................... 4 • Deleted rows for max power dissipation - info in Power Dissipation and Device Operation ................................................. 4 • Deleted rows for max power dissipation - info in Power Dissipation and Device Operation ................................................. 4 • Added 2 new paragraphs to Power Dissipation and Device Operation subsection. ............................................................ 13 Changes from Revision F (May 2013) to Revision G • 2 Page Changed layout of National Data Sheet to TI format ........................................................................................................... 10 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: LP3981 LP3981 www.ti.com SNVS159H – OCTOBER 2001 – REVISED JULY 2015 5 Pin Configuration and Functions DGK Package 8-Pin VSSOP Top View OUT 1 8 NC IN 2 7 EN LP3981 NC 3 6 BYPASS OUT-SENSE 4 5 GND NGC Package 6-Pin WSON With Exposed Thermal Pad Top View OUT 1 6 EN Device Code IN 2 OUT-SENSE 3 5 BYPASS 4 GND GND Pin Descriptions PIN NAME TYPE DESCRIPTION VSSOP WSON BYPASS 6 5 — EN 7 6 I Enable input logic, enable high. GND 5 4 G Common ground. Connect to PAD. Input voltage of the LDO. Optional bypass capacitor for noise reduction. IN 2 2 I NC 3, 8 — — No internal connection. OUT 1 1 O Output voltage of the LDO. OUT-SENSE 4 3 O Output. Voltage sense pin. Must be connected to OUT for proper operation. THERMAL PAD — √ — Common ground. Connect to pin 4. Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: LP3981 3 LP3981 SNVS159H – OCTOBER 2001 – REVISED JULY 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) IN, EN MIN MAX UNIT −0.3 6.5 V −0.3 to VIN + 0.3 OUT, OUT-SENSE Junction temperature −65 Storage temperature, Tstg (1) (2) (3) 6.5 V 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the GND pin. If Military/Aerospace specified devices are required, contact the TI Sales Office/Distributors for availability and specifications. 6.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Machine model ±200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) (2) MIN VIN VEN Junction temperature (1) (2) NOM MAX 2.7 6 UNIT V 0 VIN V –40 125 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the GND pin. 6.4 Thermal Information LP3981 THERMAL METRIC (1) DGK (VSSOP) NGC (WSON) 8 PINS 6 PINS UNIT RθJA Junction-to-ambient thermal resistance, High K 177 56.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 67.7 76.8 °C/W RθJB Junction-to-board thermal resistance 97.4 30.9 °C/W ψJT Junction-to-top characterization parameter 10.8 3.3 °C/W ψJB Junction-to-board characterization parameter 96 31 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 10.7 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: LP3981 LP3981 www.ti.com SNVS159H – OCTOBER 2001 – REVISED JULY 2015 6.5 Electrical Characteristics Unless otherwise specified: VEN = 1.2 V, VIN = VOUT + 0.5 V, CIN = 2.2 µF, CBP = 0.033 µF, IOUT = 1 mA, COUT = 2.2 µF. All values are for TJ = 25°C, unless otherwise specified. (1) (2) PARAMETER Output voltage tolerance ΔVOUT Line regulation error TEST CONDITIONS MIN TJ = –40°C to +125°C VIN = VOUT + 0.5 V to 6 V, TA < 85°C −0.1 VIN = VOUT + 0.5 V to 6 V, TJ ≤125°C –0.2 PSRR Power supply rejection ratio (4) Quiescent current 0.005 IOUT = 1 mA to 300 mA TJ = –40°C to +125°C 0.005 VIN = VOUT(nom) + 1 V, ƒ = 1 kHz, IOUT = 50 mA (Figure 16) 50 VIN = VOUT(nom) + 1 V, ƒ = 10 kHz, IOUT = 50 mA (Figure 16) 55 VEN = 1.2 V, IOUT = 1 mA 70 VEN = 1.2 V, IOUT = 1 mA to 300 mA, VOUT = 2.5 V (5) 0.003 1.5 0.5 5 IOUT = 200 mA 88 IOUT = 200 mA, TJ = –40°C to +125°C 132 IOUT = 300 mA, TJ = –40°C to +125°C en Output noise voltage Thermal shutdown hysteresis Peak output current VOUT ≥ VOUT (nom) – 5% Maximum input current at VEN VEN = 0 and VIN VIL Logic low input threshold VIN = 2.7 V to 6 V, TJ = –40°C to +125°C VIH Logic high input threshold VIN = 2.7 V to 6 V, TJ = –40°C to +125°C (6) mA 35 µVRMS °C 20 IEN (2) (3) (4) (5) 600 160 IOUT(PK) (1) 200 Thermal shutdown temperature TSD mV 133 IOUT = 300 mA BW = 10 Hz to 100 kHz, CBP = 0.033 µF µA 210 IOUT = 1 mA, TJ = –40°C to +125°C Output grounded (steady state) dB 170 VEN = 1.2 V, IOUT = 1 mA to 300 mA, VOUT = 2.5 V TJ = –40°C to +125°C (5) Short-circuit current limit %/mA 120 IOUT = 1 mA ISC %/V 0.2 VEN = 0.4 V, TJ = –40°C to +125°C (6) 0.1 0.0003 VEN = 0.4 V Dropout voltage UNIT % of 3 VOUT(nom) VEN = 1.2 V, IOUT = 1 mA TJ = –40°C to +125°C IQ MAX 2 –3 IOUT = 1 mA to 300 mA Load regulation error (3) TYP −2 300 455 mA 0.001 µA 0.4 1.4 Minimum (MIN) and maximum (MAX) limits are ensured by design, test, or statistical analysis. Typical (TYP) numbers are not verified, but do represent the most likely norm. The target output voltage, which is labeled VOUT(nom), is the desired voltage option. An increase in the load current results in a slight decrease in the output voltage and vice versa. Specified by design. Not production tested. For VOUT > 2.5 V, increase IQ(MAX) by 2.5 µA for every 0.1 V increase in VOUT(nom); that is, IQ(MAX) = 210 µA + ((VOUT(NOM) – 2.5) × 25) µA . Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply for input voltages below 2.5 V. Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: LP3981 5 LP3981 SNVS159H – OCTOBER 2001 – REVISED JULY 2015 www.ti.com Electrical Characteristics (continued) Unless otherwise specified: VEN = 1.2 V, VIN = VOUT + 0.5 V, CIN = 2.2 µF, CBP = 0.033 µF, IOUT = 1 mA, COUT = 2.2 µF. All values are for TJ = 25°C, unless otherwise specified.(1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT CAPACITANCE COUT Output capacitor Capacitance ESR 2.2 22 µF 5 500 mΩ 6.6 Timing Requirements MIN tON Turnon time (1) (2) CBYPASS = 0.033 µF 6 MAX 240 CBYPASS = 0.033 µF, TJ = –40°C to +125°C (1) (2) NOM UNIT µs 350 Specified by design. Not production tested. Turnon time is time measured between the enable input just exceeding VIH and the output voltage just reaching 95% of its nominal value. Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: LP3981 LP3981 www.ti.com SNVS159H – OCTOBER 2001 – REVISED JULY 2015 6.7 Typical Characteristics Unless otherwise specified, CIN = COUT = 2.2 µF ceramic, CBP = 0.033 µF, VIN = VOUT + 0.5 V, TA = 25°C, EN pin is tied to VIN. VOUT = 2.83 V VOUT = 2.85 V Figure 1. Output Voltage vs. Temperature Figure 2. Dropout Voltage vs. Temperature VOUT = 2.85 V Figure 4. Output Short Circuit Current Figure 3. Ground Current vs. Load Current VIN = VOUT + 1 V Figure 5. Output Short Circuit Current Figure 6. Ripple Rejection Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: LP3981 7 LP3981 SNVS159H – OCTOBER 2001 – REVISED JULY 2015 www.ti.com Typical Characteristics (continued) Unless otherwise specified, CIN = COUT = 2.2 µF ceramic, CBP = 0.033 µF, VIN = VOUT + 0.5 V, TA = 25°C, EN pin is tied to VIN. VIN = VOUT + 1 V VIN = VOUT + 1 V Figure 7. Ripple Rejection Figure 8. Ripple Rejection VIN = 3.5 V VIN = 3.5 V Figure 9. Load Transient Response 8 Figure 10. Load Transient Response VIN = VOUT + 1 V To VOUT + 1.6 V VIN = VOUT + 1 V to VOUT + 1.6 V Figure 11. Line Transient Response Figure 12. Line Transient Response Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: LP3981 LP3981 www.ti.com SNVS159H – OCTOBER 2001 – REVISED JULY 2015 Typical Characteristics (continued) Unless otherwise specified, CIN = COUT = 2.2 µF ceramic, CBP = 0.033 µF, VIN = VOUT + 0.5 V, TA = 25°C, EN pin is tied to VIN. Figure 13. Enable Response (tON) Figure 14. Enable Response (tON) 7 Parameter Measurement Information Figure 15. Line Transient Response Input Perturbation Figure 16. PSRR Input Perturbation Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: LP3981 9 LP3981 SNVS159H – OCTOBER 2001 – REVISED JULY 2015 www.ti.com 8 Detailed Description 8.1 Overview The LP3981 family of fixed-output, ultra-low-dropout, and low-noise regulators offers exceptional performance for battery-powered applications. Available for voltages from 2.5-V to 3.3-V, the family is capable of delivering 300-mA continuous load current. The LP3981 contains several features to facilitate battery-powered designs: • Low dropout voltage , typical dropout of 132-mV at 300-mA load current. • Low quiescent current and low ground current. Ground current is typically 170 µA at 150-mA load, and 70 µA at 1-mA load. • A shutdown feature is available , allowing the regulator to consume only 0.003 µA typically when the EN pin is pulled low. • Power supply rejection is 60-dB at 1 kHZ. • Low noise; BYPASS pin allows for low-noise operation, with typically 35-µVRMS output noise over 10 Hz to 100 kHz. 8.2 Functional Block Diagram IN HIGH = ON EN OUT VREFERENCE 1.23 V Fast Turnon Circuit LOW = OFF OUT-SENSE BYPASS R2 Overcurrent and Thermal Protection GND 8.3 Feature Description 8.3.1 On/Off Input Operation The LP3981 is turned off by pulling the EN pin low, and turned on by pulling it high. If this feature is not used, the EN pin must be tied to VIN to keep the regulator output on at all time. To assure proper operation, the signal source used to drive the EN input must be able to swing above and below the specified turnon and turnoff voltage thresholds listed in Electrical Characteristics under VIL and VIH. 8.3.2 Fast On-Time The LP3981 utilizes a speed up circuitry to ramp up the internal VREF voltage to its final value to achieve a fast output turn on time. 10 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: LP3981 LP3981 www.ti.com SNVS159H – OCTOBER 2001 – REVISED JULY 2015 8.4 Device Functional Modes 8.4.1 Operation with VOUT(TARGET) + 0.3 V ≤ VIN ≤ 6 V The device operate if the input voltage is equal to, or exceeds VOUT(TARGET) + 0.3 V. At input voltages below the minimum VIN requirement, the devices do not operate correctly and output voltage may not reach target value. 8.4.2 Operation With EN Control If the voltage on the EN pin is less than 0.4 V, the device is disabled, and in this state the shutdown current does not exceed 1.5 μA. Raising EN above 1.4 V initiates the start-up sequence of the device. Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: LP3981 11 LP3981 SNVS159H – OCTOBER 2001 – REVISED JULY 2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers must validate and test their design implementation to confirm system functionality. 9.1 Application Information The LP3981 can provide 300-mA output current with 2.5-V to 6-V input. It is stable with a 2.2-μF ceramic output capacitor. An optional external bypass capacitor reduces the output noise without slowing down the load transient response. Typical output noise is 35 µVRMS at frequencies from 10 Hz to 100 kHz. Typical power supply rejection is 60 dB at 1 kHz. 9.2 Typical Application 2(2) IN 2.2 µF OUT 1(1) 2.2 µF LP3981 OUT-SENSE 7(6) BYPASS EN 4(3) 6(5) 5(4) Figure 17. LP3981 Typical Application 9.2.1 Design Requirements Example requirements for typical voltage inverter applications: Table 1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage 3.5 V, ±10% Output voltage 2.5 V, ±5% Output current 300 mA (maximum) RMS noise, 10 Hz to100 kHz 35 μVRMS PSRR at 1 kHz 60 dB 9.2.2 Detailed Design Procedure 9.2.2.1 Power Dissipation and Device Operation The permissible power dissipation for any package is a measure of the capability of the device to pass heat from the power source, the junctions of the device, to the ultimate heat sink, the ambient environment. Thus, the power dissipation is dependant on the ambient temperature and the thermal resistance across the various interfaces between the die and ambient air. As stated in the notes for Absolute Maximum Ratings and Recommended Operating Conditions, the allowable power dissipation for the device in a given package can be calculated using Equation 1: 2& = 12 6, (/#: ) F 6# ) 4à,# (1) Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: LP3981 LP3981 www.ti.com SNVS159H – OCTOBER 2001 – REVISED JULY 2015 With an RθJA = 56.5°C/W, the device in the WSON package returns a value of 1.77 W with a maximum junction temperature of 125°C and an ambient temperature of 25°C. The device in a VSSOP package returns a figure of 0.565 W (R θJA = 177°C/W). The actual power dissipation across the device can be represented by Equation 2: 2& = :8+0 F 8176 ; × +176 (2) This establishes the relationship between the power dissipation allowed due to thermal considerations, the voltage drop across the device, and the continuous current capability of the device. The device can deliver 300 mA but care must be taken when choosing the continuous current output for the device under the operating load conditions. The RθJA value is not a characteristic of the package by itself but of the package, the printed circuit board (PCB), and other environmental factors. Equation 2 is only valid when the application configuration matches the EIA/JEDEC JESD51-7 (High-K) configuration in which RθJA was either measured or modeled. Few, if any, user applications conform to the PCB configuration defined by the EIA/JEDEC standards. As a result, the RθJA values are useful only when comparing assorted packages that have been measured or modeled to the EIA/JEDEC standards, but are of little use to estimate real world junction temperatures. The EIA/JEDEC standard JESD51-2 provides methodologies to estimate the junction temperature from external measurements (ψJB references the temperature at the PCB, and ψJT references the temperature at the top surface of the package) when operating under steady-state power dissipation conditions. These methodologies have been determined to be relatively independent of the PCB attached to the package when compared to the more typical RθJA. Refer to Semiconductor and IC Package Thermal Metrics application report, SPRA953, for specifics. 9.2.2.2 External Capacitors Like any low-dropout regulator, the LP3981 requires external capacitors for regulator stability. The LP3981 is specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. 9.2.2.3 Input Capacitor An input capacitance of ≊ 2.2 µF is required between the LP3981 input pin and ground (the amount of the capacitance may be increased without limit). This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. NOTE Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be specified by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance is ≊ 2.2 µF over the entire operating temperature range. 9.2.2.4 Output Capacitor The LP3981 is designed specifically to work with very small ceramic output capacitors. A ceramic capacitor (dielectric types Z5U, Y5V or X7R) in the 2.2-µF to 22-µF range with 5-mΩ to 500-mΩ ESR is suitable in the LP3981 application circuit. It is also possible to use tantalum or film capacitors at the output, but these are not as attractive for reasons of size and cost (see Capacitor Characteristics). The output capacitor must meet the requirement for minimum amount of capacitance and also have an equivalent series resistance (ESR) value which is within a stable range (5 mΩ to 500 mΩ). Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: LP3981 13 LP3981 SNVS159H – OCTOBER 2001 – REVISED JULY 2015 www.ti.com 9.2.2.5 No-Load Stability The LP3981 remains stable and in regulation with no external load. This is specially important in CMOS RAM keep-alive applications. 9.2.2.6 Noise Bypass Capacitor Connecting a 0.033-µF capacitor between the BYPASS pin and ground significantly reduces noise on the regulator output. This capacitor is connected directly to a high impedance node in the bad gap reference circuit. Any significant loading on this node causes a change on the regulated output voltage. For this reason, DC leakage current through this pin must be kept as low as possible for best output voltage accuracy. The types of capacitors best suited for the noise bypass capacitor are ceramic and film. Hight-quality ceramic capacitors with either NPO or COG dielectric typically have very low leakage. Polypropolene and polycarbonate film capacitors are available in small surface-mount packages and typically have extremely low leakage current. Unlike many other LDOs, addition of a noise reduction capacitor does not effect the transient response of the device. 9.2.2.7 Capacitor Characteristics The LP3981 is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer: for capacitance values in the range of 1 µF to 4.7 µF, ceramic capacitors are the smallest, least expensive and have the lowest ESR values (which makes them best for eliminating high frequency noise). The ESR of a typical 1µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for stability by the LP3981. Capacitance of a ceramic capacitor can vary with temperature. Most large value ceramic capacitors (≊ 2.2 µF) are manufactured with Z5U or Y5V temperature characteristics, which results in the capacitance dropping by more than 50% as the temperature goes from 25°C to 85°C. A better choice for temperature coefficient in a ceramic capacitor is X7R, which holds the capacitance within ±15%. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 1-µF to 4.7-µF range. Another important consideration is that tantalum capacitors have higher ESR values than equivalently sized ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It must also be noted that the ESR of a typical tantalum increases about 2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed. 9.2.3 Application Curves 14 VIN = VOUT + 1 V to VOUT + 1.6 V VIN = VOUT + 1V to VOUT + 1.6 V Figure 18. Line Transient Response Figure 19. Line Transient Response Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: LP3981 LP3981 www.ti.com SNVS159H – OCTOBER 2001 – REVISED JULY 2015 10 Power Supply Recommendations The LP3981 is designed to operate from an input voltage supply range between 2.5 V and 6 V. The input voltage range provides adequate headroom in order for the device to have a regulated output. This input supply must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help to improve the output noise performance. 11 Layout 11.1 Layout Guidelines For best overall performance, place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is either embedded in the PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device. In most applications, this ground plane is necessary to meet thermal requirements. 11.2 Layout Example COUT OUT 1 6 EN IN 2 5 BYPASS OUT-SENSE 3 4 CBYPASS CIN GND Figure 20. LP3981 Layout Example Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: LP3981 15 LP3981 SNVS159H – OCTOBER 2001 – REVISED JULY 2015 www.ti.com 12 Device and Documentation Support 12.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.2 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 16 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: LP3981 PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP3981ILD-2.5/NOPB ACTIVE WSON NGC 6 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 LO1UB LP3981ILD-3.0/NOPB ACTIVE WSON NGC 6 1000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-3-260C-168 HR LP3981ILD-3.3/NOPB ACTIVE WSON NGC 6 1000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-3-260C-168 HR -40 to 125 LO1XB LP3981ILDX-2.5/NOPB ACTIVE WSON NGC 6 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 LO1UB LP3981ILDX-2.7/NOPB ACTIVE WSON NGC 6 4500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-3-260C-168 HR -40 to 125 LO1VB LP3981ILDX-2.8/NOPB ACTIVE WSON NGC 6 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L01ZB LP3981ILDX-2.83/NOPB ACTIVE WSON NGC 6 4500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-3-260C-168 HR -40 to 125 LO1SB LP3981ILDX-3.03/NOPB ACTIVE WSON NGC 6 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 LO1YB L017B LP3981IMM-2.5 NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 125 LFKB LP3981IMM-2.5/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LFKB LP3981IMM-2.7/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LFLB LP3981IMM-2.8/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LFTB LP3981IMM-3.0/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LF3B LP3981IMM-3.03 NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 125 LFPB LP3981IMM-3.03/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LFPB LP3981IMM-3.3 NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 125 LFNB LP3981IMM-3.3/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LFNB LP3981IMMX-2.5/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LFKB Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 8-Oct-2015 Status (1) LP3981IMMX-3.3/NOPB ACTIVE Package Type Package Pins Package Drawing Qty VSSOP DGK 8 3500 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM Op Temp (°C) Device Marking (4/5) -40 to 125 LFNB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 Samples PACKAGE MATERIALS INFORMATION www.ti.com 24-Feb-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP3981ILD-2.5/NOPB WSON NGC 6 1000 178.0 12.4 4.3 3.3 1.0 8.0 12.0 Q1 LP3981ILD-3.0/NOPB WSON NGC 6 1000 180.0 12.4 4.3 3.3 1.0 8.0 12.0 Q1 LP3981ILD-3.3/NOPB WSON NGC 6 1000 180.0 12.4 4.3 3.3 1.0 8.0 12.0 Q1 LP3981ILDX-2.5/NOPB WSON NGC 6 4500 330.0 12.4 4.3 3.3 1.0 8.0 12.0 Q1 LP3981ILDX-2.7/NOPB WSON NGC 6 4500 330.0 12.4 4.3 3.3 1.0 8.0 12.0 Q1 LP3981ILDX-2.8/NOPB WSON NGC 6 4500 330.0 12.4 4.3 3.3 1.0 8.0 12.0 Q1 LP3981ILDX-2.83/NOPB WSON NGC 6 4500 330.0 12.4 4.3 3.3 1.0 8.0 12.0 Q1 LP3981ILDX-3.03/NOPB WSON NGC 6 4500 330.0 12.4 4.3 3.3 1.0 8.0 12.0 Q1 LP3981IMM-2.5 VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3981IMM-2.5/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3981IMM-2.7/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3981IMM-2.8/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3981IMM-3.0/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3981IMM-3.03 VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3981IMM-3.03/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3981IMM-3.3 VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3981IMM-3.3/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3981IMMX-2.5/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Feb-2016 Device LP3981IMMX-3.3/NOPB Package Package Pins Type Drawing VSSOP DGK 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3500 330.0 12.4 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.0 Q1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3981ILD-2.5/NOPB WSON NGC 6 1000 213.0 191.0 55.0 LP3981ILD-3.0/NOPB WSON NGC 6 1000 195.0 200.0 45.0 LP3981ILD-3.3/NOPB WSON NGC 6 1000 195.0 200.0 45.0 LP3981ILDX-2.5/NOPB WSON NGC 6 4500 367.0 367.0 35.0 LP3981ILDX-2.7/NOPB WSON NGC 6 4500 370.0 355.0 55.0 LP3981ILDX-2.8/NOPB WSON NGC 6 4500 367.0 367.0 35.0 LP3981ILDX-2.83/NOPB WSON NGC 6 4500 370.0 355.0 55.0 LP3981ILDX-3.03/NOPB WSON NGC 6 4500 367.0 367.0 35.0 LP3981IMM-2.5 VSSOP DGK 8 1000 210.0 185.0 35.0 LP3981IMM-2.5/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP3981IMM-2.7/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP3981IMM-2.8/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP3981IMM-3.0/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP3981IMM-3.03 VSSOP DGK 8 1000 210.0 185.0 35.0 LP3981IMM-3.03/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP3981IMM-3.3 VSSOP DGK 8 1000 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Feb-2016 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3981IMM-3.3/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP3981IMMX-2.5/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LP3981IMMX-3.3/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 3 MECHANICAL DATA NGC0006D LDC06D (Rev B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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