Davicom DM130120 15v / 30v selectable output & 122 hi-v channels driver ic Datasheet

DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
DAVICOM Semiconductor, Inc.
DM130120
15V / 30V Selectable Output &
122 Hi-V Channels Driver IC
DATA SHEET
Preliminary
Version: DM130120-11-MCO-DS-P01
July 11, 2016
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
1
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
Content
1
2
3
4
5
6
7
8
9
10
General Description........................................................................................................................... 3
Features ............................................................................................................................................. 4
Block Diagram ................................................................................................................................... 5
PAD Diagram ..................................................................................................................................... 6
Pin Description .................................................................................................................................. 7
5.1 TFBGA-145L Pin Assignment......................................................................................................... 7
5.2 LQFP-176L Pin Assignment ........................................................................................................... 8
Function Description ......................................................................................................................... 9
6.1
Generate Hi-V Driving Bias Supply...................................................................................... 9
6.1.1 Internal Charge Pump Supply ............................................................................................. 9
6.1.2 External Driving Bias Supply ............................................................................................... 9
6.2
Multi-drivers Application .....................................................................................................10
6.3
EPD Driver Control Register .............................................................................................. 11
6.4
Control Signal Waveform ...................................................................................................13
6.4.1 Format of One Byte (2-Wires Serial Interface)....................................................................13
6.4.2 SPI control waveform.........................................................................................................15
6.4.3 Com & Segment vs. Control Signal ....................................................................................17
Operating Ratings ............................................................................................................................21
Absolute Maximum Ratings .............................................................................................................21
Package Information ........................................................................................................................22
9.1
Package Detail Information ................................................................................................22
Ordering Information ........................................................................................................................26
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
2
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
1
General Description
The DM130120 consist of Hi-V DC-DC charge pump for EPD (Electrophoretic display) application. User can
chose 15V or 30V to drive EPD. All the function are controlled by 2-wires serial interface or SPI. DM130120
support synchronous serial signal interface (Maximum 4 chips cascadable).
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
3
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
2
Features
l
Operating voltage 2.2V ~ 5.5V
l
l
Selectable 15V or 30V driving voltage for EPD
120 SEG + 1 COM + 1 Background
l
DC-DC charge pump circuit
l
ON chip RC oscillator
l
2-wires serial interface
l
SPI interface
l
Voltage regulator
l
Synchronous serial signal(Maximum 4 chips cascadable)
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
4
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
3
Block Diagram
pp[1~5] pm[1~5]
Reference
voltage
Vref
(V1D5)
vx2
vx3
vx4
vx5
vpp
Charge pump
Hi-V out
pumpck
vpp15
CPen
D[7~0]
Hi-V
channel
control
Y[122~1]
Logic control
Internal
oscillator
wck
irosck
SCL SDA A0
A1 LOGICEN
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
5
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
Y77
Y76
Y75
Y74
Y73
Y72
Y71
Y70
Y85
Y84
Y83
Y82
Y81
Y80
Y79
Y78
Y93
Y92
Y91
Y90
Y89
Y88
Y87
Y86
Y101
Y100
Y99
Y98
Y97
Y96
Y95
Y94
Y109
Y108
Y107
Y106
Y105
Y104
Y103
Y102
Y117
Y116
Y115
Y114
Y113
Y112
Y111
Y110
PAD Diagram
Y119
Y118
4
Y120
Y121
Y122
Y69
Y68
Y67
Y66
Y65
Y64
Y63
Y62
VPP
PM5
PP5
VX5
PM4
PP4
VX4
PM3
PP3
VX3
PM2
PP2
Y61
Y60
Y59
Y58
Y57
Y56
Y55
Y54
DM130120
VX2
PM1
PP1
Y53
Y52
Y51
Y50
Y49
Y48
Y47
Y46
VDD
VSS
Y41
Y42
Y43
Y44
Y45
Y33
Y34
Y35
Y36
Y37
Y38
Y39
Y40
Y25
Y26
Y27
Y28
Y29
Y30
Y31
Y32
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
SDA
SCL
A1
A0
LOGICEN
V1D5
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
6
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
5
Pin Description
PIN NAME
SCL
SDA / SPIEN
A1 / SPICK
A0 / SPIDATA
LOGICEN
VPP
VX5
VX4
VX3
VX2
PP[1:5]
PM[1:5]
Y[1:122]
VDD
VSS
V1D5
Description
2-wires serial interface clock input
2-wires serial interface data input or SPIEN pin
Device ID setting bit1 or SPICK pin
Device ID setting bit0 or SPIDATA pin
Select the control interface
LOGICEN=1 2-wires serial interface
LOGICEN=0 SPI interface
Charge pump output pin about 30v
Charge pump output pin about 15v
Charge pump output pin about 7.5v
Charge pump output pin about 5v
Charge pump output pin about 2.5v
Positive terminal for charge pump capacitor
Negative terminal for charge pump capacitor
EPD Hi-V channels
Positive power source
Negative power source
Charge pump reference Voltage
Note：SCL & SDA need pull high resistor 4.7KΩ to VDD
VID5 needs connect to 0.1uF to VSS
5.1 TFBGA-145L Pin Assignment
A
B
C
D
E
F
G
H
J
K
L
M
N
A
B
C
D
E
F
G
H
J
K
L
M
N
1
A1 / Y1
B1 / Y2
C1 / Y3
D1 / Y8
E1 / Y13
F1 / Y17
G1 / Y21
H1 / Y24
J1 / Y28
K1 / Y34
L1 / Y36
M1 / Y39
N1 / Y41
8
A8 / PM3
B8 / PP4
C8 / PM4
D8 / PP5
2
A2 / Y4
B2 / Y5
C2 / Y6
D2 / Y12
E2 / Y16
F2 / Y20
G2 / Y23
H2 / Y27
J2 / Y31
K2 / Y35
L2 / Y40
M2 / Y44
N2 / Y45
9
A9 / VX5
B9 / PM5
C9 / VPP
D9 / Y121
K8 / Y65
L8 / Y62
M8 / Y64
N8 / Y63
K9 / Y83
L9 / Y66
M9 / Y68
N9 / Y67
3
A3 / V1D5
B3 / Y7
C3 / Y10
D3 / Y 14
E3 / Y18
F3 / Y22
G3 / Y25
H3 / Y29
J3 / Y32
K3 / Y37
L3 / Y42
M3 / Y43
N3 / Y46
10
A10 / Y122
B10 / Y120
C10 / Y112
D10 / Y108
E10 / Y105
F10 / Y100
G10 / Y97
H10 / Y95
J10 / Y89
K10 / Y86
L10 / Y81
M10 / Y76
N10 / Y69
4
A4 / LOGICEN
B4 / Y9
C4 / Y11
D4 / Y15
E4 / Y19
F4 / VSS
G4 / Y26
H4 / Y30
J4 / Y33
K4 / Y38
L4 / Y49
M4 / Y47
N4 / Y48
11
A11 / Y117
B11 / Y116
C11 / Y114
D11 / Y109
E11 / Y104
F11 / Y101
G11 / Y96
H11 / Y94
J11 / Y87
K11 / Y84
L11 / Y79
M11 / Y75
N11 / Y72
5
A5 / SDA
B5 / SCL
C5 / A1
D5 / A0
E5 / VDD
6
A6 / PP1
B6 / PP2
C6 / VX2
D6 / PM1
7
A7 / PM2
B7 / VX3
C7 / PP3
D7 / VX4
K5 / Y53
L5 / Y50
M5 / Y51
N5 / Y52
12
A12 / Y118
B12 / Y115
C12 / Y111
D12 / Y107
E12 / Y103
F12 / Y99
G12 / Y92
H12 / Y91
J12 / Y85
K12 / Y80
L12 / Y77
M12 / Y70
N12 / Y71
K6 / Y57
L6 / Y54
M6 / Y56
N6 / Y55
13
A13 / Y119
B13 / Y113
C13 / Y110
D13 / Y106
E13 / Y102
F13 / Y98
G13 / Y93
H13 / Y90
J13 / Y88
K13 / Y82
L13 / Y78
M13 / Y74
N13 / Y73
K7 / Y61
L7 / Y58
M7 / Y60
N7 / Y59
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
7
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
5.2 LQFP-176L Pin Assignment
PIN No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
PIN Name
Y118
Y119
Y120
Y121
Y122
VPP
PM5
PP5
VX5
PM4
PP4
VX4
PM3
PP3
VX3
PM2
PP2
VX2
PM1
PP1
VDD
VSS
SDA
SCL
A1
A0
LOGICEN
V1D5
Y1
Y2
Y3
Y4
PIN No.
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
PIN Name
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
Y37
Y38
Y39
Y40
Y41
Y42
Y43
Y44
Y45
PIN No.
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
PIN Name
Y46
Y47
Y48
Y49
Y50
Y51
Y52
Y53
Y54
Y55
Y56
Y57
Y58
Y59
Y60
Y61
Y62
Y63
Y64
Y65
Y66
Y67
Y68
Y69
Y70
Y71
Y72
Y73
Y74
Y75
Y76
Y77
Y78
Y79
Y80
Y81
Y82
Y83
Y84
Y85
Y86
Y87
Y88
Y89
PIN No.
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
PIN Name
Y90
Y91
Y92
Y93
Y94
Y95
Y96
Y97
Y98
Y99
Y100
Y101
Y102
Y103
Y104
Y105
Y106
Y107
Y108
Y109
Y110
Y111
Y112
Y113
Y114
Y115
Y116
Y117
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
8
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
6
Function Description
6.1 Generate Hi-V Driving Bias Supply
6.1.1 Internal Charge Pump Supply
The charge pump circuit can generate Hi-voltage up to 30V. User also can select 0V, 15V or 30V to drive EPD
by setting control register.
The value of Hi-voltage that pump can generate as following.
VPP=30V, VX5=15V, VSS=0V, set register #10h bit5 VPP15=0
V1D5
A0
A1
SCL
SDA
LOGICEN
PM1
PP2
0.1uF
PM2
PP3
0.01uF
PM3
PP4
Power
VDD
PP1
0.1uF
DM130120
0.01uF
VX2
VX3
VX4
VX5
VPP
PM4
PP5
0.01uF
PM5
VSS
0.01uF 0.01uF 0.01uF
0.1uF
0.1uF
0.1uF
6.1.2 External Driving Bias Supply
External Hi-V power source supply to VPP & VX3. First, user need to turn off internal pump function then
supply 15V/30V to VPP , 5V to VX3
PP1
PM1
PP2
PM2
PP3
VDD
V1D5
A0
A1
SCL
SDA
LOGICEN
Power
DM130120
PM3
PP4
PM4
PP5
PM5
VSS
VX2
VX3
VX4
VX5
VPP
0.01uF
5V
15V/
30V
External
supply
0.1uF
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
9
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
6.2 Multi-drivers Application
With 2-wires serial interface that the host device could control DM130120. (A1,A0) pins correspond the ID
setting (Maximum support 4 chips). See the following figure for setting ID option.
Note: SPI don’t support Multi-drivers application.
SDA
SCL
Power
PP1
VDD
LOGICEN
A0
A1
SCL
SDA
PM1
PP2
PM2
PP3
PM3
PP4
DM130120
ID 11
VX2
VX3
VX4
VX5
PM4
PP5
PM5
VPP
VID5
VDD
PP1
LOGICEN
A0
A1
SCL
PM1
PP2
PM2
PP3
PM3
PP4
DM130120
ID 01
PM5
VID5
PP1
VDD
DM130120
ID 10
PM5
VID5
PP1
VDD
LOGICEN
A0
A1
SCL
SDA
0.1uF
PM1
PP2
PM2
PP3
0.01uF
PM3
PP4
0.01uF
VSS
VX2
VX3
VX4
VX5
VPP
PM4
PP5
0.1uF
VSS
LOGICEN
A0
A1
SCL
SDA
PM1
PP2
PM3
PP4
SDA
VX2
VX3
VX4
VX5
VPP
PM4
PP5
PM2
PP3
VSS
DM130120
ID 00
PM4
PP5
0.01uF
PM5
VID5
0.1uF
VSS
VX2
VX3
VX4
VX5
VPP
C1=0.01uF
C2=0.01uF
C3=0.01uF
C4=0.1uF
C5=0.1uF
C1
C2
C3
C4
C5
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
10
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
6.3 EPD Driver Control Register
REGISTER
Address
$00H
$01H
$02H
$03H
$04H
$05H
$06H
$07H
$08H
$09H
$0AH
$0BH
$0CH
$0DH
$0EH
$0FH
$10H
Bit7
Y008
Y016
Y024
Y032
Y040
Y048
Y056
Y064
Y072
Y080
Y088
Y096
Y104
Y112
Y120
#
CPEN
Bit6
Y007
Y015
Y023
Y031
Y039
Y047
Y055
Y063
Y071
Y079
Y087
Y095
Y103
Y111
Y119
#
C3
Bit5
Y006
Y014
Y022
Y030
Y038
Y046
Y054
Y062
Y070
Y078
Y086
Y094
Y102
Y110
Y118
#
VPP15
Data
Bit4
Bit3
Y005 Y004
Y013 Y012
Y021 Y020
Y029 Y028
Y037 Y036
Y045 Y044
Y053 Y052
Y061 Y060
Y069 Y068
Y077 Y076
Y085 Y084
Y093 Y092
Y101 Y100
Y109 Y108
Y117 Y116
#
#
C2
Load
Bit2
Y003
Y011
Y019
Y027
Y035
Y043
Y051
Y059
Y067
Y075
Y083
Y091
Y099
Y107
Y115
#
C1
Bit1
Y002
Y010
Y018
Y026
Y034
Y042
Y050
Y058
Y066
Y074
Y082
Y090
Y098
Y106
Y114
Y122
VSEL1
Bit0
Y001
Y009
Y017
Y025
Y033
Y041
Y049
Y057
Y065
Y073
Y081
Y089
Y097
Y105
Y113
Y121
VSEL0
Y1~Y122 output setting：
Y1~Y120 mapping to segment pins
Y121 correspond to COM(Common) pin
Y122 correspond to BG(Background) pin
The output voltage (0V,15V,30V) for Y[1~122] are selectable.
If user want Y[1~122] to output 30V or 15V. Setting the correspond bit to “1”
If user want Y[1~122] to output 0V. Setting the correspond bit to “0”
Example：
If users wants Y9, Y11, Y13, Y15 output VPP and Y10, Y12, Y14,Y16 output “0V”
Register $01H = 01010101
Register “$10h” bit7 “CPEN”: Charge pump on / off
CPEN=1 , charge pump enable
CPEN=0 , charge pump disable
Register “$10h” bit6 “C3”：Internal test parameter C3. User has to set up “0” here.
Register “$10h” bit5 “VPP15” ：Half VPP output switch
VPP15=1：Hi-V channels logic high will output VX5, the voltage equal to half VPP.
VPP15=0：Hi-V channels logic high will output VPP.
Register”$10h” bit4 “C2”：Internal test parameter “C2”. Set up “0” here for recommendation.
Register”$10h” bit3 “Load”：Load data from Y[1~122] and then latch out for synchronous
Load=1：Load data from Y[1~122] to output buffer
Load=0：Latch the buffer and output
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
11
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
Output Synchronous
For the reason of output synchronous that user have to set up $10h, bit3 = 0 first. This step will load the data
Y [1~122] from register [$00h~$0Fh] into each buffer. And then set up $10h, bit3 = 1 for the next step. Y
[1~122] latch buffers will latch and output the data synchronous.
Data [7~0]
Load
Y[1]
Y[1] data register
Y[1] latch buffer
Y[2] data register
Y[2] latch buffer
Y[122] data register
Y[122] latch buffer
Y[2]
Y[122]
Note: The data hold time for this bit should be over “1us”. That means, customer set up register $10h.bit3 =1
for latching output then wait over 1us that will be available for next data.
Register”$10h” bit2 “C1”: Internal test parameter “C1”. Set up “0” here for recommendation.
Register”$10h” bit0~1 “VSEL0~1”：Adjustable internal reference voltage
All the selections are shown as below:
V1D5
VSEL[1：0]
00
1.5V
01
1.6V
10
1.7V
11
1.8V
Note:
1. All control registers don’t have initialize value after power on. Users need to initial all register manually.
2. $xxH means address and represent in hexadecimal form.
3. “xxxxxxxxb” means 8-bits data of register and represent in binary form.
4. The “VPP” here means the most high pumped voltage, “VX5” means half VPP and “GND” means the
most low voltage of system power.
5. Write by default value 00b.
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
12
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
6.4 Control Signal Waveform
6.4.1 Format of One Byte (2-Wires Serial Interface)
This byte could be $00H ~ $10H, see 6.3 EPD driver control register.
Start Bit
Device ID code
ACK
Register address
ACK
Data
ACK
Stop Bit
SDA
SCL
start bit
Device ID Code
Ack
Host device
input mode
SDA
Bit7
Bit6
Bit 5
Bit4
Bit 3
Bit2
Bit 1
Ack
Bit 0
SCL
Register Addres
Ack
Host device
input mode
SDA
Bit7
Bit 6
Bit5
Bit4
Bit3
Bit 2
Bit1
Bit0
Ack
SCL
Data
SDA
Bit7
Bit 6
Bit5
Bit4
Ack
Bit3
Bit 2
Bit1
Bit0
stop bit
Ack
SCL
Host device
input mode
Note: Timing diagram above is when SCL=500KHz
Device ID code：
ID code is defined by (A0&A1) pins. See multi-driver application in P10. Control signal input 8-bits
“111100A1,A0” (A1,A0)=00,01,10,11 then only matched driver will operate.
Register address：
Address of control register from $00H ~ $10H. The control signal here follow Device ID code
Data of register：
Definition of all control register see 6.3 EPD driver control register.
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
13
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
Condition setting
Perform with one driver IC and ID code (A1,A0)=00
Operate flow of one byte
Condition：
Perform one driver
ID code(A1,A0)=00
Host device input
Control signal
Start bit
Host device
Timeout function
For Ack feedback
Pass
Fail
Host device input
Control signal
Device ID code
Host device check
Device ID code ack
Pass
Ack feedback
Timeout
Fail
Host device
Timeout function
For Ack feedback
Pass
Fail
Host device input
Control signal
Register address
Host device check
Register address ack
Pass
Host device
Timeout function
For Ack feedback
Pass
Fail
Host device input
Control signal
Data of register
Host device check
Data of register ack
Pass
Host device input
Control signal
Stop bit
Note：
1. According to operating flow above, host device need set SDA to input mode at ACK feedback. Also check
ACK feedback “Low” that means current byte transmission pass.
2. Each byte of control register has complete format as figure in P12. Following one-byte format to compose
sequent transmission.
3. All the timing of pulse-width in operating flow above represents the minimum acceptable value.
4. Operating flow above is only for reference. For actual situation, please refer to E-paper spec.
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
14
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
6.4.2 SPI control waveform
There are two format of controlled signal as below.
Instruction code
Function
00000001
Writing Data register
00000011
Writing control register
Format of writing data register
SPIEN
SPICK
SPIDATA
D7
D6
Instruction
D5
D4
D3
D2
D1
D0
D2
D1
D0
Start address
SPIEN
SPICK
SPIDATA
D7
D6
D5
D4
D3
D2
D1
D0
D7
Data of start address
D6
D5
D4
D3
Data of (start address +1)
SPIEN
SPICK
SPIDATA
D7
D6
D5
D4
D3
D2
D1
Data of (start address +2)
D0
D7
D6
D5
D4
D3
D2
D1
D0
Data of (start address +n)
1.
2.
3.
4.
5.
SPIEN low active
SPIDATA input instruction [00000001] to writing data register
SPIDATA input start address (selectable from $00H~$0FH)
SPIDATA input the data of start address
SPIDATA input data of next address. For example, start address from $00H à #FFH(contain of $00H) à
#02H (here is the contain of $01H)….etc.
6. SPIEN high disable while data register writing finished.
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
15
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
Format of writing control register
SPIEN
SPICK
SPIDATA
D7
D6
Instruction
1.
2.
3.
4.
D5
D4
D3
D2
D1
D0
Data of control register
SPIEN low active
SPIDATA input instruction [00000011] for writing control register
SPIDATA input data of control register
SPIEN high disable after control register writing done.
Note：
1. ID code setting is not needed in SPI mode.
2. Writing data register could be sequent, but control register is single.
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
16
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
6.4.3 Com & Segment vs. Control Signal
30V
Vsegment
0V
30V
Vcom
0V
(1)Phase1=100ms (2)Phase2=50ms
(3)Phase3=80ms
Condition1-1：2-wires serial mode (one driver IC)
VDD=3V, use internal pumping function, perform with one driver IC, pin LOGICEN = 1, ID code (A1,A0)=00
Register $10H. bit5 VPP15=0, bit6 PUMPH=0 → VPP=30V
Vsegment including Y1~Y120, Vcom = Y121, Vbg = Y122
Condition1-2：SPI mode (one driver IC)
VDD=3V, use internal pumping function, perform with one driver IC, pin LOGICEN = 0
Register $10H. bit5 VPP15=0, bit6 PUMPH=0 → VPP=30V
Vsegment including Y1~Y120, Vcom = Y121, Vbg = Y122
Condition1-1 & 1-2 operate flow
1. Control register $00H~$0FH = “00000000b”, $10H = “10001000b”. This step Y1~Y122 will load data from
data register and output “0V” to all EPD pins simultaneously.
After that $10H = “10000000b” here will latch all EPD pins to “0V” and enable charge pump.
Note! $10H bit3 load = 1 → 0 will load all data to EPD pins and then latch output state.
2. Host device delay 100ms for internal pumping stability.
3. Control register $00H~$0FH = “11111111b” , $10H = “10001000b”.
Then $10H = “10000000b”. Here all EPD pins will output VPP.
4. Host device delay 100ms to display phase1 pattern.
5. Control register $00H~$0EH = “11111111b” , $0FH = “11111110b” , $10H = “10001000b”. Then $10H =
“10000000b”. All segment & background will output VPP, Y121 output “0V”.
6. Host device delay 50ms to display phase2 pattern.
7. Control register $00H~$0FH = “00000000b” , $10H = “10001000b”.
Then $10H = “10000000b”. All EPD pins will output “0V”.
8. Host device delay 80ms to display phase3 pattern.
9. All EPD pins output “0V” and disable charge pumping if there’s no pattern will be display.
Note：$xxH means address and represent in hexadecimal forml.
“xxxxxxxxb” means 8-bits data and represent in binary form.
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
17
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
Condition1-1：2-wires serial mode
VDD=3V, perform one driver, VPP=30V
LOGICEN = 1, ID code(A1,A0)=00
Control register $00~$0FH
= 00H
$10H = 88H then to 80H
Condition1-2：SPI mode
VDD=3V, perform one driver, VPP=30V
LOGICEN = 0
Y1~Y122 output0V
and pump ebable
Initialize setting
Host device
Delay 100ms for
pumping stability
Control register $00~$0FH
= FFH
$10H = 88 then to 80H
Phase1
Phase1
holding 100ms
Control register
$00~$0EH = FFH
$0FH = FEH
$10H = 88 then to 80H
Pattern1
Phase2
Phase2
holding 50ms
Control register $00~$0FH
= 00H
$10H = 88 then to 80H
Phase3
Phase3
holding 80ms
YES
Display next pattern?
NO
All EPD pins output VSS
then disable charge pump.
Control register $00~$0FH
= 00H
$10H = 08 then to 80H
Trigger
New pattern
Stop mode
IC wake up
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
18
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
Condition2：2-wires serial mode(cascade four drivers)
VDD=3V , perform with four drivers, one driver to be the pumping source and others set up supply from
external source, pin LOGICEN = 1
Register $10H. bit5 VPP15=0, bit6 PUMPH=0 → VPP=30V
Vsegment including Y1~Y120, Vcom = Y121, Vbg = Y122
Condition2 operate flow
1. ID[00] Control register $00H~$0FH = “00000000b”, $10H = “00001000b”. This step Y1~Y122 will load
data from data register and output “0V” to all EPD pins simultaneously.
After that $10H = “00000000b” here will latch all EPD pins to “0V”.
Note! $10H bit3 load = 1 → 0 will load all data to EPD pins and then latch output state.
2. ID[01~11] follow step1 to initialize all EPD pins to output “0V”
3. ID[00] register $10H = “10000000b” to enable charge pump and take ID[00] as pumping source others IC
set up supply from external source.
4. Host device delay 100ms for internal pumping stability.
5. ID[00~11] Control register $00H~$0FH = “11111111b” , *ID[00] $10H = “10001000b” , ID[01~11] $10H =
“00001000b”. Then ID[00] $10H = “10000000b” , ID[01~11] $10H = “00000000b”. Here all EPD pins will
output VPP.
6. Host device delay 100ms to display phase1 pattern.
7. ID[00~11] Control register $00H~$0EH = “11111111b” , $0FH = “00000010b” , *ID[00] $10H =
“10001000b” , ID[01~11] $10H = “00001000b”. Then ID[00] $10H = “10000000b” , ID[01~11] $10H =
“00000000b”. All segment & background will output VPP, but Y121 output “0V”.
8. Host device delay 50ms to display phase2 pattern.
9. ID[00~11] Control register $00H~$0FH = “00000000b” , *ID[00] $10H = “10001000b” , ID[01~11] $10H =
“00001000b”. Then ID[00] $10H = “10000000b” , ID[01~11] $10H = “00000000b”. All EPD pins will output
“0V”.
10. Host device delay 80ms to display phase3 pattern.
11. All EPD pins output “0V” and disable charge pumping if there’s no pattern will be display.
Note：$xxH means address and represent in hexadecimal form.
“xxxxxxxxb” means 8-bits data and represent in binary form.
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
19
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
Condition2：(4 drivers)
2-wires serial mode
perform four drivers
VDD=3V
VPP=30V
LOGICEN = 1
ID[00] Control register
$00~$0FH = 00H
$10H = 08 then to 00H
ID[00~11] Y1~Y122
output 0V
ID[01] Control register
$00~$0FH = 00H
$10H = 08 then to 00H
Host device
Delay 100ms for
pumping stability
ID[00] Control register
$00~$0FH = FFH
$10H = 88 then to 80H
ID[01] Control register
$00~$0FH = FFH
$10H = 08 then to 00H
ID[00] Control register
$00~$0EH = FFH
$0FH = 02H
$10H = 88 then to 80H
Phase2
holding 50ms
ID[00] Control register
$00~$0FH = 00H
$10H = 88 then to 80H
Phase3
holding 80ms
ID[11] Control register
$00~$0FH = 00H
$10H = 08 then to 00H
ID[10] Control register
$00~$0FH = FFH
$10H = 08 then to 00H
ID[11] Control register
$00~$0FH = FFH
$10H = 08 then to 00H
ID[10] Control register
$00~$0EH = FFH
$0FH = 02H
$10H = 08 then to 00H
ID[11] Control register
$00~$0EH = FFH
$0FH = 02H
$10H = 08 then to 00H
ID[10] Control register
$00~$0FH = 00H
$10H = 08 then to 00H
ID[11] Control register
$00~$0FH = 00H
$10H = 08 then to 00H
Initialize setting
ID[00] Control register
$10H = 80, pump enable
Phase1
holding 100ms
ID[10] Control register
$00~$0FH = 00H
$10H = 08 then to 00H
Phase1
ID[01] Control register
$00~$0EH = FFH
$0FH = 02H
$10H = 08 then to 00H
Phase2
ID[01] Control register
$00~$0FH = 00H
$10H = 08 then to 00H
Phase3
Pattern1
YES
Display next pattern?
NO
ID[00] Control register
$00~$0FH = 00H
$10H = 08 then to 00H
New pattern
ID[01] Control register
$00~$0FH = 00H
$10H = 08 then to 00H
ID[10] Control register
$00~$0FH = 00H
$10H = 08 then to 00H
ID[11] Control register
$00~$0FH = 00H
$10H = 08 then to 00H
ID[00~11] All IC keep
in stop mode
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
20
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
7
Operating Ratings
Description
Symbol
Working voltage
Driver High-voltage
capability
Ripple
High-voltage1
High-voltage2
Stop mode current
Pumping enable current
Input high voltage
Input low voltage
2wir speed (SCL&SDA)
2wir load capacitance
SPI speed
SPI load capacitance
VDD
Min
2.2
Value
Typ
3
Vdrv
30
Vrip
Vpp15
Vpp30
Istop
Icpen
VIH
VIL
FI2C
CI2C
FSPI
CSPI
200
15V
30V
0.1
350
0.8*VDD
0.2*VDD
V
32
18V
1M
15
1M
15
Unit
Max
5.5
V
mV
V, (load =15M ohm)
V, (load =15M ohm)
uA
uA
V
V
Hz
pF
Hz
pF
Note：
1. Symbol “2wir” represent SCL & SDA pins
2. Symbol “VPP15” apply to Eink 15V film. For the better life time that customer have to tie each 122 channels
to “0V” then turn off charge pumping.
8
Absolute Maximum Ratings
Symbol
Vdd
Vin
Vout
Topr
Tstg
Description
Supply Voltage
Input Voltage
Output Voltage
Operation Temperature
Storage Temperature
Rating
-0.5 ~ +3.6
-0.5 ~ VDD +0.5
-0.5 ~ VDD +0.5
0 ~ 70
-40 ~ 125
Unit
V
V
V
℃
℃
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
21
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
9
Package Information
9.1 Package Detail Information
LQFP-176L
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
22
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
23
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
TFBGA-145L
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
24
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
TFBGA-145L
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
25
DM130120
15V / 30V Selectable Output & 122 Hi-V Channels Driver IC
10 Ordering Information
Part Number
DM130120W
Pin Count
-
DM130120WB
-
DM130120
146
DM130120B
146
DM130120GP
145
DM130120EP
DM130120C
DM130120P
176
177
177
Package
Wafer (Pb-Free)
Wafer + Gold bump
(Pb-Free)
Dice (Pb-Free)
Dice + Gold bump
(Pb-Free)
TFBGA 145L
(Pb-Free)
LQFP 176L (Pb-Free)
COF (Roll) (Pb-Free)
COF (Tray) (Pb-Free)
Disclaimer
The information appearing in this publication is
believed to be accurate. Integrated circuits sold by
DAVICOM Semiconductor are covered by the
warranty and patent indemnification provisions
stipulated in the terms of sale only. DAVICOM makes
no warranty, express, statutory, implied or by
description regarding the information in this publication
or regarding the information in this publication or
regarding the freedom of the described chip(s) from
patent infringement. FURTHER, DAVICOM MAKES
NO WARRANTY OF MERCHANTABILITY OR
FITNESS FOR ANY PURPOSE. DAVICOM reserves
the right to halt production or alter the specifications
and prices at any time without notice. Accordingly, the
reader is cautioned to verify that the data sheets and
other information in this publication are current before
placing orders. Products described herein are
intended for use in normal commercial applications.
Applications involving unusual environmental or
reliability requirements, e.g. military equipment or
medical life support equipment, are specifically not
recommended without additional processing by
DAVICOM for such applications.
Please note that application circuits illustrated in
this document are for reference purposes only.
DAVICOM’s terms and conditions printed on the
order acknowledgment govern all sales by
DAVICOM. DAVICOM will not be bound by any
terms inconsistent with these unless DAVICOM
agrees otherwise in writing. Acceptance of the
buyer’s orders shall be based on these terms.
Company Overview
DAVICOM Semiconductor Inc. develops and
manufactures integrated circuits for integration
into data communication products. Our mission
is to design and produce IC products that are the
industry’s best value for Data, Audio, Video, and
Internet/Intranet applications. To achieve this
goal, we have built an organization that is able to
develop chipsets in response to the evolving
technology requirements of our customers while
still delivering products that meet their cost
requirements.
Products
We offer only products that satisfy high
performance requirements and which are
compatible with major hardware and software
standards. Our currently available and soon to
be released products are based on our
proprietary designs and deliver high quality, high
performance chipsets that comply with modem
communication
standards
and
Ethernet
networking
standards.
For
customized
products, please contact to Davicom’s sales
Contact Windows
For additional information about DAVICOM products, contact the Sales department at:
Headquarters
Hsin-chu Office:
No.6, Li-Hsin 6th Rd.,
Hsinchu Science Park,
Hsin-chu City 300, Taiwan, R.O.C.
TEL: +886-3-5798797
FAX: +886-3-5646929
MAIL: [email protected]
HTTP: http://www.davicom.com.tw
WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near
the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and function.
Preliminary
Doc No: DM130120-11-MCO-DS-P01
July 11, 2016
26