Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LM48100Q-Q1 SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 LM48100Q-Q1 Boomer™ Mono, 1.3-W Audio Power Amplifier With Output Fault Detection and Volume Control 1 Features • • • • • • • • • • 1 Operating from a single 5-V supply, the LM48100QQ1 delivers 1.3 W of continuous output power to an 8 Ω load with < 1% THD+N. Flexible power supply requirements allow operation from 3 V to 5.5 V. High power supply rejection ratio (PSRR), 74 dB at 1 kHz, allows the device to operate in noisy environments without additional power supply conditioning. Output Fault Detection I2C Volume and Mode Control Input Mixer and Multiplexer High PSRR Individual 32-Step Volume Control Short Circuit and Thermal Protection Advanced Click-and-Pop Suppression Low-Power Shutdown Mode Available in 14-Pin HTSSOP Package Key Specifications: – Output Power at VDD = 5 V, RL = 8 Ω, THD+N ≤ 1% 1.3 W (Typical) – Quiescent Power Supply Current at 5 V, 6 mA (Typical) – PSRR at 1 kHz 74 dB (Typical) – Shutdown current 0.01 μA (Typical) The LM48100Q-Q1 features dual audio inputs that can be mixed/multiplexed to the device output. Each input path has its own independent, 32-step volume control. The mixer, volume control and device mode select are controlled through an I2C compatible interface. An open drain FAULT output indicates when a fault has occurred. Comprehensive output short circuit and thermal overload protection prevent the device from being damaged during a fault condition. A low power shutdown mode reduces supply current consumption to 0.01 µA. Superior click and pop suppression eliminates audible transients on powerup/down and during shutdown. The LM48100Q-Q1 is available in an 14-pin HTSSOP PowerPAD™ IC package. 2 Applications • • • Automotive Instrument Clusters Hands-Free Car Kits Medical Device Information(1) PART NUMBER LM48100Q-Q1 3 Description PACKAGE HTSSOP (14) BODY SIZE (NOM) 5.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. The LM48100Q-Q1 is a single supply, mono, bridgetied load amplifier with I2C volume control, ideal for automotive applications. A comprehensive output fault detection system senses the load conditions, protecting the device during short circuit events, as well as detecting open circuit conditions. Typical Audio Amplifier Application Circuit 3.0V to 5.5V CB 0.1 PF CB 1 PF PVDD VDD CIN1 0.1 PF IN1 VOLUME CONTROL -80 dB TO +18 dB OUTA BIAS CBIAS BIAS MIXER/MULITPLEXER +6 dB 2.2 PF CIN2 OUTB 0.1 PF IN2 VOLUME CONTROL -80 dB TO +18 dB +1.8V to +5.5V VDD CB 0.1 PF RPU 2 I CVDD 1.5 k: SDA FAULT DETECTION 2 I C CONTROL SCL FAULT ADR GND PGND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM48100Q-Q1 SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 1 1 1 2 3 4 Absolute Maximum Ratings ...................................... 4 ESD Ratings.............................................................. 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 4 Electrical Characteristics for VDD = 5 V .................... 5 Electrical Characteristics for VDD = 5 V at Extended Temperature Limits .................................................... 5 6.7 Electrical Characteristics for VDD = 3.6 V ................. 6 6.8 Electrical Characteristics for VDD = 3.6 V at Extended Temperature Limits .................................................... 7 6.9 I2C Interface Characteristics for VDD = 5 V, 2.2 V ≤ I2C VDD ≤ 5.5 V .......................................................... 8 6.10 I2C Interface Characteristics for VDD = 5 V, 1.8 V ≤ I2C VDD ≤ 2.2 V .......................................................... 8 6.11 Typical Characteristics ............................................ 9 7 Detailed Description ............................................ 11 7.1 7.2 7.3 7.4 7.5 7.6 8 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... Register Maps ......................................................... 11 11 12 15 16 17 Application and Implementation ........................ 18 8.1 Application Information............................................ 18 8.2 Typical Application .................................................. 18 9 Power Supply Recommendations...................... 20 10 Layout................................................................... 20 10.1 Layout Guidelines ................................................. 20 10.2 Layout Example .................................................... 21 11 Device and Documentation Support ................. 22 11.1 11.2 11.3 11.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 22 22 22 22 12 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION 10/14/08 1.0 Initial release. 10/20/08 1.01 Text edits. 11/07/08 1.02 Added a column (Limits) in the Electrical tables. 11/12/08 1.03 Text edits. 03/21/2013 D 11/2015 E NOTES Changed layout of the National Data Sheet to TI format Added Pin Configuration and Functions section, ESD Ratings table, Feature Descriptionsection, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layoutsection, Device and Documentation Supportsection, and Mechanical, Packaging, and Orderable Information section Removed LM48100Q-Q1TL Demo board Bill of Materials table. 2 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: LM48100Q-Q1 LM48100Q-Q1 www.ti.com SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 5 Pin Configuration and Functions PWP Package 14-Pin HTSSOP with PowerPAD Top View FAULT 1 14 VDD SCL 2 13 BIAS SDA 3 12 IN1 I CVDD 4 11 IN2 GND 5 10 PVDD ADR 6 9 OUTB OUTA 7 8 PGND 2 Pin Functions PIN I/O DESCRIPTION NO. NAME 1 FAULT O Open-Drain output fault flag. FAULT = 0 indicates that a fault condition has occurred. 2 SCL I I2C Clock Input SDA I/O I2C Serial Data Input 4 2 I CVDD — I2C Interface Power Supply 5 GND — Ground 6 ADR I I2C Address Bit. Connect to I2CVDD to set address bit, B1 = 1. Connect to GND to set address bit B1 = 0 7 OUTA O Non-Inverting Audio Output 8 PGND — Power Ground 9 OUTB O Inverting Audio Output 10 PVDD — Output Amplifier Power Supply 11 IN2 I Audio Input 2 3 12 IN1 I Audio Input 1 13 BIAS — Bias Bypass 14 VDD — Power Supply — Exposed Pad — Exposed paddle. Connect to GND. Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: LM48100Q-Q1 3 LM48100Q-Q1 SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) (3) See MIN MAX UNIT 6 V VDD + 0.3 °C Supply voltage, continuous −0.3 Input voltage Power dissipation (4) Internally Limited Junction temperature Lead temperature (soldering 4 sec) (5) −65 Storage temperature (1) (2) (3) (4) (5) 150 °C 260 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The Electrical Characteristics tables found in Specifications list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Test Conditions, Notes, or both. Typical specifications are estimations only and are not ensured. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. θJA measured with a 4 layer JEDEC board. For detailed information on soldering plastic HTSSOP and LLP packages go to the TI Packaging site, ti.com/packaging. 6.2 ESD Ratings VALUE V(ESD) (1) Human-body model (HBM), per AEC Q100-002 Electrostatic discharge (1) UNIT 2500 Charged-device model (CDM), per AEC Q100-011 V 300 AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions Temperature TMIN ≤ TA ≤ TMAX Supply voltage VDDand PVDD I2C Supply voltage I2CVDD MIN MAX UNIT −40 105 °C 3 5.5 V 1.8 5.5 V I2CVDD VDD V 6.4 Thermal Information LM48100Q-Q1 THERMAL METRIC (1) PWP (HTSSOP) UNIT 14 PINS RθJA Junction-to-ambient thermal resistance 37.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 5.2 °C/W RθJB Junction-to-board thermal resistance — °C/W ψJT Junction-to-top characterization parameter — °C/W ψJB Junction-to-board characterization parameter — °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: LM48100Q-Q1 LM48100Q-Q1 www.ti.com SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 6.5 Electrical Characteristics for VDD = 5 V Programmable Gain = 0 dB, RL = 8 Ω, f = 1 kHz, unless otherwise specified. Limits apply for TA = 25°C, unless otherwise specified. PARAMETER MIN (1) TYP (2) MAX RL = 8 Ω 4.4 9 RL = ∞ 4.2 6 14.5 TEST CONDITIONS UNIT IDD Quiescent Power Supply Current VIN = 0 V, Both channels active IDD Diagnostic Mode Quiescent Power Supply Current Diagnostic Mode Enabled, RL = ∞ 12.5 ISD Shutdown Current Shutdown Enabled 0.01 1 µA VOS Differential Output Offset Voltage VIN = 0 V, RL = 8 Ω 8.8 50 mV TWU Wake-Up Time Time from shutdown to audio available ms AV Gain Mute Mute Attenuation 11.6 50 Minimum Gain Setting –55 –54 –53 Maximum Gain Setting 17 18 19 –80 –77 11.5 12.5 13.5 98 110 120 AV = 18 dB RIN Input Resistance PO Output Power RL = 8 Ω, f = 1 kHz THD+N Total Harmonic Distortion + Noise PO = 850 mW, f = 1 kHz, RL = 8 Ω AV = –54 dB THD+N = 10% THD+N = 1% 1.6 1.05 mA mA dB dB kΩ W 1.3 0.04% f = 217 Hz 66 79 PSRR Power Supply Rejection Ratio VRIPPLE = 200 mVP-P Sine, Inputs AC GND, CIN_= 1 μF, Input Referred, CBIAS = 2.2 μF SNR Signal-to-Noise-Ratio POUT = 450 mW, f = 1 kHz ∈OS Output Noise AV = 0 dB, A-weighted Filter IOUT(FAULT) FAULT Output Current FAULT = 0, VOUT(FAULT)= 0.4 V RFAULT Output to Supply Short Circuit Detection Threshold Short between either OUTA to VDD or GND, or OUTB to VDD or GND Short Circuit RFAULT Output to Supply Short Circuit Detection Threshold Short between both OUTA and OUTB to VDD or GND Short Circuit ROPEN Open Circuit Detection Threshold Open circuit between OUTA and OUTB 100 200 Ω RSHT Output to Output Short Circuit Detection Threshold Short circuit between OUTA and OUTB 2 6 Ω ISHTCKT Short Circuit Current Limit 1.47 TSD Thermal Shutdown Threshold 170 °C tDIAG Diagnostic Time 58 ms (1) (2) f = 1 kHz dB 74 104 dB 12 μV 3 mA 3 Open Circuit 7.5 6 Open Circuit 15 kΩ kΩ 1.67 A Datasheet min/max specification limits are specified by test or statistical analysis. Typical Values are given for TA = 25°C. 6.6 Electrical Characteristics for VDD = 5 V at Extended Temperature Limits Programmable Gain = 0 dB, RL = 8 Ω, f = 1 kHz, unless otherwise specified. Limits apply for TA = –40°C to 105°C, unless otherwise specified. PARAMETER MIN (1) TYP (2) MAX RL = 8 Ω 4.4 10.8 RL = ∞ 4.2 7.9 TEST CONDITIONS IDD Quiescent Power Supply Current VIN = 0 V, Both channels active IDD Diagnostic Mode Quiescent Power Supply Current Diagnostic Mode Enabled, RL = ∞ 12.5 ISD Shutdown Current Shutdown Enabled 0.01 VOS Differential Output Offset Voltage VIN = 0 V, RL = 8 Ω 8.8 TWU Wake-Up Time Time from shutdown to audio available AV Gain Mute Mute Attenuation (1) (2) UNIT mA mA µA 75 11.6 mV ms Minimum Gain Setting –56 –54 –52 Maximum Gain Setting 17 18 19 –80 –74 dB dB Datasheet min/max specification limits are specified by test or statistical analysis. Typical Values are given for TA = 25°C. Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: LM48100Q-Q1 5 LM48100Q-Q1 SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 www.ti.com Electrical Characteristics for VDD = 5 V at Extended Temperature Limits (continued) Programmable Gain = 0 dB, RL = 8 Ω, f = 1 kHz, unless otherwise specified. Limits apply for TA = –40°C to 105°C, unless otherwise specified. PARAMETER MIN (1) TEST CONDITIONS AV = 18 dB TYP (2) MAX UNIT 12.5 RIN Input Resistance PO Output Power RL = 8 Ω, f = 1 kHz THD+N Total Harmonic Distortion + Noise PO = 850 mW, f = 1 kHz, RL = 8 Ω AV = –54 dB 89 THD+N = 10% THD+N = 1% 110 kΩ 130 1.6 0.96 W 1.3 0.04% f = 217 Hz 63 79 PSRR Power Supply Rejection Ratio VRIPPLE = 200 mVP-P Sine, Inputs AC GND, CIN_= 1 μF, Input Referred, CBIAS = 2.2 μF SNR Signal-to-Noise-Ratio POUT = 450 mW, f = 1 kHz ∈OS Output Noise AV = 0 dB, A-weighted Filter IOUT(FAULT) FAULT Output Current FAULT = 0, VOUT(FAULT)= 0.4 V RFAULT Output to Supply Short Circuit Detection Threshold Short between either OUTA to VDD or GND, or OUTB to VDD or GND ISHTCKT Short Circuit Current Limit 1.47 TSD Thermal Shutdown Threshold 170 °C tDIAG Diagnostic Time 58 ms f = 1 kHz dB 74 104 Short Circuit dB 12 μV 3 mA 3 Open Circuit kΩ 7.5 2 A 6.7 Electrical Characteristics for VDD = 3.6 V Programmable Gain = 0 dB, RL = 8 Ω, f = 1 kHz, unless otherwise specified. Limits apply for TA = 25°C, unless otherwise specified. PARAMETER MIN (1) TYP (2) MAX RL = 8 Ω 3.8 8.5 RL = ∞ 3.6 5 14.5 TEST CONDITIONS UNIT IDD Quiescent Power Supply Current VIN = 0 V, Both channels active IDD Diagnostic Mode Quiescent Power Supply Current Diagnostic Mode Enabled, RL = ∞ 11.7 ISD Shutdown Current Shutdown Enabled 0.01 1 µA VOS Differential Output Offset Voltage VIN = 0 V, RL = 8 Ω 8.8 50 mV TWU Wake-Up Time Time from shutdown to audio available ms AV Gain Mute Mute Attenuation 11.5 50 Minimum Gain Setting –55 –54 –53 Maximum Gain Setting 17 18 19 –79 –77 11.5 12.5 13.5 98 110 120 AV = 18 dB RIN Input Resistance PO Output Power RL = 8 Ω, f = 1 kHz THD+N Total Harmonic Distortion + Noise PO = 400 mW, f = 1 kHz, RL = 8 Ω AV = –54 dB THD+N = 10% THD+N = 1% 820 480 mA mA dB dB kΩ mW 660 0.04% f = 217 Hz 66 78 PSRR Power Supply Rejection Ratio VRIPPLE = 200 mVP-P Sine, Inputs AC GND, CIN_= 1 μF, Input Referred, CBIAS = 2.2 μF SNR Signal-to-Noise-Ratio POUT = 780 mW, f = 1 kHz 106 ∈OS Output Noise AV = 0 dB, A-weighted Filter 12.5 μV IOUT(FAULT) FAULT Output Current FAULT = 0, VOUT(FAULT)= 0.4 V 3 mA RFAULT Output to Supply Short Circuit Detection Threshold Short between either OUTA to VDD or GND, or OUTB to VDD or GND Short Circuit RFAULT Output to Supply Short Circuit Detection Threshold Short between both OUTA and OUTB to VDD or GND Short Circuit ROPEN Open Circuit Detection Threshold Open circuit between OUTA and OUTB 100 200 Ω RSHT Output to Output Short Circuit Detection Threshold Short circuit between OUTA and OUTB 2 6 Ω ISHTCKT Short Circuit Current Limit (1) (2) 6 f = 1 kHz dB 75 dB 3 Open Circuit 7.5 6 Open Circuit 15 1.43 kΩ kΩ A Datasheet min/max specification limits are specified by test or statistical analysis. Typical Values are given for TA = 25°C. Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: LM48100Q-Q1 LM48100Q-Q1 www.ti.com SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 Electrical Characteristics for VDD = 3.6 V (continued) Programmable Gain = 0 dB, RL = 8 Ω, f = 1 kHz, unless otherwise specified. Limits apply for TA = 25°C, unless otherwise specified. PARAMETER TSD Thermal Shutdown Threshold tDIAG Diagnostic Time MIN (1) TEST CONDITIONS TYP (2) MAX UNIT 170 °C 63 ms 6.8 Electrical Characteristics for VDD = 3.6 V at Extended Temperature Limits Programmable Gain = 0 dB, RL = 8 Ω, f = 1 kHz, unless otherwise specified. Limits apply for TA = –40°C to 105°C, unless otherwise specified. PARAMETER MIN (1) TYP (2) MAX RL = 8 Ω 3.8 10.8 RL = ∞ 3.6 7 TEST CONDITIONS IDD Quiescent Power Supply Current VIN = 0 V, Both channels active IDD Diagnostic Mode Quiescent Power Supply Current Diagnostic Mode Enabled, RL = ∞ 11.7 ISD Shutdown Current Shutdown Enabled 0.01 VOS Differential Output Offset Voltage VIN = 0 V, RL = 8 Ω 8.8 TWU Wake-Up Time Time from shutdown to audio available 11.5 Minimum Gain Setting –54 Maximum Gain Setting 18 AV Gain Mute Mute Attenuation mA mA µA 76 mV ms dB –79 AV = 18 dB UNIT dB 12.5 RIN Input Resistance PO Output Power RL = 8 Ω, f = 1 kHz THD+N Total Harmonic Distortion + Noise PO = 400 mW, f = 1 kHz, RL = 8 Ω PSRR Power Supply Rejection Ratio VRIPPLE = 200 mVP-P Sine, Inputs AC GND, CIN_= 1 μF, Input Referred, CBIAS = 2.2 μF SNR Signal-to-Noise-Ratio POUT = 780 mW, f = 1 kHz 106 ∈OS Output Noise AV = 0 dB, A-weighted Filter 12.5 μV IOUT(FAULT) FAULT Output Current FAULT = 0, VOUT(FAULT)= 0.4 V 3 mA ISHTCKT Short Circuit Current Limit 1.43 A TSD Thermal Shutdown Threshold 170 °C tDIAG Diagnostic Time 63 ms (1) (2) AV = –54 dB 89 110 THD+N = 10% 820 THD+N = 1% 660 135 kΩ mW 0.04% f = 217 Hz f = 1 kHz 60 78 75 dB dB Datasheet min/max specification limits are specified by test or statistical analysis. Typical Values are given for TA = 25°C. Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: LM48100Q-Q1 7 LM48100Q-Q1 SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 www.ti.com 6.9 I2C Interface Characteristics for VDD = 5 V, 2.2 V ≤ I2C VDD ≤ 5.5 V AV = 0 dB, RL = 8 Ω, f = 1 kHz, unless otherwise specified. Limits apply for TA = 25 °C, unless otherwise specified. PARAMETER TEST CONDITIONS MIN (1) MAX UNIT t1 SCL Period 2.5 µs t2 SDA Setup Time 100 ns t3 SDA Stable Time 0 ns t4 Start Condition Time 100 ns t5 Stop Condition Time 100 ns t6 SDA Data Hold Time 100 ns VIH Logic High Input Threshold VIL (1) 0.7 x I2CVDD V 2 Logic Low Input Threshold 0.3 x I CVDD V Datasheet min/max specification limits are specified by test or statistical analysis. 6.10 I2C Interface Characteristics for VDD = 5 V, 1.8 V ≤ I2C VDD ≤ 2.2 V AV = 0 dB, RL = 8 Ω, f = 1 kHz, unless otherwise specified. Limits apply for TA = 25 °C, unless otherwise specified. PARAMETER TEST CONDITIONS MIN (1) MAX UNIT t1 SCL Period 2.5 µs t2 SDA Setup Time 250 ns t3 SDA Stable Time 0 ns t4 Start Condition Time 250 ns t5 Stop Condition Time 250 ns t6 SDA Data Hold Time 250 ns VIH Logic High Input Threshold 0.7 x I2CVDD V VIL Logic Low Input Threshold (1) 8 0.3 x I2CVDD V Datasheet min/max specification limits are specified by test or statistical analysis. Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: LM48100Q-Q1 LM48100Q-Q1 www.ti.com SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 100 100 10 10 THD+N (%) THD+N (%) 6.11 Typical Characteristics 1 0.1 0.01 1 0.1 0.01 0.001 10 100 1000 10000 0.001 10 100000 100 FREQUENCY (Hz) VDD = 3.6 V RL = 4 Ω POUT = 600 mW VDD = 3.6 V Figure 1. THD+N vs Frequency 100000 RL = 8 Ω POUT = 400 mW Figure 2. THD+N vs Frequency 10 THD+N (%) 10 THD+N (%) 10000 100 100 1 0.1 0.01 1 0.1 0.01 0.001 10 100 1000 10000 0.001 10 100000 100 FREQUENCY (Hz) VDD = 5 V 1000 10000 100000 FREQUENCY (Hz) RL = 4 Ω POUT = 1.2 W VDD = 5 V RL = 8 Ω POUT = 850 mW Figure 4. THD+N vs Frequency Figure 3. THD+N vs Frequency 100 100 VDD = 5V VDD = 5V 10 THD+N (%) 10 THD+N (%) 1000 FREQUENCY (Hz) VDD = 3.6V 1 0.1 VDD = 3.6V 1 0.1 0.01 0.001 0.01 0.1 1 10 0.01 0.001 OUTPUT POWER (W) f = 1 kHz 0.01 0.1 1 10 OUTPUT POWER (W) RL = 4 Ω f = 1 kHz Figure 5. THD+N vs Output Power RL = 8 Ω Figure 6. THD+N vs Output Power Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: LM48100Q-Q1 9 LM48100Q-Q1 SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 www.ti.com Typical Characteristics (continued) 800 1400 VDD = 5V VDD = 5V 700 POWER DISSIPATION (mW) POWER DISSIPATION (mW) 1200 1000 VDD = 3.6V 800 600 400 200 0 600 500 VDD = 3.6V 400 300 200 100 0 0 500 1000 1500 2000 2500 0 250 1000 1250 1500 RL = 8 Ω Figure 8. Power Dissipation vs Output Power Figure 7. Power Dissipation vs Output Power 3.5 2 3 THD+N = 10% THD+N = 10% OUTPUT POWER (W) OUTPUT POWER (W) 750 f = 1 kHz RL = 4 Ω f = 1 kHz 500 OUTPUT POWER (mW) OUTPUT POWER (mW) 2.5 2 1.5 1 THD+N = 1% 1.5 1 THD+N = 1% 0.5 0.5 0 3 3.5 4 4.5 5 0 3 5.5 3.5 f = 1 kHz 4 4.5 5 5.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) RL = 4 Ω f = 1 kHz Figure 9. Output Power vs Supply Voltage RL = 8 Ω Figure 10. Output Power vs Supply Voltage 0 -20 PSRR (dB) -40 -60 -80 -100 -120 10 100 1000 10000 100000 FREQUENCY (Hz) VDD = 3.6 V VRIPPLE = 200 mVP-P RL = 8 Ω Figure 11. PSRR vs Frequency 10 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: LM48100Q-Q1 LM48100Q-Q1 www.ti.com SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 7 Detailed Description 7.1 Overview The LM48100Q-Q1 integrates a comprehensive output fault detection system, which can sense the load conditions, protecting the device during short circuit events and detecting open circuit conditions. High power supply rejection ratio allows the device to operate in noisy environments without additional power supply conditioning. Dual audio inputs can be mixed or multiplexed to the device output. Each input path has its own independent, 32-step volume control. The mixer, volume control and device mode select are controlled through an I2C compatible interface. An open drain FAULT output indicates when a fault has occurred. Comprehensive output short circuit and thermal overload protection prevent the device from damage during fault conditions. Superior click and pop suppression eliminates audible transients on power-up, power-down, and during shutdown. 7.2 Functional Block Diagram 3.0V to 5.5V CB 0.1 PF CB 1 PF PVDD VDD CIN1 0.1 PF IN1 VOLUME CONTROL -80 dB TO +18 dB OUTA BIAS CBIAS BIAS MIXER/MULITPLEXER +6 dB 2.2 PF CIN2 OUTB 0.1 PF IN2 VOLUME CONTROL -80 dB TO +18 dB +1.8V to +5.5V VDD CB 0.1 PF RPU 2 I CVDD 1.5 k: SDA FAULT DETECTION 2 I C CONTROL SCL FAULT ADR GND PGND Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: LM48100Q-Q1 11 LM48100Q-Q1 SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 www.ti.com 7.3 Feature Description 7.3.1 Diagnostic Control The LM48100Q-Q1 output fault diagnostics are controlled through the I2C interface. When power is initially applied to the device, the LM48100Q-Q1 initializes, performing the full diagnostic sequence; output short to VDD and GND, outputs shorted together, and no load condition, is performed. The device remains in shutdown while the initial diagnostic check is performed. Any I2C commands written to the device during this time are stored and implemented once the diagnostic check is complete. The initial diagnostic sequence can be terminated by setting DG_RESET = 1. The Diagnostic Control register, register 1, controls the LM48100Q-Q1 diagnostic process. Bit B4, DG_EN, enables the output fault detection. Set DG_EN = 1 to enable the output diagnostic test sequence. The LM48100Q-Q1 treats the DG_EN bit as rising-edge-sensitive; once DG_EN = 1 is clocked into the device, the diagnostic test is performed. If the LM48100Q-Q1 is in one-shot mode, once the test sequence is performed, the DG_EN bit is ignored and the test sequence will not be run again. Cycle DG_EN from high-to-low-to-high to reenable the one-shot diagnostic test sequence. In continuous diagnostic mode, the test sequence is repeated until either a fault condition occurs, DG_RESET is cycled, or the device is taken out of continuous diagnostic mode. Set DG_CONT = 1 before setting DG_EN = 1 to initiate a continuous diagnostic. Set DG-CONT = 0 to disable continuous diagnostic mode. When the device is active and DG_EN = 0, the LM48100Q-Q1 does not perform the output short, or no load diagnostics, however, the thermal overload and output over current protection circuitry remains active, and disables the device should a thermal or over-current fault occur. The initial diagnostic operation when power is applied to the device occurs regardless of the state of DG_EN. The LM48100Q-Q1 output fault detection can be set to either continuous mode where the output diagnostic occurs every 60ms, or a one-shot mode. Set bit B3 (DG_CONT) to 1 for continuous mode, set B3 = 0 for one-shot mode. Bit B2, DG_RESET, restores the LM48100Q-Q1 to normal operation after an output fault is detected. Toggle DG_RESET to re-enable the device outputs and set FAULT high. Table 1. Diagnostic Control Register BIT NAME VALUE DESCRIPTION B0 RESERVED 0 Unused 0 Fixed output current limit 1 Supply dependent output current limit B1 ILIMIT B2 DG _RESET 0 Normal operation. FAULT remains low and device is disabled once a fault occurs. 1 Reset FAULT output. Device returns to pre-fault operation. DG _CONT 0 One shot diagnostic 1 Continuous diagnostic 0 Disable diagnostic 1 Enable diagnostic B3 B4 DG_EN 7.3.2 Fault Detection Control Register The LM48100Q-Q1 output fault tests are individually controlled through the Fault Detection Control register, register 2. Setting any of the bits in the Fault Detection Control register to 1 causes the FAULT circuitry to ignore the associated test. For example, if B2 (RAIL_SHT) = 1 and the output is shorted to VDD, the FAULT output remains high. Although the FAULT circuitry ignores the selected test, the LM48100Q-Q1 protection circuitry remains active, and disables the device. This feature is useful for diagnosing which fault caused a FAULT condition. If DG_EN = 1, and a diagnostic sequence is initiated, all the tests are performed regardless of their state in the Fault Detection Control register. If DG_EN = 0, the RAIL_SHT, OUTPUT_OPEN and OUTPUT_SHT tests are not performed, however, the thermal overload and output over-current detection circuitry remains active. 12 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: LM48100Q-Q1 LM48100Q-Q1 www.ti.com SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 Table 2. Fault Detection Control Register BIT NAME B0 VALUE OUTPUT_SHT B1 OUTPUT_OPEN RAIL _SHT B2 B3 OVF B4 TSD DESCRIPTION 0 Normal operation 1 Ignore output short circuit fault (outputs shorted together) 0 Normal operation 1 Ignore output short circuit fault 0 Normal operation 1 Ignore output short to VDD or GND fault 0 Normal operation 1 Ignore output over-current fault 0 Normal operation 1 Ignore thermal overload fault 7.3.3 General Amplifier Function 7.3.3.1 Bridge Configuration Explained The LM48100Q-Q1 is designed to drive a load differentially, a configuration commonly referred to as a bridgetied load (BTL). The BTL configuration differs from the single-ended configuration, where one side of the load is connected to ground. A BTL amplifier offers advantages over a single-ended device. By driving the load differentially, the output voltage is doubled, compared to a single-ended amplifier under similar conditions. This doubling of the output voltage leads to a quadrupling of the output power. For example, the theoretical maximum output power for a single-ended amplifier driving 8 Ω and operating from a 5 V supply is 158 mW, while the theoretical maximum output power for a BTL amplifier operating under the same conditions is 633 mW. Since the amplifier outputs are both biased about VDD/2, there is no net DC voltage across the load, eliminating the DC blocking capacitors required by single-ended, single-supply amplifiers. 7.3.3.2 Input Mixer/Multiplexer The LM48100Q-Q1 features an input mixer/multiplexer controlled through the I2C interface. The mixer/multiplexer allows either input, or the combination of both inputs to appear at the device output. Bits B2 (INPUT_1) and B3 (INPUT_2) of the Mode Control Register select the individual input channels. Set INPUT_1 = 1 to select the audio signal on IN1. Set INPUT_2 = 1 to select the audio signal on IN2. Setting both INPUT_1 and INPUT_2 = 1 mixes VIN1 and VIN2, and the LM48100Q-Q1 outputs the result as a mono signal (Table 3). Table 3. Input Multiplexer Control INPUT_1 INPUT_2 LM48100Q-Q1 OUTPUT 0 0 MUTE. No input selected 1 0 IN1 ONLY 0 1 IN2 ONLY 1 1 IN1 + IN2 7.3.4 Output Fault Detection 7.3.4.1 Output Short to Supplies (VDD or GND) With a standard speaker load (6 Ω to 100 Ω) connected between OUTA and OUTB, the LM48100Q-Q1 can detect a short between the outputs and either VDD or GND. A short is detected if the impedance between either OUTA or OUTB and VDD or GND is less than 3 kΩ. A short is also detected if the impedance between BOTH OUTA and OUTB and either VDD or GND is less than 6 kΩ. Under either of these conditions, the amplifier outputs are disabled and FAULT is driven low. No short is detected if the impedance between either output and VDD or GND is greater than 7.5 kΩ. Likewise, no short is detected if the impedance between BOTH outputs and VDD or GND is greater than 15 kΩ. Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: LM48100Q-Q1 13 LM48100Q-Q1 SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 www.ti.com 7.3.4.2 Output Short Circuit and Open Circuit Detection The LM48100Q-Q1 can detect whether the amplifier outputs have been shorted together or, an output open circuit condition has occurred. An output short circuit is detected if the impedance between OUTA and OUTB is less than 2 Ω. An open circuit is detected if the impedance between OUTA and OUTB is greater than 200 Ω. Under either of these conditions, the amplifier outputs are disabled and FAULT is driven low. The device remains in normal operation if the impedance between OUTA and OUTB is in the range of 6 Ω to 100 Ω. The output open circuit test is only performed during the initial diagnostic sequence during power up, or when DG_ENABLE is set to 1. 7.3.4.3 Output Over-Current Detection The LM48100Q-Q1 has two over current detection modes, a fixed current limit, and a supply dependent current limit. Bit B1 (ILIMIT) of the Diagnostic Control Register selects the over-current detection mode. Set ILIMIT = 0 to select a fixed current limit of 1.47 A (typ). Set ILIMIT = 1 to select the supply dependent current limit mode. In supply dependent mode, the current limit is determined by Equation 1: ISHTCKT = 0.264 x VDD (A) (1) If the output current exceeds the current limit, the device outputs are disabled and FAULT is driven low. The output over-current detection circuitry remains active when the diagnostics have been disabled (DG_EN = 0). 7.3.4.4 Thermal Overload Detection The LM48100Q-Q1 has thermal overload threshold of 170 °C (typ). If the die temperature exceeds 170 °C, the outputs are disabled and FAULT is driven low. The thermal overload detection circuitry remains active when the diagnostics have been disabled (DG_EN = 0). 7.3.5 Open FAULT Output The LM48100Q-Q1 features an open drain, fault indication output, FAULT , that asserts when a fault condition is detected by the device. FAULT goes low when either an output short, output open, over current, or thermal overload fault is detected, and the diagnostic test is not ignored, see Fault Detection Control Register section. FAULT remains low even after the fault condition has been cleared and the diagnostic tests are repeated. Toggle DG_RESET to clear FAULT. Connect a 1.5-kΩ or higher pullup resistor between FAULT and VDD. 7.3.6 Volume Control Table 4. Volume Control VOLUME STEP VOL4 VOL3 VOL2 VOL1 VOL0 GAIN (dB) 1 0 0 0 0 0 –80 2 0 0 0 0 1 –54 3 0 0 0 1 0 –40.5 4 0 0 0 1 1 –34.5 5 0 0 1 0 0 –30 6 0 0 1 0 1 –27 7 0 0 1 1 0 –24 8 0 0 1 1 1 –21 –18 14 9 0 1 0 0 0 10 0 1 0 0 1 –15 11 0 1 0 1 0 –13.5 12 0 1 0 1 1 –12 13 0 1 1 0 0 –10.5 14 0 1 1 0 1 –9 15 0 1 1 1 0 –7.5 16 0 1 1 1 1 –6 17 1 0 0 0 0 –4.5 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: LM48100Q-Q1 LM48100Q-Q1 www.ti.com SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 Table 4. Volume Control (continued) VOLUME STEP VOL4 VOL3 VOL2 VOL1 VOL0 GAIN (dB) 18 1 0 0 0 1 –3 19 1 0 0 1 0 –1.5 20 1 0 0 1 1 0 21 1 0 1 0 0 1.5 22 1 0 1 0 1 3 23 1 0 1 1 0 4.5 24 1 0 1 1 1 6 25 1 1 0 0 0 7.5 26 1 1 0 0 1 9 27 1 1 0 1 0 10.5 28 1 1 0 1 1 12 29 1 1 1 0 0 13.5 30 1 1 1 0 1 15 31 1 1 1 1 0 16.5 32 1 1 1 1 1 18 7.3.7 Shutdown Function The LM48100Q-Q1 features an I2C selectable low power shutdown mode that disables the device, reducing quiescent current consumption to 0.01 μA. Set bit B4 (POWER_ON) in the Mode Control Register to 0 to disable the device. Set B0 to 1 to enable the device. 7.3.8 Power Dissipation The increase in power delivered by a BTL amplifier leads to a direct increase in internal power dissipation. The maximum power dissipation for a BTL amplifier for a given supply voltage and load is given by Equation 2: PDMAX = 4 x VDD2 / 2π2RL (Watts) (2) The maximum power dissipation of the HTSSOP package is calculated by Equation 3: PDMAX (PKG) = TJMAX – TA / θJA (Watts) where • • • TJMAX is 150 °C TA is the ambient temperature θJA is the thermal resistance specified in the Absolute Maximum Ratings (3) If the power dissipation for a given operating condition exceeds the package maximum, either decrease the ambient temperature, increase air flow, add heat sinking to the device, or increase the load impedance and/or supply voltage. The LM48100Q-Q1 HTSSOP package features an exposed die attach pad (DAP) that can be used to increase the maximum power dissipation of the package, see Exposed DAP Mounting Considerations. The LM48100Q-Q1 features thermal overload protection that disables the amplifier output stage when the die temperature exceeds 170 °C. See the Thermal Overload Detection section. 7.4 Device Functional Modes The LM48100Q-Q1 output fault diagnostics support two different modes: one-shot mode and continuous diagnostic mode. 7.4.1 One-Shot Mode If the LM48100Q-Q1 is in one-shot mode, once the test sequence is performed, the DG_EN bit is ignored and the test sequence will not be run again. Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: LM48100Q-Q1 15 LM48100Q-Q1 SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 www.ti.com Device Functional Modes (continued) 7.4.2 Continuous Diagnostic Mode In continuous diagnostic mode, the test sequence is repeated until either a fault condition occurs, DG_RESET is cycled, or the device is taken out of continuous diagnostic mode. 7.5 Programming 7.5.1 Write-Only I2C Compatible Interface The LM48100Q-Q1 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The LM48100Q-Q1 and the master can communicate at clock rates up to 400 kHz. Figure 12 shows the I2C interface timing diagram. Data on the SDA line must be stable during the HIGH period of SCL. The LM48100Q-Q1 is a transmit/receive slave-only device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a START condition and a STOP condition (Figure 13). Each data word, device address and data, transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse (Figure 14). The LM48100Q-Q1 device address is 111110X, where X is determined by ADR (Table 6). ADR = 1 sets the device address to 1111101. ADR = 0 sets the device address to 1111100. 7.5.2 I2C Bus Format The I2C bus format is shown in Figure 14. The START signal, the transition of SDA from HIGH to LOW while SCL is HIGH, is generated, alerting all devices on the bus that a device address is being written to the bus. The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit. R/W = 0 indicates the master is writing to the slave device, RW = 1 indicates the master wants to read data from the slave device. Set R/W = 0; the LM48100Q-Q1 is a WRITE-ONLY device and will not respond the R/W = 1. The data is latched in on the rising edge of the clock. Each address bit must be stable while SCL is HIGH. After the last address bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is generated by the slave device. If the LM48100Q-Q1 receives the correct address, the device pulls the SDA line low, generating an acknowledge bit (ACK). Once the master device registers the ACK bit, the 8-bit register data word is sent. Each data bit should be stable while SCL is HIGH. After the 8-bit register data word is sent, the LM48100Q-Q1 sends another ACK bit. Following the acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go high. t1 SCL t4 t5 SDA Data In t2 SDA Data Out t3 Figure 12. I2C Timing Diagram 16 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: LM48100Q-Q1 LM48100Q-Q1 www.ti.com SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 Programming (continued) SDA SCL S P START condition STOP condition Figure 13. Start and Stop Diagram SCL SDA START MSB DEVICE ADDRESS LSB R/W ACK MSB REGISTER DATA ACK LSB STOP Figure 14. Example Write Sequence Table 5. Device Address B7 B6 B5 B4 B3 B2 B1 B0 R/W ADR = 0 1 1 1 1 1 0 0 0 ADR = 1 1 1 1 1 1 0 1 0 7.6 Register Maps Table 6. I2C Control Registers Register Address Register Name B7 B6 B5 B4 B3 B2 B1 B0 0 MODE CONTROL 0 0 0 POWER_ON INPUT_2 INPUT_1 0 0 1 DIAGNOSTIC CONTROL 0 0 1 DG_EN DG_CONT DG_RESET ILIMIT 0 2 FAULT DETECTION CONTROL 0 1 0 TSD OCF RAIL_SHT OUTPUT _OPEN OUTPUT _SHORT 3 VOLUME CONTROL 1 0 1 1 VOL1_4 VOL1_3 VOL1_2 VOL1_1 VOL1_0 4 VOLUME CONTROL 2 1 0 0 VOL2_4 VOL2_3 VOL2_2 VOL_2 VOL2_0 Table 7. Mode Control Registers BIT NAME VALUE B0, B1 RESERVED 0 Unused B2 INPUT_1 0 IN1 Input unselected 1 IN1 Input selected 0 IN2 Input unselected 1 IN2 Input selected 0 Device Disabled 1 Device Enabled B3 B4 INPUT_2 POWER_ON DESCRIPTION Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: LM48100Q-Q1 17 LM48100Q-Q1 SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LM48100Q-Q1 is a single-supply, mono, bridge-tied load amplifier with I2C volume control, ideal for automotive applications. It integrates a comprehensive output fault detection system, which can sense the load conditions, protecting the device during short circuit events and detecting open circuit conditions. High power supply rejection ratio allows the device to operate in noisy environments without additional power supply conditioning. The LM48100Q-Q1 features dual audio inputs that can mixed or multiplexed to the device output. Each input path has its own independent, 32-step volume control. The mixer, volume control and device mode select are controlled through an I2C compatible interface. The LM48100Q-Q1 device has an I2C selectable low power shutdown mode that disables the device, reducing quiescent current consumption to 0.01μA 8.2 Typical Application U1 VDD VDD 14 10 VDD C3 0.1 PF PVDD 5 8 GND C4 2.2 PF C2 1 PF C1 10 PF + VDD PGND GND 13 BIAS C7 12 9 IN1 OUTA 0.1 PF IN1 OUTA C6 11 7 IN2 0.1 PF IN2 I2CVDD OUTB I2CVDD VDD 1 OUTB JU1 2 6 JU3 ADR 3 4 I2CVDD C5 0.1 PF I2CVDD VDD 2 SCL SCL R3 1.5k I2CVDD 3 SDA R1 5k R2 5k 1 SDA FAULT FAULT J2 LM48100 JU2 SDA SCL 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 MOUNTING SUPPORT Figure 15. LM48100Q-Q1 Demo Board Schematic 18 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: LM48100Q-Q1 LM48100Q-Q1 www.ti.com SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 Typical Application (continued) 8.2.1 Design Requirements For this design example, use the parameters listed in Table 8 as the input parameters. Table 8. Design Parameters DESIGN PARAMETER EXAMPLE VALUES Supply Voltage Range 3 V to 5.5 V I2C Supply Voltage Range 1.8 V to 5.5 V Temperature Range –40 °C to 105 °C Input Voltage Range –0.3 V to VDD = 0.3 V 8.2.2 Detailed Design Procedure 8.2.2.1 Power Supply Bypassing/Filtering Proper power supply bypassing is critical for low noise performance and high PSRR. Place the supply bypass capacitors as close to the device as possible. Place a 1-µF ceramic capacitor from VDD to GND. Additional bulk capacitance may be added as required. 8.2.2.2 Input Capacitor Selection Input capacitors may be required for some applications, or when the audio source is single-ended. Input capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of the audio source and the bias voltage of the LM48100Q-Q1. The input capacitors create a high-pass filter with the input resistors RIN. The –3 dB point of the high-pass filter is found using Equation 4. f = 1 / 2πRINCIN (Hz) where • RIN is given in the Electrical Characteristics tables found in Specifications (4) High pass filtering the audio signal helps protect the speakers. When the LM48100Q-Q1 is using a single-ended source, power supply noise on the ground is seen as an input signal. Setting the high-pass filter point above the power supply noise frequencies, filters out the noise such that it is not amplified and heard on the output. Capacitors with a tolerance of 10% or better are recommended for impedance matching and improved PSRR. 8.2.2.3 Bias Capacitor Selection The LM48100Q-Q1 internally generates a VDD/2 common-mode bias voltage. The BIAS capacitor CBIAS, improves PSRR and THD+N by reducing noise at the BIAS node. Use a 2.2-µF ceramic placed as close to the device as possible. Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: LM48100Q-Q1 19 LM48100Q-Q1 SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 www.ti.com 8.2.3 Application Curve (1) IN1 (2) OUTB (3) OUTA Figure 16. Input and Output Waveforms for a 1kHz Sine Wave 9 Power Supply Recommendations The LM48100Q-Q1 is designed be operate with a power supply between 3.0 V and 5.5 V. Proper power supply bypassing is critical for low noise performance and high PSRR. Place the supply bypass capacitors as close to the device as possible. Place a 1-μF ceramic capacitor from VDD to GND. Additional bulk capacitance may be added as required. 10 Layout 10.1 Layout Guidelines Minimize trace impedance of the power, ground and all output traces for optimum performance. Voltage loss due to trace resistance between the LM48100Q-Q1 and the load results in decreased output power and efficiency. Trace resistance between the power supply and ground has the same effect as a poorly regulated supply, increased ripple and reduced peak output power. Use wide traces for power supply inputs and amplifier outputs to minimize losses due to trace resistance, as well as route heat away from the device. Proper grounding improves audio performance, minimizes crosstalk between channels and prevents digital noise from interfering with the audio signal. Use of power and ground planes is recommended. Place all digital components and route digital signal traces as far as possible from analog components and traces. Do not run digital and analog traces in parallel on the same PCB layer. If digital and analog signal lines must cross either over or under each other, ensure that they cross in a perpendicular fashion. 10.1.1 Exposed DAP Mounting Considerations The LM48100Q-Q1 HTSSOP-EP package features an exposed die-attach (thermal) pad on its backside. The exposed pad provides a direct heat conduction path from the die to the PCB, reducing the thermal resistance of the package. Connect the exposed pad to GND with a large pad and via to a large GND plane on the bottom of the PCB for best heat distribution. 20 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: LM48100Q-Q1 LM48100Q-Q1 www.ti.com SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 10.2 Layout Example Place bypass capacitors close to the device Use wide traces for power supply inputs and amplifier outputs Route digital signal traces far from analog traces Figure 17. Example Board Layout Implementing Layout Guidelines Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: LM48100Q-Q1 21 LM48100Q-Q1 SNAS470E – OCTOBER 2008 – REVISED NOVEMBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.2 Trademarks Boomer, PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: LM48100Q-Q1 PACKAGE OPTION ADDENDUM www.ti.com 2-Apr-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM48100QMH/NOPB ACTIVE HTSSOP PWP 14 94 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 105 L48100Q LM48100QMHE/NOPB ACTIVE HTSSOP PWP 14 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 105 L48100Q LM48100QMHX/NOPB ACTIVE HTSSOP PWP 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 105 L48100Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 2-Apr-2015 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM48100QMHE/NOPB HTSSOP PWP 14 250 178.0 12.4 LM48100QMHX/NOPB HTSSOP PWP 14 2500 330.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.95 5.6 1.6 8.0 12.0 Q1 6.95 5.6 1.6 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM48100QMHE/NOPB HTSSOP PWP LM48100QMHX/NOPB HTSSOP PWP 14 250 210.0 185.0 35.0 14 2500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA PWP0014A MXA14A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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